1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe RC driver for Synopsys DesignWare Core
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
7 * Authors: Joao Pinto <Joao.Pinto@synopsys.com>
10 #include <linux/delay.h>
11 #include <linux/gpio.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/of_device.h>
16 #include <linux/pci.h>
17 #include <linux/platform_device.h>
18 #include <linux/resource.h>
19 #include <linux/signal.h>
20 #include <linux/types.h>
21 #include <linux/regmap.h>
23 #include "pcie-designware.h"
27 struct regmap *regmap;
28 enum dw_pcie_device_mode mode;
31 struct dw_plat_pcie_of_data {
32 enum dw_pcie_device_mode mode;
35 static const struct of_device_id dw_plat_pcie_of_match[];
37 static int dw_plat_pcie_host_init(struct pcie_port *pp)
39 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
42 dw_pcie_wait_for_link(pci);
44 if (IS_ENABLED(CONFIG_PCI_MSI))
50 static void dw_plat_set_num_vectors(struct pcie_port *pp)
52 pp->num_vectors = MAX_MSI_IRQS;
55 static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
56 .host_init = dw_plat_pcie_host_init,
57 .set_num_vectors = dw_plat_set_num_vectors,
60 static int dw_plat_pcie_establish_link(struct dw_pcie *pci)
65 static const struct dw_pcie_ops dw_pcie_ops = {
66 .start_link = dw_plat_pcie_establish_link,
69 static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
71 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
72 struct pci_epc *epc = ep->epc;
75 for (bar = BAR_0; bar <= BAR_5; bar++)
76 dw_pcie_ep_reset_bar(pci, bar);
78 epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
79 epc->features |= EPC_FEATURE_MSIX_AVAILABLE;
82 static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
83 enum pci_epc_irq_type type,
86 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
89 case PCI_EPC_IRQ_LEGACY:
90 return dw_pcie_ep_raise_legacy_irq(ep, func_no);
92 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
93 case PCI_EPC_IRQ_MSIX:
94 return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
96 dev_err(pci->dev, "UNKNOWN IRQ type\n");
102 static struct dw_pcie_ep_ops pcie_ep_ops = {
103 .ep_init = dw_plat_pcie_ep_init,
104 .raise_irq = dw_plat_pcie_ep_raise_irq,
107 static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
108 struct platform_device *pdev)
110 struct dw_pcie *pci = dw_plat_pcie->pci;
111 struct pcie_port *pp = &pci->pp;
112 struct device *dev = &pdev->dev;
115 pp->irq = platform_get_irq(pdev, 1);
119 if (IS_ENABLED(CONFIG_PCI_MSI)) {
120 pp->msi_irq = platform_get_irq(pdev, 0);
125 pp->ops = &dw_plat_pcie_host_ops;
127 ret = dw_pcie_host_init(pp);
129 dev_err(dev, "Failed to initialize host\n");
136 static int dw_plat_add_pcie_ep(struct dw_plat_pcie *dw_plat_pcie,
137 struct platform_device *pdev)
140 struct dw_pcie_ep *ep;
141 struct resource *res;
142 struct device *dev = &pdev->dev;
143 struct dw_pcie *pci = dw_plat_pcie->pci;
146 ep->ops = &pcie_ep_ops;
148 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
149 pci->dbi_base2 = devm_ioremap_resource(dev, res);
150 if (IS_ERR(pci->dbi_base2))
151 return PTR_ERR(pci->dbi_base2);
153 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
157 ep->phys_base = res->start;
158 ep->addr_size = resource_size(res);
160 ret = dw_pcie_ep_init(ep);
162 dev_err(dev, "Failed to initialize endpoint\n");
168 static int dw_plat_pcie_probe(struct platform_device *pdev)
170 struct device *dev = &pdev->dev;
171 struct dw_plat_pcie *dw_plat_pcie;
173 struct resource *res; /* Resource from DT */
175 const struct of_device_id *match;
176 const struct dw_plat_pcie_of_data *data;
177 enum dw_pcie_device_mode mode;
179 match = of_match_device(dw_plat_pcie_of_match, dev);
183 data = (struct dw_plat_pcie_of_data *)match->data;
184 mode = (enum dw_pcie_device_mode)data->mode;
186 dw_plat_pcie = devm_kzalloc(dev, sizeof(*dw_plat_pcie), GFP_KERNEL);
190 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
195 pci->ops = &dw_pcie_ops;
197 dw_plat_pcie->pci = pci;
198 dw_plat_pcie->mode = mode;
200 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
202 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
204 pci->dbi_base = devm_ioremap_resource(dev, res);
205 if (IS_ERR(pci->dbi_base))
206 return PTR_ERR(pci->dbi_base);
208 platform_set_drvdata(pdev, dw_plat_pcie);
210 switch (dw_plat_pcie->mode) {
211 case DW_PCIE_RC_TYPE:
212 if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_HOST))
215 ret = dw_plat_add_pcie_port(dw_plat_pcie, pdev);
219 case DW_PCIE_EP_TYPE:
220 if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP))
223 ret = dw_plat_add_pcie_ep(dw_plat_pcie, pdev);
228 dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode);
234 static const struct dw_plat_pcie_of_data dw_plat_pcie_rc_of_data = {
235 .mode = DW_PCIE_RC_TYPE,
238 static const struct dw_plat_pcie_of_data dw_plat_pcie_ep_of_data = {
239 .mode = DW_PCIE_EP_TYPE,
242 static const struct of_device_id dw_plat_pcie_of_match[] = {
244 .compatible = "snps,dw-pcie",
245 .data = &dw_plat_pcie_rc_of_data,
248 .compatible = "snps,dw-pcie-ep",
249 .data = &dw_plat_pcie_ep_of_data,
254 static struct platform_driver dw_plat_pcie_driver = {
257 .of_match_table = dw_plat_pcie_of_match,
258 .suppress_bind_attrs = true,
260 .probe = dw_plat_pcie_probe,
262 builtin_platform_driver(dw_plat_pcie_driver);