drivers/net/wireless/ralink/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, see <http://www.gnu.org/licenses/>.
  28  */
  29
  30 /*
  31         Module: rt2800lib
  32         Abstract: rt2800 generic device routines.
  33  */
  34
  35 #include <linux/crc-ccitt.h>
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/slab.h>
  39
  40 #include "rt2x00.h"
  41 #include "rt2800lib.h"
  42 #include "rt2800.h"
  43
  44 /*
  45  * Register access.
  46  * All access to the CSR registers will go through the methods
  47  * rt2800_register_read and rt2800_register_write.
  48  * BBP and RF register require indirect register access,
  49  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  50  * These indirect registers work with busy bits,
  51  * and we will try maximal REGISTER_BUSY_COUNT times to access
  52  * the register while taking a REGISTER_BUSY_DELAY us delay
  53  * between each attampt. When the busy bit is still set at that time,
  54  * the access attempt is considered to have failed,
  55  * and we will print an error.
  56  * The _lock versions must be used if you already hold the csr_mutex
  57  */
  58 #define WAIT_FOR_BBP(__dev, __reg) \
  59         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  60 #define WAIT_FOR_RFCSR(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
  64                             (__reg))
  65 #define WAIT_FOR_RF(__dev, __reg) \
  66         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  67 #define WAIT_FOR_MCU(__dev, __reg) \
  68         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  69                             H2M_MAILBOX_CSR_OWNER, (__reg))
  70
  71 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  72 {
  73         /* check for rt2872 on SoC */
  74         if (!rt2x00_is_soc(rt2x00dev) ||
  75             !rt2x00_rt(rt2x00dev, RT2872))
  76                 return false;
  77
  78         /* we know for sure that these rf chipsets are used on rt305x boards */
  79         if (rt2x00_rf(rt2x00dev, RF3020) ||
  80             rt2x00_rf(rt2x00dev, RF3021) ||
  81             rt2x00_rf(rt2x00dev, RF3022))
  82                 return true;
  83
  84         rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
  85         return false;
  86 }
  87
  88 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  89                              const unsigned int word, const u8 value)
  90 {
  91         u32 reg;
  92
  93         mutex_lock(&rt2x00dev->csr_mutex);
  94
  95         /*
  96          * Wait until the BBP becomes available, afterwards we
  97          * can safely write the new data into the register.
  98          */
  99         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 100                 reg = 0;
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 105                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 106
 107                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 108         }
 109
 110         mutex_unlock(&rt2x00dev->csr_mutex);
 111 }
 112
 113 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
 114 {
 115         u32 reg;
 116         u8 value;
 117
 118         mutex_lock(&rt2x00dev->csr_mutex);
 119
 120         /*
 121          * Wait until the BBP becomes available, afterwards we
 122          * can safely write the read request into the register.
 123          * After the data has been written, we wait until hardware
 124          * returns the correct value, if at any time the register
 125          * doesn't become available in time, reg will be 0xffffffff
 126          * which means we return 0xff to the caller.
 127          */
 128         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 129                 reg = 0;
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 133                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 134
 135                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 136
 137                 WAIT_FOR_BBP(rt2x00dev, &reg);
 138         }
 139
 140         value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 141
 142         mutex_unlock(&rt2x00dev->csr_mutex);
 143
 144         return value;
 145 }
 146
 147 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 148                                const unsigned int word, const u8 value)
 149 {
 150         u32 reg;
 151
 152         mutex_lock(&rt2x00dev->csr_mutex);
 153
 154         /*
 155          * Wait until the RFCSR becomes available, afterwards we
 156          * can safely write the new data into the register.
 157          */
 158         switch (rt2x00dev->chip.rt) {
 159         case RT6352:
 160                 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
 161                         reg = 0;
 162                         rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
 163                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
 164                                            word);
 165                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
 166                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
 167
 168                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 169                 }
 170                 break;
 171
 172         default:
 173                 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 174                         reg = 0;
 175                         rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 176                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 177                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 178                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 179
 180                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 181                 }
 182                 break;
 183         }
 184
 185         mutex_unlock(&rt2x00dev->csr_mutex);
 186 }
 187
 188 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
 189                                     const unsigned int reg, const u8 value)
 190 {
 191         rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
 192 }
 193
 194 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
 195                                        const unsigned int reg, const u8 value)
 196 {
 197         rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
 198         rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
 199 }
 200
 201 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
 202                                      const unsigned int reg, const u8 value)
 203 {
 204         rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
 205         rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
 206 }
 207
 208 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 209                             const unsigned int word)
 210 {
 211         u32 reg;
 212         u8 value;
 213
 214         mutex_lock(&rt2x00dev->csr_mutex);
 215
 216         /*
 217          * Wait until the RFCSR becomes available, afterwards we
 218          * can safely write the read request into the register.
 219          * After the data has been written, we wait until hardware
 220          * returns the correct value, if at any time the register
 221          * doesn't become available in time, reg will be 0xffffffff
 222          * which means we return 0xff to the caller.
 223          */
 224         switch (rt2x00dev->chip.rt) {
 225         case RT6352:
 226                 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
 227                         reg = 0;
 228                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
 229                                            word);
 230                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
 231                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
 232
 233                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 234
 235                         WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
 236                 }
 237
 238                 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
 239                 break;
 240
 241         default:
 242                 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 243                         reg = 0;
 244                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 245                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 246                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 247
 248                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 249
 250                         WAIT_FOR_RFCSR(rt2x00dev, &reg);
 251                 }
 252
 253                 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 254                 break;
 255         }
 256
 257         mutex_unlock(&rt2x00dev->csr_mutex);
 258
 259         return value;
 260 }
 261
 262 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
 263                                  const unsigned int reg)
 264 {
 265         return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
 266 }
 267
 268 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 269                             const unsigned int word, const u32 value)
 270 {
 271         u32 reg;
 272
 273         mutex_lock(&rt2x00dev->csr_mutex);
 274
 275         /*
 276          * Wait until the RF becomes available, afterwards we
 277          * can safely write the new data into the register.
 278          */
 279         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 280                 reg = 0;
 281                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 282                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 283                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 284                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 285
 286                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 287                 rt2x00_rf_write(rt2x00dev, word, value);
 288         }
 289
 290         mutex_unlock(&rt2x00dev->csr_mutex);
 291 }
 292
 293 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
 294         [EEPROM_CHIP_ID]                = 0x0000,
 295         [EEPROM_VERSION]                = 0x0001,
 296         [EEPROM_MAC_ADDR_0]             = 0x0002,
 297         [EEPROM_MAC_ADDR_1]             = 0x0003,
 298         [EEPROM_MAC_ADDR_2]             = 0x0004,
 299         [EEPROM_NIC_CONF0]              = 0x001a,
 300         [EEPROM_NIC_CONF1]              = 0x001b,
 301         [EEPROM_FREQ]                   = 0x001d,
 302         [EEPROM_LED_AG_CONF]            = 0x001e,
 303         [EEPROM_LED_ACT_CONF]           = 0x001f,
 304         [EEPROM_LED_POLARITY]           = 0x0020,
 305         [EEPROM_NIC_CONF2]              = 0x0021,
 306         [EEPROM_LNA]                    = 0x0022,
 307         [EEPROM_RSSI_BG]                = 0x0023,
 308         [EEPROM_RSSI_BG2]               = 0x0024,
 309         [EEPROM_TXMIXER_GAIN_BG]        = 0x0024, /* overlaps with RSSI_BG2 */
 310         [EEPROM_RSSI_A]                 = 0x0025,
 311         [EEPROM_RSSI_A2]                = 0x0026,
 312         [EEPROM_TXMIXER_GAIN_A]         = 0x0026, /* overlaps with RSSI_A2 */
 313         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0027,
 314         [EEPROM_TXPOWER_DELTA]          = 0x0028,
 315         [EEPROM_TXPOWER_BG1]            = 0x0029,
 316         [EEPROM_TXPOWER_BG2]            = 0x0030,
 317         [EEPROM_TSSI_BOUND_BG1]         = 0x0037,
 318         [EEPROM_TSSI_BOUND_BG2]         = 0x0038,
 319         [EEPROM_TSSI_BOUND_BG3]         = 0x0039,
 320         [EEPROM_TSSI_BOUND_BG4]         = 0x003a,
 321         [EEPROM_TSSI_BOUND_BG5]         = 0x003b,
 322         [EEPROM_TXPOWER_A1]             = 0x003c,
 323         [EEPROM_TXPOWER_A2]             = 0x0053,
 324         [EEPROM_TXPOWER_INIT]           = 0x0068,
 325         [EEPROM_TSSI_BOUND_A1]          = 0x006a,
 326         [EEPROM_TSSI_BOUND_A2]          = 0x006b,
 327         [EEPROM_TSSI_BOUND_A3]          = 0x006c,
 328         [EEPROM_TSSI_BOUND_A4]          = 0x006d,
 329         [EEPROM_TSSI_BOUND_A5]          = 0x006e,
 330         [EEPROM_TXPOWER_BYRATE]         = 0x006f,
 331         [EEPROM_BBP_START]              = 0x0078,
 332 };
 333
 334 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
 335         [EEPROM_CHIP_ID]                = 0x0000,
 336         [EEPROM_VERSION]                = 0x0001,
 337         [EEPROM_MAC_ADDR_0]             = 0x0002,
 338         [EEPROM_MAC_ADDR_1]             = 0x0003,
 339         [EEPROM_MAC_ADDR_2]             = 0x0004,
 340         [EEPROM_NIC_CONF0]              = 0x001a,
 341         [EEPROM_NIC_CONF1]              = 0x001b,
 342         [EEPROM_NIC_CONF2]              = 0x001c,
 343         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0020,
 344         [EEPROM_FREQ]                   = 0x0022,
 345         [EEPROM_LED_AG_CONF]            = 0x0023,
 346         [EEPROM_LED_ACT_CONF]           = 0x0024,
 347         [EEPROM_LED_POLARITY]           = 0x0025,
 348         [EEPROM_LNA]                    = 0x0026,
 349         [EEPROM_EXT_LNA2]               = 0x0027,
 350         [EEPROM_RSSI_BG]                = 0x0028,
 351         [EEPROM_RSSI_BG2]               = 0x0029,
 352         [EEPROM_RSSI_A]                 = 0x002a,
 353         [EEPROM_RSSI_A2]                = 0x002b,
 354         [EEPROM_TXPOWER_BG1]            = 0x0030,
 355         [EEPROM_TXPOWER_BG2]            = 0x0037,
 356         [EEPROM_EXT_TXPOWER_BG3]        = 0x003e,
 357         [EEPROM_TSSI_BOUND_BG1]         = 0x0045,
 358         [EEPROM_TSSI_BOUND_BG2]         = 0x0046,
 359         [EEPROM_TSSI_BOUND_BG3]         = 0x0047,
 360         [EEPROM_TSSI_BOUND_BG4]         = 0x0048,
 361         [EEPROM_TSSI_BOUND_BG5]         = 0x0049,
 362         [EEPROM_TXPOWER_A1]             = 0x004b,
 363         [EEPROM_TXPOWER_A2]             = 0x0065,
 364         [EEPROM_EXT_TXPOWER_A3]         = 0x007f,
 365         [EEPROM_TSSI_BOUND_A1]          = 0x009a,
 366         [EEPROM_TSSI_BOUND_A2]          = 0x009b,
 367         [EEPROM_TSSI_BOUND_A3]          = 0x009c,
 368         [EEPROM_TSSI_BOUND_A4]          = 0x009d,
 369         [EEPROM_TSSI_BOUND_A5]          = 0x009e,
 370         [EEPROM_TXPOWER_BYRATE]         = 0x00a0,
 371 };
 372
 373 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
 374                                              const enum rt2800_eeprom_word word)
 375 {
 376         const unsigned int *map;
 377         unsigned int index;
 378
 379         if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
 380                       "%s: invalid EEPROM word %d\n",
 381                       wiphy_name(rt2x00dev->hw->wiphy), word))
 382                 return 0;
 383
 384         if (rt2x00_rt(rt2x00dev, RT3593) ||
 385             rt2x00_rt(rt2x00dev, RT3883))
 386                 map = rt2800_eeprom_map_ext;
 387         else
 388                 map = rt2800_eeprom_map;
 389
 390         index = map[word];
 391
 392         /* Index 0 is valid only for EEPROM_CHIP_ID.
 393          * Otherwise it means that the offset of the
 394          * given word is not initialized in the map,
 395          * or that the field is not usable on the
 396          * actual chipset.
 397          */
 398         WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
 399                   "%s: invalid access of EEPROM word %d\n",
 400                   wiphy_name(rt2x00dev->hw->wiphy), word);
 401
 402         return index;
 403 }
 404
 405 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
 406                                 const enum rt2800_eeprom_word word)
 407 {
 408         unsigned int index;
 409
 410         index = rt2800_eeprom_word_index(rt2x00dev, word);
 411         return rt2x00_eeprom_addr(rt2x00dev, index);
 412 }
 413
 414 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
 415                               const enum rt2800_eeprom_word word)
 416 {
 417         unsigned int index;
 418
 419         index = rt2800_eeprom_word_index(rt2x00dev, word);
 420         return rt2x00_eeprom_read(rt2x00dev, index);
 421 }
 422
 423 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
 424                                 const enum rt2800_eeprom_word word, u16 data)
 425 {
 426         unsigned int index;
 427
 428         index = rt2800_eeprom_word_index(rt2x00dev, word);
 429         rt2x00_eeprom_write(rt2x00dev, index, data);
 430 }
 431
 432 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
 433                                          const enum rt2800_eeprom_word array,
 434                                          unsigned int offset)
 435 {
 436         unsigned int index;
 437
 438         index = rt2800_eeprom_word_index(rt2x00dev, array);
 439         return rt2x00_eeprom_read(rt2x00dev, index + offset);
 440 }
 441
 442 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 443 {
 444         u32 reg;
 445         int i, count;
 446
 447         reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
 448         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 449         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 450         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 451         rt2x00_set_field32(&reg, WLAN_EN, 1);
 452         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 453
 454         udelay(REGISTER_BUSY_DELAY);
 455
 456         count = 0;
 457         do {
 458                 /*
 459                  * Check PLL_LD & XTAL_RDY.
 460                  */
 461                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 462                         reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
 463                         if (rt2x00_get_field32(reg, PLL_LD) &&
 464                             rt2x00_get_field32(reg, XTAL_RDY))
 465                                 break;
 466                         udelay(REGISTER_BUSY_DELAY);
 467                 }
 468
 469                 if (i >= REGISTER_BUSY_COUNT) {
 470
 471                         if (count >= 10)
 472                                 return -EIO;
 473
 474                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 475                         udelay(REGISTER_BUSY_DELAY);
 476                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 477                         udelay(REGISTER_BUSY_DELAY);
 478                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 479                         udelay(REGISTER_BUSY_DELAY);
 480                         count++;
 481                 } else {
 482                         count = 0;
 483                 }
 484
 485                 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
 486                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 487                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 488                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 489                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 490                 udelay(10);
 491                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 492                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 493                 udelay(10);
 494                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 495         } while (count != 0);
 496
 497         return 0;
 498 }
 499
 500 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 501                         const u8 command, const u8 token,
 502                         const u8 arg0, const u8 arg1)
 503 {
 504         u32 reg;
 505
 506         /*
 507          * SOC devices don't support MCU requests.
 508          */
 509         if (rt2x00_is_soc(rt2x00dev))
 510                 return;
 511
 512         mutex_lock(&rt2x00dev->csr_mutex);
 513
 514         /*
 515          * Wait until the MCU becomes available, afterwards we
 516          * can safely write the new data into the register.
 517          */
 518         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 519                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 520                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 521                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 522                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 523                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 524
 525                 reg = 0;
 526                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 527                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 528         }
 529
 530         mutex_unlock(&rt2x00dev->csr_mutex);
 531 }
 532 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 533
 534 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 535 {
 536         unsigned int i = 0;
 537         u32 reg;
 538
 539         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 540                 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
 541                 if (reg && reg != ~0)
 542                         return 0;
 543                 msleep(1);
 544         }
 545
 546         rt2x00_err(rt2x00dev, "Unstable hardware\n");
 547         return -EBUSY;
 548 }
 549 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 550
 551 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 552 {
 553         unsigned int i;
 554         u32 reg;
 555
 556         /*
 557          * Some devices are really slow to respond here. Wait a whole second
 558          * before timing out.
 559          */
 560         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 561                 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
 562                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 563                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 564                         return 0;
 565
 566                 msleep(10);
 567         }
 568
 569         rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
 570         return -EACCES;
 571 }
 572 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 573
 574 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 575 {
 576         u32 reg;
 577
 578         reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
 579         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 580         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 581         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 582         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 583         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 584         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 585 }
 586 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 587
 588 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
 589                                unsigned short *txwi_size,
 590                                unsigned short *rxwi_size)
 591 {
 592         switch (rt2x00dev->chip.rt) {
 593         case RT3593:
 594         case RT3883:
 595                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 596                 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
 597                 break;
 598
 599         case RT5592:
 600         case RT6352:
 601                 *txwi_size = TXWI_DESC_SIZE_5WORDS;
 602                 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
 603                 break;
 604
 605         default:
 606                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 607                 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
 608                 break;
 609         }
 610 }
 611 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
 612
 613 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 614 {
 615         u16 fw_crc;
 616         u16 crc;
 617
 618         /*
 619          * The last 2 bytes in the firmware array are the crc checksum itself,
 620          * this means that we should never pass those 2 bytes to the crc
 621          * algorithm.
 622          */
 623         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 624
 625         /*
 626          * Use the crc ccitt algorithm.
 627          * This will return the same value as the legacy driver which
 628          * used bit ordering reversion on the both the firmware bytes
 629          * before input input as well as on the final output.
 630          * Obviously using crc ccitt directly is much more efficient.
 631          */
 632         crc = crc_ccitt(~0, data, len - 2);
 633
 634         /*
 635          * There is a small difference between the crc-itu-t + bitrev and
 636          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 637          * will be swapped, use swab16 to convert the crc to the correct
 638          * value.
 639          */
 640         crc = swab16(crc);
 641
 642         return fw_crc == crc;
 643 }
 644
 645 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 646                           const u8 *data, const size_t len)
 647 {
 648         size_t offset = 0;
 649         size_t fw_len;
 650         bool multiple;
 651
 652         /*
 653          * PCI(e) & SOC devices require firmware with a length
 654          * of 8kb. USB devices require firmware files with a length
 655          * of 4kb. Certain USB chipsets however require different firmware,
 656          * which Ralink only provides attached to the original firmware
 657          * file. Thus for USB devices, firmware files have a length
 658          * which is a multiple of 4kb. The firmware for rt3290 chip also
 659          * have a length which is a multiple of 4kb.
 660          */
 661         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 662                 fw_len = 4096;
 663         else
 664                 fw_len = 8192;
 665
 666         multiple = true;
 667         /*
 668          * Validate the firmware length
 669          */
 670         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 671                 return FW_BAD_LENGTH;
 672
 673         /*
 674          * Check if the chipset requires one of the upper parts
 675          * of the firmware.
 676          */
 677         if (rt2x00_is_usb(rt2x00dev) &&
 678             !rt2x00_rt(rt2x00dev, RT2860) &&
 679             !rt2x00_rt(rt2x00dev, RT2872) &&
 680             !rt2x00_rt(rt2x00dev, RT3070) &&
 681             ((len / fw_len) == 1))
 682                 return FW_BAD_VERSION;
 683
 684         /*
 685          * 8kb firmware files must be checked as if it were
 686          * 2 separate firmware files.
 687          */
 688         while (offset < len) {
 689                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 690                         return FW_BAD_CRC;
 691
 692                 offset += fw_len;
 693         }
 694
 695         return FW_OK;
 696 }
 697 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 698
 699 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 700                          const u8 *data, const size_t len)
 701 {
 702         unsigned int i;
 703         u32 reg;
 704         int retval;
 705
 706         if (rt2x00_rt(rt2x00dev, RT3290)) {
 707                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 708                 if (retval)
 709                         return -EBUSY;
 710         }
 711
 712         /*
 713          * If driver doesn't wake up firmware here,
 714          * rt2800_load_firmware will hang forever when interface is up again.
 715          */
 716         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 717
 718         /*
 719          * Wait for stable hardware.
 720          */
 721         if (rt2800_wait_csr_ready(rt2x00dev))
 722                 return -EBUSY;
 723
 724         if (rt2x00_is_pci(rt2x00dev)) {
 725                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 726                     rt2x00_rt(rt2x00dev, RT3572) ||
 727                     rt2x00_rt(rt2x00dev, RT5390) ||
 728                     rt2x00_rt(rt2x00dev, RT5392)) {
 729                         reg = rt2800_register_read(rt2x00dev, AUX_CTRL);
 730                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 731                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 732                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 733                 }
 734                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 735         }
 736
 737         rt2800_disable_wpdma(rt2x00dev);
 738
 739         /*
 740          * Write firmware to the device.
 741          */
 742         rt2800_drv_write_firmware(rt2x00dev, data, len);
 743
 744         /*
 745          * Wait for device to stabilize.
 746          */
 747         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 748                 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL);
 749                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 750                         break;
 751                 msleep(1);
 752         }
 753
 754         if (i == REGISTER_BUSY_COUNT) {
 755                 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
 756                 return -EBUSY;
 757         }
 758
 759         /*
 760          * Disable DMA, will be reenabled later when enabling
 761          * the radio.
 762          */
 763         rt2800_disable_wpdma(rt2x00dev);
 764
 765         /*
 766          * Initialize firmware.
 767          */
 768         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 769         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 770         if (rt2x00_is_usb(rt2x00dev)) {
 771                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 772                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 773         }
 774         msleep(1);
 775
 776         return 0;
 777 }
 778 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 779
 780 void rt2800_write_tx_data(struct queue_entry *entry,
 781                           struct txentry_desc *txdesc)
 782 {
 783         __le32 *txwi = rt2800_drv_get_txwi(entry);
 784         u32 word;
 785         int i;
 786
 787         /*
 788          * Initialize TX Info descriptor
 789          */
 790         word = rt2x00_desc_read(txwi, 0);
 791         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 792                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 793         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 794                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 795         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 796         rt2x00_set_field32(&word, TXWI_W0_TS,
 797                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 798         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 799                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 800         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 801                            txdesc->u.ht.mpdu_density);
 802         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 803         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 804         rt2x00_set_field32(&word, TXWI_W0_BW,
 805                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 806         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 807                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 808         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 809         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 810         rt2x00_desc_write(txwi, 0, word);
 811
 812         word = rt2x00_desc_read(txwi, 1);
 813         rt2x00_set_field32(&word, TXWI_W1_ACK,
 814                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 815         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 816                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 817         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 818         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 819                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 820                            txdesc->key_idx : txdesc->u.ht.wcid);
 821         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 822                            txdesc->length);
 823         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 824         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 825         rt2x00_desc_write(txwi, 1, word);
 826
 827         /*
 828          * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
 829          * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
 830          * When TXD_W3_WIV is set to 1 it will use the IV data
 831          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 832          * crypto entry in the registers should be used to encrypt the frame.
 833          *
 834          * Nulify all remaining words as well, we don't know how to program them.
 835          */
 836         for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
 837                 _rt2x00_desc_write(txwi, i, 0);
 838 }
 839 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 840
 841 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 842 {
 843         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 844         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 845         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 846         u16 eeprom;
 847         u8 offset0;
 848         u8 offset1;
 849         u8 offset2;
 850
 851         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
 852                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
 853                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 854                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 855                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
 856                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 857         } else {
 858                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
 859                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 860                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 861                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
 862                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 863         }
 864
 865         /*
 866          * Convert the value from the descriptor into the RSSI value
 867          * If the value in the descriptor is 0, it is considered invalid
 868          * and the default (extremely low) rssi value is assumed
 869          */
 870         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 871         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 872         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 873
 874         /*
 875          * mac80211 only accepts a single RSSI value. Calculating the
 876          * average doesn't deliver a fair answer either since -60:-60 would
 877          * be considered equally good as -50:-70 while the second is the one
 878          * which gives less energy...
 879          */
 880         rssi0 = max(rssi0, rssi1);
 881         return (int)max(rssi0, rssi2);
 882 }
 883
 884 void rt2800_process_rxwi(struct queue_entry *entry,
 885                          struct rxdone_entry_desc *rxdesc)
 886 {
 887         __le32 *rxwi = (__le32 *) entry->skb->data;
 888         u32 word;
 889
 890         word = rt2x00_desc_read(rxwi, 0);
 891
 892         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 893         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 894
 895         word = rt2x00_desc_read(rxwi, 1);
 896
 897         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 898                 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
 899
 900         if (rt2x00_get_field32(word, RXWI_W1_BW))
 901                 rxdesc->bw = RATE_INFO_BW_40;
 902
 903         /*
 904          * Detect RX rate, always use MCS as signal type.
 905          */
 906         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 907         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 908         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 909
 910         /*
 911          * Mask of 0x8 bit to remove the short preamble flag.
 912          */
 913         if (rxdesc->rate_mode == RATE_MODE_CCK)
 914                 rxdesc->signal &= ~0x8;
 915
 916         word = rt2x00_desc_read(rxwi, 2);
 917
 918         /*
 919          * Convert descriptor AGC value to RSSI value.
 920          */
 921         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 922         /*
 923          * Remove RXWI descriptor from start of the buffer.
 924          */
 925         skb_pull(entry->skb, entry->queue->winfo_size);
 926 }
 927 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 928
 929 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc,
 930                                     u32 status, enum nl80211_band band)
 931 {
 932         u8 flags = 0;
 933         u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 934
 935         switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) {
 936         case RATE_MODE_HT_GREENFIELD:
 937                 flags |= IEEE80211_TX_RC_GREEN_FIELD;
 938                 /* fall through */
 939         case RATE_MODE_HT_MIX:
 940                 flags |= IEEE80211_TX_RC_MCS;
 941                 break;
 942         case RATE_MODE_OFDM:
 943                 if (band == NL80211_BAND_2GHZ)
 944                         idx += 4;
 945                 break;
 946         case RATE_MODE_CCK:
 947                 if (idx >= 8)
 948                         idx -= 8;
 949                 break;
 950         }
 951
 952         if (rt2x00_get_field32(status, TX_STA_FIFO_BW))
 953                 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
 954
 955         if (rt2x00_get_field32(status, TX_STA_FIFO_SGI))
 956                 flags |= IEEE80211_TX_RC_SHORT_GI;
 957
 958         skbdesc->tx_rate_idx = idx;
 959         skbdesc->tx_rate_flags = flags;
 960 }
 961
 962 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
 963 {
 964         __le32 *txwi;
 965         u32 word;
 966         int wcid, ack, pid;
 967         int tx_wcid, tx_ack, tx_pid, is_agg;
 968
 969         /*
 970          * This frames has returned with an IO error,
 971          * so the status report is not intended for this
 972          * frame.
 973          */
 974         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
 975                 return false;
 976
 977         wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
 978         ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
 979         pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
 980         is_agg  = rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE);
 981
 982         /*
 983          * Validate if this TX status report is intended for
 984          * this entry by comparing the WCID/ACK/PID fields.
 985          */
 986         txwi = rt2800_drv_get_txwi(entry);
 987
 988         word = rt2x00_desc_read(txwi, 1);
 989         tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 990         tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
 991         tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
 992
 993         if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) {
 994                 rt2x00_dbg(entry->queue->rt2x00dev,
 995                            "TX status report missed for queue %d entry %d\n",
 996                            entry->queue->qid, entry->entry_idx);
 997                 return false;
 998         }
 999
1000         return true;
1001 }
1002
1003 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,
1004                          bool match)
1005 {
1006         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1007         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1008         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1009         struct txdone_entry_desc txdesc;
1010         u32 word;
1011         u16 mcs, real_mcs;
1012         int aggr, ampdu, wcid, ack_req;
1013
1014         /*
1015          * Obtain the status about this packet.
1016          */
1017         txdesc.flags = 0;
1018         word = rt2x00_desc_read(txwi, 0);
1019
1020         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1021         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
1022
1023         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
1024         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
1025         wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
1026         ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED);
1027
1028         /*
1029          * If a frame was meant to be sent as a single non-aggregated MPDU
1030          * but ended up in an aggregate the used tx rate doesn't correlate
1031          * with the one specified in the TXWI as the whole aggregate is sent
1032          * with the same rate.
1033          *
1034          * For example: two frames are sent to rt2x00, the first one sets
1035          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
1036          * and requests MCS15. If the hw aggregates both frames into one
1037          * AMDPU the tx status for both frames will contain MCS7 although
1038          * the frame was sent successfully.
1039          *
1040          * Hence, replace the requested rate with the real tx rate to not
1041          * confuse the rate control algortihm by providing clearly wrong
1042          * data.
1043          *
1044          * FIXME: if we do not find matching entry, we tell that frame was
1045          * posted without any retries. We need to find a way to fix that
1046          * and provide retry count.
1047          */
1048         if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {
1049                 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
1050                 mcs = real_mcs;
1051         }
1052
1053         if (aggr == 1 || ampdu == 1)
1054                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
1055
1056         if (!ack_req)
1057                 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags);
1058
1059         /*
1060          * Ralink has a retry mechanism using a global fallback
1061          * table. We setup this fallback table to try the immediate
1062          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
1063          * always contains the MCS used for the last transmission, be
1064          * it successful or not.
1065          */
1066         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
1067                 /*
1068                  * Transmission succeeded. The number of retries is
1069                  * mcs - real_mcs
1070                  */
1071                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1072                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1073         } else {
1074                 /*
1075                  * Transmission failed. The number of retries is
1076                  * always 7 in this case (for a total number of 8
1077                  * frames sent).
1078                  */
1079                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1080                 txdesc.retry = rt2x00dev->long_retry;
1081         }
1082
1083         /*
1084          * the frame was retried at least once
1085          * -> hw used fallback rates
1086          */
1087         if (txdesc.retry)
1088                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1089
1090         if (!match) {
1091                 /* RCU assures non-null sta will not be freed by mac80211. */
1092                 rcu_read_lock();
1093                 if (likely(wcid >= WCID_START && wcid <= WCID_END))
1094                         skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START];
1095                 else
1096                         skbdesc->sta = NULL;
1097                 rt2x00lib_txdone_nomatch(entry, &txdesc);
1098                 rcu_read_unlock();
1099         } else {
1100                 rt2x00lib_txdone(entry, &txdesc);
1101         }
1102 }
1103 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
1104
1105 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota)
1106 {
1107         struct data_queue *queue;
1108         struct queue_entry *entry;
1109         u32 reg;
1110         u8 qid;
1111         bool match;
1112
1113         while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, &reg)) {
1114                 /*
1115                  * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is
1116                  * guaranteed to be one of the TX QIDs .
1117                  */
1118                 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
1119                 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
1120
1121                 if (unlikely(rt2x00queue_empty(queue))) {
1122                         rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
1123                                    qid);
1124                         break;
1125                 }
1126
1127                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1128
1129                 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1130                              !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) {
1131                         rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n",
1132                                     entry->entry_idx, qid);
1133                         break;
1134                 }
1135
1136                 match = rt2800_txdone_entry_check(entry, reg);
1137                 rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match);
1138         }
1139 }
1140 EXPORT_SYMBOL_GPL(rt2800_txdone);
1141
1142 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev,
1143                                                  struct queue_entry *entry)
1144 {
1145         bool ret;
1146         unsigned long tout;
1147
1148         if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1149                 return false;
1150
1151         if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags))
1152                 tout = msecs_to_jiffies(50);
1153         else
1154                 tout = msecs_to_jiffies(2000);
1155
1156         ret = time_after(jiffies, entry->last_action + tout);
1157         if (unlikely(ret))
1158                 rt2x00_dbg(entry->queue->rt2x00dev,
1159                            "TX status timeout for entry %d in queue %d\n",
1160                            entry->entry_idx, entry->queue->qid);
1161         return ret;
1162 }
1163
1164 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev)
1165 {
1166         struct data_queue *queue;
1167         struct queue_entry *entry;
1168
1169         tx_queue_for_each(rt2x00dev, queue) {
1170                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1171                 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1172                         return true;
1173         }
1174
1175         return false;
1176 }
1177 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout);
1178
1179 /*
1180  * test if there is an entry in any TX queue for which DMA is done
1181  * but the TX status has not been returned yet
1182  */
1183 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev)
1184 {
1185         struct data_queue *queue;
1186
1187         tx_queue_for_each(rt2x00dev, queue) {
1188                 if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) !=
1189                     rt2x00queue_get_entry(queue, Q_INDEX_DONE))
1190                         return true;
1191         }
1192         return false;
1193 }
1194 EXPORT_SYMBOL_GPL(rt2800_txstatus_pending);
1195
1196 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev)
1197 {
1198         struct data_queue *queue;
1199         struct queue_entry *entry;
1200
1201         /*
1202          * Process any trailing TX status reports for IO failures,
1203          * we loop until we find the first non-IO error entry. This
1204          * can either be a frame which is free, is being uploaded,
1205          * or has completed the upload but didn't have an entry
1206          * in the TX_STAT_FIFO register yet.
1207          */
1208         tx_queue_for_each(rt2x00dev, queue) {
1209                 while (!rt2x00queue_empty(queue)) {
1210                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1211
1212                         if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1213                             !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1214                                 break;
1215
1216                         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) ||
1217                             rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1218                                 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
1219                         else
1220                                 break;
1221                 }
1222         }
1223 }
1224 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus);
1225
1226 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1227                                           unsigned int index)
1228 {
1229         return HW_BEACON_BASE(index);
1230 }
1231
1232 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1233                                           unsigned int index)
1234 {
1235         return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1236 }
1237
1238 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1239 {
1240         struct data_queue *queue = rt2x00dev->bcn;
1241         struct queue_entry *entry;
1242         int i, bcn_num = 0;
1243         u64 off, reg = 0;
1244         u32 bssid_dw1;
1245
1246         /*
1247          * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
1248          */
1249         for (i = 0; i < queue->limit; i++) {
1250                 entry = &queue->entries[i];
1251                 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
1252                         continue;
1253                 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1254                 reg |= off << (8 * bcn_num);
1255                 bcn_num++;
1256         }
1257
1258         rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1259         rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1260
1261         /*
1262          * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
1263          */
1264         bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1);
1265         rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
1266                            bcn_num > 0 ? bcn_num - 1 : 0);
1267         rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1268 }
1269
1270 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
1271 {
1272         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1273         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1274         unsigned int beacon_base;
1275         unsigned int padding_len;
1276         u32 orig_reg, reg;
1277         const int txwi_desc_size = entry->queue->winfo_size;
1278
1279         /*
1280          * Disable beaconing while we are reloading the beacon data,
1281          * otherwise we might be sending out invalid data.
1282          */
1283         reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1284         orig_reg = reg;
1285         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1286         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1287
1288         /*
1289          * Add space for the TXWI in front of the skb.
1290          */
1291         memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
1292
1293         /*
1294          * Register descriptor details in skb frame descriptor.
1295          */
1296         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1297         skbdesc->desc = entry->skb->data;
1298         skbdesc->desc_len = txwi_desc_size;
1299
1300         /*
1301          * Add the TXWI for the beacon to the skb.
1302          */
1303         rt2800_write_tx_data(entry, txdesc);
1304
1305         /*
1306          * Dump beacon to userspace through debugfs.
1307          */
1308         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1309
1310         /*
1311          * Write entire beacon with TXWI and padding to register.
1312          */
1313         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1314         if (padding_len && skb_pad(entry->skb, padding_len)) {
1315                 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1316                 /* skb freed by skb_pad() on failure */
1317                 entry->skb = NULL;
1318                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1319                 return;
1320         }
1321
1322         beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1323
1324         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1325                                    entry->skb->len + padding_len);
1326         __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1327
1328         /*
1329          * Change global beacons settings.
1330          */
1331         rt2800_update_beacons_setup(rt2x00dev);
1332
1333         /*
1334          * Restore beaconing state.
1335          */
1336         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1337
1338         /*
1339          * Clean up beacon skb.
1340          */
1341         dev_kfree_skb_any(entry->skb);
1342         entry->skb = NULL;
1343 }
1344 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1345
1346 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1347                                                 unsigned int index)
1348 {
1349         int i;
1350         const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1351         unsigned int beacon_base;
1352
1353         beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1354
1355         /*
1356          * For the Beacon base registers we only need to clear
1357          * the whole TXWI which (when set to 0) will invalidate
1358          * the entire beacon.
1359          */
1360         for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1361                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1362 }
1363
1364 void rt2800_clear_beacon(struct queue_entry *entry)
1365 {
1366         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1367         u32 orig_reg, reg;
1368
1369         /*
1370          * Disable beaconing while we are reloading the beacon data,
1371          * otherwise we might be sending out invalid data.
1372          */
1373         orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1374         reg = orig_reg;
1375         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1376         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1377
1378         /*
1379          * Clear beacon.
1380          */
1381         rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1382         __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
1383
1384         /*
1385          * Change global beacons settings.
1386          */
1387         rt2800_update_beacons_setup(rt2x00dev);
1388         /*
1389          * Restore beaconing state.
1390          */
1391         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1392 }
1393 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1394
1395 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1396 const struct rt2x00debug rt2800_rt2x00debug = {
1397         .owner  = THIS_MODULE,
1398         .csr    = {
1399                 .read           = rt2800_register_read,
1400                 .write          = rt2800_register_write,
1401                 .flags          = RT2X00DEBUGFS_OFFSET,
1402                 .word_base      = CSR_REG_BASE,
1403                 .word_size      = sizeof(u32),
1404                 .word_count     = CSR_REG_SIZE / sizeof(u32),
1405         },
1406         .eeprom = {
1407                 /* NOTE: The local EEPROM access functions can't
1408                  * be used here, use the generic versions instead.
1409                  */
1410                 .read           = rt2x00_eeprom_read,
1411                 .write          = rt2x00_eeprom_write,
1412                 .word_base      = EEPROM_BASE,
1413                 .word_size      = sizeof(u16),
1414                 .word_count     = EEPROM_SIZE / sizeof(u16),
1415         },
1416         .bbp    = {
1417                 .read           = rt2800_bbp_read,
1418                 .write          = rt2800_bbp_write,
1419                 .word_base      = BBP_BASE,
1420                 .word_size      = sizeof(u8),
1421                 .word_count     = BBP_SIZE / sizeof(u8),
1422         },
1423         .rf     = {
1424                 .read           = rt2x00_rf_read,
1425                 .write          = rt2800_rf_write,
1426                 .word_base      = RF_BASE,
1427                 .word_size      = sizeof(u32),
1428                 .word_count     = RF_SIZE / sizeof(u32),
1429         },
1430         .rfcsr  = {
1431                 .read           = rt2800_rfcsr_read,
1432                 .write          = rt2800_rfcsr_write,
1433                 .word_base      = RFCSR_BASE,
1434                 .word_size      = sizeof(u8),
1435                 .word_count     = RFCSR_SIZE / sizeof(u8),
1436         },
1437 };
1438 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1439 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1440
1441 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1442 {
1443         u32 reg;
1444
1445         if (rt2x00_rt(rt2x00dev, RT3290)) {
1446                 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
1447                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1448         } else {
1449                 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1450                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1451         }
1452 }
1453 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1454
1455 #ifdef CONFIG_RT2X00_LIB_LEDS
1456 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1457                                   enum led_brightness brightness)
1458 {
1459         struct rt2x00_led *led =
1460             container_of(led_cdev, struct rt2x00_led, led_dev);
1461         unsigned int enabled = brightness != LED_OFF;
1462         unsigned int bg_mode =
1463             (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
1464         unsigned int polarity =
1465                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1466                                    EEPROM_FREQ_LED_POLARITY);
1467         unsigned int ledmode =
1468                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1469                                    EEPROM_FREQ_LED_MODE);
1470         u32 reg;
1471
1472         /* Check for SoC (SOC devices don't support MCU requests) */
1473         if (rt2x00_is_soc(led->rt2x00dev)) {
1474                 reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
1475
1476                 /* Set LED Polarity */
1477                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1478
1479                 /* Set LED Mode */
1480                 if (led->type == LED_TYPE_RADIO) {
1481                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1482                                            enabled ? 3 : 0);
1483                 } else if (led->type == LED_TYPE_ASSOC) {
1484                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1485                                            enabled ? 3 : 0);
1486                 } else if (led->type == LED_TYPE_QUALITY) {
1487                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1488                                            enabled ? 3 : 0);
1489                 }
1490
1491                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1492
1493         } else {
1494                 if (led->type == LED_TYPE_RADIO) {
1495                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1496                                               enabled ? 0x20 : 0);
1497                 } else if (led->type == LED_TYPE_ASSOC) {
1498                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1499                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1500                 } else if (led->type == LED_TYPE_QUALITY) {
1501                         /*
1502                          * The brightness is divided into 6 levels (0 - 5),
1503                          * The specs tell us the following levels:
1504                          *      0, 1 ,3, 7, 15, 31
1505                          * to determine the level in a simple way we can simply
1506                          * work with bitshifting:
1507                          *      (1 << level) - 1
1508                          */
1509                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1510                                               (1 << brightness / (LED_FULL / 6)) - 1,
1511                                               polarity);
1512                 }
1513         }
1514 }
1515
1516 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1517                      struct rt2x00_led *led, enum led_type type)
1518 {
1519         led->rt2x00dev = rt2x00dev;
1520         led->type = type;
1521         led->led_dev.brightness_set = rt2800_brightness_set;
1522         led->flags = LED_INITIALIZED;
1523 }
1524 #endif /* CONFIG_RT2X00_LIB_LEDS */
1525
1526 /*
1527  * Configuration handlers.
1528  */
1529 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1530                                const u8 *address,
1531                                int wcid)
1532 {
1533         struct mac_wcid_entry wcid_entry;
1534         u32 offset;
1535
1536         offset = MAC_WCID_ENTRY(wcid);
1537
1538         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1539         if (address)
1540                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1541
1542         rt2800_register_multiwrite(rt2x00dev, offset,
1543                                       &wcid_entry, sizeof(wcid_entry));
1544 }
1545
1546 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1547 {
1548         u32 offset;
1549         offset = MAC_WCID_ATTR_ENTRY(wcid);
1550         rt2800_register_write(rt2x00dev, offset, 0);
1551 }
1552
1553 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1554                                            int wcid, u32 bssidx)
1555 {
1556         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1557         u32 reg;
1558
1559         /*
1560          * The BSS Idx numbers is split in a main value of 3 bits,
1561          * and a extended field for adding one additional bit to the value.
1562          */
1563         reg = rt2800_register_read(rt2x00dev, offset);
1564         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1565         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1566                            (bssidx & 0x8) >> 3);
1567         rt2800_register_write(rt2x00dev, offset, reg);
1568 }
1569
1570 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1571                                            struct rt2x00lib_crypto *crypto,
1572                                            struct ieee80211_key_conf *key)
1573 {
1574         struct mac_iveiv_entry iveiv_entry;
1575         u32 offset;
1576         u32 reg;
1577
1578         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1579
1580         if (crypto->cmd == SET_KEY) {
1581                 reg = rt2800_register_read(rt2x00dev, offset);
1582                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1583                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1584                 /*
1585                  * Both the cipher as the BSS Idx numbers are split in a main
1586                  * value of 3 bits, and a extended field for adding one additional
1587                  * bit to the value.
1588                  */
1589                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1590                                    (crypto->cipher & 0x7));
1591                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1592                                    (crypto->cipher & 0x8) >> 3);
1593                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1594                 rt2800_register_write(rt2x00dev, offset, reg);
1595         } else {
1596                 /* Delete the cipher without touching the bssidx */
1597                 reg = rt2800_register_read(rt2x00dev, offset);
1598                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1599                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1600                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1601                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1602                 rt2800_register_write(rt2x00dev, offset, reg);
1603         }
1604
1605         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1606
1607         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1608         if ((crypto->cipher == CIPHER_TKIP) ||
1609             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1610             (crypto->cipher == CIPHER_AES))
1611                 iveiv_entry.iv[3] |= 0x20;
1612         iveiv_entry.iv[3] |= key->keyidx << 6;
1613         rt2800_register_multiwrite(rt2x00dev, offset,
1614                                       &iveiv_entry, sizeof(iveiv_entry));
1615 }
1616
1617 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1618                              struct rt2x00lib_crypto *crypto,
1619                              struct ieee80211_key_conf *key)
1620 {
1621         struct hw_key_entry key_entry;
1622         struct rt2x00_field32 field;
1623         u32 offset;
1624         u32 reg;
1625
1626         if (crypto->cmd == SET_KEY) {
1627                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1628
1629                 memcpy(key_entry.key, crypto->key,
1630                        sizeof(key_entry.key));
1631                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1632                        sizeof(key_entry.tx_mic));
1633                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1634                        sizeof(key_entry.rx_mic));
1635
1636                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1637                 rt2800_register_multiwrite(rt2x00dev, offset,
1638                                               &key_entry, sizeof(key_entry));
1639         }
1640
1641         /*
1642          * The cipher types are stored over multiple registers
1643          * starting with SHARED_KEY_MODE_BASE each word will have
1644          * 32 bits and contains the cipher types for 2 bssidx each.
1645          * Using the correct defines correctly will cause overhead,
1646          * so just calculate the correct offset.
1647          */
1648         field.bit_offset = 4 * (key->hw_key_idx % 8);
1649         field.bit_mask = 0x7 << field.bit_offset;
1650
1651         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1652
1653         reg = rt2800_register_read(rt2x00dev, offset);
1654         rt2x00_set_field32(&reg, field,
1655                            (crypto->cmd == SET_KEY) * crypto->cipher);
1656         rt2800_register_write(rt2x00dev, offset, reg);
1657
1658         /*
1659          * Update WCID information
1660          */
1661         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1662         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1663                                        crypto->bssidx);
1664         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1665
1666         return 0;
1667 }
1668 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1669
1670 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1671                                struct rt2x00lib_crypto *crypto,
1672                                struct ieee80211_key_conf *key)
1673 {
1674         struct hw_key_entry key_entry;
1675         u32 offset;
1676
1677         if (crypto->cmd == SET_KEY) {
1678                 /*
1679                  * Allow key configuration only for STAs that are
1680                  * known by the hw.
1681                  */
1682                 if (crypto->wcid > WCID_END)
1683                         return -ENOSPC;
1684                 key->hw_key_idx = crypto->wcid;
1685
1686                 memcpy(key_entry.key, crypto->key,
1687                        sizeof(key_entry.key));
1688                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1689                        sizeof(key_entry.tx_mic));
1690                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1691                        sizeof(key_entry.rx_mic));
1692
1693                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1694                 rt2800_register_multiwrite(rt2x00dev, offset,
1695                                               &key_entry, sizeof(key_entry));
1696         }
1697
1698         /*
1699          * Update WCID information
1700          */
1701         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1702
1703         return 0;
1704 }
1705 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1706
1707 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1708 {
1709         u8 i, max_psdu;
1710         u32 reg;
1711         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1712
1713         for (i = 0; i < 3; i++)
1714                 if (drv_data->ampdu_factor_cnt[i] > 0)
1715                         break;
1716
1717         max_psdu = min(drv_data->max_psdu, i);
1718
1719         reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
1720         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, max_psdu);
1721         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1722 }
1723
1724 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1725                    struct ieee80211_sta *sta)
1726 {
1727         struct rt2x00_dev *rt2x00dev = hw->priv;
1728         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1729         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1730         int wcid;
1731
1732         /*
1733          * Limit global maximum TX AMPDU length to smallest value of all
1734          * connected stations. In AP mode this can be suboptimal, but we
1735          * do not have a choice if some connected STA is not capable to
1736          * receive the same amount of data like the others.
1737          */
1738         if (sta->ht_cap.ht_supported) {
1739                 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++;
1740                 rt2800_set_max_psdu_len(rt2x00dev);
1741         }
1742
1743         /*
1744          * Search for the first free WCID entry and return the corresponding
1745          * index.
1746          */
1747         wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
1748
1749         /*
1750          * Store selected wcid even if it is invalid so that we can
1751          * later decide if the STA is uploaded into the hw.
1752          */
1753         sta_priv->wcid = wcid;
1754
1755         /*
1756          * No space left in the device, however, we can still communicate
1757          * with the STA -> No error.
1758          */
1759         if (wcid > WCID_END)
1760                 return 0;
1761
1762         __set_bit(wcid - WCID_START, drv_data->sta_ids);
1763         drv_data->wcid_to_sta[wcid - WCID_START] = sta;
1764
1765         /*
1766          * Clean up WCID attributes and write STA address to the device.
1767          */
1768         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1769         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1770         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1771                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1772         return 0;
1773 }
1774 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1775
1776 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1777                       struct ieee80211_sta *sta)
1778 {
1779         struct rt2x00_dev *rt2x00dev = hw->priv;
1780         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1781         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1782         int wcid = sta_priv->wcid;
1783
1784         if (sta->ht_cap.ht_supported) {
1785                 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--;
1786                 rt2800_set_max_psdu_len(rt2x00dev);
1787         }
1788
1789         if (wcid > WCID_END)
1790                 return 0;
1791         /*
1792          * Remove WCID entry, no need to clean the attributes as they will
1793          * get renewed when the WCID is reused.
1794          */
1795         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1796         drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1797         __clear_bit(wcid - WCID_START, drv_data->sta_ids);
1798
1799         return 0;
1800 }
1801 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1802
1803 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1804                           const unsigned int filter_flags)
1805 {
1806         u32 reg;
1807
1808         /*
1809          * Start configuration steps.
1810          * Note that the version error will always be dropped
1811          * and broadcast frames will always be accepted since
1812          * there is no filter for it at this time.
1813          */
1814         reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG);
1815         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1816                            !(filter_flags & FIF_FCSFAIL));
1817         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1818                            !(filter_flags & FIF_PLCPFAIL));
1819         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1820                            !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
1821         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1822         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1823         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1824                            !(filter_flags & FIF_ALLMULTI));
1825         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1826         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1827         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1828                            !(filter_flags & FIF_CONTROL));
1829         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1830                            !(filter_flags & FIF_CONTROL));
1831         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1832                            !(filter_flags & FIF_CONTROL));
1833         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1834                            !(filter_flags & FIF_CONTROL));
1835         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1836                            !(filter_flags & FIF_CONTROL));
1837         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1838                            !(filter_flags & FIF_PSPOLL));
1839         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1840         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1841                            !(filter_flags & FIF_CONTROL));
1842         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1843                            !(filter_flags & FIF_CONTROL));
1844         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1845 }
1846 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1847
1848 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1849                         struct rt2x00intf_conf *conf, const unsigned int flags)
1850 {
1851         u32 reg;
1852         bool update_bssid = false;
1853
1854         if (flags & CONFIG_UPDATE_TYPE) {
1855                 /*
1856                  * Enable synchronisation.
1857                  */
1858                 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1859                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1860                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1861
1862                 if (conf->sync == TSF_SYNC_AP_NONE) {
1863                         /*
1864                          * Tune beacon queue transmit parameters for AP mode
1865                          */
1866                         reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1867                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1868                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1869                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1870                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1871                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1872                 } else {
1873                         reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1874                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1875                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1876                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1877                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1878                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1879                 }
1880         }
1881
1882         if (flags & CONFIG_UPDATE_MAC) {
1883                 if (flags & CONFIG_UPDATE_TYPE &&
1884                     conf->sync == TSF_SYNC_AP_NONE) {
1885                         /*
1886                          * The BSSID register has to be set to our own mac
1887                          * address in AP mode.
1888                          */
1889                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1890                         update_bssid = true;
1891                 }
1892
1893                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1894                         reg = le32_to_cpu(conf->mac[1]);
1895                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1896                         conf->mac[1] = cpu_to_le32(reg);
1897                 }
1898
1899                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1900                                               conf->mac, sizeof(conf->mac));
1901         }
1902
1903         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1904                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1905                         reg = le32_to_cpu(conf->bssid[1]);
1906                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1907                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
1908                         conf->bssid[1] = cpu_to_le32(reg);
1909                 }
1910
1911                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1912                                               conf->bssid, sizeof(conf->bssid));
1913         }
1914 }
1915 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1916
1917 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1918                                     struct rt2x00lib_erp *erp)
1919 {
1920         bool any_sta_nongf = !!(erp->ht_opmode &
1921                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1922         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1923         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1924         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1925         u32 reg;
1926
1927         /* default protection rate for HT20: OFDM 24M */
1928         mm20_rate = gf20_rate = 0x4004;
1929
1930         /* default protection rate for HT40: duplicate OFDM 24M */
1931         mm40_rate = gf40_rate = 0x4084;
1932
1933         switch (protection) {
1934         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1935                 /*
1936                  * All STAs in this BSS are HT20/40 but there might be
1937                  * STAs not supporting greenfield mode.
1938                  * => Disable protection for HT transmissions.
1939                  */
1940                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1941
1942                 break;
1943         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1944                 /*
1945                  * All STAs in this BSS are HT20 or HT20/40 but there
1946                  * might be STAs not supporting greenfield mode.
1947                  * => Protect all HT40 transmissions.
1948                  */
1949                 mm20_mode = gf20_mode = 0;
1950                 mm40_mode = gf40_mode = 1;
1951
1952                 break;
1953         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1954                 /*
1955                  * Nonmember protection:
1956                  * According to 802.11n we _should_ protect all
1957                  * HT transmissions (but we don't have to).
1958                  *
1959                  * But if cts_protection is enabled we _shall_ protect
1960                  * all HT transmissions using a CCK rate.
1961                  *
1962                  * And if any station is non GF we _shall_ protect
1963                  * GF transmissions.
1964                  *
1965                  * We decide to protect everything
1966                  * -> fall through to mixed mode.
1967                  */
1968         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1969                 /*
1970                  * Legacy STAs are present
1971                  * => Protect all HT transmissions.
1972                  */
1973                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
1974
1975                 /*
1976                  * If erp protection is needed we have to protect HT
1977                  * transmissions with CCK 11M long preamble.
1978                  */
1979                 if (erp->cts_protection) {
1980                         /* don't duplicate RTS/CTS in CCK mode */
1981                         mm20_rate = mm40_rate = 0x0003;
1982                         gf20_rate = gf40_rate = 0x0003;
1983                 }
1984                 break;
1985         }
1986
1987         /* check for STAs not supporting greenfield mode */
1988         if (any_sta_nongf)
1989                 gf20_mode = gf40_mode = 1;
1990
1991         /* Update HT protection config */
1992         reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
1993         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1994         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1995         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1996
1997         reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
1998         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1999         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
2000         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2001
2002         reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
2003         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
2004         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
2005         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2006
2007         reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
2008         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
2009         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
2010         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2011 }
2012
2013 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
2014                        u32 changed)
2015 {
2016         u32 reg;
2017
2018         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2019                 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
2020                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
2021                                    !!erp->short_preamble);
2022                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2023         }
2024
2025         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2026                 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
2027                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
2028                                    erp->cts_protection ? 2 : 0);
2029                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2030         }
2031
2032         if (changed & BSS_CHANGED_BASIC_RATES) {
2033                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
2034                                       0xff0 | erp->basic_rates);
2035                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2036         }
2037
2038         if (changed & BSS_CHANGED_ERP_SLOT) {
2039                 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
2040                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
2041                                    erp->slot_time);
2042                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2043
2044                 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
2045                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
2046                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2047         }
2048
2049         if (changed & BSS_CHANGED_BEACON_INT) {
2050                 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
2051                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
2052                                    erp->beacon_int * 16);
2053                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2054         }
2055
2056         if (changed & BSS_CHANGED_HT)
2057                 rt2800_config_ht_opmode(rt2x00dev, erp);
2058 }
2059 EXPORT_SYMBOL_GPL(rt2800_config_erp);
2060
2061 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
2062 {
2063         u32 reg;
2064         u16 eeprom;
2065         u8 led_ctrl, led_g_mode, led_r_mode;
2066
2067         reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
2068         if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
2069                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
2070                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
2071         } else {
2072                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
2073                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
2074         }
2075         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2076
2077         reg = rt2800_register_read(rt2x00dev, LED_CFG);
2078         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
2079         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
2080         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
2081             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
2082                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
2083                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
2084                 if (led_ctrl == 0 || led_ctrl > 0x40) {
2085                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
2086                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
2087                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2088                 } else {
2089                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
2090                                            (led_g_mode << 2) | led_r_mode, 1);
2091                 }
2092         }
2093 }
2094
2095 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
2096                                      enum antenna ant)
2097 {
2098         u32 reg;
2099         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
2100         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
2101
2102         if (rt2x00_is_pci(rt2x00dev)) {
2103                 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR);
2104                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
2105                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
2106         } else if (rt2x00_is_usb(rt2x00dev))
2107                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
2108                                    eesk_pin, 0);
2109
2110         reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2111         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
2112         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
2113         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2114 }
2115
2116 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
2117 {
2118         u8 r1;
2119         u8 r3;
2120         u16 eeprom;
2121
2122         r1 = rt2800_bbp_read(rt2x00dev, 1);
2123         r3 = rt2800_bbp_read(rt2x00dev, 3);
2124
2125         if (rt2x00_rt(rt2x00dev, RT3572) &&
2126             rt2x00_has_cap_bt_coexist(rt2x00dev))
2127                 rt2800_config_3572bt_ant(rt2x00dev);
2128
2129         /*
2130          * Configure the TX antenna.
2131          */
2132         switch (ant->tx_chain_num) {
2133         case 1:
2134                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
2135                 break;
2136         case 2:
2137                 if (rt2x00_rt(rt2x00dev, RT3572) &&
2138                     rt2x00_has_cap_bt_coexist(rt2x00dev))
2139                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
2140                 else
2141                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2142                 break;
2143         case 3:
2144                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2145                 break;
2146         }
2147
2148         /*
2149          * Configure the RX antenna.
2150          */
2151         switch (ant->rx_chain_num) {
2152         case 1:
2153                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2154                     rt2x00_rt(rt2x00dev, RT3090) ||
2155                     rt2x00_rt(rt2x00dev, RT3352) ||
2156                     rt2x00_rt(rt2x00dev, RT3390)) {
2157                         eeprom = rt2800_eeprom_read(rt2x00dev,
2158                                                     EEPROM_NIC_CONF1);
2159                         if (rt2x00_get_field16(eeprom,
2160                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
2161                                 rt2800_set_ant_diversity(rt2x00dev,
2162                                                 rt2x00dev->default_ant.rx);
2163                 }
2164                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
2165                 break;
2166         case 2:
2167                 if (rt2x00_rt(rt2x00dev, RT3572) &&
2168                     rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2169                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
2170                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
2171                                 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
2172                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2173                 } else {
2174                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
2175                 }
2176                 break;
2177         case 3:
2178                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
2179                 break;
2180         }
2181
2182         rt2800_bbp_write(rt2x00dev, 3, r3);
2183         rt2800_bbp_write(rt2x00dev, 1, r1);
2184
2185         if (rt2x00_rt(rt2x00dev, RT3593) ||
2186             rt2x00_rt(rt2x00dev, RT3883)) {
2187                 if (ant->rx_chain_num == 1)
2188                         rt2800_bbp_write(rt2x00dev, 86, 0x00);
2189                 else
2190                         rt2800_bbp_write(rt2x00dev, 86, 0x46);
2191         }
2192 }
2193 EXPORT_SYMBOL_GPL(rt2800_config_ant);
2194
2195 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2196                                    struct rt2x00lib_conf *libconf)
2197 {
2198         u16 eeprom;
2199         short lna_gain;
2200
2201         if (libconf->rf.channel <= 14) {
2202                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2203                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
2204         } else if (libconf->rf.channel <= 64) {
2205                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2206                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
2207         } else if (libconf->rf.channel <= 128) {
2208                 if (rt2x00_rt(rt2x00dev, RT3593) ||
2209                     rt2x00_rt(rt2x00dev, RT3883)) {
2210                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2211                         lna_gain = rt2x00_get_field16(eeprom,
2212                                                       EEPROM_EXT_LNA2_A1);
2213                 } else {
2214                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
2215                         lna_gain = rt2x00_get_field16(eeprom,
2216                                                       EEPROM_RSSI_BG2_LNA_A1);
2217                 }
2218         } else {
2219                 if (rt2x00_rt(rt2x00dev, RT3593) ||
2220                     rt2x00_rt(rt2x00dev, RT3883)) {
2221                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2222                         lna_gain = rt2x00_get_field16(eeprom,
2223                                                       EEPROM_EXT_LNA2_A2);
2224                 } else {
2225                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
2226                         lna_gain = rt2x00_get_field16(eeprom,
2227                                                       EEPROM_RSSI_A2_LNA_A2);
2228                 }
2229         }
2230
2231         rt2x00dev->lna_gain = lna_gain;
2232 }
2233
2234 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2235 {
2236         return clk_get_rate(rt2x00dev->clk) == 20000000;
2237 }
2238
2239 #define FREQ_OFFSET_BOUND       0x5f
2240
2241 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
2242 {
2243         u8 freq_offset, prev_freq_offset;
2244         u8 rfcsr, prev_rfcsr;
2245
2246         freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2247         freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
2248
2249         rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
2250         prev_rfcsr = rfcsr;
2251
2252         rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
2253         if (rfcsr == prev_rfcsr)
2254                 return;
2255
2256         if (rt2x00_is_usb(rt2x00dev)) {
2257                 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2258                                    freq_offset, prev_rfcsr);
2259                 return;
2260         }
2261
2262         prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
2263         while (prev_freq_offset != freq_offset) {
2264                 if (prev_freq_offset < freq_offset)
2265                         prev_freq_offset++;
2266                 else
2267                         prev_freq_offset--;
2268
2269                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
2270                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2271
2272                 usleep_range(1000, 1500);
2273         }
2274 }
2275
2276 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2277                                          struct ieee80211_conf *conf,
2278                                          struct rf_channel *rf,
2279                                          struct channel_info *info)
2280 {
2281         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2282
2283         if (rt2x00dev->default_ant.tx_chain_num == 1)
2284                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
2285
2286         if (rt2x00dev->default_ant.rx_chain_num == 1) {
2287                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
2288                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2289         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
2290                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2291
2292         if (rf->channel > 14) {
2293                 /*
2294                  * When TX power is below 0, we should increase it by 7 to
2295                  * make it a positive value (Minimum value is -7).
2296                  * However this means that values between 0 and 7 have
2297                  * double meaning, and we should set a 7DBm boost flag.
2298                  */
2299                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
2300                                    (info->default_power1 >= 0));
2301
2302                 if (info->default_power1 < 0)
2303                         info->default_power1 += 7;
2304
2305                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
2306
2307                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
2308                                    (info->default_power2 >= 0));
2309
2310                 if (info->default_power2 < 0)
2311                         info->default_power2 += 7;
2312
2313                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
2314         } else {
2315                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2316                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
2317         }
2318
2319         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2320
2321         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2322         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2323         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2324         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2325
2326         udelay(200);
2327
2328         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2329         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2330         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2331         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2332
2333         udelay(200);
2334
2335         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2336         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2337         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2338         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2339 }
2340
2341 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2342                                          struct ieee80211_conf *conf,
2343                                          struct rf_channel *rf,
2344                                          struct channel_info *info)
2345 {
2346         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2347         u8 rfcsr, calib_tx, calib_rx;
2348
2349         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2350
2351         rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2352         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2353         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2354
2355         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2356         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2357         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2358
2359         rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2360         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2361         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2362
2363         rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2364         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2365         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2366
2367         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2368         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2369         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2370                           rt2x00dev->default_ant.rx_chain_num <= 1);
2371         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2372                           rt2x00dev->default_ant.rx_chain_num <= 2);
2373         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2374         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2375                           rt2x00dev->default_ant.tx_chain_num <= 1);
2376         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2377                           rt2x00dev->default_ant.tx_chain_num <= 2);
2378         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2379
2380         rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2381         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2382         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2383
2384         if (rt2x00_rt(rt2x00dev, RT3390)) {
2385                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2386                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2387         } else {
2388                 if (conf_is_ht40(conf)) {
2389                         calib_tx = drv_data->calibration_bw40;
2390                         calib_rx = drv_data->calibration_bw40;
2391                 } else {
2392                         calib_tx = drv_data->calibration_bw20;
2393                         calib_rx = drv_data->calibration_bw20;
2394                 }
2395         }
2396
2397         rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
2398         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2399         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2400
2401         rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
2402         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2403         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2404
2405         rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2406         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2407         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2408
2409         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2410         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2411         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2412
2413         usleep_range(1000, 1500);
2414
2415         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2416         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2417 }
2418
2419 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2420                                          struct ieee80211_conf *conf,
2421                                          struct rf_channel *rf,
2422                                          struct channel_info *info)
2423 {
2424         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2425         u8 rfcsr;
2426         u32 reg;
2427
2428         if (rf->channel <= 14) {
2429                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2430                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2431         } else {
2432                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2433                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2434         }
2435
2436         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2437         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2438
2439         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2440         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2441         if (rf->channel <= 14)
2442                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2443         else
2444                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2445         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2446
2447         rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
2448         if (rf->channel <= 14)
2449                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2450         else
2451                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2452         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2453
2454         rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2455         if (rf->channel <= 14) {
2456                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2457                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2458                                   info->default_power1);
2459         } else {
2460                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2461                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2462                                 (info->default_power1 & 0x3) |
2463                                 ((info->default_power1 & 0xC) << 1));
2464         }
2465         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2466
2467         rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2468         if (rf->channel <= 14) {
2469                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2470                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2471                                   info->default_power2);
2472         } else {
2473                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2474                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2475                                 (info->default_power2 & 0x3) |
2476                                 ((info->default_power2 & 0xC) << 1));
2477         }
2478         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2479
2480         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2481         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2482         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2483         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2484         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2485         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2486         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2487         if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2488                 if (rf->channel <= 14) {
2489                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2490                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2491                 }
2492                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2493                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2494         } else {
2495                 switch (rt2x00dev->default_ant.tx_chain_num) {
2496                 case 1:
2497                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2498                         /* fall through */
2499                 case 2:
2500                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2501                         break;
2502                 }
2503
2504                 switch (rt2x00dev->default_ant.rx_chain_num) {
2505                 case 1:
2506                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2507                         /* fall through */
2508                 case 2:
2509                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2510                         break;
2511                 }
2512         }
2513         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2514
2515         rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2516         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2517         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2518
2519         if (conf_is_ht40(conf)) {
2520                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2521                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2522         } else {
2523                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2524                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2525         }
2526
2527         if (rf->channel <= 14) {
2528                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2529                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2530                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2531                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2532                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2533                 rfcsr = 0x4c;
2534                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2535                                   drv_data->txmixer_gain_24g);
2536                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2537                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2538                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2539                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2540                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2541                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2542                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2543                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2544         } else {
2545                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2546                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2547                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2548                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2549                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2550                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2551                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2552                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2553                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2554                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2555                 rfcsr = 0x7a;
2556                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2557                                   drv_data->txmixer_gain_5g);
2558                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2559                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2560                 if (rf->channel <= 64) {
2561                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2562                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2563                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2564                 } else if (rf->channel <= 128) {
2565                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2566                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2567                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2568                 } else {
2569                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2570                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2571                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2572                 }
2573                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2574                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2575                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2576         }
2577
2578         reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2579         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2580         if (rf->channel <= 14)
2581                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2582         else
2583                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2584         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2585
2586         rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2587         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2588         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2589 }
2590
2591 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2592                                          struct ieee80211_conf *conf,
2593                                          struct rf_channel *rf,
2594                                          struct channel_info *info)
2595 {
2596         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2597         u8 txrx_agc_fc;
2598         u8 txrx_h20m;
2599         u8 rfcsr;
2600         u8 bbp;
2601         const bool txbf_enabled = false; /* TODO */
2602
2603         /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2604         bbp = rt2800_bbp_read(rt2x00dev, 109);
2605         rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2606         rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2607         rt2800_bbp_write(rt2x00dev, 109, bbp);
2608
2609         bbp = rt2800_bbp_read(rt2x00dev, 110);
2610         rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2611         rt2800_bbp_write(rt2x00dev, 110, bbp);
2612
2613         if (rf->channel <= 14) {
2614                 /* Restore BBP 25 & 26 for 2.4 GHz */
2615                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2616                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2617         } else {
2618                 /* Hard code BBP 25 & 26 for 5GHz */
2619
2620                 /* Enable IQ Phase correction */
2621                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2622                 /* Setup IQ Phase correction value */
2623                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2624         }
2625
2626         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2627         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2628
2629         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2630         rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2631         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2632
2633         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2634         rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2635         if (rf->channel <= 14)
2636                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2637         else
2638                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2639         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2640
2641         rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
2642         if (rf->channel <= 14) {
2643                 rfcsr = 0;
2644                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2645                                   info->default_power1 & 0x1f);
2646         } else {
2647                 if (rt2x00_is_usb(rt2x00dev))
2648                         rfcsr = 0x40;
2649
2650                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2651                                   ((info->default_power1 & 0x18) << 1) |
2652                                   (info->default_power1 & 7));
2653         }
2654         rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2655
2656         rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
2657         if (rf->channel <= 14) {
2658                 rfcsr = 0;
2659                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2660                                   info->default_power2 & 0x1f);
2661         } else {
2662                 if (rt2x00_is_usb(rt2x00dev))
2663                         rfcsr = 0x40;
2664
2665                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2666                                   ((info->default_power2 & 0x18) << 1) |
2667                                   (info->default_power2 & 7));
2668         }
2669         rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2670
2671         rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
2672         if (rf->channel <= 14) {
2673                 rfcsr = 0;
2674                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2675                                   info->default_power3 & 0x1f);
2676         } else {
2677                 if (rt2x00_is_usb(rt2x00dev))
2678                         rfcsr = 0x40;
2679
2680                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2681                                   ((info->default_power3 & 0x18) << 1) |
2682                                   (info->default_power3 & 7));
2683         }
2684         rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2685
2686         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2687         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2688         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2689         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2690         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2691         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2692         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2693         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2694         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2695
2696         switch (rt2x00dev->default_ant.tx_chain_num) {
2697         case 3:
2698                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2699                 /* fallthrough */
2700         case 2:
2701                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2702                 /* fallthrough */
2703         case 1:
2704                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2705                 break;
2706         }
2707
2708         switch (rt2x00dev->default_ant.rx_chain_num) {
2709         case 3:
2710                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2711                 /* fallthrough */
2712         case 2:
2713                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2714                 /* fallthrough */
2715         case 1:
2716                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2717                 break;
2718         }
2719         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2720
2721         rt2800_freq_cal_mode1(rt2x00dev);
2722
2723         if (conf_is_ht40(conf)) {
2724                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2725                                                 RFCSR24_TX_AGC_FC);
2726                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2727                                               RFCSR24_TX_H20M);
2728         } else {
2729                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2730                                                 RFCSR24_TX_AGC_FC);
2731                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2732                                               RFCSR24_TX_H20M);
2733         }
2734
2735         /* NOTE: the reference driver does not writes the new value
2736          * back to RFCSR 32
2737          */
2738         rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
2739         rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2740
2741         if (rf->channel <= 14)
2742                 rfcsr = 0xa0;
2743         else
2744                 rfcsr = 0x80;
2745         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2746
2747         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2748         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2749         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2750         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2751
2752         /* Band selection */
2753         rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2754         if (rf->channel <= 14)
2755                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2756         else
2757                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2758         rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2759
2760         rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
2761         if (rf->channel <= 14)
2762                 rfcsr = 0x3c;
2763         else
2764                 rfcsr = 0x20;
2765         rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2766
2767         rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2768         if (rf->channel <= 14)
2769                 rfcsr = 0x1a;
2770         else
2771                 rfcsr = 0x12;
2772         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2773
2774         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2775         if (rf->channel >= 1 && rf->channel <= 14)
2776                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2777         else if (rf->channel >= 36 && rf->channel <= 64)
2778                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2779         else if (rf->channel >= 100 && rf->channel <= 128)
2780                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2781         else
2782                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2783         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2784
2785         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2786         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2787         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2788
2789         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2790
2791         if (rf->channel <= 14) {
2792                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2793                 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2794         } else {
2795                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2796                 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2797         }
2798
2799         rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2800         rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2801         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2802
2803         rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2804         if (rf->channel <= 14) {
2805                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2806                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2807         } else {
2808                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2809                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2810         }
2811         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2812
2813         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2814         if (rf->channel <= 14)
2815                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2816         else
2817                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2818
2819         if (txbf_enabled)
2820                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2821
2822         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2823
2824         rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2825         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2826         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2827
2828         rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
2829         if (rf->channel <= 14)
2830                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2831         else
2832                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2833         rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2834
2835         if (rf->channel <= 14) {
2836                 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2837                 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2838         } else {
2839                 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2840                 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2841         }
2842
2843         /* Initiate VCO calibration */
2844         rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2845         if (rf->channel <= 14) {
2846                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2847         } else {
2848                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2849                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2850                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2851                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2852                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2853                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2854         }
2855         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2856
2857         if (rf->channel >= 1 && rf->channel <= 14) {
2858                 rfcsr = 0x23;
2859                 if (txbf_enabled)
2860                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2861                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2862
2863                 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2864         } else if (rf->channel >= 36 && rf->channel <= 64) {
2865                 rfcsr = 0x36;
2866                 if (txbf_enabled)
2867                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2868                 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2869
2870                 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2871         } else if (rf->channel >= 100 && rf->channel <= 128) {
2872                 rfcsr = 0x32;
2873                 if (txbf_enabled)
2874                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2875                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2876
2877                 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2878         } else {
2879                 rfcsr = 0x30;
2880                 if (txbf_enabled)
2881                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2882                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2883
2884                 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2885         }
2886 }
2887
2888 static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev,
2889                                          struct ieee80211_conf *conf,
2890                                          struct rf_channel *rf,
2891                                          struct channel_info *info)
2892 {
2893         u8 rfcsr;
2894         u8 bbp;
2895         u8 pwr1, pwr2, pwr3;
2896
2897         const bool txbf_enabled = false; /* TODO */
2898
2899         /* TODO: add band selection */
2900
2901         if (rf->channel <= 14)
2902                 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
2903         else if (rf->channel < 132)
2904                 rt2800_rfcsr_write(rt2x00dev, 6, 0x80);
2905         else
2906                 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
2907
2908         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2909         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2910
2911         if (rf->channel <= 14)
2912                 rt2800_rfcsr_write(rt2x00dev, 11, 0x46);
2913         else
2914                 rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
2915
2916         if (rf->channel <= 14)
2917                 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
2918         else
2919                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2920
2921         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2922
2923         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2924         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2925         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2926         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2927         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2928         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2929         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2930         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2931         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2932
2933         switch (rt2x00dev->default_ant.tx_chain_num) {
2934         case 3:
2935                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2936                 /* fallthrough */
2937         case 2:
2938                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2939                 /* fallthrough */
2940         case 1:
2941                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2942                 break;
2943         }
2944
2945         switch (rt2x00dev->default_ant.rx_chain_num) {
2946         case 3:
2947                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2948                 /* fallthrough */
2949         case 2:
2950                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2951                 /* fallthrough */
2952         case 1:
2953                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2954                 break;
2955         }
2956         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2957
2958         rt2800_freq_cal_mode1(rt2x00dev);
2959
2960         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2961         if (!conf_is_ht40(conf))
2962                 rfcsr &= ~(0x06);
2963         else
2964                 rfcsr |= 0x06;
2965         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2966
2967         if (rf->channel <= 14)
2968                 rt2800_rfcsr_write(rt2x00dev, 31, 0xa0);
2969         else
2970                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2971
2972         if (conf_is_ht40(conf))
2973                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2974         else
2975                 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
2976
2977         if (rf->channel <= 14)
2978                 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
2979         else
2980                 rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
2981
2982         /* loopback RF_BS */
2983         rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2984         if (rf->channel <= 14)
2985                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2986         else
2987                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2988         rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2989
2990         if (rf->channel <= 14)
2991                 rfcsr = 0x23;
2992         else if (rf->channel < 100)
2993                 rfcsr = 0x36;
2994         else if (rf->channel < 132)
2995                 rfcsr = 0x32;
2996         else
2997                 rfcsr = 0x30;
2998
2999         if (txbf_enabled)
3000                 rfcsr |= 0x40;
3001
3002         rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3003
3004         if (rf->channel <= 14)
3005                 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
3006         else
3007                 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
3008
3009         if (rf->channel <= 14)
3010                 rfcsr = 0xbb;
3011         else if (rf->channel < 100)
3012                 rfcsr = 0xeb;
3013         else if (rf->channel < 132)
3014                 rfcsr = 0xb3;
3015         else
3016                 rfcsr = 0x9b;
3017         rt2800_rfcsr_write(rt2x00dev, 45, rfcsr);
3018
3019         if (rf->channel <= 14)
3020                 rfcsr = 0x8e;
3021         else
3022                 rfcsr = 0x8a;
3023
3024         if (txbf_enabled)
3025                 rfcsr |= 0x20;
3026
3027         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3028
3029         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
3030
3031         rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3032         if (rf->channel <= 14)
3033                 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
3034         else
3035                 rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
3036
3037         rfcsr = rt2800_rfcsr_read(rt2x00dev, 52);
3038         if (rf->channel <= 14)
3039                 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
3040         else
3041                 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
3042
3043         if (rf->channel <= 14) {
3044                 pwr1 = info->default_power1 & 0x1f;
3045                 pwr2 = info->default_power2 & 0x1f;
3046                 pwr3 = info->default_power3 & 0x1f;
3047         } else {
3048                 pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) |
3049                         (info->default_power1 & 0x7);
3050                 pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) |
3051                         (info->default_power2 & 0x7);
3052                 pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) |
3053                         (info->default_power3 & 0x7);
3054         }
3055
3056         rt2800_rfcsr_write(rt2x00dev, 53, pwr1);
3057         rt2800_rfcsr_write(rt2x00dev, 54, pwr2);
3058         rt2800_rfcsr_write(rt2x00dev, 55, pwr3);
3059
3060         rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n",
3061                    rf->channel, pwr1, pwr2, pwr3);
3062
3063         bbp = (info->default_power1 >> 5) |
3064               ((info->default_power2 & 0xe0) >> 1);
3065         rt2800_bbp_write(rt2x00dev, 109, bbp);
3066
3067         bbp = rt2800_bbp_read(rt2x00dev, 110);
3068         bbp &= 0x0f;
3069         bbp |= (info->default_power3 & 0xe0) >> 1;
3070         rt2800_bbp_write(rt2x00dev, 110, bbp);
3071
3072         rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
3073         if (rf->channel <= 14)
3074                 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
3075         else
3076                 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
3077
3078         /* Enable RF tuning */
3079         rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3080         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3081         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3082
3083         udelay(2000);
3084
3085         bbp = rt2800_bbp_read(rt2x00dev, 49);
3086         /* clear update flag */
3087         rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe);
3088         rt2800_bbp_write(rt2x00dev, 49, bbp);
3089
3090         /* TODO: add calibration for TxBF */
3091 }
3092
3093 #define POWER_BOUND             0x27
3094 #define POWER_BOUND_5G          0x2b
3095
3096 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
3097                                          struct ieee80211_conf *conf,
3098                                          struct rf_channel *rf,
3099                                          struct channel_info *info)
3100 {
3101         u8 rfcsr;
3102
3103         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3104         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3105         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3106         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3107         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3108
3109         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3110         if (info->default_power1 > POWER_BOUND)
3111                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3112         else
3113                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3114         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3115
3116         rt2800_freq_cal_mode1(rt2x00dev);
3117
3118         if (rf->channel <= 14) {
3119                 if (rf->channel == 6)
3120                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
3121                 else
3122                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3123
3124                 if (rf->channel >= 1 && rf->channel <= 6)
3125                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
3126                 else if (rf->channel >= 7 && rf->channel <= 11)
3127                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
3128                 else if (rf->channel >= 12 && rf->channel <= 14)
3129                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
3130         }
3131 }
3132
3133 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
3134                                          struct ieee80211_conf *conf,
3135                                          struct rf_channel *rf,
3136                                          struct channel_info *info)
3137 {
3138         u8 rfcsr;
3139
3140         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3141         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3142
3143         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
3144         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
3145         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
3146
3147         if (info->default_power1 > POWER_BOUND)
3148                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
3149         else
3150                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
3151
3152         if (info->default_power2 > POWER_BOUND)
3153                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
3154         else
3155                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
3156
3157         rt2800_freq_cal_mode1(rt2x00dev);
3158
3159         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3160         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3161         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3162
3163         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
3164                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3165         else
3166                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
3167
3168         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
3169                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3170         else
3171                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
3172
3173         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3174         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3175
3176         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3177
3178         rt2800_rfcsr_write(rt2x00dev, 31, 80);
3179 }
3180
3181 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
3182                                          struct ieee80211_conf *conf,
3183                                          struct rf_channel *rf,
3184                                          struct channel_info *info)
3185 {
3186         u8 rfcsr;
3187         int idx = rf->channel-1;
3188
3189         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3190         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3191         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3192         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3193         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3194
3195         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3196         if (info->default_power1 > POWER_BOUND)
3197                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3198         else
3199                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3200         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3201
3202         if (rt2x00_rt(rt2x00dev, RT5392)) {
3203                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3204                 if (info->default_power2 > POWER_BOUND)
3205                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
3206                 else
3207                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
3208                                           info->default_power2);
3209                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3210         }
3211
3212         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3213         if (rt2x00_rt(rt2x00dev, RT5392)) {
3214                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3215                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3216         }
3217         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3218         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3219         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3220         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3221         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3222
3223         rt2800_freq_cal_mode1(rt2x00dev);
3224
3225         if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
3226                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3227                         /* r55/r59 value array of channel 1~14 */
3228                         static const char r55_bt_rev[] = {0x83, 0x83,
3229                                 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
3230                                 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
3231                         static const char r59_bt_rev[] = {0x0e, 0x0e,
3232                                 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
3233                                 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
3234
3235                         rt2800_rfcsr_write(rt2x00dev, 55,
3236                                            r55_bt_rev[idx]);
3237                         rt2800_rfcsr_write(rt2x00dev, 59,
3238                                            r59_bt_rev[idx]);
3239                 } else {
3240                         static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
3241                                 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
3242                                 0x88, 0x88, 0x86, 0x85, 0x84};
3243
3244                         rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
3245                 }
3246         } else {
3247                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3248                         static const char r55_nonbt_rev[] = {0x23, 0x23,
3249                                 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
3250                                 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
3251                         static const char r59_nonbt_rev[] = {0x07, 0x07,
3252                                 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
3253                                 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
3254
3255                         rt2800_rfcsr_write(rt2x00dev, 55,
3256                                            r55_nonbt_rev[idx]);
3257                         rt2800_rfcsr_write(rt2x00dev, 59,
3258                                            r59_nonbt_rev[idx]);
3259                 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3260                            rt2x00_rt(rt2x00dev, RT5392) ||
3261                            rt2x00_rt(rt2x00dev, RT6352)) {
3262                         static const char r59_non_bt[] = {0x8f, 0x8f,
3263                                 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
3264                                 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
3265
3266                         rt2800_rfcsr_write(rt2x00dev, 59,
3267                                            r59_non_bt[idx]);
3268                 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
3269                         static const char r59_non_bt[] = {0x0b, 0x0b,
3270                                 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
3271                                 0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
3272
3273                         rt2800_rfcsr_write(rt2x00dev, 59,
3274                                            r59_non_bt[idx]);
3275                 }
3276         }
3277 }
3278
3279 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
3280                                          struct ieee80211_conf *conf,
3281                                          struct rf_channel *rf,
3282                                          struct channel_info *info)
3283 {
3284         u8 rfcsr, ep_reg;
3285         u32 reg;
3286         int power_bound;
3287
3288         /* TODO */
3289         const bool is_11b = false;
3290         const bool is_type_ep = false;
3291
3292         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
3293         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
3294                            (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
3295         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3296
3297         /* Order of values on rf_channel entry: N, K, mod, R */
3298         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
3299
3300         rfcsr = rt2800_rfcsr_read(rt2x00dev,  9);
3301         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
3302         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
3303         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
3304         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
3305
3306         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3307         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
3308         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
3309         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3310
3311         if (rf->channel <= 14) {
3312                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
3313                 /* FIXME: RF11 owerwrite ? */
3314                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
3315                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3316                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3317                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3318                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
3319                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3320                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3321                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
3322                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3323                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3324                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
3325                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
3326                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
3327                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
3328                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
3329                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
3330                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
3331                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
3332                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3333                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
3334                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3335                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3336                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
3337                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3338                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3339                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3340                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3341                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3342
3343                 /* TODO RF27 <- tssi */
3344
3345                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
3346                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
3347                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
3348
3349                 if (is_11b) {
3350                         /* CCK */
3351                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
3352                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
3353                         if (is_type_ep)
3354                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
3355                         else
3356                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
3357                 } else {
3358                         /* OFDM */
3359                         if (is_type_ep)
3360                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
3361                         else
3362                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3363                 }
3364
3365                 power_bound = POWER_BOUND;
3366                 ep_reg = 0x2;
3367         } else {
3368                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
3369                 /* FIMXE: RF11 overwrite */
3370                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
3371                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
3372                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3373                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3374                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
3375                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3376                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
3377                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3378                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3379                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3380                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3381                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3382                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3383                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3384
3385                 /* TODO RF27 <- tssi */
3386
3387                 if (rf->channel >= 36 && rf->channel <= 64) {
3388
3389                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3390                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3391                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3392                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3393                         if (rf->channel <= 50)
3394                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3395                         else if (rf->channel >= 52)
3396                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3397                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3398                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3399                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3400                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3401                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3402                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3403                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3404                         if (rf->channel <= 50) {
3405                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
3406                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3407                         } else if (rf->channel >= 52) {
3408                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3409                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3410                         }
3411
3412                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3413                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3414                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3415
3416                 } else if (rf->channel >= 100 && rf->channel <= 165) {
3417
3418                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3419                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3420                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3421                         if (rf->channel <= 153) {
3422                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3423                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3424                         } else if (rf->channel >= 155) {
3425                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3426                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3427                         }
3428                         if (rf->channel <= 138) {
3429                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3430                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3431                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3432                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3433                         } else if (rf->channel >= 140) {
3434                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3435                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3436                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3437                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3438                         }
3439                         if (rf->channel <= 124)
3440                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3441                         else if (rf->channel >= 126)
3442                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3443                         if (rf->channel <= 138)
3444                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3445                         else if (rf->channel >= 140)
3446                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3447                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3448                         if (rf->channel <= 138)
3449                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3450                         else if (rf->channel >= 140)
3451                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3452                         if (rf->channel <= 128)
3453                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3454                         else if (rf->channel >= 130)
3455                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3456                         if (rf->channel <= 116)
3457                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3458                         else if (rf->channel >= 118)
3459                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3460                         if (rf->channel <= 138)
3461                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3462                         else if (rf->channel >= 140)
3463                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3464                         if (rf->channel <= 116)
3465                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3466                         else if (rf->channel >= 118)
3467                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3468                 }
3469
3470                 power_bound = POWER_BOUND_5G;
3471                 ep_reg = 0x3;
3472         }
3473
3474         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3475         if (info->default_power1 > power_bound)
3476                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
3477         else
3478                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3479         if (is_type_ep)
3480                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
3481         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3482
3483         rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3484         if (info->default_power2 > power_bound)
3485                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
3486         else
3487                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
3488         if (is_type_ep)
3489                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
3490         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3491
3492         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3493         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3494         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3495
3496         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
3497                           rt2x00dev->default_ant.tx_chain_num >= 1);
3498         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
3499                           rt2x00dev->default_ant.tx_chain_num == 2);
3500         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3501
3502         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
3503                           rt2x00dev->default_ant.rx_chain_num >= 1);
3504         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
3505                           rt2x00dev->default_ant.rx_chain_num == 2);
3506         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3507
3508         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3509         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3510
3511         if (conf_is_ht40(conf))
3512                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3513         else
3514                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3515
3516         if (!is_11b) {
3517                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3518                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3519         }
3520
3521         /* TODO proper frequency adjustment */
3522         rt2800_freq_cal_mode1(rt2x00dev);
3523
3524         /* TODO merge with others */
3525         rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3526         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3527         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3528
3529         /* BBP settings */
3530         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3531         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3532         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3533
3534         rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3535         rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3536         rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3537         rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3538
3539         /* GLRT band configuration */
3540         rt2800_bbp_write(rt2x00dev, 195, 128);
3541         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3542         rt2800_bbp_write(rt2x00dev, 195, 129);
3543         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3544         rt2800_bbp_write(rt2x00dev, 195, 130);
3545         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3546         rt2800_bbp_write(rt2x00dev, 195, 131);
3547         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3548         rt2800_bbp_write(rt2x00dev, 195, 133);
3549         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3550         rt2800_bbp_write(rt2x00dev, 195, 124);
3551         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3552 }
3553
3554 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3555                                          struct ieee80211_conf *conf,
3556                                          struct rf_channel *rf,
3557                                          struct channel_info *info)
3558 {
3559         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3560         u8 rx_agc_fc, tx_agc_fc;
3561         u8 rfcsr;
3562
3563         /* Frequeny plan setting */
3564         /* Rdiv setting (set 0x03 if Xtal==20)
3565          * R13[1:0]
3566          */
3567         rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
3568         rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
3569                           rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3570         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3571
3572         /* N setting
3573          * R20[7:0] in rf->rf1
3574          * R21[0] always 0
3575          */
3576         rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
3577         rfcsr = (rf->rf1 & 0x00ff);
3578         rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3579
3580         rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3581         rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
3582         rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3583
3584         /* K setting (always 0)
3585          * R16[3:0] (RF PLL freq selection)
3586          */
3587         rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3588         rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
3589         rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3590
3591         /* D setting (always 0)
3592          * R22[2:0] (D=15, R22[2:0]=<111>)
3593          */
3594         rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
3595         rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
3596         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3597
3598         /* Ksd setting
3599          * Ksd: R17<7:0> in rf->rf2
3600          *      R18<7:0> in rf->rf3
3601          *      R19<1:0> in rf->rf4
3602          */
3603         rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3604         rfcsr = rf->rf2;
3605         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3606
3607         rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
3608         rfcsr = rf->rf3;
3609         rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3610
3611         rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
3612         rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
3613         rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3614
3615         /* Default: XO=20MHz , SDM mode */
3616         rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3617         rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
3618         rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3619
3620         rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3621         rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
3622         rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3623
3624         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3625         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
3626                           rt2x00dev->default_ant.tx_chain_num != 1);
3627         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3628
3629         rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
3630         rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
3631                           rt2x00dev->default_ant.tx_chain_num != 1);
3632         rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
3633                           rt2x00dev->default_ant.rx_chain_num != 1);
3634         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3635
3636         rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
3637         rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
3638                           rt2x00dev->default_ant.tx_chain_num != 1);
3639         rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3640
3641         /* RF for DC Cal BW */
3642         if (conf_is_ht40(conf)) {
3643                 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3644                 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3645                 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3646                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3647                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3648         } else {
3649                 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3650                 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3651                 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3652                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3653                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3654         }
3655
3656         if (conf_is_ht40(conf)) {
3657                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3658                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3659         } else {
3660                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3661                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3662         }
3663
3664         rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
3665         rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
3666                           conf_is_ht40(conf) && (rf->channel == 11));
3667         rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3668
3669         if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3670                 if (conf_is_ht40(conf)) {
3671                         rx_agc_fc = drv_data->rx_calibration_bw40;
3672                         tx_agc_fc = drv_data->tx_calibration_bw40;
3673                 } else {
3674                         rx_agc_fc = drv_data->rx_calibration_bw20;
3675                         tx_agc_fc = drv_data->tx_calibration_bw20;
3676                 }
3677                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
3678                 rfcsr &= (~0x3F);
3679                 rfcsr |= rx_agc_fc;
3680                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3681                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
3682                 rfcsr &= (~0x3F);
3683                 rfcsr |= rx_agc_fc;
3684                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3685                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
3686                 rfcsr &= (~0x3F);
3687                 rfcsr |= rx_agc_fc;
3688                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3689                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
3690                 rfcsr &= (~0x3F);
3691                 rfcsr |= rx_agc_fc;
3692                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3693
3694                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
3695                 rfcsr &= (~0x3F);
3696                 rfcsr |= tx_agc_fc;
3697                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3698                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
3699                 rfcsr &= (~0x3F);
3700                 rfcsr |= tx_agc_fc;
3701                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3702                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
3703                 rfcsr &= (~0x3F);
3704                 rfcsr |= tx_agc_fc;
3705                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3706                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
3707                 rfcsr &= (~0x3F);
3708                 rfcsr |= tx_agc_fc;
3709                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3710         }
3711 }
3712
3713 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
3714                               struct ieee80211_channel *chan,
3715                               int power_level) {
3716         u16 eeprom, target_power, max_power;
3717         u32 mac_sys_ctrl, mac_status;
3718         u32 reg;
3719         u8 bbp;
3720         int i;
3721
3722         /* hardware unit is 0.5dBm, limited to 23.5dBm */
3723         power_level *= 2;
3724         if (power_level > 0x2f)
3725                 power_level = 0x2f;
3726
3727         max_power = chan->max_power * 2;
3728         if (max_power > 0x2f)
3729                 max_power = 0x2f;
3730
3731         reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
3732         rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, power_level);
3733         rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, power_level);
3734         rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, max_power);
3735         rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, max_power);
3736
3737         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3738         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
3739                 /* init base power by eeprom target power */
3740                 target_power = rt2800_eeprom_read(rt2x00dev,
3741                                                   EEPROM_TXPOWER_INIT);
3742                 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
3743                 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
3744         }
3745         rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3746
3747         reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
3748         rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
3749         rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3750
3751         /* Save MAC SYS CTRL registers */
3752         mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
3753         /* Disable Tx/Rx */
3754         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3755         /* Check MAC Tx/Rx idle */
3756         for (i = 0; i < 10000; i++) {
3757                 mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
3758                 if (mac_status & 0x3)
3759                         usleep_range(50, 200);
3760                 else
3761                         break;
3762         }
3763
3764         if (i == 10000)
3765                 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
3766
3767         if (chan->center_freq > 2457) {
3768                 bbp = rt2800_bbp_read(rt2x00dev, 30);
3769                 bbp = 0x40;
3770                 rt2800_bbp_write(rt2x00dev, 30, bbp);
3771                 rt2800_rfcsr_write(rt2x00dev, 39, 0);
3772                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3773                         rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3774                 else
3775                         rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3776         } else {
3777                 bbp = rt2800_bbp_read(rt2x00dev, 30);
3778                 bbp = 0x1f;
3779                 rt2800_bbp_write(rt2x00dev, 30, bbp);
3780                 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
3781                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3782                         rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
3783                 else
3784                         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
3785         }
3786         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
3787
3788         rt2800_vco_calibration(rt2x00dev);
3789 }
3790
3791 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3792                                            const unsigned int word,
3793                                            const u8 value)
3794 {
3795         u8 chain, reg;
3796
3797         for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3798                 reg = rt2800_bbp_read(rt2x00dev, 27);
3799                 rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
3800                 rt2800_bbp_write(rt2x00dev, 27, reg);
3801
3802                 rt2800_bbp_write(rt2x00dev, word, value);
3803         }
3804 }
3805
3806 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3807 {
3808         u8 cal;
3809
3810         /* TX0 IQ Gain */
3811         rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3812         if (channel <= 14)
3813                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3814         else if (channel >= 36 && channel <= 64)
3815                 cal = rt2x00_eeprom_byte(rt2x00dev,
3816                                          EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3817         else if (channel >= 100 && channel <= 138)
3818                 cal = rt2x00_eeprom_byte(rt2x00dev,
3819                                          EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3820         else if (channel >= 140 && channel <= 165)
3821                 cal = rt2x00_eeprom_byte(rt2x00dev,
3822                                          EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3823         else
3824                 cal = 0;
3825         rt2800_bbp_write(rt2x00dev, 159, cal);
3826
3827         /* TX0 IQ Phase */
3828         rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3829         if (channel <= 14)
3830                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3831         else if (channel >= 36 && channel <= 64)
3832                 cal = rt2x00_eeprom_byte(rt2x00dev,
3833                                          EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3834         else if (channel >= 100 && channel <= 138)
3835                 cal = rt2x00_eeprom_byte(rt2x00dev,
3836                                          EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3837         else if (channel >= 140 && channel <= 165)
3838                 cal = rt2x00_eeprom_byte(rt2x00dev,
3839                                          EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3840         else
3841                 cal = 0;
3842         rt2800_bbp_write(rt2x00dev, 159, cal);
3843
3844         /* TX1 IQ Gain */
3845         rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3846         if (channel <= 14)
3847                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3848         else if (channel >= 36 && channel <= 64)
3849                 cal = rt2x00_eeprom_byte(rt2x00dev,
3850                                          EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3851         else if (channel >= 100 && channel <= 138)
3852                 cal = rt2x00_eeprom_byte(rt2x00dev,
3853                                          EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3854         else if (channel >= 140 && channel <= 165)
3855                 cal = rt2x00_eeprom_byte(rt2x00dev,
3856                                          EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3857         else
3858                 cal = 0;
3859         rt2800_bbp_write(rt2x00dev, 159, cal);
3860
3861         /* TX1 IQ Phase */
3862         rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3863         if (channel <= 14)
3864                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3865         else if (channel >= 36 && channel <= 64)
3866                 cal = rt2x00_eeprom_byte(rt2x00dev,
3867                                          EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3868         else if (channel >= 100 && channel <= 138)
3869                 cal = rt2x00_eeprom_byte(rt2x00dev,
3870                                          EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3871         else if (channel >= 140 && channel <= 165)
3872                 cal = rt2x00_eeprom_byte(rt2x00dev,
3873                                          EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3874         else
3875                 cal = 0;
3876         rt2800_bbp_write(rt2x00dev, 159, cal);
3877
3878         /* FIXME: possible RX0, RX1 callibration ? */
3879
3880         /* RF IQ compensation control */
3881         rt2800_bbp_write(rt2x00dev, 158, 0x04);
3882         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3883         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3884
3885         /* RF IQ imbalance compensation control */
3886         rt2800_bbp_write(rt2x00dev, 158, 0x03);
3887         cal = rt2x00_eeprom_byte(rt2x00dev,
3888                                  EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3889         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3890 }
3891
3892 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3893                                   unsigned int channel,
3894                                   char txpower)
3895 {
3896         if (rt2x00_rt(rt2x00dev, RT3593) ||
3897             rt2x00_rt(rt2x00dev, RT3883))
3898                 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3899
3900         if (channel <= 14)
3901                 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3902
3903         if (rt2x00_rt(rt2x00dev, RT3593) ||
3904             rt2x00_rt(rt2x00dev, RT3883))
3905                 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3906                                MAX_A_TXPOWER_3593);
3907         else
3908                 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3909 }
3910
3911 static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,
3912                               struct rf_channel *rf)
3913 {
3914         u8 bbp;
3915
3916         bbp = (rf->channel > 14) ? 0x48 : 0x38;
3917         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
3918
3919         rt2800_bbp_write(rt2x00dev, 69, 0x12);
3920
3921         if (rf->channel <= 14) {
3922                 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3923         } else {
3924                 /* Disable CCK packet detection */
3925                 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3926         }
3927
3928         rt2800_bbp_write(rt2x00dev, 73, 0x10);
3929
3930         if (rf->channel > 14) {
3931                 rt2800_bbp_write(rt2x00dev, 62, 0x1d);
3932                 rt2800_bbp_write(rt2x00dev, 63, 0x1d);
3933                 rt2800_bbp_write(rt2x00dev, 64, 0x1d);
3934         } else {
3935                 rt2800_bbp_write(rt2x00dev, 62, 0x2d);
3936                 rt2800_bbp_write(rt2x00dev, 63, 0x2d);
3937                 rt2800_bbp_write(rt2x00dev, 64, 0x2d);
3938         }
3939 }
3940
3941 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3942                                   struct ieee80211_conf *conf,
3943                                   struct rf_channel *rf,
3944                                   struct channel_info *info)
3945 {
3946         u32 reg;
3947         u32 tx_pin;
3948         u8 bbp, rfcsr;
3949
3950         info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3951                                                      info->default_power1);
3952         info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3953                                                      info->default_power2);
3954         if (rt2x00dev->default_ant.tx_chain_num > 2)
3955                 info->default_power3 =
3956                         rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3957                                               info->default_power3);
3958
3959         switch (rt2x00dev->chip.rt) {
3960         case RT3883:
3961                 rt3883_bbp_adjust(rt2x00dev, rf);
3962                 break;
3963         }
3964
3965         switch (rt2x00dev->chip.rf) {
3966         case RF2020:
3967         case RF3020:
3968         case RF3021:
3969         case RF3022:
3970         case RF3320:
3971                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
3972                 break;
3973         case RF3052:
3974                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
3975                 break;
3976         case RF3053:
3977                 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3978                 break;
3979         case RF3290:
3980                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3981                 break;
3982         case RF3322:
3983                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3984                 break;
3985         case RF3853:
3986                 rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info);
3987                 break;
3988         case RF3070:
3989         case RF5350:
3990         case RF5360:
3991         case RF5362:
3992         case RF5370:
3993         case RF5372:
3994         case RF5390:
3995         case RF5392:
3996                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
3997                 break;
3998         case RF5592:
3999                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
4000                 break;
4001         case RF7620:
4002                 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
4003                 break;
4004         default:
4005                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
4006         }
4007
4008         if (rt2x00_rf(rt2x00dev, RF3070) ||
4009             rt2x00_rf(rt2x00dev, RF3290) ||
4010             rt2x00_rf(rt2x00dev, RF3322) ||
4011             rt2x00_rf(rt2x00dev, RF5350) ||
4012             rt2x00_rf(rt2x00dev, RF5360) ||
4013             rt2x00_rf(rt2x00dev, RF5362) ||
4014             rt2x00_rf(rt2x00dev, RF5370) ||
4015             rt2x00_rf(rt2x00dev, RF5372) ||
4016             rt2x00_rf(rt2x00dev, RF5390) ||
4017             rt2x00_rf(rt2x00dev, RF5392)) {
4018                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
4019                 if (rt2x00_rf(rt2x00dev, RF3322)) {
4020                         rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M,
4021                                           conf_is_ht40(conf));
4022                         rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M,
4023                                           conf_is_ht40(conf));
4024                 } else {
4025                         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M,
4026                                           conf_is_ht40(conf));
4027                         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M,
4028                                           conf_is_ht40(conf));
4029                 }
4030                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4031
4032                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
4033                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4034                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4035         }
4036
4037         /*
4038          * Change BBP settings
4039          */
4040
4041         if (rt2x00_rt(rt2x00dev, RT3352)) {
4042                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4043                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4044                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4045
4046                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
4047                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4048                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
4049                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4050                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4051                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4052         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4053                 if (rf->channel > 14) {
4054                         /* Disable CCK Packet detection on 5GHz */
4055                         rt2800_bbp_write(rt2x00dev, 70, 0x00);
4056                 } else {
4057                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4058                 }
4059
4060                 if (conf_is_ht40(conf))
4061                         rt2800_bbp_write(rt2x00dev, 105, 0x04);
4062                 else
4063                         rt2800_bbp_write(rt2x00dev, 105, 0x34);
4064
4065                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4066                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4067                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4068                 rt2800_bbp_write(rt2x00dev, 77, 0x98);
4069         } else if (rt2x00_rt(rt2x00dev, RT3883)) {
4070                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4071                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4072                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4073
4074                 if (rt2x00dev->default_ant.rx_chain_num > 1)
4075                         rt2800_bbp_write(rt2x00dev, 86, 0x46);
4076                 else
4077                         rt2800_bbp_write(rt2x00dev, 86, 0);
4078         } else {
4079                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4080                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4081                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4082                 rt2800_bbp_write(rt2x00dev, 86, 0);
4083         }
4084
4085         if (rf->channel <= 14) {
4086                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4087                     !rt2x00_rt(rt2x00dev, RT5392) &&
4088                     !rt2x00_rt(rt2x00dev, RT6352)) {
4089                         if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4090                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4091                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4092                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4093                         } else {
4094                                 if (rt2x00_rt(rt2x00dev, RT3593))
4095                                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4096                                 else
4097                                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
4098                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
4099                         }
4100                         if (rt2x00_rt(rt2x00dev, RT3593) ||
4101                             rt2x00_rt(rt2x00dev, RT3883))
4102                                 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
4103                 }
4104
4105         } else {
4106                 if (rt2x00_rt(rt2x00dev, RT3572))
4107                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
4108                 else if (rt2x00_rt(rt2x00dev, RT3593) ||
4109                          rt2x00_rt(rt2x00dev, RT3883))
4110                         rt2800_bbp_write(rt2x00dev, 82, 0x82);
4111                 else if (!rt2x00_rt(rt2x00dev, RT6352))
4112                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
4113
4114                 if (rt2x00_rt(rt2x00dev, RT3593) ||
4115                     rt2x00_rt(rt2x00dev, RT3883))
4116                         rt2800_bbp_write(rt2x00dev, 83, 0x9a);
4117
4118                 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
4119                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
4120                 else
4121                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
4122         }
4123
4124         reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG);
4125         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
4126         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
4127         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
4128         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
4129
4130         if (rt2x00_rt(rt2x00dev, RT3572))
4131                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
4132
4133         if (rt2x00_rt(rt2x00dev, RT6352)) {
4134                 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4135                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1);
4136         } else {
4137                 tx_pin = 0;
4138         }
4139
4140         switch (rt2x00dev->default_ant.tx_chain_num) {
4141         case 3:
4142                 /* Turn on tertiary PAs */
4143                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
4144                                    rf->channel > 14);
4145                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
4146                                    rf->channel <= 14);
4147                 /* fall-through */
4148         case 2:
4149                 /* Turn on secondary PAs */
4150                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
4151                                    rf->channel > 14);
4152                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
4153                                    rf->channel <= 14);
4154                 /* fall-through */
4155         case 1:
4156                 /* Turn on primary PAs */
4157                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
4158                                    rf->channel > 14);
4159                 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
4160                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4161                 else
4162                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
4163                                            rf->channel <= 14);
4164                 break;
4165         }
4166
4167         switch (rt2x00dev->default_ant.rx_chain_num) {
4168         case 3:
4169                 /* Turn on tertiary LNAs */
4170                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN,
4171                                    rf->channel > 14);
4172                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN,
4173                                    rf->channel <= 14);
4174                 /* fall-through */
4175         case 2:
4176                 /* Turn on secondary LNAs */
4177                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN,
4178                                    rf->channel > 14);
4179                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN,
4180                                    rf->channel <= 14);
4181                 /* fall-through */
4182         case 1:
4183                 /* Turn on primary LNAs */
4184                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN,
4185                                    rf->channel > 14);
4186                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN,
4187                                    rf->channel <= 14);
4188                 break;
4189         }
4190
4191         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
4192         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
4193
4194         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4195
4196         if (rt2x00_rt(rt2x00dev, RT3572)) {
4197                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
4198
4199                 /* AGC init */
4200                 if (rf->channel <= 14)
4201                         reg = 0x1c + (2 * rt2x00dev->lna_gain);
4202                 else
4203                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4204
4205                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4206         }
4207
4208         if (rt2x00_rt(rt2x00dev, RT3593)) {
4209                 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
4210
4211                 /* Band selection */
4212                 if (rt2x00_is_usb(rt2x00dev) ||
4213                     rt2x00_is_pcie(rt2x00dev)) {
4214                         /* GPIO #8 controls all paths */
4215                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
4216                         if (rf->channel <= 14)
4217                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
4218                         else
4219                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
4220                 }
4221
4222                 /* LNA PE control. */
4223                 if (rt2x00_is_usb(rt2x00dev)) {
4224                         /* GPIO #4 controls PE0 and PE1,
4225                          * GPIO #7 controls PE2
4226                          */
4227                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
4228                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
4229
4230                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
4231                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
4232                 } else if (rt2x00_is_pcie(rt2x00dev)) {
4233                         /* GPIO #4 controls PE0, PE1 and PE2 */
4234                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
4235                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
4236                 }
4237
4238                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4239
4240                 /* AGC init */
4241                 if (rf->channel <= 14)
4242                         reg = 0x1c + 2 * rt2x00dev->lna_gain;
4243                 else
4244                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4245
4246                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4247
4248                 usleep_range(1000, 1500);
4249         }
4250
4251         if (rt2x00_rt(rt2x00dev, RT3883)) {
4252                 if (!conf_is_ht40(conf))
4253                         rt2800_bbp_write(rt2x00dev, 105, 0x34);
4254                 else
4255                         rt2800_bbp_write(rt2x00dev, 105, 0x04);
4256
4257                 /* AGC init */
4258                 if (rf->channel <= 14)
4259                         reg = 0x2e + rt2x00dev->lna_gain;
4260                 else
4261                         reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3);
4262
4263                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4264
4265                 usleep_range(1000, 1500);
4266         }
4267
4268         if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
4269                 reg = 0x10;
4270                 if (!conf_is_ht40(conf)) {
4271                         if (rt2x00_rt(rt2x00dev, RT6352) &&
4272                             rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4273                                 reg |= 0x5;
4274                         } else {
4275                                 reg |= 0xa;
4276                         }
4277                 }
4278                 rt2800_bbp_write(rt2x00dev, 195, 141);
4279                 rt2800_bbp_write(rt2x00dev, 196, reg);
4280
4281                 /* AGC init.
4282                  * Despite the vendor driver using different values here for
4283                  * RT6352 chip, we use 0x1c for now. This may have to be changed
4284                  * once TSSI got implemented.
4285                  */
4286                 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
4287                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4288
4289                 rt2800_iq_calibrate(rt2x00dev, rf->channel);
4290         }
4291
4292         bbp = rt2800_bbp_read(rt2x00dev, 4);
4293         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
4294         rt2800_bbp_write(rt2x00dev, 4, bbp);
4295
4296         bbp = rt2800_bbp_read(rt2x00dev, 3);
4297         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
4298         rt2800_bbp_write(rt2x00dev, 3, bbp);
4299
4300         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4301                 if (conf_is_ht40(conf)) {
4302                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
4303                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4304                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
4305                 } else {
4306                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
4307                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
4308                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
4309                 }
4310         }
4311
4312         usleep_range(1000, 1500);
4313
4314         /*
4315          * Clear channel statistic counters
4316          */
4317         reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
4318         reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
4319         reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
4320
4321         /*
4322          * Clear update flag
4323          */
4324         if (rt2x00_rt(rt2x00dev, RT3352) ||
4325             rt2x00_rt(rt2x00dev, RT5350)) {
4326                 bbp = rt2800_bbp_read(rt2x00dev, 49);
4327                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
4328                 rt2800_bbp_write(rt2x00dev, 49, bbp);
4329         }
4330 }
4331
4332 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
4333 {
4334         u8 tssi_bounds[9];
4335         u8 current_tssi;
4336         u16 eeprom;
4337         u8 step;
4338         int i;
4339
4340         /*
4341          * First check if temperature compensation is supported.
4342          */
4343         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
4344         if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
4345                 return 0;
4346
4347         /*
4348          * Read TSSI boundaries for temperature compensation from
4349          * the EEPROM.
4350          *
4351          * Array idx               0    1    2    3    4    5    6    7    8
4352          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
4353          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
4354          */
4355         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
4356                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1);
4357                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
4358                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
4359                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
4360                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
4361
4362                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2);
4363                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
4364                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
4365                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
4366                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
4367
4368                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3);
4369                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
4370                                         EEPROM_TSSI_BOUND_BG3_REF);
4371                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
4372                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
4373
4374                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4);
4375                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
4376                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
4377                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
4378                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
4379
4380                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5);
4381                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
4382                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
4383
4384                 step = rt2x00_get_field16(eeprom,
4385                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
4386         } else {
4387                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1);
4388                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
4389                                         EEPROM_TSSI_BOUND_A1_MINUS4);
4390                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
4391                                         EEPROM_TSSI_BOUND_A1_MINUS3);
4392
4393                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2);
4394                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
4395                                         EEPROM_TSSI_BOUND_A2_MINUS2);
4396                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
4397                                         EEPROM_TSSI_BOUND_A2_MINUS1);
4398
4399                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3);
4400                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
4401                                         EEPROM_TSSI_BOUND_A3_REF);
4402                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
4403                                         EEPROM_TSSI_BOUND_A3_PLUS1);
4404
4405                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4);
4406                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
4407                                         EEPROM_TSSI_BOUND_A4_PLUS2);
4408                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
4409                                         EEPROM_TSSI_BOUND_A4_PLUS3);
4410
4411                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5);
4412                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
4413                                         EEPROM_TSSI_BOUND_A5_PLUS4);
4414
4415                 step = rt2x00_get_field16(eeprom,
4416                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
4417         }
4418
4419         /*
4420          * Check if temperature compensation is supported.
4421          */
4422         if (tssi_bounds[4] == 0xff || step == 0xff)
4423                 return 0;
4424
4425         /*
4426          * Read current TSSI (BBP 49).
4427          */
4428         current_tssi = rt2800_bbp_read(rt2x00dev, 49);
4429
4430         /*
4431          * Compare TSSI value (BBP49) with the compensation boundaries
4432          * from the EEPROM and increase or decrease tx power.
4433          */
4434         for (i = 0; i <= 3; i++) {
4435                 if (current_tssi > tssi_bounds[i])
4436                         break;
4437         }
4438
4439         if (i == 4) {
4440                 for (i = 8; i >= 5; i--) {
4441                         if (current_tssi < tssi_bounds[i])
4442                                 break;
4443                 }
4444         }
4445
4446         return (i - 4) * step;
4447 }
4448
4449 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
4450                                       enum nl80211_band band)
4451 {
4452         u16 eeprom;
4453         u8 comp_en;
4454         u8 comp_type;
4455         int comp_value = 0;
4456
4457         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA);
4458
4459         /*
4460          * HT40 compensation not required.
4461          */
4462         if (eeprom == 0xffff ||
4463             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4464                 return 0;
4465
4466         if (band == NL80211_BAND_2GHZ) {
4467                 comp_en = rt2x00_get_field16(eeprom,
4468                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
4469                 if (comp_en) {
4470                         comp_type = rt2x00_get_field16(eeprom,
4471                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
4472                         comp_value = rt2x00_get_field16(eeprom,
4473                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
4474                         if (!comp_type)
4475                                 comp_value = -comp_value;
4476                 }
4477         } else {
4478                 comp_en = rt2x00_get_field16(eeprom,
4479                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
4480                 if (comp_en) {
4481                         comp_type = rt2x00_get_field16(eeprom,
4482                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
4483                         comp_value = rt2x00_get_field16(eeprom,
4484                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
4485                         if (!comp_type)
4486                                 comp_value = -comp_value;
4487                 }
4488         }
4489
4490         return comp_value;
4491 }
4492
4493 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4494                                         int power_level, int max_power)
4495 {
4496         int delta;
4497
4498         if (rt2x00_has_cap_power_limit(rt2x00dev))
4499                 return 0;
4500
4501         /*
4502          * XXX: We don't know the maximum transmit power of our hardware since
4503          * the EEPROM doesn't expose it. We only know that we are calibrated
4504          * to 100% tx power.
4505          *
4506          * Hence, we assume the regulatory limit that cfg80211 calulated for
4507          * the current channel is our maximum and if we are requested to lower
4508          * the value we just reduce our tx power accordingly.
4509          */
4510         delta = power_level - max_power;
4511         return min(delta, 0);
4512 }
4513
4514 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
4515                                    enum nl80211_band band, int power_level,
4516                                    u8 txpower, int delta)
4517 {
4518         u16 eeprom;
4519         u8 criterion;
4520         u8 eirp_txpower;
4521         u8 eirp_txpower_criterion;
4522         u8 reg_limit;
4523
4524         if (rt2x00_rt(rt2x00dev, RT3593))
4525                 return min_t(u8, txpower, 0xc);
4526
4527         if (rt2x00_rt(rt2x00dev, RT3883))
4528                 return min_t(u8, txpower, 0xf);
4529
4530         if (rt2x00_has_cap_power_limit(rt2x00dev)) {
4531                 /*
4532                  * Check if eirp txpower exceed txpower_limit.
4533                  * We use OFDM 6M as criterion and its eirp txpower
4534                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
4535                  * .11b data rate need add additional 4dbm
4536                  * when calculating eirp txpower.
4537                  */
4538                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4539                                                        EEPROM_TXPOWER_BYRATE,
4540                                                        1);
4541                 criterion = rt2x00_get_field16(eeprom,
4542                                                EEPROM_TXPOWER_BYRATE_RATE0);
4543
4544                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
4545
4546                 if (band == NL80211_BAND_2GHZ)
4547                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4548                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
4549                 else
4550                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4551                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
4552
4553                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
4554                                (is_rate_b ? 4 : 0) + delta;
4555
4556                 reg_limit = (eirp_txpower > power_level) ?
4557                                         (eirp_txpower - power_level) : 0;
4558         } else
4559                 reg_limit = 0;
4560
4561         txpower = max(0, txpower + delta - reg_limit);
4562         return min_t(u8, txpower, 0xc);
4563 }
4564
4565
4566 enum {
4567         TX_PWR_CFG_0_IDX,
4568         TX_PWR_CFG_1_IDX,
4569         TX_PWR_CFG_2_IDX,
4570         TX_PWR_CFG_3_IDX,
4571         TX_PWR_CFG_4_IDX,
4572         TX_PWR_CFG_5_IDX,
4573         TX_PWR_CFG_6_IDX,
4574         TX_PWR_CFG_7_IDX,
4575         TX_PWR_CFG_8_IDX,
4576         TX_PWR_CFG_9_IDX,
4577         TX_PWR_CFG_0_EXT_IDX,
4578         TX_PWR_CFG_1_EXT_IDX,
4579         TX_PWR_CFG_2_EXT_IDX,
4580         TX_PWR_CFG_3_EXT_IDX,
4581         TX_PWR_CFG_4_EXT_IDX,
4582         TX_PWR_CFG_IDX_COUNT,
4583 };
4584
4585 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4586                                          struct ieee80211_channel *chan,
4587                                          int power_level)
4588 {
4589         u8 txpower;
4590         u16 eeprom;
4591         u32 regs[TX_PWR_CFG_IDX_COUNT];
4592         unsigned int offset;
4593         enum nl80211_band band = chan->band;
4594         int delta;
4595         int i;
4596
4597         memset(regs, '\0', sizeof(regs));
4598
4599         /* TODO: adapt TX power reduction from the rt28xx code */
4600
4601         /* calculate temperature compensation delta */
4602         delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4603
4604         if (band == NL80211_BAND_5GHZ)
4605                 offset = 16;
4606         else
4607                 offset = 0;
4608
4609         if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4610                 offset += 8;
4611
4612         /* read the next four txpower values */
4613         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4614                                                offset);
4615
4616         /* CCK 1MBS,2MBS */
4617         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4618         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4619                                             txpower, delta);
4620         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4621                            TX_PWR_CFG_0_CCK1_CH0, txpower);
4622         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4623                            TX_PWR_CFG_0_CCK1_CH1, txpower);
4624         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4625                            TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
4626
4627         /* CCK 5.5MBS,11MBS */
4628         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4629         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4630                                             txpower, delta);
4631         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4632                            TX_PWR_CFG_0_CCK5_CH0, txpower);
4633         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4634                            TX_PWR_CFG_0_CCK5_CH1, txpower);
4635         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4636                            TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
4637
4638         /* OFDM 6MBS,9MBS */
4639         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4640         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4641                                             txpower, delta);
4642         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4643                            TX_PWR_CFG_0_OFDM6_CH0, txpower);
4644         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4645                            TX_PWR_CFG_0_OFDM6_CH1, txpower);
4646         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4647                            TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
4648
4649         /* OFDM 12MBS,18MBS */
4650         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4651         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4652                                             txpower, delta);
4653         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4654                            TX_PWR_CFG_0_OFDM12_CH0, txpower);
4655         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4656                            TX_PWR_CFG_0_OFDM12_CH1, txpower);
4657         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4658                            TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
4659
4660         /* read the next four txpower values */
4661         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4662                                                offset + 1);
4663
4664         /* OFDM 24MBS,36MBS */
4665         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4666         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4667                                             txpower, delta);
4668         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4669                            TX_PWR_CFG_1_OFDM24_CH0, txpower);
4670         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4671                            TX_PWR_CFG_1_OFDM24_CH1, txpower);
4672         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4673                            TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
4674
4675         /* OFDM 48MBS */
4676         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4677         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4678                                             txpower, delta);
4679         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4680                            TX_PWR_CFG_1_OFDM48_CH0, txpower);
4681         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4682                            TX_PWR_CFG_1_OFDM48_CH1, txpower);
4683         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4684                            TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
4685
4686         /* OFDM 54MBS */
4687         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4688         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4689                                             txpower, delta);
4690         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4691                            TX_PWR_CFG_7_OFDM54_CH0, txpower);
4692         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4693                            TX_PWR_CFG_7_OFDM54_CH1, txpower);
4694         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4695                            TX_PWR_CFG_7_OFDM54_CH2, txpower);
4696
4697         /* read the next four txpower values */
4698         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4699                                                offset + 2);
4700
4701         /* MCS 0,1 */
4702         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4703         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4704                                             txpower, delta);
4705         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4706                            TX_PWR_CFG_1_MCS0_CH0, txpower);
4707         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4708                            TX_PWR_CFG_1_MCS0_CH1, txpower);
4709         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4710                            TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
4711
4712         /* MCS 2,3 */
4713         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4714         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4715                                             txpower, delta);
4716         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4717                            TX_PWR_CFG_1_MCS2_CH0, txpower);
4718         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4719                            TX_PWR_CFG_1_MCS2_CH1, txpower);
4720         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4721                            TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
4722
4723         /* MCS 4,5 */
4724         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4725         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4726                                             txpower, delta);
4727         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4728                            TX_PWR_CFG_2_MCS4_CH0, txpower);
4729         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4730                            TX_PWR_CFG_2_MCS4_CH1, txpower);
4731         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4732                            TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
4733
4734         /* MCS 6 */
4735         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4736         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4737                                             txpower, delta);
4738         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4739                            TX_PWR_CFG_2_MCS6_CH0, txpower);
4740         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4741                            TX_PWR_CFG_2_MCS6_CH1, txpower);
4742         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4743                            TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
4744
4745         /* read the next four txpower values */
4746         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4747                                                offset + 3);
4748
4749         /* MCS 7 */
4750         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4751         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4752                                             txpower, delta);
4753         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4754                            TX_PWR_CFG_7_MCS7_CH0, txpower);
4755         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4756                            TX_PWR_CFG_7_MCS7_CH1, txpower);
4757         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4758                            TX_PWR_CFG_7_MCS7_CH2, txpower);
4759
4760         /* MCS 8,9 */
4761         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4762         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4763                                             txpower, delta);
4764         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4765                            TX_PWR_CFG_2_MCS8_CH0, txpower);
4766         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4767                            TX_PWR_CFG_2_MCS8_CH1, txpower);
4768         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4769                            TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
4770
4771         /* MCS 10,11 */
4772         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4773         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4774                                             txpower, delta);
4775         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4776                            TX_PWR_CFG_2_MCS10_CH0, txpower);
4777         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4778                            TX_PWR_CFG_2_MCS10_CH1, txpower);
4779         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4780                            TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
4781
4782         /* MCS 12,13 */
4783         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4784         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4785                                             txpower, delta);
4786         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4787                            TX_PWR_CFG_3_MCS12_CH0, txpower);
4788         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4789                            TX_PWR_CFG_3_MCS12_CH1, txpower);
4790         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4791                            TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
4792
4793         /* read the next four txpower values */
4794         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4795                                                offset + 4);
4796
4797         /* MCS 14 */
4798         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4799         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4800                                             txpower, delta);
4801         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4802                            TX_PWR_CFG_3_MCS14_CH0, txpower);
4803         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4804                            TX_PWR_CFG_3_MCS14_CH1, txpower);
4805         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4806                            TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
4807
4808         /* MCS 15 */
4809         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4810         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4811                                             txpower, delta);
4812         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4813                            TX_PWR_CFG_8_MCS15_CH0, txpower);
4814         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4815                            TX_PWR_CFG_8_MCS15_CH1, txpower);
4816         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4817                            TX_PWR_CFG_8_MCS15_CH2, txpower);
4818
4819         /* MCS 16,17 */
4820         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4821         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4822                                             txpower, delta);
4823         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4824                            TX_PWR_CFG_5_MCS16_CH0, txpower);
4825         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4826                            TX_PWR_CFG_5_MCS16_CH1, txpower);
4827         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4828                            TX_PWR_CFG_5_MCS16_CH2, txpower);
4829
4830         /* MCS 18,19 */
4831         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4832         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4833                                             txpower, delta);
4834         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4835                            TX_PWR_CFG_5_MCS18_CH0, txpower);
4836         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4837                            TX_PWR_CFG_5_MCS18_CH1, txpower);
4838         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4839                            TX_PWR_CFG_5_MCS18_CH2, txpower);
4840
4841         /* read the next four txpower values */
4842         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4843                                                offset + 5);
4844
4845         /* MCS 20,21 */
4846         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4847         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4848                                             txpower, delta);
4849         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4850                            TX_PWR_CFG_6_MCS20_CH0, txpower);
4851         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4852                            TX_PWR_CFG_6_MCS20_CH1, txpower);
4853         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4854                            TX_PWR_CFG_6_MCS20_CH2, txpower);
4855
4856         /* MCS 22 */
4857         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4858         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4859                                             txpower, delta);
4860         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4861                            TX_PWR_CFG_6_MCS22_CH0, txpower);
4862         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4863                            TX_PWR_CFG_6_MCS22_CH1, txpower);
4864         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4865                            TX_PWR_CFG_6_MCS22_CH2, txpower);
4866
4867         /* MCS 23 */
4868         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4869         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4870                                             txpower, delta);
4871         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4872                            TX_PWR_CFG_8_MCS23_CH0, txpower);
4873         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4874                            TX_PWR_CFG_8_MCS23_CH1, txpower);
4875         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4876                            TX_PWR_CFG_8_MCS23_CH2, txpower);
4877
4878         /* read the next four txpower values */
4879         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4880                                                offset + 6);
4881
4882         /* STBC, MCS 0,1 */
4883         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4884         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4885                                             txpower, delta);
4886         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4887                            TX_PWR_CFG_3_STBC0_CH0, txpower);
4888         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4889                            TX_PWR_CFG_3_STBC0_CH1, txpower);
4890         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4891                            TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
4892
4893         /* STBC, MCS 2,3 */
4894         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4895         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4896                                             txpower, delta);
4897         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4898                            TX_PWR_CFG_3_STBC2_CH0, txpower);
4899         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4900                            TX_PWR_CFG_3_STBC2_CH1, txpower);
4901         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4902                            TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
4903
4904         /* STBC, MCS 4,5 */
4905         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4906         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4907                                             txpower, delta);
4908         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4909         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4910         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4911                            txpower);
4912
4913         /* STBC, MCS 6 */
4914         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4915         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4916                                             txpower, delta);
4917         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4918         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4919         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4920                            txpower);
4921
4922         /* read the next four txpower values */
4923         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4924                                                offset + 7);
4925
4926         /* STBC, MCS 7 */
4927         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4928         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4929                                             txpower, delta);
4930         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4931                            TX_PWR_CFG_9_STBC7_CH0, txpower);
4932         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4933                            TX_PWR_CFG_9_STBC7_CH1, txpower);
4934         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4935                            TX_PWR_CFG_9_STBC7_CH2, txpower);
4936
4937         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4938         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4939         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4940         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4941         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4942         rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4943         rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4944         rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4945         rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4946         rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4947
4948         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4949                               regs[TX_PWR_CFG_0_EXT_IDX]);
4950         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4951                               regs[TX_PWR_CFG_1_EXT_IDX]);
4952         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4953                               regs[TX_PWR_CFG_2_EXT_IDX]);
4954         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4955                               regs[TX_PWR_CFG_3_EXT_IDX]);
4956         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4957                               regs[TX_PWR_CFG_4_EXT_IDX]);
4958
4959         for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4960                 rt2x00_dbg(rt2x00dev,
4961                            "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4962                            (band == NL80211_BAND_5GHZ) ? '5' : '2',
4963                            (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4964                                                                 '4' : '2',
4965                            (i > TX_PWR_CFG_9_IDX) ?
4966                                         (i - TX_PWR_CFG_9_IDX - 1) : i,
4967                            (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4968                            (unsigned long) regs[i]);
4969 }
4970
4971 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
4972                                          struct ieee80211_channel *chan,
4973                                          int power_level)
4974 {
4975         u32 reg, pwreg;
4976         u16 eeprom;
4977         u32 data, gdata;
4978         u8 t, i;
4979         enum nl80211_band band = chan->band;
4980         int delta;
4981
4982         /* Warn user if bw_comp is set in EEPROM */
4983         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4984
4985         if (delta)
4986                 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
4987                             delta);
4988
4989         /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
4990          * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
4991          * driver does as well, though it looks kinda wrong.
4992          * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
4993          * the hardware has a problem handling 0x20, and as the code initially
4994          * used a fixed offset between HT20 and HT40 rates they had to work-
4995          * around that issue and most likely just forgot about it later on.
4996          * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
4997          * however, the corresponding EEPROM value is not respected by the
4998          * vendor driver, so maybe this is rather being taken care of the
4999          * TXALC and the driver doesn't need to handle it...?
5000          * Though this is all very awkward, just do as they did, as that's what
5001          * board vendors expected when they populated the EEPROM...
5002          */
5003         for (i = 0; i < 5; i++) {
5004                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5005                                                        EEPROM_TXPOWER_BYRATE,
5006                                                        i * 2);
5007
5008                 data = eeprom;
5009
5010                 t = eeprom & 0x3f;
5011                 if (t == 32)
5012                         t++;
5013
5014                 gdata = t;
5015
5016                 t = (eeprom & 0x3f00) >> 8;
5017                 if (t == 32)
5018                         t++;
5019
5020                 gdata |= (t << 8);
5021
5022                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5023                                                        EEPROM_TXPOWER_BYRATE,
5024                                                        (i * 2) + 1);
5025
5026                 t = eeprom & 0x3f;
5027                 if (t == 32)
5028                         t++;
5029
5030                 gdata |= (t << 16);
5031
5032                 t = (eeprom & 0x3f00) >> 8;
5033                 if (t == 32)
5034                         t++;
5035
5036                 gdata |= (t << 24);
5037                 data |= (eeprom << 16);
5038
5039                 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
5040                         /* HT20 */
5041                         if (data != 0xffffffff)
5042                                 rt2800_register_write(rt2x00dev,
5043                                                       TX_PWR_CFG_0 + (i * 4),
5044                                                       data);
5045                 } else {
5046                         /* HT40 */
5047                         if (gdata != 0xffffffff)
5048                                 rt2800_register_write(rt2x00dev,
5049                                                       TX_PWR_CFG_0 + (i * 4),
5050                                                       gdata);
5051                 }
5052         }
5053
5054         /* Aparently Ralink ran out of space in the BYRATE calibration section
5055          * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
5056          * registers. As recent 2T chips use 8-bit instead of 4-bit values for
5057          * power-offsets more space would be needed. Ralink decided to keep the
5058          * EEPROM layout untouched and rather have some shared values covering
5059          * multiple bitrates.
5060          * Populate the registers not covered by the EEPROM in the same way the
5061          * vendor driver does.
5062          */
5063
5064         /* For OFDM 54MBS use value from OFDM 48MBS */
5065         pwreg = 0;
5066         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1);
5067         t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
5068         rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
5069
5070         /* For MCS 7 use value from MCS 6 */
5071         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2);
5072         t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
5073         rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
5074         rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
5075
5076         /* For MCS 15 use value from MCS 14 */
5077         pwreg = 0;
5078         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3);
5079         t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
5080         rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
5081         rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
5082
5083         /* For STBC MCS 7 use value from STBC MCS 6 */
5084         pwreg = 0;
5085         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4);
5086         t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
5087         rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
5088         rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
5089
5090         rt2800_config_alc(rt2x00dev, chan, power_level);
5091
5092         /* TODO: temperature compensation code! */
5093 }
5094
5095 /*
5096  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
5097  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
5098  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
5099  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
5100  * Reference per rate transmit power values are located in the EEPROM at
5101  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
5102  * current conditions (i.e. band, bandwidth, temperature, user settings).
5103  */
5104 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
5105                                          struct ieee80211_channel *chan,
5106                                          int power_level)
5107 {
5108         u8 txpower, r1;
5109         u16 eeprom;
5110         u32 reg, offset;
5111         int i, is_rate_b, delta, power_ctrl;
5112         enum nl80211_band band = chan->band;
5113
5114         /*
5115          * Calculate HT40 compensation. For 40MHz we need to add or subtract
5116          * value read from EEPROM (different for 2GHz and for 5GHz).
5117          */
5118         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5119
5120         /*
5121          * Calculate temperature compensation. Depends on measurement of current
5122          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
5123          * to temperature or maybe other factors) is smaller or bigger than
5124          * expected. We adjust it, based on TSSI reference and boundaries values
5125          * provided in EEPROM.
5126          */
5127         switch (rt2x00dev->chip.rt) {
5128         case RT2860:
5129         case RT2872:
5130         case RT2883:
5131         case RT3070:
5132         case RT3071:
5133         case RT3090:
5134         case RT3572:
5135                 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
5136                 break;
5137         default:
5138                 /* TODO: temperature compensation code for other chips. */
5139                 break;
5140         }
5141
5142         /*
5143          * Decrease power according to user settings, on devices with unknown
5144          * maximum tx power. For other devices we take user power_level into
5145          * consideration on rt2800_compensate_txpower().
5146          */
5147         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
5148                                               chan->max_power);
5149
5150         /*
5151          * BBP_R1 controls TX power for all rates, it allow to set the following
5152          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
5153          *
5154          * TODO: we do not use +6 dBm option to do not increase power beyond
5155          * regulatory limit, however this could be utilized for devices with
5156          * CAPABILITY_POWER_LIMIT.
5157          */
5158         if (delta <= -12) {
5159                 power_ctrl = 2;
5160                 delta += 12;
5161         } else if (delta <= -6) {
5162                 power_ctrl = 1;
5163                 delta += 6;
5164         } else {
5165                 power_ctrl = 0;
5166         }
5167         r1 = rt2800_bbp_read(rt2x00dev, 1);
5168         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
5169         rt2800_bbp_write(rt2x00dev, 1, r1);
5170
5171         offset = TX_PWR_CFG_0;
5172
5173         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
5174                 /* just to be safe */
5175                 if (offset > TX_PWR_CFG_4)
5176                         break;
5177
5178                 reg = rt2800_register_read(rt2x00dev, offset);
5179
5180                 /* read the next four txpower values */
5181                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5182                                                        EEPROM_TXPOWER_BYRATE,
5183                                                        i);
5184
5185                 is_rate_b = i ? 0 : 1;
5186                 /*
5187                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5188                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
5189                  * TX_PWR_CFG_4: unknown
5190                  */
5191                 txpower = rt2x00_get_field16(eeprom,
5192                                              EEPROM_TXPOWER_BYRATE_RATE0);
5193                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5194                                              power_level, txpower, delta);
5195                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5196
5197                 /*
5198                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5199                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
5200                  * TX_PWR_CFG_4: unknown
5201                  */
5202                 txpower = rt2x00_get_field16(eeprom,
5203                                              EEPROM_TXPOWER_BYRATE_RATE1);
5204                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5205                                              power_level, txpower, delta);
5206                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5207
5208                 /*
5209                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5210                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
5211                  * TX_PWR_CFG_4: unknown
5212                  */
5213                 txpower = rt2x00_get_field16(eeprom,
5214                                              EEPROM_TXPOWER_BYRATE_RATE2);
5215                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5216                                              power_level, txpower, delta);
5217                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5218
5219                 /*
5220                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5221                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
5222                  * TX_PWR_CFG_4: unknown
5223                  */
5224                 txpower = rt2x00_get_field16(eeprom,
5225                                              EEPROM_TXPOWER_BYRATE_RATE3);
5226                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5227                                              power_level, txpower, delta);
5228                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5229
5230                 /* read the next four txpower values */
5231                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5232                                                        EEPROM_TXPOWER_BYRATE,
5233                                                        i + 1);
5234
5235                 is_rate_b = 0;
5236                 /*
5237                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5238                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
5239                  * TX_PWR_CFG_4: unknown
5240                  */
5241                 txpower = rt2x00_get_field16(eeprom,
5242                                              EEPROM_TXPOWER_BYRATE_RATE0);
5243                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5244                                              power_level, txpower, delta);
5245                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5246
5247                 /*
5248                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5249                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
5250                  * TX_PWR_CFG_4: unknown
5251                  */
5252                 txpower = rt2x00_get_field16(eeprom,
5253                                              EEPROM_TXPOWER_BYRATE_RATE1);
5254                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5255                                              power_level, txpower, delta);
5256                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5257
5258                 /*
5259                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5260                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
5261                  * TX_PWR_CFG_4: unknown
5262                  */
5263                 txpower = rt2x00_get_field16(eeprom,
5264                                              EEPROM_TXPOWER_BYRATE_RATE2);
5265                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5266                                              power_level, txpower, delta);
5267                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5268
5269                 /*
5270                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5271                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
5272                  * TX_PWR_CFG_4: unknown
5273                  */
5274                 txpower = rt2x00_get_field16(eeprom,
5275                                              EEPROM_TXPOWER_BYRATE_RATE3);
5276                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5277                                              power_level, txpower, delta);
5278                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5279
5280                 rt2800_register_write(rt2x00dev, offset, reg);
5281
5282                 /* next TX_PWR_CFG register */
5283                 offset += 4;
5284         }
5285 }
5286
5287 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5288                                   struct ieee80211_channel *chan,
5289                                   int power_level)
5290 {
5291         if (rt2x00_rt(rt2x00dev, RT3593) ||
5292             rt2x00_rt(rt2x00dev, RT3883))
5293                 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
5294         else if (rt2x00_rt(rt2x00dev, RT6352))
5295                 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
5296         else
5297                 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
5298 }
5299
5300 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
5301 {
5302         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
5303                               rt2x00dev->tx_power);
5304 }
5305 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
5306
5307 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
5308 {
5309         u32     tx_pin;
5310         u8      rfcsr;
5311         unsigned long min_sleep = 0;
5312
5313         /*
5314          * A voltage-controlled oscillator(VCO) is an electronic oscillator
5315          * designed to be controlled in oscillation frequency by a voltage
5316          * input. Maybe the temperature will affect the frequency of
5317          * oscillation to be shifted. The VCO calibration will be called
5318          * periodically to adjust the frequency to be precision.
5319         */
5320
5321         tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5322         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
5323         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5324
5325         switch (rt2x00dev->chip.rf) {
5326         case RF2020:
5327         case RF3020:
5328         case RF3021:
5329         case RF3022:
5330         case RF3320:
5331         case RF3052:
5332                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
5333                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
5334                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
5335                 break;
5336         case RF3053:
5337         case RF3070:
5338         case RF3290:
5339         case RF3853:
5340         case RF5350:
5341         case RF5360:
5342         case RF5362:
5343         case RF5370:
5344         case RF5372:
5345         case RF5390:
5346         case RF5392:
5347         case RF5592:
5348                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
5349                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
5350                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
5351                 min_sleep = 1000;
5352                 break;
5353         case RF7620:
5354                 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
5355                 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
5356                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
5357                 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
5358                 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
5359                 min_sleep = 2000;
5360                 break;
5361         default:
5362                 WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration",
5363                           rt2x00dev->chip.rf);
5364                 return;
5365         }
5366
5367         if (min_sleep > 0)
5368                 usleep_range(min_sleep, min_sleep * 2);
5369
5370         tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5371         if (rt2x00dev->rf_channel <= 14) {
5372                 switch (rt2x00dev->default_ant.tx_chain_num) {
5373                 case 3:
5374                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
5375                         /* fall through */
5376                 case 2:
5377                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
5378                         /* fall through */
5379                 case 1:
5380                 default:
5381                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
5382                         break;
5383                 }
5384         } else {
5385                 switch (rt2x00dev->default_ant.tx_chain_num) {
5386                 case 3:
5387                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
5388                         /* fall through */
5389                 case 2:
5390                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
5391                         /* fall through */
5392                 case 1:
5393                 default:
5394                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
5395                         break;
5396                 }
5397         }
5398         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5399
5400         if (rt2x00_rt(rt2x00dev, RT6352)) {
5401                 if (rt2x00dev->default_ant.rx_chain_num == 1) {
5402                         rt2800_bbp_write(rt2x00dev, 91, 0x07);
5403                         rt2800_bbp_write(rt2x00dev, 95, 0x1A);
5404                         rt2800_bbp_write(rt2x00dev, 195, 128);
5405                         rt2800_bbp_write(rt2x00dev, 196, 0xA0);
5406                         rt2800_bbp_write(rt2x00dev, 195, 170);
5407                         rt2800_bbp_write(rt2x00dev, 196, 0x12);
5408                         rt2800_bbp_write(rt2x00dev, 195, 171);
5409                         rt2800_bbp_write(rt2x00dev, 196, 0x10);
5410                 } else {
5411                         rt2800_bbp_write(rt2x00dev, 91, 0x06);
5412                         rt2800_bbp_write(rt2x00dev, 95, 0x9A);
5413                         rt2800_bbp_write(rt2x00dev, 195, 128);
5414                         rt2800_bbp_write(rt2x00dev, 196, 0xE0);
5415                         rt2800_bbp_write(rt2x00dev, 195, 170);
5416                         rt2800_bbp_write(rt2x00dev, 196, 0x30);
5417                         rt2800_bbp_write(rt2x00dev, 195, 171);
5418                         rt2800_bbp_write(rt2x00dev, 196, 0x30);
5419                 }
5420
5421                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
5422                         rt2800_bbp_write(rt2x00dev, 75, 0x68);
5423                         rt2800_bbp_write(rt2x00dev, 76, 0x4C);
5424                         rt2800_bbp_write(rt2x00dev, 79, 0x1C);
5425                         rt2800_bbp_write(rt2x00dev, 80, 0x0C);
5426                         rt2800_bbp_write(rt2x00dev, 82, 0xB6);
5427                 }
5428
5429                 /* On 11A, We should delay and wait RF/BBP to be stable
5430                  * and the appropriate time should be 1000 micro seconds
5431                  * 2005/06/05 - On 11G, we also need this delay time.
5432                  * Otherwise it's difficult to pass the WHQL.
5433                  */
5434                 usleep_range(1000, 1500);
5435         }
5436 }
5437 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
5438
5439 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5440                                       struct rt2x00lib_conf *libconf)
5441 {
5442         u32 reg;
5443
5444         reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5445         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
5446                            libconf->conf->short_frame_max_tx_count);
5447         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
5448                            libconf->conf->long_frame_max_tx_count);
5449         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5450 }
5451
5452 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
5453                              struct rt2x00lib_conf *libconf)
5454 {
5455         enum dev_state state =
5456             (libconf->conf->flags & IEEE80211_CONF_PS) ?
5457                 STATE_SLEEP : STATE_AWAKE;
5458         u32 reg;
5459
5460         if (state == STATE_SLEEP) {
5461                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
5462
5463                 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5464                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
5465                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
5466                                    libconf->conf->listen_interval - 1);
5467                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
5468                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5469
5470                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5471         } else {
5472                 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5473                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
5474                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
5475                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
5476                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5477
5478                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5479         }
5480 }
5481
5482 void rt2800_config(struct rt2x00_dev *rt2x00dev,
5483                    struct rt2x00lib_conf *libconf,
5484                    const unsigned int flags)
5485 {
5486         /* Always recalculate LNA gain before changing configuration */
5487         rt2800_config_lna_gain(rt2x00dev, libconf);
5488
5489         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
5490                 rt2800_config_channel(rt2x00dev, libconf->conf,
5491                                       &libconf->rf, &libconf->channel);
5492                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5493                                       libconf->conf->power_level);
5494         }
5495         if (flags & IEEE80211_CONF_CHANGE_POWER)
5496                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5497                                       libconf->conf->power_level);
5498         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
5499                 rt2800_config_retry_limit(rt2x00dev, libconf);
5500         if (flags & IEEE80211_CONF_CHANGE_PS)
5501                 rt2800_config_ps(rt2x00dev, libconf);
5502 }
5503 EXPORT_SYMBOL_GPL(rt2800_config);
5504
5505 /*
5506  * Link tuning
5507  */
5508 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5509 {
5510         u32 reg;
5511
5512         /*
5513          * Update FCS error count from register.
5514          */
5515         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5516         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5517 }
5518 EXPORT_SYMBOL_GPL(rt2800_link_stats);
5519
5520 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5521 {
5522         u8 vgc;
5523
5524         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
5525                 if (rt2x00_rt(rt2x00dev, RT3070) ||
5526                     rt2x00_rt(rt2x00dev, RT3071) ||
5527                     rt2x00_rt(rt2x00dev, RT3090) ||
5528                     rt2x00_rt(rt2x00dev, RT3290) ||
5529                     rt2x00_rt(rt2x00dev, RT3390) ||
5530                     rt2x00_rt(rt2x00dev, RT3572) ||
5531                     rt2x00_rt(rt2x00dev, RT3593) ||
5532                     rt2x00_rt(rt2x00dev, RT5390) ||
5533                     rt2x00_rt(rt2x00dev, RT5392) ||
5534                     rt2x00_rt(rt2x00dev, RT5592) ||
5535                     rt2x00_rt(rt2x00dev, RT6352))
5536                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5537                 else
5538                         vgc = 0x2e + rt2x00dev->lna_gain;
5539         } else { /* 5GHZ band */
5540                 if (rt2x00_rt(rt2x00dev, RT3593) ||
5541                     rt2x00_rt(rt2x00dev, RT3883))
5542                         vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
5543                 else if (rt2x00_rt(rt2x00dev, RT5592))
5544                         vgc = 0x24 + (2 * rt2x00dev->lna_gain);
5545                 else {
5546                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5547                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5548                         else
5549                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5550                 }
5551         }
5552
5553         return vgc;
5554 }
5555
5556 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5557                                   struct link_qual *qual, u8 vgc_level)
5558 {
5559         if (qual->vgc_level != vgc_level) {
5560                 if (rt2x00_rt(rt2x00dev, RT3572) ||
5561                     rt2x00_rt(rt2x00dev, RT3593) ||
5562                     rt2x00_rt(rt2x00dev, RT3883)) {
5563                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5564                                                        vgc_level);
5565                 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5566                         rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5567                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
5568                 } else {
5569                         rt2800_bbp_write(rt2x00dev, 66, vgc_level);
5570                 }
5571
5572                 qual->vgc_level = vgc_level;
5573                 qual->vgc_level_reg = vgc_level;
5574         }
5575 }
5576
5577 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5578 {
5579         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5580 }
5581 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
5582
5583 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5584                        const u32 count)
5585 {
5586         u8 vgc;
5587
5588         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
5589                 return;
5590
5591         /* When RSSI is better than a certain threshold, increase VGC
5592          * with a chip specific value in order to improve the balance
5593          * between sensibility and noise isolation.
5594          */
5595
5596         vgc = rt2800_get_default_vgc(rt2x00dev);
5597
5598         switch (rt2x00dev->chip.rt) {
5599         case RT3572:
5600         case RT3593:
5601                 if (qual->rssi > -65) {
5602                         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
5603                                 vgc += 0x20;
5604                         else
5605                                 vgc += 0x10;
5606                 }
5607                 break;
5608
5609         case RT3883:
5610                 if (qual->rssi > -65)
5611                         vgc += 0x10;
5612                 break;
5613
5614         case RT5592:
5615                 if (qual->rssi > -65)
5616                         vgc += 0x20;
5617                 break;
5618
5619         default:
5620                 if (qual->rssi > -80)
5621                         vgc += 0x10;
5622                 break;
5623         }
5624
5625         rt2800_set_vgc(rt2x00dev, qual, vgc);
5626 }
5627 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
5628
5629 /*
5630  * Initialization functions.
5631  */
5632 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
5633 {
5634         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5635         u32 reg;
5636         u16 eeprom;
5637         unsigned int i;
5638         int ret;
5639
5640         rt2800_disable_wpdma(rt2x00dev);
5641
5642         ret = rt2800_drv_init_registers(rt2x00dev);
5643         if (ret)
5644                 return ret;
5645
5646         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5647         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5648
5649         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5650
5651         reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
5652         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
5653         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
5654         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
5655         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
5656         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
5657         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
5658         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5659
5660         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5661
5662         reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
5663         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
5664         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
5665         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5666
5667         if (rt2x00_rt(rt2x00dev, RT3290)) {
5668                 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
5669                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
5670                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
5671                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5672                 }
5673
5674                 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
5675                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
5676                         rt2x00_set_field32(&reg, LDO0_EN, 1);
5677                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
5678                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5679                 }
5680
5681                 reg = rt2800_register_read(rt2x00dev, OSC_CTRL);
5682                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
5683                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
5684                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
5685                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5686
5687                 reg = rt2800_register_read(rt2x00dev, COEX_CFG0);
5688                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
5689                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5690
5691                 reg = rt2800_register_read(rt2x00dev, COEX_CFG2);
5692                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
5693                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
5694                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
5695                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
5696                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5697
5698                 reg = rt2800_register_read(rt2x00dev, PLL_CTRL);
5699                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
5700                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5701         }
5702
5703         if (rt2x00_rt(rt2x00dev, RT3071) ||
5704             rt2x00_rt(rt2x00dev, RT3090) ||
5705             rt2x00_rt(rt2x00dev, RT3290) ||
5706             rt2x00_rt(rt2x00dev, RT3390)) {
5707
5708                 if (rt2x00_rt(rt2x00dev, RT3290))
5709                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5710                                               0x00000404);
5711                 else
5712                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5713                                               0x00000400);
5714
5715                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5716                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5717                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5718                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5719                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5720                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5721                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5722                                                       0x0000002c);
5723                         else
5724                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5725                                                       0x0000000f);
5726                 } else {
5727                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5728                 }
5729         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
5730                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5731
5732                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5733                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5734                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5735                 } else {
5736                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5737                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5738                 }
5739         } else if (rt2800_is_305x_soc(rt2x00dev)) {
5740                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5741                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5742                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
5743         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
5744                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5745                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5746                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5747         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
5748                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5749                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5750         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
5751                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5752                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5753                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5754                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5755                         if (rt2x00_get_field16(eeprom,
5756                                                EEPROM_NIC_CONF1_DAC_TEST))
5757                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5758                                                       0x0000001f);
5759                         else
5760                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5761                                                       0x0000000f);
5762                 } else {
5763                         rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5764                                               0x00000000);
5765                 }
5766         } else if (rt2x00_rt(rt2x00dev, RT3883)) {
5767                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5768                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5769                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000);
5770                 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21);
5771                 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40);
5772         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
5773                    rt2x00_rt(rt2x00dev, RT5392) ||
5774                    rt2x00_rt(rt2x00dev, RT6352)) {
5775                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5776                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5777                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5778         } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5779                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5780                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5781                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5782         } else if (rt2x00_rt(rt2x00dev, RT5350)) {
5783                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5784         } else if (rt2x00_rt(rt2x00dev, RT6352)) {
5785                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
5786                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
5787                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5788                 rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002);
5789                 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F);
5790                 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
5791                 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
5792                 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
5793                 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
5794                 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
5795                 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
5796                                       0x3630363A);
5797                 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
5798                                       0x3630363A);
5799                 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
5800                 rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
5801                 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
5802         } else {
5803                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
5804                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5805         }
5806
5807         reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG);
5808         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
5809         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
5810         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
5811         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
5812         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
5813         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
5814         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
5815         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
5816         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
5817
5818         reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG);
5819         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
5820         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
5821         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
5822         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5823
5824         reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
5825         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
5826         if (rt2x00_is_usb(rt2x00dev)) {
5827                 drv_data->max_psdu = 3;
5828         } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
5829                    rt2x00_rt(rt2x00dev, RT2883) ||
5830                    rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
5831                 drv_data->max_psdu = 2;
5832         } else {
5833                 drv_data->max_psdu = 1;
5834         }
5835         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu);
5836         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 10);
5837         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 10);
5838         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
5839
5840         reg = rt2800_register_read(rt2x00dev, LED_CFG);
5841         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
5842         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
5843         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
5844         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
5845         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
5846         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
5847         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
5848         rt2800_register_write(rt2x00dev, LED_CFG, reg);
5849
5850         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
5851
5852         reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5853         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 2);
5854         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 2);
5855         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
5856         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
5857         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
5858         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
5859         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5860
5861         reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
5862         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
5863         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
5864         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 1);
5865         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
5866         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 0);
5867         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
5868         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
5869         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5870
5871         reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
5872         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
5873         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
5874         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
5875         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5876         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5877         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5878         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5879         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5880         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5881         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
5882         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5883
5884         reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
5885         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
5886         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
5887         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
5888         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5889         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5890         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5891         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5892         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5893         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5894         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
5895         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5896
5897         reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
5898         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
5899         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 1);
5900         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5901         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5902         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5903         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5904         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5905         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5906         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5907         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
5908         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5909
5910         reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
5911         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
5912         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 1);
5913         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
5914         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5915         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5916         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5917         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5918         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5919         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5920         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
5921         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5922
5923         reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
5924         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
5925         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 1);
5926         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5927         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5928         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5929         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5930         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5931         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5932         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5933         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
5934         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
5935
5936         reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
5937         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
5938         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 1);
5939         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
5940         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5941         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5942         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5943         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5944         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5945         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5946         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
5947         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
5948
5949         if (rt2x00_is_usb(rt2x00dev)) {
5950                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
5951
5952                 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
5953                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
5954                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
5955                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
5956                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
5957                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
5958                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
5959                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
5960                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
5961                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
5962                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5963         }
5964
5965         /*
5966          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
5967          * although it is reserved.
5968          */
5969         reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG);
5970         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
5971         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
5972         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
5973         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
5974         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
5975         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
5976         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
5977         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
5978         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
5979         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
5980         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
5981
5982         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
5983         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
5984
5985         if (rt2x00_rt(rt2x00dev, RT3883)) {
5986                 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008);
5987                 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413);
5988         }
5989
5990         reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
5991         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
5992         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
5993                            IEEE80211_MAX_RTS_THRESHOLD);
5994         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 1);
5995         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
5996
5997         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
5998
5999         /*
6000          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
6001          * time should be set to 16. However, the original Ralink driver uses
6002          * 16 for both and indeed using a value of 10 for CCK SIFS results in
6003          * connection problems with 11g + CTS protection. Hence, use the same
6004          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
6005          */
6006         reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
6007         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
6008         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
6009         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
6010         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
6011         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
6012         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
6013
6014         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
6015
6016         /*
6017          * ASIC will keep garbage value after boot, clear encryption keys.
6018          */
6019         for (i = 0; i < 4; i++)
6020                 rt2800_register_write(rt2x00dev,
6021                                          SHARED_KEY_MODE_ENTRY(i), 0);
6022
6023         for (i = 0; i < 256; i++) {
6024                 rt2800_config_wcid(rt2x00dev, NULL, i);
6025                 rt2800_delete_wcid_attr(rt2x00dev, i);
6026                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
6027         }
6028
6029         /*
6030          * Clear all beacons
6031          */
6032         for (i = 0; i < 8; i++)
6033                 rt2800_clear_beacon_register(rt2x00dev, i);
6034
6035         if (rt2x00_is_usb(rt2x00dev)) {
6036                 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6037                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
6038                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6039         } else if (rt2x00_is_pcie(rt2x00dev)) {
6040                 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6041                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
6042                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6043         }
6044
6045         reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
6046         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
6047         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
6048         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
6049         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
6050         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
6051         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
6052         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
6053         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
6054         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
6055
6056         reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1);
6057         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
6058         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
6059         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
6060         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
6061         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
6062         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
6063         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
6064         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
6065         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
6066
6067         reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0);
6068         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
6069         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
6070         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
6071         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
6072         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
6073         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
6074         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
6075         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
6076         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
6077
6078         reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1);
6079         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
6080         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
6081         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
6082         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
6083         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
6084
6085         /*
6086          * Do not force the BA window size, we use the TXWI to set it
6087          */
6088         reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE);
6089         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
6090         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
6091         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
6092
6093         /*
6094          * We must clear the error counters.
6095          * These registers are cleared on read,
6096          * so we may pass a useless variable to store the value.
6097          */
6098         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
6099         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1);
6100         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2);
6101         reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0);
6102         reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1);
6103         reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2);
6104
6105         /*
6106          * Setup leadtime for pre tbtt interrupt to 6ms
6107          */
6108         reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG);
6109         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
6110         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
6111
6112         /*
6113          * Set up channel statistics timer
6114          */
6115         reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG);
6116         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
6117         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
6118         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
6119         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
6120         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
6121         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
6122
6123         return 0;
6124 }
6125
6126 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
6127 {
6128         unsigned int i;
6129         u32 reg;
6130
6131         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
6132                 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
6133                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
6134                         return 0;
6135
6136                 udelay(REGISTER_BUSY_DELAY);
6137         }
6138
6139         rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
6140         return -EACCES;
6141 }
6142
6143 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
6144 {
6145         unsigned int i;
6146         u8 value;
6147
6148         /*
6149          * BBP was enabled after firmware was loaded,
6150          * but we need to reactivate it now.
6151          */
6152         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6153         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6154         msleep(1);
6155
6156         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
6157                 value = rt2800_bbp_read(rt2x00dev, 0);
6158                 if ((value != 0xff) && (value != 0x00))
6159                         return 0;
6160                 udelay(REGISTER_BUSY_DELAY);
6161         }
6162
6163         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
6164         return -EACCES;
6165 }
6166
6167 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
6168 {
6169         u8 value;
6170
6171         value = rt2800_bbp_read(rt2x00dev, 4);
6172         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
6173         rt2800_bbp_write(rt2x00dev, 4, value);
6174 }
6175
6176 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
6177 {
6178         rt2800_bbp_write(rt2x00dev, 142, 1);
6179         rt2800_bbp_write(rt2x00dev, 143, 57);
6180 }
6181
6182 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
6183 {
6184         static const u8 glrt_table[] = {
6185                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
6186                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
6187                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
6188                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
6189                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
6190                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
6191                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
6192                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
6193                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
6194         };
6195         int i;
6196
6197         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
6198                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
6199                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
6200         }
6201 };
6202
6203 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
6204 {
6205         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6206         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6207         rt2800_bbp_write(rt2x00dev, 68, 0x0B);
6208         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6209         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6210         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6211         rt2800_bbp_write(rt2x00dev, 81, 0x37);
6212         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6213         rt2800_bbp_write(rt2x00dev, 83, 0x6A);
6214         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6215         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6216         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6217         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6218         rt2800_bbp_write(rt2x00dev, 103, 0x00);
6219         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6220         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6221 }
6222
6223 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
6224 {
6225         u16 eeprom;
6226         u8 value;
6227
6228         value = rt2800_bbp_read(rt2x00dev, 138);
6229         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6230         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6231                 value |= 0x20;
6232         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6233                 value &= ~0x02;
6234         rt2800_bbp_write(rt2x00dev, 138, value);
6235 }
6236
6237 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
6238 {
6239         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6240
6241         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6242         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6243
6244         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6245         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6246
6247         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6248
6249         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6250         rt2800_bbp_write(rt2x00dev, 80, 0x08);
6251
6252         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6253
6254         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6255
6256         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6257
6258         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6259
6260         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6261
6262         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6263
6264         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6265
6266         rt2800_bbp_write(rt2x00dev, 105, 0x01);
6267
6268         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6269 }
6270
6271 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
6272 {
6273         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6274         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6275
6276         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
6277                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
6278                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
6279         } else {
6280                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6281                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6282         }
6283
6284         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6285
6286         rt2800_bbp_write(rt2x00dev, 81, 0x37);
6287
6288         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6289
6290         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6291
6292         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
6293                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6294         else
6295                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6296
6297         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6298
6299         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6300
6301         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6302
6303         rt2800_bbp_write(rt2x00dev, 103, 0x00);
6304
6305         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6306
6307         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6308 }
6309
6310 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
6311 {
6312         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6313         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6314
6315         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6316         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6317
6318         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6319
6320         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6321         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6322         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6323
6324         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6325
6326         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6327
6328         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6329
6330         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6331
6332         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6333
6334         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6335
6336         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
6337             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
6338             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
6339                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6340         else
6341                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6342
6343         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6344
6345         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6346
6347         if (rt2x00_rt(rt2x00dev, RT3071) ||
6348             rt2x00_rt(rt2x00dev, RT3090))
6349                 rt2800_disable_unused_dac_adc(rt2x00dev);
6350 }
6351
6352 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
6353 {
6354         u8 value;
6355
6356         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6357
6358         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6359
6360         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6361         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6362
6363         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6364
6365         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6366         rt2800_bbp_write(rt2x00dev, 73, 0x13);
6367         rt2800_bbp_write(rt2x00dev, 75, 0x46);
6368         rt2800_bbp_write(rt2x00dev, 76, 0x28);
6369
6370         rt2800_bbp_write(rt2x00dev, 77, 0x58);
6371
6372         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6373
6374         rt2800_bbp_write(rt2x00dev, 74, 0x0b);
6375         rt2800_bbp_write(rt2x00dev, 79, 0x18);
6376         rt2800_bbp_write(rt2x00dev, 80, 0x09);
6377         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6378
6379         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6380
6381         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6382
6383         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6384
6385         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6386
6387         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6388
6389         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6390
6391         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6392
6393         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6394
6395         rt2800_bbp_write(rt2x00dev, 105, 0x1c);
6396
6397         rt2800_bbp_write(rt2x00dev, 106, 0x03);
6398
6399         rt2800_bbp_write(rt2x00dev, 128, 0x12);
6400
6401         rt2800_bbp_write(rt2x00dev, 67, 0x24);
6402         rt2800_bbp_write(rt2x00dev, 143, 0x04);
6403         rt2800_bbp_write(rt2x00dev, 142, 0x99);
6404         rt2800_bbp_write(rt2x00dev, 150, 0x30);
6405         rt2800_bbp_write(rt2x00dev, 151, 0x2e);
6406         rt2800_bbp_write(rt2x00dev, 152, 0x20);
6407         rt2800_bbp_write(rt2x00dev, 153, 0x34);
6408         rt2800_bbp_write(rt2x00dev, 154, 0x40);
6409         rt2800_bbp_write(rt2x00dev, 155, 0x3b);
6410         rt2800_bbp_write(rt2x00dev, 253, 0x04);
6411
6412         value = rt2800_bbp_read(rt2x00dev, 47);
6413         rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
6414         rt2800_bbp_write(rt2x00dev, 47, value);
6415
6416         /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
6417         value = rt2800_bbp_read(rt2x00dev, 3);
6418         rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
6419         rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
6420         rt2800_bbp_write(rt2x00dev, 3, value);
6421 }
6422
6423 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
6424 {
6425         rt2800_bbp_write(rt2x00dev, 3, 0x00);
6426         rt2800_bbp_write(rt2x00dev, 4, 0x50);
6427
6428         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6429
6430         rt2800_bbp_write(rt2x00dev, 47, 0x48);
6431
6432         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6433         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6434
6435         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6436
6437         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6438         rt2800_bbp_write(rt2x00dev, 73, 0x13);
6439         rt2800_bbp_write(rt2x00dev, 75, 0x46);
6440         rt2800_bbp_write(rt2x00dev, 76, 0x28);
6441
6442         rt2800_bbp_write(rt2x00dev, 77, 0x59);
6443
6444         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6445
6446         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6447         rt2800_bbp_write(rt2x00dev, 80, 0x08);
6448         rt2800_bbp_write(rt2x00dev, 81, 0x37);
6449
6450         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6451
6452         if (rt2x00_rt(rt2x00dev, RT5350)) {
6453                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6454                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6455         } else {
6456                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6457                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6458         }
6459
6460         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6461
6462         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6463
6464         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6465
6466         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6467
6468         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6469
6470         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6471
6472         if (rt2x00_rt(rt2x00dev, RT5350)) {
6473                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6474                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6475         } else {
6476                 rt2800_bbp_write(rt2x00dev, 105, 0x34);
6477                 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6478         }
6479
6480         rt2800_bbp_write(rt2x00dev, 120, 0x50);
6481
6482         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6483
6484         rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6485         /* Set ITxBF timeout to 0x9c40=1000msec */
6486         rt2800_bbp_write(rt2x00dev, 179, 0x02);
6487         rt2800_bbp_write(rt2x00dev, 180, 0x00);
6488         rt2800_bbp_write(rt2x00dev, 182, 0x40);
6489         rt2800_bbp_write(rt2x00dev, 180, 0x01);
6490         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6491         rt2800_bbp_write(rt2x00dev, 179, 0x00);
6492         /* Reprogram the inband interface to put right values in RXWI */
6493         rt2800_bbp_write(rt2x00dev, 142, 0x04);
6494         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6495         rt2800_bbp_write(rt2x00dev, 142, 0x06);
6496         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6497         rt2800_bbp_write(rt2x00dev, 142, 0x07);
6498         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6499         rt2800_bbp_write(rt2x00dev, 142, 0x08);
6500         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6501
6502         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6503
6504         if (rt2x00_rt(rt2x00dev, RT5350)) {
6505                 /* Antenna Software OFDM */
6506                 rt2800_bbp_write(rt2x00dev, 150, 0x40);
6507                 /* Antenna Software CCK */
6508                 rt2800_bbp_write(rt2x00dev, 151, 0x30);
6509                 rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6510                 /* Clear previously selected antenna */
6511                 rt2800_bbp_write(rt2x00dev, 154, 0);
6512         }
6513 }
6514
6515 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6516 {
6517         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6518         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6519
6520         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6521         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6522
6523         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6524
6525         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6526         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6527         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6528
6529         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6530
6531         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6532
6533         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6534
6535         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6536
6537         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6538
6539         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6540
6541         if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6542                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6543         else
6544                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6545
6546         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6547
6548         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6549
6550         rt2800_disable_unused_dac_adc(rt2x00dev);
6551 }
6552
6553 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6554 {
6555         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6556
6557         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6558         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6559
6560         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6561         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6562
6563         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6564
6565         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6566         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6567         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6568
6569         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6570
6571         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6572
6573         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6574
6575         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6576
6577         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6578
6579         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6580
6581         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6582
6583         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6584
6585         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6586
6587         rt2800_disable_unused_dac_adc(rt2x00dev);
6588 }
6589
6590 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6591 {
6592         rt2800_init_bbp_early(rt2x00dev);
6593
6594         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6595         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6596         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6597         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6598
6599         rt2800_bbp_write(rt2x00dev, 84, 0x19);
6600
6601         /* Enable DC filter */
6602         if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6603                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6604 }
6605
6606 static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev)
6607 {
6608         rt2800_init_bbp_early(rt2x00dev);
6609
6610         rt2800_bbp_write(rt2x00dev, 4, 0x50);
6611         rt2800_bbp_write(rt2x00dev, 47, 0x48);
6612
6613         rt2800_bbp_write(rt2x00dev, 86, 0x46);
6614         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6615
6616         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6617
6618         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6619         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6620         rt2800_bbp_write(rt2x00dev, 105, 0x34);
6621         rt2800_bbp_write(rt2x00dev, 106, 0x12);
6622         rt2800_bbp_write(rt2x00dev, 120, 0x50);
6623         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6624         rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6625
6626         /* Set ITxBF timeout to 0x9C40=1000msec */
6627         rt2800_bbp_write(rt2x00dev, 179, 0x02);
6628         rt2800_bbp_write(rt2x00dev, 180, 0x00);
6629         rt2800_bbp_write(rt2x00dev, 182, 0x40);
6630         rt2800_bbp_write(rt2x00dev, 180, 0x01);
6631         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6632
6633         rt2800_bbp_write(rt2x00dev, 179, 0x00);
6634
6635         /* Reprogram the inband interface to put right values in RXWI */
6636         rt2800_bbp_write(rt2x00dev, 142, 0x04);
6637         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6638         rt2800_bbp_write(rt2x00dev, 142, 0x06);
6639         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6640         rt2800_bbp_write(rt2x00dev, 142, 0x07);
6641         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6642         rt2800_bbp_write(rt2x00dev, 142, 0x08);
6643         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6644         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6645 }
6646
6647 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6648 {
6649         int ant, div_mode;
6650         u16 eeprom;
6651         u8 value;
6652
6653         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6654
6655         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6656
6657         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6658         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6659
6660         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6661
6662         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6663         rt2800_bbp_write(rt2x00dev, 73, 0x13);
6664         rt2800_bbp_write(rt2x00dev, 75, 0x46);
6665         rt2800_bbp_write(rt2x00dev, 76, 0x28);
6666
6667         rt2800_bbp_write(rt2x00dev, 77, 0x59);
6668
6669         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6670
6671         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6672         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6673         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6674
6675         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6676
6677         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6678
6679         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6680
6681         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6682
6683         if (rt2x00_rt(rt2x00dev, RT5392))
6684                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6685
6686         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6687
6688         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6689
6690         if (rt2x00_rt(rt2x00dev, RT5392)) {
6691                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6692                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6693         }
6694
6695         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6696
6697         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6698
6699         rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6700
6701         if (rt2x00_rt(rt2x00dev, RT5390))
6702                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6703         else if (rt2x00_rt(rt2x00dev, RT5392))
6704                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6705         else
6706                 WARN_ON(1);
6707
6708         rt2800_bbp_write(rt2x00dev, 128, 0x12);
6709
6710         if (rt2x00_rt(rt2x00dev, RT5392)) {
6711                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6712                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6713         }
6714
6715         rt2800_disable_unused_dac_adc(rt2x00dev);
6716
6717         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6718         div_mode = rt2x00_get_field16(eeprom,
6719                                       EEPROM_NIC_CONF1_ANT_DIVERSITY);
6720         ant = (div_mode == 3) ? 1 : 0;
6721
6722         /* check if this is a Bluetooth combo card */
6723         if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
6724                 u32 reg;
6725
6726                 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
6727                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
6728                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
6729                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
6730                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
6731                 if (ant == 0)
6732                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
6733                 else if (ant == 1)
6734                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
6735                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6736         }
6737
6738         /* These chips have hardware RX antenna diversity */
6739         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
6740             rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
6741                 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6742                 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6743                 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6744         }
6745
6746         value = rt2800_bbp_read(rt2x00dev, 152);
6747         if (ant == 0)
6748                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6749         else
6750                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6751         rt2800_bbp_write(rt2x00dev, 152, value);
6752
6753         rt2800_init_freq_calibration(rt2x00dev);
6754 }
6755
6756 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6757 {
6758         int ant, div_mode;
6759         u16 eeprom;
6760         u8 value;
6761
6762         rt2800_init_bbp_early(rt2x00dev);
6763
6764         value = rt2800_bbp_read(rt2x00dev, 105);
6765         rt2x00_set_field8(&value, BBP105_MLD,
6766                           rt2x00dev->default_ant.rx_chain_num == 2);
6767         rt2800_bbp_write(rt2x00dev, 105, value);
6768
6769         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6770
6771         rt2800_bbp_write(rt2x00dev, 20, 0x06);
6772         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6773         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6774         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6775         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6776         rt2800_bbp_write(rt2x00dev, 70, 0x05);
6777         rt2800_bbp_write(rt2x00dev, 73, 0x13);
6778         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6779         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6780         rt2800_bbp_write(rt2x00dev, 76, 0x28);
6781         rt2800_bbp_write(rt2x00dev, 77, 0x59);
6782         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6783         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6784         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6785         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6786         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6787         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6788         rt2800_bbp_write(rt2x00dev, 98, 0x12);
6789         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6790         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6791         /* FIXME BBP105 owerwrite */
6792         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6793         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6794         rt2800_bbp_write(rt2x00dev, 128, 0x12);
6795         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
6796         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
6797         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
6798
6799         /* Initialize GLRT (Generalized Likehood Radio Test) */
6800         rt2800_init_bbp_5592_glrt(rt2x00dev);
6801
6802         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6803
6804         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6805         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
6806         ant = (div_mode == 3) ? 1 : 0;
6807         value = rt2800_bbp_read(rt2x00dev, 152);
6808         if (ant == 0) {
6809                 /* Main antenna */
6810                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6811         } else {
6812                 /* Auxiliary antenna */
6813                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6814         }
6815         rt2800_bbp_write(rt2x00dev, 152, value);
6816
6817         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
6818                 value = rt2800_bbp_read(rt2x00dev, 254);
6819                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
6820                 rt2800_bbp_write(rt2x00dev, 254, value);
6821         }
6822
6823         rt2800_init_freq_calibration(rt2x00dev);
6824
6825         rt2800_bbp_write(rt2x00dev, 84, 0x19);
6826         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6827                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6828 }
6829
6830 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
6831                                   const u8 reg, const u8 value)
6832 {
6833         rt2800_bbp_write(rt2x00dev, 195, reg);
6834         rt2800_bbp_write(rt2x00dev, 196, value);
6835 }
6836
6837 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
6838                                   const u8 reg, const u8 value)
6839 {
6840         rt2800_bbp_write(rt2x00dev, 158, reg);
6841         rt2800_bbp_write(rt2x00dev, 159, value);
6842 }
6843
6844 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)
6845 {
6846         rt2800_bbp_write(rt2x00dev, 158, reg);
6847         return rt2800_bbp_read(rt2x00dev, 159);
6848 }
6849
6850 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
6851 {
6852         u8 bbp;
6853
6854         /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
6855         bbp = rt2800_bbp_read(rt2x00dev, 105);
6856         rt2x00_set_field8(&bbp, BBP105_MLD,
6857                           rt2x00dev->default_ant.rx_chain_num == 2);
6858         rt2800_bbp_write(rt2x00dev, 105, bbp);
6859
6860         /* Avoid data loss and CRC errors */
6861         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6862
6863         /* Fix I/Q swap issue */
6864         bbp = rt2800_bbp_read(rt2x00dev, 1);
6865         bbp |= 0x04;
6866         rt2800_bbp_write(rt2x00dev, 1, bbp);
6867
6868         /* BBP for G band */
6869         rt2800_bbp_write(rt2x00dev, 3, 0x08);
6870         rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
6871         rt2800_bbp_write(rt2x00dev, 6, 0x08);
6872         rt2800_bbp_write(rt2x00dev, 14, 0x09);
6873         rt2800_bbp_write(rt2x00dev, 15, 0xFF);
6874         rt2800_bbp_write(rt2x00dev, 16, 0x01);
6875         rt2800_bbp_write(rt2x00dev, 20, 0x06);
6876         rt2800_bbp_write(rt2x00dev, 21, 0x00);
6877         rt2800_bbp_write(rt2x00dev, 22, 0x00);
6878         rt2800_bbp_write(rt2x00dev, 27, 0x00);
6879         rt2800_bbp_write(rt2x00dev, 28, 0x00);
6880         rt2800_bbp_write(rt2x00dev, 30, 0x00);
6881         rt2800_bbp_write(rt2x00dev, 31, 0x48);
6882         rt2800_bbp_write(rt2x00dev, 47, 0x40);
6883         rt2800_bbp_write(rt2x00dev, 62, 0x00);
6884         rt2800_bbp_write(rt2x00dev, 63, 0x00);
6885         rt2800_bbp_write(rt2x00dev, 64, 0x00);
6886         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6887         rt2800_bbp_write(rt2x00dev, 66, 0x1C);
6888         rt2800_bbp_write(rt2x00dev, 67, 0x20);
6889         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6890         rt2800_bbp_write(rt2x00dev, 69, 0x10);
6891         rt2800_bbp_write(rt2x00dev, 70, 0x05);
6892         rt2800_bbp_write(rt2x00dev, 73, 0x18);
6893         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6894         rt2800_bbp_write(rt2x00dev, 75, 0x60);
6895         rt2800_bbp_write(rt2x00dev, 76, 0x44);
6896         rt2800_bbp_write(rt2x00dev, 77, 0x59);
6897         rt2800_bbp_write(rt2x00dev, 78, 0x1E);
6898         rt2800_bbp_write(rt2x00dev, 79, 0x1C);
6899         rt2800_bbp_write(rt2x00dev, 80, 0x0C);
6900         rt2800_bbp_write(rt2x00dev, 81, 0x3A);
6901         rt2800_bbp_write(rt2x00dev, 82, 0xB6);
6902         rt2800_bbp_write(rt2x00dev, 83, 0x9A);
6903         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6904         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6905         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6906         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6907         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6908         rt2800_bbp_write(rt2x00dev, 95, 0x9A);
6909         rt2800_bbp_write(rt2x00dev, 96, 0x00);
6910         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6911         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6912         /* FIXME BBP105 owerwrite */
6913         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6914         rt2800_bbp_write(rt2x00dev, 106, 0x12);
6915         rt2800_bbp_write(rt2x00dev, 109, 0x00);
6916         rt2800_bbp_write(rt2x00dev, 134, 0x10);
6917         rt2800_bbp_write(rt2x00dev, 135, 0xA6);
6918         rt2800_bbp_write(rt2x00dev, 137, 0x04);
6919         rt2800_bbp_write(rt2x00dev, 142, 0x30);
6920         rt2800_bbp_write(rt2x00dev, 143, 0xF7);
6921         rt2800_bbp_write(rt2x00dev, 160, 0xEC);
6922         rt2800_bbp_write(rt2x00dev, 161, 0xC4);
6923         rt2800_bbp_write(rt2x00dev, 162, 0x77);
6924         rt2800_bbp_write(rt2x00dev, 163, 0xF9);
6925         rt2800_bbp_write(rt2x00dev, 164, 0x00);
6926         rt2800_bbp_write(rt2x00dev, 165, 0x00);
6927         rt2800_bbp_write(rt2x00dev, 186, 0x00);
6928         rt2800_bbp_write(rt2x00dev, 187, 0x00);
6929         rt2800_bbp_write(rt2x00dev, 188, 0x00);
6930         rt2800_bbp_write(rt2x00dev, 186, 0x00);
6931         rt2800_bbp_write(rt2x00dev, 187, 0x01);
6932         rt2800_bbp_write(rt2x00dev, 188, 0x00);
6933         rt2800_bbp_write(rt2x00dev, 189, 0x00);
6934
6935         rt2800_bbp_write(rt2x00dev, 91, 0x06);
6936         rt2800_bbp_write(rt2x00dev, 92, 0x04);
6937         rt2800_bbp_write(rt2x00dev, 93, 0x54);
6938         rt2800_bbp_write(rt2x00dev, 99, 0x50);
6939         rt2800_bbp_write(rt2x00dev, 148, 0x84);
6940         rt2800_bbp_write(rt2x00dev, 167, 0x80);
6941         rt2800_bbp_write(rt2x00dev, 178, 0xFF);
6942         rt2800_bbp_write(rt2x00dev, 106, 0x13);
6943
6944         /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
6945         rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
6946         rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
6947         rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
6948         rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
6949         rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
6950         rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
6951         rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
6952         rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
6953         rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
6954         rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
6955         rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
6956         rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
6957         rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
6958         rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
6959         rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
6960         rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
6961         rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
6962         rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
6963         rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
6964         rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
6965         rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
6966         rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
6967         rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
6968         rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
6969         rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
6970         rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
6971         rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
6972         rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
6973         rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
6974         rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
6975         rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
6976         rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
6977         rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
6978         rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
6979         rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
6980         rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
6981         rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
6982         rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
6983         rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
6984         rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
6985         rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
6986         rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
6987         rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
6988         rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
6989         rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
6990         rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
6991         rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
6992         rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
6993         rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
6994         rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
6995         rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
6996         rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
6997         rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
6998         rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
6999         rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
7000         rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
7001         rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
7002         rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
7003         rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
7004         rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
7005         rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
7006         rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
7007         rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
7008         rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
7009         rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
7010         rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
7011         rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
7012         rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
7013         rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
7014         rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
7015         rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
7016         rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
7017         rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
7018         rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
7019         rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
7020         rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
7021         rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
7022         rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
7023         rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
7024         rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
7025         rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
7026         rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
7027         rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
7028
7029         /* BBP for G band DCOC function */
7030         rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
7031         rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
7032         rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
7033         rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
7034         rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
7035         rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
7036         rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
7037         rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
7038         rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
7039         rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
7040         rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
7041         rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
7042         rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
7043         rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
7044         rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
7045         rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
7046         rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
7047         rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
7048         rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
7049         rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
7050
7051         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7052 }
7053
7054 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
7055 {
7056         unsigned int i;
7057         u16 eeprom;
7058         u8 reg_id;
7059         u8 value;
7060
7061         if (rt2800_is_305x_soc(rt2x00dev))
7062                 rt2800_init_bbp_305x_soc(rt2x00dev);
7063
7064         switch (rt2x00dev->chip.rt) {
7065         case RT2860:
7066         case RT2872:
7067         case RT2883:
7068                 rt2800_init_bbp_28xx(rt2x00dev);
7069                 break;
7070         case RT3070:
7071         case RT3071:
7072         case RT3090:
7073                 rt2800_init_bbp_30xx(rt2x00dev);
7074                 break;
7075         case RT3290:
7076                 rt2800_init_bbp_3290(rt2x00dev);
7077                 break;
7078         case RT3352:
7079         case RT5350:
7080                 rt2800_init_bbp_3352(rt2x00dev);
7081                 break;
7082         case RT3390:
7083                 rt2800_init_bbp_3390(rt2x00dev);
7084                 break;
7085         case RT3572:
7086                 rt2800_init_bbp_3572(rt2x00dev);
7087                 break;
7088         case RT3593:
7089                 rt2800_init_bbp_3593(rt2x00dev);
7090                 return;
7091         case RT3883:
7092                 rt2800_init_bbp_3883(rt2x00dev);
7093                 return;
7094         case RT5390:
7095         case RT5392:
7096                 rt2800_init_bbp_53xx(rt2x00dev);
7097                 break;
7098         case RT5592:
7099                 rt2800_init_bbp_5592(rt2x00dev);
7100                 return;
7101         case RT6352:
7102                 rt2800_init_bbp_6352(rt2x00dev);
7103                 break;
7104         }
7105
7106         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
7107                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
7108                                                        EEPROM_BBP_START, i);
7109
7110                 if (eeprom != 0xffff && eeprom != 0x0000) {
7111                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
7112                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
7113                         rt2800_bbp_write(rt2x00dev, reg_id, value);
7114                 }
7115         }
7116 }
7117
7118 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
7119 {
7120         u32 reg;
7121
7122         reg = rt2800_register_read(rt2x00dev, OPT_14_CSR);
7123         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
7124         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
7125 }
7126
7127 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
7128                                 u8 filter_target)
7129 {
7130         unsigned int i;
7131         u8 bbp;
7132         u8 rfcsr;
7133         u8 passband;
7134         u8 stopband;
7135         u8 overtuned = 0;
7136         u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
7137
7138         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7139
7140         bbp = rt2800_bbp_read(rt2x00dev, 4);
7141         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
7142         rt2800_bbp_write(rt2x00dev, 4, bbp);
7143
7144         rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
7145         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
7146         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
7147
7148         rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7149         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
7150         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7151
7152         /*
7153          * Set power & frequency of passband test tone
7154          */
7155         rt2800_bbp_write(rt2x00dev, 24, 0);
7156
7157         for (i = 0; i < 100; i++) {
7158                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
7159                 msleep(1);
7160
7161                 passband = rt2800_bbp_read(rt2x00dev, 55);
7162                 if (passband)
7163                         break;
7164         }
7165
7166         /*
7167          * Set power & frequency of stopband test tone
7168          */
7169         rt2800_bbp_write(rt2x00dev, 24, 0x06);
7170
7171         for (i = 0; i < 100; i++) {
7172                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
7173                 msleep(1);
7174
7175                 stopband = rt2800_bbp_read(rt2x00dev, 55);
7176
7177                 if ((passband - stopband) <= filter_target) {
7178                         rfcsr24++;
7179                         overtuned += ((passband - stopband) == filter_target);
7180                 } else
7181                         break;
7182
7183                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7184         }
7185
7186         rfcsr24 -= !!overtuned;
7187
7188         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7189         return rfcsr24;
7190 }
7191
7192 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
7193                                        const unsigned int rf_reg)
7194 {
7195         u8 rfcsr;
7196
7197         rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
7198         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
7199         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7200         msleep(1);
7201         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
7202         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7203 }
7204
7205 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
7206 {
7207         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7208         u8 filter_tgt_bw20;
7209         u8 filter_tgt_bw40;
7210         u8 rfcsr, bbp;
7211
7212         /*
7213          * TODO: sync filter_tgt values with vendor driver
7214          */
7215         if (rt2x00_rt(rt2x00dev, RT3070)) {
7216                 filter_tgt_bw20 = 0x16;
7217                 filter_tgt_bw40 = 0x19;
7218         } else {
7219                 filter_tgt_bw20 = 0x13;
7220                 filter_tgt_bw40 = 0x15;
7221         }
7222
7223         drv_data->calibration_bw20 =
7224                 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
7225         drv_data->calibration_bw40 =
7226                 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
7227
7228         /*
7229          * Save BBP 25 & 26 values for later use in channel switching (for 3052)
7230          */
7231         drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7232         drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7233
7234         /*
7235          * Set back to initial state
7236          */
7237         rt2800_bbp_write(rt2x00dev, 24, 0);
7238
7239         rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7240         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
7241         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7242
7243         /*
7244          * Set BBP back to BW20
7245          */
7246         bbp = rt2800_bbp_read(rt2x00dev, 4);
7247         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
7248         rt2800_bbp_write(rt2x00dev, 4, bbp);
7249 }
7250
7251 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
7252 {
7253         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7254         u8 min_gain, rfcsr, bbp;
7255         u16 eeprom;
7256
7257         rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
7258
7259         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
7260         if (rt2x00_rt(rt2x00dev, RT3070) ||
7261             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7262             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
7263             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7264                 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
7265                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
7266         }
7267
7268         min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
7269         if (drv_data->txmixer_gain_24g >= min_gain) {
7270                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
7271                                   drv_data->txmixer_gain_24g);
7272         }
7273
7274         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
7275
7276         if (rt2x00_rt(rt2x00dev, RT3090)) {
7277                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
7278                 bbp = rt2800_bbp_read(rt2x00dev, 138);
7279                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7280                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
7281                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
7282                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
7283                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
7284                 rt2800_bbp_write(rt2x00dev, 138, bbp);
7285         }
7286
7287         if (rt2x00_rt(rt2x00dev, RT3070)) {
7288                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
7289                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
7290                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
7291                 else
7292                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
7293                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
7294                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
7295                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
7296                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
7297         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
7298                    rt2x00_rt(rt2x00dev, RT3090) ||
7299                    rt2x00_rt(rt2x00dev, RT3390)) {
7300                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7301                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7302                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7303                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7304                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
7305                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
7306                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7307
7308                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
7309                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
7310                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
7311
7312                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
7313                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
7314                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
7315
7316                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
7317                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
7318                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
7319         }
7320 }
7321
7322 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
7323 {
7324         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7325         u8 rfcsr;
7326         u8 tx_gain;
7327
7328         rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
7329         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
7330         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7331
7332         rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
7333         tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
7334                                     RFCSR17_TXMIXER_GAIN);
7335         rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
7336         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
7337
7338         rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
7339         rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
7340         rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
7341
7342         rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
7343         rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
7344         rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
7345
7346         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7347         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7348         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
7349         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7350
7351         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
7352         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
7353         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
7354
7355         /* TODO: enable stream mode */
7356 }
7357
7358 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
7359 {
7360         u8 reg;
7361         u16 eeprom;
7362
7363         /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
7364         reg = rt2800_bbp_read(rt2x00dev, 138);
7365         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7366         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
7367                 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
7368         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
7369                 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
7370         rt2800_bbp_write(rt2x00dev, 138, reg);
7371
7372         reg = rt2800_rfcsr_read(rt2x00dev, 38);
7373         rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
7374         rt2800_rfcsr_write(rt2x00dev, 38, reg);
7375
7376         reg = rt2800_rfcsr_read(rt2x00dev, 39);
7377         rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
7378         rt2800_rfcsr_write(rt2x00dev, 39, reg);
7379
7380         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7381
7382         reg = rt2800_rfcsr_read(rt2x00dev, 30);
7383         rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
7384         rt2800_rfcsr_write(rt2x00dev, 30, reg);
7385 }
7386
7387 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
7388 {
7389         rt2800_rf_init_calibration(rt2x00dev, 30);
7390
7391         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
7392         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
7393         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
7394         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
7395         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7396         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7397         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7398         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
7399         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
7400         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7401         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
7402         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7403         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
7404         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
7405         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7406         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7407         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7408         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7409         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7410         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7411         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7412         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7413         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7414         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
7415         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7416         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
7417         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
7418         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
7419         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
7420         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
7421         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
7422         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
7423 }
7424
7425 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
7426 {
7427         u8 rfcsr;
7428         u16 eeprom;
7429         u32 reg;
7430
7431         /* XXX vendor driver do this only for 3070 */
7432         rt2800_rf_init_calibration(rt2x00dev, 30);
7433
7434         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7435         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7436         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7437         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
7438         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7439         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
7440         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7441         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
7442         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7443         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7444         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7445         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7446         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7447         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7448         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7449         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7450         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7451         rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
7452         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
7453
7454         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
7455                 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7456                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7457                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7458                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7459         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
7460                    rt2x00_rt(rt2x00dev, RT3090)) {
7461                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
7462
7463                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7464                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7465                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7466
7467                 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7468                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7469                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7470                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
7471                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
7472                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
7473                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7474                         else
7475                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7476                 }
7477                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7478
7479                 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7480                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7481                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7482         }
7483
7484         rt2800_rx_filter_calibration(rt2x00dev);
7485
7486         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
7487             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7488             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
7489                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7490
7491         rt2800_led_open_drain_enable(rt2x00dev);
7492         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7493 }
7494
7495 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
7496 {
7497         u8 rfcsr;
7498
7499         rt2800_rf_init_calibration(rt2x00dev, 2);
7500
7501         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7502         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7503         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7504         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7505         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7506         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
7507         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7508         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7509         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7510         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7511         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7512         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
7513         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7514         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
7515         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7516         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7517         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7518         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7519         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7520         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7521         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7522         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
7523         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7524         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7525         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7526         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7527         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7528         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7529         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7530         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7531         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7532         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7533         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7534         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7535         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7536         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7537         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7538         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7539         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7540         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7541         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7542         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7543         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7544         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7545         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7546         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
7547
7548         rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
7549         rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
7550         rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
7551
7552         rt2800_led_open_drain_enable(rt2x00dev);
7553         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7554 }
7555
7556 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7557 {
7558         int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0,
7559                                   &rt2x00dev->cap_flags);
7560         int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1,
7561                                   &rt2x00dev->cap_flags);
7562         u8 rfcsr;
7563
7564         rt2800_rf_init_calibration(rt2x00dev, 30);
7565
7566         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7567         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7568         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7569         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7570         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7571         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7572         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7573         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7574         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7575         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7576         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7577         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7578         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7579         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7580         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7581         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7582         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7583         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7584         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7585         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7586         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7587         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7588         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7589         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7590         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7591         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7592         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7593         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7594         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7595         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7596         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7597         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7598         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7599         rfcsr = 0x01;
7600         if (tx0_ext_pa)
7601                 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1);
7602         if (tx1_ext_pa)
7603                 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1);
7604         rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
7605         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7606         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7607         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7608         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7609         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7610         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
7611         rfcsr = 0x52;
7612         if (!tx0_ext_pa) {
7613                 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1);
7614                 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1);
7615         }
7616         rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7617         rfcsr = 0x52;
7618         if (!tx1_ext_pa) {
7619                 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1);
7620                 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1);
7621         }
7622         rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
7623         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7624         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7625         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7626         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7627         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7628         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7629         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
7630         rfcsr = 0x2d;
7631         if (tx0_ext_pa)
7632                 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1);
7633         if (tx1_ext_pa)
7634                 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1);
7635         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7636         rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7637         rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7638         rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7639         rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7640         rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7641         rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7642         rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7643         rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
7644         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7645         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7646         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7647         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7648         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7649
7650         rt2800_rx_filter_calibration(rt2x00dev);
7651         rt2800_led_open_drain_enable(rt2x00dev);
7652         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7653 }
7654
7655 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7656 {
7657         u32 reg;
7658
7659         rt2800_rf_init_calibration(rt2x00dev, 30);
7660
7661         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7662         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7663         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7664         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7665         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7666         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7667         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7668         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7669         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7670         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7671         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7672         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7673         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7674         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7675         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7676         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7677         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7678         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7679         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7680         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7681         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7682         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7683         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7684         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7685         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7686         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7687         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7688         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7689         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7690         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7691         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7692         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
7693
7694         reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7695         rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7696         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7697
7698         rt2800_rx_filter_calibration(rt2x00dev);
7699
7700         if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7701                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7702
7703         rt2800_led_open_drain_enable(rt2x00dev);
7704         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7705 }
7706
7707 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7708 {
7709         u8 rfcsr;
7710         u32 reg;
7711
7712         rt2800_rf_init_calibration(rt2x00dev, 30);
7713
7714         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7715         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7716         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7717         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7718         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7719         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7720         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7721         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7722         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7723         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7724         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7725         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7726         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7727         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7728         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7729         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7730         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7731         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7732         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7733         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7734         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7735         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7736         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7737         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7738         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7739         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7740         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7741         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7742         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7743         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7744         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
7745
7746         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7747         rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7748         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7749
7750         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7751         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7752         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7753         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7754         msleep(1);
7755         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7756         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7757         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7758         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7759
7760         rt2800_rx_filter_calibration(rt2x00dev);
7761         rt2800_led_open_drain_enable(rt2x00dev);
7762         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7763 }
7764
7765 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7766 {
7767         u8 bbp;
7768         bool txbf_enabled = false; /* FIXME */
7769
7770         bbp = rt2800_bbp_read(rt2x00dev, 105);
7771         if (rt2x00dev->default_ant.rx_chain_num == 1)
7772                 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
7773         else
7774                 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
7775         rt2800_bbp_write(rt2x00dev, 105, bbp);
7776
7777         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7778
7779         rt2800_bbp_write(rt2x00dev, 92, 0x02);
7780         rt2800_bbp_write(rt2x00dev, 82, 0x82);
7781         rt2800_bbp_write(rt2x00dev, 106, 0x05);
7782         rt2800_bbp_write(rt2x00dev, 104, 0x92);
7783         rt2800_bbp_write(rt2x00dev, 88, 0x90);
7784         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7785         rt2800_bbp_write(rt2x00dev, 47, 0x48);
7786         rt2800_bbp_write(rt2x00dev, 120, 0x50);
7787
7788         if (txbf_enabled)
7789                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7790         else
7791                 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7792
7793         /* SNR mapping */
7794         rt2800_bbp_write(rt2x00dev, 142, 6);
7795         rt2800_bbp_write(rt2x00dev, 143, 160);
7796         rt2800_bbp_write(rt2x00dev, 142, 7);
7797         rt2800_bbp_write(rt2x00dev, 143, 161);
7798         rt2800_bbp_write(rt2x00dev, 142, 8);
7799         rt2800_bbp_write(rt2x00dev, 143, 162);
7800
7801         /* ADC/DAC control */
7802         rt2800_bbp_write(rt2x00dev, 31, 0x08);
7803
7804         /* RX AGC energy lower bound in log2 */
7805         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
7806
7807         /* FIXME: BBP 105 owerwrite? */
7808         rt2800_bbp_write(rt2x00dev, 105, 0x04);
7809
7810 }
7811
7812 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
7813 {
7814         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7815         u32 reg;
7816         u8 rfcsr;
7817
7818         /* Disable GPIO #4 and #7 function for LAN PE control */
7819         reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7820         rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
7821         rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
7822         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7823
7824         /* Initialize default register values */
7825         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
7826         rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
7827         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7828         rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
7829         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7830         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7831         rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
7832         rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
7833         rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
7834         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
7835         rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
7836         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7837         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7838         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7839         rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
7840         rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
7841         rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
7842         rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
7843         rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
7844         rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
7845         rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
7846         rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
7847         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
7848         rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
7849         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
7850         rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
7851         rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
7852         rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
7853         rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
7854         rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
7855         rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
7856         rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
7857
7858         /* Initiate calibration */
7859         /* TODO: use rt2800_rf_init_calibration ? */
7860         rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
7861         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
7862         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
7863
7864         rt2800_freq_cal_mode1(rt2x00dev);
7865
7866         rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
7867         rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
7868         rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
7869
7870         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7871         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7872         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7873         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7874         usleep_range(1000, 1500);
7875         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7876         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7877         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7878
7879         /* Set initial values for RX filter calibration */
7880         drv_data->calibration_bw20 = 0x1f;
7881         drv_data->calibration_bw40 = 0x2f;
7882
7883         /* Save BBP 25 & 26 values for later use in channel switching */
7884         drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7885         drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7886
7887         rt2800_led_open_drain_enable(rt2x00dev);
7888         rt2800_normal_mode_setup_3593(rt2x00dev);
7889
7890         rt3593_post_bbp_init(rt2x00dev);
7891
7892         /* TODO: enable stream mode support */
7893 }
7894
7895 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
7896 {
7897         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7898         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7899         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7900         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7901         rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
7902         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7903         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7904         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7905         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7906         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7907         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7908         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7909         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7910         if (rt2800_clk_is_20mhz(rt2x00dev))
7911                 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
7912         else
7913                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7914         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7915         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7916         rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
7917         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7918         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7919         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7920         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7921         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7922         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7923         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7924         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7925         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7926         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7927         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7928         rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
7929         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7930         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7931         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7932         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7933         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7934         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7935         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7936         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7937         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7938         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7939         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7940         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7941         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7942         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
7943         rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
7944         rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
7945         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7946         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7947         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7948         rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
7949         rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
7950         rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
7951         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7952         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7953         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
7954         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7955         rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
7956         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
7957         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
7958         rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
7959         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7960         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
7961         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7962         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7963 }
7964
7965 static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev)
7966 {
7967         u8 rfcsr;
7968
7969         /* TODO: get the actual ECO value from the SoC */
7970         const unsigned int eco = 5;
7971
7972         rt2800_rf_init_calibration(rt2x00dev, 2);
7973
7974         rt2800_rfcsr_write(rt2x00dev, 0, 0xe0);
7975         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
7976         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7977         rt2800_rfcsr_write(rt2x00dev, 3, 0x20);
7978         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7979         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7980         rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
7981         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7982         rt2800_rfcsr_write(rt2x00dev, 8, 0x5b);
7983         rt2800_rfcsr_write(rt2x00dev, 9, 0x08);
7984         rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
7985         rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
7986         rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
7987         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
7988         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7989         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7990         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7991
7992         /* RFCSR 17 will be initialized later based on the
7993          * frequency offset stored in the EEPROM
7994          */
7995
7996         rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
7997         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7998         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7999         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8000         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8001         rt2800_rfcsr_write(rt2x00dev, 23, 0xc0);
8002         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8003         rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8004         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8005         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8006         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8007         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
8008         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8009         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8010         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8011         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8012         rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
8013         rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8014         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8015         rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8016         rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
8017         rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
8018         rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8019         rt2800_rfcsr_write(rt2x00dev, 41, 0x00);
8020         rt2800_rfcsr_write(rt2x00dev, 42, 0x00);
8021         rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8022         rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
8023         rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
8024         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
8025         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8026         rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
8027         rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
8028         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
8029         rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
8030         rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
8031         rt2800_rfcsr_write(rt2x00dev, 53, 0x76);
8032         rt2800_rfcsr_write(rt2x00dev, 54, 0x76);
8033         rt2800_rfcsr_write(rt2x00dev, 55, 0x76);
8034         rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
8035         rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
8036         rt2800_rfcsr_write(rt2x00dev, 58, 0x00);
8037         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
8038         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
8039         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
8040         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8041         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8042
8043         /* TODO: rx filter calibration? */
8044
8045         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
8046
8047         rt2800_bbp_write(rt2x00dev, 163, 0x9d);
8048
8049         rt2800_bbp_write(rt2x00dev, 105, 0x05);
8050
8051         rt2800_bbp_write(rt2x00dev, 179, 0x02);
8052         rt2800_bbp_write(rt2x00dev, 180, 0x00);
8053         rt2800_bbp_write(rt2x00dev, 182, 0x40);
8054         rt2800_bbp_write(rt2x00dev, 180, 0x01);
8055         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
8056
8057         rt2800_bbp_write(rt2x00dev, 179, 0x00);
8058
8059         rt2800_bbp_write(rt2x00dev, 142, 0x04);
8060         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
8061         rt2800_bbp_write(rt2x00dev, 142, 0x06);
8062         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
8063         rt2800_bbp_write(rt2x00dev, 142, 0x07);
8064         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
8065         rt2800_bbp_write(rt2x00dev, 142, 0x08);
8066         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
8067         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
8068
8069         if (eco == 5) {
8070                 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
8071                 rt2800_rfcsr_write(rt2x00dev, 33, 0x32);
8072         }
8073
8074         rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8075         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0);
8076         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
8077         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8078         msleep(1);
8079         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
8080         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8081
8082         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
8083         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
8084         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
8085
8086         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
8087         rfcsr |= 0xc0;
8088         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
8089
8090         rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
8091         rfcsr |= 0x20;
8092         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
8093
8094         rfcsr = rt2800_rfcsr_read(rt2x00dev, 46);
8095         rfcsr |= 0x20;
8096         rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
8097
8098         rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
8099         rfcsr &= ~0xee;
8100         rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
8101 }
8102
8103 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
8104 {
8105         rt2800_rf_init_calibration(rt2x00dev, 2);
8106
8107         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
8108         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8109         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8110         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8111         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8112                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8113         else
8114                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
8115         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8116         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8117         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8118         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8119         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8120         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8121         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8122         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8123         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8124         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8125
8126         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8127         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8128         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8129         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8130         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8131         if (rt2x00_is_usb(rt2x00dev) &&
8132             rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8133                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8134         else
8135                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
8136         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8137         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8138         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8139         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8140
8141         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8142         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8143         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8144         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8145         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8146         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8147         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8148         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8149         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8150         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8151
8152         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8153         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8154         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
8155         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
8156         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8157         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8158         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8159                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8160         else
8161                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
8162         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8163         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8164         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8165
8166         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8167         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8168                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8169         else
8170                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
8171         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
8172         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
8173         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8174                 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
8175         else
8176                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
8177         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
8178         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
8179         rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
8180
8181         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8182         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
8183                 if (rt2x00_is_usb(rt2x00dev))
8184                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8185                 else
8186                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
8187         } else {
8188                 if (rt2x00_is_usb(rt2x00dev))
8189                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
8190                 else
8191                         rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
8192         }
8193         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8194         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8195
8196         rt2800_normal_mode_setup_5xxx(rt2x00dev);
8197
8198         rt2800_led_open_drain_enable(rt2x00dev);
8199 }
8200
8201 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
8202 {
8203         rt2800_rf_init_calibration(rt2x00dev, 2);
8204
8205         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
8206         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8207         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8208         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8209         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8210         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8211         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8212         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8213         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8214         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8215         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8216         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8217         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8218         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
8219         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8220         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
8221         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8222         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
8223         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
8224         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8225         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8226         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8227         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8228         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8229         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8230         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8231         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
8232         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8233         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8234         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8235         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8236         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8237         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
8238         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8239         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
8240         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8241         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8242         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8243         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8244         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8245         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8246         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
8247         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8248         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8249         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
8250         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
8251         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
8252         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
8253         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8254         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8255         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
8256         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8257         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8258         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
8259         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8260         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
8261         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
8262         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8263
8264         rt2800_normal_mode_setup_5xxx(rt2x00dev);
8265
8266         rt2800_led_open_drain_enable(rt2x00dev);
8267 }
8268
8269 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
8270 {
8271         rt2800_rf_init_calibration(rt2x00dev, 30);
8272
8273         rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
8274         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
8275         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8276         rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
8277         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8278         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8279         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8280         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8281         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8282         rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
8283         rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
8284         rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
8285         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8286         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8287         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8288         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8289         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8290         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8291         rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
8292         rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
8293         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8294
8295         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8296         msleep(1);
8297
8298         rt2800_freq_cal_mode1(rt2x00dev);
8299
8300         /* Enable DC filter */
8301         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
8302                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
8303
8304         rt2800_normal_mode_setup_5xxx(rt2x00dev);
8305
8306         if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
8307                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8308
8309         rt2800_led_open_drain_enable(rt2x00dev);
8310 }
8311
8312 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
8313                                        bool set_bw, bool is_ht40)
8314 {
8315         u8 bbp_val;
8316
8317         bbp_val = rt2800_bbp_read(rt2x00dev, 21);
8318         bbp_val |= 0x1;
8319         rt2800_bbp_write(rt2x00dev, 21, bbp_val);
8320         usleep_range(100, 200);
8321
8322         if (set_bw) {
8323                 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
8324                 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
8325                 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
8326                 usleep_range(100, 200);
8327         }
8328
8329         bbp_val = rt2800_bbp_read(rt2x00dev, 21);
8330         bbp_val &= (~0x1);
8331         rt2800_bbp_write(rt2x00dev, 21, bbp_val);
8332         usleep_range(100, 200);
8333 }
8334
8335 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
8336 {
8337         u8 rf_val;
8338
8339         if (btxcal)
8340                 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
8341         else
8342                 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
8343
8344         rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
8345
8346         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8347         rf_val |= 0x80;
8348         rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
8349
8350         if (btxcal) {
8351                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
8352                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
8353                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
8354                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8355                 rf_val &= (~0x3F);
8356                 rf_val |= 0x3F;
8357                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
8358                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8359                 rf_val &= (~0x3F);
8360                 rf_val |= 0x3F;
8361                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
8362                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
8363         } else {
8364                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
8365                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
8366                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
8367                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8368                 rf_val &= (~0x3F);
8369                 rf_val |= 0x34;
8370                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
8371                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8372                 rf_val &= (~0x3F);
8373                 rf_val |= 0x34;
8374                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
8375         }
8376
8377         return 0;
8378 }
8379
8380 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
8381 {
8382         unsigned int cnt;
8383         u8 bbp_val;
8384         char cal_val;
8385
8386         rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
8387
8388         cnt = 0;
8389         do {
8390                 usleep_range(500, 2000);
8391                 bbp_val = rt2800_bbp_read(rt2x00dev, 159);
8392                 if (bbp_val == 0x02 || cnt == 20)
8393                         break;
8394
8395                 cnt++;
8396         } while (cnt < 20);
8397
8398         bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39);
8399         cal_val = bbp_val & 0x7F;
8400         if (cal_val >= 0x40)
8401                 cal_val -= 128;
8402
8403         return cal_val;
8404 }
8405
8406 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
8407                                          bool btxcal)
8408 {
8409         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8410         u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
8411         u8 filter_target;
8412         u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
8413         u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
8414         int loop = 0, is_ht40, cnt;
8415         u8 bbp_val, rf_val;
8416         char cal_r32_init, cal_r32_val, cal_diff;
8417         u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
8418         u8 saverfb5r06, saverfb5r07;
8419         u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
8420         u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
8421         u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
8422         u8 saverfb5r58, saverfb5r59;
8423         u8 savebbp159r0, savebbp159r2, savebbpr23;
8424         u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
8425
8426         /* Save MAC registers */
8427         MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8428         MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8429
8430         /* save BBP registers */
8431         savebbpr23 = rt2800_bbp_read(rt2x00dev, 23);
8432
8433         savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0);
8434         savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8435
8436         /* Save RF registers */
8437         saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8438         saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8439         saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8440         saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8441         saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
8442         saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8443         saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8444         saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
8445         saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8446         saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
8447         saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
8448         saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
8449
8450         saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
8451         saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
8452         saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
8453         saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
8454         saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
8455         saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
8456         saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
8457         saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
8458         saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
8459         saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
8460
8461         saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8462         saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8463
8464         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8465         rf_val |= 0x3;
8466         rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
8467
8468         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8469         rf_val |= 0x1;
8470         rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
8471
8472         cnt = 0;
8473         do {
8474                 usleep_range(500, 2000);
8475                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8476                 if (((rf_val & 0x1) == 0x00) || (cnt == 40))
8477                         break;
8478                 cnt++;
8479         } while (cnt < 40);
8480
8481         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
8482         rf_val &= (~0x3);
8483         rf_val |= 0x1;
8484         rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
8485
8486         /* I-3 */
8487         bbp_val = rt2800_bbp_read(rt2x00dev, 23);
8488         bbp_val &= (~0x1F);
8489         bbp_val |= 0x10;
8490         rt2800_bbp_write(rt2x00dev, 23, bbp_val);
8491
8492         do {
8493                 /* I-4,5,6,7,8,9 */
8494                 if (loop == 0) {
8495                         is_ht40 = false;
8496
8497                         if (btxcal)
8498                                 filter_target = tx_filter_target_20m;
8499                         else
8500                                 filter_target = rx_filter_target_20m;
8501                 } else {
8502                         is_ht40 = true;
8503
8504                         if (btxcal)
8505                                 filter_target = tx_filter_target_40m;
8506                         else
8507                                 filter_target = rx_filter_target_40m;
8508                 }
8509
8510                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
8511                 rf_val &= (~0x04);
8512                 if (loop == 1)
8513                         rf_val |= 0x4;
8514
8515                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
8516
8517                 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
8518
8519                 rt2800_rf_lp_config(rt2x00dev, btxcal);
8520                 if (btxcal) {
8521                         tx_agc_fc = 0;
8522                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8523                         rf_val &= (~0x7F);
8524                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
8525                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8526                         rf_val &= (~0x7F);
8527                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
8528                 } else {
8529                         rx_agc_fc = 0;
8530                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8531                         rf_val &= (~0x7F);
8532                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
8533                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8534                         rf_val &= (~0x7F);
8535                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
8536                 }
8537
8538                 usleep_range(1000, 2000);
8539
8540                 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8541                 bbp_val &= (~0x6);
8542                 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
8543
8544                 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
8545
8546                 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
8547
8548                 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
8549                 bbp_val |= 0x6;
8550                 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
8551 do_cal:
8552                 if (btxcal) {
8553                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
8554                         rf_val &= (~0x7F);
8555                         rf_val |= tx_agc_fc;
8556                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
8557                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
8558                         rf_val &= (~0x7F);
8559                         rf_val |= tx_agc_fc;
8560                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
8561                 } else {
8562                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
8563                         rf_val &= (~0x7F);
8564                         rf_val |= rx_agc_fc;
8565                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
8566                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
8567                         rf_val &= (~0x7F);
8568                         rf_val |= rx_agc_fc;
8569                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
8570                 }
8571
8572                 usleep_range(500, 1000);
8573
8574                 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
8575
8576                 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
8577
8578                 cal_diff = cal_r32_init - cal_r32_val;
8579
8580                 if (btxcal)
8581                         cmm_agc_fc = tx_agc_fc;
8582                 else
8583                         cmm_agc_fc = rx_agc_fc;
8584
8585                 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
8586                     ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
8587                         if (btxcal)
8588                                 tx_agc_fc = 0;
8589                         else
8590                                 rx_agc_fc = 0;
8591                 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
8592                         if (btxcal)
8593                                 tx_agc_fc++;
8594                         else
8595                                 rx_agc_fc++;
8596                         goto do_cal;
8597                 }
8598
8599                 if (btxcal) {
8600                         if (loop == 0)
8601                                 drv_data->tx_calibration_bw20 = tx_agc_fc;
8602                         else
8603                                 drv_data->tx_calibration_bw40 = tx_agc_fc;
8604                 } else {
8605                         if (loop == 0)
8606                                 drv_data->rx_calibration_bw20 = rx_agc_fc;
8607                         else
8608                                 drv_data->rx_calibration_bw40 = rx_agc_fc;
8609                 }
8610
8611                 loop++;
8612         } while (loop <= 1);
8613
8614         rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
8615         rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
8616         rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
8617         rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
8618         rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
8619         rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
8620         rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
8621         rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
8622         rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
8623         rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
8624         rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
8625         rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
8626
8627         rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
8628         rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
8629         rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
8630         rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
8631         rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
8632         rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
8633         rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
8634         rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
8635         rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
8636         rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
8637
8638         rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
8639         rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
8640
8641         rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
8642
8643         rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
8644         rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
8645
8646         bbp_val = rt2800_bbp_read(rt2x00dev, 4);
8647         rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
8648                           2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
8649         rt2800_bbp_write(rt2x00dev, 4, bbp_val);
8650
8651         rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
8652         rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
8653 }
8654
8655 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
8656 {
8657         /* Initialize RF central register to default value */
8658         rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
8659         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8660         rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
8661         rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
8662         rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
8663         rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
8664         rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
8665         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8666         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
8667         rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
8668         rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
8669         rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
8670         rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
8671         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8672         rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
8673         rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
8674         rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
8675         rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
8676         rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
8677         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8678         rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
8679         rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
8680         rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
8681         rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
8682         rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
8683         rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
8684         rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
8685         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8686         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8687         rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
8688         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
8689         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
8690         rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
8691         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8692         rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
8693         rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8694         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8695         rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8696         rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
8697         rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
8698         rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8699         rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
8700         rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
8701         rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8702
8703         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
8704         if (rt2800_clk_is_20mhz(rt2x00dev))
8705                 rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
8706         else
8707                 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8708         rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
8709         rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
8710         rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
8711         rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
8712         rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
8713         rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
8714         rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
8715         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
8716         rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
8717         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8718         rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8719         rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
8720         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8721         rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
8722         rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
8723         rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
8724
8725         rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
8726         rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
8727         rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
8728
8729         /* Initialize RF channel register to default value */
8730         rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
8731         rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
8732         rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
8733         rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
8734         rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
8735         rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
8736         rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
8737         rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
8738         rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
8739         rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
8740         rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
8741         rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8742         rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
8743         rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
8744         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8745         rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
8746         rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
8747         rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
8748         rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
8749         rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8750         rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
8751         rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
8752         rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
8753         rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
8754         rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
8755         rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
8756         rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
8757         rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
8758         rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
8759         rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
8760         rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
8761         rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
8762         rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
8763         rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
8764         rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
8765         rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
8766         rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
8767         rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
8768         rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
8769         rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
8770         rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
8771         rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
8772         rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
8773         rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
8774         rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
8775         rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8776         rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
8777         rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
8778         rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
8779         rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
8780         rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
8781         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
8782         rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
8783         rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
8784         rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
8785         rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
8786         rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
8787         rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
8788         rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
8789         rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
8790
8791         rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
8792
8793         rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
8794         rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
8795         rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
8796         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
8797         rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
8798         rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
8799         rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
8800         rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
8801         rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
8802         rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
8803         rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
8804         rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
8805         rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
8806         rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
8807         rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8808         rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
8809         rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8810         rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
8811         rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
8812         rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
8813         rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
8814         rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
8815         rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
8816         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8817         rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
8818         rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
8819         rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
8820         rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8821         rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
8822         rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
8823
8824         rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
8825         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8826         rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8827         rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
8828         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
8829         rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
8830         rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
8831         rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8832         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
8833
8834         rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
8835         rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
8836         rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
8837         rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
8838         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8839         rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8840
8841         /* Initialize RF channel register for DRQFN */
8842         rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8843         rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
8844         rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
8845         rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
8846         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
8847         rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
8848         rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
8849         rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
8850
8851         /* Initialize RF DC calibration register to default value */
8852         rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
8853         rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
8854         rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
8855         rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
8856         rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
8857         rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8858         rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
8859         rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
8860         rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
8861         rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
8862         rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
8863         rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
8864         rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
8865         rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
8866         rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
8867         rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
8868         rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
8869         rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
8870         rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
8871         rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
8872         rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8873         rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
8874         rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
8875         rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
8876         rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
8877         rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
8878         rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
8879         rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
8880         rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
8881         rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
8882         rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
8883         rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
8884         rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
8885         rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
8886         rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
8887         rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
8888         rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
8889         rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
8890         rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
8891         rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
8892         rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
8893         rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
8894         rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
8895         rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
8896         rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
8897         rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
8898         rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
8899         rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
8900         rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
8901         rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
8902         rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
8903         rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
8904         rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
8905         rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
8906         rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
8907         rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
8908         rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
8909         rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
8910         rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
8911
8912         rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
8913         rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
8914         rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
8915
8916         rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8917         rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
8918
8919         rt2800_bw_filter_calibration(rt2x00dev, true);
8920         rt2800_bw_filter_calibration(rt2x00dev, false);
8921 }
8922
8923 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
8924 {
8925         if (rt2800_is_305x_soc(rt2x00dev)) {
8926                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
8927                 return;
8928         }
8929
8930         switch (rt2x00dev->chip.rt) {
8931         case RT3070:
8932         case RT3071:
8933         case RT3090:
8934                 rt2800_init_rfcsr_30xx(rt2x00dev);
8935                 break;
8936         case RT3290:
8937                 rt2800_init_rfcsr_3290(rt2x00dev);
8938                 break;
8939         case RT3352:
8940                 rt2800_init_rfcsr_3352(rt2x00dev);
8941                 break;
8942         case RT3390:
8943                 rt2800_init_rfcsr_3390(rt2x00dev);
8944                 break;
8945         case RT3883:
8946                 rt2800_init_rfcsr_3883(rt2x00dev);
8947                 break;
8948         case RT3572:
8949                 rt2800_init_rfcsr_3572(rt2x00dev);
8950                 break;
8951         case RT3593:
8952                 rt2800_init_rfcsr_3593(rt2x00dev);
8953                 break;
8954         case RT5350:
8955                 rt2800_init_rfcsr_5350(rt2x00dev);
8956                 break;
8957         case RT5390:
8958                 rt2800_init_rfcsr_5390(rt2x00dev);
8959                 break;
8960         case RT5392:
8961                 rt2800_init_rfcsr_5392(rt2x00dev);
8962                 break;
8963         case RT5592:
8964                 rt2800_init_rfcsr_5592(rt2x00dev);
8965                 break;
8966         case RT6352:
8967                 rt2800_init_rfcsr_6352(rt2x00dev);
8968                 break;
8969         }
8970 }
8971
8972 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
8973 {
8974         u32 reg;
8975         u16 word;
8976
8977         /*
8978          * Initialize MAC registers.
8979          */
8980         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
8981                      rt2800_init_registers(rt2x00dev)))
8982                 return -EIO;
8983
8984         /*
8985          * Wait BBP/RF to wake up.
8986          */
8987         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
8988                 return -EIO;
8989
8990         /*
8991          * Send signal during boot time to initialize firmware.
8992          */
8993         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
8994         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8995         if (rt2x00_is_usb(rt2x00dev))
8996                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8997         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
8998         msleep(1);
8999
9000         /*
9001          * Make sure BBP is up and running.
9002          */
9003         if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
9004                 return -EIO;
9005
9006         /*
9007          * Initialize BBP/RF registers.
9008          */
9009         rt2800_init_bbp(rt2x00dev);
9010         rt2800_init_rfcsr(rt2x00dev);
9011
9012         if (rt2x00_is_usb(rt2x00dev) &&
9013             (rt2x00_rt(rt2x00dev, RT3070) ||
9014              rt2x00_rt(rt2x00dev, RT3071) ||
9015              rt2x00_rt(rt2x00dev, RT3572))) {
9016                 udelay(200);
9017                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
9018                 udelay(10);
9019         }
9020
9021         /*
9022          * Enable RX.
9023          */
9024         reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9025         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
9026         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9027         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9028
9029         udelay(50);
9030
9031         reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
9032         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
9033         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
9034         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
9035         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
9036
9037         reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9038         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
9039         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
9040         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9041
9042         /*
9043          * Initialize LED control
9044          */
9045         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF);
9046         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
9047                            word & 0xff, (word >> 8) & 0xff);
9048
9049         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF);
9050         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
9051                            word & 0xff, (word >> 8) & 0xff);
9052
9053         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY);
9054         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
9055                            word & 0xff, (word >> 8) & 0xff);
9056
9057         return 0;
9058 }
9059 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
9060
9061 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
9062 {
9063         u32 reg;
9064
9065         rt2800_disable_wpdma(rt2x00dev);
9066
9067         /* Wait for DMA, ignore error */
9068         rt2800_wait_wpdma_ready(rt2x00dev);
9069
9070         reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9071         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
9072         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
9073         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
9074 }
9075 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
9076
9077 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
9078 {
9079         u32 reg;
9080         u16 efuse_ctrl_reg;
9081
9082         if (rt2x00_rt(rt2x00dev, RT3290))
9083                 efuse_ctrl_reg = EFUSE_CTRL_3290;
9084         else
9085                 efuse_ctrl_reg = EFUSE_CTRL;
9086
9087         reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg);
9088         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
9089 }
9090 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
9091
9092 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
9093 {
9094         u32 reg;
9095         u16 efuse_ctrl_reg;
9096         u16 efuse_data0_reg;
9097         u16 efuse_data1_reg;
9098         u16 efuse_data2_reg;
9099         u16 efuse_data3_reg;
9100
9101         if (rt2x00_rt(rt2x00dev, RT3290)) {
9102                 efuse_ctrl_reg = EFUSE_CTRL_3290;
9103                 efuse_data0_reg = EFUSE_DATA0_3290;
9104                 efuse_data1_reg = EFUSE_DATA1_3290;
9105                 efuse_data2_reg = EFUSE_DATA2_3290;
9106                 efuse_data3_reg = EFUSE_DATA3_3290;
9107         } else {
9108                 efuse_ctrl_reg = EFUSE_CTRL;
9109                 efuse_data0_reg = EFUSE_DATA0;
9110                 efuse_data1_reg = EFUSE_DATA1;
9111                 efuse_data2_reg = EFUSE_DATA2;
9112                 efuse_data3_reg = EFUSE_DATA3;
9113         }
9114         mutex_lock(&rt2x00dev->csr_mutex);
9115
9116         reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg);
9117         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
9118         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
9119         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
9120         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
9121
9122         /* Wait until the EEPROM has been loaded */
9123         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
9124         /* Apparently the data is read from end to start */
9125         reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg);
9126         /* The returned value is in CPU order, but eeprom is le */
9127         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
9128         reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg);
9129         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
9130         reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg);
9131         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
9132         reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg);
9133         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
9134
9135         mutex_unlock(&rt2x00dev->csr_mutex);
9136 }
9137
9138 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
9139 {
9140         unsigned int i;
9141
9142         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
9143                 rt2800_efuse_read(rt2x00dev, i);
9144
9145         return 0;
9146 }
9147 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
9148
9149 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
9150 {
9151         u16 word;
9152
9153         if (rt2x00_rt(rt2x00dev, RT3593) ||
9154             rt2x00_rt(rt2x00dev, RT3883))
9155                 return 0;
9156
9157         word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
9158         if ((word & 0x00ff) != 0x00ff)
9159                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
9160
9161         return 0;
9162 }
9163
9164 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
9165 {
9166         u16 word;
9167
9168         if (rt2x00_rt(rt2x00dev, RT3593) ||
9169             rt2x00_rt(rt2x00dev, RT3883))
9170                 return 0;
9171
9172         word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
9173         if ((word & 0x00ff) != 0x00ff)
9174                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
9175
9176         return 0;
9177 }
9178
9179 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
9180 {
9181         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
9182         u16 word;
9183         u8 *mac;
9184         u8 default_lna_gain;
9185         int retval;
9186
9187         /*
9188          * Read the EEPROM.
9189          */
9190         retval = rt2800_read_eeprom(rt2x00dev);
9191         if (retval)
9192                 return retval;
9193
9194         /*
9195          * Start validation of the data that has been read.
9196          */
9197         mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
9198         rt2x00lib_set_mac_address(rt2x00dev, mac);
9199
9200         word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
9201         if (word == 0xffff) {
9202                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
9203                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
9204                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
9205                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
9206                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
9207         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
9208                    rt2x00_rt(rt2x00dev, RT2872)) {
9209                 /*
9210                  * There is a max of 2 RX streams for RT28x0 series
9211                  */
9212                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
9213                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
9214                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
9215         }
9216
9217         word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9218         if (word == 0xffff) {
9219                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
9220                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
9221                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
9222                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
9223                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
9224                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
9225                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
9226                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
9227                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
9228                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
9229                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
9230                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
9231                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
9232                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
9233                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
9234                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
9235                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
9236         }
9237
9238         word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
9239         if ((word & 0x00ff) == 0x00ff) {
9240                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
9241                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
9242                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
9243         }
9244         if ((word & 0xff00) == 0xff00) {
9245                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
9246                                    LED_MODE_TXRX_ACTIVITY);
9247                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
9248                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
9249                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
9250                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
9251                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
9252                 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
9253         }
9254
9255         /*
9256          * During the LNA validation we are going to use
9257          * lna0 as correct value. Note that EEPROM_LNA
9258          * is never validated.
9259          */
9260         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
9261         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
9262
9263         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
9264         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
9265                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
9266         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
9267                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
9268         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
9269
9270         drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
9271
9272         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
9273         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
9274                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
9275         if (!rt2x00_rt(rt2x00dev, RT3593) &&
9276             !rt2x00_rt(rt2x00dev, RT3883)) {
9277                 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
9278                     rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
9279                         rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
9280                                            default_lna_gain);
9281         }
9282         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
9283
9284         drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
9285
9286         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
9287         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
9288                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
9289         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
9290                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
9291         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
9292
9293         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
9294         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
9295                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
9296         if (!rt2x00_rt(rt2x00dev, RT3593) &&
9297             !rt2x00_rt(rt2x00dev, RT3883)) {
9298                 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
9299                     rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
9300                         rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
9301                                            default_lna_gain);
9302         }
9303         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
9304
9305         if (rt2x00_rt(rt2x00dev, RT3593) ||
9306             rt2x00_rt(rt2x00dev, RT3883)) {
9307                 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
9308                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
9309                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
9310                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
9311                                            default_lna_gain);
9312                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
9313                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
9314                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
9315                                            default_lna_gain);
9316                 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
9317         }
9318
9319         return 0;
9320 }
9321
9322 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
9323 {
9324         u16 value;
9325         u16 eeprom;
9326         u16 rf;
9327
9328         /*
9329          * Read EEPROM word for configuration.
9330          */
9331         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
9332
9333         /*
9334          * Identify RF chipset by EEPROM value
9335          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
9336          * RT53xx: defined in "EEPROM_CHIP_ID" field
9337          */
9338         if (rt2x00_rt(rt2x00dev, RT3290) ||
9339             rt2x00_rt(rt2x00dev, RT5390) ||
9340             rt2x00_rt(rt2x00dev, RT5392) ||
9341             rt2x00_rt(rt2x00dev, RT6352))
9342                 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
9343         else if (rt2x00_rt(rt2x00dev, RT3352))
9344                 rf = RF3322;
9345         else if (rt2x00_rt(rt2x00dev, RT3883))
9346                 rf = RF3853;
9347         else if (rt2x00_rt(rt2x00dev, RT5350))
9348                 rf = RF5350;
9349         else
9350                 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
9351
9352         switch (rf) {
9353         case RF2820:
9354         case RF2850:
9355         case RF2720:
9356         case RF2750:
9357         case RF3020:
9358         case RF2020:
9359         case RF3021:
9360         case RF3022:
9361         case RF3052:
9362         case RF3053:
9363         case RF3070:
9364         case RF3290:
9365         case RF3320:
9366         case RF3322:
9367         case RF3853:
9368         case RF5350:
9369         case RF5360:
9370         case RF5362:
9371         case RF5370:
9372         case RF5372:
9373         case RF5390:
9374         case RF5392:
9375         case RF5592:
9376         case RF7620:
9377                 break;
9378         default:
9379                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
9380                            rf);
9381                 return -ENODEV;
9382         }
9383
9384         rt2x00_set_rf(rt2x00dev, rf);
9385
9386         /*
9387          * Identify default antenna configuration.
9388          */
9389         rt2x00dev->default_ant.tx_chain_num =
9390             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
9391         rt2x00dev->default_ant.rx_chain_num =
9392             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
9393
9394         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9395
9396         if (rt2x00_rt(rt2x00dev, RT3070) ||
9397             rt2x00_rt(rt2x00dev, RT3090) ||
9398             rt2x00_rt(rt2x00dev, RT3352) ||
9399             rt2x00_rt(rt2x00dev, RT3390)) {
9400                 value = rt2x00_get_field16(eeprom,
9401                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
9402                 switch (value) {
9403                 case 0:
9404                 case 1:
9405                 case 2:
9406                         rt2x00dev->default_ant.tx = ANTENNA_A;
9407                         rt2x00dev->default_ant.rx = ANTENNA_A;
9408                         break;
9409                 case 3:
9410                         rt2x00dev->default_ant.tx = ANTENNA_A;
9411                         rt2x00dev->default_ant.rx = ANTENNA_B;
9412                         break;
9413                 }
9414         } else {
9415                 rt2x00dev->default_ant.tx = ANTENNA_A;
9416                 rt2x00dev->default_ant.rx = ANTENNA_A;
9417         }
9418
9419         /* These chips have hardware RX antenna diversity */
9420         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
9421             rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
9422                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
9423                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
9424         }
9425
9426         /*
9427          * Determine external LNA informations.
9428          */
9429         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
9430                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
9431         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
9432                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
9433
9434         /*
9435          * Detect if this device has an hardware controlled radio.
9436          */
9437         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
9438                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
9439
9440         /*
9441          * Detect if this device has Bluetooth co-existence.
9442          */
9443         if (!rt2x00_rt(rt2x00dev, RT3352) &&
9444             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
9445                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
9446
9447         /*
9448          * Read frequency offset and RF programming sequence.
9449          */
9450         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
9451         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
9452
9453         /*
9454          * Store led settings, for correct led behaviour.
9455          */
9456 #ifdef CONFIG_RT2X00_LIB_LEDS
9457         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
9458         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
9459         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
9460
9461         rt2x00dev->led_mcu_reg = eeprom;
9462 #endif /* CONFIG_RT2X00_LIB_LEDS */
9463
9464         /*
9465          * Check if support EIRP tx power limit feature.
9466          */
9467         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
9468
9469         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
9470                                         EIRP_MAX_TX_POWER_LIMIT)
9471                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
9472
9473         /*
9474          * Detect if device uses internal or external PA
9475          */
9476         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
9477
9478         if (rt2x00_rt(rt2x00dev, RT3352)) {
9479                 if (rt2x00_get_field16(eeprom,
9480                     EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
9481                     __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
9482                               &rt2x00dev->cap_flags);
9483                 if (rt2x00_get_field16(eeprom,
9484                     EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352))
9485                     __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
9486                               &rt2x00dev->cap_flags);
9487         }
9488
9489         return 0;
9490 }
9491
9492 /*
9493  * RF value list for rt28xx
9494  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
9495  */
9496 static const struct rf_channel rf_vals[] = {
9497         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
9498         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
9499         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
9500         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
9501         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
9502         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
9503         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
9504         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
9505         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
9506         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
9507         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
9508         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
9509         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
9510         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
9511
9512         /* 802.11 UNI / HyperLan 2 */
9513         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
9514         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
9515         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
9516         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
9517         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
9518         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
9519         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
9520         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
9521         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
9522         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
9523         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
9524         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
9525
9526         /* 802.11 HyperLan 2 */
9527         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
9528         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
9529         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
9530         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
9531         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
9532         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
9533         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
9534         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
9535         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
9536         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
9537         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
9538         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
9539         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
9540         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
9541         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
9542         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
9543
9544         /* 802.11 UNII */
9545         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
9546         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
9547         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
9548         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
9549         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
9550         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
9551         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
9552         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
9553         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
9554         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
9555         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
9556
9557         /* 802.11 Japan */
9558         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
9559         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
9560         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
9561         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
9562         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
9563         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
9564         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
9565 };
9566
9567 /*
9568  * RF value list for rt3xxx
9569  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
9570  */
9571 static const struct rf_channel rf_vals_3x[] = {
9572         {1,  241, 2, 2 },
9573         {2,  241, 2, 7 },
9574         {3,  242, 2, 2 },
9575         {4,  242, 2, 7 },
9576         {5,  243, 2, 2 },
9577         {6,  243, 2, 7 },
9578         {7,  244, 2, 2 },
9579         {8,  244, 2, 7 },
9580         {9,  245, 2, 2 },
9581         {10, 245, 2, 7 },
9582         {11, 246, 2, 2 },
9583         {12, 246, 2, 7 },
9584         {13, 247, 2, 2 },
9585         {14, 248, 2, 4 },
9586
9587         /* 802.11 UNI / HyperLan 2 */
9588         {36, 0x56, 0, 4},
9589         {38, 0x56, 0, 6},
9590         {40, 0x56, 0, 8},
9591         {44, 0x57, 0, 0},
9592         {46, 0x57, 0, 2},
9593         {48, 0x57, 0, 4},
9594         {52, 0x57, 0, 8},
9595         {54, 0x57, 0, 10},
9596         {56, 0x58, 0, 0},
9597         {60, 0x58, 0, 4},
9598         {62, 0x58, 0, 6},
9599         {64, 0x58, 0, 8},
9600
9601         /* 802.11 HyperLan 2 */
9602         {100, 0x5b, 0, 8},
9603         {102, 0x5b, 0, 10},
9604         {104, 0x5c, 0, 0},
9605         {108, 0x5c, 0, 4},
9606         {110, 0x5c, 0, 6},
9607         {112, 0x5c, 0, 8},
9608         {116, 0x5d, 0, 0},
9609         {118, 0x5d, 0, 2},
9610         {120, 0x5d, 0, 4},
9611         {124, 0x5d, 0, 8},
9612         {126, 0x5d, 0, 10},
9613         {128, 0x5e, 0, 0},
9614         {132, 0x5e, 0, 4},
9615         {134, 0x5e, 0, 6},
9616         {136, 0x5e, 0, 8},
9617         {140, 0x5f, 0, 0},
9618
9619         /* 802.11 UNII */
9620         {149, 0x5f, 0, 9},
9621         {151, 0x5f, 0, 11},
9622         {153, 0x60, 0, 1},
9623         {157, 0x60, 0, 5},
9624         {159, 0x60, 0, 7},
9625         {161, 0x60, 0, 9},
9626         {165, 0x61, 0, 1},
9627         {167, 0x61, 0, 3},
9628         {169, 0x61, 0, 5},
9629         {171, 0x61, 0, 7},
9630         {173, 0x61, 0, 9},
9631 };
9632
9633 /*
9634  * RF value list for rt3xxx with Xtal20MHz
9635  * Supports: 2.4 GHz (all) (RF3322)
9636  */
9637 static const struct rf_channel rf_vals_3x_xtal20[] = {
9638         {1,    0xE2,     2,  0x14},
9639         {2,    0xE3,     2,  0x14},
9640         {3,    0xE4,     2,  0x14},
9641         {4,    0xE5,     2,  0x14},
9642         {5,    0xE6,     2,  0x14},
9643         {6,    0xE7,     2,  0x14},
9644         {7,    0xE8,     2,  0x14},
9645         {8,    0xE9,     2,  0x14},
9646         {9,    0xEA,     2,  0x14},
9647         {10,   0xEB,     2,  0x14},
9648         {11,   0xEC,     2,  0x14},
9649         {12,   0xED,     2,  0x14},
9650         {13,   0xEE,     2,  0x14},
9651         {14,   0xF0,     2,  0x18},
9652 };
9653
9654 static const struct rf_channel rf_vals_3853[] = {
9655         {1,  241, 6, 2},
9656         {2,  241, 6, 7},
9657         {3,  242, 6, 2},
9658         {4,  242, 6, 7},
9659         {5,  243, 6, 2},
9660         {6,  243, 6, 7},
9661         {7,  244, 6, 2},
9662         {8,  244, 6, 7},
9663         {9,  245, 6, 2},
9664         {10, 245, 6, 7},
9665         {11, 246, 6, 2},
9666         {12, 246, 6, 7},
9667         {13, 247, 6, 2},
9668         {14, 248, 6, 4},
9669
9670         {36, 0x56, 8, 4},
9671         {38, 0x56, 8, 6},
9672         {40, 0x56, 8, 8},
9673         {44, 0x57, 8, 0},
9674         {46, 0x57, 8, 2},
9675         {48, 0x57, 8, 4},
9676         {52, 0x57, 8, 8},
9677         {54, 0x57, 8, 10},
9678         {56, 0x58, 8, 0},
9679         {60, 0x58, 8, 4},
9680         {62, 0x58, 8, 6},
9681         {64, 0x58, 8, 8},
9682
9683         {100, 0x5b, 8, 8},
9684         {102, 0x5b, 8, 10},
9685         {104, 0x5c, 8, 0},
9686         {108, 0x5c, 8, 4},
9687         {110, 0x5c, 8, 6},
9688         {112, 0x5c, 8, 8},
9689         {114, 0x5c, 8, 10},
9690         {116, 0x5d, 8, 0},
9691         {118, 0x5d, 8, 2},
9692         {120, 0x5d, 8, 4},
9693         {124, 0x5d, 8, 8},
9694         {126, 0x5d, 8, 10},
9695         {128, 0x5e, 8, 0},
9696         {132, 0x5e, 8, 4},
9697         {134, 0x5e, 8, 6},
9698         {136, 0x5e, 8, 8},
9699         {140, 0x5f, 8, 0},
9700
9701         {149, 0x5f, 8, 9},
9702         {151, 0x5f, 8, 11},
9703         {153, 0x60, 8, 1},
9704         {157, 0x60, 8, 5},
9705         {159, 0x60, 8, 7},
9706         {161, 0x60, 8, 9},
9707         {165, 0x61, 8, 1},
9708         {167, 0x61, 8, 3},
9709         {169, 0x61, 8, 5},
9710         {171, 0x61, 8, 7},
9711         {173, 0x61, 8, 9},
9712 };
9713
9714 static const struct rf_channel rf_vals_5592_xtal20[] = {
9715         /* Channel, N, K, mod, R */
9716         {1, 482, 4, 10, 3},
9717         {2, 483, 4, 10, 3},
9718         {3, 484, 4, 10, 3},
9719         {4, 485, 4, 10, 3},
9720         {5, 486, 4, 10, 3},
9721         {6, 487, 4, 10, 3},
9722         {7, 488, 4, 10, 3},
9723         {8, 489, 4, 10, 3},
9724         {9, 490, 4, 10, 3},
9725         {10, 491, 4, 10, 3},
9726         {11, 492, 4, 10, 3},
9727         {12, 493, 4, 10, 3},
9728         {13, 494, 4, 10, 3},
9729         {14, 496, 8, 10, 3},
9730         {36, 172, 8, 12, 1},
9731         {38, 173, 0, 12, 1},
9732         {40, 173, 4, 12, 1},
9733         {42, 173, 8, 12, 1},
9734         {44, 174, 0, 12, 1},
9735         {46, 174, 4, 12, 1},
9736         {48, 174, 8, 12, 1},
9737         {50, 175, 0, 12, 1},
9738         {52, 175, 4, 12, 1},
9739         {54, 175, 8, 12, 1},
9740         {56, 176, 0, 12, 1},
9741         {58, 176, 4, 12, 1},
9742         {60, 176, 8, 12, 1},
9743         {62, 177, 0, 12, 1},
9744         {64, 177, 4, 12, 1},
9745         {100, 183, 4, 12, 1},
9746         {102, 183, 8, 12, 1},
9747         {104, 184, 0, 12, 1},
9748         {106, 184, 4, 12, 1},
9749         {108, 184, 8, 12, 1},
9750         {110, 185, 0, 12, 1},
9751         {112, 185, 4, 12, 1},
9752         {114, 185, 8, 12, 1},
9753         {116, 186, 0, 12, 1},
9754         {118, 186, 4, 12, 1},
9755         {120, 186, 8, 12, 1},
9756         {122, 187, 0, 12, 1},
9757         {124, 187, 4, 12, 1},
9758         {126, 187, 8, 12, 1},
9759         {128, 188, 0, 12, 1},
9760         {130, 188, 4, 12, 1},
9761         {132, 188, 8, 12, 1},
9762         {134, 189, 0, 12, 1},
9763         {136, 189, 4, 12, 1},
9764         {138, 189, 8, 12, 1},
9765         {140, 190, 0, 12, 1},
9766         {149, 191, 6, 12, 1},
9767         {151, 191, 10, 12, 1},
9768         {153, 192, 2, 12, 1},
9769         {155, 192, 6, 12, 1},
9770         {157, 192, 10, 12, 1},
9771         {159, 193, 2, 12, 1},
9772         {161, 193, 6, 12, 1},
9773         {165, 194, 2, 12, 1},
9774         {184, 164, 0, 12, 1},
9775         {188, 164, 4, 12, 1},
9776         {192, 165, 8, 12, 1},
9777         {196, 166, 0, 12, 1},
9778 };
9779
9780 static const struct rf_channel rf_vals_5592_xtal40[] = {
9781         /* Channel, N, K, mod, R */
9782         {1, 241, 2, 10, 3},
9783         {2, 241, 7, 10, 3},
9784         {3, 242, 2, 10, 3},
9785         {4, 242, 7, 10, 3},
9786         {5, 243, 2, 10, 3},
9787         {6, 243, 7, 10, 3},
9788         {7, 244, 2, 10, 3},
9789         {8, 244, 7, 10, 3},
9790         {9, 245, 2, 10, 3},
9791         {10, 245, 7, 10, 3},
9792         {11, 246, 2, 10, 3},
9793         {12, 246, 7, 10, 3},
9794         {13, 247, 2, 10, 3},
9795         {14, 248, 4, 10, 3},
9796         {36, 86, 4, 12, 1},
9797         {38, 86, 6, 12, 1},
9798         {40, 86, 8, 12, 1},
9799         {42, 86, 10, 12, 1},
9800         {44, 87, 0, 12, 1},
9801         {46, 87, 2, 12, 1},
9802         {48, 87, 4, 12, 1},
9803         {50, 87, 6, 12, 1},
9804         {52, 87, 8, 12, 1},
9805         {54, 87, 10, 12, 1},
9806         {56, 88, 0, 12, 1},
9807         {58, 88, 2, 12, 1},
9808         {60, 88, 4, 12, 1},
9809         {62, 88, 6, 12, 1},
9810         {64, 88, 8, 12, 1},
9811         {100, 91, 8, 12, 1},
9812         {102, 91, 10, 12, 1},
9813         {104, 92, 0, 12, 1},
9814         {106, 92, 2, 12, 1},
9815         {108, 92, 4, 12, 1},
9816         {110, 92, 6, 12, 1},
9817         {112, 92, 8, 12, 1},
9818         {114, 92, 10, 12, 1},
9819         {116, 93, 0, 12, 1},
9820         {118, 93, 2, 12, 1},
9821         {120, 93, 4, 12, 1},
9822         {122, 93, 6, 12, 1},
9823         {124, 93, 8, 12, 1},
9824         {126, 93, 10, 12, 1},
9825         {128, 94, 0, 12, 1},
9826         {130, 94, 2, 12, 1},
9827         {132, 94, 4, 12, 1},
9828         {134, 94, 6, 12, 1},
9829         {136, 94, 8, 12, 1},
9830         {138, 94, 10, 12, 1},
9831         {140, 95, 0, 12, 1},
9832         {149, 95, 9, 12, 1},
9833         {151, 95, 11, 12, 1},
9834         {153, 96, 1, 12, 1},
9835         {155, 96, 3, 12, 1},
9836         {157, 96, 5, 12, 1},
9837         {159, 96, 7, 12, 1},
9838         {161, 96, 9, 12, 1},
9839         {165, 97, 1, 12, 1},
9840         {184, 82, 0, 12, 1},
9841         {188, 82, 4, 12, 1},
9842         {192, 82, 8, 12, 1},
9843         {196, 83, 0, 12, 1},
9844 };
9845
9846 static const struct rf_channel rf_vals_7620[] = {
9847         {1, 0x50, 0x99, 0x99, 1},
9848         {2, 0x50, 0x44, 0x44, 2},
9849         {3, 0x50, 0xEE, 0xEE, 2},
9850         {4, 0x50, 0x99, 0x99, 3},
9851         {5, 0x51, 0x44, 0x44, 0},
9852         {6, 0x51, 0xEE, 0xEE, 0},
9853         {7, 0x51, 0x99, 0x99, 1},
9854         {8, 0x51, 0x44, 0x44, 2},
9855         {9, 0x51, 0xEE, 0xEE, 2},
9856         {10, 0x51, 0x99, 0x99, 3},
9857         {11, 0x52, 0x44, 0x44, 0},
9858         {12, 0x52, 0xEE, 0xEE, 0},
9859         {13, 0x52, 0x99, 0x99, 1},
9860         {14, 0x52, 0x33, 0x33, 3},
9861 };
9862
9863 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
9864 {
9865         struct hw_mode_spec *spec = &rt2x00dev->spec;
9866         struct channel_info *info;
9867         char *default_power1;
9868         char *default_power2;
9869         char *default_power3;
9870         unsigned int i, tx_chains, rx_chains;
9871         u32 reg;
9872
9873         /*
9874          * Disable powersaving as default.
9875          */
9876         rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
9877
9878         /*
9879          * Change default retry settings to values corresponding more closely
9880          * to rate[0].count setting of minstrel rate control algorithm.
9881          */
9882         rt2x00dev->hw->wiphy->retry_short = 2;
9883         rt2x00dev->hw->wiphy->retry_long = 2;
9884
9885         /*
9886          * Initialize all hw fields.
9887          */
9888         ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
9889         ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
9890         ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
9891         ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
9892         ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
9893
9894         /*
9895          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
9896          * unless we are capable of sending the buffered frames out after the
9897          * DTIM transmission using rt2x00lib_beacondone. This will send out
9898          * multicast and broadcast traffic immediately instead of buffering it
9899          * infinitly and thus dropping it after some time.
9900          */
9901         if (!rt2x00_is_usb(rt2x00dev))
9902                 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
9903
9904         /* Set MFP if HW crypto is disabled. */
9905         if (rt2800_hwcrypt_disabled(rt2x00dev))
9906                 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
9907
9908         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
9909         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
9910                                 rt2800_eeprom_addr(rt2x00dev,
9911                                                    EEPROM_MAC_ADDR_0));
9912
9913         /*
9914          * As rt2800 has a global fallback table we cannot specify
9915          * more then one tx rate per frame but since the hw will
9916          * try several rates (based on the fallback table) we should
9917          * initialize max_report_rates to the maximum number of rates
9918          * we are going to try. Otherwise mac80211 will truncate our
9919          * reported tx rates and the rc algortihm will end up with
9920          * incorrect data.
9921          */
9922         rt2x00dev->hw->max_rates = 1;
9923         rt2x00dev->hw->max_report_rates = 7;
9924         rt2x00dev->hw->max_rate_tries = 1;
9925
9926         /*
9927          * Initialize hw_mode information.
9928          */
9929         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
9930
9931         switch (rt2x00dev->chip.rf) {
9932         case RF2720:
9933         case RF2820:
9934                 spec->num_channels = 14;
9935                 spec->channels = rf_vals;
9936                 break;
9937
9938         case RF2750:
9939         case RF2850:
9940                 spec->num_channels = ARRAY_SIZE(rf_vals);
9941                 spec->channels = rf_vals;
9942                 break;
9943
9944         case RF2020:
9945         case RF3020:
9946         case RF3021:
9947         case RF3022:
9948         case RF3070:
9949         case RF3290:
9950         case RF3320:
9951         case RF3322:
9952         case RF5350:
9953         case RF5360:
9954         case RF5362:
9955         case RF5370:
9956         case RF5372:
9957         case RF5390:
9958         case RF5392:
9959                 spec->num_channels = 14;
9960                 if (rt2800_clk_is_20mhz(rt2x00dev))
9961                         spec->channels = rf_vals_3x_xtal20;
9962                 else
9963                         spec->channels = rf_vals_3x;
9964                 break;
9965
9966         case RF7620:
9967                 spec->num_channels = ARRAY_SIZE(rf_vals_7620);
9968                 spec->channels = rf_vals_7620;
9969                 break;
9970
9971         case RF3052:
9972         case RF3053:
9973                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
9974                 spec->channels = rf_vals_3x;
9975                 break;
9976
9977         case RF3853:
9978                 spec->num_channels = ARRAY_SIZE(rf_vals_3853);
9979                 spec->channels = rf_vals_3853;
9980                 break;
9981
9982         case RF5592:
9983                 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
9984                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
9985                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
9986                         spec->channels = rf_vals_5592_xtal40;
9987                 } else {
9988                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
9989                         spec->channels = rf_vals_5592_xtal20;
9990                 }
9991                 break;
9992         }
9993
9994         if (WARN_ON_ONCE(!spec->channels))
9995                 return -ENODEV;
9996
9997         spec->supported_bands = SUPPORT_BAND_2GHZ;
9998         if (spec->num_channels > 14)
9999                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
10000
10001         /*
10002          * Initialize HT information.
10003          */
10004         if (!rt2x00_rf(rt2x00dev, RF2020))
10005                 spec->ht.ht_supported = true;
10006         else
10007                 spec->ht.ht_supported = false;
10008
10009         spec->ht.cap =
10010             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
10011             IEEE80211_HT_CAP_GRN_FLD |
10012             IEEE80211_HT_CAP_SGI_20 |
10013             IEEE80211_HT_CAP_SGI_40;
10014
10015         tx_chains = rt2x00dev->default_ant.tx_chain_num;
10016         rx_chains = rt2x00dev->default_ant.rx_chain_num;
10017
10018         if (tx_chains >= 2)
10019                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
10020
10021         spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
10022
10023         spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
10024         spec->ht.ampdu_density = 4;
10025         spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
10026         if (tx_chains != rx_chains) {
10027                 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
10028                 spec->ht.mcs.tx_params |=
10029                     (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
10030         }
10031
10032         switch (rx_chains) {
10033         case 3:
10034                 spec->ht.mcs.rx_mask[2] = 0xff;
10035                 /* fall through */
10036         case 2:
10037                 spec->ht.mcs.rx_mask[1] = 0xff;
10038                 /* fall through */
10039         case 1:
10040                 spec->ht.mcs.rx_mask[0] = 0xff;
10041                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
10042                 break;
10043         }
10044
10045         /*
10046          * Create channel information array
10047          */
10048         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
10049         if (!info)
10050                 return -ENOMEM;
10051
10052         spec->channels_info = info;
10053
10054         default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
10055         default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
10056
10057         if (rt2x00dev->default_ant.tx_chain_num > 2)
10058                 default_power3 = rt2800_eeprom_addr(rt2x00dev,
10059                                                     EEPROM_EXT_TXPOWER_BG3);
10060         else
10061                 default_power3 = NULL;
10062
10063         for (i = 0; i < 14; i++) {
10064                 info[i].default_power1 = default_power1[i];
10065                 info[i].default_power2 = default_power2[i];
10066                 if (default_power3)
10067                         info[i].default_power3 = default_power3[i];
10068         }
10069
10070         if (spec->num_channels > 14) {
10071                 default_power1 = rt2800_eeprom_addr(rt2x00dev,
10072                                                     EEPROM_TXPOWER_A1);
10073                 default_power2 = rt2800_eeprom_addr(rt2x00dev,
10074                                                     EEPROM_TXPOWER_A2);
10075
10076                 if (rt2x00dev->default_ant.tx_chain_num > 2)
10077                         default_power3 =
10078                                 rt2800_eeprom_addr(rt2x00dev,
10079                                                    EEPROM_EXT_TXPOWER_A3);
10080                 else
10081                         default_power3 = NULL;
10082
10083                 for (i = 14; i < spec->num_channels; i++) {
10084                         info[i].default_power1 = default_power1[i - 14];
10085                         info[i].default_power2 = default_power2[i - 14];
10086                         if (default_power3)
10087                                 info[i].default_power3 = default_power3[i - 14];
10088                 }
10089         }
10090
10091         switch (rt2x00dev->chip.rf) {
10092         case RF2020:
10093         case RF3020:
10094         case RF3021:
10095         case RF3022:
10096         case RF3320:
10097         case RF3052:
10098         case RF3053:
10099         case RF3070:
10100         case RF3290:
10101         case RF3853:
10102         case RF5350:
10103         case RF5360:
10104         case RF5362:
10105         case RF5370:
10106         case RF5372:
10107         case RF5390:
10108         case RF5392:
10109         case RF5592:
10110         case RF7620:
10111                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
10112                 break;
10113         }
10114
10115         return 0;
10116 }
10117
10118 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
10119 {
10120         u32 reg;
10121         u32 rt;
10122         u32 rev;
10123
10124         if (rt2x00_rt(rt2x00dev, RT3290))
10125                 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290);
10126         else
10127                 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
10128
10129         rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
10130         rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
10131
10132         switch (rt) {
10133         case RT2860:
10134         case RT2872:
10135         case RT2883:
10136         case RT3070:
10137         case RT3071:
10138         case RT3090:
10139         case RT3290:
10140         case RT3352:
10141         case RT3390:
10142         case RT3572:
10143         case RT3593:
10144         case RT3883:
10145         case RT5350:
10146         case RT5390:
10147         case RT5392:
10148         case RT5592:
10149                 break;
10150         default:
10151                 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
10152                            rt, rev);
10153                 return -ENODEV;
10154         }
10155
10156         if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
10157                 rt = RT6352;
10158
10159         rt2x00_set_rt(rt2x00dev, rt, rev);
10160
10161         return 0;
10162 }
10163
10164 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
10165 {
10166         int retval;
10167         u32 reg;
10168
10169         retval = rt2800_probe_rt(rt2x00dev);
10170         if (retval)
10171                 return retval;
10172
10173         /*
10174          * Allocate eeprom data.
10175          */
10176         retval = rt2800_validate_eeprom(rt2x00dev);
10177         if (retval)
10178                 return retval;
10179
10180         retval = rt2800_init_eeprom(rt2x00dev);
10181         if (retval)
10182                 return retval;
10183
10184         /*
10185          * Enable rfkill polling by setting GPIO direction of the
10186          * rfkill switch GPIO pin correctly.
10187          */
10188         reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
10189         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
10190         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
10191
10192         /*
10193          * Initialize hw specifications.
10194          */
10195         retval = rt2800_probe_hw_mode(rt2x00dev);
10196         if (retval)
10197                 return retval;
10198
10199         /*
10200          * Set device capabilities.
10201          */
10202         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
10203         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
10204         if (!rt2x00_is_usb(rt2x00dev))
10205                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
10206
10207         /*
10208          * Set device requirements.
10209          */
10210         if (!rt2x00_is_soc(rt2x00dev))
10211                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
10212         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
10213         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
10214         if (!rt2800_hwcrypt_disabled(rt2x00dev))
10215                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
10216         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
10217         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
10218         if (rt2x00_is_usb(rt2x00dev))
10219                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
10220         else {
10221                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
10222                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
10223         }
10224
10225         /*
10226          * Set the rssi offset.
10227          */
10228         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
10229
10230         return 0;
10231 }
10232 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
10233
10234 /*
10235  * IEEE80211 stack callback functions.
10236  */
10237 void rt2800_get_key_seq(struct ieee80211_hw *hw,
10238                         struct ieee80211_key_conf *key,
10239                         struct ieee80211_key_seq *seq)
10240 {
10241         struct rt2x00_dev *rt2x00dev = hw->priv;
10242         struct mac_iveiv_entry iveiv_entry;
10243         u32 offset;
10244
10245         if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
10246                 return;
10247
10248         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
10249         rt2800_register_multiread(rt2x00dev, offset,
10250                                       &iveiv_entry, sizeof(iveiv_entry));
10251
10252         memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
10253         memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
10254 }
10255 EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
10256
10257 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
10258 {
10259         struct rt2x00_dev *rt2x00dev = hw->priv;
10260         u32 reg;
10261         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
10262
10263         reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
10264         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
10265         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
10266
10267         reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
10268         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
10269         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
10270
10271         reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
10272         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
10273         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
10274
10275         reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
10276         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
10277         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
10278
10279         reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
10280         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
10281         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
10282
10283         reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
10284         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
10285         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
10286
10287         reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
10288         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
10289         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
10290
10291         return 0;
10292 }
10293 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
10294
10295 int rt2800_conf_tx(struct ieee80211_hw *hw,
10296                    struct ieee80211_vif *vif, u16 queue_idx,
10297                    const struct ieee80211_tx_queue_params *params)
10298 {
10299         struct rt2x00_dev *rt2x00dev = hw->priv;
10300         struct data_queue *queue;
10301         struct rt2x00_field32 field;
10302         int retval;
10303         u32 reg;
10304         u32 offset;
10305
10306         /*
10307          * First pass the configuration through rt2x00lib, that will
10308          * update the queue settings and validate the input. After that
10309          * we are free to update the registers based on the value
10310          * in the queue parameter.
10311          */
10312         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
10313         if (retval)
10314                 return retval;
10315
10316         /*
10317          * We only need to perform additional register initialization
10318          * for WMM queues/
10319          */
10320         if (queue_idx >= 4)
10321                 return 0;
10322
10323         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
10324
10325         /* Update WMM TXOP register */
10326         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
10327         field.bit_offset = (queue_idx & 1) * 16;
10328         field.bit_mask = 0xffff << field.bit_offset;
10329
10330         reg = rt2800_register_read(rt2x00dev, offset);
10331         rt2x00_set_field32(&reg, field, queue->txop);
10332         rt2800_register_write(rt2x00dev, offset, reg);
10333
10334         /* Update WMM registers */
10335         field.bit_offset = queue_idx * 4;
10336         field.bit_mask = 0xf << field.bit_offset;
10337
10338         reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG);
10339         rt2x00_set_field32(&reg, field, queue->aifs);
10340         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
10341
10342         reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG);
10343         rt2x00_set_field32(&reg, field, queue->cw_min);
10344         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
10345
10346         reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG);
10347         rt2x00_set_field32(&reg, field, queue->cw_max);
10348         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
10349
10350         /* Update EDCA registers */
10351         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
10352
10353         reg = rt2800_register_read(rt2x00dev, offset);
10354         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
10355         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
10356         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
10357         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
10358         rt2800_register_write(rt2x00dev, offset, reg);
10359
10360         return 0;
10361 }
10362 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
10363
10364 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
10365 {
10366         struct rt2x00_dev *rt2x00dev = hw->priv;
10367         u64 tsf;
10368         u32 reg;
10369
10370         reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1);
10371         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
10372         reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0);
10373         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
10374
10375         return tsf;
10376 }
10377 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
10378
10379 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
10380                         struct ieee80211_ampdu_params *params)
10381 {
10382         struct ieee80211_sta *sta = params->sta;
10383         enum ieee80211_ampdu_mlme_action action = params->action;
10384         u16 tid = params->tid;
10385         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
10386         int ret = 0;
10387
10388         /*
10389          * Don't allow aggregation for stations the hardware isn't aware
10390          * of because tx status reports for frames to an unknown station
10391          * always contain wcid=WCID_END+1 and thus we can't distinguish
10392          * between multiple stations which leads to unwanted situations
10393          * when the hw reorders frames due to aggregation.
10394          */
10395         if (sta_priv->wcid > WCID_END)
10396                 return 1;
10397
10398         switch (action) {
10399         case IEEE80211_AMPDU_RX_START:
10400         case IEEE80211_AMPDU_RX_STOP:
10401                 /*
10402                  * The hw itself takes care of setting up BlockAck mechanisms.
10403                  * So, we only have to allow mac80211 to nagotiate a BlockAck
10404                  * agreement. Once that is done, the hw will BlockAck incoming
10405                  * AMPDUs without further setup.
10406                  */
10407                 break;
10408         case IEEE80211_AMPDU_TX_START:
10409                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
10410                 break;
10411         case IEEE80211_AMPDU_TX_STOP_CONT:
10412         case IEEE80211_AMPDU_TX_STOP_FLUSH:
10413         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
10414                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
10415                 break;
10416         case IEEE80211_AMPDU_TX_OPERATIONAL:
10417                 break;
10418         default:
10419                 rt2x00_warn((struct rt2x00_dev *)hw->priv,
10420                             "Unknown AMPDU action\n");
10421         }
10422
10423         return ret;
10424 }
10425 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
10426
10427 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
10428                       struct survey_info *survey)
10429 {
10430         struct rt2x00_dev *rt2x00dev = hw->priv;
10431         struct ieee80211_conf *conf = &hw->conf;
10432         u32 idle, busy, busy_ext;
10433
10434         if (idx != 0)
10435                 return -ENOENT;
10436
10437         survey->channel = conf->chandef.chan;
10438
10439         idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
10440         busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
10441         busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
10442
10443         if (idle || busy) {
10444                 survey->filled = SURVEY_INFO_TIME |
10445                                  SURVEY_INFO_TIME_BUSY |
10446                                  SURVEY_INFO_TIME_EXT_BUSY;
10447
10448                 survey->time = (idle + busy) / 1000;
10449                 survey->time_busy = busy / 1000;
10450                 survey->time_ext_busy = busy_ext / 1000;
10451         }
10452
10453         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
10454                 survey->filled |= SURVEY_INFO_IN_USE;
10455
10456         return 0;
10457
10458 }
10459 EXPORT_SYMBOL_GPL(rt2800_get_survey);
10460
10461 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
10462 MODULE_VERSION(DRV_VERSION);
10463 MODULE_DESCRIPTION("Ralink RT2800 library");
10464 MODULE_LICENSE("GPL");