1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2019 Intel Corporation
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 * The full GNU General Public License is included in this distribution in the
23 * file called COPYING.
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 - 2019 Intel Corporation
35 * All rights reserved.
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
41 * * Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in
45 * the documentation and/or other materials provided with the
47 * * Neither the name Intel Corporation nor the names of its
48 * contributors may be used to endorse or promote products derived
49 * from this software without specific prior written permission.
51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *****************************************************************************/
64 #include <linux/etherdevice.h>
65 #include <linux/ieee80211.h>
66 #include <linux/slab.h>
67 #include <linux/sched.h>
68 #include <net/ip6_checksum.h>
71 #include "iwl-debug.h"
76 #include "iwl-op-mode.h"
78 #include "fw/api/tx.h"
80 #define IWL_TX_CRC_SIZE 4
81 #define IWL_TX_DELIMITER_SIZE 4
83 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
88 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
89 * of buffer descriptors, each of which points to one or more data buffers for
90 * the device to read from or fill. Driver and device exchange status of each
91 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
92 * entries in each circular buffer, to protect against confusing empty and full
95 * The device reads or writes the data in the queues via the device's several
96 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
98 * For Tx queue, there are low mark and high mark limits. If, after queuing
99 * the packet for Tx, free space become < low mark, Tx queue stopped. When
100 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
103 ***************************************************/
105 int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q)
111 * To avoid ambiguity between empty and completely full queues, there
112 * should always be less than max_tfd_queue_size elements in the queue.
113 * If q->n_window is smaller than max_tfd_queue_size, there is no need
114 * to reserve any queue entries for this purpose.
116 if (q->n_window < trans->trans_cfg->base_params->max_tfd_queue_size)
119 max = trans->trans_cfg->base_params->max_tfd_queue_size - 1;
122 * max_tfd_queue_size is a power of 2, so the following is equivalent to
123 * modulo by max_tfd_queue_size and is well defined.
125 used = (q->write_ptr - q->read_ptr) &
126 (trans->trans_cfg->base_params->max_tfd_queue_size - 1);
128 if (WARN_ON(used > max))
135 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
137 static int iwl_queue_init(struct iwl_txq *q, int slots_num)
139 q->n_window = slots_num;
141 /* slots_num must be power-of-two size, otherwise
142 * iwl_pcie_get_cmd_index is broken. */
143 if (WARN_ON(!is_power_of_2(slots_num)))
146 q->low_mark = q->n_window / 4;
150 q->high_mark = q->n_window / 8;
151 if (q->high_mark < 2)
160 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
161 struct iwl_dma_ptr *ptr, size_t size)
163 if (WARN_ON(ptr->addr))
166 ptr->addr = dma_alloc_coherent(trans->dev, size,
167 &ptr->dma, GFP_KERNEL);
174 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr)
176 if (unlikely(!ptr->addr))
179 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
180 memset(ptr, 0, sizeof(*ptr));
183 static void iwl_pcie_txq_stuck_timer(struct timer_list *t)
185 struct iwl_txq *txq = from_timer(txq, t, stuck_timer);
186 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
187 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
189 spin_lock(&txq->lock);
190 /* check if triggered erroneously */
191 if (txq->read_ptr == txq->write_ptr) {
192 spin_unlock(&txq->lock);
195 spin_unlock(&txq->lock);
197 iwl_trans_pcie_log_scd_error(trans, txq);
199 iwl_force_nmi(trans);
203 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
205 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
206 struct iwl_txq *txq, u16 byte_cnt,
209 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
210 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
211 int write_ptr = txq->write_ptr;
212 int txq_id = txq->id;
214 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
216 struct iwl_tx_cmd *tx_cmd =
217 (void *)txq->entries[txq->write_ptr].cmd->payload;
218 u8 sta_id = tx_cmd->sta_id;
220 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
222 sec_ctl = tx_cmd->sec_ctl;
224 switch (sec_ctl & TX_CMD_SEC_MSK) {
226 len += IEEE80211_CCMP_MIC_LEN;
228 case TX_CMD_SEC_TKIP:
229 len += IEEE80211_TKIP_ICV_LEN;
232 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
235 if (trans_pcie->bc_table_dword)
236 len = DIV_ROUND_UP(len, 4);
238 if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
241 bc_ent = cpu_to_le16(len | (sta_id << 12));
243 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
245 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
247 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
250 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
253 struct iwl_trans_pcie *trans_pcie =
254 IWL_TRANS_GET_PCIE_TRANS(trans);
255 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
256 int txq_id = txq->id;
257 int read_ptr = txq->read_ptr;
260 struct iwl_tx_cmd *tx_cmd =
261 (void *)txq->entries[read_ptr].cmd->payload;
263 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
265 if (txq_id != trans_pcie->cmd_queue)
266 sta_id = tx_cmd->sta_id;
268 bc_ent = cpu_to_le16(1 | (sta_id << 12));
270 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
272 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
274 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
278 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
280 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
283 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
285 int txq_id = txq->id;
287 lockdep_assert_held(&txq->lock);
290 * explicitly wake up the NIC if:
291 * 1. shadow registers aren't enabled
292 * 2. NIC is woken up for CMD regardless of shadow outside this function
293 * 3. there is a chance that the NIC is asleep
295 if (!trans->trans_cfg->base_params->shadow_reg_enable &&
296 txq_id != trans_pcie->cmd_queue &&
297 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
299 * wake up nic if it's powered down ...
300 * uCode will wake up, and interrupt us again, so next
301 * time we'll skip this part.
303 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
305 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
306 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
308 iwl_set_bit(trans, CSR_GP_CNTRL,
309 BIT(trans->trans_cfg->csr->flag_mac_access_req));
310 txq->need_update = true;
316 * if not in power-save mode, uCode will never sleep when we're
317 * trying to tx (during RFKILL, we're not trying to tx).
319 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
321 iwl_write32(trans, HBUS_TARG_WRPTR,
322 txq->write_ptr | (txq_id << 8));
325 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
327 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
330 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
331 struct iwl_txq *txq = trans_pcie->txq[i];
333 if (!test_bit(i, trans_pcie->queue_used))
336 spin_lock_bh(&txq->lock);
337 if (txq->need_update) {
338 iwl_pcie_txq_inc_wr_ptr(trans, txq);
339 txq->need_update = false;
341 spin_unlock_bh(&txq->lock);
345 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans,
349 if (trans->trans_cfg->use_tfh) {
350 struct iwl_tfh_tfd *tfd = _tfd;
351 struct iwl_tfh_tb *tb = &tfd->tbs[idx];
353 return (dma_addr_t)(le64_to_cpu(tb->addr));
355 struct iwl_tfd *tfd = _tfd;
356 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
357 dma_addr_t addr = get_unaligned_le32(&tb->lo);
360 if (sizeof(dma_addr_t) <= sizeof(u32))
363 hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
366 * shift by 16 twice to avoid warnings on 32-bit
367 * (where this code never runs anyway due to the
368 * if statement above)
370 return addr | ((hi_len << 16) << 16);
374 static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd,
375 u8 idx, dma_addr_t addr, u16 len)
377 struct iwl_tfd *tfd_fh = (void *)tfd;
378 struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx];
380 u16 hi_n_len = len << 4;
382 put_unaligned_le32(addr, &tb->lo);
383 hi_n_len |= iwl_get_dma_hi_addr(addr);
385 tb->hi_n_len = cpu_to_le16(hi_n_len);
387 tfd_fh->num_tbs = idx + 1;
390 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd)
392 if (trans->trans_cfg->use_tfh) {
393 struct iwl_tfh_tfd *tfd = _tfd;
395 return le16_to_cpu(tfd->num_tbs) & 0x1f;
397 struct iwl_tfd *tfd = _tfd;
399 return tfd->num_tbs & 0x1f;
403 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
404 struct iwl_cmd_meta *meta,
405 struct iwl_txq *txq, int index)
407 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
409 void *tfd = iwl_pcie_get_tfd(trans, txq, index);
411 /* Sanity check on number of chunks */
412 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
414 if (num_tbs > trans_pcie->max_tbs) {
415 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
416 /* @todo issue fatal error, it is quite serious situation */
420 /* first TB is never freed - it's the bidirectional DMA data */
422 for (i = 1; i < num_tbs; i++) {
423 if (meta->tbs & BIT(i))
424 dma_unmap_page(trans->dev,
425 iwl_pcie_tfd_tb_get_addr(trans, tfd, i),
426 iwl_pcie_tfd_tb_get_len(trans, tfd, i),
429 dma_unmap_single(trans->dev,
430 iwl_pcie_tfd_tb_get_addr(trans, tfd,
432 iwl_pcie_tfd_tb_get_len(trans, tfd,
439 if (trans->trans_cfg->use_tfh) {
440 struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
444 struct iwl_tfd *tfd_fh = (void *)tfd;
452 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
453 * @trans - transport private data
455 * @dma_dir - the direction of the DMA mapping
457 * Does NOT advance any TFD circular buffer read/write indexes
458 * Does NOT free the TFD itself (which is within circular buffer)
460 void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
462 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
463 * idx is bounded by n_window
465 int rd_ptr = txq->read_ptr;
466 int idx = iwl_pcie_get_cmd_index(txq, rd_ptr);
468 lockdep_assert_held(&txq->lock);
470 /* We have only q->n_window txq->entries, but we use
471 * TFD_QUEUE_SIZE_MAX tfds
473 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr);
479 skb = txq->entries[idx].skb;
481 /* Can be called from irqs-disabled context
482 * If skb is not NULL, it means that the whole queue is being
483 * freed and that the queue is not empty - free the skb
486 iwl_op_mode_free_skb(trans->op_mode, skb);
487 txq->entries[idx].skb = NULL;
492 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
493 dma_addr_t addr, u16 len, bool reset)
495 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
499 tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr;
502 memset(tfd, 0, trans_pcie->tfd_size);
504 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
506 /* Each TFD can point to a maximum max_tbs Tx buffers */
507 if (num_tbs >= trans_pcie->max_tbs) {
508 IWL_ERR(trans, "Error can not send more than %d chunks\n",
509 trans_pcie->max_tbs);
513 if (WARN(addr & ~IWL_TX_DMA_MASK,
514 "Unaligned address = %llx\n", (unsigned long long)addr))
517 iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len);
522 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq,
523 int slots_num, bool cmd_queue)
525 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
526 size_t tfd_sz = trans_pcie->tfd_size *
527 trans->trans_cfg->base_params->max_tfd_queue_size;
531 if (WARN_ON(txq->entries || txq->tfds))
534 if (trans->trans_cfg->use_tfh)
535 tfd_sz = trans_pcie->tfd_size * slots_num;
537 timer_setup(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 0);
538 txq->trans_pcie = trans_pcie;
540 txq->n_window = slots_num;
542 txq->entries = kcalloc(slots_num,
543 sizeof(struct iwl_pcie_txq_entry),
550 for (i = 0; i < slots_num; i++) {
551 txq->entries[i].cmd =
552 kmalloc(sizeof(struct iwl_device_cmd),
554 if (!txq->entries[i].cmd)
558 /* Circular buffer of transmit frame descriptors (TFDs),
559 * shared with device */
560 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
561 &txq->dma_addr, GFP_KERNEL);
565 BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs));
567 tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num;
569 txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz,
572 if (!txq->first_tb_bufs)
577 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr);
579 if (txq->entries && cmd_queue)
580 for (i = 0; i < slots_num; i++)
581 kfree(txq->entries[i].cmd);
589 int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
590 int slots_num, bool cmd_queue)
593 u32 tfd_queue_max_size =
594 trans->trans_cfg->base_params->max_tfd_queue_size;
596 txq->need_update = false;
598 /* max_tfd_queue_size must be power-of-two size, otherwise
599 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
600 if (WARN_ONCE(tfd_queue_max_size & (tfd_queue_max_size - 1),
601 "Max tfd queue size must be a power of two, but is %d",
605 /* Initialize queue's high/low-water marks, and head/tail indexes */
606 ret = iwl_queue_init(txq, slots_num);
610 spin_lock_init(&txq->lock);
613 static struct lock_class_key iwl_pcie_cmd_queue_lock_class;
615 lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class);
618 __skb_queue_head_init(&txq->overflow_q);
623 void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie,
626 struct page **page_ptr;
628 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
631 __free_page(*page_ptr);
636 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
638 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
640 lockdep_assert_held(&trans_pcie->reg_lock);
642 if (!trans->trans_cfg->base_params->apmg_wake_up_wa)
644 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
647 trans_pcie->cmd_hold_nic_awake = false;
648 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
649 BIT(trans->trans_cfg->csr->flag_mac_access_req));
653 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
655 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
657 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
658 struct iwl_txq *txq = trans_pcie->txq[txq_id];
660 spin_lock_bh(&txq->lock);
661 while (txq->write_ptr != txq->read_ptr) {
662 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
663 txq_id, txq->read_ptr);
665 if (txq_id != trans_pcie->cmd_queue) {
666 struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
668 if (WARN_ON_ONCE(!skb))
671 iwl_pcie_free_tso_page(trans_pcie, skb);
673 iwl_pcie_txq_free_tfd(trans, txq);
674 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr);
676 if (txq->read_ptr == txq->write_ptr) {
679 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
680 if (txq_id == trans_pcie->cmd_queue)
681 iwl_pcie_clear_cmd_in_flight(trans);
682 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
686 while (!skb_queue_empty(&txq->overflow_q)) {
687 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
689 iwl_op_mode_free_skb(trans->op_mode, skb);
692 spin_unlock_bh(&txq->lock);
694 /* just in case - this queue may have been stopped */
695 iwl_wake_queue(trans, txq);
699 * iwl_pcie_txq_free - Deallocate DMA queue.
700 * @txq: Transmit queue to deallocate.
702 * Empty queue by removing and destroying all BD's.
704 * 0-fill, but do not free "txq" descriptor structure.
706 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
708 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
709 struct iwl_txq *txq = trans_pcie->txq[txq_id];
710 struct device *dev = trans->dev;
716 iwl_pcie_txq_unmap(trans, txq_id);
718 /* De-alloc array of command/tx buffers */
719 if (txq_id == trans_pcie->cmd_queue)
720 for (i = 0; i < txq->n_window; i++) {
721 kzfree(txq->entries[i].cmd);
722 kzfree(txq->entries[i].free_buf);
725 /* De-alloc circular buffer of TFDs */
727 dma_free_coherent(dev,
728 trans_pcie->tfd_size *
729 trans->trans_cfg->base_params->max_tfd_queue_size,
730 txq->tfds, txq->dma_addr);
734 dma_free_coherent(dev,
735 sizeof(*txq->first_tb_bufs) * txq->n_window,
736 txq->first_tb_bufs, txq->first_tb_dma);
742 del_timer_sync(&txq->stuck_timer);
744 /* 0-fill queue descriptor structure */
745 memset(txq, 0, sizeof(*txq));
748 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
750 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
751 int nq = trans->trans_cfg->base_params->num_of_queues;
754 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
755 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
757 /* make sure all queue are not stopped/used */
758 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
759 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
761 trans_pcie->scd_base_addr =
762 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
764 WARN_ON(scd_base_addr != 0 &&
765 scd_base_addr != trans_pcie->scd_base_addr);
767 /* reset context data, TX status and translation data */
768 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
769 SCD_CONTEXT_MEM_LOWER_BOUND,
772 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
773 trans_pcie->scd_bc_tbls.dma >> 10);
775 /* The chain extension of the SCD doesn't work well. This feature is
776 * enabled by default by the HW, so we need to disable it manually.
778 if (trans->trans_cfg->base_params->scd_chain_ext_wa)
779 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
781 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
782 trans_pcie->cmd_fifo,
783 trans_pcie->cmd_q_wdg_timeout);
785 /* Activate all Tx DMA/FIFO channels */
786 iwl_scd_activate_fifos(trans);
788 /* Enable DMA channel */
789 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
790 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
791 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
792 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
794 /* Update FH chicken bits */
795 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
796 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
797 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
799 /* Enable L1-Active */
800 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
801 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
802 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
805 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
807 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
811 * we should never get here in gen2 trans mode return early to avoid
812 * having invalid accesses
814 if (WARN_ON_ONCE(trans->trans_cfg->gen2))
817 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
819 struct iwl_txq *txq = trans_pcie->txq[txq_id];
820 if (trans->trans_cfg->use_tfh)
821 iwl_write_direct64(trans,
822 FH_MEM_CBBC_QUEUE(trans, txq_id),
825 iwl_write_direct32(trans,
826 FH_MEM_CBBC_QUEUE(trans, txq_id),
828 iwl_pcie_txq_unmap(trans, txq_id);
833 /* Tell NIC where to find the "keep warm" buffer */
834 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
835 trans_pcie->kw.dma >> 4);
838 * Send 0 as the scd_base_addr since the device may have be reset
839 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
842 iwl_pcie_tx_start(trans, 0);
845 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
847 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
852 spin_lock(&trans_pcie->irq_lock);
854 if (!iwl_trans_grab_nic_access(trans, &flags))
857 /* Stop each Tx DMA channel */
858 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
859 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
860 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
863 /* Wait for DMA channels to be idle */
864 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
867 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
868 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
870 iwl_trans_release_nic_access(trans, &flags);
873 spin_unlock(&trans_pcie->irq_lock);
877 * iwl_pcie_tx_stop - Stop all Tx DMA channels
879 int iwl_pcie_tx_stop(struct iwl_trans *trans)
881 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
884 /* Turn off all Tx DMA fifos */
885 iwl_scd_deactivate_fifos(trans);
887 /* Turn off all Tx DMA channels */
888 iwl_pcie_tx_stop_fh(trans);
891 * This function can be called before the op_mode disabled the
892 * queues. This happens when we have an rfkill interrupt.
893 * Since we stop Tx altogether - mark the queues as stopped.
895 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
896 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
898 /* This can happen: start_hw, stop_device */
899 if (!trans_pcie->txq_memory)
902 /* Unmap DMA from host system and free skb's */
903 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
905 iwl_pcie_txq_unmap(trans, txq_id);
911 * iwl_trans_tx_free - Free TXQ Context
913 * Destroy all TX DMA queues and structures
915 void iwl_pcie_tx_free(struct iwl_trans *trans)
918 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
920 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
923 if (trans_pcie->txq_memory) {
925 txq_id < trans->trans_cfg->base_params->num_of_queues;
927 iwl_pcie_txq_free(trans, txq_id);
928 trans_pcie->txq[txq_id] = NULL;
932 kfree(trans_pcie->txq_memory);
933 trans_pcie->txq_memory = NULL;
935 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
937 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
941 * iwl_pcie_tx_alloc - allocate TX context
942 * Allocate all Tx DMA structures and initialize them
944 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
947 int txq_id, slots_num;
948 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
949 u16 bc_tbls_size = trans->trans_cfg->base_params->num_of_queues;
951 bc_tbls_size *= (trans->trans_cfg->device_family >=
952 IWL_DEVICE_FAMILY_22560) ?
953 sizeof(struct iwl_gen3_bc_tbl) :
954 sizeof(struct iwlagn_scd_bc_tbl);
956 /*It is not allowed to alloc twice, so warn when this happens.
957 * We cannot rely on the previous allocation, so free and fail */
958 if (WARN_ON(trans_pcie->txq_memory)) {
963 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
966 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
970 /* Alloc keep-warm buffer */
971 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
973 IWL_ERR(trans, "Keep Warm allocation failed\n");
977 trans_pcie->txq_memory =
978 kcalloc(trans->trans_cfg->base_params->num_of_queues,
979 sizeof(struct iwl_txq), GFP_KERNEL);
980 if (!trans_pcie->txq_memory) {
981 IWL_ERR(trans, "Not enough memory for txq\n");
986 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
987 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
989 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
992 slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
993 trans->cfg->min_txq_size);
995 slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
996 trans->cfg->min_256_ba_txq_size);
997 trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id];
998 ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id],
999 slots_num, cmd_queue);
1001 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
1004 trans_pcie->txq[txq_id]->id = txq_id;
1010 iwl_pcie_tx_free(trans);
1015 int iwl_pcie_tx_init(struct iwl_trans *trans)
1017 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1019 int txq_id, slots_num;
1022 if (!trans_pcie->txq_memory) {
1023 ret = iwl_pcie_tx_alloc(trans);
1029 spin_lock(&trans_pcie->irq_lock);
1031 /* Turn off all Tx DMA fifos */
1032 iwl_scd_deactivate_fifos(trans);
1034 /* Tell NIC where to find the "keep warm" buffer */
1035 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
1036 trans_pcie->kw.dma >> 4);
1038 spin_unlock(&trans_pcie->irq_lock);
1040 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
1041 for (txq_id = 0; txq_id < trans->trans_cfg->base_params->num_of_queues;
1043 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
1046 slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
1047 trans->cfg->min_txq_size);
1049 slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
1050 trans->cfg->min_256_ba_txq_size);
1051 ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id],
1052 slots_num, cmd_queue);
1054 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
1059 * Tell nic where to find circular buffer of TFDs for a
1060 * given Tx queue, and enable the DMA channel used for that
1062 * Circular buffer (TFD queue in DRAM) physical base address
1064 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
1065 trans_pcie->txq[txq_id]->dma_addr >> 8);
1068 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
1069 if (trans->trans_cfg->base_params->num_of_queues > 20)
1070 iwl_set_bits_prph(trans, SCD_GP_CTRL,
1071 SCD_GP_CTRL_ENABLE_31_QUEUES);
1075 /*Upon error, free only if we allocated something */
1077 iwl_pcie_tx_free(trans);
1081 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
1083 lockdep_assert_held(&txq->lock);
1085 if (!txq->wd_timeout)
1089 * station is asleep and we send data - that must
1090 * be uAPSD or PS-Poll. Don't rearm the timer.
1096 * if empty delete timer, otherwise move timer forward
1097 * since we're making progress on this queue
1099 if (txq->read_ptr == txq->write_ptr)
1100 del_timer(&txq->stuck_timer);
1102 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1105 /* Frees buffers until index _not_ inclusive */
1106 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1107 struct sk_buff_head *skbs)
1109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1110 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1111 int tfd_num = iwl_pcie_get_cmd_index(txq, ssn);
1112 int read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1115 /* This function is not meant to release cmd queue*/
1116 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
1119 spin_lock_bh(&txq->lock);
1121 if (!test_bit(txq_id, trans_pcie->queue_used)) {
1122 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
1127 if (read_ptr == tfd_num)
1130 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1131 txq_id, txq->read_ptr, tfd_num, ssn);
1133 /*Since we free until index _not_ inclusive, the one before index is
1134 * the last we will free. This one must be used */
1135 last_to_free = iwl_queue_dec_wrap(trans, tfd_num);
1137 if (!iwl_queue_used(txq, last_to_free)) {
1139 "%s: Read index for txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
1140 __func__, txq_id, last_to_free,
1141 trans->trans_cfg->base_params->max_tfd_queue_size,
1142 txq->write_ptr, txq->read_ptr);
1146 if (WARN_ON(!skb_queue_empty(skbs)))
1150 read_ptr != tfd_num;
1151 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr),
1152 read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr)) {
1153 struct sk_buff *skb = txq->entries[read_ptr].skb;
1155 if (WARN_ON_ONCE(!skb))
1158 iwl_pcie_free_tso_page(trans_pcie, skb);
1160 __skb_queue_tail(skbs, skb);
1162 txq->entries[read_ptr].skb = NULL;
1164 if (!trans->trans_cfg->use_tfh)
1165 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1167 iwl_pcie_txq_free_tfd(trans, txq);
1170 iwl_pcie_txq_progress(txq);
1172 if (iwl_queue_space(trans, txq) > txq->low_mark &&
1173 test_bit(txq_id, trans_pcie->queue_stopped)) {
1174 struct sk_buff_head overflow_skbs;
1176 __skb_queue_head_init(&overflow_skbs);
1177 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs);
1180 * We are going to transmit from the overflow queue.
1181 * Remember this state so that wait_for_txq_empty will know we
1182 * are adding more packets to the TFD queue. It cannot rely on
1183 * the state of &txq->overflow_q, as we just emptied it, but
1184 * haven't TXed the content yet.
1186 txq->overflow_tx = true;
1189 * This is tricky: we are in reclaim path which is non
1190 * re-entrant, so noone will try to take the access the
1191 * txq data from that path. We stopped tx, so we can't
1192 * have tx as well. Bottom line, we can unlock and re-lock
1195 spin_unlock_bh(&txq->lock);
1197 while (!skb_queue_empty(&overflow_skbs)) {
1198 struct sk_buff *skb = __skb_dequeue(&overflow_skbs);
1199 struct iwl_device_cmd *dev_cmd_ptr;
1201 dev_cmd_ptr = *(void **)((u8 *)skb->cb +
1202 trans_pcie->dev_cmd_offs);
1205 * Note that we can very well be overflowing again.
1206 * In that case, iwl_queue_space will be small again
1207 * and we won't wake mac80211's queue.
1209 iwl_trans_tx(trans, skb, dev_cmd_ptr, txq_id);
1212 if (iwl_queue_space(trans, txq) > txq->low_mark)
1213 iwl_wake_queue(trans, txq);
1215 spin_lock_bh(&txq->lock);
1216 txq->overflow_tx = false;
1220 spin_unlock_bh(&txq->lock);
1223 /* Set wr_ptr of specific device and txq */
1224 void iwl_trans_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr)
1226 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1227 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1229 spin_lock_bh(&txq->lock);
1231 txq->write_ptr = ptr;
1232 txq->read_ptr = txq->write_ptr;
1234 spin_unlock_bh(&txq->lock);
1237 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1238 const struct iwl_host_cmd *cmd)
1240 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1243 lockdep_assert_held(&trans_pcie->reg_lock);
1245 /* Make sure the NIC is still alive in the bus */
1246 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
1250 * wake up the NIC to make sure that the firmware will see the host
1251 * command - we will let the NIC sleep once all the host commands
1252 * returned. This needs to be done only on NICs that have
1253 * apmg_wake_up_wa set.
1255 if (trans->trans_cfg->base_params->apmg_wake_up_wa &&
1256 !trans_pcie->cmd_hold_nic_awake) {
1257 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1258 BIT(trans->trans_cfg->csr->flag_mac_access_req));
1260 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1261 BIT(trans->trans_cfg->csr->flag_val_mac_access_en),
1262 (BIT(trans->trans_cfg->csr->flag_mac_clock_ready) |
1263 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1266 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1267 BIT(trans->trans_cfg->csr->flag_mac_access_req));
1268 IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1271 trans_pcie->cmd_hold_nic_awake = true;
1278 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1280 * When FW advances 'R' index, all entries between old and new 'R' index
1281 * need to be reclaimed. As result, some free space forms. If there is
1282 * enough free space (> low mark), wake the stack that feeds us.
1284 void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1286 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1287 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1288 unsigned long flags;
1292 lockdep_assert_held(&txq->lock);
1294 idx = iwl_pcie_get_cmd_index(txq, idx);
1295 r = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1297 if (idx >= trans->trans_cfg->base_params->max_tfd_queue_size ||
1298 (!iwl_queue_used(txq, idx))) {
1299 WARN_ONCE(test_bit(txq_id, trans_pcie->queue_used),
1300 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1301 __func__, txq_id, idx,
1302 trans->trans_cfg->base_params->max_tfd_queue_size,
1303 txq->write_ptr, txq->read_ptr);
1307 for (idx = iwl_queue_inc_wrap(trans, idx); r != idx;
1308 r = iwl_queue_inc_wrap(trans, r)) {
1309 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr);
1312 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1313 idx, txq->write_ptr, r);
1314 iwl_force_nmi(trans);
1318 if (txq->read_ptr == txq->write_ptr) {
1319 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1320 iwl_pcie_clear_cmd_in_flight(trans);
1321 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1324 iwl_pcie_txq_progress(txq);
1327 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1330 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1335 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1337 tbl_dw_addr = trans_pcie->scd_base_addr +
1338 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1340 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1343 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1345 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1347 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1352 /* Receiver address (actually, Rx station's index into station table),
1353 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1354 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1356 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1357 const struct iwl_trans_txq_scd_cfg *cfg,
1358 unsigned int wdg_timeout)
1360 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1361 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1363 bool scd_bug = false;
1365 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1366 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1368 txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1373 /* Disable the scheduler prior configuring the cmd queue */
1374 if (txq_id == trans_pcie->cmd_queue &&
1375 trans_pcie->scd_set_active)
1376 iwl_scd_enable_set_active(trans, 0);
1378 /* Stop this Tx queue before configuring it */
1379 iwl_scd_txq_set_inactive(trans, txq_id);
1381 /* Set this queue as a chain-building queue unless it is CMD */
1382 if (txq_id != trans_pcie->cmd_queue)
1383 iwl_scd_txq_set_chain(trans, txq_id);
1385 if (cfg->aggregate) {
1386 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1388 /* Map receiver-address / traffic-ID to this queue */
1389 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1391 /* enable aggregations for the queue */
1392 iwl_scd_txq_enable_agg(trans, txq_id);
1396 * disable aggregations for the queue, this will also
1397 * make the ra_tid mapping configuration irrelevant
1398 * since it is now a non-AGG queue.
1400 iwl_scd_txq_disable_agg(trans, txq_id);
1402 ssn = txq->read_ptr;
1406 * If we need to move the SCD write pointer by steps of
1407 * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let
1408 * the op_mode know by returning true later.
1409 * Do this only in case cfg is NULL since this trick can
1410 * be done only if we have DQA enabled which is true for mvm
1411 * only. And mvm never sets a cfg pointer.
1412 * This is really ugly, but this is the easiest way out for
1413 * this sad hardware issue.
1414 * This bug has been fixed on devices 9000 and up.
1416 scd_bug = !trans->trans_cfg->mq_rx_supported &&
1417 !((ssn - txq->write_ptr) & 0x3f) &&
1418 (ssn != txq->write_ptr);
1423 /* Place first TFD at index corresponding to start sequence number.
1424 * Assumes that ssn_idx is valid (!= 0xFFF) */
1425 txq->read_ptr = (ssn & 0xff);
1426 txq->write_ptr = (ssn & 0xff);
1427 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1428 (ssn & 0xff) | (txq_id << 8));
1431 u8 frame_limit = cfg->frame_limit;
1433 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1435 /* Set up Tx window size and frame limit for this queue */
1436 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1437 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1438 iwl_trans_write_mem32(trans,
1439 trans_pcie->scd_base_addr +
1440 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1441 SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) |
1442 SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit));
1444 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1445 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1446 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1447 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1448 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1449 SCD_QUEUE_STTS_REG_MSK);
1451 /* enable the scheduler for this queue (only) */
1452 if (txq_id == trans_pcie->cmd_queue &&
1453 trans_pcie->scd_set_active)
1454 iwl_scd_enable_set_active(trans, BIT(txq_id));
1456 IWL_DEBUG_TX_QUEUES(trans,
1457 "Activate queue %d on FIFO %d WrPtr: %d\n",
1458 txq_id, fifo, ssn & 0xff);
1460 IWL_DEBUG_TX_QUEUES(trans,
1461 "Activate queue %d WrPtr: %d\n",
1462 txq_id, ssn & 0xff);
1468 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
1471 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1472 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1474 txq->ampdu = !shared_mode;
1477 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1480 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1481 u32 stts_addr = trans_pcie->scd_base_addr +
1482 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1483 static const u32 zero_val[4] = {};
1485 trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0;
1486 trans_pcie->txq[txq_id]->frozen = false;
1489 * Upon HW Rfkill - we stop the device, and then stop the queues
1490 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1491 * allow the op_mode to call txq_disable after it already called
1494 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1495 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1496 "queue %d not used", txq_id);
1500 if (configure_scd) {
1501 iwl_scd_txq_set_inactive(trans, txq_id);
1503 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1504 ARRAY_SIZE(zero_val));
1507 iwl_pcie_txq_unmap(trans, txq_id);
1508 trans_pcie->txq[txq_id]->ampdu = false;
1510 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1513 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1516 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1517 * @priv: device private data point
1518 * @cmd: a pointer to the ucode command structure
1520 * The function returns < 0 values to indicate the operation
1521 * failed. On success, it returns the index (>= 0) of command in the
1524 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1525 struct iwl_host_cmd *cmd)
1527 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1528 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1529 struct iwl_device_cmd *out_cmd;
1530 struct iwl_cmd_meta *out_meta;
1531 unsigned long flags;
1532 void *dup_buf = NULL;
1533 dma_addr_t phys_addr;
1535 u16 copy_size, cmd_size, tb0_size;
1536 bool had_nocopy = false;
1537 u8 group_id = iwl_cmd_groupid(cmd->id);
1540 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1541 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1543 if (WARN(!trans->wide_cmd_header &&
1544 group_id > IWL_ALWAYS_LONG_GROUP,
1545 "unsupported wide command %#x\n", cmd->id))
1548 if (group_id != 0) {
1549 copy_size = sizeof(struct iwl_cmd_header_wide);
1550 cmd_size = sizeof(struct iwl_cmd_header_wide);
1552 copy_size = sizeof(struct iwl_cmd_header);
1553 cmd_size = sizeof(struct iwl_cmd_header);
1556 /* need one for the header if the first is NOCOPY */
1557 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1559 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1560 cmddata[i] = cmd->data[i];
1561 cmdlen[i] = cmd->len[i];
1566 /* need at least IWL_FIRST_TB_SIZE copied */
1567 if (copy_size < IWL_FIRST_TB_SIZE) {
1568 int copy = IWL_FIRST_TB_SIZE - copy_size;
1570 if (copy > cmdlen[i])
1577 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1579 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1583 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1585 * This is also a chunk that isn't copied
1586 * to the static buffer so set had_nocopy.
1590 /* only allowed once */
1591 if (WARN_ON(dup_buf)) {
1596 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1601 /* NOCOPY must not be followed by normal! */
1602 if (WARN_ON(had_nocopy)) {
1606 copy_size += cmdlen[i];
1608 cmd_size += cmd->len[i];
1612 * If any of the command structures end up being larger than
1613 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1614 * allocated into separate TFDs, then we will need to
1615 * increase the size of the buffers.
1617 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1618 "Command %s (%#x) is too large (%d bytes)\n",
1619 iwl_get_cmd_string(trans, cmd->id),
1620 cmd->id, copy_size)) {
1625 spin_lock_bh(&txq->lock);
1627 if (iwl_queue_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1628 spin_unlock_bh(&txq->lock);
1630 IWL_ERR(trans, "No space in command queue\n");
1631 iwl_op_mode_cmd_queue_full(trans->op_mode);
1636 idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
1637 out_cmd = txq->entries[idx].cmd;
1638 out_meta = &txq->entries[idx].meta;
1640 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1641 if (cmd->flags & CMD_WANT_SKB)
1642 out_meta->source = cmd;
1644 /* set up the header */
1645 if (group_id != 0) {
1646 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1647 out_cmd->hdr_wide.group_id = group_id;
1648 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1649 out_cmd->hdr_wide.length =
1650 cpu_to_le16(cmd_size -
1651 sizeof(struct iwl_cmd_header_wide));
1652 out_cmd->hdr_wide.reserved = 0;
1653 out_cmd->hdr_wide.sequence =
1654 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1655 INDEX_TO_SEQ(txq->write_ptr));
1657 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1658 copy_size = sizeof(struct iwl_cmd_header_wide);
1660 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1661 out_cmd->hdr.sequence =
1662 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1663 INDEX_TO_SEQ(txq->write_ptr));
1664 out_cmd->hdr.group_id = 0;
1666 cmd_pos = sizeof(struct iwl_cmd_header);
1667 copy_size = sizeof(struct iwl_cmd_header);
1670 /* and copy the data that needs to be copied */
1671 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1677 /* copy everything if not nocopy/dup */
1678 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1679 IWL_HCMD_DFL_DUP))) {
1682 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1689 * Otherwise we need at least IWL_FIRST_TB_SIZE copied
1690 * in total (for bi-directional DMA), but copy up to what
1691 * we can fit into the payload for debug dump purposes.
1693 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1695 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1698 /* However, treat copy_size the proper way, we need it below */
1699 if (copy_size < IWL_FIRST_TB_SIZE) {
1700 copy = IWL_FIRST_TB_SIZE - copy_size;
1702 if (copy > cmd->len[i])
1709 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1710 iwl_get_cmd_string(trans, cmd->id),
1711 group_id, out_cmd->hdr.cmd,
1712 le16_to_cpu(out_cmd->hdr.sequence),
1713 cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
1715 /* start the TFD with the minimum copy bytes */
1716 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
1717 memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
1718 iwl_pcie_txq_build_tfd(trans, txq,
1719 iwl_pcie_get_first_tb_dma(txq, idx),
1722 /* map first command fragment, if any remains */
1723 if (copy_size > tb0_size) {
1724 phys_addr = dma_map_single(trans->dev,
1725 ((u8 *)&out_cmd->hdr) + tb0_size,
1726 copy_size - tb0_size,
1728 if (dma_mapping_error(trans->dev, phys_addr)) {
1729 iwl_pcie_tfd_unmap(trans, out_meta, txq,
1735 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1736 copy_size - tb0_size, false);
1739 /* map the remaining (adjusted) nocopy/dup fragments */
1740 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1741 const void *data = cmddata[i];
1745 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1748 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1750 phys_addr = dma_map_single(trans->dev, (void *)data,
1751 cmdlen[i], DMA_TO_DEVICE);
1752 if (dma_mapping_error(trans->dev, phys_addr)) {
1753 iwl_pcie_tfd_unmap(trans, out_meta, txq,
1759 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1762 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
1763 out_meta->flags = cmd->flags;
1764 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1765 kzfree(txq->entries[idx].free_buf);
1766 txq->entries[idx].free_buf = dup_buf;
1768 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1770 /* start timer if queue currently empty */
1771 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
1772 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1774 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1775 ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1778 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1782 /* Increment and update queue's write index */
1783 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
1784 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1786 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1789 spin_unlock_bh(&txq->lock);
1797 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1798 * @rxb: Rx buffer to reclaim
1800 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1801 struct iwl_rx_cmd_buffer *rxb)
1803 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1804 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1807 int txq_id = SEQ_TO_QUEUE(sequence);
1808 int index = SEQ_TO_INDEX(sequence);
1810 struct iwl_device_cmd *cmd;
1811 struct iwl_cmd_meta *meta;
1812 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1813 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1815 /* If a Tx command is being handled and it isn't in the actual
1816 * command queue then there a command routing bug has been introduced
1817 * in the queue management code. */
1818 if (WARN(txq_id != trans_pcie->cmd_queue,
1819 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1820 txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr,
1822 iwl_print_hex_error(trans, pkt, 32);
1826 spin_lock_bh(&txq->lock);
1828 cmd_index = iwl_pcie_get_cmd_index(txq, index);
1829 cmd = txq->entries[cmd_index].cmd;
1830 meta = &txq->entries[cmd_index].meta;
1831 group_id = cmd->hdr.group_id;
1832 cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0);
1834 iwl_pcie_tfd_unmap(trans, meta, txq, index);
1836 /* Input error checking is done when commands are added to queue. */
1837 if (meta->flags & CMD_WANT_SKB) {
1838 struct page *p = rxb_steal_page(rxb);
1840 meta->source->resp_pkt = pkt;
1841 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1842 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1845 if (meta->flags & CMD_WANT_ASYNC_CALLBACK)
1846 iwl_op_mode_async_cb(trans->op_mode, cmd);
1848 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1850 if (!(meta->flags & CMD_ASYNC)) {
1851 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1853 "HCMD_ACTIVE already clear for command %s\n",
1854 iwl_get_cmd_string(trans, cmd_id));
1856 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1857 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1858 iwl_get_cmd_string(trans, cmd_id));
1859 wake_up(&trans_pcie->wait_command_queue);
1864 spin_unlock_bh(&txq->lock);
1867 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1869 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1870 struct iwl_host_cmd *cmd)
1874 /* An asynchronous command can not expect an SKB to be set. */
1875 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1878 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1881 "Error sending %s: enqueue_hcmd failed: %d\n",
1882 iwl_get_cmd_string(trans, cmd->id), ret);
1888 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1889 struct iwl_host_cmd *cmd)
1891 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1892 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1896 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1897 iwl_get_cmd_string(trans, cmd->id));
1899 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1901 "Command %s: a command is already active!\n",
1902 iwl_get_cmd_string(trans, cmd->id)))
1905 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1906 iwl_get_cmd_string(trans, cmd->id));
1908 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1911 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1913 "Error sending %s: enqueue_hcmd failed: %d\n",
1914 iwl_get_cmd_string(trans, cmd->id), ret);
1918 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1919 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1921 HOST_COMPLETE_TIMEOUT);
1923 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1924 iwl_get_cmd_string(trans, cmd->id),
1925 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1927 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1928 txq->read_ptr, txq->write_ptr);
1930 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1931 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1932 iwl_get_cmd_string(trans, cmd->id));
1935 iwl_trans_pcie_sync_nmi(trans);
1939 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1940 iwl_trans_pcie_dump_regs(trans);
1941 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1942 iwl_get_cmd_string(trans, cmd->id));
1948 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1949 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1950 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1955 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1956 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1957 iwl_get_cmd_string(trans, cmd->id));
1965 if (cmd->flags & CMD_WANT_SKB) {
1967 * Cancel the CMD_WANT_SKB flag for the cmd in the
1968 * TX cmd queue. Otherwise in case the cmd comes
1969 * in later, it will possibly set an invalid
1970 * address (cmd->meta.source).
1972 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1975 if (cmd->resp_pkt) {
1977 cmd->resp_pkt = NULL;
1983 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1985 /* Make sure the NIC is still alive in the bus */
1986 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
1989 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1990 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1991 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1996 if (cmd->flags & CMD_ASYNC)
1997 return iwl_pcie_send_hcmd_async(trans, cmd);
1999 /* We still can fail on RFKILL that can be asserted while we wait */
2000 return iwl_pcie_send_hcmd_sync(trans, cmd);
2003 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
2004 struct iwl_txq *txq, u8 hdr_len,
2005 struct iwl_cmd_meta *out_meta)
2011 * Set up TFD's third entry to point directly to remainder
2012 * of skb's head, if any
2014 head_tb_len = skb_headlen(skb) - hdr_len;
2016 if (head_tb_len > 0) {
2017 dma_addr_t tb_phys = dma_map_single(trans->dev,
2018 skb->data + hdr_len,
2019 head_tb_len, DMA_TO_DEVICE);
2020 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
2022 trace_iwlwifi_dev_tx_tb(trans->dev, skb,
2023 skb->data + hdr_len,
2025 iwl_pcie_txq_build_tfd(trans, txq, tb_phys, head_tb_len, false);
2028 /* set up the remaining entries to point to the data */
2029 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2030 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2034 if (!skb_frag_size(frag))
2037 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
2038 skb_frag_size(frag), DMA_TO_DEVICE);
2040 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
2042 trace_iwlwifi_dev_tx_tb(trans->dev, skb,
2043 skb_frag_address(frag),
2044 skb_frag_size(frag));
2045 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2046 skb_frag_size(frag), false);
2050 out_meta->tbs |= BIT(tb_idx);
2057 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len)
2059 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2060 struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page);
2065 /* enough room on this page */
2066 if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE)
2069 /* We don't have enough room on this page, get a new one. */
2070 __free_page(p->page);
2073 p->page = alloc_page(GFP_ATOMIC);
2076 p->pos = page_address(p->page);
2080 static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
2081 bool ipv6, unsigned int len)
2084 struct ipv6hdr *iphv6 = iph;
2086 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr,
2087 len + tcph->doff * 4,
2090 struct iphdr *iphv4 = iph;
2092 ip_send_check(iphv4);
2093 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr,
2094 len + tcph->doff * 4,
2099 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2100 struct iwl_txq *txq, u8 hdr_len,
2101 struct iwl_cmd_meta *out_meta,
2102 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2104 struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
2105 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
2106 struct ieee80211_hdr *hdr = (void *)skb->data;
2107 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
2108 unsigned int mss = skb_shinfo(skb)->gso_size;
2109 u16 length, iv_len, amsdu_pad;
2111 struct iwl_tso_hdr_page *hdr_page;
2112 struct page **page_ptr;
2115 /* if the packet is protected, then it must be CCMP or GCMP */
2116 BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
2117 iv_len = ieee80211_has_protected(hdr->frame_control) ?
2118 IEEE80211_CCMP_HDR_LEN : 0;
2120 trace_iwlwifi_dev_tx(trans->dev, skb,
2121 iwl_pcie_get_tfd(trans, txq, txq->write_ptr),
2122 trans_pcie->tfd_size,
2123 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0);
2125 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
2126 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
2127 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
2130 /* total amount of header we may need for this A-MSDU */
2131 hdr_room = DIV_ROUND_UP(total_len, mss) *
2132 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
2134 /* Our device supports 9 segments at most, it will fit in 1 page */
2135 hdr_page = get_page_hdr(trans, hdr_room);
2139 get_page(hdr_page->page);
2140 start_hdr = hdr_page->pos;
2141 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
2142 *page_ptr = hdr_page->page;
2143 memcpy(hdr_page->pos, skb->data + hdr_len, iv_len);
2144 hdr_page->pos += iv_len;
2147 * Pull the ieee80211 header + IV to be able to use TSO core,
2148 * we will restore it for the tx_status flow.
2150 skb_pull(skb, hdr_len + iv_len);
2153 * Remove the length of all the headers that we don't actually
2154 * have in the MPDU by themselves, but that we duplicate into
2155 * all the different MSDUs inside the A-MSDU.
2157 le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen);
2159 tso_start(skb, &tso);
2162 /* this is the data left for this subframe */
2163 unsigned int data_left =
2164 min_t(unsigned int, mss, total_len);
2165 struct sk_buff *csum_skb = NULL;
2166 unsigned int hdr_tb_len;
2167 dma_addr_t hdr_tb_phys;
2168 struct tcphdr *tcph;
2169 u8 *iph, *subf_hdrs_start = hdr_page->pos;
2171 total_len -= data_left;
2173 memset(hdr_page->pos, 0, amsdu_pad);
2174 hdr_page->pos += amsdu_pad;
2175 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
2177 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
2178 hdr_page->pos += ETH_ALEN;
2179 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
2180 hdr_page->pos += ETH_ALEN;
2182 length = snap_ip_tcp_hdrlen + data_left;
2183 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
2184 hdr_page->pos += sizeof(length);
2187 * This will copy the SNAP as well which will be considered
2190 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
2191 iph = hdr_page->pos + 8;
2192 tcph = (void *)(iph + ip_hdrlen);
2194 /* For testing on current hardware only */
2195 if (trans_pcie->sw_csum_tx) {
2196 csum_skb = alloc_skb(data_left + tcp_hdrlen(skb),
2201 iwl_compute_pseudo_hdr_csum(iph, tcph,
2206 skb_put_data(csum_skb, tcph, tcp_hdrlen(skb));
2207 skb_reset_transport_header(csum_skb);
2208 csum_skb->csum_start =
2209 (unsigned char *)tcp_hdr(csum_skb) -
2213 hdr_page->pos += snap_ip_tcp_hdrlen;
2215 hdr_tb_len = hdr_page->pos - start_hdr;
2216 hdr_tb_phys = dma_map_single(trans->dev, start_hdr,
2217 hdr_tb_len, DMA_TO_DEVICE);
2218 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) {
2219 dev_kfree_skb(csum_skb);
2222 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2224 trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr,
2226 /* add this subframe's headers' length to the tx_cmd */
2227 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start);
2229 /* prepare the start_hdr for the next subframe */
2230 start_hdr = hdr_page->pos;
2232 /* put the payload */
2234 unsigned int size = min_t(unsigned int, tso.size,
2238 if (trans_pcie->sw_csum_tx)
2239 skb_put_data(csum_skb, tso.data, size);
2241 tb_phys = dma_map_single(trans->dev, tso.data,
2242 size, DMA_TO_DEVICE);
2243 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2244 dev_kfree_skb(csum_skb);
2248 iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2250 trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data,
2254 tso_build_data(skb, &tso, size);
2257 /* For testing on early hardware only */
2258 if (trans_pcie->sw_csum_tx) {
2261 csum = skb_checksum(csum_skb,
2262 skb_checksum_start_offset(csum_skb),
2264 skb_checksum_start_offset(csum_skb),
2266 dev_kfree_skb(csum_skb);
2267 dma_sync_single_for_cpu(trans->dev, hdr_tb_phys,
2268 hdr_tb_len, DMA_TO_DEVICE);
2269 tcph->check = csum_fold(csum);
2270 dma_sync_single_for_device(trans->dev, hdr_tb_phys,
2271 hdr_tb_len, DMA_TO_DEVICE);
2275 /* re -add the WiFi header and IV */
2276 skb_push(skb, hdr_len + iv_len);
2280 #else /* CONFIG_INET */
2281 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2282 struct iwl_txq *txq, u8 hdr_len,
2283 struct iwl_cmd_meta *out_meta,
2284 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2286 /* No A-MSDU without CONFIG_INET */
2291 #endif /* CONFIG_INET */
2293 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2294 struct iwl_device_cmd *dev_cmd, int txq_id)
2296 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2297 struct ieee80211_hdr *hdr;
2298 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
2299 struct iwl_cmd_meta *out_meta;
2300 struct iwl_txq *txq;
2301 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2305 bool wait_write_ptr;
2311 txq = trans_pcie->txq[txq_id];
2313 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
2314 "TX on unused queue %d\n", txq_id))
2317 if (unlikely(trans_pcie->sw_csum_tx &&
2318 skb->ip_summed == CHECKSUM_PARTIAL)) {
2319 int offs = skb_checksum_start_offset(skb);
2320 int csum_offs = offs + skb->csum_offset;
2323 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
2326 csum = skb_checksum(skb, offs, skb->len - offs, 0);
2327 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
2329 skb->ip_summed = CHECKSUM_UNNECESSARY;
2332 if (skb_is_nonlinear(skb) &&
2333 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
2334 __skb_linearize(skb))
2337 /* mac80211 always puts the full header into the SKB's head,
2338 * so there's no need to check if it's readable there
2340 hdr = (struct ieee80211_hdr *)skb->data;
2341 fc = hdr->frame_control;
2342 hdr_len = ieee80211_hdrlen(fc);
2344 spin_lock(&txq->lock);
2346 if (iwl_queue_space(trans, txq) < txq->high_mark) {
2347 iwl_stop_queue(trans, txq);
2349 /* don't put the packet on the ring, if there is no room */
2350 if (unlikely(iwl_queue_space(trans, txq) < 3)) {
2351 struct iwl_device_cmd **dev_cmd_ptr;
2353 dev_cmd_ptr = (void *)((u8 *)skb->cb +
2354 trans_pcie->dev_cmd_offs);
2356 *dev_cmd_ptr = dev_cmd;
2357 __skb_queue_tail(&txq->overflow_q, skb);
2359 spin_unlock(&txq->lock);
2364 /* In AGG mode, the index in the ring must correspond to the WiFi
2365 * sequence number. This is a HW requirements to help the SCD to parse
2367 * Check here that the packets are in the right place on the ring.
2369 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
2370 WARN_ONCE(txq->ampdu &&
2371 (wifi_seq & 0xff) != txq->write_ptr,
2372 "Q: %d WiFi Seq %d tfdNum %d",
2373 txq_id, wifi_seq, txq->write_ptr);
2375 /* Set up driver data for this TFD */
2376 txq->entries[txq->write_ptr].skb = skb;
2377 txq->entries[txq->write_ptr].cmd = dev_cmd;
2379 dev_cmd->hdr.sequence =
2380 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2381 INDEX_TO_SEQ(txq->write_ptr)));
2383 tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr);
2384 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2385 offsetof(struct iwl_tx_cmd, scratch);
2387 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
2388 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2390 /* Set up first empty entry in queue's array of Tx/cmd buffers */
2391 out_meta = &txq->entries[txq->write_ptr].meta;
2392 out_meta->flags = 0;
2395 * The second TB (tb1) points to the remainder of the TX command
2396 * and the 802.11 header - dword aligned size
2397 * (This calculation modifies the TX command, so do it before the
2398 * setup of the first TB)
2400 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
2401 hdr_len - IWL_FIRST_TB_SIZE;
2402 /* do not align A-MSDU to dword as the subframe header aligns it */
2403 amsdu = ieee80211_is_data_qos(fc) &&
2404 (*ieee80211_get_qos_ctl(hdr) &
2405 IEEE80211_QOS_CTL_A_MSDU_PRESENT);
2406 if (trans_pcie->sw_csum_tx || !amsdu) {
2407 tb1_len = ALIGN(len, 4);
2408 /* Tell NIC about any 2-byte padding after MAC header */
2410 tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD);
2416 * The first TB points to bi-directional DMA data, we'll
2417 * memcpy the data into it later.
2419 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
2420 IWL_FIRST_TB_SIZE, true);
2422 /* there must be data left over for TB1 or this code must be changed */
2423 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE);
2425 /* map the data for TB1 */
2426 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
2427 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2428 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2430 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
2432 trace_iwlwifi_dev_tx(trans->dev, skb,
2433 iwl_pcie_get_tfd(trans, txq,
2435 trans_pcie->tfd_size,
2436 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
2440 * If gso_size wasn't set, don't give the frame "amsdu treatment"
2441 * (adding subframes, etc.).
2442 * This can happen in some testing flows when the amsdu was already
2443 * pre-built, and we just need to send the resulting skb.
2445 if (amsdu && skb_shinfo(skb)->gso_size) {
2446 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2451 struct sk_buff *frag;
2453 if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2457 skb_walk_frags(skb, frag) {
2458 if (unlikely(iwl_fill_data_tbs(trans, frag, txq, 0,
2464 /* building the A-MSDU might have changed this data, so memcpy it now */
2465 memcpy(&txq->first_tb_bufs[txq->write_ptr], dev_cmd, IWL_FIRST_TB_SIZE);
2467 tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr);
2468 /* Set up entry for this TFD in Tx byte-count array */
2469 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
2470 iwl_pcie_tfd_get_num_tbs(trans, tfd));
2472 wait_write_ptr = ieee80211_has_morefrags(fc);
2474 /* start timer if queue currently empty */
2475 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) {
2477 * If the TXQ is active, then set the timer, if not,
2478 * set the timer in remainder so that the timer will
2479 * be armed with the right value when the station will
2483 mod_timer(&txq->stuck_timer,
2484 jiffies + txq->wd_timeout);
2486 txq->frozen_expiry_remainder = txq->wd_timeout;
2489 /* Tell device the write index *just past* this latest filled TFD */
2490 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr);
2491 if (!wait_write_ptr)
2492 iwl_pcie_txq_inc_wr_ptr(trans, txq);
2495 * At this point the frame is "transmitted" successfully
2496 * and we will get a TX status notification eventually.
2498 spin_unlock(&txq->lock);
2501 iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr);
2502 spin_unlock(&txq->lock);