drivers/net/wireless/intel/iwlwifi/pcie/trans.c

   1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2007-2015, 2018-2023 Intel Corporation
   4  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
   5  * Copyright (C) 2016-2017 Intel Deutschland GmbH
   6  */
   7 #include <linux/pci.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/sched.h>
  11 #include <linux/bitops.h>
  12 #include <linux/gfp.h>
  13 #include <linux/vmalloc.h>
  14 #include <linux/module.h>
  15 #include <linux/wait.h>
  16 #include <linux/seq_file.h>
  17
  18 #include "iwl-drv.h"
  19 #include "iwl-trans.h"
  20 #include "iwl-csr.h"
  21 #include "iwl-prph.h"
  22 #include "iwl-scd.h"
  23 #include "iwl-agn-hw.h"
  24 #include "fw/error-dump.h"
  25 #include "fw/dbg.h"
  26 #include "fw/api/tx.h"
  27 #include "mei/iwl-mei.h"
  28 #include "internal.h"
  29 #include "iwl-fh.h"
  30 #include "iwl-context-info-gen3.h"
  31
  32 /* extended range in FW SRAM */
  33 #define IWL_FW_MEM_EXTENDED_START       0x40000
  34 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  35
  36 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
  37 {
  38 #define PCI_DUMP_SIZE           352
  39 #define PCI_MEM_DUMP_SIZE       64
  40 #define PCI_PARENT_DUMP_SIZE    524
  41 #define PREFIX_LEN              32
  42         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  43         struct pci_dev *pdev = trans_pcie->pci_dev;
  44         u32 i, pos, alloc_size, *ptr, *buf;
  45         char *prefix;
  46
  47         if (trans_pcie->pcie_dbg_dumped_once)
  48                 return;
  49
  50         /* Should be a multiple of 4 */
  51         BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
  52         BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);
  53         BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);
  54
  55         /* Alloc a max size buffer */
  56         alloc_size = PCI_ERR_ROOT_ERR_SRC +  4 + PREFIX_LEN;
  57         alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
  58         alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
  59         alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
  60
  61         buf = kmalloc(alloc_size, GFP_ATOMIC);
  62         if (!buf)
  63                 return;
  64         prefix = (char *)buf + alloc_size - PREFIX_LEN;
  65
  66         IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
  67
  68         /* Print wifi device registers */
  69         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
  70         IWL_ERR(trans, "iwlwifi device config registers:\n");
  71         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
  72                 if (pci_read_config_dword(pdev, i, ptr))
  73                         goto err_read;
  74         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
  75
  76         IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
  77         for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
  78                 *ptr = iwl_read32(trans, i);
  79         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
  80
  81         pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
  82         if (pos) {
  83                 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
  84                 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
  85                         if (pci_read_config_dword(pdev, pos + i, ptr))
  86                                 goto err_read;
  87                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
  88                                32, 4, buf, i, 0);
  89         }
  90
  91         /* Print parent device registers next */
  92         if (!pdev->bus->self)
  93                 goto out;
  94
  95         pdev = pdev->bus->self;
  96         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
  97
  98         IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
  99                 pci_name(pdev));
 100         for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
 101                 if (pci_read_config_dword(pdev, i, ptr))
 102                         goto err_read;
 103         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 104
 105         /* Print root port AER registers */
 106         pos = 0;
 107         pdev = pcie_find_root_port(pdev);
 108         if (pdev)
 109                 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 110         if (pos) {
 111                 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
 112                         pci_name(pdev));
 113                 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 114                 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
 115                         if (pci_read_config_dword(pdev, pos + i, ptr))
 116                                 goto err_read;
 117                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
 118                                4, buf, i, 0);
 119         }
 120         goto out;
 121
 122 err_read:
 123         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 124         IWL_ERR(trans, "Read failed at 0x%X\n", i);
 125 out:
 126         trans_pcie->pcie_dbg_dumped_once = 1;
 127         kfree(buf);
 128 }
 129
 130 static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans,
 131                                    bool retake_ownership)
 132 {
 133         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 134         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
 135                 iwl_set_bit(trans, CSR_GP_CNTRL,
 136                             CSR_GP_CNTRL_REG_FLAG_SW_RESET);
 137                 usleep_range(10000, 20000);
 138         } else {
 139                 iwl_set_bit(trans, CSR_RESET,
 140                             CSR_RESET_REG_FLAG_SW_RESET);
 141                 usleep_range(5000, 6000);
 142         }
 143
 144         if (retake_ownership)
 145                 return iwl_pcie_prepare_card_hw(trans);
 146
 147         return 0;
 148 }
 149
 150 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
 151 {
 152         struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
 153
 154         if (!fw_mon->size)
 155                 return;
 156
 157         dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
 158                           fw_mon->physical);
 159
 160         fw_mon->block = NULL;
 161         fw_mon->physical = 0;
 162         fw_mon->size = 0;
 163 }
 164
 165 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
 166                                             u8 max_power)
 167 {
 168         struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
 169         void *block = NULL;
 170         dma_addr_t physical = 0;
 171         u32 size = 0;
 172         u8 power;
 173
 174         if (fw_mon->size) {
 175                 memset(fw_mon->block, 0, fw_mon->size);
 176                 return;
 177         }
 178
 179         /* need at least 2 KiB, so stop at 11 */
 180         for (power = max_power; power >= 11; power--) {
 181                 size = BIT(power);
 182                 block = dma_alloc_coherent(trans->dev, size, &physical,
 183                                            GFP_KERNEL | __GFP_NOWARN);
 184                 if (!block)
 185                         continue;
 186
 187                 IWL_INFO(trans,
 188                          "Allocated 0x%08x bytes for firmware monitor.\n",
 189                          size);
 190                 break;
 191         }
 192
 193         if (WARN_ON_ONCE(!block))
 194                 return;
 195
 196         if (power != max_power)
 197                 IWL_ERR(trans,
 198                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 199                         (unsigned long)BIT(power - 10),
 200                         (unsigned long)BIT(max_power - 10));
 201
 202         fw_mon->block = block;
 203         fw_mon->physical = physical;
 204         fw_mon->size = size;
 205 }
 206
 207 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 208 {
 209         if (!max_power) {
 210                 /* default max_power is maximum */
 211                 max_power = 26;
 212         } else {
 213                 max_power += 11;
 214         }
 215
 216         if (WARN(max_power > 26,
 217                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 218                  max_power))
 219                 return;
 220
 221         iwl_pcie_alloc_fw_monitor_block(trans, max_power);
 222 }
 223
 224 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 225 {
 226         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 227                     ((reg & 0x0000ffff) | (2 << 28)));
 228         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 229 }
 230
 231 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 232 {
 233         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 234         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 235                     ((reg & 0x0000ffff) | (3 << 28)));
 236 }
 237
 238 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 239 {
 240         if (trans->cfg->apmg_not_supported)
 241                 return;
 242
 243         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 244                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 245                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 246                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 247         else
 248                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 249                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 250                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 251 }
 252
 253 /* PCI registers */
 254 #define PCI_CFG_RETRY_TIMEOUT   0x041
 255
 256 void iwl_pcie_apm_config(struct iwl_trans *trans)
 257 {
 258         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 259         u16 lctl;
 260         u16 cap;
 261
 262         /*
 263          * L0S states have been found to be unstable with our devices
 264          * and in newer hardware they are not officially supported at
 265          * all, so we must always set the L0S_DISABLED bit.
 266          */
 267         iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
 268
 269         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 270         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 271
 272         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 273         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 274         IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
 275                         (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 276                         trans->ltr_enabled ? "En" : "Dis");
 277 }
 278
 279 /*
 280  * Start up NIC's basic functionality after it has been reset
 281  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 282  * NOTE:  This does not load uCode nor start the embedded processor
 283  */
 284 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 285 {
 286         int ret;
 287
 288         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 289
 290         /*
 291          * Use "set_bit" below rather than "write", to preserve any hardware
 292          * bits already set by default after reset.
 293          */
 294
 295         /* Disable L0S exit timer (platform NMI Work/Around) */
 296         if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
 297                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 298                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 299
 300         /*
 301          * Disable L0s without affecting L1;
 302          *  don't wait for ICH L0s (ICH bug W/A)
 303          */
 304         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 305                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 306
 307         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 308         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 309
 310         /*
 311          * Enable HAP INTA (interrupt from management bus) to
 312          * wake device's PCI Express link L1a -> L0s
 313          */
 314         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 315                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 316
 317         iwl_pcie_apm_config(trans);
 318
 319         /* Configure analog phase-lock-loop before activating to D0A */
 320         if (trans->trans_cfg->base_params->pll_cfg)
 321                 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 322
 323         ret = iwl_finish_nic_init(trans);
 324         if (ret)
 325                 return ret;
 326
 327         if (trans->cfg->host_interrupt_operation_mode) {
 328                 /*
 329                  * This is a bit of an abuse - This is needed for 7260 / 3160
 330                  * only check host_interrupt_operation_mode even if this is
 331                  * not related to host_interrupt_operation_mode.
 332                  *
 333                  * Enable the oscillator to count wake up time for L1 exit. This
 334                  * consumes slightly more power (100uA) - but allows to be sure
 335                  * that we wake up from L1 on time.
 336                  *
 337                  * This looks weird: read twice the same register, discard the
 338                  * value, set a bit, and yet again, read that same register
 339                  * just to discard the value. But that's the way the hardware
 340                  * seems to like it.
 341                  */
 342                 iwl_read_prph(trans, OSC_CLK);
 343                 iwl_read_prph(trans, OSC_CLK);
 344                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 345                 iwl_read_prph(trans, OSC_CLK);
 346                 iwl_read_prph(trans, OSC_CLK);
 347         }
 348
 349         /*
 350          * Enable DMA clock and wait for it to stabilize.
 351          *
 352          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 353          * bits do not disable clocks.  This preserves any hardware
 354          * bits already set by default in "CLK_CTRL_REG" after reset.
 355          */
 356         if (!trans->cfg->apmg_not_supported) {
 357                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 358                                APMG_CLK_VAL_DMA_CLK_RQT);
 359                 udelay(20);
 360
 361                 /* Disable L1-Active */
 362                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 363                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 364
 365                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 366                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 367                                APMG_RTC_INT_STT_RFKILL);
 368         }
 369
 370         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 371
 372         return 0;
 373 }
 374
 375 /*
 376  * Enable LP XTAL to avoid HW bug where device may consume much power if
 377  * FW is not loaded after device reset. LP XTAL is disabled by default
 378  * after device HW reset. Do it only if XTAL is fed by internal source.
 379  * Configure device's "persistence" mode to avoid resetting XTAL again when
 380  * SHRD_HW_RST occurs in S3.
 381  */
 382 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 383 {
 384         int ret;
 385         u32 apmg_gp1_reg;
 386         u32 apmg_xtal_cfg_reg;
 387         u32 dl_cfg_reg;
 388
 389         /* Force XTAL ON */
 390         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 391                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 392
 393         ret = iwl_trans_pcie_sw_reset(trans, true);
 394
 395         if (!ret)
 396                 ret = iwl_finish_nic_init(trans);
 397
 398         if (WARN_ON(ret)) {
 399                 /* Release XTAL ON request */
 400                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 401                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 402                 return;
 403         }
 404
 405         /*
 406          * Clear "disable persistence" to avoid LP XTAL resetting when
 407          * SHRD_HW_RST is applied in S3.
 408          */
 409         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 410                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 411
 412         /*
 413          * Force APMG XTAL to be active to prevent its disabling by HW
 414          * caused by APMG idle state.
 415          */
 416         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 417                                                     SHR_APMG_XTAL_CFG_REG);
 418         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 419                                  apmg_xtal_cfg_reg |
 420                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 421
 422         ret = iwl_trans_pcie_sw_reset(trans, true);
 423         if (ret)
 424                 IWL_ERR(trans,
 425                         "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n");
 426
 427         /* Enable LP XTAL by indirect access through CSR */
 428         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 429         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 430                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 431                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 432
 433         /* Clear delay line clock power up */
 434         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 435         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 436                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 437
 438         /*
 439          * Enable persistence mode to avoid LP XTAL resetting when
 440          * SHRD_HW_RST is applied in S3.
 441          */
 442         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 443                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 444
 445         /*
 446          * Clear "initialization complete" bit to move adapter from
 447          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 448          */
 449         iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 450
 451         /* Activates XTAL resources monitor */
 452         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 453                                  CSR_MONITOR_XTAL_RESOURCES);
 454
 455         /* Release XTAL ON request */
 456         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 457                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 458         udelay(10);
 459
 460         /* Release APMG XTAL */
 461         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 462                                  apmg_xtal_cfg_reg &
 463                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 464 }
 465
 466 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 467 {
 468         int ret;
 469
 470         /* stop device's busmaster DMA activity */
 471
 472         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
 473                 iwl_set_bit(trans, CSR_GP_CNTRL,
 474                             CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);
 475
 476                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 477                                    CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
 478                                    CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
 479                                    100);
 480                 usleep_range(10000, 20000);
 481         } else {
 482                 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 483
 484                 ret = iwl_poll_bit(trans, CSR_RESET,
 485                                    CSR_RESET_REG_FLAG_MASTER_DISABLED,
 486                                    CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 487         }
 488
 489         if (ret < 0)
 490                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 491
 492         IWL_DEBUG_INFO(trans, "stop master\n");
 493 }
 494
 495 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 496 {
 497         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 498
 499         if (op_mode_leave) {
 500                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 501                         iwl_pcie_apm_init(trans);
 502
 503                 /* inform ME that we are leaving */
 504                 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
 505                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 506                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 507                 else if (trans->trans_cfg->device_family >=
 508                          IWL_DEVICE_FAMILY_8000) {
 509                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 510                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 511                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 512                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 513                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 514                         mdelay(1);
 515                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 516                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 517                 }
 518                 mdelay(5);
 519         }
 520
 521         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 522
 523         /* Stop device's DMA activity */
 524         iwl_pcie_apm_stop_master(trans);
 525
 526         if (trans->cfg->lp_xtal_workaround) {
 527                 iwl_pcie_apm_lp_xtal_enable(trans);
 528                 return;
 529         }
 530
 531         iwl_trans_pcie_sw_reset(trans, false);
 532
 533         /*
 534          * Clear "initialization complete" bit to move adapter from
 535          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 536          */
 537         iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 538 }
 539
 540 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 541 {
 542         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 543         int ret;
 544
 545         /* nic_init */
 546         spin_lock_bh(&trans_pcie->irq_lock);
 547         ret = iwl_pcie_apm_init(trans);
 548         spin_unlock_bh(&trans_pcie->irq_lock);
 549
 550         if (ret)
 551                 return ret;
 552
 553         iwl_pcie_set_pwr(trans, false);
 554
 555         iwl_op_mode_nic_config(trans->op_mode);
 556
 557         /* Allocate the RX queue, or reset if it is already allocated */
 558         ret = iwl_pcie_rx_init(trans);
 559         if (ret)
 560                 return ret;
 561
 562         /* Allocate or reset and init all Tx and Command queues */
 563         if (iwl_pcie_tx_init(trans)) {
 564                 iwl_pcie_rx_free(trans);
 565                 return -ENOMEM;
 566         }
 567
 568         if (trans->trans_cfg->base_params->shadow_reg_enable) {
 569                 /* enable shadow regs in HW */
 570                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 571                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 572         }
 573
 574         return 0;
 575 }
 576
 577 #define HW_READY_TIMEOUT (50)
 578
 579 /* Note: returns poll_bit return value, which is >= 0 if success */
 580 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 581 {
 582         int ret;
 583
 584         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 585                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 586
 587         /* See if we got it */
 588         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 589                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 590                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 591                            HW_READY_TIMEOUT);
 592
 593         if (ret >= 0)
 594                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 595
 596         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 597         return ret;
 598 }
 599
 600 /* Note: returns standard 0/-ERROR code */
 601 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 602 {
 603         int ret;
 604         int iter;
 605
 606         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 607
 608         ret = iwl_pcie_set_hw_ready(trans);
 609         /* If the card is ready, exit 0 */
 610         if (ret >= 0) {
 611                 trans->csme_own = false;
 612                 return 0;
 613         }
 614
 615         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 616                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 617         usleep_range(1000, 2000);
 618
 619         for (iter = 0; iter < 10; iter++) {
 620                 int t = 0;
 621
 622                 /* If HW is not ready, prepare the conditions to check again */
 623                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 624                             CSR_HW_IF_CONFIG_REG_PREPARE);
 625
 626                 do {
 627                         ret = iwl_pcie_set_hw_ready(trans);
 628                         if (ret >= 0) {
 629                                 trans->csme_own = false;
 630                                 return 0;
 631                         }
 632
 633                         if (iwl_mei_is_connected()) {
 634                                 IWL_DEBUG_INFO(trans,
 635                                                "Couldn't prepare the card but SAP is connected\n");
 636                                 trans->csme_own = true;
 637                                 if (trans->trans_cfg->device_family !=
 638                                     IWL_DEVICE_FAMILY_9000)
 639                                         IWL_ERR(trans,
 640                                                 "SAP not supported for this NIC family\n");
 641
 642                                 return -EBUSY;
 643                         }
 644
 645                         usleep_range(200, 1000);
 646                         t += 200;
 647                 } while (t < 150000);
 648                 msleep(25);
 649         }
 650
 651         IWL_ERR(trans, "Couldn't prepare the card\n");
 652
 653         return ret;
 654 }
 655
 656 /*
 657  * ucode
 658  */
 659 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
 660                                             u32 dst_addr, dma_addr_t phy_addr,
 661                                             u32 byte_cnt)
 662 {
 663         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 664                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 665
 666         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 667                     dst_addr);
 668
 669         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 670                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 671
 672         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 673                     (iwl_get_dma_hi_addr(phy_addr)
 674                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 675
 676         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 677                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
 678                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
 679                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 680
 681         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 682                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 683                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 684                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 685 }
 686
 687 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
 688                                         u32 dst_addr, dma_addr_t phy_addr,
 689                                         u32 byte_cnt)
 690 {
 691         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 692         int ret;
 693
 694         trans_pcie->ucode_write_complete = false;
 695
 696         if (!iwl_trans_grab_nic_access(trans))
 697                 return -EIO;
 698
 699         iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
 700                                         byte_cnt);
 701         iwl_trans_release_nic_access(trans);
 702
 703         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 704                                  trans_pcie->ucode_write_complete, 5 * HZ);
 705         if (!ret) {
 706                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 707                 iwl_trans_pcie_dump_regs(trans);
 708                 return -ETIMEDOUT;
 709         }
 710
 711         return 0;
 712 }
 713
 714 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 715                             const struct fw_desc *section)
 716 {
 717         u8 *v_addr;
 718         dma_addr_t p_addr;
 719         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 720         int ret = 0;
 721
 722         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 723                      section_num);
 724
 725         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 726                                     GFP_KERNEL | __GFP_NOWARN);
 727         if (!v_addr) {
 728                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 729                 chunk_sz = PAGE_SIZE;
 730                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 731                                             &p_addr, GFP_KERNEL);
 732                 if (!v_addr)
 733                         return -ENOMEM;
 734         }
 735
 736         for (offset = 0; offset < section->len; offset += chunk_sz) {
 737                 u32 copy_size, dst_addr;
 738                 bool extended_addr = false;
 739
 740                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 741                 dst_addr = section->offset + offset;
 742
 743                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 744                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 745                         extended_addr = true;
 746
 747                 if (extended_addr)
 748                         iwl_set_bits_prph(trans, LMPM_CHICK,
 749                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 750
 751                 memcpy(v_addr, (const u8 *)section->data + offset, copy_size);
 752                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 753                                                    copy_size);
 754
 755                 if (extended_addr)
 756                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 757                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 758
 759                 if (ret) {
 760                         IWL_ERR(trans,
 761                                 "Could not load the [%d] uCode section\n",
 762                                 section_num);
 763                         break;
 764                 }
 765         }
 766
 767         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 768         return ret;
 769 }
 770
 771 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 772                                            const struct fw_img *image,
 773                                            int cpu,
 774                                            int *first_ucode_section)
 775 {
 776         int shift_param;
 777         int i, ret = 0, sec_num = 0x1;
 778         u32 val, last_read_idx = 0;
 779
 780         if (cpu == 1) {
 781                 shift_param = 0;
 782                 *first_ucode_section = 0;
 783         } else {
 784                 shift_param = 16;
 785                 (*first_ucode_section)++;
 786         }
 787
 788         for (i = *first_ucode_section; i < image->num_sec; i++) {
 789                 last_read_idx = i;
 790
 791                 /*
 792                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 793                  * CPU1 to CPU2.
 794                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 795                  * CPU2 non paged to CPU2 paging sec.
 796                  */
 797                 if (!image->sec[i].data ||
 798                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 799                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 800                         IWL_DEBUG_FW(trans,
 801                                      "Break since Data not valid or Empty section, sec = %d\n",
 802                                      i);
 803                         break;
 804                 }
 805
 806                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 807                 if (ret)
 808                         return ret;
 809
 810                 /* Notify ucode of loaded section number and status */
 811                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 812                 val = val | (sec_num << shift_param);
 813                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 814
 815                 sec_num = (sec_num << 1) | 0x1;
 816         }
 817
 818         *first_ucode_section = last_read_idx;
 819
 820         iwl_enable_interrupts(trans);
 821
 822         if (trans->trans_cfg->gen2) {
 823                 if (cpu == 1)
 824                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 825                                        0xFFFF);
 826                 else
 827                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 828                                        0xFFFFFFFF);
 829         } else {
 830                 if (cpu == 1)
 831                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 832                                            0xFFFF);
 833                 else
 834                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 835                                            0xFFFFFFFF);
 836         }
 837
 838         return 0;
 839 }
 840
 841 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 842                                       const struct fw_img *image,
 843                                       int cpu,
 844                                       int *first_ucode_section)
 845 {
 846         int i, ret = 0;
 847         u32 last_read_idx = 0;
 848
 849         if (cpu == 1)
 850                 *first_ucode_section = 0;
 851         else
 852                 (*first_ucode_section)++;
 853
 854         for (i = *first_ucode_section; i < image->num_sec; i++) {
 855                 last_read_idx = i;
 856
 857                 /*
 858                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 859                  * CPU1 to CPU2.
 860                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 861                  * CPU2 non paged to CPU2 paging sec.
 862                  */
 863                 if (!image->sec[i].data ||
 864                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 865                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 866                         IWL_DEBUG_FW(trans,
 867                                      "Break since Data not valid or Empty section, sec = %d\n",
 868                                      i);
 869                         break;
 870                 }
 871
 872                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 873                 if (ret)
 874                         return ret;
 875         }
 876
 877         *first_ucode_section = last_read_idx;
 878
 879         return 0;
 880 }
 881
 882 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
 883 {
 884         enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
 885         struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
 886                 &trans->dbg.fw_mon_cfg[alloc_id];
 887         struct iwl_dram_data *frag;
 888
 889         if (!iwl_trans_dbg_ini_valid(trans))
 890                 return;
 891
 892         if (le32_to_cpu(fw_mon_cfg->buf_location) ==
 893             IWL_FW_INI_LOCATION_SRAM_PATH) {
 894                 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
 895                 /* set sram monitor by enabling bit 7 */
 896                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 897                             CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
 898
 899                 return;
 900         }
 901
 902         if (le32_to_cpu(fw_mon_cfg->buf_location) !=
 903             IWL_FW_INI_LOCATION_DRAM_PATH ||
 904             !trans->dbg.fw_mon_ini[alloc_id].num_frags)
 905                 return;
 906
 907         frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
 908
 909         IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
 910                      alloc_id);
 911
 912         iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
 913                             frag->physical >> MON_BUFF_SHIFT_VER2);
 914         iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
 915                             (frag->physical + frag->size - 256) >>
 916                             MON_BUFF_SHIFT_VER2);
 917 }
 918
 919 void iwl_pcie_apply_destination(struct iwl_trans *trans)
 920 {
 921         const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
 922         const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
 923         int i;
 924
 925         if (iwl_trans_dbg_ini_valid(trans)) {
 926                 iwl_pcie_apply_destination_ini(trans);
 927                 return;
 928         }
 929
 930         IWL_INFO(trans, "Applying debug destination %s\n",
 931                  get_fw_dbg_mode_string(dest->monitor_mode));
 932
 933         if (dest->monitor_mode == EXTERNAL_MODE)
 934                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 935         else
 936                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 937
 938         for (i = 0; i < trans->dbg.n_dest_reg; i++) {
 939                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 940                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 941
 942                 switch (dest->reg_ops[i].op) {
 943                 case CSR_ASSIGN:
 944                         iwl_write32(trans, addr, val);
 945                         break;
 946                 case CSR_SETBIT:
 947                         iwl_set_bit(trans, addr, BIT(val));
 948                         break;
 949                 case CSR_CLEARBIT:
 950                         iwl_clear_bit(trans, addr, BIT(val));
 951                         break;
 952                 case PRPH_ASSIGN:
 953                         iwl_write_prph(trans, addr, val);
 954                         break;
 955                 case PRPH_SETBIT:
 956                         iwl_set_bits_prph(trans, addr, BIT(val));
 957                         break;
 958                 case PRPH_CLEARBIT:
 959                         iwl_clear_bits_prph(trans, addr, BIT(val));
 960                         break;
 961                 case PRPH_BLOCKBIT:
 962                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 963                                 IWL_ERR(trans,
 964                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 965                                         val, addr);
 966                                 goto monitor;
 967                         }
 968                         break;
 969                 default:
 970                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 971                                 dest->reg_ops[i].op);
 972                         break;
 973                 }
 974         }
 975
 976 monitor:
 977         if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
 978                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 979                                fw_mon->physical >> dest->base_shift);
 980                 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
 981                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 982                                        (fw_mon->physical + fw_mon->size -
 983                                         256) >> dest->end_shift);
 984                 else
 985                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 986                                        (fw_mon->physical + fw_mon->size) >>
 987                                        dest->end_shift);
 988         }
 989 }
 990
 991 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 992                                 const struct fw_img *image)
 993 {
 994         int ret = 0;
 995         int first_ucode_section;
 996
 997         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 998                      image->is_dual_cpus ? "Dual" : "Single");
 999
1000         /* load to FW the binary non secured sections of CPU1 */
1001         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1002         if (ret)
1003                 return ret;
1004
1005         if (image->is_dual_cpus) {
1006                 /* set CPU2 header address */
1007                 iwl_write_prph(trans,
1008                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1009                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
1010
1011                 /* load to FW the binary sections of CPU2 */
1012                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1013                                                  &first_ucode_section);
1014                 if (ret)
1015                         return ret;
1016         }
1017
1018         if (iwl_pcie_dbg_on(trans))
1019                 iwl_pcie_apply_destination(trans);
1020
1021         iwl_enable_interrupts(trans);
1022
1023         /* release CPU reset */
1024         iwl_write32(trans, CSR_RESET, 0);
1025
1026         return 0;
1027 }
1028
1029 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1030                                           const struct fw_img *image)
1031 {
1032         int ret = 0;
1033         int first_ucode_section;
1034
1035         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1036                      image->is_dual_cpus ? "Dual" : "Single");
1037
1038         if (iwl_pcie_dbg_on(trans))
1039                 iwl_pcie_apply_destination(trans);
1040
1041         IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1042                         iwl_read_prph(trans, WFPM_GP2));
1043
1044         /*
1045          * Set default value. On resume reading the values that were
1046          * zeored can provide debug data on the resume flow.
1047          * This is for debugging only and has no functional impact.
1048          */
1049         iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1050
1051         /* configure the ucode to be ready to get the secured image */
1052         /* release CPU reset */
1053         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1054
1055         /* load to FW the binary Secured sections of CPU1 */
1056         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1057                                               &first_ucode_section);
1058         if (ret)
1059                 return ret;
1060
1061         /* load to FW the binary sections of CPU2 */
1062         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1063                                                &first_ucode_section);
1064 }
1065
1066 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1067 {
1068         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1069         bool hw_rfkill = iwl_is_rfkill_set(trans);
1070         bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1071         bool report;
1072
1073         if (hw_rfkill) {
1074                 set_bit(STATUS_RFKILL_HW, &trans->status);
1075                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1076         } else {
1077                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1078                 if (trans_pcie->opmode_down)
1079                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1080         }
1081
1082         report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1083
1084         if (prev != report)
1085                 iwl_trans_pcie_rf_kill(trans, report, false);
1086
1087         return hw_rfkill;
1088 }
1089
1090 struct iwl_causes_list {
1091         u16 mask_reg;
1092         u8 bit;
1093         u8 addr;
1094 };
1095
1096 #define IWL_CAUSE(reg, mask)                                            \
1097         {                                                               \
1098                 .mask_reg = reg,                                        \
1099                 .bit = ilog2(mask),                                     \
1100                 .addr = ilog2(mask) +                                   \
1101                         ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 :       \
1102                          (reg) == CSR_MSIX_HW_INT_MASK_AD ? 16 :        \
1103                          0xffff),       /* causes overflow warning */   \
1104         }
1105
1106 static const struct iwl_causes_list causes_list_common[] = {
1107         IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH0_NUM),
1108         IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH1_NUM),
1109         IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_S2D),
1110         IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_FH_ERR),
1111         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_ALIVE),
1112         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_WAKEUP),
1113         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RESET_DONE),
1114         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_TOP_FATAL_ERR),
1115         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_CT_KILL),
1116         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RF_KILL),
1117         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_PERIODIC),
1118         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SCD),
1119         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_FH_TX),
1120         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HW_ERR),
1121         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HAP),
1122 };
1123
1124 static const struct iwl_causes_list causes_list_pre_bz[] = {
1125         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR),
1126 };
1127
1128 static const struct iwl_causes_list causes_list_bz[] = {
1129         IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ),
1130 };
1131
1132 static void iwl_pcie_map_list(struct iwl_trans *trans,
1133                               const struct iwl_causes_list *causes,
1134                               int arr_size, int val)
1135 {
1136         int i;
1137
1138         for (i = 0; i < arr_size; i++) {
1139                 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1140                 iwl_clear_bit(trans, causes[i].mask_reg,
1141                               BIT(causes[i].bit));
1142         }
1143 }
1144
1145 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1146 {
1147         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1148         int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1149         /*
1150          * Access all non RX causes and map them to the default irq.
1151          * In case we are missing at least one interrupt vector,
1152          * the first interrupt vector will serve non-RX and FBQ causes.
1153          */
1154         iwl_pcie_map_list(trans, causes_list_common,
1155                           ARRAY_SIZE(causes_list_common), val);
1156         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1157                 iwl_pcie_map_list(trans, causes_list_bz,
1158                                   ARRAY_SIZE(causes_list_bz), val);
1159         else
1160                 iwl_pcie_map_list(trans, causes_list_pre_bz,
1161                                   ARRAY_SIZE(causes_list_pre_bz), val);
1162 }
1163
1164 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1165 {
1166         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1167         u32 offset =
1168                 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1169         u32 val, idx;
1170
1171         /*
1172          * The first RX queue - fallback queue, which is designated for
1173          * management frame, command responses etc, is always mapped to the
1174          * first interrupt vector. The other RX queues are mapped to
1175          * the other (N - 2) interrupt vectors.
1176          */
1177         val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1178         for (idx = 1; idx < trans->num_rx_queues; idx++) {
1179                 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1180                            MSIX_FH_INT_CAUSES_Q(idx - offset));
1181                 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1182         }
1183         iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1184
1185         val = MSIX_FH_INT_CAUSES_Q(0);
1186         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1187                 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1188         iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1189
1190         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1191                 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1192 }
1193
1194 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1195 {
1196         struct iwl_trans *trans = trans_pcie->trans;
1197
1198         if (!trans_pcie->msix_enabled) {
1199                 if (trans->trans_cfg->mq_rx_supported &&
1200                     test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1201                         iwl_write_umac_prph(trans, UREG_CHICK,
1202                                             UREG_CHICK_MSI_ENABLE);
1203                 return;
1204         }
1205         /*
1206          * The IVAR table needs to be configured again after reset,
1207          * but if the device is disabled, we can't write to
1208          * prph.
1209          */
1210         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1211                 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1212
1213         /*
1214          * Each cause from the causes list above and the RX causes is
1215          * represented as a byte in the IVAR table. The first nibble
1216          * represents the bound interrupt vector of the cause, the second
1217          * represents no auto clear for this cause. This will be set if its
1218          * interrupt vector is bound to serve other causes.
1219          */
1220         iwl_pcie_map_rx_causes(trans);
1221
1222         iwl_pcie_map_non_rx_causes(trans);
1223 }
1224
1225 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1226 {
1227         struct iwl_trans *trans = trans_pcie->trans;
1228
1229         iwl_pcie_conf_msix_hw(trans_pcie);
1230
1231         if (!trans_pcie->msix_enabled)
1232                 return;
1233
1234         trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1235         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1236         trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1237         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1238 }
1239
1240 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool from_irq)
1241 {
1242         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1243
1244         lockdep_assert_held(&trans_pcie->mutex);
1245
1246         if (trans_pcie->is_down)
1247                 return;
1248
1249         trans_pcie->is_down = true;
1250
1251         /* tell the device to stop sending interrupts */
1252         iwl_disable_interrupts(trans);
1253
1254         /* device going down, Stop using ICT table */
1255         iwl_pcie_disable_ict(trans);
1256
1257         /*
1258          * If a HW restart happens during firmware loading,
1259          * then the firmware loading might call this function
1260          * and later it might be called again due to the
1261          * restart. So don't process again if the device is
1262          * already dead.
1263          */
1264         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1265                 IWL_DEBUG_INFO(trans,
1266                                "DEVICE_ENABLED bit was set and is now cleared\n");
1267                 if (!from_irq)
1268                         iwl_pcie_synchronize_irqs(trans);
1269                 iwl_pcie_rx_napi_sync(trans);
1270                 iwl_pcie_tx_stop(trans);
1271                 iwl_pcie_rx_stop(trans);
1272
1273                 /* Power-down device's busmaster DMA clocks */
1274                 if (!trans->cfg->apmg_not_supported) {
1275                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1276                                        APMG_CLK_VAL_DMA_CLK_RQT);
1277                         udelay(5);
1278                 }
1279         }
1280
1281         /* Make sure (redundant) we've released our request to stay awake */
1282         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1283                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1284                               CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
1285         else
1286                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1287                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1288
1289         /* Stop the device, and put it in low power state */
1290         iwl_pcie_apm_stop(trans, false);
1291
1292         /* re-take ownership to prevent other users from stealing the device */
1293         iwl_trans_pcie_sw_reset(trans, true);
1294
1295         /*
1296          * Upon stop, the IVAR table gets erased, so msi-x won't
1297          * work. This causes a bug in RF-KILL flows, since the interrupt
1298          * that enables radio won't fire on the correct irq, and the
1299          * driver won't be able to handle the interrupt.
1300          * Configure the IVAR table again after reset.
1301          */
1302         iwl_pcie_conf_msix_hw(trans_pcie);
1303
1304         /*
1305          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1306          * This is a bug in certain verions of the hardware.
1307          * Certain devices also keep sending HW RF kill interrupt all
1308          * the time, unless the interrupt is ACKed even if the interrupt
1309          * should be masked. Re-ACK all the interrupts here.
1310          */
1311         iwl_disable_interrupts(trans);
1312
1313         /* clear all status bits */
1314         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1315         clear_bit(STATUS_INT_ENABLED, &trans->status);
1316         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1317
1318         /*
1319          * Even if we stop the HW, we still want the RF kill
1320          * interrupt
1321          */
1322         iwl_enable_rfkill_int(trans);
1323 }
1324
1325 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1326 {
1327         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1328
1329         if (trans_pcie->msix_enabled) {
1330                 int i;
1331
1332                 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1333                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1334         } else {
1335                 synchronize_irq(trans_pcie->pci_dev->irq);
1336         }
1337 }
1338
1339 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1340                                    const struct fw_img *fw, bool run_in_rfkill)
1341 {
1342         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1343         bool hw_rfkill;
1344         int ret;
1345
1346         /* This may fail if AMT took ownership of the device */
1347         if (iwl_pcie_prepare_card_hw(trans)) {
1348                 IWL_WARN(trans, "Exit HW not ready\n");
1349                 return -EIO;
1350         }
1351
1352         iwl_enable_rfkill_int(trans);
1353
1354         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1355
1356         /*
1357          * We enabled the RF-Kill interrupt and the handler may very
1358          * well be running. Disable the interrupts to make sure no other
1359          * interrupt can be fired.
1360          */
1361         iwl_disable_interrupts(trans);
1362
1363         /* Make sure it finished running */
1364         iwl_pcie_synchronize_irqs(trans);
1365
1366         mutex_lock(&trans_pcie->mutex);
1367
1368         /* If platform's RF_KILL switch is NOT set to KILL */
1369         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1370         if (hw_rfkill && !run_in_rfkill) {
1371                 ret = -ERFKILL;
1372                 goto out;
1373         }
1374
1375         /* Someone called stop_device, don't try to start_fw */
1376         if (trans_pcie->is_down) {
1377                 IWL_WARN(trans,
1378                          "Can't start_fw since the HW hasn't been started\n");
1379                 ret = -EIO;
1380                 goto out;
1381         }
1382
1383         /* make sure rfkill handshake bits are cleared */
1384         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1385         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1386                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1387
1388         /* clear (again), then enable host interrupts */
1389         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1390
1391         ret = iwl_pcie_nic_init(trans);
1392         if (ret) {
1393                 IWL_ERR(trans, "Unable to init nic\n");
1394                 goto out;
1395         }
1396
1397         /*
1398          * Now, we load the firmware and don't want to be interrupted, even
1399          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1400          * FH_TX interrupt which is needed to load the firmware). If the
1401          * RF-Kill switch is toggled, we will find out after having loaded
1402          * the firmware and return the proper value to the caller.
1403          */
1404         iwl_enable_fw_load_int(trans);
1405
1406         /* really make sure rfkill handshake bits are cleared */
1407         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1408         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1409
1410         /* Load the given image to the HW */
1411         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1412                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1413         else
1414                 ret = iwl_pcie_load_given_ucode(trans, fw);
1415
1416         /* re-check RF-Kill state since we may have missed the interrupt */
1417         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1418         if (hw_rfkill && !run_in_rfkill)
1419                 ret = -ERFKILL;
1420
1421 out:
1422         mutex_unlock(&trans_pcie->mutex);
1423         return ret;
1424 }
1425
1426 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1427 {
1428         iwl_pcie_reset_ict(trans);
1429         iwl_pcie_tx_start(trans, scd_addr);
1430 }
1431
1432 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1433                                        bool was_in_rfkill)
1434 {
1435         bool hw_rfkill;
1436
1437         /*
1438          * Check again since the RF kill state may have changed while
1439          * all the interrupts were disabled, in this case we couldn't
1440          * receive the RF kill interrupt and update the state in the
1441          * op_mode.
1442          * Don't call the op_mode if the rkfill state hasn't changed.
1443          * This allows the op_mode to call stop_device from the rfkill
1444          * notification without endless recursion. Under very rare
1445          * circumstances, we might have a small recursion if the rfkill
1446          * state changed exactly now while we were called from stop_device.
1447          * This is very unlikely but can happen and is supported.
1448          */
1449         hw_rfkill = iwl_is_rfkill_set(trans);
1450         if (hw_rfkill) {
1451                 set_bit(STATUS_RFKILL_HW, &trans->status);
1452                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1453         } else {
1454                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1455                 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1456         }
1457         if (hw_rfkill != was_in_rfkill)
1458                 iwl_trans_pcie_rf_kill(trans, hw_rfkill, false);
1459 }
1460
1461 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1462 {
1463         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1464         bool was_in_rfkill;
1465
1466         iwl_op_mode_time_point(trans->op_mode,
1467                                IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
1468                                NULL);
1469
1470         mutex_lock(&trans_pcie->mutex);
1471         trans_pcie->opmode_down = true;
1472         was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1473         _iwl_trans_pcie_stop_device(trans, false);
1474         iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1475         mutex_unlock(&trans_pcie->mutex);
1476 }
1477
1478 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq)
1479 {
1480         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1481                 IWL_TRANS_GET_PCIE_TRANS(trans);
1482
1483         lockdep_assert_held(&trans_pcie->mutex);
1484
1485         IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1486                  state ? "disabled" : "enabled");
1487         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state) &&
1488             !WARN_ON(trans->trans_cfg->gen2))
1489                 _iwl_trans_pcie_stop_device(trans, from_irq);
1490 }
1491
1492 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1493                                   bool test, bool reset)
1494 {
1495         iwl_disable_interrupts(trans);
1496
1497         /*
1498          * in testing mode, the host stays awake and the
1499          * hardware won't be reset (not even partially)
1500          */
1501         if (test)
1502                 return;
1503
1504         iwl_pcie_disable_ict(trans);
1505
1506         iwl_pcie_synchronize_irqs(trans);
1507
1508         iwl_clear_bit(trans, CSR_GP_CNTRL,
1509                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1510         iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1511
1512         if (reset) {
1513                 /*
1514                  * reset TX queues -- some of their registers reset during S3
1515                  * so if we don't reset everything here the D3 image would try
1516                  * to execute some invalid memory upon resume
1517                  */
1518                 iwl_trans_pcie_tx_reset(trans);
1519         }
1520
1521         iwl_pcie_set_pwr(trans, true);
1522 }
1523
1524 static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend)
1525 {
1526         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1527         int ret;
1528
1529         if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
1530                 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1531                                     suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND :
1532                                               UREG_DOORBELL_TO_ISR6_RESUME);
1533         else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1534                 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL,
1535                             suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND :
1536                                       CSR_IPC_SLEEP_CONTROL_RESUME);
1537         else
1538                 return 0;
1539
1540         ret = wait_event_timeout(trans_pcie->sx_waitq,
1541                                  trans_pcie->sx_complete, 2 * HZ);
1542
1543         /* Invalidate it toward next suspend or resume */
1544         trans_pcie->sx_complete = false;
1545
1546         if (!ret) {
1547                 IWL_ERR(trans, "Timeout %s D3\n",
1548                         suspend ? "entering" : "exiting");
1549                 return -ETIMEDOUT;
1550         }
1551
1552         return 0;
1553 }
1554
1555 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1556                                      bool reset)
1557 {
1558         int ret;
1559
1560         if (!reset)
1561                 /* Enable persistence mode to avoid reset */
1562                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1563                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1564
1565         ret = iwl_pcie_d3_handshake(trans, true);
1566         if (ret)
1567                 return ret;
1568
1569         iwl_pcie_d3_complete_suspend(trans, test, reset);
1570
1571         return 0;
1572 }
1573
1574 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1575                                     enum iwl_d3_status *status,
1576                                     bool test,  bool reset)
1577 {
1578         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1579         u32 val;
1580         int ret;
1581
1582         if (test) {
1583                 iwl_enable_interrupts(trans);
1584                 *status = IWL_D3_STATUS_ALIVE;
1585                 ret = 0;
1586                 goto out;
1587         }
1588
1589         iwl_set_bit(trans, CSR_GP_CNTRL,
1590                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1591
1592         ret = iwl_finish_nic_init(trans);
1593         if (ret)
1594                 return ret;
1595
1596         /*
1597          * Reconfigure IVAR table in case of MSIX or reset ict table in
1598          * MSI mode since HW reset erased it.
1599          * Also enables interrupts - none will happen as
1600          * the device doesn't know we're waking it up, only when
1601          * the opmode actually tells it after this call.
1602          */
1603         iwl_pcie_conf_msix_hw(trans_pcie);
1604         if (!trans_pcie->msix_enabled)
1605                 iwl_pcie_reset_ict(trans);
1606         iwl_enable_interrupts(trans);
1607
1608         iwl_pcie_set_pwr(trans, false);
1609
1610         if (!reset) {
1611                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1612                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1613         } else {
1614                 iwl_trans_pcie_tx_reset(trans);
1615
1616                 ret = iwl_pcie_rx_init(trans);
1617                 if (ret) {
1618                         IWL_ERR(trans,
1619                                 "Failed to resume the device (RX reset)\n");
1620                         return ret;
1621                 }
1622         }
1623
1624         IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1625                         iwl_read_umac_prph(trans, WFPM_GP2));
1626
1627         val = iwl_read32(trans, CSR_RESET);
1628         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1629                 *status = IWL_D3_STATUS_RESET;
1630         else
1631                 *status = IWL_D3_STATUS_ALIVE;
1632
1633 out:
1634         if (*status == IWL_D3_STATUS_ALIVE)
1635                 ret = iwl_pcie_d3_handshake(trans, false);
1636
1637         return ret;
1638 }
1639
1640 static void
1641 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1642                             struct iwl_trans *trans,
1643                             const struct iwl_cfg_trans_params *cfg_trans)
1644 {
1645         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1646         int max_irqs, num_irqs, i, ret;
1647         u16 pci_cmd;
1648         u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES;
1649
1650         if (!cfg_trans->mq_rx_supported)
1651                 goto enable_msi;
1652
1653         if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000)
1654                 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES;
1655
1656         max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues);
1657         for (i = 0; i < max_irqs; i++)
1658                 trans_pcie->msix_entries[i].entry = i;
1659
1660         num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1661                                          MSIX_MIN_INTERRUPT_VECTORS,
1662                                          max_irqs);
1663         if (num_irqs < 0) {
1664                 IWL_DEBUG_INFO(trans,
1665                                "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1666                                num_irqs);
1667                 goto enable_msi;
1668         }
1669         trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1670
1671         IWL_DEBUG_INFO(trans,
1672                        "MSI-X enabled. %d interrupt vectors were allocated\n",
1673                        num_irqs);
1674
1675         /*
1676          * In case the OS provides fewer interrupts than requested, different
1677          * causes will share the same interrupt vector as follows:
1678          * One interrupt less: non rx causes shared with FBQ.
1679          * Two interrupts less: non rx causes shared with FBQ and RSS.
1680          * More than two interrupts: we will use fewer RSS queues.
1681          */
1682         if (num_irqs <= max_irqs - 2) {
1683                 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1684                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1685                         IWL_SHARED_IRQ_FIRST_RSS;
1686         } else if (num_irqs == max_irqs - 1) {
1687                 trans_pcie->trans->num_rx_queues = num_irqs;
1688                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1689         } else {
1690                 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1691         }
1692
1693         IWL_DEBUG_INFO(trans,
1694                        "MSI-X enabled with rx queues %d, vec mask 0x%x\n",
1695                        trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask);
1696
1697         WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
1698
1699         trans_pcie->alloc_vecs = num_irqs;
1700         trans_pcie->msix_enabled = true;
1701         return;
1702
1703 enable_msi:
1704         ret = pci_enable_msi(pdev);
1705         if (ret) {
1706                 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1707                 /* enable rfkill interrupt: hw bug w/a */
1708                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1709                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1710                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1711                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1712                 }
1713         }
1714 }
1715
1716 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1717 {
1718 #if defined(CONFIG_SMP)
1719         int iter_rx_q, i, ret, cpu, offset;
1720         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1721
1722         i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1723         iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1724         offset = 1 + i;
1725         for (; i < iter_rx_q ; i++) {
1726                 /*
1727                  * Get the cpu prior to the place to search
1728                  * (i.e. return will be > i - 1).
1729                  */
1730                 cpu = cpumask_next(i - offset, cpu_online_mask);
1731                 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1732                 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1733                                             &trans_pcie->affinity_mask[i]);
1734                 if (ret)
1735                         IWL_ERR(trans_pcie->trans,
1736                                 "Failed to set affinity mask for IRQ %d\n",
1737                                 trans_pcie->msix_entries[i].vector);
1738         }
1739 #endif
1740 }
1741
1742 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1743                                       struct iwl_trans_pcie *trans_pcie)
1744 {
1745         int i;
1746
1747         for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1748                 int ret;
1749                 struct msix_entry *msix_entry;
1750                 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1751
1752                 if (!qname)
1753                         return -ENOMEM;
1754
1755                 msix_entry = &trans_pcie->msix_entries[i];
1756                 ret = devm_request_threaded_irq(&pdev->dev,
1757                                                 msix_entry->vector,
1758                                                 iwl_pcie_msix_isr,
1759                                                 (i == trans_pcie->def_irq) ?
1760                                                 iwl_pcie_irq_msix_handler :
1761                                                 iwl_pcie_irq_rx_msix_handler,
1762                                                 IRQF_SHARED,
1763                                                 qname,
1764                                                 msix_entry);
1765                 if (ret) {
1766                         IWL_ERR(trans_pcie->trans,
1767                                 "Error allocating IRQ %d\n", i);
1768
1769                         return ret;
1770                 }
1771         }
1772         iwl_pcie_irq_set_affinity(trans_pcie->trans);
1773
1774         return 0;
1775 }
1776
1777 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
1778 {
1779         u32 hpm, wprot;
1780
1781         switch (trans->trans_cfg->device_family) {
1782         case IWL_DEVICE_FAMILY_9000:
1783                 wprot = PREG_PRPH_WPROT_9000;
1784                 break;
1785         case IWL_DEVICE_FAMILY_22000:
1786                 wprot = PREG_PRPH_WPROT_22000;
1787                 break;
1788         default:
1789                 return 0;
1790         }
1791
1792         hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
1793         if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) {
1794                 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
1795
1796                 if (wprot_val & PREG_WFPM_ACCESS) {
1797                         IWL_ERR(trans,
1798                                 "Error, can not clear persistence bit\n");
1799                         return -EPERM;
1800                 }
1801                 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1802                                             hpm & ~PERSISTENCE_BIT);
1803         }
1804
1805         return 0;
1806 }
1807
1808 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1809 {
1810         int ret;
1811
1812         ret = iwl_finish_nic_init(trans);
1813         if (ret < 0)
1814                 return ret;
1815
1816         iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1817                           HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1818         udelay(20);
1819         iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1820                           HPM_HIPM_GEN_CFG_CR_PG_EN |
1821                           HPM_HIPM_GEN_CFG_CR_SLP_EN);
1822         udelay(20);
1823         iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1824                             HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1825
1826         return iwl_trans_pcie_sw_reset(trans, true);
1827 }
1828
1829 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1830 {
1831         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1832         int err;
1833
1834         lockdep_assert_held(&trans_pcie->mutex);
1835
1836         err = iwl_pcie_prepare_card_hw(trans);
1837         if (err) {
1838                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1839                 return err;
1840         }
1841
1842         err = iwl_trans_pcie_clear_persistence_bit(trans);
1843         if (err)
1844                 return err;
1845
1846         err = iwl_trans_pcie_sw_reset(trans, true);
1847         if (err)
1848                 return err;
1849
1850         if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1851             trans->trans_cfg->integrated) {
1852                 err = iwl_pcie_gen2_force_power_gating(trans);
1853                 if (err)
1854                         return err;
1855         }
1856
1857         err = iwl_pcie_apm_init(trans);
1858         if (err)
1859                 return err;
1860
1861         iwl_pcie_init_msix(trans_pcie);
1862
1863         /* From now on, the op_mode will be kept updated about RF kill state */
1864         iwl_enable_rfkill_int(trans);
1865
1866         trans_pcie->opmode_down = false;
1867
1868         /* Set is_down to false here so that...*/
1869         trans_pcie->is_down = false;
1870
1871         /* ...rfkill can call stop_device and set it false if needed */
1872         iwl_pcie_check_hw_rf_kill(trans);
1873
1874         return 0;
1875 }
1876
1877 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1878 {
1879         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1880         int ret;
1881
1882         mutex_lock(&trans_pcie->mutex);
1883         ret = _iwl_trans_pcie_start_hw(trans);
1884         mutex_unlock(&trans_pcie->mutex);
1885
1886         return ret;
1887 }
1888
1889 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1890 {
1891         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1892
1893         mutex_lock(&trans_pcie->mutex);
1894
1895         /* disable interrupts - don't enable HW RF kill interrupt */
1896         iwl_disable_interrupts(trans);
1897
1898         iwl_pcie_apm_stop(trans, true);
1899
1900         iwl_disable_interrupts(trans);
1901
1902         iwl_pcie_disable_ict(trans);
1903
1904         mutex_unlock(&trans_pcie->mutex);
1905
1906         iwl_pcie_synchronize_irqs(trans);
1907 }
1908
1909 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1910 {
1911         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1912 }
1913
1914 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1915 {
1916         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1917 }
1918
1919 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1920 {
1921         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1922 }
1923
1924 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1925 {
1926         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1927                 return 0x00FFFFFF;
1928         else
1929                 return 0x000FFFFF;
1930 }
1931
1932 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1933 {
1934         u32 mask = iwl_trans_pcie_prph_msk(trans);
1935
1936         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1937                                ((reg & mask) | (3 << 24)));
1938         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1939 }
1940
1941 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1942                                       u32 val)
1943 {
1944         u32 mask = iwl_trans_pcie_prph_msk(trans);
1945
1946         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1947                                ((addr & mask) | (3 << 24)));
1948         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1949 }
1950
1951 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1952                                      const struct iwl_trans_config *trans_cfg)
1953 {
1954         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1955
1956         /* free all first - we might be reconfigured for a different size */
1957         iwl_pcie_free_rbs_pool(trans);
1958
1959         trans->txqs.cmd.q_id = trans_cfg->cmd_queue;
1960         trans->txqs.cmd.fifo = trans_cfg->cmd_fifo;
1961         trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1962         trans->txqs.page_offs = trans_cfg->cb_data_offs;
1963         trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1964         trans->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver;
1965
1966         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1967                 trans_pcie->n_no_reclaim_cmds = 0;
1968         else
1969                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1970         if (trans_pcie->n_no_reclaim_cmds)
1971                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1972                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1973
1974         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1975         trans_pcie->rx_page_order =
1976                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1977         trans_pcie->rx_buf_bytes =
1978                 iwl_trans_get_rb_size(trans_pcie->rx_buf_size);
1979         trans_pcie->supported_dma_mask = DMA_BIT_MASK(12);
1980         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1981                 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11);
1982
1983         trans->txqs.bc_table_dword = trans_cfg->bc_table_dword;
1984         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1985
1986         trans->command_groups = trans_cfg->command_groups;
1987         trans->command_groups_size = trans_cfg->command_groups_size;
1988
1989
1990         trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake;
1991 }
1992
1993 void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions,
1994                                            struct device *dev)
1995 {
1996         u8 i;
1997         struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc;
1998
1999         /* free DRAM payloads */
2000         for (i = 0; i < dram_regions->n_regions; i++) {
2001                 dma_free_coherent(dev, dram_regions->drams[i].size,
2002                                   dram_regions->drams[i].block,
2003                                   dram_regions->drams[i].physical);
2004         }
2005         dram_regions->n_regions = 0;
2006
2007         /* free DRAM addresses array */
2008         if (desc_dram->block) {
2009                 dma_free_coherent(dev, desc_dram->size,
2010                                   desc_dram->block,
2011                                   desc_dram->physical);
2012         }
2013         memset(desc_dram, 0, sizeof(*desc_dram));
2014 }
2015
2016 static void iwl_pcie_free_invalid_tx_cmd(struct iwl_trans *trans)
2017 {
2018         iwl_pcie_free_dma_ptr(trans, &trans->invalid_tx_cmd);
2019 }
2020
2021 static int iwl_pcie_alloc_invalid_tx_cmd(struct iwl_trans *trans)
2022 {
2023         struct iwl_cmd_header_wide bad_cmd = {
2024                 .cmd = INVALID_WR_PTR_CMD,
2025                 .group_id = DEBUG_GROUP,
2026                 .sequence = cpu_to_le16(0xffff),
2027                 .length = cpu_to_le16(0),
2028                 .version = 0,
2029         };
2030         int ret;
2031
2032         ret = iwl_pcie_alloc_dma_ptr(trans, &trans->invalid_tx_cmd,
2033                                      sizeof(bad_cmd));
2034         if (ret)
2035                 return ret;
2036         memcpy(trans->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd));
2037         return 0;
2038 }
2039
2040 void iwl_trans_pcie_free(struct iwl_trans *trans)
2041 {
2042         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2043         int i;
2044
2045         iwl_pcie_synchronize_irqs(trans);
2046
2047         if (trans->trans_cfg->gen2)
2048                 iwl_txq_gen2_tx_free(trans);
2049         else
2050                 iwl_pcie_tx_free(trans);
2051         iwl_pcie_rx_free(trans);
2052
2053         if (trans_pcie->rba.alloc_wq) {
2054                 destroy_workqueue(trans_pcie->rba.alloc_wq);
2055                 trans_pcie->rba.alloc_wq = NULL;
2056         }
2057
2058         if (trans_pcie->msix_enabled) {
2059                 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2060                         irq_set_affinity_hint(
2061                                 trans_pcie->msix_entries[i].vector,
2062                                 NULL);
2063                 }
2064
2065                 trans_pcie->msix_enabled = false;
2066         } else {
2067                 iwl_pcie_free_ict(trans);
2068         }
2069
2070         free_netdev(trans_pcie->napi_dev);
2071
2072         iwl_pcie_free_invalid_tx_cmd(trans);
2073
2074         iwl_pcie_free_fw_monitor(trans);
2075
2076         iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data,
2077                                               trans->dev);
2078         iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data,
2079                                               trans->dev);
2080
2081         mutex_destroy(&trans_pcie->mutex);
2082         iwl_trans_free(trans);
2083 }
2084
2085 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
2086 {
2087         if (state)
2088                 set_bit(STATUS_TPOWER_PMI, &trans->status);
2089         else
2090                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
2091 }
2092
2093 struct iwl_trans_pcie_removal {
2094         struct pci_dev *pdev;
2095         struct work_struct work;
2096         bool rescan;
2097 };
2098
2099 static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
2100 {
2101         struct iwl_trans_pcie_removal *removal =
2102                 container_of(wk, struct iwl_trans_pcie_removal, work);
2103         struct pci_dev *pdev = removal->pdev;
2104         static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
2105         struct pci_bus *bus;
2106
2107         pci_lock_rescan_remove();
2108
2109         bus = pdev->bus;
2110         /* in this case, something else already removed the device */
2111         if (!bus)
2112                 goto out;
2113
2114         dev_err(&pdev->dev, "Device gone - attempting removal\n");
2115
2116         kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
2117
2118         pci_stop_and_remove_bus_device(pdev);
2119         pci_dev_put(pdev);
2120
2121         if (removal->rescan) {
2122                 if (bus->parent)
2123                         bus = bus->parent;
2124                 pci_rescan_bus(bus);
2125         }
2126
2127 out:
2128         pci_unlock_rescan_remove();
2129
2130         kfree(removal);
2131         module_put(THIS_MODULE);
2132 }
2133
2134 void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan)
2135 {
2136         struct iwl_trans_pcie_removal *removal;
2137
2138         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2139                 return;
2140
2141         IWL_ERR(trans, "Device gone - scheduling removal!\n");
2142         iwl_pcie_dump_csr(trans);
2143
2144         /*
2145          * get a module reference to avoid doing this
2146          * while unloading anyway and to avoid
2147          * scheduling a work with code that's being
2148          * removed.
2149          */
2150         if (!try_module_get(THIS_MODULE)) {
2151                 IWL_ERR(trans,
2152                         "Module is being unloaded - abort\n");
2153                 return;
2154         }
2155
2156         removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2157         if (!removal) {
2158                 module_put(THIS_MODULE);
2159                 return;
2160         }
2161         /*
2162          * we don't need to clear this flag, because
2163          * the trans will be freed and reallocated.
2164          */
2165         set_bit(STATUS_TRANS_DEAD, &trans->status);
2166
2167         removal->pdev = to_pci_dev(trans->dev);
2168         removal->rescan = rescan;
2169         INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2170         pci_dev_get(removal->pdev);
2171         schedule_work(&removal->work);
2172 }
2173 EXPORT_SYMBOL(iwl_trans_pcie_remove);
2174
2175 /*
2176  * This version doesn't disable BHs but rather assumes they're
2177  * already disabled.
2178  */
2179 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
2180 {
2181         int ret;
2182         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2183         u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ;
2184         u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
2185                    CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP;
2186         u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN;
2187
2188         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2189                 return false;
2190
2191         spin_lock(&trans_pcie->reg_lock);
2192
2193         if (trans_pcie->cmd_hold_nic_awake)
2194                 goto out;
2195
2196         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
2197                 write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ;
2198                 mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
2199                 poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
2200         }
2201
2202         /* this bit wakes up the NIC */
2203         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write);
2204         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
2205                 udelay(2);
2206
2207         /*
2208          * These bits say the device is running, and should keep running for
2209          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2210          * but they do not indicate that embedded SRAM is restored yet;
2211          * HW with volatile SRAM must save/restore contents to/from
2212          * host DRAM when sleeping/waking for power-saving.
2213          * Each direction takes approximately 1/4 millisecond; with this
2214          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2215          * series of register accesses are expected (e.g. reading Event Log),
2216          * to keep device from sleeping.
2217          *
2218          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2219          * SRAM is okay/restored.  We don't check that here because this call
2220          * is just for hardware register access; but GP1 MAC_SLEEP
2221          * check is a good idea before accessing the SRAM of HW with
2222          * volatile SRAM (e.g. reading Event Log).
2223          *
2224          * 5000 series and later (including 1000 series) have non-volatile SRAM,
2225          * and do not save/restore SRAM when power cycling.
2226          */
2227         ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000);
2228         if (unlikely(ret < 0)) {
2229                 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2230
2231                 WARN_ONCE(1,
2232                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
2233                           cntrl);
2234
2235                 iwl_trans_pcie_dump_regs(trans);
2236
2237                 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U)
2238                         iwl_trans_pcie_remove(trans, false);
2239                 else
2240                         iwl_write32(trans, CSR_RESET,
2241                                     CSR_RESET_REG_FLAG_FORCE_NMI);
2242
2243                 spin_unlock(&trans_pcie->reg_lock);
2244                 return false;
2245         }
2246
2247 out:
2248         /*
2249          * Fool sparse by faking we release the lock - sparse will
2250          * track nic_access anyway.
2251          */
2252         __release(&trans_pcie->reg_lock);
2253         return true;
2254 }
2255
2256 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
2257 {
2258         bool ret;
2259
2260         local_bh_disable();
2261         ret = __iwl_trans_pcie_grab_nic_access(trans);
2262         if (ret) {
2263                 /* keep BHs disabled until iwl_trans_pcie_release_nic_access */
2264                 return ret;
2265         }
2266         local_bh_enable();
2267         return false;
2268 }
2269
2270 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
2271 {
2272         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2273
2274         lockdep_assert_held(&trans_pcie->reg_lock);
2275
2276         /*
2277          * Fool sparse by faking we acquiring the lock - sparse will
2278          * track nic_access anyway.
2279          */
2280         __acquire(&trans_pcie->reg_lock);
2281
2282         if (trans_pcie->cmd_hold_nic_awake)
2283                 goto out;
2284         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
2285                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2286                                            CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
2287         else
2288                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2289                                            CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2290         /*
2291          * Above we read the CSR_GP_CNTRL register, which will flush
2292          * any previous writes, but we need the write that clears the
2293          * MAC_ACCESS_REQ bit to be performed before any other writes
2294          * scheduled on different CPUs (after we drop reg_lock).
2295          */
2296 out:
2297         spin_unlock_bh(&trans_pcie->reg_lock);
2298 }
2299
2300 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2301                                    void *buf, int dwords)
2302 {
2303 #define IWL_MAX_HW_ERRS 5
2304         unsigned int num_consec_hw_errors = 0;
2305         int offs = 0;
2306         u32 *vals = buf;
2307
2308         while (offs < dwords) {
2309                 /* limit the time we spin here under lock to 1/2s */
2310                 unsigned long end = jiffies + HZ / 2;
2311                 bool resched = false;
2312
2313                 if (iwl_trans_grab_nic_access(trans)) {
2314                         iwl_write32(trans, HBUS_TARG_MEM_RADDR,
2315                                     addr + 4 * offs);
2316
2317                         while (offs < dwords) {
2318                                 vals[offs] = iwl_read32(trans,
2319                                                         HBUS_TARG_MEM_RDAT);
2320
2321                                 if (iwl_trans_is_hw_error_value(vals[offs]))
2322                                         num_consec_hw_errors++;
2323                                 else
2324                                         num_consec_hw_errors = 0;
2325
2326                                 if (num_consec_hw_errors >= IWL_MAX_HW_ERRS) {
2327                                         iwl_trans_release_nic_access(trans);
2328                                         return -EIO;
2329                                 }
2330
2331                                 offs++;
2332
2333                                 if (time_after(jiffies, end)) {
2334                                         resched = true;
2335                                         break;
2336                                 }
2337                         }
2338                         iwl_trans_release_nic_access(trans);
2339
2340                         if (resched)
2341                                 cond_resched();
2342                 } else {
2343                         return -EBUSY;
2344                 }
2345         }
2346
2347         return 0;
2348 }
2349
2350 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
2351                                     const void *buf, int dwords)
2352 {
2353         int offs, ret = 0;
2354         const u32 *vals = buf;
2355
2356         if (iwl_trans_grab_nic_access(trans)) {
2357                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2358                 for (offs = 0; offs < dwords; offs++)
2359                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2360                                     vals ? vals[offs] : 0);
2361                 iwl_trans_release_nic_access(trans);
2362         } else {
2363                 ret = -EBUSY;
2364         }
2365         return ret;
2366 }
2367
2368 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
2369                                         u32 *val)
2370 {
2371         return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,
2372                                      ofs, val);
2373 }
2374
2375 #define IWL_FLUSH_WAIT_MS       2000
2376
2377 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2378                                        struct iwl_trans_rxq_dma_data *data)
2379 {
2380         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2381
2382         if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2383                 return -EINVAL;
2384
2385         data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2386         data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2387         data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2388         data->fr_bd_wid = 0;
2389
2390         return 0;
2391 }
2392
2393 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2394 {
2395         struct iwl_txq *txq;
2396         unsigned long now = jiffies;
2397         bool overflow_tx;
2398         u8 wr_ptr;
2399
2400         /* Make sure the NIC is still alive in the bus */
2401         if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2402                 return -ENODEV;
2403
2404         if (!test_bit(txq_idx, trans->txqs.queue_used))
2405                 return -EINVAL;
2406
2407         IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2408         txq = trans->txqs.txq[txq_idx];
2409
2410         spin_lock_bh(&txq->lock);
2411         overflow_tx = txq->overflow_tx ||
2412                       !skb_queue_empty(&txq->overflow_q);
2413         spin_unlock_bh(&txq->lock);
2414
2415         wr_ptr = READ_ONCE(txq->write_ptr);
2416
2417         while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2418                 overflow_tx) &&
2419                !time_after(jiffies,
2420                            now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2421                 u8 write_ptr = READ_ONCE(txq->write_ptr);
2422
2423                 /*
2424                  * If write pointer moved during the wait, warn only
2425                  * if the TX came from op mode. In case TX came from
2426                  * trans layer (overflow TX) don't warn.
2427                  */
2428                 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
2429                               "WR pointer moved while flushing %d -> %d\n",
2430                               wr_ptr, write_ptr))
2431                         return -ETIMEDOUT;
2432                 wr_ptr = write_ptr;
2433
2434                 usleep_range(1000, 2000);
2435
2436                 spin_lock_bh(&txq->lock);
2437                 overflow_tx = txq->overflow_tx ||
2438                               !skb_queue_empty(&txq->overflow_q);
2439                 spin_unlock_bh(&txq->lock);
2440         }
2441
2442         if (txq->read_ptr != txq->write_ptr) {
2443                 IWL_ERR(trans,
2444                         "fail to flush all tx fifo queues Q %d\n", txq_idx);
2445                 iwl_txq_log_scd_error(trans, txq);
2446                 return -ETIMEDOUT;
2447         }
2448
2449         IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2450
2451         return 0;
2452 }
2453
2454 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2455 {
2456         int cnt;
2457         int ret = 0;
2458
2459         /* waiting for all the tx frames complete might take a while */
2460         for (cnt = 0;
2461              cnt < trans->trans_cfg->base_params->num_of_queues;
2462              cnt++) {
2463
2464                 if (cnt == trans->txqs.cmd.q_id)
2465                         continue;
2466                 if (!test_bit(cnt, trans->txqs.queue_used))
2467                         continue;
2468                 if (!(BIT(cnt) & txq_bm))
2469                         continue;
2470
2471                 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2472                 if (ret)
2473                         break;
2474         }
2475
2476         return ret;
2477 }
2478
2479 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2480                                          u32 mask, u32 value)
2481 {
2482         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2483
2484         spin_lock_bh(&trans_pcie->reg_lock);
2485         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2486         spin_unlock_bh(&trans_pcie->reg_lock);
2487 }
2488
2489 static const char *get_csr_string(int cmd)
2490 {
2491 #define IWL_CMD(x) case x: return #x
2492         switch (cmd) {
2493         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2494         IWL_CMD(CSR_INT_COALESCING);
2495         IWL_CMD(CSR_INT);
2496         IWL_CMD(CSR_INT_MASK);
2497         IWL_CMD(CSR_FH_INT_STATUS);
2498         IWL_CMD(CSR_GPIO_IN);
2499         IWL_CMD(CSR_RESET);
2500         IWL_CMD(CSR_GP_CNTRL);
2501         IWL_CMD(CSR_HW_REV);
2502         IWL_CMD(CSR_EEPROM_REG);
2503         IWL_CMD(CSR_EEPROM_GP);
2504         IWL_CMD(CSR_OTP_GP_REG);
2505         IWL_CMD(CSR_GIO_REG);
2506         IWL_CMD(CSR_GP_UCODE_REG);
2507         IWL_CMD(CSR_GP_DRIVER_REG);
2508         IWL_CMD(CSR_UCODE_DRV_GP1);
2509         IWL_CMD(CSR_UCODE_DRV_GP2);
2510         IWL_CMD(CSR_LED_REG);
2511         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2512         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2513         IWL_CMD(CSR_ANA_PLL_CFG);
2514         IWL_CMD(CSR_HW_REV_WA_REG);
2515         IWL_CMD(CSR_MONITOR_STATUS_REG);
2516         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2517         default:
2518                 return "UNKNOWN";
2519         }
2520 #undef IWL_CMD
2521 }
2522
2523 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2524 {
2525         int i;
2526         static const u32 csr_tbl[] = {
2527                 CSR_HW_IF_CONFIG_REG,
2528                 CSR_INT_COALESCING,
2529                 CSR_INT,
2530                 CSR_INT_MASK,
2531                 CSR_FH_INT_STATUS,
2532                 CSR_GPIO_IN,
2533                 CSR_RESET,
2534                 CSR_GP_CNTRL,
2535                 CSR_HW_REV,
2536                 CSR_EEPROM_REG,
2537                 CSR_EEPROM_GP,
2538                 CSR_OTP_GP_REG,
2539                 CSR_GIO_REG,
2540                 CSR_GP_UCODE_REG,
2541                 CSR_GP_DRIVER_REG,
2542                 CSR_UCODE_DRV_GP1,
2543                 CSR_UCODE_DRV_GP2,
2544                 CSR_LED_REG,
2545                 CSR_DRAM_INT_TBL_REG,
2546                 CSR_GIO_CHICKEN_BITS,
2547                 CSR_ANA_PLL_CFG,
2548                 CSR_MONITOR_STATUS_REG,
2549                 CSR_HW_REV_WA_REG,
2550                 CSR_DBG_HPET_MEM_REG
2551         };
2552         IWL_ERR(trans, "CSR values:\n");
2553         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2554                 "CSR_INT_PERIODIC_REG)\n");
2555         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2556                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2557                         get_csr_string(csr_tbl[i]),
2558                         iwl_read32(trans, csr_tbl[i]));
2559         }
2560 }
2561
2562 #ifdef CONFIG_IWLWIFI_DEBUGFS
2563 /* create and remove of files */
2564 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2565         debugfs_create_file(#name, mode, parent, trans,                 \
2566                             &iwl_dbgfs_##name##_ops);                   \
2567 } while (0)
2568
2569 /* file operation */
2570 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2571 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2572         .read = iwl_dbgfs_##name##_read,                                \
2573         .open = simple_open,                                            \
2574         .llseek = generic_file_llseek,                                  \
2575 };
2576
2577 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2578 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2579         .write = iwl_dbgfs_##name##_write,                              \
2580         .open = simple_open,                                            \
2581         .llseek = generic_file_llseek,                                  \
2582 };
2583
2584 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2585 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2586         .write = iwl_dbgfs_##name##_write,                              \
2587         .read = iwl_dbgfs_##name##_read,                                \
2588         .open = simple_open,                                            \
2589         .llseek = generic_file_llseek,                                  \
2590 };
2591
2592 struct iwl_dbgfs_tx_queue_priv {
2593         struct iwl_trans *trans;
2594 };
2595
2596 struct iwl_dbgfs_tx_queue_state {
2597         loff_t pos;
2598 };
2599
2600 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos)
2601 {
2602         struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2603         struct iwl_dbgfs_tx_queue_state *state;
2604
2605         if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2606                 return NULL;
2607
2608         state = kmalloc(sizeof(*state), GFP_KERNEL);
2609         if (!state)
2610                 return NULL;
2611         state->pos = *pos;
2612         return state;
2613 }
2614
2615 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq,
2616                                          void *v, loff_t *pos)
2617 {
2618         struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2619         struct iwl_dbgfs_tx_queue_state *state = v;
2620
2621         *pos = ++state->pos;
2622
2623         if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2624                 return NULL;
2625
2626         return state;
2627 }
2628
2629 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v)
2630 {
2631         kfree(v);
2632 }
2633
2634 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)
2635 {
2636         struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2637         struct iwl_dbgfs_tx_queue_state *state = v;
2638         struct iwl_trans *trans = priv->trans;
2639         struct iwl_txq *txq = trans->txqs.txq[state->pos];
2640
2641         seq_printf(seq, "hwq %.3u: used=%d stopped=%d ",
2642                    (unsigned int)state->pos,
2643                    !!test_bit(state->pos, trans->txqs.queue_used),
2644                    !!test_bit(state->pos, trans->txqs.queue_stopped));
2645         if (txq)
2646                 seq_printf(seq,
2647                            "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",
2648                            txq->read_ptr, txq->write_ptr,
2649                            txq->need_update, txq->frozen,
2650                            txq->n_window, txq->ampdu);
2651         else
2652                 seq_puts(seq, "(unallocated)");
2653
2654         if (state->pos == trans->txqs.cmd.q_id)
2655                 seq_puts(seq, " (HCMD)");
2656         seq_puts(seq, "\n");
2657
2658         return 0;
2659 }
2660
2661 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = {
2662         .start = iwl_dbgfs_tx_queue_seq_start,
2663         .next = iwl_dbgfs_tx_queue_seq_next,
2664         .stop = iwl_dbgfs_tx_queue_seq_stop,
2665         .show = iwl_dbgfs_tx_queue_seq_show,
2666 };
2667
2668 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp)
2669 {
2670         struct iwl_dbgfs_tx_queue_priv *priv;
2671
2672         priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops,
2673                                   sizeof(*priv));
2674
2675         if (!priv)
2676                 return -ENOMEM;
2677
2678         priv->trans = inode->i_private;
2679         return 0;
2680 }
2681
2682 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2683                                        char __user *user_buf,
2684                                        size_t count, loff_t *ppos)
2685 {
2686         struct iwl_trans *trans = file->private_data;
2687         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2688         char *buf;
2689         int pos = 0, i, ret;
2690         size_t bufsz;
2691
2692         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2693
2694         if (!trans_pcie->rxq)
2695                 return -EAGAIN;
2696
2697         buf = kzalloc(bufsz, GFP_KERNEL);
2698         if (!buf)
2699                 return -ENOMEM;
2700
2701         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2702                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2703
2704                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2705                                  i);
2706                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2707                                  rxq->read);
2708                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2709                                  rxq->write);
2710                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2711                                  rxq->write_actual);
2712                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2713                                  rxq->need_update);
2714                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2715                                  rxq->free_count);
2716                 if (rxq->rb_stts) {
2717                         u32 r = iwl_get_closed_rb_stts(trans, rxq);
2718                         pos += scnprintf(buf + pos, bufsz - pos,
2719                                          "\tclosed_rb_num: %u\n", r);
2720                 } else {
2721                         pos += scnprintf(buf + pos, bufsz - pos,
2722                                          "\tclosed_rb_num: Not Allocated\n");
2723                 }
2724         }
2725         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2726         kfree(buf);
2727
2728         return ret;
2729 }
2730
2731 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2732                                         char __user *user_buf,
2733                                         size_t count, loff_t *ppos)
2734 {
2735         struct iwl_trans *trans = file->private_data;
2736         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2737         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2738
2739         int pos = 0;
2740         char *buf;
2741         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2742         ssize_t ret;
2743
2744         buf = kzalloc(bufsz, GFP_KERNEL);
2745         if (!buf)
2746                 return -ENOMEM;
2747
2748         pos += scnprintf(buf + pos, bufsz - pos,
2749                         "Interrupt Statistics Report:\n");
2750
2751         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2752                 isr_stats->hw);
2753         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2754                 isr_stats->sw);
2755         if (isr_stats->sw || isr_stats->hw) {
2756                 pos += scnprintf(buf + pos, bufsz - pos,
2757                         "\tLast Restarting Code:  0x%X\n",
2758                         isr_stats->err_code);
2759         }
2760 #ifdef CONFIG_IWLWIFI_DEBUG
2761         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2762                 isr_stats->sch);
2763         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2764                 isr_stats->alive);
2765 #endif
2766         pos += scnprintf(buf + pos, bufsz - pos,
2767                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2768
2769         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2770                 isr_stats->ctkill);
2771
2772         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2773                 isr_stats->wakeup);
2774
2775         pos += scnprintf(buf + pos, bufsz - pos,
2776                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2777
2778         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2779                 isr_stats->tx);
2780
2781         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2782                 isr_stats->unhandled);
2783
2784         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2785         kfree(buf);
2786         return ret;
2787 }
2788
2789 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2790                                          const char __user *user_buf,
2791                                          size_t count, loff_t *ppos)
2792 {
2793         struct iwl_trans *trans = file->private_data;
2794         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2795         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2796         u32 reset_flag;
2797         int ret;
2798
2799         ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2800         if (ret)
2801                 return ret;
2802         if (reset_flag == 0)
2803                 memset(isr_stats, 0, sizeof(*isr_stats));
2804
2805         return count;
2806 }
2807
2808 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2809                                    const char __user *user_buf,
2810                                    size_t count, loff_t *ppos)
2811 {
2812         struct iwl_trans *trans = file->private_data;
2813
2814         iwl_pcie_dump_csr(trans);
2815
2816         return count;
2817 }
2818
2819 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2820                                      char __user *user_buf,
2821                                      size_t count, loff_t *ppos)
2822 {
2823         struct iwl_trans *trans = file->private_data;
2824         char *buf = NULL;
2825         ssize_t ret;
2826
2827         ret = iwl_dump_fh(trans, &buf);
2828         if (ret < 0)
2829                 return ret;
2830         if (!buf)
2831                 return -EINVAL;
2832         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2833         kfree(buf);
2834         return ret;
2835 }
2836
2837 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2838                                      char __user *user_buf,
2839                                      size_t count, loff_t *ppos)
2840 {
2841         struct iwl_trans *trans = file->private_data;
2842         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2843         char buf[100];
2844         int pos;
2845
2846         pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2847                         trans_pcie->debug_rfkill,
2848                         !(iwl_read32(trans, CSR_GP_CNTRL) &
2849                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2850
2851         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2852 }
2853
2854 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2855                                       const char __user *user_buf,
2856                                       size_t count, loff_t *ppos)
2857 {
2858         struct iwl_trans *trans = file->private_data;
2859         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2860         bool new_value;
2861         int ret;
2862
2863         ret = kstrtobool_from_user(user_buf, count, &new_value);
2864         if (ret)
2865                 return ret;
2866         if (new_value == trans_pcie->debug_rfkill)
2867                 return count;
2868         IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2869                  trans_pcie->debug_rfkill, new_value);
2870         trans_pcie->debug_rfkill = new_value;
2871         iwl_pcie_handle_rfkill_irq(trans, false);
2872
2873         return count;
2874 }
2875
2876 static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2877                                        struct file *file)
2878 {
2879         struct iwl_trans *trans = inode->i_private;
2880         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2881
2882         if (!trans->dbg.dest_tlv ||
2883             trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
2884                 IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2885                 return -ENOENT;
2886         }
2887
2888         if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2889                 return -EBUSY;
2890
2891         trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2892         return simple_open(inode, file);
2893 }
2894
2895 static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2896                                           struct file *file)
2897 {
2898         struct iwl_trans_pcie *trans_pcie =
2899                 IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2900
2901         if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2902                 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2903         return 0;
2904 }
2905
2906 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2907                                   void *buf, ssize_t *size,
2908                                   ssize_t *bytes_copied)
2909 {
2910         ssize_t buf_size_left = count - *bytes_copied;
2911
2912         buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2913         if (*size > buf_size_left)
2914                 *size = buf_size_left;
2915
2916         *size -= copy_to_user(user_buf, buf, *size);
2917         *bytes_copied += *size;
2918
2919         if (buf_size_left == *size)
2920                 return true;
2921         return false;
2922 }
2923
2924 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2925                                            char __user *user_buf,
2926                                            size_t count, loff_t *ppos)
2927 {
2928         struct iwl_trans *trans = file->private_data;
2929         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2930         u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
2931         struct cont_rec *data = &trans_pcie->fw_mon_data;
2932         u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2933         ssize_t size, bytes_copied = 0;
2934         bool b_full;
2935
2936         if (trans->dbg.dest_tlv) {
2937                 write_ptr_addr =
2938                         le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
2939                 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
2940         } else {
2941                 write_ptr_addr = MON_BUFF_WRPTR;
2942                 wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2943         }
2944
2945         if (unlikely(!trans->dbg.rec_on))
2946                 return 0;
2947
2948         mutex_lock(&data->mutex);
2949         if (data->state ==
2950             IWL_FW_MON_DBGFS_STATE_DISABLED) {
2951                 mutex_unlock(&data->mutex);
2952                 return 0;
2953         }
2954
2955         /* write_ptr position in bytes rather then DW */
2956         write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2957         wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2958
2959         if (data->prev_wrap_cnt == wrap_cnt) {
2960                 size = write_ptr - data->prev_wr_ptr;
2961                 curr_buf = cpu_addr + data->prev_wr_ptr;
2962                 b_full = iwl_write_to_user_buf(user_buf, count,
2963                                                curr_buf, &size,
2964                                                &bytes_copied);
2965                 data->prev_wr_ptr += size;
2966
2967         } else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2968                    write_ptr < data->prev_wr_ptr) {
2969                 size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
2970                 curr_buf = cpu_addr + data->prev_wr_ptr;
2971                 b_full = iwl_write_to_user_buf(user_buf, count,
2972                                                curr_buf, &size,
2973                                                &bytes_copied);
2974                 data->prev_wr_ptr += size;
2975
2976                 if (!b_full) {
2977                         size = write_ptr;
2978                         b_full = iwl_write_to_user_buf(user_buf, count,
2979                                                        cpu_addr, &size,
2980                                                        &bytes_copied);
2981                         data->prev_wr_ptr = size;
2982                         data->prev_wrap_cnt++;
2983                 }
2984         } else {
2985                 if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2986                     write_ptr > data->prev_wr_ptr)
2987                         IWL_WARN(trans,
2988                                  "write pointer passed previous write pointer, start copying from the beginning\n");
2989                 else if (!unlikely(data->prev_wrap_cnt == 0 &&
2990                                    data->prev_wr_ptr == 0))
2991                         IWL_WARN(trans,
2992                                  "monitor data is out of sync, start copying from the beginning\n");
2993
2994                 size = write_ptr;
2995                 b_full = iwl_write_to_user_buf(user_buf, count,
2996                                                cpu_addr, &size,
2997                                                &bytes_copied);
2998                 data->prev_wr_ptr = size;
2999                 data->prev_wrap_cnt = wrap_cnt;
3000         }
3001
3002         mutex_unlock(&data->mutex);
3003
3004         return bytes_copied;
3005 }
3006
3007 static ssize_t iwl_dbgfs_rf_read(struct file *file,
3008                                  char __user *user_buf,
3009                                  size_t count, loff_t *ppos)
3010 {
3011         struct iwl_trans *trans = file->private_data;
3012         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3013
3014         if (!trans_pcie->rf_name[0])
3015                 return -ENODEV;
3016
3017         return simple_read_from_buffer(user_buf, count, ppos,
3018                                        trans_pcie->rf_name,
3019                                        strlen(trans_pcie->rf_name));
3020 }
3021
3022 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
3023 DEBUGFS_READ_FILE_OPS(fh_reg);
3024 DEBUGFS_READ_FILE_OPS(rx_queue);
3025 DEBUGFS_WRITE_FILE_OPS(csr);
3026 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
3027 DEBUGFS_READ_FILE_OPS(rf);
3028
3029 static const struct file_operations iwl_dbgfs_tx_queue_ops = {
3030         .owner = THIS_MODULE,
3031         .open = iwl_dbgfs_tx_queue_open,
3032         .read = seq_read,
3033         .llseek = seq_lseek,
3034         .release = seq_release_private,
3035 };
3036
3037 static const struct file_operations iwl_dbgfs_monitor_data_ops = {
3038         .read = iwl_dbgfs_monitor_data_read,
3039         .open = iwl_dbgfs_monitor_data_open,
3040         .release = iwl_dbgfs_monitor_data_release,
3041 };
3042
3043 /* Create the debugfs files and directories */
3044 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
3045 {
3046         struct dentry *dir = trans->dbgfs_dir;
3047
3048         DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
3049         DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
3050         DEBUGFS_ADD_FILE(interrupt, dir, 0600);
3051         DEBUGFS_ADD_FILE(csr, dir, 0200);
3052         DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
3053         DEBUGFS_ADD_FILE(rfkill, dir, 0600);
3054         DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
3055         DEBUGFS_ADD_FILE(rf, dir, 0400);
3056 }
3057
3058 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
3059 {
3060         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3061         struct cont_rec *data = &trans_pcie->fw_mon_data;
3062
3063         mutex_lock(&data->mutex);
3064         data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
3065         mutex_unlock(&data->mutex);
3066 }
3067 #endif /*CONFIG_IWLWIFI_DEBUGFS */
3068
3069 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
3070 {
3071         u32 cmdlen = 0;
3072         int i;
3073
3074         for (i = 0; i < trans->txqs.tfd.max_tbs; i++)
3075                 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i);
3076
3077         return cmdlen;
3078 }
3079
3080 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
3081                                    struct iwl_fw_error_dump_data **data,
3082                                    int allocated_rb_nums)
3083 {
3084         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3085         int max_len = trans_pcie->rx_buf_bytes;
3086         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3087         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3088         u32 i, r, j, rb_len = 0;
3089
3090         spin_lock_bh(&rxq->lock);
3091
3092         r = iwl_get_closed_rb_stts(trans, rxq);
3093
3094         for (i = rxq->read, j = 0;
3095              i != r && j < allocated_rb_nums;
3096              i = (i + 1) & RX_QUEUE_MASK, j++) {
3097                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
3098                 struct iwl_fw_error_dump_rb *rb;
3099
3100                 dma_sync_single_for_cpu(trans->dev, rxb->page_dma,
3101                                         max_len, DMA_FROM_DEVICE);
3102
3103                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
3104
3105                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
3106                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
3107                 rb = (void *)(*data)->data;
3108                 rb->index = cpu_to_le32(i);
3109                 memcpy(rb->data, page_address(rxb->page), max_len);
3110
3111                 *data = iwl_fw_error_next_data(*data);
3112         }
3113
3114         spin_unlock_bh(&rxq->lock);
3115
3116         return rb_len;
3117 }
3118 #define IWL_CSR_TO_DUMP (0x250)
3119
3120 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
3121                                    struct iwl_fw_error_dump_data **data)
3122 {
3123         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
3124         __le32 *val;
3125         int i;
3126
3127         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
3128         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
3129         val = (void *)(*data)->data;
3130
3131         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
3132                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3133
3134         *data = iwl_fw_error_next_data(*data);
3135
3136         return csr_len;
3137 }
3138
3139 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
3140                                        struct iwl_fw_error_dump_data **data)
3141 {
3142         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
3143         __le32 *val;
3144         int i;
3145
3146         if (!iwl_trans_grab_nic_access(trans))
3147                 return 0;
3148
3149         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
3150         (*data)->len = cpu_to_le32(fh_regs_len);
3151         val = (void *)(*data)->data;
3152
3153         if (!trans->trans_cfg->gen2)
3154                 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
3155                      i += sizeof(u32))
3156                         *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3157         else
3158                 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3159                      i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
3160                      i += sizeof(u32))
3161                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3162                                                                       i));
3163
3164         iwl_trans_release_nic_access(trans);
3165
3166         *data = iwl_fw_error_next_data(*data);
3167
3168         return sizeof(**data) + fh_regs_len;
3169 }
3170
3171 static u32
3172 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3173                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3174                                  u32 monitor_len)
3175 {
3176         u32 buf_size_in_dwords = (monitor_len >> 2);
3177         u32 *buffer = (u32 *)fw_mon_data->data;
3178         u32 i;
3179
3180         if (!iwl_trans_grab_nic_access(trans))
3181                 return 0;
3182
3183         iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
3184         for (i = 0; i < buf_size_in_dwords; i++)
3185                 buffer[i] = iwl_read_umac_prph_no_grab(trans,
3186                                                        MON_DMARB_RD_DATA_ADDR);
3187         iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
3188
3189         iwl_trans_release_nic_access(trans);
3190
3191         return monitor_len;
3192 }
3193
3194 static void
3195 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3196                              struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3197 {
3198         u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
3199
3200         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3201                 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3202                 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3203                 write_ptr = DBGC_CUR_DBGBUF_STATUS;
3204                 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
3205         } else if (trans->dbg.dest_tlv) {
3206                 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3207                 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3208                 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3209         } else {
3210                 base = MON_BUFF_BASE_ADDR;
3211                 write_ptr = MON_BUFF_WRPTR;
3212                 wrap_cnt = MON_BUFF_CYCLE_CNT;
3213         }
3214
3215         write_ptr_val = iwl_read_prph(trans, write_ptr);
3216         fw_mon_data->fw_mon_cycle_cnt =
3217                 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3218         fw_mon_data->fw_mon_base_ptr =
3219                 cpu_to_le32(iwl_read_prph(trans, base));
3220         if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3221                 fw_mon_data->fw_mon_base_high_ptr =
3222                         cpu_to_le32(iwl_read_prph(trans, base_high));
3223                 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
3224                 /* convert wrtPtr to DWs, to align with all HWs */
3225                 write_ptr_val >>= 2;
3226         }
3227         fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
3228 }
3229
3230 static u32
3231 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3232                             struct iwl_fw_error_dump_data **data,
3233                             u32 monitor_len)
3234 {
3235         struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
3236         u32 len = 0;
3237
3238         if (trans->dbg.dest_tlv ||
3239             (fw_mon->size &&
3240              (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3241               trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
3242                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
3243
3244                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3245                 fw_mon_data = (void *)(*data)->data;
3246
3247                 iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
3248
3249                 len += sizeof(**data) + sizeof(*fw_mon_data);
3250                 if (fw_mon->size) {
3251                         memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
3252                         monitor_len = fw_mon->size;
3253                 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
3254                         u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
3255                         /*
3256                          * Update pointers to reflect actual values after
3257                          * shifting
3258                          */
3259                         if (trans->dbg.dest_tlv->version) {
3260                                 base = (iwl_read_prph(trans, base) &
3261                                         IWL_LDBG_M2S_BUF_BA_MSK) <<
3262                                        trans->dbg.dest_tlv->base_shift;
3263                                 base *= IWL_M2S_UNIT_SIZE;
3264                                 base += trans->cfg->smem_offset;
3265                         } else {
3266                                 base = iwl_read_prph(trans, base) <<
3267                                        trans->dbg.dest_tlv->base_shift;
3268                         }
3269
3270                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
3271                                            monitor_len / sizeof(u32));
3272                 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
3273                         monitor_len =
3274                                 iwl_trans_pci_dump_marbh_monitor(trans,
3275                                                                  fw_mon_data,
3276                                                                  monitor_len);
3277                 } else {
3278                         /* Didn't match anything - output no monitor data */
3279                         monitor_len = 0;
3280                 }
3281
3282                 len += monitor_len;
3283                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3284         }
3285
3286         return len;
3287 }
3288
3289 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
3290 {
3291         if (trans->dbg.fw_mon.size) {
3292                 *len += sizeof(struct iwl_fw_error_dump_data) +
3293                         sizeof(struct iwl_fw_error_dump_fw_mon) +
3294                         trans->dbg.fw_mon.size;
3295                 return trans->dbg.fw_mon.size;
3296         } else if (trans->dbg.dest_tlv) {
3297                 u32 base, end, cfg_reg, monitor_len;
3298
3299                 if (trans->dbg.dest_tlv->version == 1) {
3300                         cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3301                         cfg_reg = iwl_read_prph(trans, cfg_reg);
3302                         base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
3303                                 trans->dbg.dest_tlv->base_shift;
3304                         base *= IWL_M2S_UNIT_SIZE;
3305                         base += trans->cfg->smem_offset;
3306
3307                         monitor_len =
3308                                 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
3309                                 trans->dbg.dest_tlv->end_shift;
3310                         monitor_len *= IWL_M2S_UNIT_SIZE;
3311                 } else {
3312                         base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3313                         end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
3314
3315                         base = iwl_read_prph(trans, base) <<
3316                                trans->dbg.dest_tlv->base_shift;
3317                         end = iwl_read_prph(trans, end) <<
3318                               trans->dbg.dest_tlv->end_shift;
3319
3320                         /* Make "end" point to the actual end */
3321                         if (trans->trans_cfg->device_family >=
3322                             IWL_DEVICE_FAMILY_8000 ||
3323                             trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3324                                 end += (1 << trans->dbg.dest_tlv->end_shift);
3325                         monitor_len = end - base;
3326                 }
3327                 *len += sizeof(struct iwl_fw_error_dump_data) +
3328                         sizeof(struct iwl_fw_error_dump_fw_mon) +
3329                         monitor_len;
3330                 return monitor_len;
3331         }
3332         return 0;
3333 }
3334
3335 static struct iwl_trans_dump_data *
3336 iwl_trans_pcie_dump_data(struct iwl_trans *trans,
3337                          u32 dump_mask,
3338                          const struct iwl_dump_sanitize_ops *sanitize_ops,
3339                          void *sanitize_ctx)
3340 {
3341         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3342         struct iwl_fw_error_dump_data *data;
3343         struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id];
3344         struct iwl_fw_error_dump_txcmd *txcmd;
3345         struct iwl_trans_dump_data *dump_data;
3346         u32 len, num_rbs = 0, monitor_len = 0;
3347         int i, ptr;
3348         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
3349                         !trans->trans_cfg->mq_rx_supported &&
3350                         dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3351
3352         if (!dump_mask)
3353                 return NULL;
3354
3355         /* transport dump header */
3356         len = sizeof(*dump_data);
3357
3358         /* host commands */
3359         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
3360                 len += sizeof(*data) +
3361                         cmdq->n_window * (sizeof(*txcmd) +
3362                                           TFD_MAX_PAYLOAD_SIZE);
3363
3364         /* FW monitor */
3365         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3366                 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
3367
3368         /* CSR registers */
3369         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3370                 len += sizeof(*data) + IWL_CSR_TO_DUMP;
3371
3372         /* FH registers */
3373         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
3374                 if (trans->trans_cfg->gen2)
3375                         len += sizeof(*data) +
3376                                (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3377                                 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
3378                 else
3379                         len += sizeof(*data) +
3380                                (FH_MEM_UPPER_BOUND -
3381                                 FH_MEM_LOWER_BOUND);
3382         }
3383
3384         if (dump_rbs) {
3385                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3386                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3387                 /* RBs */
3388                 num_rbs = iwl_get_closed_rb_stts(trans, rxq);
3389                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
3390                 len += num_rbs * (sizeof(*data) +
3391                                   sizeof(struct iwl_fw_error_dump_rb) +
3392                                   (PAGE_SIZE << trans_pcie->rx_page_order));
3393         }
3394
3395         /* Paged memory for gen2 HW */
3396         if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
3397                 for (i = 0; i < trans->init_dram.paging_cnt; i++)
3398                         len += sizeof(*data) +
3399                                sizeof(struct iwl_fw_error_dump_paging) +
3400                                trans->init_dram.paging[i].size;
3401
3402         dump_data = vzalloc(len);
3403         if (!dump_data)
3404                 return NULL;
3405
3406         len = 0;
3407         data = (void *)dump_data->data;
3408
3409         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
3410                 u16 tfd_size = trans->txqs.tfd.size;
3411
3412                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3413                 txcmd = (void *)data->data;
3414                 spin_lock_bh(&cmdq->lock);
3415                 ptr = cmdq->write_ptr;
3416                 for (i = 0; i < cmdq->n_window; i++) {
3417                         u8 idx = iwl_txq_get_cmd_index(cmdq, ptr);
3418                         u8 tfdidx;
3419                         u32 caplen, cmdlen;
3420
3421                         if (trans->trans_cfg->gen2)
3422                                 tfdidx = idx;
3423                         else
3424                                 tfdidx = ptr;
3425
3426                         cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3427                                                            (u8 *)cmdq->tfds +
3428                                                            tfd_size * tfdidx);
3429                         caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3430
3431                         if (cmdlen) {
3432                                 len += sizeof(*txcmd) + caplen;
3433                                 txcmd->cmdlen = cpu_to_le32(cmdlen);
3434                                 txcmd->caplen = cpu_to_le32(caplen);
3435                                 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3436                                        caplen);
3437                                 if (sanitize_ops && sanitize_ops->frob_hcmd)
3438                                         sanitize_ops->frob_hcmd(sanitize_ctx,
3439                                                                 txcmd->data,
3440                                                                 caplen);
3441                                 txcmd = (void *)((u8 *)txcmd->data + caplen);
3442                         }
3443
3444                         ptr = iwl_txq_dec_wrap(trans, ptr);
3445                 }
3446                 spin_unlock_bh(&cmdq->lock);
3447
3448                 data->len = cpu_to_le32(len);
3449                 len += sizeof(*data);
3450                 data = iwl_fw_error_next_data(data);
3451         }
3452
3453         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3454                 len += iwl_trans_pcie_dump_csr(trans, &data);
3455         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
3456                 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
3457         if (dump_rbs)
3458                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
3459
3460         /* Paged memory for gen2 HW */
3461         if (trans->trans_cfg->gen2 &&
3462             dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
3463                 for (i = 0; i < trans->init_dram.paging_cnt; i++) {
3464                         struct iwl_fw_error_dump_paging *paging;
3465                         u32 page_len = trans->init_dram.paging[i].size;
3466
3467                         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3468                         data->len = cpu_to_le32(sizeof(*paging) + page_len);
3469                         paging = (void *)data->data;
3470                         paging->index = cpu_to_le32(i);
3471                         memcpy(paging->data,
3472                                trans->init_dram.paging[i].block, page_len);
3473                         data = iwl_fw_error_next_data(data);
3474
3475                         len += sizeof(*data) + sizeof(*paging) + page_len;
3476                 }
3477         }
3478         if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3479                 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3480
3481         dump_data->len = len;
3482
3483         return dump_data;
3484 }
3485
3486 static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable)
3487 {
3488         if (enable)
3489                 iwl_enable_interrupts(trans);
3490         else
3491                 iwl_disable_interrupts(trans);
3492 }
3493
3494 static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
3495 {
3496         u32 inta_addr, sw_err_bit;
3497         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3498
3499         if (trans_pcie->msix_enabled) {
3500                 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
3501                 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
3502                         sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ;
3503                 else
3504                         sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
3505         } else {
3506                 inta_addr = CSR_INT;
3507                 sw_err_bit = CSR_INT_BIT_SW_ERR;
3508         }
3509
3510         iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit);
3511 }
3512
3513 #define IWL_TRANS_COMMON_OPS                                            \
3514         .op_mode_leave = iwl_trans_pcie_op_mode_leave,                  \
3515         .write8 = iwl_trans_pcie_write8,                                \
3516         .write32 = iwl_trans_pcie_write32,                              \
3517         .read32 = iwl_trans_pcie_read32,                                \
3518         .read_prph = iwl_trans_pcie_read_prph,                          \
3519         .write_prph = iwl_trans_pcie_write_prph,                        \
3520         .read_mem = iwl_trans_pcie_read_mem,                            \
3521         .write_mem = iwl_trans_pcie_write_mem,                          \
3522         .read_config32 = iwl_trans_pcie_read_config32,                  \
3523         .configure = iwl_trans_pcie_configure,                          \
3524         .set_pmi = iwl_trans_pcie_set_pmi,                              \
3525         .sw_reset = iwl_trans_pcie_sw_reset,                            \
3526         .grab_nic_access = iwl_trans_pcie_grab_nic_access,              \
3527         .release_nic_access = iwl_trans_pcie_release_nic_access,        \
3528         .set_bits_mask = iwl_trans_pcie_set_bits_mask,                  \
3529         .dump_data = iwl_trans_pcie_dump_data,                          \
3530         .d3_suspend = iwl_trans_pcie_d3_suspend,                        \
3531         .d3_resume = iwl_trans_pcie_d3_resume,                          \
3532         .interrupts = iwl_trans_pci_interrupts,                         \
3533         .sync_nmi = iwl_trans_pcie_sync_nmi,                            \
3534         .imr_dma_data = iwl_trans_pcie_copy_imr                         \
3535
3536 static const struct iwl_trans_ops trans_ops_pcie = {
3537         IWL_TRANS_COMMON_OPS,
3538         .start_hw = iwl_trans_pcie_start_hw,
3539         .fw_alive = iwl_trans_pcie_fw_alive,
3540         .start_fw = iwl_trans_pcie_start_fw,
3541         .stop_device = iwl_trans_pcie_stop_device,
3542
3543         .send_cmd = iwl_pcie_enqueue_hcmd,
3544
3545         .tx = iwl_trans_pcie_tx,
3546         .reclaim = iwl_txq_reclaim,
3547
3548         .txq_disable = iwl_trans_pcie_txq_disable,
3549         .txq_enable = iwl_trans_pcie_txq_enable,
3550
3551         .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3552
3553         .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3554
3555         .freeze_txq_timer = iwl_trans_txq_freeze_timer,
3556 #ifdef CONFIG_IWLWIFI_DEBUGFS
3557         .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3558 #endif
3559 };
3560
3561 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3562         IWL_TRANS_COMMON_OPS,
3563         .start_hw = iwl_trans_pcie_start_hw,
3564         .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3565         .start_fw = iwl_trans_pcie_gen2_start_fw,
3566         .stop_device = iwl_trans_pcie_gen2_stop_device,
3567
3568         .send_cmd = iwl_pcie_gen2_enqueue_hcmd,
3569
3570         .tx = iwl_txq_gen2_tx,
3571         .reclaim = iwl_txq_reclaim,
3572
3573         .set_q_ptrs = iwl_txq_set_q_ptrs,
3574
3575         .txq_alloc = iwl_txq_dyn_alloc,
3576         .txq_free = iwl_txq_dyn_free,
3577         .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3578         .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
3579         .load_pnvm = iwl_trans_pcie_ctx_info_gen3_load_pnvm,
3580         .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm,
3581         .load_reduce_power = iwl_trans_pcie_ctx_info_gen3_load_reduce_power,
3582         .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power,
3583 #ifdef CONFIG_IWLWIFI_DEBUGFS
3584         .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3585 #endif
3586 };
3587
3588 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3589                                const struct pci_device_id *ent,
3590                                const struct iwl_cfg_trans_params *cfg_trans)
3591 {
3592         struct iwl_trans_pcie *trans_pcie, **priv;
3593         struct iwl_trans *trans;
3594         int ret, addr_size;
3595         const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2;
3596         void __iomem * const *table;
3597         u32 bar0;
3598
3599         if (!cfg_trans->gen2)
3600                 ops = &trans_ops_pcie;
3601
3602         /* reassign our BAR 0 if invalid due to possible runtime PM races */
3603         pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &bar0);
3604         if (bar0 == PCI_BASE_ADDRESS_MEM_TYPE_64) {
3605                 ret = pci_assign_resource(pdev, 0);
3606                 if (ret)
3607                         return ERR_PTR(ret);
3608         }
3609
3610         ret = pcim_enable_device(pdev);
3611         if (ret)
3612                 return ERR_PTR(ret);
3613
3614         trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops,
3615                                 cfg_trans);
3616         if (!trans)
3617                 return ERR_PTR(-ENOMEM);
3618
3619         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3620
3621         /* Initialize NAPI here - it should be before registering to mac80211
3622          * in the opmode but after the HW struct is allocated.
3623          */
3624         trans_pcie->napi_dev = alloc_netdev_dummy(sizeof(struct iwl_trans_pcie *));
3625         if (!trans_pcie->napi_dev) {
3626                 ret = -ENOMEM;
3627                 goto out_free_trans;
3628         }
3629         /* The private struct in netdev is a pointer to struct iwl_trans_pcie */
3630         priv = netdev_priv(trans_pcie->napi_dev);
3631         *priv = trans_pcie;
3632
3633         trans_pcie->trans = trans;
3634         trans_pcie->opmode_down = true;
3635         spin_lock_init(&trans_pcie->irq_lock);
3636         spin_lock_init(&trans_pcie->reg_lock);
3637         spin_lock_init(&trans_pcie->alloc_page_lock);
3638         mutex_init(&trans_pcie->mutex);
3639         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3640         init_waitqueue_head(&trans_pcie->fw_reset_waitq);
3641         init_waitqueue_head(&trans_pcie->imr_waitq);
3642
3643         trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3644                                                    WQ_HIGHPRI | WQ_UNBOUND, 0);
3645         if (!trans_pcie->rba.alloc_wq) {
3646                 ret = -ENOMEM;
3647                 goto out_free_ndev;
3648         }
3649         INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3650
3651         trans_pcie->debug_rfkill = -1;
3652
3653         if (!cfg_trans->base_params->pcie_l1_allowed) {
3654                 /*
3655                  * W/A - seems to solve weird behavior. We need to remove this
3656                  * if we don't want to stay in L1 all the time. This wastes a
3657                  * lot of power.
3658                  */
3659                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3660                                        PCIE_LINK_STATE_L1 |
3661                                        PCIE_LINK_STATE_CLKPM);
3662         }
3663
3664         pci_set_master(pdev);
3665
3666         addr_size = trans->txqs.tfd.addr_size;
3667         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size));
3668         if (ret) {
3669                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3670                 /* both attempts failed: */
3671                 if (ret) {
3672                         dev_err(&pdev->dev, "No suitable DMA available\n");
3673                         goto out_no_pci;
3674                 }
3675         }
3676
3677         ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3678         if (ret) {
3679                 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3680                 goto out_no_pci;
3681         }
3682
3683         table = pcim_iomap_table(pdev);
3684         if (!table) {
3685                 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3686                 ret = -ENOMEM;
3687                 goto out_no_pci;
3688         }
3689
3690         trans_pcie->hw_base = table[0];
3691         if (!trans_pcie->hw_base) {
3692                 dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n");
3693                 ret = -ENODEV;
3694                 goto out_no_pci;
3695         }
3696
3697         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3698          * PCI Tx retries from interfering with C3 CPU state */
3699         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3700
3701         trans_pcie->pci_dev = pdev;
3702         iwl_disable_interrupts(trans);
3703
3704         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3705         if (trans->hw_rev == 0xffffffff) {
3706                 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3707                 ret = -EIO;
3708                 goto out_no_pci;
3709         }
3710
3711         /*
3712          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3713          * changed, and now the revision step also includes bit 0-1 (no more
3714          * "dash" value). To keep hw_rev backwards compatible - we'll store it
3715          * in the old format.
3716          */
3717         if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000)
3718                 trans->hw_rev_step = trans->hw_rev & 0xF;
3719         else
3720                 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2;
3721
3722         IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3723
3724         iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
3725         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3726         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3727                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3728
3729         init_waitqueue_head(&trans_pcie->sx_waitq);
3730
3731         ret = iwl_pcie_alloc_invalid_tx_cmd(trans);
3732         if (ret)
3733                 goto out_no_pci;
3734
3735         if (trans_pcie->msix_enabled) {
3736                 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3737                 if (ret)
3738                         goto out_no_pci;
3739          } else {
3740                 ret = iwl_pcie_alloc_ict(trans);
3741                 if (ret)
3742                         goto out_no_pci;
3743
3744                 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3745                                                 iwl_pcie_isr,
3746                                                 iwl_pcie_irq_handler,
3747                                                 IRQF_SHARED, DRV_NAME, trans);
3748                 if (ret) {
3749                         IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3750                         goto out_free_ict;
3751                 }
3752          }
3753
3754 #ifdef CONFIG_IWLWIFI_DEBUGFS
3755         trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3756         mutex_init(&trans_pcie->fw_mon_data.mutex);
3757 #endif
3758
3759         iwl_dbg_tlv_init(trans);
3760
3761         return trans;
3762
3763 out_free_ict:
3764         iwl_pcie_free_ict(trans);
3765 out_no_pci:
3766         destroy_workqueue(trans_pcie->rba.alloc_wq);
3767 out_free_ndev:
3768         free_netdev(trans_pcie->napi_dev);
3769 out_free_trans:
3770         iwl_trans_free(trans);
3771         return ERR_PTR(ret);
3772 }
3773
3774 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,
3775                                 u32 dst_addr, u64 src_addr, u32 byte_cnt)
3776 {
3777         iwl_write_prph(trans, IMR_UREG_CHICK,
3778                        iwl_read_prph(trans, IMR_UREG_CHICK) |
3779                        IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK);
3780         iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr);
3781         iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB,
3782                        (u32)(src_addr & 0xFFFFFFFF));
3783         iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB,
3784                        iwl_get_dma_hi_addr(src_addr));
3785         iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt);
3786         iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL,
3787                        IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS |
3788                        IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS |
3789                        IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK);
3790 }
3791
3792 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
3793                             u32 dst_addr, u64 src_addr, u32 byte_cnt)
3794 {
3795         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3796         int ret = -1;
3797
3798         trans_pcie->imr_status = IMR_D2S_REQUESTED;
3799         iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt);
3800         ret = wait_event_timeout(trans_pcie->imr_waitq,
3801                                  trans_pcie->imr_status !=
3802                                  IMR_D2S_REQUESTED, 5 * HZ);
3803         if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) {
3804                 IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n");
3805                 iwl_trans_pcie_dump_regs(trans);
3806                 return -ETIMEDOUT;
3807         }
3808         trans_pcie->imr_status = IMR_D2S_IDLE;
3809         return 0;
3810 }