drivers/net/phy/dp83869.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Driver for the Texas Instruments DP83869 PHY
   3  * Copyright (C) 2019 Texas Instruments Inc.
   4  */
   5
   6 #include <linux/ethtool.h>
   7 #include <linux/kernel.h>
   8 #include <linux/mii.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/phy.h>
  12 #include <linux/delay.h>
  13
  14 #include <dt-bindings/net/ti-dp83869.h>
  15
  16 #define DP83869_PHY_ID          0x2000a0f1
  17 #define DP83869_DEVADDR         0x1f
  18
  19 #define MII_DP83869_PHYCTRL     0x10
  20 #define MII_DP83869_MICR        0x12
  21 #define MII_DP83869_ISR         0x13
  22 #define DP83869_CTRL            0x1f
  23 #define DP83869_CFG4            0x1e
  24
  25 /* Extended Registers */
  26 #define DP83869_GEN_CFG3        0x0031
  27 #define DP83869_RGMIICTL        0x0032
  28 #define DP83869_STRAP_STS1      0x006e
  29 #define DP83869_RGMIIDCTL       0x0086
  30 #define DP83869_IO_MUX_CFG      0x0170
  31 #define DP83869_OP_MODE         0x01df
  32 #define DP83869_FX_CTRL         0x0c00
  33
  34 #define DP83869_SW_RESET        BIT(15)
  35 #define DP83869_SW_RESTART      BIT(14)
  36
  37 /* MICR Interrupt bits */
  38 #define MII_DP83869_MICR_AN_ERR_INT_EN          BIT(15)
  39 #define MII_DP83869_MICR_SPEED_CHNG_INT_EN      BIT(14)
  40 #define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  41 #define MII_DP83869_MICR_PAGE_RXD_INT_EN        BIT(12)
  42 #define MII_DP83869_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  43 #define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  44 #define MII_DP83869_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  45 #define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  46 #define MII_DP83869_MICR_WOL_INT_EN             BIT(3)
  47 #define MII_DP83869_MICR_XGMII_ERR_INT_EN       BIT(2)
  48 #define MII_DP83869_MICR_POL_CHNG_INT_EN        BIT(1)
  49 #define MII_DP83869_MICR_JABBER_INT_EN          BIT(0)
  50
  51 #define MII_DP83869_BMCR_DEFAULT        (BMCR_ANENABLE | \
  52                                          BMCR_FULLDPLX | \
  53                                          BMCR_SPEED1000)
  54
  55 /* This is the same bit mask as the BMCR so re-use the BMCR default */
  56 #define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT
  57
  58 /* CFG1 bits */
  59 #define DP83869_CFG1_DEFAULT    (ADVERTISE_1000HALF | \
  60                                  ADVERTISE_1000FULL | \
  61                                  CTL1000_AS_MASTER)
  62
  63 /* RGMIICTL bits */
  64 #define DP83869_RGMII_TX_CLK_DELAY_EN           BIT(1)
  65 #define DP83869_RGMII_RX_CLK_DELAY_EN           BIT(0)
  66
  67 /* STRAP_STS1 bits */
  68 #define DP83869_STRAP_STS1_RESERVED             BIT(11)
  69
  70 /* PHYCTRL bits */
  71 #define DP83869_RX_FIFO_SHIFT   12
  72 #define DP83869_TX_FIFO_SHIFT   14
  73
  74 /* PHY_CTRL lower bytes 0x48 are declared as reserved */
  75 #define DP83869_PHY_CTRL_DEFAULT        0x48
  76 #define DP83869_PHYCR_FIFO_DEPTH_MASK   GENMASK(15, 12)
  77 #define DP83869_PHYCR_RESERVED_MASK     BIT(11)
  78
  79 /* RGMIIDCTL bits */
  80 #define DP83869_RGMII_TX_CLK_DELAY_SHIFT        4
  81
  82 /* IO_MUX_CFG bits */
  83 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
  84
  85 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  86 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
  87 #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK       (0x1f << 8)
  88 #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
  89
  90 /* CFG3 bits */
  91 #define DP83869_CFG3_PORT_MIRROR_EN              BIT(0)
  92
  93 /* CFG4 bits */
  94 #define DP83869_INT_OE  BIT(7)
  95
  96 /* OP MODE */
  97 #define DP83869_OP_MODE_MII                     BIT(5)
  98 #define DP83869_SGMII_RGMII_BRIDGE              BIT(6)
  99
 100 enum {
 101         DP83869_PORT_MIRRORING_KEEP,
 102         DP83869_PORT_MIRRORING_EN,
 103         DP83869_PORT_MIRRORING_DIS,
 104 };
 105
 106 struct dp83869_private {
 107         int tx_fifo_depth;
 108         int rx_fifo_depth;
 109         int io_impedance;
 110         int port_mirroring;
 111         bool rxctrl_strap_quirk;
 112         int clk_output_sel;
 113         int mode;
 114 };
 115
 116 static int dp83869_ack_interrupt(struct phy_device *phydev)
 117 {
 118         int err = phy_read(phydev, MII_DP83869_ISR);
 119
 120         if (err < 0)
 121                 return err;
 122
 123         return 0;
 124 }
 125
 126 static int dp83869_config_intr(struct phy_device *phydev)
 127 {
 128         int micr_status = 0;
 129
 130         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 131                 micr_status = phy_read(phydev, MII_DP83869_MICR);
 132                 if (micr_status < 0)
 133                         return micr_status;
 134
 135                 micr_status |=
 136                         (MII_DP83869_MICR_AN_ERR_INT_EN |
 137                         MII_DP83869_MICR_SPEED_CHNG_INT_EN |
 138                         MII_DP83869_MICR_AUTONEG_COMP_INT_EN |
 139                         MII_DP83869_MICR_LINK_STS_CHNG_INT_EN |
 140                         MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN |
 141                         MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN);
 142
 143                 return phy_write(phydev, MII_DP83869_MICR, micr_status);
 144         }
 145
 146         return phy_write(phydev, MII_DP83869_MICR, micr_status);
 147 }
 148
 149 static int dp83869_config_port_mirroring(struct phy_device *phydev)
 150 {
 151         struct dp83869_private *dp83869 = phydev->priv;
 152
 153         if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN)
 154                 phy_set_bits_mmd(phydev, DP83869_DEVADDR, DP83869_GEN_CFG3,
 155                                  DP83869_CFG3_PORT_MIRROR_EN);
 156         else
 157                 phy_clear_bits_mmd(phydev, DP83869_DEVADDR, DP83869_GEN_CFG3,
 158                                    DP83869_CFG3_PORT_MIRROR_EN);
 159
 160         return 0;
 161 }
 162
 163 #ifdef CONFIG_OF_MDIO
 164 static int dp83869_of_init(struct phy_device *phydev)
 165 {
 166         struct dp83869_private *dp83869 = phydev->priv;
 167         struct device *dev = &phydev->mdio.dev;
 168         struct device_node *of_node = dev->of_node;
 169         int ret;
 170
 171         if (!of_node)
 172                 return -ENODEV;
 173
 174         dp83869->io_impedance = -EINVAL;
 175
 176         /* Optional configuration */
 177         ret = of_property_read_u32(of_node, "ti,clk-output-sel",
 178                                    &dp83869->clk_output_sel);
 179         if (ret || dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK)
 180                 dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK;
 181
 182         ret = of_property_read_u32(of_node, "ti,op-mode", &dp83869->mode);
 183         if (ret == 0) {
 184                 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
 185                     dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
 186                         return -EINVAL;
 187         }
 188
 189         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
 190                 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 191         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
 192                 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 193
 194         if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
 195                 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
 196         else
 197                 dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS;
 198
 199         if (of_property_read_u32(of_node, "rx-fifo-depth",
 200                                  &dp83869->rx_fifo_depth))
 201                 dp83869->rx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
 202
 203         if (of_property_read_u32(of_node, "tx-fifo-depth",
 204                                  &dp83869->tx_fifo_depth))
 205                 dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
 206
 207         return 0;
 208 }
 209 #else
 210 static int dp83869_of_init(struct phy_device *phydev)
 211 {
 212         return 0;
 213 }
 214 #endif /* CONFIG_OF_MDIO */
 215
 216 static int dp83869_configure_rgmii(struct phy_device *phydev,
 217                                    struct dp83869_private *dp83869)
 218 {
 219         int ret, val;
 220
 221         if (phy_interface_is_rgmii(phydev)) {
 222                 val = phy_read(phydev, MII_DP83869_PHYCTRL);
 223                 if (val < 0)
 224                         return val;
 225
 226                 val &= ~DP83869_PHYCR_FIFO_DEPTH_MASK;
 227                 val |= (dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT);
 228                 val |= (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT);
 229
 230                 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val);
 231                 if (ret)
 232                         return ret;
 233         }
 234
 235         if (dp83869->io_impedance >= 0)
 236                 phy_modify_mmd(phydev, DP83869_DEVADDR,
 237                                DP83869_IO_MUX_CFG,
 238                                DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
 239                                dp83869->io_impedance &
 240                                DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
 241
 242         return ret;
 243 }
 244
 245 static int dp83869_configure_mode(struct phy_device *phydev,
 246                                   struct dp83869_private *dp83869)
 247 {
 248         int phy_ctrl_val;
 249         int ret;
 250
 251         if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
 252             dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
 253                 return -EINVAL;
 254
 255         /* Below init sequence for each operational mode is defined in
 256          * section 9.4.8 of the datasheet.
 257          */
 258         ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
 259                             dp83869->mode);
 260         if (ret)
 261                 return ret;
 262
 263         ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT);
 264         if (ret)
 265                 return ret;
 266
 267         phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT |
 268                         dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT |
 269                         DP83869_PHY_CTRL_DEFAULT);
 270
 271         switch (dp83869->mode) {
 272         case DP83869_RGMII_COPPER_ETHERNET:
 273                 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
 274                                 phy_ctrl_val);
 275                 if (ret)
 276                         return ret;
 277
 278                 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
 279                 if (ret)
 280                         return ret;
 281
 282                 ret = dp83869_configure_rgmii(phydev, dp83869);
 283                 if (ret)
 284                         return ret;
 285                 break;
 286         case DP83869_RGMII_SGMII_BRIDGE:
 287                 phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
 288                                DP83869_SGMII_RGMII_BRIDGE,
 289                                DP83869_SGMII_RGMII_BRIDGE);
 290
 291                 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
 292                                     DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
 293                 if (ret)
 294                         return ret;
 295
 296                 break;
 297         case DP83869_1000M_MEDIA_CONVERT:
 298                 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
 299                                 phy_ctrl_val);
 300                 if (ret)
 301                         return ret;
 302
 303                 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
 304                                     DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
 305                 if (ret)
 306                         return ret;
 307                 break;
 308         case DP83869_100M_MEDIA_CONVERT:
 309                 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
 310                                 phy_ctrl_val);
 311                 if (ret)
 312                         return ret;
 313                 break;
 314         case DP83869_SGMII_COPPER_ETHERNET:
 315                 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
 316                                 phy_ctrl_val);
 317                 if (ret)
 318                         return ret;
 319
 320                 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
 321                 if (ret)
 322                         return ret;
 323
 324                 ret = phy_write_mmd(phydev, DP83869_DEVADDR,
 325                                     DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
 326                 if (ret)
 327                         return ret;
 328
 329                 break;
 330         case DP83869_RGMII_1000_BASE:
 331         case DP83869_RGMII_100_BASE:
 332                 break;
 333         default:
 334                 return -EINVAL;
 335         };
 336
 337         return 0;
 338 }
 339
 340 static int dp83869_config_init(struct phy_device *phydev)
 341 {
 342         struct dp83869_private *dp83869 = phydev->priv;
 343         int ret, val;
 344
 345         ret = dp83869_configure_mode(phydev, dp83869);
 346         if (ret)
 347                 return ret;
 348
 349         /* Enable Interrupt output INT_OE in CFG4 register */
 350         if (phy_interrupt_is_valid(phydev)) {
 351                 val = phy_read(phydev, DP83869_CFG4);
 352                 val |= DP83869_INT_OE;
 353                 phy_write(phydev, DP83869_CFG4, val);
 354         }
 355
 356         if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP)
 357                 dp83869_config_port_mirroring(phydev);
 358
 359         /* Clock output selection if muxing property is set */
 360         if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK)
 361                 phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG,
 362                                DP83869_IO_MUX_CFG_CLK_O_SEL_MASK,
 363                                dp83869->clk_output_sel <<
 364                                DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT);
 365
 366         return 0;
 367 }
 368
 369 static int dp83869_probe(struct phy_device *phydev)
 370 {
 371         struct dp83869_private *dp83869;
 372         int ret;
 373
 374         dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869),
 375                                GFP_KERNEL);
 376         if (!dp83869)
 377                 return -ENOMEM;
 378
 379         phydev->priv = dp83869;
 380
 381         ret = dp83869_of_init(phydev);
 382         if (ret)
 383                 return ret;
 384
 385         return dp83869_config_init(phydev);
 386 }
 387
 388 static int dp83869_phy_reset(struct phy_device *phydev)
 389 {
 390         int ret;
 391
 392         ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET);
 393         if (ret < 0)
 394                 return ret;
 395
 396         usleep_range(10, 20);
 397
 398         /* Global sw reset sets all registers to default.
 399          * Need to set the registers in the PHY to the right config.
 400          */
 401         return dp83869_config_init(phydev);
 402 }
 403
 404 static struct phy_driver dp83869_driver[] = {
 405         {
 406                 PHY_ID_MATCH_MODEL(DP83869_PHY_ID),
 407                 .name           = "TI DP83869",
 408
 409                 .probe          = dp83869_probe,
 410                 .config_init    = dp83869_config_init,
 411                 .soft_reset     = dp83869_phy_reset,
 412
 413                 /* IRQ related */
 414                 .ack_interrupt  = dp83869_ack_interrupt,
 415                 .config_intr    = dp83869_config_intr,
 416
 417                 .suspend        = genphy_suspend,
 418                 .resume         = genphy_resume,
 419         },
 420 };
 421 module_phy_driver(dp83869_driver);
 422
 423 static struct mdio_device_id __maybe_unused dp83869_tbl[] = {
 424         { PHY_ID_MATCH_MODEL(DP83869_PHY_ID) },
 425         { }
 426 };
 427 MODULE_DEVICE_TABLE(mdio, dp83869_tbl);
 428
 429 MODULE_DESCRIPTION("Texas Instruments DP83869 PHY driver");
 430 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 431 MODULE_LICENSE("GPL v2");