drivers/net/ethernet/ti/cpsw_ale.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Texas Instruments N-Port Ethernet Switch Address Lookup Engine
   4  *
   5  * Copyright (C) 2012 Texas Instruments
   6  *
   7  */
   8 #include <linux/bitmap.h>
   9 #include <linux/if_vlan.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/seq_file.h>
  14 #include <linux/slab.h>
  15 #include <linux/err.h>
  16 #include <linux/io.h>
  17 #include <linux/stat.h>
  18 #include <linux/sysfs.h>
  19 #include <linux/etherdevice.h>
  20
  21 #include "cpsw_ale.h"
  22
  23 #define BITMASK(bits)           (BIT(bits) - 1)
  24
  25 #define ALE_VERSION_MAJOR(rev, mask) (((rev) >> 8) & (mask))
  26 #define ALE_VERSION_MINOR(rev)  (rev & 0xff)
  27 #define ALE_VERSION_1R3         0x0103
  28 #define ALE_VERSION_1R4         0x0104
  29
  30 /* ALE Registers */
  31 #define ALE_IDVER               0x00
  32 #define ALE_STATUS              0x04
  33 #define ALE_CONTROL             0x08
  34 #define ALE_PRESCALE            0x10
  35 #define ALE_UNKNOWNVLAN         0x18
  36 #define ALE_TABLE_CONTROL       0x20
  37 #define ALE_TABLE               0x34
  38 #define ALE_PORTCTL             0x40
  39
  40 /* ALE NetCP NU switch specific Registers */
  41 #define ALE_UNKNOWNVLAN_MEMBER                  0x90
  42 #define ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD       0x94
  43 #define ALE_UNKNOWNVLAN_REG_MCAST_FLOOD         0x98
  44 #define ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS      0x9C
  45 #define ALE_VLAN_MASK_MUX(reg)                  (0xc0 + (0x4 * (reg)))
  46
  47 #define ALE_TABLE_WRITE         BIT(31)
  48
  49 #define ALE_TYPE_FREE                   0
  50 #define ALE_TYPE_ADDR                   1
  51 #define ALE_TYPE_VLAN                   2
  52 #define ALE_TYPE_VLAN_ADDR              3
  53
  54 #define ALE_UCAST_PERSISTANT            0
  55 #define ALE_UCAST_UNTOUCHED             1
  56 #define ALE_UCAST_OUI                   2
  57 #define ALE_UCAST_TOUCHED               3
  58
  59 #define ALE_TABLE_SIZE_MULTIPLIER       1024
  60 #define ALE_STATUS_SIZE_MASK            0x1f
  61 #define ALE_TABLE_SIZE_DEFAULT          64
  62
  63 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
  64 {
  65         int idx;
  66
  67         idx    = start / 32;
  68         start -= idx * 32;
  69         idx    = 2 - idx; /* flip */
  70         return (ale_entry[idx] >> start) & BITMASK(bits);
  71 }
  72
  73 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
  74                                       u32 value)
  75 {
  76         int idx;
  77
  78         value &= BITMASK(bits);
  79         idx    = start / 32;
  80         start -= idx * 32;
  81         idx    = 2 - idx; /* flip */
  82         ale_entry[idx] &= ~(BITMASK(bits) << start);
  83         ale_entry[idx] |=  (value << start);
  84 }
  85
  86 #define DEFINE_ALE_FIELD(name, start, bits)                             \
  87 static inline int cpsw_ale_get_##name(u32 *ale_entry)                   \
  88 {                                                                       \
  89         return cpsw_ale_get_field(ale_entry, start, bits);              \
  90 }                                                                       \
  91 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value)       \
  92 {                                                                       \
  93         cpsw_ale_set_field(ale_entry, start, bits, value);              \
  94 }
  95
  96 #define DEFINE_ALE_FIELD1(name, start)                                  \
  97 static inline int cpsw_ale_get_##name(u32 *ale_entry, u32 bits)         \
  98 {                                                                       \
  99         return cpsw_ale_get_field(ale_entry, start, bits);              \
 100 }                                                                       \
 101 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value,       \
 102                 u32 bits)                                               \
 103 {                                                                       \
 104         cpsw_ale_set_field(ale_entry, start, bits, value);              \
 105 }
 106
 107 DEFINE_ALE_FIELD(entry_type,            60,     2)
 108 DEFINE_ALE_FIELD(vlan_id,               48,     12)
 109 DEFINE_ALE_FIELD(mcast_state,           62,     2)
 110 DEFINE_ALE_FIELD1(port_mask,            66)
 111 DEFINE_ALE_FIELD(super,                 65,     1)
 112 DEFINE_ALE_FIELD(ucast_type,            62,     2)
 113 DEFINE_ALE_FIELD1(port_num,             66)
 114 DEFINE_ALE_FIELD(blocked,               65,     1)
 115 DEFINE_ALE_FIELD(secure,                64,     1)
 116 DEFINE_ALE_FIELD1(vlan_untag_force,     24)
 117 DEFINE_ALE_FIELD1(vlan_reg_mcast,       16)
 118 DEFINE_ALE_FIELD1(vlan_unreg_mcast,     8)
 119 DEFINE_ALE_FIELD1(vlan_member_list,     0)
 120 DEFINE_ALE_FIELD(mcast,                 40,     1)
 121 /* ALE NetCP nu switch specific */
 122 DEFINE_ALE_FIELD(vlan_unreg_mcast_idx,  20,     3)
 123 DEFINE_ALE_FIELD(vlan_reg_mcast_idx,    44,     3)
 124
 125 /* The MAC address field in the ALE entry cannot be macroized as above */
 126 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
 127 {
 128         int i;
 129
 130         for (i = 0; i < 6; i++)
 131                 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
 132 }
 133
 134 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
 135 {
 136         int i;
 137
 138         for (i = 0; i < 6; i++)
 139                 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
 140 }
 141
 142 static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry)
 143 {
 144         int i;
 145
 146         WARN_ON(idx > ale->params.ale_entries);
 147
 148         writel_relaxed(idx, ale->params.ale_regs + ALE_TABLE_CONTROL);
 149
 150         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 151                 ale_entry[i] = readl_relaxed(ale->params.ale_regs +
 152                                              ALE_TABLE + 4 * i);
 153
 154         return idx;
 155 }
 156
 157 static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry)
 158 {
 159         int i;
 160
 161         WARN_ON(idx > ale->params.ale_entries);
 162
 163         for (i = 0; i < ALE_ENTRY_WORDS; i++)
 164                 writel_relaxed(ale_entry[i], ale->params.ale_regs +
 165                                ALE_TABLE + 4 * i);
 166
 167         writel_relaxed(idx | ALE_TABLE_WRITE, ale->params.ale_regs +
 168                        ALE_TABLE_CONTROL);
 169
 170         return idx;
 171 }
 172
 173 static int cpsw_ale_match_addr(struct cpsw_ale *ale, const u8 *addr, u16 vid)
 174 {
 175         u32 ale_entry[ALE_ENTRY_WORDS];
 176         int type, idx;
 177
 178         for (idx = 0; idx < ale->params.ale_entries; idx++) {
 179                 u8 entry_addr[6];
 180
 181                 cpsw_ale_read(ale, idx, ale_entry);
 182                 type = cpsw_ale_get_entry_type(ale_entry);
 183                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 184                         continue;
 185                 if (cpsw_ale_get_vlan_id(ale_entry) != vid)
 186                         continue;
 187                 cpsw_ale_get_addr(ale_entry, entry_addr);
 188                 if (ether_addr_equal(entry_addr, addr))
 189                         return idx;
 190         }
 191         return -ENOENT;
 192 }
 193
 194 static int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid)
 195 {
 196         u32 ale_entry[ALE_ENTRY_WORDS];
 197         int type, idx;
 198
 199         for (idx = 0; idx < ale->params.ale_entries; idx++) {
 200                 cpsw_ale_read(ale, idx, ale_entry);
 201                 type = cpsw_ale_get_entry_type(ale_entry);
 202                 if (type != ALE_TYPE_VLAN)
 203                         continue;
 204                 if (cpsw_ale_get_vlan_id(ale_entry) == vid)
 205                         return idx;
 206         }
 207         return -ENOENT;
 208 }
 209
 210 static int cpsw_ale_match_free(struct cpsw_ale *ale)
 211 {
 212         u32 ale_entry[ALE_ENTRY_WORDS];
 213         int type, idx;
 214
 215         for (idx = 0; idx < ale->params.ale_entries; idx++) {
 216                 cpsw_ale_read(ale, idx, ale_entry);
 217                 type = cpsw_ale_get_entry_type(ale_entry);
 218                 if (type == ALE_TYPE_FREE)
 219                         return idx;
 220         }
 221         return -ENOENT;
 222 }
 223
 224 static int cpsw_ale_find_ageable(struct cpsw_ale *ale)
 225 {
 226         u32 ale_entry[ALE_ENTRY_WORDS];
 227         int type, idx;
 228
 229         for (idx = 0; idx < ale->params.ale_entries; idx++) {
 230                 cpsw_ale_read(ale, idx, ale_entry);
 231                 type = cpsw_ale_get_entry_type(ale_entry);
 232                 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
 233                         continue;
 234                 if (cpsw_ale_get_mcast(ale_entry))
 235                         continue;
 236                 type = cpsw_ale_get_ucast_type(ale_entry);
 237                 if (type != ALE_UCAST_PERSISTANT &&
 238                     type != ALE_UCAST_OUI)
 239                         return idx;
 240         }
 241         return -ENOENT;
 242 }
 243
 244 static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry,
 245                                  int port_mask)
 246 {
 247         int mask;
 248
 249         mask = cpsw_ale_get_port_mask(ale_entry,
 250                                       ale->port_mask_bits);
 251         if ((mask & port_mask) == 0)
 252                 return; /* ports dont intersect, not interested */
 253         mask &= ~port_mask;
 254
 255         /* free if only remaining port is host port */
 256         if (mask)
 257                 cpsw_ale_set_port_mask(ale_entry, mask,
 258                                        ale->port_mask_bits);
 259         else
 260                 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
 261 }
 262
 263 int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid)
 264 {
 265         u32 ale_entry[ALE_ENTRY_WORDS];
 266         int ret, idx;
 267
 268         for (idx = 0; idx < ale->params.ale_entries; idx++) {
 269                 cpsw_ale_read(ale, idx, ale_entry);
 270                 ret = cpsw_ale_get_entry_type(ale_entry);
 271                 if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
 272                         continue;
 273
 274                 /* if vid passed is -1 then remove all multicast entry from
 275                  * the table irrespective of vlan id, if a valid vlan id is
 276                  * passed then remove only multicast added to that vlan id.
 277                  * if vlan id doesn't match then move on to next entry.
 278                  */
 279                 if (vid != -1 && cpsw_ale_get_vlan_id(ale_entry) != vid)
 280                         continue;
 281
 282                 if (cpsw_ale_get_mcast(ale_entry)) {
 283                         u8 addr[6];
 284
 285                         if (cpsw_ale_get_super(ale_entry))
 286                                 continue;
 287
 288                         cpsw_ale_get_addr(ale_entry, addr);
 289                         if (!is_broadcast_ether_addr(addr))
 290                                 cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
 291                 }
 292
 293                 cpsw_ale_write(ale, idx, ale_entry);
 294         }
 295         return 0;
 296 }
 297
 298 static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry,
 299                                                 int flags, u16 vid)
 300 {
 301         if (flags & ALE_VLAN) {
 302                 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR);
 303                 cpsw_ale_set_vlan_id(ale_entry, vid);
 304         } else {
 305                 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
 306         }
 307 }
 308
 309 int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
 310                        int flags, u16 vid)
 311 {
 312         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 313         int idx;
 314
 315         cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
 316
 317         cpsw_ale_set_addr(ale_entry, addr);
 318         cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
 319         cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
 320         cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
 321         cpsw_ale_set_port_num(ale_entry, port, ale->port_num_bits);
 322
 323         idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
 324         if (idx < 0)
 325                 idx = cpsw_ale_match_free(ale);
 326         if (idx < 0)
 327                 idx = cpsw_ale_find_ageable(ale);
 328         if (idx < 0)
 329                 return -ENOMEM;
 330
 331         cpsw_ale_write(ale, idx, ale_entry);
 332         return 0;
 333 }
 334
 335 int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
 336                        int flags, u16 vid)
 337 {
 338         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 339         int idx;
 340
 341         idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
 342         if (idx < 0)
 343                 return -ENOENT;
 344
 345         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
 346         cpsw_ale_write(ale, idx, ale_entry);
 347         return 0;
 348 }
 349
 350 int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
 351                        int flags, u16 vid, int mcast_state)
 352 {
 353         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 354         int idx, mask;
 355
 356         idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
 357         if (idx >= 0)
 358                 cpsw_ale_read(ale, idx, ale_entry);
 359
 360         cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
 361
 362         cpsw_ale_set_addr(ale_entry, addr);
 363         cpsw_ale_set_super(ale_entry, (flags & ALE_SUPER) ? 1 : 0);
 364         cpsw_ale_set_mcast_state(ale_entry, mcast_state);
 365
 366         mask = cpsw_ale_get_port_mask(ale_entry,
 367                                       ale->port_mask_bits);
 368         port_mask |= mask;
 369         cpsw_ale_set_port_mask(ale_entry, port_mask,
 370                                ale->port_mask_bits);
 371
 372         if (idx < 0)
 373                 idx = cpsw_ale_match_free(ale);
 374         if (idx < 0)
 375                 idx = cpsw_ale_find_ageable(ale);
 376         if (idx < 0)
 377                 return -ENOMEM;
 378
 379         cpsw_ale_write(ale, idx, ale_entry);
 380         return 0;
 381 }
 382
 383 int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
 384                        int flags, u16 vid)
 385 {
 386         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 387         int mcast_members;
 388         int idx;
 389
 390         idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
 391         if (idx < 0)
 392                 return -ENOENT;
 393
 394         cpsw_ale_read(ale, idx, ale_entry);
 395
 396         if (port_mask) {
 397                 mcast_members = cpsw_ale_get_port_mask(ale_entry,
 398                                                        ale->port_mask_bits);
 399                 mcast_members &= ~port_mask;
 400                 cpsw_ale_set_port_mask(ale_entry, mcast_members,
 401                                        ale->port_mask_bits);
 402         } else {
 403                 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
 404         }
 405
 406         cpsw_ale_write(ale, idx, ale_entry);
 407         return 0;
 408 }
 409
 410 /* ALE NetCP NU switch specific vlan functions */
 411 static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry,
 412                                     int reg_mcast, int unreg_mcast)
 413 {
 414         int idx;
 415
 416         /* Set VLAN registered multicast flood mask */
 417         idx = cpsw_ale_get_vlan_reg_mcast_idx(ale_entry);
 418         writel(reg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
 419
 420         /* Set VLAN unregistered multicast flood mask */
 421         idx = cpsw_ale_get_vlan_unreg_mcast_idx(ale_entry);
 422         writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
 423 }
 424
 425 static void cpsw_ale_set_vlan_untag(struct cpsw_ale *ale, u32 *ale_entry,
 426                                     u16 vid, int untag_mask)
 427 {
 428         cpsw_ale_set_vlan_untag_force(ale_entry,
 429                                       untag_mask, ale->vlan_field_bits);
 430         if (untag_mask & ALE_PORT_HOST)
 431                 bitmap_set(ale->p0_untag_vid_mask, vid, 1);
 432         else
 433                 bitmap_clear(ale->p0_untag_vid_mask, vid, 1);
 434 }
 435
 436 int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag,
 437                       int reg_mcast, int unreg_mcast)
 438 {
 439         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 440         int idx;
 441
 442         idx = cpsw_ale_match_vlan(ale, vid);
 443         if (idx >= 0)
 444                 cpsw_ale_read(ale, idx, ale_entry);
 445
 446         cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN);
 447         cpsw_ale_set_vlan_id(ale_entry, vid);
 448         cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag);
 449
 450         if (!ale->params.nu_switch_ale) {
 451                 cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast,
 452                                             ale->vlan_field_bits);
 453                 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast,
 454                                               ale->vlan_field_bits);
 455         } else {
 456                 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, unreg_mcast);
 457         }
 458         cpsw_ale_set_vlan_member_list(ale_entry, port_mask,
 459                                       ale->vlan_field_bits);
 460
 461         if (idx < 0)
 462                 idx = cpsw_ale_match_free(ale);
 463         if (idx < 0)
 464                 idx = cpsw_ale_find_ageable(ale);
 465         if (idx < 0)
 466                 return -ENOMEM;
 467
 468         cpsw_ale_write(ale, idx, ale_entry);
 469         return 0;
 470 }
 471
 472 static void cpsw_ale_del_vlan_modify(struct cpsw_ale *ale, u32 *ale_entry,
 473                                      u16 vid, int port_mask)
 474 {
 475         int reg_mcast, unreg_mcast;
 476         int members, untag;
 477
 478         members = cpsw_ale_get_vlan_member_list(ale_entry,
 479                                                 ale->vlan_field_bits);
 480         members &= ~port_mask;
 481
 482         untag = cpsw_ale_get_vlan_untag_force(ale_entry,
 483                                               ale->vlan_field_bits);
 484         reg_mcast = cpsw_ale_get_vlan_reg_mcast(ale_entry,
 485                                                 ale->vlan_field_bits);
 486         unreg_mcast = cpsw_ale_get_vlan_unreg_mcast(ale_entry,
 487                                                     ale->vlan_field_bits);
 488         untag &= members;
 489         reg_mcast &= members;
 490         unreg_mcast &= members;
 491
 492         cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag);
 493
 494         if (!ale->params.nu_switch_ale) {
 495                 cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast,
 496                                             ale->vlan_field_bits);
 497                 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast,
 498                                               ale->vlan_field_bits);
 499         } else {
 500                 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast,
 501                                         unreg_mcast);
 502         }
 503         cpsw_ale_set_vlan_member_list(ale_entry, members,
 504                                       ale->vlan_field_bits);
 505 }
 506
 507 int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask)
 508 {
 509         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 510         int idx;
 511
 512         idx = cpsw_ale_match_vlan(ale, vid);
 513         if (idx < 0)
 514                 return -ENOENT;
 515
 516         cpsw_ale_read(ale, idx, ale_entry);
 517
 518         if (port_mask) {
 519                 cpsw_ale_del_vlan_modify(ale, ale_entry, vid, port_mask);
 520         } else {
 521                 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0);
 522                 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
 523         }
 524
 525         cpsw_ale_write(ale, idx, ale_entry);
 526
 527         return 0;
 528 }
 529
 530 int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask,
 531                              int untag_mask, int reg_mask, int unreg_mask)
 532 {
 533         u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
 534         int reg_mcast_members, unreg_mcast_members;
 535         int vlan_members, untag_members;
 536         int idx, ret = 0;
 537
 538         idx = cpsw_ale_match_vlan(ale, vid);
 539         if (idx >= 0)
 540                 cpsw_ale_read(ale, idx, ale_entry);
 541
 542         vlan_members = cpsw_ale_get_vlan_member_list(ale_entry,
 543                                                      ale->vlan_field_bits);
 544         reg_mcast_members = cpsw_ale_get_vlan_reg_mcast(ale_entry,
 545                                                         ale->vlan_field_bits);
 546         unreg_mcast_members =
 547                 cpsw_ale_get_vlan_unreg_mcast(ale_entry,
 548                                               ale->vlan_field_bits);
 549         untag_members = cpsw_ale_get_vlan_untag_force(ale_entry,
 550                                                       ale->vlan_field_bits);
 551
 552         vlan_members |= port_mask;
 553         untag_members = (untag_members & ~port_mask) | untag_mask;
 554         reg_mcast_members = (reg_mcast_members & ~port_mask) | reg_mask;
 555         unreg_mcast_members = (unreg_mcast_members & ~port_mask) | unreg_mask;
 556
 557         ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members,
 558                                 reg_mcast_members, unreg_mcast_members);
 559         if (ret) {
 560                 dev_err(ale->params.dev, "Unable to add vlan\n");
 561                 return ret;
 562         }
 563         dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members,
 564                 untag_mask);
 565
 566         return ret;
 567 }
 568
 569 void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask,
 570                               bool add)
 571 {
 572         u32 ale_entry[ALE_ENTRY_WORDS];
 573         int unreg_members = 0;
 574         int type, idx;
 575
 576         for (idx = 0; idx < ale->params.ale_entries; idx++) {
 577                 cpsw_ale_read(ale, idx, ale_entry);
 578                 type = cpsw_ale_get_entry_type(ale_entry);
 579                 if (type != ALE_TYPE_VLAN)
 580                         continue;
 581
 582                 unreg_members =
 583                         cpsw_ale_get_vlan_unreg_mcast(ale_entry,
 584                                                       ale->vlan_field_bits);
 585                 if (add)
 586                         unreg_members |= unreg_mcast_mask;
 587                 else
 588                         unreg_members &= ~unreg_mcast_mask;
 589                 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_members,
 590                                               ale->vlan_field_bits);
 591                 cpsw_ale_write(ale, idx, ale_entry);
 592         }
 593 }
 594
 595 void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port)
 596 {
 597         u32 ale_entry[ALE_ENTRY_WORDS];
 598         int unreg_mcast = 0;
 599         int type, idx;
 600
 601         for (idx = 0; idx < ale->params.ale_entries; idx++) {
 602                 int vlan_members;
 603
 604                 cpsw_ale_read(ale, idx, ale_entry);
 605                 type = cpsw_ale_get_entry_type(ale_entry);
 606                 if (type != ALE_TYPE_VLAN)
 607                         continue;
 608                 vlan_members =
 609                         cpsw_ale_get_vlan_member_list(ale_entry,
 610                                                       ale->vlan_field_bits);
 611
 612                 if (port != -1 && !(vlan_members & BIT(port)))
 613                         continue;
 614
 615                 unreg_mcast =
 616                         cpsw_ale_get_vlan_unreg_mcast(ale_entry,
 617                                                       ale->vlan_field_bits);
 618                 if (allmulti)
 619                         unreg_mcast |= ALE_PORT_HOST;
 620                 else
 621                         unreg_mcast &= ~ALE_PORT_HOST;
 622                 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast,
 623                                               ale->vlan_field_bits);
 624                 cpsw_ale_write(ale, idx, ale_entry);
 625         }
 626 }
 627
 628 struct ale_control_info {
 629         const char      *name;
 630         int             offset, port_offset;
 631         int             shift, port_shift;
 632         int             bits;
 633 };
 634
 635 static struct ale_control_info ale_controls[ALE_NUM_CONTROLS] = {
 636         [ALE_ENABLE]            = {
 637                 .name           = "enable",
 638                 .offset         = ALE_CONTROL,
 639                 .port_offset    = 0,
 640                 .shift          = 31,
 641                 .port_shift     = 0,
 642                 .bits           = 1,
 643         },
 644         [ALE_CLEAR]             = {
 645                 .name           = "clear",
 646                 .offset         = ALE_CONTROL,
 647                 .port_offset    = 0,
 648                 .shift          = 30,
 649                 .port_shift     = 0,
 650                 .bits           = 1,
 651         },
 652         [ALE_AGEOUT]            = {
 653                 .name           = "ageout",
 654                 .offset         = ALE_CONTROL,
 655                 .port_offset    = 0,
 656                 .shift          = 29,
 657                 .port_shift     = 0,
 658                 .bits           = 1,
 659         },
 660         [ALE_P0_UNI_FLOOD]      = {
 661                 .name           = "port0_unicast_flood",
 662                 .offset         = ALE_CONTROL,
 663                 .port_offset    = 0,
 664                 .shift          = 8,
 665                 .port_shift     = 0,
 666                 .bits           = 1,
 667         },
 668         [ALE_VLAN_NOLEARN]      = {
 669                 .name           = "vlan_nolearn",
 670                 .offset         = ALE_CONTROL,
 671                 .port_offset    = 0,
 672                 .shift          = 7,
 673                 .port_shift     = 0,
 674                 .bits           = 1,
 675         },
 676         [ALE_NO_PORT_VLAN]      = {
 677                 .name           = "no_port_vlan",
 678                 .offset         = ALE_CONTROL,
 679                 .port_offset    = 0,
 680                 .shift          = 6,
 681                 .port_shift     = 0,
 682                 .bits           = 1,
 683         },
 684         [ALE_OUI_DENY]          = {
 685                 .name           = "oui_deny",
 686                 .offset         = ALE_CONTROL,
 687                 .port_offset    = 0,
 688                 .shift          = 5,
 689                 .port_shift     = 0,
 690                 .bits           = 1,
 691         },
 692         [ALE_BYPASS]            = {
 693                 .name           = "bypass",
 694                 .offset         = ALE_CONTROL,
 695                 .port_offset    = 0,
 696                 .shift          = 4,
 697                 .port_shift     = 0,
 698                 .bits           = 1,
 699         },
 700         [ALE_RATE_LIMIT_TX]     = {
 701                 .name           = "rate_limit_tx",
 702                 .offset         = ALE_CONTROL,
 703                 .port_offset    = 0,
 704                 .shift          = 3,
 705                 .port_shift     = 0,
 706                 .bits           = 1,
 707         },
 708         [ALE_VLAN_AWARE]        = {
 709                 .name           = "vlan_aware",
 710                 .offset         = ALE_CONTROL,
 711                 .port_offset    = 0,
 712                 .shift          = 2,
 713                 .port_shift     = 0,
 714                 .bits           = 1,
 715         },
 716         [ALE_AUTH_ENABLE]       = {
 717                 .name           = "auth_enable",
 718                 .offset         = ALE_CONTROL,
 719                 .port_offset    = 0,
 720                 .shift          = 1,
 721                 .port_shift     = 0,
 722                 .bits           = 1,
 723         },
 724         [ALE_RATE_LIMIT]        = {
 725                 .name           = "rate_limit",
 726                 .offset         = ALE_CONTROL,
 727                 .port_offset    = 0,
 728                 .shift          = 0,
 729                 .port_shift     = 0,
 730                 .bits           = 1,
 731         },
 732         [ALE_PORT_STATE]        = {
 733                 .name           = "port_state",
 734                 .offset         = ALE_PORTCTL,
 735                 .port_offset    = 4,
 736                 .shift          = 0,
 737                 .port_shift     = 0,
 738                 .bits           = 2,
 739         },
 740         [ALE_PORT_DROP_UNTAGGED] = {
 741                 .name           = "drop_untagged",
 742                 .offset         = ALE_PORTCTL,
 743                 .port_offset    = 4,
 744                 .shift          = 2,
 745                 .port_shift     = 0,
 746                 .bits           = 1,
 747         },
 748         [ALE_PORT_DROP_UNKNOWN_VLAN] = {
 749                 .name           = "drop_unknown",
 750                 .offset         = ALE_PORTCTL,
 751                 .port_offset    = 4,
 752                 .shift          = 3,
 753                 .port_shift     = 0,
 754                 .bits           = 1,
 755         },
 756         [ALE_PORT_NOLEARN]      = {
 757                 .name           = "nolearn",
 758                 .offset         = ALE_PORTCTL,
 759                 .port_offset    = 4,
 760                 .shift          = 4,
 761                 .port_shift     = 0,
 762                 .bits           = 1,
 763         },
 764         [ALE_PORT_NO_SA_UPDATE] = {
 765                 .name           = "no_source_update",
 766                 .offset         = ALE_PORTCTL,
 767                 .port_offset    = 4,
 768                 .shift          = 5,
 769                 .port_shift     = 0,
 770                 .bits           = 1,
 771         },
 772         [ALE_PORT_MCAST_LIMIT]  = {
 773                 .name           = "mcast_limit",
 774                 .offset         = ALE_PORTCTL,
 775                 .port_offset    = 4,
 776                 .shift          = 16,
 777                 .port_shift     = 0,
 778                 .bits           = 8,
 779         },
 780         [ALE_PORT_BCAST_LIMIT]  = {
 781                 .name           = "bcast_limit",
 782                 .offset         = ALE_PORTCTL,
 783                 .port_offset    = 4,
 784                 .shift          = 24,
 785                 .port_shift     = 0,
 786                 .bits           = 8,
 787         },
 788         [ALE_PORT_UNKNOWN_VLAN_MEMBER] = {
 789                 .name           = "unknown_vlan_member",
 790                 .offset         = ALE_UNKNOWNVLAN,
 791                 .port_offset    = 0,
 792                 .shift          = 0,
 793                 .port_shift     = 0,
 794                 .bits           = 6,
 795         },
 796         [ALE_PORT_UNKNOWN_MCAST_FLOOD] = {
 797                 .name           = "unknown_mcast_flood",
 798                 .offset         = ALE_UNKNOWNVLAN,
 799                 .port_offset    = 0,
 800                 .shift          = 8,
 801                 .port_shift     = 0,
 802                 .bits           = 6,
 803         },
 804         [ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = {
 805                 .name           = "unknown_reg_flood",
 806                 .offset         = ALE_UNKNOWNVLAN,
 807                 .port_offset    = 0,
 808                 .shift          = 16,
 809                 .port_shift     = 0,
 810                 .bits           = 6,
 811         },
 812         [ALE_PORT_UNTAGGED_EGRESS] = {
 813                 .name           = "untagged_egress",
 814                 .offset         = ALE_UNKNOWNVLAN,
 815                 .port_offset    = 0,
 816                 .shift          = 24,
 817                 .port_shift     = 0,
 818                 .bits           = 6,
 819         },
 820 };
 821
 822 int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control,
 823                          int value)
 824 {
 825         const struct ale_control_info *info;
 826         int offset, shift;
 827         u32 tmp, mask;
 828
 829         if (control < 0 || control >= ARRAY_SIZE(ale_controls))
 830                 return -EINVAL;
 831
 832         info = &ale_controls[control];
 833         if (info->port_offset == 0 && info->port_shift == 0)
 834                 port = 0; /* global, port is a dont care */
 835
 836         if (port < 0 || port >= ale->params.ale_ports)
 837                 return -EINVAL;
 838
 839         mask = BITMASK(info->bits);
 840         if (value & ~mask)
 841                 return -EINVAL;
 842
 843         offset = info->offset + (port * info->port_offset);
 844         shift  = info->shift  + (port * info->port_shift);
 845
 846         tmp = readl_relaxed(ale->params.ale_regs + offset);
 847         tmp = (tmp & ~(mask << shift)) | (value << shift);
 848         writel_relaxed(tmp, ale->params.ale_regs + offset);
 849
 850         return 0;
 851 }
 852
 853 int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control)
 854 {
 855         const struct ale_control_info *info;
 856         int offset, shift;
 857         u32 tmp;
 858
 859         if (control < 0 || control >= ARRAY_SIZE(ale_controls))
 860                 return -EINVAL;
 861
 862         info = &ale_controls[control];
 863         if (info->port_offset == 0 && info->port_shift == 0)
 864                 port = 0; /* global, port is a dont care */
 865
 866         if (port < 0 || port >= ale->params.ale_ports)
 867                 return -EINVAL;
 868
 869         offset = info->offset + (port * info->port_offset);
 870         shift  = info->shift  + (port * info->port_shift);
 871
 872         tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift;
 873         return tmp & BITMASK(info->bits);
 874 }
 875
 876 static void cpsw_ale_timer(struct timer_list *t)
 877 {
 878         struct cpsw_ale *ale = from_timer(ale, t, timer);
 879
 880         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 881
 882         if (ale->ageout) {
 883                 ale->timer.expires = jiffies + ale->ageout;
 884                 add_timer(&ale->timer);
 885         }
 886 }
 887
 888 void cpsw_ale_start(struct cpsw_ale *ale)
 889 {
 890         cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1);
 891         cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
 892
 893         timer_setup(&ale->timer, cpsw_ale_timer, 0);
 894         if (ale->ageout) {
 895                 ale->timer.expires = jiffies + ale->ageout;
 896                 add_timer(&ale->timer);
 897         }
 898 }
 899
 900 void cpsw_ale_stop(struct cpsw_ale *ale)
 901 {
 902         del_timer_sync(&ale->timer);
 903         cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
 904         cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
 905 }
 906
 907 struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params)
 908 {
 909         struct cpsw_ale *ale;
 910         u32 rev, ale_entries;
 911
 912         ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL);
 913         if (!ale)
 914                 return NULL;
 915
 916         ale->p0_untag_vid_mask =
 917                 devm_kmalloc_array(params->dev, BITS_TO_LONGS(VLAN_N_VID),
 918                                    sizeof(unsigned long),
 919                                    GFP_KERNEL);
 920         if (!ale->p0_untag_vid_mask)
 921                 return ERR_PTR(-ENOMEM);
 922
 923         ale->params = *params;
 924         ale->ageout = ale->params.ale_ageout * HZ;
 925
 926         rev = readl_relaxed(ale->params.ale_regs + ALE_IDVER);
 927         if (!ale->params.major_ver_mask)
 928                 ale->params.major_ver_mask = 0xff;
 929         ale->version =
 930                 (ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask) << 8) |
 931                  ALE_VERSION_MINOR(rev);
 932         dev_info(ale->params.dev, "initialized cpsw ale version %d.%d\n",
 933                  ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask),
 934                  ALE_VERSION_MINOR(rev));
 935
 936         if (!ale->params.ale_entries) {
 937                 ale_entries =
 938                         readl_relaxed(ale->params.ale_regs + ALE_STATUS) &
 939                         ALE_STATUS_SIZE_MASK;
 940                 /* ALE available on newer NetCP switches has introduced
 941                  * a register, ALE_STATUS, to indicate the size of ALE
 942                  * table which shows the size as a multiple of 1024 entries.
 943                  * For these, params.ale_entries will be set to zero. So
 944                  * read the register and update the value of ale_entries.
 945                  * ALE table on NetCP lite, is much smaller and is indicated
 946                  * by a value of zero in ALE_STATUS. So use a default value
 947                  * of ALE_TABLE_SIZE_DEFAULT for this. Caller is expected
 948                  * to set the value of ale_entries for all other versions
 949                  * of ALE.
 950                  */
 951                 if (!ale_entries)
 952                         ale_entries = ALE_TABLE_SIZE_DEFAULT;
 953                 else
 954                         ale_entries *= ALE_TABLE_SIZE_MULTIPLIER;
 955                 ale->params.ale_entries = ale_entries;
 956         }
 957         dev_info(ale->params.dev,
 958                  "ALE Table size %ld\n", ale->params.ale_entries);
 959
 960         /* set default bits for existing h/w */
 961         ale->port_mask_bits = ale->params.ale_ports;
 962         ale->port_num_bits = order_base_2(ale->params.ale_ports);
 963         ale->vlan_field_bits = ale->params.ale_ports;
 964
 965         /* Set defaults override for ALE on NetCP NU switch and for version
 966          * 1R3
 967          */
 968         if (ale->params.nu_switch_ale) {
 969                 /* Separate registers for unknown vlan configuration.
 970                  * Also there are N bits, where N is number of ale
 971                  * ports and shift value should be 0
 972                  */
 973                 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].bits =
 974                                         ale->params.ale_ports;
 975                 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].offset =
 976                                         ALE_UNKNOWNVLAN_MEMBER;
 977                 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].bits =
 978                                         ale->params.ale_ports;
 979                 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].shift = 0;
 980                 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].offset =
 981                                         ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD;
 982                 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].bits =
 983                                         ale->params.ale_ports;
 984                 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].shift = 0;
 985                 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].offset =
 986                                         ALE_UNKNOWNVLAN_REG_MCAST_FLOOD;
 987                 ale_controls[ALE_PORT_UNTAGGED_EGRESS].bits =
 988                                         ale->params.ale_ports;
 989                 ale_controls[ALE_PORT_UNTAGGED_EGRESS].shift = 0;
 990                 ale_controls[ALE_PORT_UNTAGGED_EGRESS].offset =
 991                                         ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS;
 992         }
 993
 994         cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
 995         return ale;
 996 }
 997
 998 void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data)
 999 {
1000         int i;
1001
1002         for (i = 0; i < ale->params.ale_entries; i++) {
1003                 cpsw_ale_read(ale, i, data);
1004                 data += ALE_ENTRY_WORDS;
1005         }
1006 }