1 // SPDX-License-Identifier: GPL-2.0-only
3 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 * DWC Ether MAC version 4.00 has been used for developing this code.
6 * This only implements the mac core functions for this chip.
8 * Copyright (C) 2015 STMicroelectronics Ltd
10 * Author: Alexandre Torgue <alexandre.torgue@st.com>
13 #include <linux/crc32.h>
14 #include <linux/slab.h>
15 #include <linux/ethtool.h>
19 #include "stmmac_pcs.h"
23 static void dwmac4_core_init(struct mac_device_info *hw,
24 struct net_device *dev)
26 void __iomem *ioaddr = hw->pcsr;
27 u32 value = readl(ioaddr + GMAC_CONFIG);
30 value |= GMAC_CORE_INIT;
33 value |= GMAC_CONFIG_2K;
35 value |= GMAC_CONFIG_JE;
38 value |= GMAC_CONFIG_TE;
40 value &= hw->link.speed_mask;
43 value |= hw->link.speed1000;
46 value |= hw->link.speed100;
49 value |= hw->link.speed10;
54 writel(value, ioaddr + GMAC_CONFIG);
56 /* Enable GMAC interrupts */
57 value = GMAC_INT_DEFAULT_ENABLE;
60 value |= GMAC_PCS_IRQ_DEFAULT;
62 writel(value, ioaddr + GMAC_INT_EN);
65 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
68 void __iomem *ioaddr = hw->pcsr;
69 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
71 value &= GMAC_RX_QUEUE_CLEAR(queue);
72 if (mode == MTL_QUEUE_AVB)
73 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
74 else if (mode == MTL_QUEUE_DCB)
75 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
77 writel(value, ioaddr + GMAC_RXQ_CTRL0);
80 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
83 void __iomem *ioaddr = hw->pcsr;
87 base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
89 value = readl(ioaddr + base_register);
91 value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
92 value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
93 GMAC_RXQCTRL_PSRQX_MASK(queue);
94 writel(value, ioaddr + base_register);
97 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
100 void __iomem *ioaddr = hw->pcsr;
104 base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
106 value = readl(ioaddr + base_register);
108 value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
109 value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
110 GMAC_TXQCTRL_PSTQX_MASK(queue);
112 writel(value, ioaddr + base_register);
115 static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
116 u8 packet, u32 queue)
118 void __iomem *ioaddr = hw->pcsr;
121 static const struct stmmac_rx_routing route_possibilities[] = {
122 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
123 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
124 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
125 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
126 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
129 value = readl(ioaddr + GMAC_RXQ_CTRL1);
131 /* routing configuration */
132 value &= ~route_possibilities[packet - 1].reg_mask;
133 value |= (queue << route_possibilities[packet-1].reg_shift) &
134 route_possibilities[packet - 1].reg_mask;
136 /* some packets require extra ops */
137 if (packet == PACKET_AVCPQ) {
138 value &= ~GMAC_RXQCTRL_TACPQE;
139 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
140 } else if (packet == PACKET_MCBCQ) {
141 value &= ~GMAC_RXQCTRL_MCBCQEN;
142 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
145 writel(value, ioaddr + GMAC_RXQ_CTRL1);
148 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
151 void __iomem *ioaddr = hw->pcsr;
152 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
154 value &= ~MTL_OPERATION_RAA;
156 case MTL_RX_ALGORITHM_SP:
157 value |= MTL_OPERATION_RAA_SP;
159 case MTL_RX_ALGORITHM_WSP:
160 value |= MTL_OPERATION_RAA_WSP;
166 writel(value, ioaddr + MTL_OPERATION_MODE);
169 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
172 void __iomem *ioaddr = hw->pcsr;
173 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
175 value &= ~MTL_OPERATION_SCHALG_MASK;
177 case MTL_TX_ALGORITHM_WRR:
178 value |= MTL_OPERATION_SCHALG_WRR;
180 case MTL_TX_ALGORITHM_WFQ:
181 value |= MTL_OPERATION_SCHALG_WFQ;
183 case MTL_TX_ALGORITHM_DWRR:
184 value |= MTL_OPERATION_SCHALG_DWRR;
186 case MTL_TX_ALGORITHM_SP:
187 value |= MTL_OPERATION_SCHALG_SP;
193 writel(value, ioaddr + MTL_OPERATION_MODE);
196 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
197 u32 weight, u32 queue)
199 void __iomem *ioaddr = hw->pcsr;
200 u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
202 value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
203 value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
204 writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
207 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
209 void __iomem *ioaddr = hw->pcsr;
213 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
215 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
217 if (queue == 0 || queue == 4) {
218 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
219 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
221 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
222 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
226 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
228 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
231 static void dwmac4_config_cbs(struct mac_device_info *hw,
232 u32 send_slope, u32 idle_slope,
233 u32 high_credit, u32 low_credit, u32 queue)
235 void __iomem *ioaddr = hw->pcsr;
238 pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
239 pr_debug("\tsend_slope: 0x%08x\n", send_slope);
240 pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
241 pr_debug("\thigh_credit: 0x%08x\n", high_credit);
242 pr_debug("\tlow_credit: 0x%08x\n", low_credit);
244 /* enable AV algorithm */
245 value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
246 value |= MTL_ETS_CTRL_AVALG;
247 value |= MTL_ETS_CTRL_CC;
248 writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
250 /* configure send slope */
251 value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
252 value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
253 value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
254 writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
256 /* configure idle slope (same register as tx weight) */
257 dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
259 /* configure high credit */
260 value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
261 value &= ~MTL_HIGH_CRED_HC_MASK;
262 value |= high_credit & MTL_HIGH_CRED_HC_MASK;
263 writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
265 /* configure high credit */
266 value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
267 value &= ~MTL_HIGH_CRED_LC_MASK;
268 value |= low_credit & MTL_HIGH_CRED_LC_MASK;
269 writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
272 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
274 void __iomem *ioaddr = hw->pcsr;
277 for (i = 0; i < GMAC_REG_NUM; i++)
278 reg_space[i] = readl(ioaddr + i * 4);
281 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
283 void __iomem *ioaddr = hw->pcsr;
284 u32 value = readl(ioaddr + GMAC_CONFIG);
287 value |= GMAC_CONFIG_IPC;
289 value &= ~GMAC_CONFIG_IPC;
291 writel(value, ioaddr + GMAC_CONFIG);
293 value = readl(ioaddr + GMAC_CONFIG);
295 return !!(value & GMAC_CONFIG_IPC);
298 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
300 void __iomem *ioaddr = hw->pcsr;
301 unsigned int pmt = 0;
304 if (mode & WAKE_MAGIC) {
305 pr_debug("GMAC: WOL Magic frame\n");
306 pmt |= power_down | magic_pkt_en;
308 if (mode & WAKE_UCAST) {
309 pr_debug("GMAC: WOL on global unicast\n");
310 pmt |= power_down | global_unicast | wake_up_frame_en;
314 /* The receiver must be enabled for WOL before powering down */
315 config = readl(ioaddr + GMAC_CONFIG);
316 config |= GMAC_CONFIG_RE;
317 writel(config, ioaddr + GMAC_CONFIG);
319 writel(pmt, ioaddr + GMAC_PMT);
322 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
323 unsigned char *addr, unsigned int reg_n)
325 void __iomem *ioaddr = hw->pcsr;
327 stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
328 GMAC_ADDR_LOW(reg_n));
331 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
332 unsigned char *addr, unsigned int reg_n)
334 void __iomem *ioaddr = hw->pcsr;
336 stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
337 GMAC_ADDR_LOW(reg_n));
340 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
341 bool en_tx_lpi_clockgating)
343 void __iomem *ioaddr = hw->pcsr;
346 /* Enable the link status receive on RGMII, SGMII ore SMII
347 * receive path and instruct the transmit to enter in LPI
350 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
351 value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
353 if (en_tx_lpi_clockgating)
354 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
356 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
359 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
361 void __iomem *ioaddr = hw->pcsr;
364 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
365 value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
366 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
369 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
371 void __iomem *ioaddr = hw->pcsr;
374 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
377 value |= GMAC4_LPI_CTRL_STATUS_PLS;
379 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
381 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
384 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
386 void __iomem *ioaddr = hw->pcsr;
387 int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
389 /* Program the timers in the LPI timer control register:
390 * LS: minimum time (ms) for which the link
391 * status from PHY should be ok before transmitting
393 * TW: minimum time (us) for which the core waits
394 * after it has stopped transmitting the LPI pattern.
396 writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
399 static void dwmac4_set_filter(struct mac_device_info *hw,
400 struct net_device *dev)
402 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
403 unsigned int value = 0;
405 if (dev->flags & IFF_PROMISC) {
406 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF;
407 } else if ((dev->flags & IFF_ALLMULTI) ||
408 (netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
410 value = GMAC_PACKET_FILTER_PM;
411 /* Set the 64 bits of the HASH tab. To be updated if taller
414 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
415 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
416 } else if (!netdev_mc_empty(dev)) {
418 struct netdev_hw_addr *ha;
420 /* Hash filter for multicast */
421 value = GMAC_PACKET_FILTER_HMC;
423 memset(mc_filter, 0, sizeof(mc_filter));
424 netdev_for_each_mc_addr(ha, dev) {
425 /* The upper 6 bits of the calculated CRC are used to
426 * index the content of the Hash Table Reg 0 and 1.
429 (bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
430 /* The most significant bit determines the register
431 * to use while the other 5 bits determines the bit
432 * within the selected register
434 mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F));
436 writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
437 writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
440 value |= GMAC_PACKET_FILTER_HPF;
442 /* Handle multiple unicast addresses */
443 if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) {
444 /* Switch to promiscuous mode if more than 128 addrs
447 value |= GMAC_PACKET_FILTER_PR;
449 struct netdev_hw_addr *ha;
452 netdev_for_each_uc_addr(ha, dev) {
453 dwmac4_set_umac_addr(hw, ha->addr, reg);
457 while (reg < GMAC_MAX_PERFECT_ADDRESSES) {
458 writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
459 writel(0, ioaddr + GMAC_ADDR_LOW(reg));
464 writel(value, ioaddr + GMAC_PACKET_FILTER);
467 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
468 unsigned int fc, unsigned int pause_time,
471 void __iomem *ioaddr = hw->pcsr;
472 unsigned int flow = 0;
475 pr_debug("GMAC Flow-Control:\n");
477 pr_debug("\tReceive Flow-Control ON\n");
478 flow |= GMAC_RX_FLOW_CTRL_RFE;
480 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
483 pr_debug("\tTransmit Flow-Control ON\n");
486 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
488 for (queue = 0; queue < tx_cnt; queue++) {
489 flow = GMAC_TX_FLOW_CTRL_TFE;
493 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
495 writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
498 for (queue = 0; queue < tx_cnt; queue++)
499 writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
503 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
506 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
509 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
511 dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
514 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
516 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
519 /* RGMII or SMII interface */
520 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
524 status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
527 /* Check the link status */
528 if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
533 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
534 GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
535 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
536 x->pcs_speed = SPEED_1000;
537 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
538 x->pcs_speed = SPEED_100;
540 x->pcs_speed = SPEED_10;
542 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
544 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
545 x->pcs_duplex ? "Full" : "Half");
548 pr_info("Link is Down\n");
552 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
554 void __iomem *ioaddr = hw->pcsr;
555 u32 mtl_int_qx_status;
558 mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
560 /* Check MTL Interrupt */
561 if (mtl_int_qx_status & MTL_INT_QX(chan)) {
562 /* read Queue x Interrupt status */
563 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
565 if (status & MTL_RX_OVERFLOW_INT) {
566 /* clear Interrupt */
567 writel(status | MTL_RX_OVERFLOW_INT,
568 ioaddr + MTL_CHAN_INT_CTRL(chan));
569 ret = CORE_IRQ_MTL_RX_OVERFLOW;
576 static int dwmac4_irq_status(struct mac_device_info *hw,
577 struct stmmac_extra_stats *x)
579 void __iomem *ioaddr = hw->pcsr;
580 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
581 u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
584 /* Discard disabled bits */
585 intr_status &= intr_enable;
587 /* Not used events (e.g. MMC interrupts) are not handled. */
588 if ((intr_status & mmc_tx_irq))
590 if (unlikely(intr_status & mmc_rx_irq))
592 if (unlikely(intr_status & mmc_rx_csum_offload_irq))
593 x->mmc_rx_csum_offload_irq_n++;
594 /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
595 if (unlikely(intr_status & pmt_irq)) {
596 readl(ioaddr + GMAC_PMT);
597 x->irq_receive_pmt_irq_n++;
600 /* MAC tx/rx EEE LPI entry/exit interrupts */
601 if (intr_status & lpi_irq) {
602 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
603 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
605 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
606 ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
607 x->irq_tx_path_in_lpi_mode_n++;
609 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
610 ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
611 x->irq_tx_path_exit_lpi_mode_n++;
613 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
614 x->irq_rx_path_in_lpi_mode_n++;
615 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
616 x->irq_rx_path_exit_lpi_mode_n++;
619 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
620 if (intr_status & PCS_RGSMIIIS_IRQ)
621 dwmac4_phystatus(ioaddr, x);
626 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
627 u32 rx_queues, u32 tx_queues)
632 for (queue = 0; queue < tx_queues; queue++) {
633 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
635 if (value & MTL_DEBUG_TXSTSFSTS)
636 x->mtl_tx_status_fifo_full++;
637 if (value & MTL_DEBUG_TXFSTS)
638 x->mtl_tx_fifo_not_empty++;
639 if (value & MTL_DEBUG_TWCSTS)
641 if (value & MTL_DEBUG_TRCSTS_MASK) {
642 u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
643 >> MTL_DEBUG_TRCSTS_SHIFT;
644 if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
645 x->mtl_tx_fifo_read_ctrl_write++;
646 else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
647 x->mtl_tx_fifo_read_ctrl_wait++;
648 else if (trcsts == MTL_DEBUG_TRCSTS_READ)
649 x->mtl_tx_fifo_read_ctrl_read++;
651 x->mtl_tx_fifo_read_ctrl_idle++;
653 if (value & MTL_DEBUG_TXPAUSED)
654 x->mac_tx_in_pause++;
657 for (queue = 0; queue < rx_queues; queue++) {
658 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
660 if (value & MTL_DEBUG_RXFSTS_MASK) {
661 u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
662 >> MTL_DEBUG_RRCSTS_SHIFT;
664 if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
665 x->mtl_rx_fifo_fill_level_full++;
666 else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
667 x->mtl_rx_fifo_fill_above_thresh++;
668 else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
669 x->mtl_rx_fifo_fill_below_thresh++;
671 x->mtl_rx_fifo_fill_level_empty++;
673 if (value & MTL_DEBUG_RRCSTS_MASK) {
674 u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
675 MTL_DEBUG_RRCSTS_SHIFT;
677 if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
678 x->mtl_rx_fifo_read_ctrl_flush++;
679 else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
680 x->mtl_rx_fifo_read_ctrl_read_data++;
681 else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
682 x->mtl_rx_fifo_read_ctrl_status++;
684 x->mtl_rx_fifo_read_ctrl_idle++;
686 if (value & MTL_DEBUG_RWCSTS)
687 x->mtl_rx_fifo_ctrl_active++;
691 value = readl(ioaddr + GMAC_DEBUG);
693 if (value & GMAC_DEBUG_TFCSTS_MASK) {
694 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
695 >> GMAC_DEBUG_TFCSTS_SHIFT;
697 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
698 x->mac_tx_frame_ctrl_xfer++;
699 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
700 x->mac_tx_frame_ctrl_pause++;
701 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
702 x->mac_tx_frame_ctrl_wait++;
704 x->mac_tx_frame_ctrl_idle++;
706 if (value & GMAC_DEBUG_TPESTS)
707 x->mac_gmii_tx_proto_engine++;
708 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
709 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
710 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
711 if (value & GMAC_DEBUG_RPESTS)
712 x->mac_gmii_rx_proto_engine++;
715 static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)
717 u32 value = readl(ioaddr + GMAC_CONFIG);
720 value |= GMAC_CONFIG_LM;
722 value &= ~GMAC_CONFIG_LM;
724 writel(value, ioaddr + GMAC_CONFIG);
727 const struct stmmac_ops dwmac4_ops = {
728 .core_init = dwmac4_core_init,
729 .set_mac = stmmac_set_mac,
730 .rx_ipc = dwmac4_rx_ipc_enable,
731 .rx_queue_enable = dwmac4_rx_queue_enable,
732 .rx_queue_prio = dwmac4_rx_queue_priority,
733 .tx_queue_prio = dwmac4_tx_queue_priority,
734 .rx_queue_routing = dwmac4_rx_queue_routing,
735 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
736 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
737 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
738 .map_mtl_to_dma = dwmac4_map_mtl_dma,
739 .config_cbs = dwmac4_config_cbs,
740 .dump_regs = dwmac4_dump_regs,
741 .host_irq_status = dwmac4_irq_status,
742 .host_mtl_irq_status = dwmac4_irq_mtl_status,
743 .flow_ctrl = dwmac4_flow_ctrl,
745 .set_umac_addr = dwmac4_set_umac_addr,
746 .get_umac_addr = dwmac4_get_umac_addr,
747 .set_eee_mode = dwmac4_set_eee_mode,
748 .reset_eee_mode = dwmac4_reset_eee_mode,
749 .set_eee_timer = dwmac4_set_eee_timer,
750 .set_eee_pls = dwmac4_set_eee_pls,
751 .pcs_ctrl_ane = dwmac4_ctrl_ane,
752 .pcs_rane = dwmac4_rane,
753 .pcs_get_adv_lp = dwmac4_get_adv_lp,
754 .debug = dwmac4_debug,
755 .set_filter = dwmac4_set_filter,
756 .set_mac_loopback = dwmac4_set_mac_loopback,
759 const struct stmmac_ops dwmac410_ops = {
760 .core_init = dwmac4_core_init,
761 .set_mac = stmmac_dwmac4_set_mac,
762 .rx_ipc = dwmac4_rx_ipc_enable,
763 .rx_queue_enable = dwmac4_rx_queue_enable,
764 .rx_queue_prio = dwmac4_rx_queue_priority,
765 .tx_queue_prio = dwmac4_tx_queue_priority,
766 .rx_queue_routing = dwmac4_rx_queue_routing,
767 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
768 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
769 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
770 .map_mtl_to_dma = dwmac4_map_mtl_dma,
771 .config_cbs = dwmac4_config_cbs,
772 .dump_regs = dwmac4_dump_regs,
773 .host_irq_status = dwmac4_irq_status,
774 .host_mtl_irq_status = dwmac4_irq_mtl_status,
775 .flow_ctrl = dwmac4_flow_ctrl,
777 .set_umac_addr = dwmac4_set_umac_addr,
778 .get_umac_addr = dwmac4_get_umac_addr,
779 .set_eee_mode = dwmac4_set_eee_mode,
780 .reset_eee_mode = dwmac4_reset_eee_mode,
781 .set_eee_timer = dwmac4_set_eee_timer,
782 .set_eee_pls = dwmac4_set_eee_pls,
783 .pcs_ctrl_ane = dwmac4_ctrl_ane,
784 .pcs_rane = dwmac4_rane,
785 .pcs_get_adv_lp = dwmac4_get_adv_lp,
786 .debug = dwmac4_debug,
787 .set_filter = dwmac4_set_filter,
788 .set_mac_loopback = dwmac4_set_mac_loopback,
791 const struct stmmac_ops dwmac510_ops = {
792 .core_init = dwmac4_core_init,
793 .set_mac = stmmac_dwmac4_set_mac,
794 .rx_ipc = dwmac4_rx_ipc_enable,
795 .rx_queue_enable = dwmac4_rx_queue_enable,
796 .rx_queue_prio = dwmac4_rx_queue_priority,
797 .tx_queue_prio = dwmac4_tx_queue_priority,
798 .rx_queue_routing = dwmac4_rx_queue_routing,
799 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
800 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
801 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
802 .map_mtl_to_dma = dwmac4_map_mtl_dma,
803 .config_cbs = dwmac4_config_cbs,
804 .dump_regs = dwmac4_dump_regs,
805 .host_irq_status = dwmac4_irq_status,
806 .host_mtl_irq_status = dwmac4_irq_mtl_status,
807 .flow_ctrl = dwmac4_flow_ctrl,
809 .set_umac_addr = dwmac4_set_umac_addr,
810 .get_umac_addr = dwmac4_get_umac_addr,
811 .set_eee_mode = dwmac4_set_eee_mode,
812 .reset_eee_mode = dwmac4_reset_eee_mode,
813 .set_eee_timer = dwmac4_set_eee_timer,
814 .set_eee_pls = dwmac4_set_eee_pls,
815 .pcs_ctrl_ane = dwmac4_ctrl_ane,
816 .pcs_rane = dwmac4_rane,
817 .pcs_get_adv_lp = dwmac4_get_adv_lp,
818 .debug = dwmac4_debug,
819 .set_filter = dwmac4_set_filter,
820 .safety_feat_config = dwmac5_safety_feat_config,
821 .safety_feat_irq_status = dwmac5_safety_feat_irq_status,
822 .safety_feat_dump = dwmac5_safety_feat_dump,
823 .rxp_config = dwmac5_rxp_config,
824 .flex_pps_config = dwmac5_flex_pps_config,
825 .set_mac_loopback = dwmac4_set_mac_loopback,
828 int dwmac4_setup(struct stmmac_priv *priv)
830 struct mac_device_info *mac = priv->hw;
832 dev_info(priv->device, "\tDWMAC4/5\n");
834 priv->dev->priv_flags |= IFF_UNICAST_FLT;
835 mac->pcsr = priv->ioaddr;
836 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
837 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
838 mac->mcast_bits_log2 = 0;
840 if (mac->multicast_filter_bins)
841 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
843 mac->link.duplex = GMAC_CONFIG_DM;
844 mac->link.speed10 = GMAC_CONFIG_PS;
845 mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
846 mac->link.speed1000 = 0;
847 mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
848 mac->mii.addr = GMAC_MDIO_ADDR;
849 mac->mii.data = GMAC_MDIO_DATA;
850 mac->mii.addr_shift = 21;
851 mac->mii.addr_mask = GENMASK(25, 21);
852 mac->mii.reg_shift = 16;
853 mac->mii.reg_mask = GENMASK(20, 16);
854 mac->mii.clk_csr_shift = 8;
855 mac->mii.clk_csr_mask = GENMASK(11, 8);