1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
5 * Copyright (C) 2017 Corentin Labbe <clabbe.montjoie@gmail.com>
10 #include <linux/iopoll.h>
11 #include <linux/mdio-mux.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/of_mdio.h>
16 #include <linux/of_net.h>
17 #include <linux/phy.h>
18 #include <linux/platform_device.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/regmap.h>
21 #include <linux/stmmac.h>
24 #include "stmmac_platform.h"
26 /* General notes on dwmac-sun8i:
27 * Locking: no locking is necessary in this file because all necessary locking
28 * is done in the "stmmac files"
31 /* struct emac_variant - Describe dwmac-sun8i hardware variant
32 * @default_syscon_value: The default value of the EMAC register in syscon
33 * This value is used for disabling properly EMAC
34 * and used as a good starting value in case of the
35 * boot process(uboot) leave some stuff.
36 * @syscon_field reg_field for the syscon's gmac register
37 * @soc_has_internal_phy: Does the MAC embed an internal PHY
38 * @support_mii: Does the MAC handle MII
39 * @support_rmii: Does the MAC handle RMII
40 * @support_rgmii: Does the MAC handle RGMII
42 * @rx_delay_max: Maximum raw value for RX delay chain
43 * @tx_delay_max: Maximum raw value for TX delay chain
44 * These two also indicate the bitmask for
45 * the RX and TX delay chain registers. A
46 * value of zero indicates this is not supported.
49 u32 default_syscon_value;
50 const struct reg_field *syscon_field;
51 bool soc_has_internal_phy;
59 /* struct sunxi_priv_data - hold all sunxi private data
60 * @tx_clk: reference to MAC TX clock
61 * @ephy_clk: reference to the optional EPHY clock for the internal PHY
62 * @regulator: reference to the optional regulator
63 * @rst_ephy: reference to the optional EPHY reset for the internal PHY
64 * @variant: reference to the current board variant
65 * @regmap: regmap for using the syscon
66 * @internal_phy_powered: Does the internal PHY is enabled
67 * @mux_handle: Internal pointer used by mdio-mux lib
69 struct sunxi_priv_data {
72 struct regulator *regulator;
73 struct reset_control *rst_ephy;
74 const struct emac_variant *variant;
75 struct regmap_field *regmap_field;
76 bool internal_phy_powered;
80 /* EMAC clock register @ 0x30 in the "system control" address range */
81 static const struct reg_field sun8i_syscon_reg_field = {
87 /* EMAC clock register @ 0x164 in the CCU address range */
88 static const struct reg_field sun8i_ccu_reg_field = {
94 static const struct emac_variant emac_variant_h3 = {
95 .default_syscon_value = 0x58000,
96 .syscon_field = &sun8i_syscon_reg_field,
97 .soc_has_internal_phy = true,
100 .support_rgmii = true,
105 static const struct emac_variant emac_variant_v3s = {
106 .default_syscon_value = 0x38000,
107 .syscon_field = &sun8i_syscon_reg_field,
108 .soc_has_internal_phy = true,
112 static const struct emac_variant emac_variant_a83t = {
113 .default_syscon_value = 0,
114 .syscon_field = &sun8i_syscon_reg_field,
115 .soc_has_internal_phy = false,
117 .support_rgmii = true,
122 static const struct emac_variant emac_variant_r40 = {
123 .default_syscon_value = 0,
124 .syscon_field = &sun8i_ccu_reg_field,
126 .support_rgmii = true,
130 static const struct emac_variant emac_variant_a64 = {
131 .default_syscon_value = 0,
132 .syscon_field = &sun8i_syscon_reg_field,
133 .soc_has_internal_phy = false,
135 .support_rmii = true,
136 .support_rgmii = true,
141 static const struct emac_variant emac_variant_h6 = {
142 .default_syscon_value = 0x50000,
143 .syscon_field = &sun8i_syscon_reg_field,
144 /* The "Internal PHY" of H6 is not on the die. It's on the
145 * co-packaged AC200 chip instead.
147 .soc_has_internal_phy = false,
149 .support_rmii = true,
150 .support_rgmii = true,
155 #define EMAC_BASIC_CTL0 0x00
156 #define EMAC_BASIC_CTL1 0x04
157 #define EMAC_INT_STA 0x08
158 #define EMAC_INT_EN 0x0C
159 #define EMAC_TX_CTL0 0x10
160 #define EMAC_TX_CTL1 0x14
161 #define EMAC_TX_FLOW_CTL 0x1C
162 #define EMAC_TX_DESC_LIST 0x20
163 #define EMAC_RX_CTL0 0x24
164 #define EMAC_RX_CTL1 0x28
165 #define EMAC_RX_DESC_LIST 0x34
166 #define EMAC_RX_FRM_FLT 0x38
167 #define EMAC_MDIO_CMD 0x48
168 #define EMAC_MDIO_DATA 0x4C
169 #define EMAC_MACADDR_HI(reg) (0x50 + (reg) * 8)
170 #define EMAC_MACADDR_LO(reg) (0x54 + (reg) * 8)
171 #define EMAC_TX_DMA_STA 0xB0
172 #define EMAC_TX_CUR_DESC 0xB4
173 #define EMAC_TX_CUR_BUF 0xB8
174 #define EMAC_RX_DMA_STA 0xC0
175 #define EMAC_RX_CUR_DESC 0xC4
176 #define EMAC_RX_CUR_BUF 0xC8
178 /* Use in EMAC_BASIC_CTL0 */
179 #define EMAC_DUPLEX_FULL BIT(0)
180 #define EMAC_LOOPBACK BIT(1)
181 #define EMAC_SPEED_1000 0
182 #define EMAC_SPEED_100 (0x03 << 2)
183 #define EMAC_SPEED_10 (0x02 << 2)
185 /* Use in EMAC_BASIC_CTL1 */
186 #define EMAC_BURSTLEN_SHIFT 24
188 /* Used in EMAC_RX_FRM_FLT */
189 #define EMAC_FRM_FLT_RXALL BIT(0)
190 #define EMAC_FRM_FLT_CTL BIT(13)
191 #define EMAC_FRM_FLT_MULTICAST BIT(16)
194 #define EMAC_RX_MD BIT(1)
195 #define EMAC_RX_TH_MASK GENMASK(5, 4)
196 #define EMAC_RX_TH_32 0
197 #define EMAC_RX_TH_64 (0x1 << 4)
198 #define EMAC_RX_TH_96 (0x2 << 4)
199 #define EMAC_RX_TH_128 (0x3 << 4)
200 #define EMAC_RX_DMA_EN BIT(30)
201 #define EMAC_RX_DMA_START BIT(31)
204 #define EMAC_TX_MD BIT(1)
205 #define EMAC_TX_NEXT_FRM BIT(2)
206 #define EMAC_TX_TH_MASK GENMASK(10, 8)
207 #define EMAC_TX_TH_64 0
208 #define EMAC_TX_TH_128 (0x1 << 8)
209 #define EMAC_TX_TH_192 (0x2 << 8)
210 #define EMAC_TX_TH_256 (0x3 << 8)
211 #define EMAC_TX_DMA_EN BIT(30)
212 #define EMAC_TX_DMA_START BIT(31)
214 /* Used in RX_CTL0 */
215 #define EMAC_RX_RECEIVER_EN BIT(31)
216 #define EMAC_RX_DO_CRC BIT(27)
217 #define EMAC_RX_FLOW_CTL_EN BIT(16)
219 /* Used in TX_CTL0 */
220 #define EMAC_TX_TRANSMITTER_EN BIT(31)
222 /* Used in EMAC_TX_FLOW_CTL */
223 #define EMAC_TX_FLOW_CTL_EN BIT(0)
225 /* Used in EMAC_INT_STA */
226 #define EMAC_TX_INT BIT(0)
227 #define EMAC_TX_DMA_STOP_INT BIT(1)
228 #define EMAC_TX_BUF_UA_INT BIT(2)
229 #define EMAC_TX_TIMEOUT_INT BIT(3)
230 #define EMAC_TX_UNDERFLOW_INT BIT(4)
231 #define EMAC_TX_EARLY_INT BIT(5)
232 #define EMAC_RX_INT BIT(8)
233 #define EMAC_RX_BUF_UA_INT BIT(9)
234 #define EMAC_RX_DMA_STOP_INT BIT(10)
235 #define EMAC_RX_TIMEOUT_INT BIT(11)
236 #define EMAC_RX_OVERFLOW_INT BIT(12)
237 #define EMAC_RX_EARLY_INT BIT(13)
238 #define EMAC_RGMII_STA_INT BIT(16)
240 #define MAC_ADDR_TYPE_DST BIT(31)
242 /* H3 specific bits for EPHY */
243 #define H3_EPHY_ADDR_SHIFT 20
244 #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */
245 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
246 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
247 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
248 #define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)
249 #define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1
250 #define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2
252 /* H3/A64 specific bits */
253 #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */
255 /* Generic system control EMAC_CLK bits */
256 #define SYSCON_ETXDC_SHIFT 10
257 #define SYSCON_ERXDC_SHIFT 5
258 /* EMAC PHY Interface Type */
259 #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */
260 #define SYSCON_ETCS_MASK GENMASK(1, 0)
261 #define SYSCON_ETCS_MII 0x0
262 #define SYSCON_ETCS_EXT_GMII 0x1
263 #define SYSCON_ETCS_INT_GMII 0x2
265 /* sun8i_dwmac_dma_reset() - reset the EMAC
266 * Called from stmmac via stmmac_dma_ops->reset
268 static int sun8i_dwmac_dma_reset(void __iomem *ioaddr)
270 writel(0, ioaddr + EMAC_RX_CTL1);
271 writel(0, ioaddr + EMAC_TX_CTL1);
272 writel(0, ioaddr + EMAC_RX_FRM_FLT);
273 writel(0, ioaddr + EMAC_RX_DESC_LIST);
274 writel(0, ioaddr + EMAC_TX_DESC_LIST);
275 writel(0, ioaddr + EMAC_INT_EN);
276 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
280 /* sun8i_dwmac_dma_init() - initialize the EMAC
281 * Called from stmmac via stmmac_dma_ops->init
283 static void sun8i_dwmac_dma_init(void __iomem *ioaddr,
284 struct stmmac_dma_cfg *dma_cfg, int atds)
286 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
287 writel(0x1FFFFFF, ioaddr + EMAC_INT_STA);
290 static void sun8i_dwmac_dma_init_rx(void __iomem *ioaddr,
291 struct stmmac_dma_cfg *dma_cfg,
292 dma_addr_t dma_rx_phy, u32 chan)
294 /* Write RX descriptors address */
295 writel(lower_32_bits(dma_rx_phy), ioaddr + EMAC_RX_DESC_LIST);
298 static void sun8i_dwmac_dma_init_tx(void __iomem *ioaddr,
299 struct stmmac_dma_cfg *dma_cfg,
300 dma_addr_t dma_tx_phy, u32 chan)
302 /* Write TX descriptors address */
303 writel(lower_32_bits(dma_tx_phy), ioaddr + EMAC_TX_DESC_LIST);
306 /* sun8i_dwmac_dump_regs() - Dump EMAC address space
307 * Called from stmmac_dma_ops->dump_regs
310 static void sun8i_dwmac_dump_regs(void __iomem *ioaddr, u32 *reg_space)
314 for (i = 0; i < 0xC8; i += 4) {
315 if (i == 0x32 || i == 0x3C)
317 reg_space[i / 4] = readl(ioaddr + i);
321 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space
322 * Called from stmmac_ops->dump_regs
325 static void sun8i_dwmac_dump_mac_regs(struct mac_device_info *hw,
329 void __iomem *ioaddr = hw->pcsr;
331 for (i = 0; i < 0xC8; i += 4) {
332 if (i == 0x32 || i == 0x3C)
334 reg_space[i / 4] = readl(ioaddr + i);
338 static void sun8i_dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan)
340 writel(EMAC_RX_INT | EMAC_TX_INT, ioaddr + EMAC_INT_EN);
343 static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan)
345 writel(0, ioaddr + EMAC_INT_EN);
348 static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
352 v = readl(ioaddr + EMAC_TX_CTL1);
353 v |= EMAC_TX_DMA_START;
355 writel(v, ioaddr + EMAC_TX_CTL1);
358 static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
362 v = readl(ioaddr + EMAC_TX_CTL1);
363 v |= EMAC_TX_DMA_START;
365 writel(v, ioaddr + EMAC_TX_CTL1);
368 static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
372 v = readl(ioaddr + EMAC_TX_CTL1);
373 v &= ~EMAC_TX_DMA_EN;
374 writel(v, ioaddr + EMAC_TX_CTL1);
377 static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
381 v = readl(ioaddr + EMAC_RX_CTL1);
382 v |= EMAC_RX_DMA_START;
384 writel(v, ioaddr + EMAC_RX_CTL1);
387 static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
391 v = readl(ioaddr + EMAC_RX_CTL1);
392 v &= ~EMAC_RX_DMA_EN;
393 writel(v, ioaddr + EMAC_RX_CTL1);
396 static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,
397 struct stmmac_extra_stats *x, u32 chan)
402 v = readl(ioaddr + EMAC_INT_STA);
404 if (v & EMAC_TX_INT) {
406 x->tx_normal_irq_n++;
409 if (v & EMAC_TX_DMA_STOP_INT)
410 x->tx_process_stopped_irq++;
412 if (v & EMAC_TX_BUF_UA_INT)
413 x->tx_process_stopped_irq++;
415 if (v & EMAC_TX_TIMEOUT_INT)
416 ret |= tx_hard_error;
418 if (v & EMAC_TX_UNDERFLOW_INT) {
419 ret |= tx_hard_error;
420 x->tx_undeflow_irq++;
423 if (v & EMAC_TX_EARLY_INT)
426 if (v & EMAC_RX_INT) {
428 x->rx_normal_irq_n++;
431 if (v & EMAC_RX_BUF_UA_INT)
432 x->rx_buf_unav_irq++;
434 if (v & EMAC_RX_DMA_STOP_INT)
435 x->rx_process_stopped_irq++;
437 if (v & EMAC_RX_TIMEOUT_INT)
438 ret |= tx_hard_error;
440 if (v & EMAC_RX_OVERFLOW_INT) {
441 ret |= tx_hard_error;
442 x->rx_overflow_irq++;
445 if (v & EMAC_RX_EARLY_INT)
448 if (v & EMAC_RGMII_STA_INT)
451 writel(v, ioaddr + EMAC_INT_STA);
456 static void sun8i_dwmac_dma_operation_mode_rx(void __iomem *ioaddr, int mode,
457 u32 channel, int fifosz, u8 qmode)
461 v = readl(ioaddr + EMAC_RX_CTL1);
462 if (mode == SF_DMA_MODE) {
466 v &= ~EMAC_RX_TH_MASK;
476 writel(v, ioaddr + EMAC_RX_CTL1);
479 static void sun8i_dwmac_dma_operation_mode_tx(void __iomem *ioaddr, int mode,
480 u32 channel, int fifosz, u8 qmode)
484 v = readl(ioaddr + EMAC_TX_CTL1);
485 if (mode == SF_DMA_MODE) {
487 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original
489 * "Operating on second frame increase the performance
490 * especially when transmit store-and-forward is used."
492 v |= EMAC_TX_NEXT_FRM;
495 v &= ~EMAC_TX_TH_MASK;
505 writel(v, ioaddr + EMAC_TX_CTL1);
508 static const struct stmmac_dma_ops sun8i_dwmac_dma_ops = {
509 .reset = sun8i_dwmac_dma_reset,
510 .init = sun8i_dwmac_dma_init,
511 .init_rx_chan = sun8i_dwmac_dma_init_rx,
512 .init_tx_chan = sun8i_dwmac_dma_init_tx,
513 .dump_regs = sun8i_dwmac_dump_regs,
514 .dma_rx_mode = sun8i_dwmac_dma_operation_mode_rx,
515 .dma_tx_mode = sun8i_dwmac_dma_operation_mode_tx,
516 .enable_dma_transmission = sun8i_dwmac_enable_dma_transmission,
517 .enable_dma_irq = sun8i_dwmac_enable_dma_irq,
518 .disable_dma_irq = sun8i_dwmac_disable_dma_irq,
519 .start_tx = sun8i_dwmac_dma_start_tx,
520 .stop_tx = sun8i_dwmac_dma_stop_tx,
521 .start_rx = sun8i_dwmac_dma_start_rx,
522 .stop_rx = sun8i_dwmac_dma_stop_rx,
523 .dma_interrupt = sun8i_dwmac_dma_interrupt,
526 static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
528 struct sunxi_priv_data *gmac = priv;
531 if (gmac->regulator) {
532 ret = regulator_enable(gmac->regulator);
534 dev_err(&pdev->dev, "Fail to enable regulator\n");
539 ret = clk_prepare_enable(gmac->tx_clk);
542 regulator_disable(gmac->regulator);
543 dev_err(&pdev->dev, "Could not enable AHB clock\n");
550 static void sun8i_dwmac_core_init(struct mac_device_info *hw,
551 struct net_device *dev)
553 void __iomem *ioaddr = hw->pcsr;
556 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */
557 writel(v, ioaddr + EMAC_BASIC_CTL1);
560 static void sun8i_dwmac_set_mac(void __iomem *ioaddr, bool enable)
564 t = readl(ioaddr + EMAC_TX_CTL0);
565 r = readl(ioaddr + EMAC_RX_CTL0);
567 t |= EMAC_TX_TRANSMITTER_EN;
568 r |= EMAC_RX_RECEIVER_EN;
570 t &= ~EMAC_TX_TRANSMITTER_EN;
571 r &= ~EMAC_RX_RECEIVER_EN;
573 writel(t, ioaddr + EMAC_TX_CTL0);
574 writel(r, ioaddr + EMAC_RX_CTL0);
577 /* Set MAC address at slot reg_n
578 * All slot > 0 need to be enabled with MAC_ADDR_TYPE_DST
579 * If addr is NULL, clear the slot
581 static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
585 void __iomem *ioaddr = hw->pcsr;
589 writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
593 stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
594 EMAC_MACADDR_LO(reg_n));
596 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
597 v |= MAC_ADDR_TYPE_DST;
598 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
602 static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
606 void __iomem *ioaddr = hw->pcsr;
608 stmmac_get_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
609 EMAC_MACADDR_LO(reg_n));
612 /* caution this function must return non 0 to work */
613 static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
615 void __iomem *ioaddr = hw->pcsr;
618 v = readl(ioaddr + EMAC_RX_CTL0);
620 writel(v, ioaddr + EMAC_RX_CTL0);
625 static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
626 struct net_device *dev)
628 void __iomem *ioaddr = hw->pcsr;
631 struct netdev_hw_addr *ha;
632 int macaddrs = netdev_uc_count(dev) + netdev_mc_count(dev) + 1;
634 v = EMAC_FRM_FLT_CTL;
636 if (dev->flags & IFF_PROMISC) {
637 v = EMAC_FRM_FLT_RXALL;
638 } else if (dev->flags & IFF_ALLMULTI) {
639 v |= EMAC_FRM_FLT_MULTICAST;
640 } else if (macaddrs <= hw->unicast_filter_entries) {
641 if (!netdev_mc_empty(dev)) {
642 netdev_for_each_mc_addr(ha, dev) {
643 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
647 if (!netdev_uc_empty(dev)) {
648 netdev_for_each_uc_addr(ha, dev) {
649 sun8i_dwmac_set_umac_addr(hw, ha->addr, i);
654 if (!(readl(ioaddr + EMAC_RX_FRM_FLT) & EMAC_FRM_FLT_RXALL))
655 netdev_info(dev, "Too many address, switching to promiscuous\n");
656 v = EMAC_FRM_FLT_RXALL;
659 /* Disable unused address filter slots */
660 while (i < hw->unicast_filter_entries)
661 sun8i_dwmac_set_umac_addr(hw, NULL, i++);
663 writel(v, ioaddr + EMAC_RX_FRM_FLT);
666 static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
667 unsigned int duplex, unsigned int fc,
668 unsigned int pause_time, u32 tx_cnt)
670 void __iomem *ioaddr = hw->pcsr;
673 v = readl(ioaddr + EMAC_RX_CTL0);
675 v |= EMAC_RX_FLOW_CTL_EN;
677 v &= ~EMAC_RX_FLOW_CTL_EN;
678 writel(v, ioaddr + EMAC_RX_CTL0);
680 v = readl(ioaddr + EMAC_TX_FLOW_CTL);
682 v |= EMAC_TX_FLOW_CTL_EN;
684 v &= ~EMAC_TX_FLOW_CTL_EN;
685 writel(v, ioaddr + EMAC_TX_FLOW_CTL);
688 static int sun8i_dwmac_reset(struct stmmac_priv *priv)
693 v = readl(priv->ioaddr + EMAC_BASIC_CTL1);
694 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1);
696 /* The timeout was previoulsy set to 10ms, but some board (OrangePI0)
697 * need more if no cable plugged. 100ms seems OK
699 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v,
700 !(v & 0x01), 100, 100000);
703 dev_err(priv->device, "EMAC reset timeout\n");
709 /* Search in mdio-mux node for internal PHY node and get its clk/reset */
710 static int get_ephy_nodes(struct stmmac_priv *priv)
712 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
713 struct device_node *mdio_mux, *iphynode;
714 struct device_node *mdio_internal;
717 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
719 dev_err(priv->device, "Cannot get mdio-mux node\n");
723 mdio_internal = of_get_compatible_child(mdio_mux,
724 "allwinner,sun8i-h3-mdio-internal");
725 of_node_put(mdio_mux);
726 if (!mdio_internal) {
727 dev_err(priv->device, "Cannot get internal_mdio node\n");
731 /* Seek for internal PHY */
732 for_each_child_of_node(mdio_internal, iphynode) {
733 gmac->ephy_clk = of_clk_get(iphynode, 0);
734 if (IS_ERR(gmac->ephy_clk))
736 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL);
737 if (IS_ERR(gmac->rst_ephy)) {
738 ret = PTR_ERR(gmac->rst_ephy);
739 if (ret == -EPROBE_DEFER) {
740 of_node_put(iphynode);
741 of_node_put(mdio_internal);
746 dev_info(priv->device, "Found internal PHY node\n");
747 of_node_put(iphynode);
748 of_node_put(mdio_internal);
752 of_node_put(mdio_internal);
756 static int sun8i_dwmac_power_internal_phy(struct stmmac_priv *priv)
758 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
761 if (gmac->internal_phy_powered) {
762 dev_warn(priv->device, "Internal PHY already powered\n");
766 dev_info(priv->device, "Powering internal PHY\n");
767 ret = clk_prepare_enable(gmac->ephy_clk);
769 dev_err(priv->device, "Cannot enable internal PHY\n");
773 /* Make sure the EPHY is properly reseted, as U-Boot may leave
774 * it at deasserted state, and thus it may fail to reset EMAC.
776 reset_control_assert(gmac->rst_ephy);
778 ret = reset_control_deassert(gmac->rst_ephy);
780 dev_err(priv->device, "Cannot deassert internal phy\n");
781 clk_disable_unprepare(gmac->ephy_clk);
785 gmac->internal_phy_powered = true;
790 static int sun8i_dwmac_unpower_internal_phy(struct sunxi_priv_data *gmac)
792 if (!gmac->internal_phy_powered)
795 clk_disable_unprepare(gmac->ephy_clk);
796 reset_control_assert(gmac->rst_ephy);
797 gmac->internal_phy_powered = false;
801 /* MDIO multiplexing switch function
802 * This function is called by the mdio-mux layer when it thinks the mdio bus
803 * multiplexer needs to switch.
804 * 'current_child' is the current value of the mux register
805 * 'desired_child' is the value of the 'reg' property of the target child MDIO
807 * The first time this function is called, current_child == -1.
808 * If current_child == desired_child, then the mux is already set to the
811 static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
814 struct stmmac_priv *priv = data;
815 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
818 bool need_power_ephy = false;
820 if (current_child ^ desired_child) {
821 regmap_field_read(gmac->regmap_field, ®);
822 switch (desired_child) {
823 case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:
824 dev_info(priv->device, "Switch mux to internal PHY");
825 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;
827 need_power_ephy = true;
829 case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:
830 dev_info(priv->device, "Switch mux to external PHY");
831 val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;
832 need_power_ephy = false;
835 dev_err(priv->device, "Invalid child ID %x\n",
839 regmap_field_write(gmac->regmap_field, val);
840 if (need_power_ephy) {
841 ret = sun8i_dwmac_power_internal_phy(priv);
845 sun8i_dwmac_unpower_internal_phy(gmac);
847 /* After changing syscon value, the MAC need reset or it will
848 * use the last value (and so the last PHY set).
850 ret = sun8i_dwmac_reset(priv);
855 static int sun8i_dwmac_register_mdio_mux(struct stmmac_priv *priv)
858 struct device_node *mdio_mux;
859 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
861 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux");
865 ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn,
866 &gmac->mux_handle, priv, priv->mii);
870 static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
872 struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
873 struct device_node *node = priv->device->of_node;
877 ret = regmap_field_read(gmac->regmap_field, &val);
879 dev_err(priv->device, "Fail to read from regmap field.\n");
883 reg = gmac->variant->default_syscon_value;
885 dev_warn(priv->device,
886 "Current syscon value is not the default %x (expect %x)\n",
889 if (gmac->variant->soc_has_internal_phy) {
890 if (of_property_read_bool(node, "allwinner,leds-active-low"))
891 reg |= H3_EPHY_LED_POL;
893 reg &= ~H3_EPHY_LED_POL;
895 /* Force EPHY xtal frequency to 24MHz. */
896 reg |= H3_EPHY_CLK_SEL;
898 ret = of_mdio_parse_addr(priv->device, priv->plat->phy_node);
900 dev_err(priv->device, "Could not parse MDIO addr\n");
903 /* of_mdio_parse_addr returns a valid (0 ~ 31) PHY
904 * address. No need to mask it again.
906 reg |= 1 << H3_EPHY_ADDR_SHIFT;
908 /* For SoCs without internal PHY the PHY selection bit should be
909 * set to 0 (external PHY).
911 reg &= ~H3_EPHY_SELECT;
914 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {
916 dev_err(priv->device, "tx-delay must be a multiple of 100\n");
920 dev_dbg(priv->device, "set tx-delay to %x\n", val);
921 if (val <= gmac->variant->tx_delay_max) {
922 reg &= ~(gmac->variant->tx_delay_max <<
924 reg |= (val << SYSCON_ETXDC_SHIFT);
926 dev_err(priv->device, "Invalid TX clock delay: %d\n",
932 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) {
934 dev_err(priv->device, "rx-delay must be a multiple of 100\n");
938 dev_dbg(priv->device, "set rx-delay to %x\n", val);
939 if (val <= gmac->variant->rx_delay_max) {
940 reg &= ~(gmac->variant->rx_delay_max <<
942 reg |= (val << SYSCON_ERXDC_SHIFT);
944 dev_err(priv->device, "Invalid RX clock delay: %d\n",
950 /* Clear interface mode bits */
951 reg &= ~(SYSCON_ETCS_MASK | SYSCON_EPIT);
952 if (gmac->variant->support_rmii)
953 reg &= ~SYSCON_RMII_EN;
955 switch (priv->plat->interface) {
956 case PHY_INTERFACE_MODE_MII:
959 case PHY_INTERFACE_MODE_RGMII:
960 reg |= SYSCON_EPIT | SYSCON_ETCS_INT_GMII;
962 case PHY_INTERFACE_MODE_RMII:
963 reg |= SYSCON_RMII_EN | SYSCON_ETCS_EXT_GMII;
966 dev_err(priv->device, "Unsupported interface mode: %s",
967 phy_modes(priv->plat->interface));
971 regmap_field_write(gmac->regmap_field, reg);
976 static void sun8i_dwmac_unset_syscon(struct sunxi_priv_data *gmac)
978 u32 reg = gmac->variant->default_syscon_value;
980 regmap_field_write(gmac->regmap_field, reg);
983 static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
985 struct sunxi_priv_data *gmac = priv;
987 if (gmac->variant->soc_has_internal_phy) {
988 /* sun8i_dwmac_exit could be called with mdiomux uninit */
989 if (gmac->mux_handle)
990 mdio_mux_uninit(gmac->mux_handle);
991 if (gmac->internal_phy_powered)
992 sun8i_dwmac_unpower_internal_phy(gmac);
995 sun8i_dwmac_unset_syscon(gmac);
997 reset_control_put(gmac->rst_ephy);
999 clk_disable_unprepare(gmac->tx_clk);
1001 if (gmac->regulator)
1002 regulator_disable(gmac->regulator);
1005 static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
1007 u32 value = readl(ioaddr + EMAC_BASIC_CTL0);
1010 value |= EMAC_LOOPBACK;
1012 value &= ~EMAC_LOOPBACK;
1014 writel(value, ioaddr + EMAC_BASIC_CTL0);
1017 static const struct stmmac_ops sun8i_dwmac_ops = {
1018 .core_init = sun8i_dwmac_core_init,
1019 .set_mac = sun8i_dwmac_set_mac,
1020 .dump_regs = sun8i_dwmac_dump_mac_regs,
1021 .rx_ipc = sun8i_dwmac_rx_ipc_enable,
1022 .set_filter = sun8i_dwmac_set_filter,
1023 .flow_ctrl = sun8i_dwmac_flow_ctrl,
1024 .set_umac_addr = sun8i_dwmac_set_umac_addr,
1025 .get_umac_addr = sun8i_dwmac_get_umac_addr,
1026 .set_mac_loopback = sun8i_dwmac_set_mac_loopback,
1029 static struct mac_device_info *sun8i_dwmac_setup(void *ppriv)
1031 struct mac_device_info *mac;
1032 struct stmmac_priv *priv = ppriv;
1035 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL);
1039 ret = sun8i_dwmac_set_syscon(priv);
1043 mac->pcsr = priv->ioaddr;
1044 mac->mac = &sun8i_dwmac_ops;
1045 mac->dma = &sun8i_dwmac_dma_ops;
1047 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1049 /* The loopback bit seems to be re-set when link change
1050 * Simply mask it each time
1051 * Speed 10/100/1000 are set in BIT(2)/BIT(3)
1053 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK;
1054 mac->link.speed10 = EMAC_SPEED_10;
1055 mac->link.speed100 = EMAC_SPEED_100;
1056 mac->link.speed1000 = EMAC_SPEED_1000;
1057 mac->link.duplex = EMAC_DUPLEX_FULL;
1058 mac->mii.addr = EMAC_MDIO_CMD;
1059 mac->mii.data = EMAC_MDIO_DATA;
1060 mac->mii.reg_shift = 4;
1061 mac->mii.reg_mask = GENMASK(8, 4);
1062 mac->mii.addr_shift = 12;
1063 mac->mii.addr_mask = GENMASK(16, 12);
1064 mac->mii.clk_csr_shift = 20;
1065 mac->mii.clk_csr_mask = GENMASK(22, 20);
1066 mac->unicast_filter_entries = 8;
1068 /* Synopsys Id is not available */
1069 priv->synopsys_id = 0;
1074 static struct regmap *sun8i_dwmac_get_syscon_from_dev(struct device_node *node)
1076 struct device_node *syscon_node;
1077 struct platform_device *syscon_pdev;
1078 struct regmap *regmap = NULL;
1080 syscon_node = of_parse_phandle(node, "syscon", 0);
1082 return ERR_PTR(-ENODEV);
1084 syscon_pdev = of_find_device_by_node(syscon_node);
1086 /* platform device might not be probed yet */
1087 regmap = ERR_PTR(-EPROBE_DEFER);
1091 /* If no regmap is found then the other device driver is at fault */
1092 regmap = dev_get_regmap(&syscon_pdev->dev, NULL);
1094 regmap = ERR_PTR(-EINVAL);
1096 platform_device_put(syscon_pdev);
1098 of_node_put(syscon_node);
1102 static int sun8i_dwmac_probe(struct platform_device *pdev)
1104 struct plat_stmmacenet_data *plat_dat;
1105 struct stmmac_resources stmmac_res;
1106 struct sunxi_priv_data *gmac;
1107 struct device *dev = &pdev->dev;
1109 struct stmmac_priv *priv;
1110 struct net_device *ndev;
1111 struct regmap *regmap;
1113 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1117 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
1118 if (IS_ERR(plat_dat))
1119 return PTR_ERR(plat_dat);
1121 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
1125 gmac->variant = of_device_get_match_data(&pdev->dev);
1126 if (!gmac->variant) {
1127 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n");
1131 gmac->tx_clk = devm_clk_get(dev, "stmmaceth");
1132 if (IS_ERR(gmac->tx_clk)) {
1133 dev_err(dev, "Could not get TX clock\n");
1134 return PTR_ERR(gmac->tx_clk);
1137 /* Optional regulator for PHY */
1138 gmac->regulator = devm_regulator_get_optional(dev, "phy");
1139 if (IS_ERR(gmac->regulator)) {
1140 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
1141 return -EPROBE_DEFER;
1142 dev_info(dev, "No regulator found\n");
1143 gmac->regulator = NULL;
1146 /* The "GMAC clock control" register might be located in the
1147 * CCU address range (on the R40), or the system control address
1148 * range (on most other sun8i and later SoCs).
1150 * The former controls most if not all clocks in the SoC. The
1151 * latter has an SoC identification register, and on some SoCs,
1152 * controls to map device specific SRAM to either the intended
1153 * peripheral, or the CPU address space.
1155 * In either case, there should be a coordinated and restricted
1156 * method of accessing the register needed here. This is done by
1157 * having the device export a custom regmap, instead of a generic
1158 * syscon, which grants all access to all registers.
1160 * To support old device trees, we fall back to using the syscon
1161 * interface if possible.
1163 regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node);
1165 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1167 if (IS_ERR(regmap)) {
1168 ret = PTR_ERR(regmap);
1169 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret);
1173 gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
1174 *gmac->variant->syscon_field);
1175 if (IS_ERR(gmac->regmap_field)) {
1176 ret = PTR_ERR(gmac->regmap_field);
1177 dev_err(dev, "Unable to map syscon register: %d\n", ret);
1181 ret = of_get_phy_mode(dev->of_node);
1184 plat_dat->interface = ret;
1186 /* platform data specifying hardware features and callbacks.
1187 * hardware features were copied from Allwinner drivers.
1189 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
1190 plat_dat->tx_coe = 1;
1191 plat_dat->has_sun8i = true;
1192 plat_dat->bsp_priv = gmac;
1193 plat_dat->init = sun8i_dwmac_init;
1194 plat_dat->exit = sun8i_dwmac_exit;
1195 plat_dat->setup = sun8i_dwmac_setup;
1197 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv);
1201 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1205 ndev = dev_get_drvdata(&pdev->dev);
1206 priv = netdev_priv(ndev);
1207 /* The mux must be registered after parent MDIO
1208 * so after stmmac_dvr_probe()
1210 if (gmac->variant->soc_has_internal_phy) {
1211 ret = get_ephy_nodes(priv);
1214 ret = sun8i_dwmac_register_mdio_mux(priv);
1216 dev_err(&pdev->dev, "Failed to register mux\n");
1220 ret = sun8i_dwmac_reset(priv);
1227 sun8i_dwmac_unset_syscon(gmac);
1229 sun8i_dwmac_exit(pdev, plat_dat->bsp_priv);
1233 static const struct of_device_id sun8i_dwmac_match[] = {
1234 { .compatible = "allwinner,sun8i-h3-emac",
1235 .data = &emac_variant_h3 },
1236 { .compatible = "allwinner,sun8i-v3s-emac",
1237 .data = &emac_variant_v3s },
1238 { .compatible = "allwinner,sun8i-a83t-emac",
1239 .data = &emac_variant_a83t },
1240 { .compatible = "allwinner,sun8i-r40-gmac",
1241 .data = &emac_variant_r40 },
1242 { .compatible = "allwinner,sun50i-a64-emac",
1243 .data = &emac_variant_a64 },
1244 { .compatible = "allwinner,sun50i-h6-emac",
1245 .data = &emac_variant_h6 },
1248 MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
1250 static struct platform_driver sun8i_dwmac_driver = {
1251 .probe = sun8i_dwmac_probe,
1252 .remove = stmmac_pltfr_remove,
1254 .name = "dwmac-sun8i",
1255 .pm = &stmmac_pltfr_pm_ops,
1256 .of_match_table = sun8i_dwmac_match,
1259 module_platform_driver(sun8i_dwmac_driver);
1261 MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>");
1262 MODULE_DESCRIPTION("Allwinner sun8i DWMAC specific glue layer");
1263 MODULE_LICENSE("GPL");