drivers/net/ethernet/realtek/r8169_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/pci.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/phy.h>
  21 #include <linux/if_vlan.h>
  22 #include <linux/crc32.h>
  23 #include <linux/in.h>
  24 #include <linux/io.h>
  25 #include <linux/ip.h>
  26 #include <linux/tcp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/ipv6.h>
  32 #include <net/ip6_checksum.h>
  33
  34 #include "r8169_firmware.h"
  35
  36 #define MODULENAME "r8169"
  37
  38 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48 #define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53 #define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54 #define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55 #define FIRMWARE_8168FP_3       "rtl_nic/rtl8168fp-3.fw"
  56 #define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  57 #define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  58 #define FIRMWARE_8125A_3        "rtl_nic/rtl8125a-3.fw"
  59
  60 #define R8169_MSG_DEFAULT \
  61         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  62
  63 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  64    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  65 #define MC_FILTER_LIMIT 32
  66
  67 #define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  68 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  69
  70 #define R8169_REGS_SIZE         256
  71 #define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  72 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  73 #define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  74 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  75 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  76
  77 #define RTL_CFG_NO_GBIT 1
  78
  79 /* write/read MMIO register */
  80 #define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  83 #define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  84 #define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  85 #define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  86
  87 enum mac_version {
  88         /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
  89         RTL_GIGA_MAC_VER_02,
  90         RTL_GIGA_MAC_VER_03,
  91         RTL_GIGA_MAC_VER_04,
  92         RTL_GIGA_MAC_VER_05,
  93         RTL_GIGA_MAC_VER_06,
  94         RTL_GIGA_MAC_VER_07,
  95         RTL_GIGA_MAC_VER_08,
  96         RTL_GIGA_MAC_VER_09,
  97         RTL_GIGA_MAC_VER_10,
  98         RTL_GIGA_MAC_VER_11,
  99         RTL_GIGA_MAC_VER_12,
 100         RTL_GIGA_MAC_VER_13,
 101         RTL_GIGA_MAC_VER_14,
 102         RTL_GIGA_MAC_VER_15,
 103         RTL_GIGA_MAC_VER_16,
 104         RTL_GIGA_MAC_VER_17,
 105         RTL_GIGA_MAC_VER_18,
 106         RTL_GIGA_MAC_VER_19,
 107         RTL_GIGA_MAC_VER_20,
 108         RTL_GIGA_MAC_VER_21,
 109         RTL_GIGA_MAC_VER_22,
 110         RTL_GIGA_MAC_VER_23,
 111         RTL_GIGA_MAC_VER_24,
 112         RTL_GIGA_MAC_VER_25,
 113         RTL_GIGA_MAC_VER_26,
 114         RTL_GIGA_MAC_VER_27,
 115         RTL_GIGA_MAC_VER_28,
 116         RTL_GIGA_MAC_VER_29,
 117         RTL_GIGA_MAC_VER_30,
 118         RTL_GIGA_MAC_VER_31,
 119         RTL_GIGA_MAC_VER_32,
 120         RTL_GIGA_MAC_VER_33,
 121         RTL_GIGA_MAC_VER_34,
 122         RTL_GIGA_MAC_VER_35,
 123         RTL_GIGA_MAC_VER_36,
 124         RTL_GIGA_MAC_VER_37,
 125         RTL_GIGA_MAC_VER_38,
 126         RTL_GIGA_MAC_VER_39,
 127         RTL_GIGA_MAC_VER_40,
 128         RTL_GIGA_MAC_VER_41,
 129         RTL_GIGA_MAC_VER_42,
 130         RTL_GIGA_MAC_VER_43,
 131         RTL_GIGA_MAC_VER_44,
 132         RTL_GIGA_MAC_VER_45,
 133         RTL_GIGA_MAC_VER_46,
 134         RTL_GIGA_MAC_VER_47,
 135         RTL_GIGA_MAC_VER_48,
 136         RTL_GIGA_MAC_VER_49,
 137         RTL_GIGA_MAC_VER_50,
 138         RTL_GIGA_MAC_VER_51,
 139         RTL_GIGA_MAC_VER_52,
 140         RTL_GIGA_MAC_VER_60,
 141         RTL_GIGA_MAC_VER_61,
 142         RTL_GIGA_MAC_NONE
 143 };
 144
 145 #define JUMBO_1K        ETH_DATA_LEN
 146 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 147 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 148 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 149 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 150
 151 static const struct {
 152         const char *name;
 153         const char *fw_name;
 154 } rtl_chip_infos[] = {
 155         /* PCI devices. */
 156         [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 157         [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 158         [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 159         [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 160         [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 161         /* PCI-E devices. */
 162         [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 163         [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 164         [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 165         [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 166         [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 167         [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 168         [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 169         [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 170         [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 171         [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 172         [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 173         [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 174         [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 175         [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 176         [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 177         [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 178         [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 179         [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 180         [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 181         [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 182         [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 183         [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 184         [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 185         [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 186         [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 187         [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 188         [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 189         [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 190         [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 191         [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 192         [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 193         [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 194         [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 195         [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 196         [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 197         [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 198         [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 199         [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 200         [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 201         [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 202         [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 203         [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 204         [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 205         [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 206         [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 207         [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
 208         [RTL_GIGA_MAC_VER_60] = {"RTL8125"                              },
 209         [RTL_GIGA_MAC_VER_61] = {"RTL8125",             FIRMWARE_8125A_3},
 210 };
 211
 212 static const struct pci_device_id rtl8169_pci_tbl[] = {
 213         { PCI_VDEVICE(REALTEK,  0x2502) },
 214         { PCI_VDEVICE(REALTEK,  0x2600) },
 215         { PCI_VDEVICE(REALTEK,  0x8129) },
 216         { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 217         { PCI_VDEVICE(REALTEK,  0x8161) },
 218         { PCI_VDEVICE(REALTEK,  0x8167) },
 219         { PCI_VDEVICE(REALTEK,  0x8168) },
 220         { PCI_VDEVICE(NCUBE,    0x8168) },
 221         { PCI_VDEVICE(REALTEK,  0x8169) },
 222         { PCI_VENDOR_ID_DLINK,  0x4300,
 223                 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 224         { PCI_VDEVICE(DLINK,    0x4300) },
 225         { PCI_VDEVICE(DLINK,    0x4302) },
 226         { PCI_VDEVICE(AT,       0xc107) },
 227         { PCI_VDEVICE(USR,      0x0116) },
 228         { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 229         { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 230         { PCI_VDEVICE(REALTEK,  0x8125) },
 231         { PCI_VDEVICE(REALTEK,  0x3000) },
 232         {}
 233 };
 234
 235 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 236
 237 static struct {
 238         u32 msg_enable;
 239 } debug = { -1 };
 240
 241 enum rtl_registers {
 242         MAC0            = 0,    /* Ethernet hardware address. */
 243         MAC4            = 4,
 244         MAR0            = 8,    /* Multicast filter. */
 245         CounterAddrLow          = 0x10,
 246         CounterAddrHigh         = 0x14,
 247         TxDescStartAddrLow      = 0x20,
 248         TxDescStartAddrHigh     = 0x24,
 249         TxHDescStartAddrLow     = 0x28,
 250         TxHDescStartAddrHigh    = 0x2c,
 251         FLASH           = 0x30,
 252         ERSR            = 0x36,
 253         ChipCmd         = 0x37,
 254         TxPoll          = 0x38,
 255         IntrMask        = 0x3c,
 256         IntrStatus      = 0x3e,
 257
 258         TxConfig        = 0x40,
 259 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 260 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 261
 262         RxConfig        = 0x44,
 263 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 264 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 265 #define RXCFG_FIFO_SHIFT                13
 266                                         /* No threshold before first PCI xfer */
 267 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 268 #define RX_EARLY_OFF                    (1 << 11)
 269 #define RXCFG_DMA_SHIFT                 8
 270                                         /* Unlimited maximum PCI burst. */
 271 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 272
 273         RxMissed        = 0x4c,
 274         Cfg9346         = 0x50,
 275         Config0         = 0x51,
 276         Config1         = 0x52,
 277         Config2         = 0x53,
 278 #define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 279
 280         Config3         = 0x54,
 281         Config4         = 0x55,
 282         Config5         = 0x56,
 283         PHYAR           = 0x60,
 284         PHYstatus       = 0x6c,
 285         RxMaxSize       = 0xda,
 286         CPlusCmd        = 0xe0,
 287         IntrMitigate    = 0xe2,
 288
 289 #define RTL_COALESCE_MASK       0x0f
 290 #define RTL_COALESCE_SHIFT      4
 291 #define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 292 #define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 293
 294         RxDescAddrLow   = 0xe4,
 295         RxDescAddrHigh  = 0xe8,
 296         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 297
 298 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 299
 300         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 301
 302 #define TxPacketMax     (8064 >> 7)
 303 #define EarlySize       0x27
 304
 305         FuncEvent       = 0xf0,
 306         FuncEventMask   = 0xf4,
 307         FuncPresetState = 0xf8,
 308         IBCR0           = 0xf8,
 309         IBCR2           = 0xf9,
 310         IBIMR0          = 0xfa,
 311         IBISR0          = 0xfb,
 312         FuncForceEvent  = 0xfc,
 313 };
 314
 315 enum rtl8168_8101_registers {
 316         CSIDR                   = 0x64,
 317         CSIAR                   = 0x68,
 318 #define CSIAR_FLAG                      0x80000000
 319 #define CSIAR_WRITE_CMD                 0x80000000
 320 #define CSIAR_BYTE_ENABLE               0x0000f000
 321 #define CSIAR_ADDR_MASK                 0x00000fff
 322         PMCH                    = 0x6f,
 323         EPHYAR                  = 0x80,
 324 #define EPHYAR_FLAG                     0x80000000
 325 #define EPHYAR_WRITE_CMD                0x80000000
 326 #define EPHYAR_REG_MASK                 0x1f
 327 #define EPHYAR_REG_SHIFT                16
 328 #define EPHYAR_DATA_MASK                0xffff
 329         DLLPR                   = 0xd0,
 330 #define PFM_EN                          (1 << 6)
 331 #define TX_10M_PS_EN                    (1 << 7)
 332         DBG_REG                 = 0xd1,
 333 #define FIX_NAK_1                       (1 << 4)
 334 #define FIX_NAK_2                       (1 << 3)
 335         TWSI                    = 0xd2,
 336         MCU                     = 0xd3,
 337 #define NOW_IS_OOB                      (1 << 7)
 338 #define TX_EMPTY                        (1 << 5)
 339 #define RX_EMPTY                        (1 << 4)
 340 #define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 341 #define EN_NDP                          (1 << 3)
 342 #define EN_OOB_RESET                    (1 << 2)
 343 #define LINK_LIST_RDY                   (1 << 1)
 344         EFUSEAR                 = 0xdc,
 345 #define EFUSEAR_FLAG                    0x80000000
 346 #define EFUSEAR_WRITE_CMD               0x80000000
 347 #define EFUSEAR_READ_CMD                0x00000000
 348 #define EFUSEAR_REG_MASK                0x03ff
 349 #define EFUSEAR_REG_SHIFT               8
 350 #define EFUSEAR_DATA_MASK               0xff
 351         MISC_1                  = 0xf2,
 352 #define PFM_D3COLD_EN                   (1 << 6)
 353 };
 354
 355 enum rtl8168_registers {
 356         LED_FREQ                = 0x1a,
 357         EEE_LED                 = 0x1b,
 358         ERIDR                   = 0x70,
 359         ERIAR                   = 0x74,
 360 #define ERIAR_FLAG                      0x80000000
 361 #define ERIAR_WRITE_CMD                 0x80000000
 362 #define ERIAR_READ_CMD                  0x00000000
 363 #define ERIAR_ADDR_BYTE_ALIGN           4
 364 #define ERIAR_TYPE_SHIFT                16
 365 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 366 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 367 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 368 #define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 369 #define ERIAR_MASK_SHIFT                12
 370 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 371 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 372 #define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 373 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 374 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 375         EPHY_RXER_NUM           = 0x7c,
 376         OCPDR                   = 0xb0, /* OCP GPHY access */
 377 #define OCPDR_WRITE_CMD                 0x80000000
 378 #define OCPDR_READ_CMD                  0x00000000
 379 #define OCPDR_REG_MASK                  0x7f
 380 #define OCPDR_GPHY_REG_SHIFT            16
 381 #define OCPDR_DATA_MASK                 0xffff
 382         OCPAR                   = 0xb4,
 383 #define OCPAR_FLAG                      0x80000000
 384 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 385 #define OCPAR_GPHY_READ_CMD             0x0000f060
 386         GPHY_OCP                = 0xb8,
 387         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 388         MISC                    = 0xf0, /* 8168e only. */
 389 #define TXPLA_RST                       (1 << 29)
 390 #define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 391 #define PWM_EN                          (1 << 22)
 392 #define RXDV_GATED_EN                   (1 << 19)
 393 #define EARLY_TALLY_EN                  (1 << 16)
 394 };
 395
 396 enum rtl8125_registers {
 397         IntrMask_8125           = 0x38,
 398         IntrStatus_8125         = 0x3c,
 399         TxPoll_8125             = 0x90,
 400         MAC0_BKP                = 0x19e0,
 401 };
 402
 403 #define RX_VLAN_INNER_8125      BIT(22)
 404 #define RX_VLAN_OUTER_8125      BIT(23)
 405 #define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 406
 407 #define RX_FETCH_DFLT_8125      (8 << 27)
 408
 409 enum rtl_register_content {
 410         /* InterruptStatusBits */
 411         SYSErr          = 0x8000,
 412         PCSTimeout      = 0x4000,
 413         SWInt           = 0x0100,
 414         TxDescUnavail   = 0x0080,
 415         RxFIFOOver      = 0x0040,
 416         LinkChg         = 0x0020,
 417         RxOverflow      = 0x0010,
 418         TxErr           = 0x0008,
 419         TxOK            = 0x0004,
 420         RxErr           = 0x0002,
 421         RxOK            = 0x0001,
 422
 423         /* RxStatusDesc */
 424         RxRWT   = (1 << 22),
 425         RxRES   = (1 << 21),
 426         RxRUNT  = (1 << 20),
 427         RxCRC   = (1 << 19),
 428
 429         /* ChipCmdBits */
 430         StopReq         = 0x80,
 431         CmdReset        = 0x10,
 432         CmdRxEnb        = 0x08,
 433         CmdTxEnb        = 0x04,
 434         RxBufEmpty      = 0x01,
 435
 436         /* TXPoll register p.5 */
 437         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 438         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 439         FSWInt          = 0x01,         /* Forced software interrupt */
 440
 441         /* Cfg9346Bits */
 442         Cfg9346_Lock    = 0x00,
 443         Cfg9346_Unlock  = 0xc0,
 444
 445         /* rx_mode_bits */
 446         AcceptErr       = 0x20,
 447         AcceptRunt      = 0x10,
 448         AcceptBroadcast = 0x08,
 449         AcceptMulticast = 0x04,
 450         AcceptMyPhys    = 0x02,
 451         AcceptAllPhys   = 0x01,
 452 #define RX_CONFIG_ACCEPT_MASK           0x3f
 453
 454         /* TxConfigBits */
 455         TxInterFrameGapShift = 24,
 456         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 457
 458         /* Config1 register p.24 */
 459         LEDS1           = (1 << 7),
 460         LEDS0           = (1 << 6),
 461         Speed_down      = (1 << 4),
 462         MEMMAP          = (1 << 3),
 463         IOMAP           = (1 << 2),
 464         VPD             = (1 << 1),
 465         PMEnable        = (1 << 0),     /* Power Management Enable */
 466
 467         /* Config2 register p. 25 */
 468         ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 469         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 470         PCI_Clock_66MHz = 0x01,
 471         PCI_Clock_33MHz = 0x00,
 472
 473         /* Config3 register p.25 */
 474         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 475         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 476         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 477         Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 478         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 479
 480         /* Config4 register */
 481         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 482
 483         /* Config5 register p.27 */
 484         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 485         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 486         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 487         Spi_en          = (1 << 3),
 488         LanWake         = (1 << 1),     /* LanWake enable/disable */
 489         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 490         ASPM_en         = (1 << 0),     /* ASPM enable */
 491
 492         /* CPlusCmd p.31 */
 493         EnableBist      = (1 << 15),    // 8168 8101
 494         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 495         Normal_mode     = (1 << 13),    // unused
 496         Force_half_dup  = (1 << 12),    // 8168 8101
 497         Force_rxflow_en = (1 << 11),    // 8168 8101
 498         Force_txflow_en = (1 << 10),    // 8168 8101
 499         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 500         ASF             = (1 << 8),     // 8168 8101
 501         PktCntrDisable  = (1 << 7),     // 8168 8101
 502         Mac_dbgo_sel    = 0x001c,       // 8168
 503         RxVlan          = (1 << 6),
 504         RxChkSum        = (1 << 5),
 505         PCIDAC          = (1 << 4),
 506         PCIMulRW        = (1 << 3),
 507 #define INTT_MASK       GENMASK(1, 0)
 508 #define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 509
 510         /* rtl8169_PHYstatus */
 511         TBI_Enable      = 0x80,
 512         TxFlowCtrl      = 0x40,
 513         RxFlowCtrl      = 0x20,
 514         _1000bpsF       = 0x10,
 515         _100bps         = 0x08,
 516         _10bps          = 0x04,
 517         LinkStatus      = 0x02,
 518         FullDup         = 0x01,
 519
 520         /* ResetCounterCommand */
 521         CounterReset    = 0x1,
 522
 523         /* DumpCounterCommand */
 524         CounterDump     = 0x8,
 525
 526         /* magic enable v2 */
 527         MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 528 };
 529
 530 enum rtl_desc_bit {
 531         /* First doubleword. */
 532         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 533         RingEnd         = (1 << 30), /* End of descriptor ring */
 534         FirstFrag       = (1 << 29), /* First segment of a packet */
 535         LastFrag        = (1 << 28), /* Final segment of a packet */
 536 };
 537
 538 /* Generic case. */
 539 enum rtl_tx_desc_bit {
 540         /* First doubleword. */
 541         TD_LSO          = (1 << 27),            /* Large Send Offload */
 542 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 543
 544         /* Second doubleword. */
 545         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 546 };
 547
 548 /* 8169, 8168b and 810x except 8102e. */
 549 enum rtl_tx_desc_bit_0 {
 550         /* First doubleword. */
 551 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 552         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 553         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 554         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 555 };
 556
 557 /* 8102e, 8168c and beyond. */
 558 enum rtl_tx_desc_bit_1 {
 559         /* First doubleword. */
 560         TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 561         TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 562 #define GTTCPHO_SHIFT                   18
 563 #define GTTCPHO_MAX                     0x7f
 564
 565         /* Second doubleword. */
 566 #define TCPHO_SHIFT                     18
 567 #define TCPHO_MAX                       0x3ff
 568 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 569         TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 570         TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 571         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 572         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 573 };
 574
 575 enum rtl_rx_desc_bit {
 576         /* Rx private */
 577         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 578         PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 579
 580 #define RxProtoUDP      (PID1)
 581 #define RxProtoTCP      (PID0)
 582 #define RxProtoIP       (PID1 | PID0)
 583 #define RxProtoMask     RxProtoIP
 584
 585         IPFail          = (1 << 16), /* IP checksum failed */
 586         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 587         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 588         RxVlanTag       = (1 << 16), /* VLAN tag available */
 589 };
 590
 591 #define RsvdMask        0x3fffc000
 592
 593 #define RTL_GSO_MAX_SIZE_V1     32000
 594 #define RTL_GSO_MAX_SEGS_V1     24
 595 #define RTL_GSO_MAX_SIZE_V2     64000
 596 #define RTL_GSO_MAX_SEGS_V2     64
 597
 598 struct TxDesc {
 599         __le32 opts1;
 600         __le32 opts2;
 601         __le64 addr;
 602 };
 603
 604 struct RxDesc {
 605         __le32 opts1;
 606         __le32 opts2;
 607         __le64 addr;
 608 };
 609
 610 struct ring_info {
 611         struct sk_buff  *skb;
 612         u32             len;
 613 };
 614
 615 struct rtl8169_counters {
 616         __le64  tx_packets;
 617         __le64  rx_packets;
 618         __le64  tx_errors;
 619         __le32  rx_errors;
 620         __le16  rx_missed;
 621         __le16  align_errors;
 622         __le32  tx_one_collision;
 623         __le32  tx_multi_collision;
 624         __le64  rx_unicast;
 625         __le64  rx_broadcast;
 626         __le32  rx_multicast;
 627         __le16  tx_aborted;
 628         __le16  tx_underun;
 629 };
 630
 631 struct rtl8169_tc_offsets {
 632         bool    inited;
 633         __le64  tx_errors;
 634         __le32  tx_multi_collision;
 635         __le16  tx_aborted;
 636 };
 637
 638 enum rtl_flag {
 639         RTL_FLAG_TASK_ENABLED = 0,
 640         RTL_FLAG_TASK_RESET_PENDING,
 641         RTL_FLAG_MAX
 642 };
 643
 644 struct rtl8169_stats {
 645         u64                     packets;
 646         u64                     bytes;
 647         struct u64_stats_sync   syncp;
 648 };
 649
 650 struct rtl8169_private {
 651         void __iomem *mmio_addr;        /* memory map physical address */
 652         struct pci_dev *pci_dev;
 653         struct net_device *dev;
 654         struct phy_device *phydev;
 655         struct napi_struct napi;
 656         u32 msg_enable;
 657         enum mac_version mac_version;
 658         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 659         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 660         u32 dirty_tx;
 661         struct rtl8169_stats rx_stats;
 662         struct rtl8169_stats tx_stats;
 663         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 664         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 665         dma_addr_t TxPhyAddr;
 666         dma_addr_t RxPhyAddr;
 667         struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 668         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 669         u16 cp_cmd;
 670         u32 irq_mask;
 671         struct clk *clk;
 672
 673         struct {
 674                 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 675                 struct mutex mutex;
 676                 struct work_struct work;
 677         } wk;
 678
 679         unsigned irq_enabled:1;
 680         unsigned supports_gmii:1;
 681         unsigned aspm_manageable:1;
 682         dma_addr_t counters_phys_addr;
 683         struct rtl8169_counters *counters;
 684         struct rtl8169_tc_offsets tc_offset;
 685         u32 saved_wolopts;
 686         int eee_adv;
 687
 688         const char *fw_name;
 689         struct rtl_fw *rtl_fw;
 690
 691         u32 ocp_base;
 692 };
 693
 694 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 695
 696 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 697 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 698 module_param_named(debug, debug.msg_enable, int, 0);
 699 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 700 MODULE_SOFTDEP("pre: realtek");
 701 MODULE_LICENSE("GPL");
 702 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 703 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 704 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 705 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 706 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 707 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 708 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 709 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 710 MODULE_FIRMWARE(FIRMWARE_8402_1);
 711 MODULE_FIRMWARE(FIRMWARE_8411_1);
 712 MODULE_FIRMWARE(FIRMWARE_8411_2);
 713 MODULE_FIRMWARE(FIRMWARE_8106E_1);
 714 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 715 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 716 MODULE_FIRMWARE(FIRMWARE_8168G_3);
 717 MODULE_FIRMWARE(FIRMWARE_8168H_1);
 718 MODULE_FIRMWARE(FIRMWARE_8168H_2);
 719 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
 720 MODULE_FIRMWARE(FIRMWARE_8107E_1);
 721 MODULE_FIRMWARE(FIRMWARE_8107E_2);
 722 MODULE_FIRMWARE(FIRMWARE_8125A_3);
 723
 724 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 725 {
 726         return &tp->pci_dev->dev;
 727 }
 728
 729 static void rtl_lock_work(struct rtl8169_private *tp)
 730 {
 731         mutex_lock(&tp->wk.mutex);
 732 }
 733
 734 static void rtl_unlock_work(struct rtl8169_private *tp)
 735 {
 736         mutex_unlock(&tp->wk.mutex);
 737 }
 738
 739 static void rtl_lock_config_regs(struct rtl8169_private *tp)
 740 {
 741         RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 742 }
 743
 744 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 745 {
 746         RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 747 }
 748
 749 static bool rtl_is_8125(struct rtl8169_private *tp)
 750 {
 751         return tp->mac_version >= RTL_GIGA_MAC_VER_60;
 752 }
 753
 754 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 755 {
 756         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 757                tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 758                tp->mac_version <= RTL_GIGA_MAC_VER_52;
 759 }
 760
 761 static bool rtl_supports_eee(struct rtl8169_private *tp)
 762 {
 763         return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 764                tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 765                tp->mac_version != RTL_GIGA_MAC_VER_39;
 766 }
 767
 768 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 769 {
 770         int i;
 771
 772         for (i = 0; i < ETH_ALEN; i++)
 773                 mac[i] = RTL_R8(tp, reg + i);
 774 }
 775
 776 struct rtl_cond {
 777         bool (*check)(struct rtl8169_private *);
 778         const char *msg;
 779 };
 780
 781 static void rtl_udelay(unsigned int d)
 782 {
 783         udelay(d);
 784 }
 785
 786 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 787                           void (*delay)(unsigned int), unsigned int d, int n,
 788                           bool high)
 789 {
 790         int i;
 791
 792         for (i = 0; i < n; i++) {
 793                 if (c->check(tp) == high)
 794                         return true;
 795                 delay(d);
 796         }
 797         netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 798                   c->msg, !high, n, d);
 799         return false;
 800 }
 801
 802 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 803                                       const struct rtl_cond *c,
 804                                       unsigned int d, int n)
 805 {
 806         return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 807 }
 808
 809 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 810                                      const struct rtl_cond *c,
 811                                      unsigned int d, int n)
 812 {
 813         return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 814 }
 815
 816 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 817                                       const struct rtl_cond *c,
 818                                       unsigned int d, int n)
 819 {
 820         return rtl_loop_wait(tp, c, msleep, d, n, true);
 821 }
 822
 823 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 824                                      const struct rtl_cond *c,
 825                                      unsigned int d, int n)
 826 {
 827         return rtl_loop_wait(tp, c, msleep, d, n, false);
 828 }
 829
 830 #define DECLARE_RTL_COND(name)                          \
 831 static bool name ## _check(struct rtl8169_private *);   \
 832                                                         \
 833 static const struct rtl_cond name = {                   \
 834         .check  = name ## _check,                       \
 835         .msg    = #name                                 \
 836 };                                                      \
 837                                                         \
 838 static bool name ## _check(struct rtl8169_private *tp)
 839
 840 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 841 {
 842         if (reg & 0xffff0001) {
 843                 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 844                 return true;
 845         }
 846         return false;
 847 }
 848
 849 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 850 {
 851         return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 852 }
 853
 854 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 855 {
 856         if (rtl_ocp_reg_failure(tp, reg))
 857                 return;
 858
 859         RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 860
 861         rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 862 }
 863
 864 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 865 {
 866         if (rtl_ocp_reg_failure(tp, reg))
 867                 return 0;
 868
 869         RTL_W32(tp, GPHY_OCP, reg << 15);
 870
 871         return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 872                 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 873 }
 874
 875 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 876 {
 877         if (rtl_ocp_reg_failure(tp, reg))
 878                 return;
 879
 880         RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 881 }
 882
 883 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 884 {
 885         if (rtl_ocp_reg_failure(tp, reg))
 886                 return 0;
 887
 888         RTL_W32(tp, OCPDR, reg << 15);
 889
 890         return RTL_R32(tp, OCPDR);
 891 }
 892
 893 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 894                                  u16 set)
 895 {
 896         u16 data = r8168_mac_ocp_read(tp, reg);
 897
 898         r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 899 }
 900
 901 #define OCP_STD_PHY_BASE        0xa400
 902
 903 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 904 {
 905         if (reg == 0x1f) {
 906                 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 907                 return;
 908         }
 909
 910         if (tp->ocp_base != OCP_STD_PHY_BASE)
 911                 reg -= 0x10;
 912
 913         r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 914 }
 915
 916 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 917 {
 918         if (reg == 0x1f)
 919                 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
 920
 921         if (tp->ocp_base != OCP_STD_PHY_BASE)
 922                 reg -= 0x10;
 923
 924         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 925 }
 926
 927 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 928 {
 929         if (reg == 0x1f) {
 930                 tp->ocp_base = value << 4;
 931                 return;
 932         }
 933
 934         r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 935 }
 936
 937 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 938 {
 939         return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 940 }
 941
 942 DECLARE_RTL_COND(rtl_phyar_cond)
 943 {
 944         return RTL_R32(tp, PHYAR) & 0x80000000;
 945 }
 946
 947 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 948 {
 949         RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 950
 951         rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 952         /*
 953          * According to hardware specs a 20us delay is required after write
 954          * complete indication, but before sending next command.
 955          */
 956         udelay(20);
 957 }
 958
 959 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 960 {
 961         int value;
 962
 963         RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 964
 965         value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 966                 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 967
 968         /*
 969          * According to hardware specs a 20us delay is required after read
 970          * complete indication, but before sending next command.
 971          */
 972         udelay(20);
 973
 974         return value;
 975 }
 976
 977 DECLARE_RTL_COND(rtl_ocpar_cond)
 978 {
 979         return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 980 }
 981
 982 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 983 {
 984         RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 985         RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 986         RTL_W32(tp, EPHY_RXER_NUM, 0);
 987
 988         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 989 }
 990
 991 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 992 {
 993         r8168dp_1_mdio_access(tp, reg,
 994                               OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 995 }
 996
 997 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 998 {
 999         r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1000
1001         mdelay(1);
1002         RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1003         RTL_W32(tp, EPHY_RXER_NUM, 0);
1004
1005         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1006                 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
1007 }
1008
1009 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1010
1011 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1012 {
1013         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1014 }
1015
1016 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1017 {
1018         RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1019 }
1020
1021 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1022 {
1023         r8168dp_2_mdio_start(tp);
1024
1025         r8169_mdio_write(tp, reg, value);
1026
1027         r8168dp_2_mdio_stop(tp);
1028 }
1029
1030 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1031 {
1032         int value;
1033
1034         /* Work around issue with chip reporting wrong PHY ID */
1035         if (reg == MII_PHYSID2)
1036                 return 0xc912;
1037
1038         r8168dp_2_mdio_start(tp);
1039
1040         value = r8169_mdio_read(tp, reg);
1041
1042         r8168dp_2_mdio_stop(tp);
1043
1044         return value;
1045 }
1046
1047 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1048 {
1049         switch (tp->mac_version) {
1050         case RTL_GIGA_MAC_VER_27:
1051                 r8168dp_1_mdio_write(tp, location, val);
1052                 break;
1053         case RTL_GIGA_MAC_VER_28:
1054         case RTL_GIGA_MAC_VER_31:
1055                 r8168dp_2_mdio_write(tp, location, val);
1056                 break;
1057         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1058                 r8168g_mdio_write(tp, location, val);
1059                 break;
1060         default:
1061                 r8169_mdio_write(tp, location, val);
1062                 break;
1063         }
1064 }
1065
1066 static int rtl_readphy(struct rtl8169_private *tp, int location)
1067 {
1068         switch (tp->mac_version) {
1069         case RTL_GIGA_MAC_VER_27:
1070                 return r8168dp_1_mdio_read(tp, location);
1071         case RTL_GIGA_MAC_VER_28:
1072         case RTL_GIGA_MAC_VER_31:
1073                 return r8168dp_2_mdio_read(tp, location);
1074         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1075                 return r8168g_mdio_read(tp, location);
1076         default:
1077                 return r8169_mdio_read(tp, location);
1078         }
1079 }
1080
1081 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1082 {
1083         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1084 }
1085
1086 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1087 {
1088         int val;
1089
1090         val = rtl_readphy(tp, reg_addr);
1091         rtl_writephy(tp, reg_addr, (val & ~m) | p);
1092 }
1093
1094 static void r8168d_modify_extpage(struct phy_device *phydev, int extpage,
1095                                   int reg, u16 mask, u16 val)
1096 {
1097         int oldpage = phy_select_page(phydev, 0x0007);
1098
1099         __phy_write(phydev, 0x1e, extpage);
1100         __phy_modify(phydev, reg, mask, val);
1101
1102         phy_restore_page(phydev, oldpage, 0);
1103 }
1104
1105 static void r8168d_phy_param(struct phy_device *phydev, u16 parm,
1106                              u16 mask, u16 val)
1107 {
1108         int oldpage = phy_select_page(phydev, 0x0005);
1109
1110         __phy_write(phydev, 0x05, parm);
1111         __phy_modify(phydev, 0x06, mask, val);
1112
1113         phy_restore_page(phydev, oldpage, 0);
1114 }
1115
1116 static void r8168g_phy_param(struct phy_device *phydev, u16 parm,
1117                              u16 mask, u16 val)
1118 {
1119         int oldpage = phy_select_page(phydev, 0x0a43);
1120
1121         __phy_write(phydev, 0x13, parm);
1122         __phy_modify(phydev, 0x14, mask, val);
1123
1124         phy_restore_page(phydev, oldpage, 0);
1125 }
1126
1127 DECLARE_RTL_COND(rtl_ephyar_cond)
1128 {
1129         return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1130 }
1131
1132 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1133 {
1134         RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1135                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1136
1137         rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1138
1139         udelay(10);
1140 }
1141
1142 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1143 {
1144         RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1145
1146         return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1147                 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1148 }
1149
1150 DECLARE_RTL_COND(rtl_eriar_cond)
1151 {
1152         return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1153 }
1154
1155 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1156                            u32 val, int type)
1157 {
1158         BUG_ON((addr & 3) || (mask == 0));
1159         RTL_W32(tp, ERIDR, val);
1160         RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1161
1162         rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1163 }
1164
1165 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1166                           u32 val)
1167 {
1168         _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1169 }
1170
1171 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1172 {
1173         RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1174
1175         return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1176                 RTL_R32(tp, ERIDR) : ~0;
1177 }
1178
1179 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1180 {
1181         return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1182 }
1183
1184 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1185                          u32 m)
1186 {
1187         u32 val;
1188
1189         val = rtl_eri_read(tp, addr);
1190         rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1191 }
1192
1193 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1194                              u32 p)
1195 {
1196         rtl_w0w1_eri(tp, addr, mask, p, 0);
1197 }
1198
1199 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1200                                u32 m)
1201 {
1202         rtl_w0w1_eri(tp, addr, mask, 0, m);
1203 }
1204
1205 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1206 {
1207         RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1208         return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1209                 RTL_R32(tp, OCPDR) : ~0;
1210 }
1211
1212 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1213 {
1214         return _rtl_eri_read(tp, reg, ERIAR_OOB);
1215 }
1216
1217 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1218                               u32 data)
1219 {
1220         RTL_W32(tp, OCPDR, data);
1221         RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1222         rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1223 }
1224
1225 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1226                               u32 data)
1227 {
1228         _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1229                        data, ERIAR_OOB);
1230 }
1231
1232 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1233 {
1234         rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1235
1236         r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1237 }
1238
1239 #define OOB_CMD_RESET           0x00
1240 #define OOB_CMD_DRIVER_START    0x05
1241 #define OOB_CMD_DRIVER_STOP     0x06
1242
1243 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1244 {
1245         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1246 }
1247
1248 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1249 {
1250         u16 reg;
1251
1252         reg = rtl8168_get_ocp_reg(tp);
1253
1254         return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1255 }
1256
1257 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1258 {
1259         return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1260 }
1261
1262 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1263 {
1264         return RTL_R8(tp, IBISR0) & 0x20;
1265 }
1266
1267 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1268 {
1269         RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1270         rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1271         RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1272         RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1273 }
1274
1275 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1276 {
1277         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1278         rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1279 }
1280
1281 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1282 {
1283         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1284         r8168ep_ocp_write(tp, 0x01, 0x30,
1285                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1286         rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1287 }
1288
1289 static void rtl8168_driver_start(struct rtl8169_private *tp)
1290 {
1291         switch (tp->mac_version) {
1292         case RTL_GIGA_MAC_VER_27:
1293         case RTL_GIGA_MAC_VER_28:
1294         case RTL_GIGA_MAC_VER_31:
1295                 rtl8168dp_driver_start(tp);
1296                 break;
1297         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1298                 rtl8168ep_driver_start(tp);
1299                 break;
1300         default:
1301                 BUG();
1302                 break;
1303         }
1304 }
1305
1306 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1307 {
1308         r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1309         rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1310 }
1311
1312 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1313 {
1314         rtl8168ep_stop_cmac(tp);
1315         r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1316         r8168ep_ocp_write(tp, 0x01, 0x30,
1317                           r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1318         rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1319 }
1320
1321 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1322 {
1323         switch (tp->mac_version) {
1324         case RTL_GIGA_MAC_VER_27:
1325         case RTL_GIGA_MAC_VER_28:
1326         case RTL_GIGA_MAC_VER_31:
1327                 rtl8168dp_driver_stop(tp);
1328                 break;
1329         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1330                 rtl8168ep_driver_stop(tp);
1331                 break;
1332         default:
1333                 BUG();
1334                 break;
1335         }
1336 }
1337
1338 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1339 {
1340         u16 reg = rtl8168_get_ocp_reg(tp);
1341
1342         return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1343 }
1344
1345 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1346 {
1347         return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1348 }
1349
1350 static bool r8168_check_dash(struct rtl8169_private *tp)
1351 {
1352         switch (tp->mac_version) {
1353         case RTL_GIGA_MAC_VER_27:
1354         case RTL_GIGA_MAC_VER_28:
1355         case RTL_GIGA_MAC_VER_31:
1356                 return r8168dp_check_dash(tp);
1357         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1358                 return r8168ep_check_dash(tp);
1359         default:
1360                 return false;
1361         }
1362 }
1363
1364 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1365 {
1366         rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1367         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1368 }
1369
1370 DECLARE_RTL_COND(rtl_efusear_cond)
1371 {
1372         return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1373 }
1374
1375 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1376 {
1377         RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1378
1379         return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1380                 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1381 }
1382
1383 static u32 rtl_get_events(struct rtl8169_private *tp)
1384 {
1385         if (rtl_is_8125(tp))
1386                 return RTL_R32(tp, IntrStatus_8125);
1387         else
1388                 return RTL_R16(tp, IntrStatus);
1389 }
1390
1391 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1392 {
1393         if (rtl_is_8125(tp))
1394                 RTL_W32(tp, IntrStatus_8125, bits);
1395         else
1396                 RTL_W16(tp, IntrStatus, bits);
1397 }
1398
1399 static void rtl_irq_disable(struct rtl8169_private *tp)
1400 {
1401         if (rtl_is_8125(tp))
1402                 RTL_W32(tp, IntrMask_8125, 0);
1403         else
1404                 RTL_W16(tp, IntrMask, 0);
1405         tp->irq_enabled = 0;
1406 }
1407
1408 #define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1409 #define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1410 #define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1411
1412 static void rtl_irq_enable(struct rtl8169_private *tp)
1413 {
1414         tp->irq_enabled = 1;
1415         if (rtl_is_8125(tp))
1416                 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1417         else
1418                 RTL_W16(tp, IntrMask, tp->irq_mask);
1419 }
1420
1421 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1422 {
1423         rtl_irq_disable(tp);
1424         rtl_ack_events(tp, 0xffffffff);
1425         /* PCI commit */
1426         RTL_R8(tp, ChipCmd);
1427 }
1428
1429 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1430 {
1431         struct net_device *dev = tp->dev;
1432         struct phy_device *phydev = tp->phydev;
1433
1434         if (!netif_running(dev))
1435                 return;
1436
1437         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1438             tp->mac_version == RTL_GIGA_MAC_VER_38) {
1439                 if (phydev->speed == SPEED_1000) {
1440                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1441                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1442                 } else if (phydev->speed == SPEED_100) {
1443                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1444                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1445                 } else {
1446                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1447                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1448                 }
1449                 rtl_reset_packet_filter(tp);
1450         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1451                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1452                 if (phydev->speed == SPEED_1000) {
1453                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1454                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1455                 } else {
1456                         rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1457                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1458                 }
1459         } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1460                 if (phydev->speed == SPEED_10) {
1461                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1462                         rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1463                 } else {
1464                         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1465                 }
1466         }
1467 }
1468
1469 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1470
1471 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1472 {
1473         struct rtl8169_private *tp = netdev_priv(dev);
1474
1475         rtl_lock_work(tp);
1476         wol->supported = WAKE_ANY;
1477         wol->wolopts = tp->saved_wolopts;
1478         rtl_unlock_work(tp);
1479 }
1480
1481 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1482 {
1483         static const struct {
1484                 u32 opt;
1485                 u16 reg;
1486                 u8  mask;
1487         } cfg[] = {
1488                 { WAKE_PHY,   Config3, LinkUp },
1489                 { WAKE_UCAST, Config5, UWF },
1490                 { WAKE_BCAST, Config5, BWF },
1491                 { WAKE_MCAST, Config5, MWF },
1492                 { WAKE_ANY,   Config5, LanWake },
1493                 { WAKE_MAGIC, Config3, MagicPacket }
1494         };
1495         unsigned int i, tmp = ARRAY_SIZE(cfg);
1496         u8 options;
1497
1498         rtl_unlock_config_regs(tp);
1499
1500         if (rtl_is_8168evl_up(tp)) {
1501                 tmp--;
1502                 if (wolopts & WAKE_MAGIC)
1503                         rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1504                                          MagicPacket_v2);
1505                 else
1506                         rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1507                                            MagicPacket_v2);
1508         } else if (rtl_is_8125(tp)) {
1509                 tmp--;
1510                 if (wolopts & WAKE_MAGIC)
1511                         r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1512                 else
1513                         r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1514         }
1515
1516         for (i = 0; i < tmp; i++) {
1517                 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1518                 if (wolopts & cfg[i].opt)
1519                         options |= cfg[i].mask;
1520                 RTL_W8(tp, cfg[i].reg, options);
1521         }
1522
1523         switch (tp->mac_version) {
1524         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1525                 options = RTL_R8(tp, Config1) & ~PMEnable;
1526                 if (wolopts)
1527                         options |= PMEnable;
1528                 RTL_W8(tp, Config1, options);
1529                 break;
1530         case RTL_GIGA_MAC_VER_34:
1531         case RTL_GIGA_MAC_VER_37:
1532         case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_52:
1533                 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1534                 if (wolopts)
1535                         options |= PME_SIGNAL;
1536                 RTL_W8(tp, Config2, options);
1537                 break;
1538         default:
1539                 break;
1540         }
1541
1542         rtl_lock_config_regs(tp);
1543
1544         device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1545 }
1546
1547 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1548 {
1549         struct rtl8169_private *tp = netdev_priv(dev);
1550         struct device *d = tp_to_dev(tp);
1551
1552         if (wol->wolopts & ~WAKE_ANY)
1553                 return -EINVAL;
1554
1555         pm_runtime_get_noresume(d);
1556
1557         rtl_lock_work(tp);
1558
1559         tp->saved_wolopts = wol->wolopts;
1560
1561         if (pm_runtime_active(d))
1562                 __rtl8169_set_wol(tp, tp->saved_wolopts);
1563
1564         rtl_unlock_work(tp);
1565
1566         pm_runtime_put_noidle(d);
1567
1568         return 0;
1569 }
1570
1571 static void rtl8169_get_drvinfo(struct net_device *dev,
1572                                 struct ethtool_drvinfo *info)
1573 {
1574         struct rtl8169_private *tp = netdev_priv(dev);
1575         struct rtl_fw *rtl_fw = tp->rtl_fw;
1576
1577         strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1578         strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1579         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1580         if (rtl_fw)
1581                 strlcpy(info->fw_version, rtl_fw->version,
1582                         sizeof(info->fw_version));
1583 }
1584
1585 static int rtl8169_get_regs_len(struct net_device *dev)
1586 {
1587         return R8169_REGS_SIZE;
1588 }
1589
1590 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1591         netdev_features_t features)
1592 {
1593         struct rtl8169_private *tp = netdev_priv(dev);
1594
1595         if (dev->mtu > TD_MSS_MAX)
1596                 features &= ~NETIF_F_ALL_TSO;
1597
1598         if (dev->mtu > JUMBO_1K &&
1599             tp->mac_version > RTL_GIGA_MAC_VER_06)
1600                 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1601
1602         return features;
1603 }
1604
1605 static int rtl8169_set_features(struct net_device *dev,
1606                                 netdev_features_t features)
1607 {
1608         struct rtl8169_private *tp = netdev_priv(dev);
1609         u32 rx_config;
1610
1611         rtl_lock_work(tp);
1612
1613         rx_config = RTL_R32(tp, RxConfig);
1614         if (features & NETIF_F_RXALL)
1615                 rx_config |= (AcceptErr | AcceptRunt);
1616         else
1617                 rx_config &= ~(AcceptErr | AcceptRunt);
1618
1619         if (rtl_is_8125(tp)) {
1620                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1621                         rx_config |= RX_VLAN_8125;
1622                 else
1623                         rx_config &= ~RX_VLAN_8125;
1624         }
1625
1626         RTL_W32(tp, RxConfig, rx_config);
1627
1628         if (features & NETIF_F_RXCSUM)
1629                 tp->cp_cmd |= RxChkSum;
1630         else
1631                 tp->cp_cmd &= ~RxChkSum;
1632
1633         if (!rtl_is_8125(tp)) {
1634                 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1635                         tp->cp_cmd |= RxVlan;
1636                 else
1637                         tp->cp_cmd &= ~RxVlan;
1638         }
1639
1640         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1641         RTL_R16(tp, CPlusCmd);
1642
1643         rtl_unlock_work(tp);
1644
1645         return 0;
1646 }
1647
1648 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1649 {
1650         return (skb_vlan_tag_present(skb)) ?
1651                 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1652 }
1653
1654 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1655 {
1656         u32 opts2 = le32_to_cpu(desc->opts2);
1657
1658         if (opts2 & RxVlanTag)
1659                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1660 }
1661
1662 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1663                              void *p)
1664 {
1665         struct rtl8169_private *tp = netdev_priv(dev);
1666         u32 __iomem *data = tp->mmio_addr;
1667         u32 *dw = p;
1668         int i;
1669
1670         rtl_lock_work(tp);
1671         for (i = 0; i < R8169_REGS_SIZE; i += 4)
1672                 memcpy_fromio(dw++, data++, 4);
1673         rtl_unlock_work(tp);
1674 }
1675
1676 static u32 rtl8169_get_msglevel(struct net_device *dev)
1677 {
1678         struct rtl8169_private *tp = netdev_priv(dev);
1679
1680         return tp->msg_enable;
1681 }
1682
1683 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1684 {
1685         struct rtl8169_private *tp = netdev_priv(dev);
1686
1687         tp->msg_enable = value;
1688 }
1689
1690 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1691         "tx_packets",
1692         "rx_packets",
1693         "tx_errors",
1694         "rx_errors",
1695         "rx_missed",
1696         "align_errors",
1697         "tx_single_collisions",
1698         "tx_multi_collisions",
1699         "unicast",
1700         "broadcast",
1701         "multicast",
1702         "tx_aborted",
1703         "tx_underrun",
1704 };
1705
1706 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1707 {
1708         switch (sset) {
1709         case ETH_SS_STATS:
1710                 return ARRAY_SIZE(rtl8169_gstrings);
1711         default:
1712                 return -EOPNOTSUPP;
1713         }
1714 }
1715
1716 DECLARE_RTL_COND(rtl_counters_cond)
1717 {
1718         return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1719 }
1720
1721 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1722 {
1723         dma_addr_t paddr = tp->counters_phys_addr;
1724         u32 cmd;
1725
1726         RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1727         RTL_R32(tp, CounterAddrHigh);
1728         cmd = (u64)paddr & DMA_BIT_MASK(32);
1729         RTL_W32(tp, CounterAddrLow, cmd);
1730         RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1731
1732         return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1733 }
1734
1735 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1736 {
1737         /*
1738          * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1739          * tally counters.
1740          */
1741         if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1742                 return true;
1743
1744         return rtl8169_do_counters(tp, CounterReset);
1745 }
1746
1747 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1748 {
1749         u8 val = RTL_R8(tp, ChipCmd);
1750
1751         /*
1752          * Some chips are unable to dump tally counters when the receiver
1753          * is disabled. If 0xff chip may be in a PCI power-save state.
1754          */
1755         if (!(val & CmdRxEnb) || val == 0xff)
1756                 return true;
1757
1758         return rtl8169_do_counters(tp, CounterDump);
1759 }
1760
1761 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1762 {
1763         struct rtl8169_counters *counters = tp->counters;
1764         bool ret = false;
1765
1766         /*
1767          * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1768          * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1769          * reset by a power cycle, while the counter values collected by the
1770          * driver are reset at every driver unload/load cycle.
1771          *
1772          * To make sure the HW values returned by @get_stats64 match the SW
1773          * values, we collect the initial values at first open(*) and use them
1774          * as offsets to normalize the values returned by @get_stats64.
1775          *
1776          * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1777          * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1778          * set at open time by rtl_hw_start.
1779          */
1780
1781         if (tp->tc_offset.inited)
1782                 return true;
1783
1784         /* If both, reset and update fail, propagate to caller. */
1785         if (rtl8169_reset_counters(tp))
1786                 ret = true;
1787
1788         if (rtl8169_update_counters(tp))
1789                 ret = true;
1790
1791         tp->tc_offset.tx_errors = counters->tx_errors;
1792         tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1793         tp->tc_offset.tx_aborted = counters->tx_aborted;
1794         tp->tc_offset.inited = true;
1795
1796         return ret;
1797 }
1798
1799 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1800                                       struct ethtool_stats *stats, u64 *data)
1801 {
1802         struct rtl8169_private *tp = netdev_priv(dev);
1803         struct device *d = tp_to_dev(tp);
1804         struct rtl8169_counters *counters = tp->counters;
1805
1806         ASSERT_RTNL();
1807
1808         pm_runtime_get_noresume(d);
1809
1810         if (pm_runtime_active(d))
1811                 rtl8169_update_counters(tp);
1812
1813         pm_runtime_put_noidle(d);
1814
1815         data[0] = le64_to_cpu(counters->tx_packets);
1816         data[1] = le64_to_cpu(counters->rx_packets);
1817         data[2] = le64_to_cpu(counters->tx_errors);
1818         data[3] = le32_to_cpu(counters->rx_errors);
1819         data[4] = le16_to_cpu(counters->rx_missed);
1820         data[5] = le16_to_cpu(counters->align_errors);
1821         data[6] = le32_to_cpu(counters->tx_one_collision);
1822         data[7] = le32_to_cpu(counters->tx_multi_collision);
1823         data[8] = le64_to_cpu(counters->rx_unicast);
1824         data[9] = le64_to_cpu(counters->rx_broadcast);
1825         data[10] = le32_to_cpu(counters->rx_multicast);
1826         data[11] = le16_to_cpu(counters->tx_aborted);
1827         data[12] = le16_to_cpu(counters->tx_underun);
1828 }
1829
1830 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1831 {
1832         switch(stringset) {
1833         case ETH_SS_STATS:
1834                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1835                 break;
1836         }
1837 }
1838
1839 /*
1840  * Interrupt coalescing
1841  *
1842  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1843  * >     8169, 8168 and 810x line of chipsets
1844  *
1845  * 8169, 8168, and 8136(810x) serial chipsets support it.
1846  *
1847  * > 2 - the Tx timer unit at gigabit speed
1848  *
1849  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1850  * (0xe0) bit 1 and bit 0.
1851  *
1852  * For 8169
1853  * bit[1:0] \ speed        1000M           100M            10M
1854  * 0 0                     320ns           2.56us          40.96us
1855  * 0 1                     2.56us          20.48us         327.7us
1856  * 1 0                     5.12us          40.96us         655.4us
1857  * 1 1                     10.24us         81.92us         1.31ms
1858  *
1859  * For the other
1860  * bit[1:0] \ speed        1000M           100M            10M
1861  * 0 0                     5us             2.56us          40.96us
1862  * 0 1                     40us            20.48us         327.7us
1863  * 1 0                     80us            40.96us         655.4us
1864  * 1 1                     160us           81.92us         1.31ms
1865  */
1866
1867 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1868 struct rtl_coalesce_scale {
1869         /* Rx / Tx */
1870         u32 nsecs[2];
1871 };
1872
1873 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1874 struct rtl_coalesce_info {
1875         u32 speed;
1876         struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1877 };
1878
1879 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1880 #define rxtx_x1822(r, t) {              \
1881         {{(r),          (t)}},          \
1882         {{(r)*8,        (t)*8}},        \
1883         {{(r)*8*2,      (t)*8*2}},      \
1884         {{(r)*8*2*2,    (t)*8*2*2}},    \
1885 }
1886 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1887         /* speed        delays:     rx00   tx00 */
1888         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1889         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1890         { SPEED_1000,   rxtx_x1822(  320,   320)        },
1891         { 0 },
1892 };
1893
1894 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1895         /* speed        delays:     rx00   tx00 */
1896         { SPEED_10,     rxtx_x1822(40960, 40960)        },
1897         { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1898         { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1899         { 0 },
1900 };
1901 #undef rxtx_x1822
1902
1903 /* get rx/tx scale vector corresponding to current speed */
1904 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1905 {
1906         struct rtl8169_private *tp = netdev_priv(dev);
1907         const struct rtl_coalesce_info *ci;
1908
1909         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1910                 ci = rtl_coalesce_info_8169;
1911         else
1912                 ci = rtl_coalesce_info_8168_8136;
1913
1914         for (; ci->speed; ci++) {
1915                 if (tp->phydev->speed == ci->speed)
1916                         return ci;
1917         }
1918
1919         return ERR_PTR(-ELNRNG);
1920 }
1921
1922 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1923 {
1924         struct rtl8169_private *tp = netdev_priv(dev);
1925         const struct rtl_coalesce_info *ci;
1926         const struct rtl_coalesce_scale *scale;
1927         struct {
1928                 u32 *max_frames;
1929                 u32 *usecs;
1930         } coal_settings [] = {
1931                 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1932                 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1933         }, *p = coal_settings;
1934         int i;
1935         u16 w;
1936
1937         if (rtl_is_8125(tp))
1938                 return -EOPNOTSUPP;
1939
1940         memset(ec, 0, sizeof(*ec));
1941
1942         /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1943         ci = rtl_coalesce_info(dev);
1944         if (IS_ERR(ci))
1945                 return PTR_ERR(ci);
1946
1947         scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1948
1949         /* read IntrMitigate and adjust according to scale */
1950         for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1951                 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1952                 w >>= RTL_COALESCE_SHIFT;
1953                 *p->usecs = w & RTL_COALESCE_MASK;
1954         }
1955
1956         for (i = 0; i < 2; i++) {
1957                 p = coal_settings + i;
1958                 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1959
1960                 /*
1961                  * ethtool_coalesce says it is illegal to set both usecs and
1962                  * max_frames to 0.
1963                  */
1964                 if (!*p->usecs && !*p->max_frames)
1965                         *p->max_frames = 1;
1966         }
1967
1968         return 0;
1969 }
1970
1971 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1972 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1973                         struct net_device *dev, u32 nsec, u16 *cp01)
1974 {
1975         const struct rtl_coalesce_info *ci;
1976         u16 i;
1977
1978         ci = rtl_coalesce_info(dev);
1979         if (IS_ERR(ci))
1980                 return ERR_CAST(ci);
1981
1982         for (i = 0; i < 4; i++) {
1983                 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1984                                         ci->scalev[i].nsecs[1]);
1985                 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1986                         *cp01 = i;
1987                         return &ci->scalev[i];
1988                 }
1989         }
1990
1991         return ERR_PTR(-EINVAL);
1992 }
1993
1994 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1995 {
1996         struct rtl8169_private *tp = netdev_priv(dev);
1997         const struct rtl_coalesce_scale *scale;
1998         struct {
1999                 u32 frames;
2000                 u32 usecs;
2001         } coal_settings [] = {
2002                 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
2003                 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
2004         }, *p = coal_settings;
2005         u16 w = 0, cp01;
2006         int i;
2007
2008         if (rtl_is_8125(tp))
2009                 return -EOPNOTSUPP;
2010
2011         scale = rtl_coalesce_choose_scale(dev,
2012                         max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2013         if (IS_ERR(scale))
2014                 return PTR_ERR(scale);
2015
2016         for (i = 0; i < 2; i++, p++) {
2017                 u32 units;
2018
2019                 /*
2020                  * accept max_frames=1 we returned in rtl_get_coalesce.
2021                  * accept it not only when usecs=0 because of e.g. the following scenario:
2022                  *
2023                  * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2024                  * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2025                  * - then user does `ethtool -C eth0 rx-usecs 100`
2026                  *
2027                  * since ethtool sends to kernel whole ethtool_coalesce
2028                  * settings, if we do not handle rx_usecs=!0, rx_frames=1
2029                  * we'll reject it below in `frames % 4 != 0`.
2030                  */
2031                 if (p->frames == 1) {
2032                         p->frames = 0;
2033                 }
2034
2035                 units = p->usecs * 1000 / scale->nsecs[i];
2036                 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2037                         return -EINVAL;
2038
2039                 w <<= RTL_COALESCE_SHIFT;
2040                 w |= units;
2041                 w <<= RTL_COALESCE_SHIFT;
2042                 w |= p->frames >> 2;
2043         }
2044
2045         rtl_lock_work(tp);
2046
2047         RTL_W16(tp, IntrMitigate, swab16(w));
2048
2049         tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2050         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2051         RTL_R16(tp, CPlusCmd);
2052
2053         rtl_unlock_work(tp);
2054
2055         return 0;
2056 }
2057
2058 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2059 {
2060         struct rtl8169_private *tp = netdev_priv(dev);
2061         struct device *d = tp_to_dev(tp);
2062         int ret;
2063
2064         if (!rtl_supports_eee(tp))
2065                 return -EOPNOTSUPP;
2066
2067         pm_runtime_get_noresume(d);
2068
2069         if (!pm_runtime_active(d)) {
2070                 ret = -EOPNOTSUPP;
2071         } else {
2072                 ret = phy_ethtool_get_eee(tp->phydev, data);
2073         }
2074
2075         pm_runtime_put_noidle(d);
2076
2077         return ret;
2078 }
2079
2080 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2081 {
2082         struct rtl8169_private *tp = netdev_priv(dev);
2083         struct device *d = tp_to_dev(tp);
2084         int ret;
2085
2086         if (!rtl_supports_eee(tp))
2087                 return -EOPNOTSUPP;
2088
2089         pm_runtime_get_noresume(d);
2090
2091         if (!pm_runtime_active(d)) {
2092                 ret = -EOPNOTSUPP;
2093                 goto out;
2094         }
2095
2096         if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2097             dev->phydev->duplex != DUPLEX_FULL) {
2098                 ret = -EPROTONOSUPPORT;
2099                 goto out;
2100         }
2101
2102         ret = phy_ethtool_set_eee(tp->phydev, data);
2103
2104         if (!ret)
2105                 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
2106                                            MDIO_AN_EEE_ADV);
2107 out:
2108         pm_runtime_put_noidle(d);
2109         return ret;
2110 }
2111
2112 static const struct ethtool_ops rtl8169_ethtool_ops = {
2113         .get_drvinfo            = rtl8169_get_drvinfo,
2114         .get_regs_len           = rtl8169_get_regs_len,
2115         .get_link               = ethtool_op_get_link,
2116         .get_coalesce           = rtl_get_coalesce,
2117         .set_coalesce           = rtl_set_coalesce,
2118         .get_msglevel           = rtl8169_get_msglevel,
2119         .set_msglevel           = rtl8169_set_msglevel,
2120         .get_regs               = rtl8169_get_regs,
2121         .get_wol                = rtl8169_get_wol,
2122         .set_wol                = rtl8169_set_wol,
2123         .get_strings            = rtl8169_get_strings,
2124         .get_sset_count         = rtl8169_get_sset_count,
2125         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2126         .get_ts_info            = ethtool_op_get_ts_info,
2127         .nway_reset             = phy_ethtool_nway_reset,
2128         .get_eee                = rtl8169_get_eee,
2129         .set_eee                = rtl8169_set_eee,
2130         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2131         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2132 };
2133
2134 static void rtl_enable_eee(struct rtl8169_private *tp)
2135 {
2136         struct phy_device *phydev = tp->phydev;
2137         int adv;
2138
2139         /* respect EEE advertisement the user may have set */
2140         if (tp->eee_adv >= 0)
2141                 adv = tp->eee_adv;
2142         else
2143                 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2144
2145         if (adv >= 0)
2146                 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
2147 }
2148
2149 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2150 {
2151         /*
2152          * The driver currently handles the 8168Bf and the 8168Be identically
2153          * but they can be identified more specifically through the test below
2154          * if needed:
2155          *
2156          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2157          *
2158          * Same thing for the 8101Eb and the 8101Ec:
2159          *
2160          * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2161          */
2162         static const struct rtl_mac_info {
2163                 u16 mask;
2164                 u16 val;
2165                 u16 mac_version;
2166         } mac_info[] = {
2167                 /* 8125 family. */
2168                 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2169                 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2170
2171                 /* RTL8117 */
2172                 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2173
2174                 /* 8168EP family. */
2175                 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2176                 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2177                 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2178
2179                 /* 8168H family. */
2180                 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2181                 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2182
2183                 /* 8168G family. */
2184                 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2185                 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2186                 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2187                 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2188
2189                 /* 8168F family. */
2190                 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2191                 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2192                 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2193
2194                 /* 8168E family. */
2195                 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2196                 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2197                 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2198
2199                 /* 8168D family. */
2200                 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2201                 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2202
2203                 /* 8168DP family. */
2204                 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2205                 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2206                 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2207
2208                 /* 8168C family. */
2209                 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2210                 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2211                 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2212                 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2213                 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2214                 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2215                 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2216
2217                 /* 8168B family. */
2218                 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2219                 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2220                 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2221
2222                 /* 8101 family. */
2223                 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2224                 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2225                 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2226                 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2227                 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2228                 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2229                 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2230                 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2231                 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2232                 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2233                 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2234                 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2235                 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2236                 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2237                 /* FIXME: where did these entries come from ? -- FR */
2238                 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2239                 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2240
2241                 /* 8110 family. */
2242                 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2243                 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2244                 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2245                 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2246                 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2247
2248                 /* Catch-all */
2249                 { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2250         };
2251         const struct rtl_mac_info *p = mac_info;
2252         u16 reg = RTL_R32(tp, TxConfig) >> 20;
2253
2254         while ((reg & p->mask) != p->val)
2255                 p++;
2256         tp->mac_version = p->mac_version;
2257
2258         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2259                 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2260         } else if (!tp->supports_gmii) {
2261                 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2262                         tp->mac_version = RTL_GIGA_MAC_VER_43;
2263                 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2264                         tp->mac_version = RTL_GIGA_MAC_VER_47;
2265                 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2266                         tp->mac_version = RTL_GIGA_MAC_VER_48;
2267         }
2268 }
2269
2270 struct phy_reg {
2271         u16 reg;
2272         u16 val;
2273 };
2274
2275 static void __rtl_writephy_batch(struct rtl8169_private *tp,
2276                                  const struct phy_reg *regs, int len)
2277 {
2278         while (len-- > 0) {
2279                 rtl_writephy(tp, regs->reg, regs->val);
2280                 regs++;
2281         }
2282 }
2283
2284 #define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2285
2286 static void rtl_release_firmware(struct rtl8169_private *tp)
2287 {
2288         if (tp->rtl_fw) {
2289                 rtl_fw_release_firmware(tp->rtl_fw);
2290                 kfree(tp->rtl_fw);
2291                 tp->rtl_fw = NULL;
2292         }
2293 }
2294
2295 static void rtl_apply_firmware(struct rtl8169_private *tp)
2296 {
2297         /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2298         if (tp->rtl_fw)
2299                 rtl_fw_write_firmware(tp, tp->rtl_fw);
2300 }
2301
2302 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2303 {
2304         /* Adjust EEE LED frequency */
2305         if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2306                 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2307
2308         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2309 }
2310
2311 static void rtl8125_config_eee_mac(struct rtl8169_private *tp)
2312 {
2313         r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2314         r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2315 }
2316
2317 static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2318 {
2319         struct phy_device *phydev = tp->phydev;
2320
2321         r8168d_modify_extpage(phydev, 0x0020, 0x15, 0, BIT(8));
2322         r8168d_phy_param(phydev, 0x8b85, 0, BIT(13));
2323 }
2324
2325 static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2326 {
2327         phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2328 }
2329
2330 static void rtl8168h_config_eee_phy(struct rtl8169_private *tp)
2331 {
2332         struct phy_device *phydev = tp->phydev;
2333
2334         rtl8168g_config_eee_phy(tp);
2335
2336         phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200);
2337         phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080);
2338 }
2339
2340 static void rtl8125_config_eee_phy(struct rtl8169_private *tp)
2341 {
2342         struct phy_device *phydev = tp->phydev;
2343
2344         rtl8168h_config_eee_phy(tp);
2345
2346         phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000);
2347         phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000);
2348 }
2349
2350 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2351 {
2352         static const struct phy_reg phy_reg_init[] = {
2353                 { 0x1f, 0x0001 },
2354                 { 0x06, 0x006e },
2355                 { 0x08, 0x0708 },
2356                 { 0x15, 0x4000 },
2357                 { 0x18, 0x65c7 },
2358
2359                 { 0x1f, 0x0001 },
2360                 { 0x03, 0x00a1 },
2361                 { 0x02, 0x0008 },
2362                 { 0x01, 0x0120 },
2363                 { 0x00, 0x1000 },
2364                 { 0x04, 0x0800 },
2365                 { 0x04, 0x0000 },
2366
2367                 { 0x03, 0xff41 },
2368                 { 0x02, 0xdf60 },
2369                 { 0x01, 0x0140 },
2370                 { 0x00, 0x0077 },
2371                 { 0x04, 0x7800 },
2372                 { 0x04, 0x7000 },
2373
2374                 { 0x03, 0x802f },
2375                 { 0x02, 0x4f02 },
2376                 { 0x01, 0x0409 },
2377                 { 0x00, 0xf0f9 },
2378                 { 0x04, 0x9800 },
2379                 { 0x04, 0x9000 },
2380
2381                 { 0x03, 0xdf01 },
2382                 { 0x02, 0xdf20 },
2383                 { 0x01, 0xff95 },
2384                 { 0x00, 0xba00 },
2385                 { 0x04, 0xa800 },
2386                 { 0x04, 0xa000 },
2387
2388                 { 0x03, 0xff41 },
2389                 { 0x02, 0xdf20 },
2390                 { 0x01, 0x0140 },
2391                 { 0x00, 0x00bb },
2392                 { 0x04, 0xb800 },
2393                 { 0x04, 0xb000 },
2394
2395                 { 0x03, 0xdf41 },
2396                 { 0x02, 0xdc60 },
2397                 { 0x01, 0x6340 },
2398                 { 0x00, 0x007d },
2399                 { 0x04, 0xd800 },
2400                 { 0x04, 0xd000 },
2401
2402                 { 0x03, 0xdf01 },
2403                 { 0x02, 0xdf20 },
2404                 { 0x01, 0x100a },
2405                 { 0x00, 0xa0ff },
2406                 { 0x04, 0xf800 },
2407                 { 0x04, 0xf000 },
2408
2409                 { 0x1f, 0x0000 },
2410                 { 0x0b, 0x0000 },
2411                 { 0x00, 0x9200 }
2412         };
2413
2414         rtl_writephy_batch(tp, phy_reg_init);
2415 }
2416
2417 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2418 {
2419         phy_write_paged(tp->phydev, 0x0002, 0x01, 0x90d0);
2420 }
2421
2422 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2423 {
2424         struct pci_dev *pdev = tp->pci_dev;
2425
2426         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2427             (pdev->subsystem_device != 0xe000))
2428                 return;
2429
2430         phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2431 }
2432
2433 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2434 {
2435         static const struct phy_reg phy_reg_init[] = {
2436                 { 0x1f, 0x0001 },
2437                 { 0x04, 0x0000 },
2438                 { 0x03, 0x00a1 },
2439                 { 0x02, 0x0008 },
2440                 { 0x01, 0x0120 },
2441                 { 0x00, 0x1000 },
2442                 { 0x04, 0x0800 },
2443                 { 0x04, 0x9000 },
2444                 { 0x03, 0x802f },
2445                 { 0x02, 0x4f02 },
2446                 { 0x01, 0x0409 },
2447                 { 0x00, 0xf099 },
2448                 { 0x04, 0x9800 },
2449                 { 0x04, 0xa000 },
2450                 { 0x03, 0xdf01 },
2451                 { 0x02, 0xdf20 },
2452                 { 0x01, 0xff95 },
2453                 { 0x00, 0xba00 },
2454                 { 0x04, 0xa800 },
2455                 { 0x04, 0xf000 },
2456                 { 0x03, 0xdf01 },
2457                 { 0x02, 0xdf20 },
2458                 { 0x01, 0x101a },
2459                 { 0x00, 0xa0ff },
2460                 { 0x04, 0xf800 },
2461                 { 0x04, 0x0000 },
2462                 { 0x1f, 0x0000 },
2463
2464                 { 0x1f, 0x0001 },
2465                 { 0x10, 0xf41b },
2466                 { 0x14, 0xfb54 },
2467                 { 0x18, 0xf5c7 },
2468                 { 0x1f, 0x0000 },
2469
2470                 { 0x1f, 0x0001 },
2471                 { 0x17, 0x0cc0 },
2472                 { 0x1f, 0x0000 }
2473         };
2474
2475         rtl_writephy_batch(tp, phy_reg_init);
2476
2477         rtl8169scd_hw_phy_config_quirk(tp);
2478 }
2479
2480 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2481 {
2482         static const struct phy_reg phy_reg_init[] = {
2483                 { 0x1f, 0x0001 },
2484                 { 0x04, 0x0000 },
2485                 { 0x03, 0x00a1 },
2486                 { 0x02, 0x0008 },
2487                 { 0x01, 0x0120 },
2488                 { 0x00, 0x1000 },
2489                 { 0x04, 0x0800 },
2490                 { 0x04, 0x9000 },
2491                 { 0x03, 0x802f },
2492                 { 0x02, 0x4f02 },
2493                 { 0x01, 0x0409 },
2494                 { 0x00, 0xf099 },
2495                 { 0x04, 0x9800 },
2496                 { 0x04, 0xa000 },
2497                 { 0x03, 0xdf01 },
2498                 { 0x02, 0xdf20 },
2499                 { 0x01, 0xff95 },
2500                 { 0x00, 0xba00 },
2501                 { 0x04, 0xa800 },
2502                 { 0x04, 0xf000 },
2503                 { 0x03, 0xdf01 },
2504                 { 0x02, 0xdf20 },
2505                 { 0x01, 0x101a },
2506                 { 0x00, 0xa0ff },
2507                 { 0x04, 0xf800 },
2508                 { 0x04, 0x0000 },
2509                 { 0x1f, 0x0000 },
2510
2511                 { 0x1f, 0x0001 },
2512                 { 0x0b, 0x8480 },
2513                 { 0x1f, 0x0000 },
2514
2515                 { 0x1f, 0x0001 },
2516                 { 0x18, 0x67c7 },
2517                 { 0x04, 0x2000 },
2518                 { 0x03, 0x002f },
2519                 { 0x02, 0x4360 },
2520                 { 0x01, 0x0109 },
2521                 { 0x00, 0x3022 },
2522                 { 0x04, 0x2800 },
2523                 { 0x1f, 0x0000 },
2524
2525                 { 0x1f, 0x0001 },
2526                 { 0x17, 0x0cc0 },
2527                 { 0x1f, 0x0000 }
2528         };
2529
2530         rtl_writephy_batch(tp, phy_reg_init);
2531 }
2532
2533 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2534 {
2535         rtl_writephy(tp, 0x1f, 0x0001);
2536         rtl_patchphy(tp, 0x16, 1 << 0);
2537         rtl_writephy(tp, 0x10, 0xf41b);
2538         rtl_writephy(tp, 0x1f, 0x0000);
2539 }
2540
2541 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2542 {
2543         phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf41b);
2544 }
2545
2546 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2547 {
2548         phy_write(tp->phydev, 0x1d, 0x0f00);
2549         phy_write_paged(tp->phydev, 0x0002, 0x0c, 0x1ec8);
2550 }
2551
2552 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2553 {
2554         phy_set_bits(tp->phydev, 0x14, BIT(5));
2555         phy_set_bits(tp->phydev, 0x0d, BIT(5));
2556         phy_write_paged(tp->phydev, 0x0001, 0x1d, 0x3d98);
2557 }
2558
2559 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2560 {
2561         static const struct phy_reg phy_reg_init[] = {
2562                 { 0x1f, 0x0001 },
2563                 { 0x12, 0x2300 },
2564                 { 0x1f, 0x0002 },
2565                 { 0x00, 0x88d4 },
2566                 { 0x01, 0x82b1 },
2567                 { 0x03, 0x7002 },
2568                 { 0x08, 0x9e30 },
2569                 { 0x09, 0x01f0 },
2570                 { 0x0a, 0x5500 },
2571                 { 0x0c, 0x00c8 },
2572                 { 0x1f, 0x0003 },
2573                 { 0x12, 0xc096 },
2574                 { 0x16, 0x000a },
2575                 { 0x1f, 0x0000 },
2576                 { 0x1f, 0x0000 },
2577                 { 0x09, 0x2000 },
2578                 { 0x09, 0x0000 }
2579         };
2580
2581         rtl_writephy_batch(tp, phy_reg_init);
2582
2583         rtl_patchphy(tp, 0x14, 1 << 5);
2584         rtl_patchphy(tp, 0x0d, 1 << 5);
2585         rtl_writephy(tp, 0x1f, 0x0000);
2586 }
2587
2588 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2589 {
2590         static const struct phy_reg phy_reg_init[] = {
2591                 { 0x1f, 0x0001 },
2592                 { 0x12, 0x2300 },
2593                 { 0x03, 0x802f },
2594                 { 0x02, 0x4f02 },
2595                 { 0x01, 0x0409 },
2596                 { 0x00, 0xf099 },
2597                 { 0x04, 0x9800 },
2598                 { 0x04, 0x9000 },
2599                 { 0x1d, 0x3d98 },
2600                 { 0x1f, 0x0002 },
2601                 { 0x0c, 0x7eb8 },
2602                 { 0x06, 0x0761 },
2603                 { 0x1f, 0x0003 },
2604                 { 0x16, 0x0f0a },
2605                 { 0x1f, 0x0000 }
2606         };
2607
2608         rtl_writephy_batch(tp, phy_reg_init);
2609
2610         rtl_patchphy(tp, 0x16, 1 << 0);
2611         rtl_patchphy(tp, 0x14, 1 << 5);
2612         rtl_patchphy(tp, 0x0d, 1 << 5);
2613         rtl_writephy(tp, 0x1f, 0x0000);
2614 }
2615
2616 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2617 {
2618         static const struct phy_reg phy_reg_init[] = {
2619                 { 0x1f, 0x0001 },
2620                 { 0x12, 0x2300 },
2621                 { 0x1d, 0x3d98 },
2622                 { 0x1f, 0x0002 },
2623                 { 0x0c, 0x7eb8 },
2624                 { 0x06, 0x5461 },
2625                 { 0x1f, 0x0003 },
2626                 { 0x16, 0x0f0a },
2627                 { 0x1f, 0x0000 }
2628         };
2629
2630         rtl_writephy_batch(tp, phy_reg_init);
2631
2632         rtl_patchphy(tp, 0x16, 1 << 0);
2633         rtl_patchphy(tp, 0x14, 1 << 5);
2634         rtl_patchphy(tp, 0x0d, 1 << 5);
2635         rtl_writephy(tp, 0x1f, 0x0000);
2636 }
2637
2638 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2639         /* Channel Estimation */
2640         { 0x1f, 0x0001 },
2641         { 0x06, 0x4064 },
2642         { 0x07, 0x2863 },
2643         { 0x08, 0x059c },
2644         { 0x09, 0x26b4 },
2645         { 0x0a, 0x6a19 },
2646         { 0x0b, 0xdcc8 },
2647         { 0x10, 0xf06d },
2648         { 0x14, 0x7f68 },
2649         { 0x18, 0x7fd9 },
2650         { 0x1c, 0xf0ff },
2651         { 0x1d, 0x3d9c },
2652         { 0x1f, 0x0003 },
2653         { 0x12, 0xf49f },
2654         { 0x13, 0x070b },
2655         { 0x1a, 0x05ad },
2656         { 0x14, 0x94c0 },
2657
2658         /*
2659          * Tx Error Issue
2660          * Enhance line driver power
2661          */
2662         { 0x1f, 0x0002 },
2663         { 0x06, 0x5561 },
2664         { 0x1f, 0x0005 },
2665         { 0x05, 0x8332 },
2666         { 0x06, 0x5561 },
2667
2668         /*
2669          * Can not link to 1Gbps with bad cable
2670          * Decrease SNR threshold form 21.07dB to 19.04dB
2671          */
2672         { 0x1f, 0x0001 },
2673         { 0x17, 0x0cc0 },
2674
2675         { 0x1f, 0x0000 },
2676         { 0x0d, 0xf880 }
2677 };
2678
2679 static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2680         { 0x1f, 0x0002 },
2681         { 0x05, 0x669a },
2682         { 0x1f, 0x0005 },
2683         { 0x05, 0x8330 },
2684         { 0x06, 0x669a },
2685         { 0x1f, 0x0002 }
2686 };
2687
2688 static void rtl8168d_apply_firmware_cond(struct rtl8169_private *tp, u16 val)
2689 {
2690         u16 reg_val;
2691
2692         rtl_writephy(tp, 0x1f, 0x0005);
2693         rtl_writephy(tp, 0x05, 0x001b);
2694         reg_val = rtl_readphy(tp, 0x06);
2695         rtl_writephy(tp, 0x1f, 0x0000);
2696
2697         if (reg_val != val)
2698                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2699         else
2700                 rtl_apply_firmware(tp);
2701 }
2702
2703 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2704 {
2705         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2706
2707         /*
2708          * Rx Error Issue
2709          * Fine Tune Switching regulator parameter
2710          */
2711         rtl_writephy(tp, 0x1f, 0x0002);
2712         rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2713         rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2714
2715         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2716                 int val;
2717
2718                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2719
2720                 val = rtl_readphy(tp, 0x0d);
2721
2722                 if ((val & 0x00ff) != 0x006c) {
2723                         static const u32 set[] = {
2724                                 0x0065, 0x0066, 0x0067, 0x0068,
2725                                 0x0069, 0x006a, 0x006b, 0x006c
2726                         };
2727                         int i;
2728
2729                         rtl_writephy(tp, 0x1f, 0x0002);
2730
2731                         val &= 0xff00;
2732                         for (i = 0; i < ARRAY_SIZE(set); i++)
2733                                 rtl_writephy(tp, 0x0d, val | set[i]);
2734                 }
2735         } else {
2736                 phy_write_paged(tp->phydev, 0x0002, 0x05, 0x6662);
2737                 r8168d_phy_param(tp->phydev, 0x8330, 0xffff, 0x6662);
2738         }
2739
2740         /* RSET couple improve */
2741         rtl_writephy(tp, 0x1f, 0x0002);
2742         rtl_patchphy(tp, 0x0d, 0x0300);
2743         rtl_patchphy(tp, 0x0f, 0x0010);
2744
2745         /* Fine tune PLL performance */
2746         rtl_writephy(tp, 0x1f, 0x0002);
2747         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2748         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2749         rtl_writephy(tp, 0x1f, 0x0000);
2750
2751         rtl8168d_apply_firmware_cond(tp, 0xbf00);
2752 }
2753
2754 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2755 {
2756         rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2757
2758         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2759                 int val;
2760
2761                 rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2762
2763                 val = rtl_readphy(tp, 0x0d);
2764                 if ((val & 0x00ff) != 0x006c) {
2765                         static const u32 set[] = {
2766                                 0x0065, 0x0066, 0x0067, 0x0068,
2767                                 0x0069, 0x006a, 0x006b, 0x006c
2768                         };
2769                         int i;
2770
2771                         rtl_writephy(tp, 0x1f, 0x0002);
2772
2773                         val &= 0xff00;
2774                         for (i = 0; i < ARRAY_SIZE(set); i++)
2775                                 rtl_writephy(tp, 0x0d, val | set[i]);
2776                 }
2777         } else {
2778                 phy_write_paged(tp->phydev, 0x0002, 0x05, 0x2642);
2779                 r8168d_phy_param(tp->phydev, 0x8330, 0xffff, 0x2642);
2780         }
2781
2782         /* Fine tune PLL performance */
2783         rtl_writephy(tp, 0x1f, 0x0002);
2784         rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2785         rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2786
2787         /* Switching regulator Slew rate */
2788         rtl_writephy(tp, 0x1f, 0x0002);
2789         rtl_patchphy(tp, 0x0f, 0x0017);
2790         rtl_writephy(tp, 0x1f, 0x0000);
2791
2792         rtl8168d_apply_firmware_cond(tp, 0xb300);
2793 }
2794
2795 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2796 {
2797         static const struct phy_reg phy_reg_init[] = {
2798                 { 0x1f, 0x0002 },
2799                 { 0x10, 0x0008 },
2800                 { 0x0d, 0x006c },
2801
2802                 { 0x1f, 0x0000 },
2803                 { 0x0d, 0xf880 },
2804
2805                 { 0x1f, 0x0001 },
2806                 { 0x17, 0x0cc0 },
2807
2808                 { 0x1f, 0x0001 },
2809                 { 0x0b, 0xa4d8 },
2810                 { 0x09, 0x281c },
2811                 { 0x07, 0x2883 },
2812                 { 0x0a, 0x6b35 },
2813                 { 0x1d, 0x3da4 },
2814                 { 0x1c, 0xeffd },
2815                 { 0x14, 0x7f52 },
2816                 { 0x18, 0x7fc6 },
2817                 { 0x08, 0x0601 },
2818                 { 0x06, 0x4063 },
2819                 { 0x10, 0xf074 },
2820                 { 0x1f, 0x0003 },
2821                 { 0x13, 0x0789 },
2822                 { 0x12, 0xf4bd },
2823                 { 0x1a, 0x04fd },
2824                 { 0x14, 0x84b0 },
2825                 { 0x1f, 0x0000 },
2826                 { 0x00, 0x9200 },
2827
2828                 { 0x1f, 0x0005 },
2829                 { 0x01, 0x0340 },
2830                 { 0x1f, 0x0001 },
2831                 { 0x04, 0x4000 },
2832                 { 0x03, 0x1d21 },
2833                 { 0x02, 0x0c32 },
2834                 { 0x01, 0x0200 },
2835                 { 0x00, 0x5554 },
2836                 { 0x04, 0x4800 },
2837                 { 0x04, 0x4000 },
2838                 { 0x04, 0xf000 },
2839                 { 0x03, 0xdf01 },
2840                 { 0x02, 0xdf20 },
2841                 { 0x01, 0x101a },
2842                 { 0x00, 0xa0ff },
2843                 { 0x04, 0xf800 },
2844                 { 0x04, 0xf000 },
2845                 { 0x1f, 0x0000 },
2846         };
2847
2848         rtl_writephy_batch(tp, phy_reg_init);
2849
2850         r8168d_modify_extpage(tp->phydev, 0x0023, 0x16, 0xffff, 0x0000);
2851 }
2852
2853 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2854 {
2855         phy_write_paged(tp->phydev, 0x0001, 0x17, 0x0cc0);
2856         r8168d_modify_extpage(tp->phydev, 0x002d, 0x18, 0xffff, 0x0040);
2857         phy_set_bits(tp->phydev, 0x0d, BIT(5));
2858 }
2859
2860 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2861 {
2862         static const struct phy_reg phy_reg_init[] = {
2863                 /* Channel estimation fine tune */
2864                 { 0x1f, 0x0001 },
2865                 { 0x0b, 0x6c20 },
2866                 { 0x07, 0x2872 },
2867                 { 0x1c, 0xefff },
2868                 { 0x1f, 0x0003 },
2869                 { 0x14, 0x6420 },
2870                 { 0x1f, 0x0000 },
2871         };
2872         struct phy_device *phydev = tp->phydev;
2873
2874         rtl_apply_firmware(tp);
2875
2876         /* Enable Delay cap */
2877         r8168d_phy_param(phydev, 0x8b80, 0xffff, 0xc896);
2878
2879         rtl_writephy_batch(tp, phy_reg_init);
2880
2881         /* Update PFM & 10M TX idle timer */
2882         r8168d_modify_extpage(phydev, 0x002f, 0x15, 0xffff, 0x1919);
2883
2884         r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006);
2885
2886         /* DCO enable for 10M IDLE Power */
2887         r8168d_modify_extpage(phydev, 0x0023, 0x17, 0x0000, 0x0006);
2888
2889         /* For impedance matching */
2890         phy_modify_paged(phydev, 0x0002, 0x08, 0x7f00, 0x8000);
2891
2892         /* PHY auto speed down */
2893         r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0050);
2894         phy_set_bits(phydev, 0x14, BIT(15));
2895
2896         r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001);
2897         r8168d_phy_param(phydev, 0x8b85, 0x2000, 0x0000);
2898
2899         r8168d_modify_extpage(phydev, 0x0020, 0x15, 0x1100, 0x0000);
2900         phy_write_paged(phydev, 0x0006, 0x00, 0x5a00);
2901
2902         phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0000);
2903 }
2904
2905 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2906 {
2907         const u16 w[] = {
2908                 addr[0] | (addr[1] << 8),
2909                 addr[2] | (addr[3] << 8),
2910                 addr[4] | (addr[5] << 8)
2911         };
2912
2913         rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2914         rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2915         rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2916         rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2917 }
2918
2919 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2920 {
2921         struct phy_device *phydev = tp->phydev;
2922
2923         rtl_apply_firmware(tp);
2924
2925         /* Enable Delay cap */
2926         r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006);
2927
2928         /* Channel estimation fine tune */
2929         phy_write_paged(phydev, 0x0003, 0x09, 0xa20f);
2930
2931         /* Green Setting */
2932         r8168d_phy_param(phydev, 0x8b5b, 0xffff, 0x9222);
2933         r8168d_phy_param(phydev, 0x8b6d, 0xffff, 0x8000);
2934         r8168d_phy_param(phydev, 0x8b76, 0xffff, 0x8000);
2935
2936         /* For 4-corner performance improve */
2937         rtl_writephy(tp, 0x1f, 0x0005);
2938         rtl_writephy(tp, 0x05, 0x8b80);
2939         rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2940         rtl_writephy(tp, 0x1f, 0x0000);
2941
2942         /* PHY auto speed down */
2943         r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010);
2944         phy_set_bits(phydev, 0x14, BIT(15));
2945
2946         /* improve 10M EEE waveform */
2947         r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001);
2948
2949         /* Improve 2-pair detection performance */
2950         r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000);
2951
2952         rtl8168f_config_eee_phy(tp);
2953         rtl_enable_eee(tp);
2954
2955         /* Green feature */
2956         rtl_writephy(tp, 0x1f, 0x0003);
2957         rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
2958         rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
2959         rtl_writephy(tp, 0x1f, 0x0000);
2960         rtl_writephy(tp, 0x1f, 0x0005);
2961         rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
2962         rtl_writephy(tp, 0x1f, 0x0000);
2963
2964         /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
2965         rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
2966 }
2967
2968 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
2969 {
2970         struct phy_device *phydev = tp->phydev;
2971
2972         /* For 4-corner performance improve */
2973         r8168d_phy_param(phydev, 0x8b80, 0x0000, 0x0006);
2974
2975         /* PHY auto speed down */
2976         r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010);
2977         phy_set_bits(phydev, 0x14, BIT(15));
2978
2979         /* Improve 10M EEE waveform */
2980         r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001);
2981
2982         rtl8168f_config_eee_phy(tp);
2983         rtl_enable_eee(tp);
2984 }
2985
2986 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
2987 {
2988         struct phy_device *phydev = tp->phydev;
2989
2990         rtl_apply_firmware(tp);
2991
2992         /* Channel estimation fine tune */
2993         phy_write_paged(phydev, 0x0003, 0x09, 0xa20f);
2994
2995         /* Modify green table for giga & fnet */
2996         r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000);
2997         r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000);
2998         r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000);
2999         r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000);
3000         r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000);
3001         r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00fb);
3002
3003         /* Modify green table for 10M */
3004         r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00);
3005
3006         /* Disable hiimpedance detection (RTCT) */
3007         phy_write_paged(phydev, 0x0003, 0x01, 0x328a);
3008
3009         rtl8168f_hw_phy_config(tp);
3010
3011         /* Improve 2-pair detection performance */
3012         r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000);
3013 }
3014
3015 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3016 {
3017         rtl_apply_firmware(tp);
3018
3019         rtl8168f_hw_phy_config(tp);
3020 }
3021
3022 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3023 {
3024         struct phy_device *phydev = tp->phydev;
3025
3026         rtl_apply_firmware(tp);
3027
3028         rtl8168f_hw_phy_config(tp);
3029
3030         /* Improve 2-pair detection performance */
3031         r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000);
3032
3033         /* Channel estimation fine tune */
3034         phy_write_paged(phydev, 0x0003, 0x09, 0xa20f);
3035
3036         /* Modify green table for giga & fnet */
3037         r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000);
3038         r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000);
3039         r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000);
3040         r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000);
3041         r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000);
3042         r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00aa);
3043
3044         /* Modify green table for 10M */
3045         r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00);
3046
3047         /* Disable hiimpedance detection (RTCT) */
3048         phy_write_paged(phydev, 0x0003, 0x01, 0x328a);
3049
3050         /* Modify green table for giga */
3051         r8168d_phy_param(phydev, 0x8b54, 0x0800, 0x0000);
3052         r8168d_phy_param(phydev, 0x8b5d, 0x0800, 0x0000);
3053         r8168d_phy_param(phydev, 0x8a7c, 0x0100, 0x0000);
3054         r8168d_phy_param(phydev, 0x8a7f, 0x0000, 0x0100);
3055         r8168d_phy_param(phydev, 0x8a82, 0x0100, 0x0000);
3056         r8168d_phy_param(phydev, 0x8a85, 0x0100, 0x0000);
3057         r8168d_phy_param(phydev, 0x8a88, 0x0100, 0x0000);
3058
3059         /* uc same-seed solution */
3060         r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x8000);
3061
3062         /* Green feature */
3063         rtl_writephy(tp, 0x1f, 0x0003);
3064         rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3065         rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3066         rtl_writephy(tp, 0x1f, 0x0000);
3067 }
3068
3069 static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3070 {
3071         phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3072 }
3073
3074 static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3075 {
3076         struct phy_device *phydev = tp->phydev;
3077
3078         phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3079         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3080         r8168g_phy_param(phydev, 0x8084, 0x6000, 0x0000);
3081         phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x1003);
3082 }
3083
3084 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3085 {
3086         int ret;
3087
3088         rtl_apply_firmware(tp);
3089
3090         ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3091         if (ret & BIT(8))
3092                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3093         else
3094                 phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3095
3096         ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3097         if (ret & BIT(8))
3098                 phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
3099         else
3100                 phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
3101
3102         /* Enable PHY auto speed down */
3103         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3104
3105         rtl8168g_phy_adjust_10m_aldps(tp);
3106
3107         /* EEE auto-fallback function */
3108         phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3109
3110         /* Enable UC LPF tune function */
3111         r8168g_phy_param(tp->phydev, 0x8012, 0x0000, 0x8000);
3112
3113         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3114
3115         /* Improve SWR Efficiency */
3116         rtl_writephy(tp, 0x1f, 0x0bcd);
3117         rtl_writephy(tp, 0x14, 0x5065);
3118         rtl_writephy(tp, 0x14, 0xd065);
3119         rtl_writephy(tp, 0x1f, 0x0bc8);
3120         rtl_writephy(tp, 0x11, 0x5655);
3121         rtl_writephy(tp, 0x1f, 0x0bcd);
3122         rtl_writephy(tp, 0x14, 0x1065);
3123         rtl_writephy(tp, 0x14, 0x9065);
3124         rtl_writephy(tp, 0x14, 0x1065);
3125         rtl_writephy(tp, 0x1f, 0x0000);
3126
3127         rtl8168g_disable_aldps(tp);
3128         rtl8168g_config_eee_phy(tp);
3129         rtl_enable_eee(tp);
3130 }
3131
3132 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3133 {
3134         rtl_apply_firmware(tp);
3135         rtl8168g_config_eee_phy(tp);
3136         rtl_enable_eee(tp);
3137 }
3138
3139 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3140 {
3141         struct phy_device *phydev = tp->phydev;
3142         u16 dout_tapbin;
3143         u32 data;
3144
3145         rtl_apply_firmware(tp);
3146
3147         /* CHN EST parameters adjust - giga master */
3148         r8168g_phy_param(phydev, 0x809b, 0xf800, 0x8000);
3149         r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x8000);
3150         r8168g_phy_param(phydev, 0x80a4, 0xff00, 0x8500);
3151         r8168g_phy_param(phydev, 0x809c, 0xff00, 0xbd00);
3152
3153         /* CHN EST parameters adjust - giga slave */
3154         r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x7000);
3155         r8168g_phy_param(phydev, 0x80b4, 0xff00, 0x5000);
3156         r8168g_phy_param(phydev, 0x80ac, 0xff00, 0x4000);
3157
3158         /* CHN EST parameters adjust - fnet */
3159         r8168g_phy_param(phydev, 0x808e, 0xff00, 0x1200);
3160         r8168g_phy_param(phydev, 0x8090, 0xff00, 0xe500);
3161         r8168g_phy_param(phydev, 0x8092, 0xff00, 0x9f00);
3162
3163         /* enable R-tune & PGA-retune function */
3164         dout_tapbin = 0;
3165         data = phy_read_paged(phydev, 0x0a46, 0x13);
3166         data &= 3;
3167         data <<= 2;
3168         dout_tapbin |= data;
3169         data = phy_read_paged(phydev, 0x0a46, 0x12);
3170         data &= 0xc000;
3171         data >>= 14;
3172         dout_tapbin |= data;
3173         dout_tapbin = ~(dout_tapbin^0x08);
3174         dout_tapbin <<= 12;
3175         dout_tapbin &= 0xf000;
3176
3177         r8168g_phy_param(phydev, 0x827a, 0xf000, dout_tapbin);
3178         r8168g_phy_param(phydev, 0x827b, 0xf000, dout_tapbin);
3179         r8168g_phy_param(phydev, 0x827c, 0xf000, dout_tapbin);
3180         r8168g_phy_param(phydev, 0x827d, 0xf000, dout_tapbin);
3181         r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800);
3182         phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002);
3183
3184         /* enable GPHY 10M */
3185         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3186
3187         /* SAR ADC performance */
3188         phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3189
3190         r8168g_phy_param(phydev, 0x803f, 0x3000, 0x0000);
3191         r8168g_phy_param(phydev, 0x8047, 0x3000, 0x0000);
3192         r8168g_phy_param(phydev, 0x804f, 0x3000, 0x0000);
3193         r8168g_phy_param(phydev, 0x8057, 0x3000, 0x0000);
3194         r8168g_phy_param(phydev, 0x805f, 0x3000, 0x0000);
3195         r8168g_phy_param(phydev, 0x8067, 0x3000, 0x0000);
3196         r8168g_phy_param(phydev, 0x806f, 0x3000, 0x0000);
3197
3198         /* disable phy pfm mode */
3199         phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3200
3201         rtl8168g_disable_aldps(tp);
3202         rtl8168h_config_eee_phy(tp);
3203         rtl_enable_eee(tp);
3204 }
3205
3206 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3207 {
3208         u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3209         struct phy_device *phydev = tp->phydev;
3210         u16 rlen;
3211         u32 data;
3212
3213         rtl_apply_firmware(tp);
3214
3215         /* CHIN EST parameter update */
3216         r8168g_phy_param(phydev, 0x808a, 0x003f, 0x000a);
3217
3218         /* enable R-tune & PGA-retune function */
3219         r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800);
3220         phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002);
3221
3222         /* enable GPHY 10M */
3223         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3224
3225         r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3226         data = r8168_mac_ocp_read(tp, 0xdd02);
3227         ioffset_p3 = ((data & 0x80)>>7);
3228         ioffset_p3 <<= 3;
3229
3230         data = r8168_mac_ocp_read(tp, 0xdd00);
3231         ioffset_p3 |= ((data & (0xe000))>>13);
3232         ioffset_p2 = ((data & (0x1e00))>>9);
3233         ioffset_p1 = ((data & (0x01e0))>>5);
3234         ioffset_p0 = ((data & 0x0010)>>4);
3235         ioffset_p0 <<= 3;
3236         ioffset_p0 |= (data & (0x07));
3237         data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3238
3239         if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3240             (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f))
3241                 phy_write_paged(phydev, 0x0bcf, 0x16, data);
3242
3243         /* Modify rlen (TX LPF corner frequency) level */
3244         data = phy_read_paged(phydev, 0x0bcd, 0x16);
3245         data &= 0x000f;
3246         rlen = 0;
3247         if (data > 3)
3248                 rlen = data - 3;
3249         data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3250         phy_write_paged(phydev, 0x0bcd, 0x17, data);
3251
3252         /* disable phy pfm mode */
3253         phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0);
3254
3255         rtl8168g_disable_aldps(tp);
3256         rtl8168g_config_eee_phy(tp);
3257         rtl_enable_eee(tp);
3258 }
3259
3260 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3261 {
3262         struct phy_device *phydev = tp->phydev;
3263
3264         /* Enable PHY auto speed down */
3265         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3266
3267         rtl8168g_phy_adjust_10m_aldps(tp);
3268
3269         /* Enable EEE auto-fallback function */
3270         phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2));
3271
3272         /* Enable UC LPF tune function */
3273         r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
3274
3275         /* set rg_sel_sdm_rate */
3276         phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3277
3278         rtl8168g_disable_aldps(tp);
3279         rtl8168g_config_eee_phy(tp);
3280         rtl_enable_eee(tp);
3281 }
3282
3283 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3284 {
3285         struct phy_device *phydev = tp->phydev;
3286
3287         rtl8168g_phy_adjust_10m_aldps(tp);
3288
3289         /* Enable UC LPF tune function */
3290         r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
3291
3292         /* Set rg_sel_sdm_rate */
3293         phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3294
3295         /* Channel estimation parameters */
3296         r8168g_phy_param(phydev, 0x80f3, 0xff00, 0x8b00);
3297         r8168g_phy_param(phydev, 0x80f0, 0xff00, 0x3a00);
3298         r8168g_phy_param(phydev, 0x80ef, 0xff00, 0x0500);
3299         r8168g_phy_param(phydev, 0x80f6, 0xff00, 0x6e00);
3300         r8168g_phy_param(phydev, 0x80ec, 0xff00, 0x6800);
3301         r8168g_phy_param(phydev, 0x80ed, 0xff00, 0x7c00);
3302         r8168g_phy_param(phydev, 0x80f2, 0xff00, 0xf400);
3303         r8168g_phy_param(phydev, 0x80f4, 0xff00, 0x8500);
3304         r8168g_phy_param(phydev, 0x8110, 0xff00, 0xa800);
3305         r8168g_phy_param(phydev, 0x810f, 0xff00, 0x1d00);
3306         r8168g_phy_param(phydev, 0x8111, 0xff00, 0xf500);
3307         r8168g_phy_param(phydev, 0x8113, 0xff00, 0x6100);
3308         r8168g_phy_param(phydev, 0x8115, 0xff00, 0x9200);
3309         r8168g_phy_param(phydev, 0x810e, 0xff00, 0x0400);
3310         r8168g_phy_param(phydev, 0x810c, 0xff00, 0x7c00);
3311         r8168g_phy_param(phydev, 0x810b, 0xff00, 0x5a00);
3312         r8168g_phy_param(phydev, 0x80d1, 0xff00, 0xff00);
3313         r8168g_phy_param(phydev, 0x80cd, 0xff00, 0x9e00);
3314         r8168g_phy_param(phydev, 0x80d3, 0xff00, 0x0e00);
3315         r8168g_phy_param(phydev, 0x80d5, 0xff00, 0xca00);
3316         r8168g_phy_param(phydev, 0x80d7, 0xff00, 0x8400);
3317
3318         /* Force PWM-mode */
3319         rtl_writephy(tp, 0x1f, 0x0bcd);
3320         rtl_writephy(tp, 0x14, 0x5065);
3321         rtl_writephy(tp, 0x14, 0xd065);
3322         rtl_writephy(tp, 0x1f, 0x0bc8);
3323         rtl_writephy(tp, 0x12, 0x00ed);
3324         rtl_writephy(tp, 0x1f, 0x0bcd);
3325         rtl_writephy(tp, 0x14, 0x1065);
3326         rtl_writephy(tp, 0x14, 0x9065);
3327         rtl_writephy(tp, 0x14, 0x1065);
3328         rtl_writephy(tp, 0x1f, 0x0000);
3329
3330         rtl8168g_disable_aldps(tp);
3331         rtl8168g_config_eee_phy(tp);
3332         rtl_enable_eee(tp);
3333 }
3334
3335 static void rtl8117_hw_phy_config(struct rtl8169_private *tp)
3336 {
3337         struct phy_device *phydev = tp->phydev;
3338
3339         /* CHN EST parameters adjust - fnet */
3340         r8168g_phy_param(phydev, 0x808e, 0xff00, 0x4800);
3341         r8168g_phy_param(phydev, 0x8090, 0xff00, 0xcc00);
3342         r8168g_phy_param(phydev, 0x8092, 0xff00, 0xb000);
3343
3344         r8168g_phy_param(phydev, 0x8088, 0xff00, 0x6000);
3345         r8168g_phy_param(phydev, 0x808b, 0x3f00, 0x0b00);
3346         r8168g_phy_param(phydev, 0x808d, 0x1f00, 0x0600);
3347         r8168g_phy_param(phydev, 0x808c, 0xff00, 0xb000);
3348         r8168g_phy_param(phydev, 0x80a0, 0xff00, 0x2800);
3349         r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x5000);
3350         r8168g_phy_param(phydev, 0x809b, 0xf800, 0xb000);
3351         r8168g_phy_param(phydev, 0x809a, 0xff00, 0x4b00);
3352         r8168g_phy_param(phydev, 0x809d, 0x3f00, 0x0800);
3353         r8168g_phy_param(phydev, 0x80a1, 0xff00, 0x7000);
3354         r8168g_phy_param(phydev, 0x809f, 0x1f00, 0x0300);
3355         r8168g_phy_param(phydev, 0x809e, 0xff00, 0x8800);
3356         r8168g_phy_param(phydev, 0x80b2, 0xff00, 0x2200);
3357         r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x9800);
3358         r8168g_phy_param(phydev, 0x80af, 0x3f00, 0x0800);
3359         r8168g_phy_param(phydev, 0x80b3, 0xff00, 0x6f00);
3360         r8168g_phy_param(phydev, 0x80b1, 0x1f00, 0x0300);
3361         r8168g_phy_param(phydev, 0x80b0, 0xff00, 0x9300);
3362
3363         r8168g_phy_param(phydev, 0x8011, 0x0000, 0x0800);
3364
3365         /* enable GPHY 10M */
3366         phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3367
3368         r8168g_phy_param(phydev, 0x8016, 0x0000, 0x0400);
3369
3370         rtl8168g_disable_aldps(tp);
3371         rtl8168h_config_eee_phy(tp);
3372         rtl_enable_eee(tp);
3373 }
3374
3375 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3376 {
3377         static const struct phy_reg phy_reg_init[] = {
3378                 { 0x1f, 0x0003 },
3379                 { 0x08, 0x441d },
3380                 { 0x01, 0x9100 },
3381                 { 0x1f, 0x0000 }
3382         };
3383
3384         rtl_writephy(tp, 0x1f, 0x0000);
3385         rtl_patchphy(tp, 0x11, 1 << 12);
3386         rtl_patchphy(tp, 0x19, 1 << 13);
3387         rtl_patchphy(tp, 0x10, 1 << 15);
3388
3389         rtl_writephy_batch(tp, phy_reg_init);
3390 }
3391
3392 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3393 {
3394         /* Disable ALDPS before ram code */
3395         phy_write(tp->phydev, 0x18, 0x0310);
3396         msleep(100);
3397
3398         rtl_apply_firmware(tp);
3399
3400         phy_write_paged(tp->phydev, 0x0005, 0x1a, 0x0000);
3401         phy_write_paged(tp->phydev, 0x0004, 0x1c, 0x0000);
3402         phy_write_paged(tp->phydev, 0x0001, 0x15, 0x7701);
3403 }
3404
3405 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3406 {
3407         /* Disable ALDPS before setting firmware */
3408         phy_write(tp->phydev, 0x18, 0x0310);
3409         msleep(20);
3410
3411         rtl_apply_firmware(tp);
3412
3413         /* EEE setting */
3414         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3415         rtl_writephy(tp, 0x1f, 0x0004);
3416         rtl_writephy(tp, 0x10, 0x401f);
3417         rtl_writephy(tp, 0x19, 0x7030);
3418         rtl_writephy(tp, 0x1f, 0x0000);
3419 }
3420
3421 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3422 {
3423         static const struct phy_reg phy_reg_init[] = {
3424                 { 0x1f, 0x0004 },
3425                 { 0x10, 0xc07f },
3426                 { 0x19, 0x7030 },
3427                 { 0x1f, 0x0000 }
3428         };
3429
3430         /* Disable ALDPS before ram code */
3431         phy_write(tp->phydev, 0x18, 0x0310);
3432         msleep(100);
3433
3434         rtl_apply_firmware(tp);
3435
3436         rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3437         rtl_writephy_batch(tp, phy_reg_init);
3438
3439         rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3440 }
3441
3442 static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp)
3443 {
3444         struct phy_device *phydev = tp->phydev;
3445
3446         phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084);
3447         phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3448         phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006);
3449         phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3450         phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100);
3451         phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000);
3452         phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400);
3453         phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff);
3454         phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff);
3455
3456         r8168g_phy_param(phydev, 0x80ea, 0xff00, 0xc400);
3457         r8168g_phy_param(phydev, 0x80eb, 0x0700, 0x0300);
3458         r8168g_phy_param(phydev, 0x80f8, 0xff00, 0x1c00);
3459         r8168g_phy_param(phydev, 0x80f1, 0xff00, 0x3000);
3460         r8168g_phy_param(phydev, 0x80fe, 0xff00, 0xa500);
3461         r8168g_phy_param(phydev, 0x8102, 0xff00, 0x5000);
3462         r8168g_phy_param(phydev, 0x8105, 0xff00, 0x3300);
3463         r8168g_phy_param(phydev, 0x8100, 0xff00, 0x7000);
3464         r8168g_phy_param(phydev, 0x8104, 0xff00, 0xf000);
3465         r8168g_phy_param(phydev, 0x8106, 0xff00, 0x6500);
3466         r8168g_phy_param(phydev, 0x80dc, 0xff00, 0xed00);
3467         r8168g_phy_param(phydev, 0x80df, 0x0000, 0x0100);
3468         r8168g_phy_param(phydev, 0x80e1, 0x0100, 0x0000);
3469
3470         phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038);
3471         r8168g_phy_param(phydev, 0x819f, 0xffff, 0xd0b6);
3472
3473         phy_write_paged(phydev, 0xbc3, 0x12, 0x5555);
3474         phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00);
3475         phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000);
3476         phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
3477
3478         rtl8125_config_eee_phy(tp);
3479         rtl_enable_eee(tp);
3480 }
3481
3482 static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp)
3483 {
3484         struct phy_device *phydev = tp->phydev;
3485         int i;
3486
3487         phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3488         phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff);
3489         phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3490         phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000);
3491         phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002);
3492         phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044);
3493         phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000);
3494         phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000);
3495         phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002);
3496         phy_write_paged(phydev, 0xad4, 0x16, 0x00a8);
3497         phy_write_paged(phydev, 0xac5, 0x16, 0x01ff);
3498         phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030);
3499
3500         phy_write(phydev, 0x1f, 0x0b87);
3501         phy_write(phydev, 0x16, 0x80a2);
3502         phy_write(phydev, 0x17, 0x0153);
3503         phy_write(phydev, 0x16, 0x809c);
3504         phy_write(phydev, 0x17, 0x0153);
3505         phy_write(phydev, 0x1f, 0x0000);
3506
3507         phy_write(phydev, 0x1f, 0x0a43);
3508         phy_write(phydev, 0x13, 0x81B3);
3509         phy_write(phydev, 0x14, 0x0043);
3510         phy_write(phydev, 0x14, 0x00A7);
3511         phy_write(phydev, 0x14, 0x00D6);
3512         phy_write(phydev, 0x14, 0x00EC);
3513         phy_write(phydev, 0x14, 0x00F6);
3514         phy_write(phydev, 0x14, 0x00FB);
3515         phy_write(phydev, 0x14, 0x00FD);
3516         phy_write(phydev, 0x14, 0x00FF);
3517         phy_write(phydev, 0x14, 0x00BB);
3518         phy_write(phydev, 0x14, 0x0058);
3519         phy_write(phydev, 0x14, 0x0029);
3520         phy_write(phydev, 0x14, 0x0013);
3521         phy_write(phydev, 0x14, 0x0009);
3522         phy_write(phydev, 0x14, 0x0004);
3523         phy_write(phydev, 0x14, 0x0002);
3524         for (i = 0; i < 25; i++)
3525                 phy_write(phydev, 0x14, 0x0000);
3526         phy_write(phydev, 0x1f, 0x0000);
3527
3528         r8168g_phy_param(phydev, 0x8257, 0xffff, 0x020F);
3529         r8168g_phy_param(phydev, 0x80ea, 0xffff, 0x7843);
3530
3531         rtl_apply_firmware(tp);
3532
3533         phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000);
3534
3535         r8168g_phy_param(phydev, 0x81a2, 0x0000, 0x0100);
3536
3537         phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00);
3538         phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000);
3539         phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020);
3540         phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000);
3541         phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000);
3542         phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
3543
3544         rtl8125_config_eee_phy(tp);
3545         rtl_enable_eee(tp);
3546 }
3547
3548 static void rtl_hw_phy_config(struct net_device *dev)
3549 {
3550         static const rtl_generic_fct phy_configs[] = {
3551                 /* PCI devices. */
3552                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3553                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3554                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3555                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3556                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3557                 /* PCI-E devices. */
3558                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3559                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3560                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3561                 [RTL_GIGA_MAC_VER_10] = NULL,
3562                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3563                 [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3564                 [RTL_GIGA_MAC_VER_13] = NULL,
3565                 [RTL_GIGA_MAC_VER_14] = NULL,
3566                 [RTL_GIGA_MAC_VER_15] = NULL,
3567                 [RTL_GIGA_MAC_VER_16] = NULL,
3568                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3569                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3570                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3571                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3572                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3573                 [RTL_GIGA_MAC_VER_22] = rtl8168c_3_hw_phy_config,
3574                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3575                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3576                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3577                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3578                 [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3579                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3580                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3581                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3582                 [RTL_GIGA_MAC_VER_31] = NULL,
3583                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3584                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3585                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3586                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3587                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3588                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3589                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3590                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3591                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3592                 [RTL_GIGA_MAC_VER_41] = NULL,
3593                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3594                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3595                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3596                 [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3597                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3598                 [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3599                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3600                 [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3601                 [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3602                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3603                 [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config,
3604                 [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config,
3605                 [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config,
3606         };
3607         struct rtl8169_private *tp = netdev_priv(dev);
3608
3609         if (phy_configs[tp->mac_version])
3610                 phy_configs[tp->mac_version](tp);
3611 }
3612
3613 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3614 {
3615         if (!test_and_set_bit(flag, tp->wk.flags))
3616                 schedule_work(&tp->wk.work);
3617 }
3618
3619 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3620 {
3621         rtl_hw_phy_config(dev);
3622
3623         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3624                 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3625                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3626                 netif_dbg(tp, drv, dev,
3627                           "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3628                 RTL_W8(tp, 0x82, 0x01);
3629         }
3630
3631         /* We may have called phy_speed_down before */
3632         phy_speed_up(tp->phydev);
3633
3634         genphy_soft_reset(tp->phydev);
3635 }
3636
3637 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3638 {
3639         rtl_lock_work(tp);
3640
3641         rtl_unlock_config_regs(tp);
3642
3643         RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3644         RTL_R32(tp, MAC4);
3645
3646         RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3647         RTL_R32(tp, MAC0);
3648
3649         if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3650                 rtl_rar_exgmac_set(tp, addr);
3651
3652         rtl_lock_config_regs(tp);
3653
3654         rtl_unlock_work(tp);
3655 }
3656
3657 static int rtl_set_mac_address(struct net_device *dev, void *p)
3658 {
3659         struct rtl8169_private *tp = netdev_priv(dev);
3660         struct device *d = tp_to_dev(tp);
3661         int ret;
3662
3663         ret = eth_mac_addr(dev, p);
3664         if (ret)
3665                 return ret;
3666
3667         pm_runtime_get_noresume(d);
3668
3669         if (pm_runtime_active(d))
3670                 rtl_rar_set(tp, dev->dev_addr);
3671
3672         pm_runtime_put_noidle(d);
3673
3674         return 0;
3675 }
3676
3677 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3678 {
3679         struct rtl8169_private *tp = netdev_priv(dev);
3680
3681         if (!netif_running(dev))
3682                 return -ENODEV;
3683
3684         return phy_mii_ioctl(tp->phydev, ifr, cmd);
3685 }
3686
3687 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3688 {
3689         switch (tp->mac_version) {
3690         case RTL_GIGA_MAC_VER_25:
3691         case RTL_GIGA_MAC_VER_26:
3692         case RTL_GIGA_MAC_VER_29:
3693         case RTL_GIGA_MAC_VER_30:
3694         case RTL_GIGA_MAC_VER_32:
3695         case RTL_GIGA_MAC_VER_33:
3696         case RTL_GIGA_MAC_VER_34:
3697         case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_52:
3698                 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
3699                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3700                 break;
3701         default:
3702                 break;
3703         }
3704 }
3705
3706 static void rtl_pll_power_down(struct rtl8169_private *tp)
3707 {
3708         if (r8168_check_dash(tp))
3709                 return;
3710
3711         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3712             tp->mac_version == RTL_GIGA_MAC_VER_33)
3713                 rtl_ephy_write(tp, 0x19, 0xff64);
3714
3715         if (device_may_wakeup(tp_to_dev(tp))) {
3716                 phy_speed_down(tp->phydev, false);
3717                 rtl_wol_suspend_quirk(tp);
3718                 return;
3719         }
3720
3721         switch (tp->mac_version) {
3722         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3723         case RTL_GIGA_MAC_VER_37:
3724         case RTL_GIGA_MAC_VER_39:
3725         case RTL_GIGA_MAC_VER_43:
3726         case RTL_GIGA_MAC_VER_44:
3727         case RTL_GIGA_MAC_VER_45:
3728         case RTL_GIGA_MAC_VER_46:
3729         case RTL_GIGA_MAC_VER_47:
3730         case RTL_GIGA_MAC_VER_48:
3731         case RTL_GIGA_MAC_VER_50:
3732         case RTL_GIGA_MAC_VER_51:
3733         case RTL_GIGA_MAC_VER_52:
3734         case RTL_GIGA_MAC_VER_60:
3735         case RTL_GIGA_MAC_VER_61:
3736                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3737                 break;
3738         case RTL_GIGA_MAC_VER_40:
3739         case RTL_GIGA_MAC_VER_41:
3740         case RTL_GIGA_MAC_VER_49:
3741                 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3742                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3743                 break;
3744         default:
3745                 break;
3746         }
3747 }
3748
3749 static void rtl_pll_power_up(struct rtl8169_private *tp)
3750 {
3751         switch (tp->mac_version) {
3752         case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3753         case RTL_GIGA_MAC_VER_37:
3754         case RTL_GIGA_MAC_VER_39:
3755         case RTL_GIGA_MAC_VER_43:
3756                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
3757                 break;
3758         case RTL_GIGA_MAC_VER_44:
3759         case RTL_GIGA_MAC_VER_45:
3760         case RTL_GIGA_MAC_VER_46:
3761         case RTL_GIGA_MAC_VER_47:
3762         case RTL_GIGA_MAC_VER_48:
3763         case RTL_GIGA_MAC_VER_50:
3764         case RTL_GIGA_MAC_VER_51:
3765         case RTL_GIGA_MAC_VER_52:
3766         case RTL_GIGA_MAC_VER_60:
3767         case RTL_GIGA_MAC_VER_61:
3768                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3769                 break;
3770         case RTL_GIGA_MAC_VER_40:
3771         case RTL_GIGA_MAC_VER_41:
3772         case RTL_GIGA_MAC_VER_49:
3773                 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3774                 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3775                 break;
3776         default:
3777                 break;
3778         }
3779
3780         phy_resume(tp->phydev);
3781         /* give MAC/PHY some time to resume */
3782         msleep(20);
3783 }
3784
3785 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3786 {
3787         switch (tp->mac_version) {
3788         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
3789         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
3790                 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3791                 break;
3792         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
3793         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
3794         case RTL_GIGA_MAC_VER_38:
3795                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3796                 break;
3797         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
3798                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
3799                 break;
3800         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
3801                 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 |
3802                                       RX_DMA_BURST);
3803                 break;
3804         default:
3805                 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
3806                 break;
3807         }
3808 }
3809
3810 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3811 {
3812         tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
3813 }
3814
3815 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3816 {
3817         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3818         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
3819 }
3820
3821 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3822 {
3823         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3824         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
3825 }
3826
3827 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3828 {
3829         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3830 }
3831
3832 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3833 {
3834         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3835 }
3836
3837 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3838 {
3839         RTL_W8(tp, MaxTxPacketSize, 0x3f);
3840         RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
3841         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
3842 }
3843
3844 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3845 {
3846         RTL_W8(tp, MaxTxPacketSize, 0x0c);
3847         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
3848         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
3849 }
3850
3851 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3852 {
3853         RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
3854 }
3855
3856 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3857 {
3858         RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
3859 }
3860
3861 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3862 {
3863         rtl_unlock_config_regs(tp);
3864         switch (tp->mac_version) {
3865         case RTL_GIGA_MAC_VER_12:
3866         case RTL_GIGA_MAC_VER_17:
3867                 r8168b_1_hw_jumbo_enable(tp);
3868                 break;
3869         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3870                 r8168c_hw_jumbo_enable(tp);
3871                 break;
3872         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3873                 r8168dp_hw_jumbo_enable(tp);
3874                 break;
3875         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
3876                 r8168e_hw_jumbo_enable(tp);
3877                 break;
3878         default:
3879                 break;
3880         }
3881         rtl_lock_config_regs(tp);
3882 }
3883
3884 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3885 {
3886         rtl_unlock_config_regs(tp);
3887         switch (tp->mac_version) {
3888         case RTL_GIGA_MAC_VER_12:
3889         case RTL_GIGA_MAC_VER_17:
3890                 r8168b_1_hw_jumbo_disable(tp);
3891                 break;
3892         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
3893                 r8168c_hw_jumbo_disable(tp);
3894                 break;
3895         case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
3896                 r8168dp_hw_jumbo_disable(tp);
3897                 break;
3898         case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
3899                 r8168e_hw_jumbo_disable(tp);
3900                 break;
3901         default:
3902                 break;
3903         }
3904         rtl_lock_config_regs(tp);
3905 }
3906
3907 static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu)
3908 {
3909         if (mtu > ETH_DATA_LEN)
3910                 rtl_hw_jumbo_enable(tp);
3911         else
3912                 rtl_hw_jumbo_disable(tp);
3913 }
3914
3915 DECLARE_RTL_COND(rtl_chipcmd_cond)
3916 {
3917         return RTL_R8(tp, ChipCmd) & CmdReset;
3918 }
3919
3920 static void rtl_hw_reset(struct rtl8169_private *tp)
3921 {
3922         RTL_W8(tp, ChipCmd, CmdReset);
3923
3924         rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
3925 }
3926
3927 static void rtl_request_firmware(struct rtl8169_private *tp)
3928 {
3929         struct rtl_fw *rtl_fw;
3930
3931         /* firmware loaded already or no firmware available */
3932         if (tp->rtl_fw || !tp->fw_name)
3933                 return;
3934
3935         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3936         if (!rtl_fw) {
3937                 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
3938                 return;
3939         }
3940
3941         rtl_fw->phy_write = rtl_writephy;
3942         rtl_fw->phy_read = rtl_readphy;
3943         rtl_fw->mac_mcu_write = mac_mcu_write;
3944         rtl_fw->mac_mcu_read = mac_mcu_read;
3945         rtl_fw->fw_name = tp->fw_name;
3946         rtl_fw->dev = tp_to_dev(tp);
3947
3948         if (rtl_fw_request_firmware(rtl_fw))
3949                 kfree(rtl_fw);
3950         else
3951                 tp->rtl_fw = rtl_fw;
3952 }
3953
3954 static void rtl_rx_close(struct rtl8169_private *tp)
3955 {
3956         RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3957 }
3958
3959 DECLARE_RTL_COND(rtl_npq_cond)
3960 {
3961         return RTL_R8(tp, TxPoll) & NPQ;
3962 }
3963
3964 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
3965 {
3966         return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
3967 }
3968
3969 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3970 {
3971         /* Disable interrupts */
3972         rtl8169_irq_mask_and_ack(tp);
3973
3974         rtl_rx_close(tp);
3975
3976         switch (tp->mac_version) {
3977         case RTL_GIGA_MAC_VER_27:
3978         case RTL_GIGA_MAC_VER_28:
3979         case RTL_GIGA_MAC_VER_31:
3980                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
3981                 break;
3982         case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3983         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
3984                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3985                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3986                 break;
3987         default:
3988                 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3989                 udelay(100);
3990                 break;
3991         }
3992
3993         rtl_hw_reset(tp);
3994 }
3995
3996 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
3997 {
3998         u32 val = TX_DMA_BURST << TxDMAShift |
3999                   InterFrameGap << TxInterFrameGapShift;
4000
4001         if (rtl_is_8168evl_up(tp))
4002                 val |= TXCFG_AUTO_FIFO;
4003
4004         RTL_W32(tp, TxConfig, val);
4005 }
4006
4007 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4008 {
4009         /* Low hurts. Let's disable the filtering. */
4010         RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4011 }
4012
4013 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4014 {
4015         /*
4016          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4017          * register to be written before TxDescAddrLow to work.
4018          * Switching from MMIO to I/O access fixes the issue as well.
4019          */
4020         RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4021         RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4022         RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4023         RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4024 }
4025
4026 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4027 {
4028         u32 val;
4029
4030         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4031                 val = 0x000fff00;
4032         else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4033                 val = 0x00ffff00;
4034         else
4035                 return;
4036
4037         if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4038                 val |= 0xff;
4039
4040         RTL_W32(tp, 0x7c, val);
4041 }
4042
4043 static void rtl_set_rx_mode(struct net_device *dev)
4044 {
4045         u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
4046         /* Multicast hash filter */
4047         u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
4048         struct rtl8169_private *tp = netdev_priv(dev);
4049         u32 tmp;
4050
4051         if (dev->flags & IFF_PROMISC) {
4052                 /* Unconditionally log net taps. */
4053                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4054                 rx_mode |= AcceptAllPhys;
4055         } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
4056                    dev->flags & IFF_ALLMULTI ||
4057                    tp->mac_version == RTL_GIGA_MAC_VER_35) {
4058                 /* accept all multicasts */
4059         } else if (netdev_mc_empty(dev)) {
4060                 rx_mode &= ~AcceptMulticast;
4061         } else {
4062                 struct netdev_hw_addr *ha;
4063
4064                 mc_filter[1] = mc_filter[0] = 0;
4065                 netdev_for_each_mc_addr(ha, dev) {
4066                         u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4067                         mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
4068                 }
4069
4070                 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4071                         tmp = mc_filter[0];
4072                         mc_filter[0] = swab32(mc_filter[1]);
4073                         mc_filter[1] = swab32(tmp);
4074                 }
4075         }
4076
4077         if (dev->features & NETIF_F_RXALL)
4078                 rx_mode |= (AcceptErr | AcceptRunt);
4079
4080         RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4081         RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4082
4083         tmp = RTL_R32(tp, RxConfig);
4084         RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
4085 }
4086
4087 DECLARE_RTL_COND(rtl_csiar_cond)
4088 {
4089         return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4090 }
4091
4092 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4093 {
4094         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4095
4096         RTL_W32(tp, CSIDR, value);
4097         RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4098                 CSIAR_BYTE_ENABLE | func << 16);
4099
4100         rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4101 }
4102
4103 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4104 {
4105         u32 func = PCI_FUNC(tp->pci_dev->devfn);
4106
4107         RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4108                 CSIAR_BYTE_ENABLE);
4109
4110         return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4111                 RTL_R32(tp, CSIDR) : ~0;
4112 }
4113
4114 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4115 {
4116         struct pci_dev *pdev = tp->pci_dev;
4117         u32 csi;
4118
4119         /* According to Realtek the value at config space address 0x070f
4120          * controls the L0s/L1 entrance latency. We try standard ECAM access
4121          * first and if it fails fall back to CSI.
4122          */
4123         if (pdev->cfg_size > 0x070f &&
4124             pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4125                 return;
4126
4127         netdev_notice_once(tp->dev,
4128                 "No native access to PCI extended config space, falling back to CSI\n");
4129         csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4130         rtl_csi_write(tp, 0x070c, csi | val << 24);
4131 }
4132
4133 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4134 {
4135         rtl_csi_access_enable(tp, 0x27);
4136 }
4137
4138 struct ephy_info {
4139         unsigned int offset;
4140         u16 mask;
4141         u16 bits;
4142 };
4143
4144 static void __rtl_ephy_init(struct rtl8169_private *tp,
4145                             const struct ephy_info *e, int len)
4146 {
4147         u16 w;
4148
4149         while (len-- > 0) {
4150                 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4151                 rtl_ephy_write(tp, e->offset, w);
4152                 e++;
4153         }
4154 }
4155
4156 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4157
4158 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4159 {
4160         pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4161                                    PCI_EXP_LNKCTL_CLKREQ_EN);
4162 }
4163
4164 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4165 {
4166         pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4167                                  PCI_EXP_LNKCTL_CLKREQ_EN);
4168 }
4169
4170 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4171 {
4172         /* work around an issue when PCI reset occurs during L2/L3 state */
4173         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4174 }
4175
4176 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4177 {
4178         /* Don't enable ASPM in the chip if OS can't control ASPM */
4179         if (enable && tp->aspm_manageable) {
4180                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4181                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4182         } else {
4183                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4184                 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4185         }
4186
4187         udelay(10);
4188 }
4189
4190 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4191                               u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4192 {
4193         /* Usage of dynamic vs. static FIFO is controlled by bit
4194          * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4195          */
4196         rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4197         rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4198 }
4199
4200 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4201                                           u8 low, u8 high)
4202 {
4203         /* FIFO thresholds for pause flow control */
4204         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4205         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4206 }
4207
4208 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
4209 {
4210         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4211 }
4212
4213 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4214 {
4215         RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4216
4217         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4218
4219         rtl_disable_clock_request(tp);
4220 }
4221
4222 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4223 {
4224         static const struct ephy_info e_info_8168cp[] = {
4225                 { 0x01, 0,      0x0001 },
4226                 { 0x02, 0x0800, 0x1000 },
4227                 { 0x03, 0,      0x0042 },
4228                 { 0x06, 0x0080, 0x0000 },
4229                 { 0x07, 0,      0x2000 }
4230         };
4231
4232         rtl_set_def_aspm_entry_latency(tp);
4233
4234         rtl_ephy_init(tp, e_info_8168cp);
4235
4236         __rtl_hw_start_8168cp(tp);
4237 }
4238
4239 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4240 {
4241         rtl_set_def_aspm_entry_latency(tp);
4242
4243         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4244 }
4245
4246 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4247 {
4248         rtl_set_def_aspm_entry_latency(tp);
4249
4250         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4251
4252         /* Magic. */
4253         RTL_W8(tp, DBG_REG, 0x20);
4254 }
4255
4256 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4257 {
4258         static const struct ephy_info e_info_8168c_1[] = {
4259                 { 0x02, 0x0800, 0x1000 },
4260                 { 0x03, 0,      0x0002 },
4261                 { 0x06, 0x0080, 0x0000 }
4262         };
4263
4264         rtl_set_def_aspm_entry_latency(tp);
4265
4266         RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4267
4268         rtl_ephy_init(tp, e_info_8168c_1);
4269
4270         __rtl_hw_start_8168cp(tp);
4271 }
4272
4273 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4274 {
4275         static const struct ephy_info e_info_8168c_2[] = {
4276                 { 0x01, 0,      0x0001 },
4277                 { 0x03, 0x0400, 0x0020 }
4278         };
4279
4280         rtl_set_def_aspm_entry_latency(tp);
4281
4282         rtl_ephy_init(tp, e_info_8168c_2);
4283
4284         __rtl_hw_start_8168cp(tp);
4285 }
4286
4287 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4288 {
4289         rtl_hw_start_8168c_2(tp);
4290 }
4291
4292 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4293 {
4294         rtl_set_def_aspm_entry_latency(tp);
4295
4296         __rtl_hw_start_8168cp(tp);
4297 }
4298
4299 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4300 {
4301         rtl_set_def_aspm_entry_latency(tp);
4302
4303         rtl_disable_clock_request(tp);
4304 }
4305
4306 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4307 {
4308         static const struct ephy_info e_info_8168d_4[] = {
4309                 { 0x0b, 0x0000, 0x0048 },
4310                 { 0x19, 0x0020, 0x0050 },
4311                 { 0x0c, 0x0100, 0x0020 },
4312                 { 0x10, 0x0004, 0x0000 },
4313         };
4314
4315         rtl_set_def_aspm_entry_latency(tp);
4316
4317         rtl_ephy_init(tp, e_info_8168d_4);
4318
4319         rtl_enable_clock_request(tp);
4320 }
4321
4322 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4323 {
4324         static const struct ephy_info e_info_8168e_1[] = {
4325                 { 0x00, 0x0200, 0x0100 },
4326                 { 0x00, 0x0000, 0x0004 },
4327                 { 0x06, 0x0002, 0x0001 },
4328                 { 0x06, 0x0000, 0x0030 },
4329                 { 0x07, 0x0000, 0x2000 },
4330                 { 0x00, 0x0000, 0x0020 },
4331                 { 0x03, 0x5800, 0x2000 },
4332                 { 0x03, 0x0000, 0x0001 },
4333                 { 0x01, 0x0800, 0x1000 },
4334                 { 0x07, 0x0000, 0x4000 },
4335                 { 0x1e, 0x0000, 0x2000 },
4336                 { 0x19, 0xffff, 0xfe6c },
4337                 { 0x0a, 0x0000, 0x0040 }
4338         };
4339
4340         rtl_set_def_aspm_entry_latency(tp);
4341
4342         rtl_ephy_init(tp, e_info_8168e_1);
4343
4344         rtl_disable_clock_request(tp);
4345
4346         /* Reset tx FIFO pointer */
4347         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4348         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4349
4350         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4351 }
4352
4353 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4354 {
4355         static const struct ephy_info e_info_8168e_2[] = {
4356                 { 0x09, 0x0000, 0x0080 },
4357                 { 0x19, 0x0000, 0x0224 },
4358                 { 0x00, 0x0000, 0x0004 },
4359                 { 0x0c, 0x3df0, 0x0200 },
4360         };
4361
4362         rtl_set_def_aspm_entry_latency(tp);
4363
4364         rtl_ephy_init(tp, e_info_8168e_2);
4365
4366         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4367         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4368         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4369         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4370         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4371         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4372         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4373
4374         rtl_disable_clock_request(tp);
4375
4376         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4377
4378         rtl8168_config_eee_mac(tp);
4379
4380         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4381         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4382         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4383
4384         rtl_hw_aspm_clkreq_enable(tp, true);
4385 }
4386
4387 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4388 {
4389         rtl_set_def_aspm_entry_latency(tp);
4390
4391         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4392         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4393         rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4394         rtl_reset_packet_filter(tp);
4395         rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4396         rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4397         rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4398         rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4399
4400         rtl_disable_clock_request(tp);
4401
4402         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4403         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4404         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4405         RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4406
4407         rtl8168_config_eee_mac(tp);
4408 }
4409
4410 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4411 {
4412         static const struct ephy_info e_info_8168f_1[] = {
4413                 { 0x06, 0x00c0, 0x0020 },
4414                 { 0x08, 0x0001, 0x0002 },
4415                 { 0x09, 0x0000, 0x0080 },
4416                 { 0x19, 0x0000, 0x0224 },
4417                 { 0x00, 0x0000, 0x0004 },
4418                 { 0x0c, 0x3df0, 0x0200 },
4419         };
4420
4421         rtl_hw_start_8168f(tp);
4422
4423         rtl_ephy_init(tp, e_info_8168f_1);
4424
4425         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4426 }
4427
4428 static void rtl_hw_start_8411(struct rtl8169_private *tp)
4429 {
4430         static const struct ephy_info e_info_8168f_1[] = {
4431                 { 0x06, 0x00c0, 0x0020 },
4432                 { 0x0f, 0xffff, 0x5200 },
4433                 { 0x19, 0x0000, 0x0224 },
4434                 { 0x00, 0x0000, 0x0004 },
4435                 { 0x0c, 0x3df0, 0x0200 },
4436         };
4437
4438         rtl_hw_start_8168f(tp);
4439         rtl_pcie_state_l2l3_disable(tp);
4440
4441         rtl_ephy_init(tp, e_info_8168f_1);
4442
4443         rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4444 }
4445
4446 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4447 {
4448         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4449         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4450
4451         rtl_set_def_aspm_entry_latency(tp);
4452
4453         rtl_reset_packet_filter(tp);
4454         rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4455
4456         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4457
4458         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4459         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4460
4461         rtl8168_config_eee_mac(tp);
4462
4463         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4464         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4465
4466         rtl_pcie_state_l2l3_disable(tp);
4467 }
4468
4469 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4470 {
4471         static const struct ephy_info e_info_8168g_1[] = {
4472                 { 0x00, 0x0008, 0x0000 },
4473                 { 0x0c, 0x3ff0, 0x0820 },
4474                 { 0x1e, 0x0000, 0x0001 },
4475                 { 0x19, 0x8000, 0x0000 }
4476         };
4477
4478         rtl_hw_start_8168g(tp);
4479
4480         /* disable aspm and clock request before access ephy */
4481         rtl_hw_aspm_clkreq_enable(tp, false);
4482         rtl_ephy_init(tp, e_info_8168g_1);
4483         rtl_hw_aspm_clkreq_enable(tp, true);
4484 }
4485
4486 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4487 {
4488         static const struct ephy_info e_info_8168g_2[] = {
4489                 { 0x00, 0x0008, 0x0000 },
4490                 { 0x0c, 0x3ff0, 0x0820 },
4491                 { 0x19, 0xffff, 0x7c00 },
4492                 { 0x1e, 0xffff, 0x20eb },
4493                 { 0x0d, 0xffff, 0x1666 },
4494                 { 0x00, 0xffff, 0x10a3 },
4495                 { 0x06, 0xffff, 0xf050 },
4496                 { 0x04, 0x0000, 0x0010 },
4497                 { 0x1d, 0x4000, 0x0000 },
4498         };
4499
4500         rtl_hw_start_8168g(tp);
4501
4502         /* disable aspm and clock request before access ephy */
4503         rtl_hw_aspm_clkreq_enable(tp, false);
4504         rtl_ephy_init(tp, e_info_8168g_2);
4505 }
4506
4507 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4508 {
4509         static const struct ephy_info e_info_8411_2[] = {
4510                 { 0x00, 0x0008, 0x0000 },
4511                 { 0x0c, 0x37d0, 0x0820 },
4512                 { 0x1e, 0x0000, 0x0001 },
4513                 { 0x19, 0x8021, 0x0000 },
4514                 { 0x1e, 0x0000, 0x2000 },
4515                 { 0x0d, 0x0100, 0x0200 },
4516                 { 0x00, 0x0000, 0x0080 },
4517                 { 0x06, 0x0000, 0x0010 },
4518                 { 0x04, 0x0000, 0x0010 },
4519                 { 0x1d, 0x0000, 0x4000 },
4520         };
4521
4522         rtl_hw_start_8168g(tp);
4523
4524         /* disable aspm and clock request before access ephy */
4525         rtl_hw_aspm_clkreq_enable(tp, false);
4526         rtl_ephy_init(tp, e_info_8411_2);
4527
4528         /* The following Realtek-provided magic fixes an issue with the RX unit
4529          * getting confused after the PHY having been powered-down.
4530          */
4531         r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
4532         r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
4533         r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
4534         r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
4535         r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
4536         r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
4537         r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
4538         r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
4539         mdelay(3);
4540         r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
4541
4542         r8168_mac_ocp_write(tp, 0xF800, 0xE008);
4543         r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
4544         r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
4545         r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
4546         r8168_mac_ocp_write(tp, 0xF808, 0xE027);
4547         r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
4548         r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
4549         r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
4550         r8168_mac_ocp_write(tp, 0xF810, 0xC602);
4551         r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
4552         r8168_mac_ocp_write(tp, 0xF814, 0x0000);
4553         r8168_mac_ocp_write(tp, 0xF816, 0xC502);
4554         r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
4555         r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
4556         r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
4557         r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
4558         r8168_mac_ocp_write(tp, 0xF820, 0x080A);
4559         r8168_mac_ocp_write(tp, 0xF822, 0x6420);
4560         r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
4561         r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
4562         r8168_mac_ocp_write(tp, 0xF828, 0xC516);
4563         r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
4564         r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
4565         r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
4566         r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
4567         r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
4568         r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
4569         r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
4570         r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
4571         r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
4572         r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
4573         r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
4574         r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
4575         r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
4576         r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
4577         r8168_mac_ocp_write(tp, 0xF846, 0xC404);
4578         r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
4579         r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
4580         r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
4581         r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
4582         r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
4583         r8168_mac_ocp_write(tp, 0xF852, 0xE434);
4584         r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
4585         r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
4586         r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
4587         r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
4588         r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
4589         r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
4590         r8168_mac_ocp_write(tp, 0xF860, 0xF007);
4591         r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
4592         r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
4593         r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
4594         r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
4595         r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
4596         r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
4597         r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
4598         r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
4599         r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
4600         r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
4601         r8168_mac_ocp_write(tp, 0xF876, 0xC516);
4602         r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
4603         r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
4604         r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
4605         r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
4606         r8168_mac_ocp_write(tp, 0xF880, 0xC512);
4607         r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
4608         r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
4609         r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
4610         r8168_mac_ocp_write(tp, 0xF888, 0x483F);
4611         r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
4612         r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
4613         r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
4614         r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
4615         r8168_mac_ocp_write(tp, 0xF892, 0xC505);
4616         r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
4617         r8168_mac_ocp_write(tp, 0xF896, 0xC502);
4618         r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
4619         r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
4620         r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
4621         r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
4622         r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
4623         r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
4624         r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
4625         r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
4626         r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
4627         r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
4628         r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
4629         r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
4630         r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
4631         r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
4632         r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
4633         r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
4634         r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
4635         r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
4636         r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
4637         r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
4638         r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
4639         r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
4640         r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
4641         r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
4642         r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
4643         r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
4644         r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
4645         r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
4646         r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
4647         r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
4648         r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
4649         r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
4650         r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
4651         r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
4652         r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
4653
4654         r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
4655
4656         r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
4657         r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
4658         r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
4659         r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
4660         r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
4661         r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
4662         r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
4663
4664         rtl_hw_aspm_clkreq_enable(tp, true);
4665 }
4666
4667 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4668 {
4669         static const struct ephy_info e_info_8168h_1[] = {
4670                 { 0x1e, 0x0800, 0x0001 },
4671                 { 0x1d, 0x0000, 0x0800 },
4672                 { 0x05, 0xffff, 0x2089 },
4673                 { 0x06, 0xffff, 0x5881 },
4674                 { 0x04, 0xffff, 0x854a },
4675                 { 0x01, 0xffff, 0x068b }
4676         };
4677         int rg_saw_cnt;
4678
4679         /* disable aspm and clock request before access ephy */
4680         rtl_hw_aspm_clkreq_enable(tp, false);
4681         rtl_ephy_init(tp, e_info_8168h_1);
4682
4683         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4684         rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4685
4686         rtl_set_def_aspm_entry_latency(tp);
4687
4688         rtl_reset_packet_filter(tp);
4689
4690         rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
4691
4692         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
4693
4694         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4695
4696         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4697
4698         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4699         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4700
4701         rtl8168_config_eee_mac(tp);
4702
4703         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4704         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4705
4706         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4707
4708         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4709
4710         rtl_pcie_state_l2l3_disable(tp);
4711
4712         rtl_writephy(tp, 0x1f, 0x0c42);
4713         rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
4714         rtl_writephy(tp, 0x1f, 0x0000);
4715         if (rg_saw_cnt > 0) {
4716                 u16 sw_cnt_1ms_ini;
4717
4718                 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4719                 sw_cnt_1ms_ini &= 0x0fff;
4720                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
4721         }
4722
4723         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
4724         r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
4725         r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
4726         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
4727
4728         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4729         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4730         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4731         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
4732
4733         rtl_hw_aspm_clkreq_enable(tp, true);
4734 }
4735
4736 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
4737 {
4738         rtl8168ep_stop_cmac(tp);
4739
4740         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4741         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
4742
4743         rtl_set_def_aspm_entry_latency(tp);
4744
4745         rtl_reset_packet_filter(tp);
4746
4747         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
4748
4749         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4750
4751         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4752
4753         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4754         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4755
4756         rtl8168_config_eee_mac(tp);
4757
4758         rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4759
4760         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4761
4762         rtl_pcie_state_l2l3_disable(tp);
4763 }
4764
4765 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
4766 {
4767         static const struct ephy_info e_info_8168ep_1[] = {
4768                 { 0x00, 0xffff, 0x10ab },
4769                 { 0x06, 0xffff, 0xf030 },
4770                 { 0x08, 0xffff, 0x2006 },
4771                 { 0x0d, 0xffff, 0x1666 },
4772                 { 0x0c, 0x3ff0, 0x0000 }
4773         };
4774
4775         /* disable aspm and clock request before access ephy */
4776         rtl_hw_aspm_clkreq_enable(tp, false);
4777         rtl_ephy_init(tp, e_info_8168ep_1);
4778
4779         rtl_hw_start_8168ep(tp);
4780
4781         rtl_hw_aspm_clkreq_enable(tp, true);
4782 }
4783
4784 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
4785 {
4786         static const struct ephy_info e_info_8168ep_2[] = {
4787                 { 0x00, 0xffff, 0x10a3 },
4788                 { 0x19, 0xffff, 0xfc00 },
4789                 { 0x1e, 0xffff, 0x20ea }
4790         };
4791
4792         /* disable aspm and clock request before access ephy */
4793         rtl_hw_aspm_clkreq_enable(tp, false);
4794         rtl_ephy_init(tp, e_info_8168ep_2);
4795
4796         rtl_hw_start_8168ep(tp);
4797
4798         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4799         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4800
4801         rtl_hw_aspm_clkreq_enable(tp, true);
4802 }
4803
4804 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
4805 {
4806         static const struct ephy_info e_info_8168ep_3[] = {
4807                 { 0x00, 0x0000, 0x0080 },
4808                 { 0x0d, 0x0100, 0x0200 },
4809                 { 0x19, 0x8021, 0x0000 },
4810                 { 0x1e, 0x0000, 0x2000 },
4811         };
4812
4813         /* disable aspm and clock request before access ephy */
4814         rtl_hw_aspm_clkreq_enable(tp, false);
4815         rtl_ephy_init(tp, e_info_8168ep_3);
4816
4817         rtl_hw_start_8168ep(tp);
4818
4819         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4820         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4821
4822         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
4823         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
4824         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
4825
4826         rtl_hw_aspm_clkreq_enable(tp, true);
4827 }
4828
4829 static void rtl_hw_start_8117(struct rtl8169_private *tp)
4830 {
4831         static const struct ephy_info e_info_8117[] = {
4832                 { 0x19, 0x0040, 0x1100 },
4833                 { 0x59, 0x0040, 0x1100 },
4834         };
4835         int rg_saw_cnt;
4836
4837         rtl8168ep_stop_cmac(tp);
4838
4839         /* disable aspm and clock request before access ephy */
4840         rtl_hw_aspm_clkreq_enable(tp, false);
4841         rtl_ephy_init(tp, e_info_8117);
4842
4843         rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4844         rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
4845
4846         rtl_set_def_aspm_entry_latency(tp);
4847
4848         rtl_reset_packet_filter(tp);
4849
4850         rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f90);
4851
4852         rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4853
4854         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4855
4856         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4857         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4858
4859         rtl8168_config_eee_mac(tp);
4860
4861         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4862         RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4863
4864         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4865
4866         rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4867
4868         rtl_pcie_state_l2l3_disable(tp);
4869
4870         rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
4871         if (rg_saw_cnt > 0) {
4872                 u16 sw_cnt_1ms_ini;
4873
4874                 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
4875                 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
4876         }
4877
4878         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
4879         r8168_mac_ocp_write(tp, 0xea80, 0x0003);
4880         r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
4881         r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
4882
4883         r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
4884         r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
4885         r8168_mac_ocp_write(tp, 0xc094, 0x0000);
4886         r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
4887
4888         /* firmware is for MAC only */
4889         rtl_apply_firmware(tp);
4890
4891         rtl_hw_aspm_clkreq_enable(tp, true);
4892 }
4893
4894 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
4895 {
4896         static const struct ephy_info e_info_8102e_1[] = {
4897                 { 0x01, 0, 0x6e65 },
4898                 { 0x02, 0, 0x091f },
4899                 { 0x03, 0, 0xc2f9 },
4900                 { 0x06, 0, 0xafb5 },
4901                 { 0x07, 0, 0x0e00 },
4902                 { 0x19, 0, 0xec80 },
4903                 { 0x01, 0, 0x2e65 },
4904                 { 0x01, 0, 0x6e65 }
4905         };
4906         u8 cfg1;
4907
4908         rtl_set_def_aspm_entry_latency(tp);
4909
4910         RTL_W8(tp, DBG_REG, FIX_NAK_1);
4911
4912         RTL_W8(tp, Config1,
4913                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4914         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4915
4916         cfg1 = RTL_R8(tp, Config1);
4917         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4918                 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
4919
4920         rtl_ephy_init(tp, e_info_8102e_1);
4921 }
4922
4923 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
4924 {
4925         rtl_set_def_aspm_entry_latency(tp);
4926
4927         RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
4928         RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4929 }
4930
4931 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
4932 {
4933         rtl_hw_start_8102e_2(tp);
4934
4935         rtl_ephy_write(tp, 0x03, 0xc2f9);
4936 }
4937
4938 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
4939 {
4940         static const struct ephy_info e_info_8105e_1[] = {
4941                 { 0x07, 0, 0x4000 },
4942                 { 0x19, 0, 0x0200 },
4943                 { 0x19, 0, 0x0020 },
4944                 { 0x1e, 0, 0x2000 },
4945                 { 0x03, 0, 0x0001 },
4946                 { 0x19, 0, 0x0100 },
4947                 { 0x19, 0, 0x0004 },
4948                 { 0x0a, 0, 0x0020 }
4949         };
4950
4951         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4952         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4953
4954         /* Disable Early Tally Counter */
4955         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
4956
4957         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
4958         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4959
4960         rtl_ephy_init(tp, e_info_8105e_1);
4961
4962         rtl_pcie_state_l2l3_disable(tp);
4963 }
4964
4965 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
4966 {
4967         rtl_hw_start_8105e_1(tp);
4968         rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
4969 }
4970
4971 static void rtl_hw_start_8402(struct rtl8169_private *tp)
4972 {
4973         static const struct ephy_info e_info_8402[] = {
4974                 { 0x19, 0xffff, 0xff64 },
4975                 { 0x1e, 0, 0x4000 }
4976         };
4977
4978         rtl_set_def_aspm_entry_latency(tp);
4979
4980         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4981         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
4982
4983         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4984
4985         rtl_ephy_init(tp, e_info_8402);
4986
4987         rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
4988         rtl_reset_packet_filter(tp);
4989         rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4990         rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4991         rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
4992
4993         rtl_pcie_state_l2l3_disable(tp);
4994 }
4995
4996 static void rtl_hw_start_8106(struct rtl8169_private *tp)
4997 {
4998         rtl_hw_aspm_clkreq_enable(tp, false);
4999
5000         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5001         RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5002
5003         RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5004         RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5005         RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5006
5007         rtl_pcie_state_l2l3_disable(tp);
5008         rtl_hw_aspm_clkreq_enable(tp, true);
5009 }
5010
5011 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
5012 {
5013         return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
5014 }
5015
5016 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
5017 {
5018         rtl_pcie_state_l2l3_disable(tp);
5019
5020         RTL_W16(tp, 0x382, 0x221b);
5021         RTL_W8(tp, 0x4500, 0);
5022         RTL_W16(tp, 0x4800, 0);
5023
5024         /* disable UPS */
5025         r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
5026
5027         RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
5028
5029         r8168_mac_ocp_write(tp, 0xc140, 0xffff);
5030         r8168_mac_ocp_write(tp, 0xc142, 0xffff);
5031
5032         r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
5033         r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
5034         r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
5035
5036         /* disable new tx descriptor format */
5037         r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
5038
5039         r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
5040         r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
5041         r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
5042         r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
5043         r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
5044         r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
5045         r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
5046         r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
5047         r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067);
5048         r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
5049         r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
5050         r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0);
5051         r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
5052         r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
5053         udelay(1);
5054         r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
5055         RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
5056
5057         r8168_mac_ocp_write(tp, 0xe098, 0xc302);
5058
5059         rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
5060
5061         rtl8125_config_eee_mac(tp);
5062
5063         RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5064         udelay(10);
5065 }
5066
5067 static void rtl_hw_start_8125_1(struct rtl8169_private *tp)
5068 {
5069         static const struct ephy_info e_info_8125_1[] = {
5070                 { 0x01, 0xffff, 0xa812 },
5071                 { 0x09, 0xffff, 0x520c },
5072                 { 0x04, 0xffff, 0xd000 },
5073                 { 0x0d, 0xffff, 0xf702 },
5074                 { 0x0a, 0xffff, 0x8653 },
5075                 { 0x06, 0xffff, 0x001e },
5076                 { 0x08, 0xffff, 0x3595 },
5077                 { 0x20, 0xffff, 0x9455 },
5078                 { 0x21, 0xffff, 0x99ff },
5079                 { 0x02, 0xffff, 0x6046 },
5080                 { 0x29, 0xffff, 0xfe00 },
5081                 { 0x23, 0xffff, 0xab62 },
5082
5083                 { 0x41, 0xffff, 0xa80c },
5084                 { 0x49, 0xffff, 0x520c },
5085                 { 0x44, 0xffff, 0xd000 },
5086                 { 0x4d, 0xffff, 0xf702 },
5087                 { 0x4a, 0xffff, 0x8653 },
5088                 { 0x46, 0xffff, 0x001e },
5089                 { 0x48, 0xffff, 0x3595 },
5090                 { 0x60, 0xffff, 0x9455 },
5091                 { 0x61, 0xffff, 0x99ff },
5092                 { 0x42, 0xffff, 0x6046 },
5093                 { 0x69, 0xffff, 0xfe00 },
5094                 { 0x63, 0xffff, 0xab62 },
5095         };
5096
5097         rtl_set_def_aspm_entry_latency(tp);
5098
5099         /* disable aspm and clock request before access ephy */
5100         rtl_hw_aspm_clkreq_enable(tp, false);
5101         rtl_ephy_init(tp, e_info_8125_1);
5102
5103         rtl_hw_start_8125_common(tp);
5104 }
5105
5106 static void rtl_hw_start_8125_2(struct rtl8169_private *tp)
5107 {
5108         static const struct ephy_info e_info_8125_2[] = {
5109                 { 0x04, 0xffff, 0xd000 },
5110                 { 0x0a, 0xffff, 0x8653 },
5111                 { 0x23, 0xffff, 0xab66 },
5112                 { 0x20, 0xffff, 0x9455 },
5113                 { 0x21, 0xffff, 0x99ff },
5114                 { 0x29, 0xffff, 0xfe04 },
5115
5116                 { 0x44, 0xffff, 0xd000 },
5117                 { 0x4a, 0xffff, 0x8653 },
5118                 { 0x63, 0xffff, 0xab66 },
5119                 { 0x60, 0xffff, 0x9455 },
5120                 { 0x61, 0xffff, 0x99ff },
5121                 { 0x69, 0xffff, 0xfe04 },
5122         };
5123
5124         rtl_set_def_aspm_entry_latency(tp);
5125
5126         /* disable aspm and clock request before access ephy */
5127         rtl_hw_aspm_clkreq_enable(tp, false);
5128         rtl_ephy_init(tp, e_info_8125_2);
5129
5130         rtl_hw_start_8125_common(tp);
5131 }
5132
5133 static void rtl_hw_config(struct rtl8169_private *tp)
5134 {
5135         static const rtl_generic_fct hw_configs[] = {
5136                 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
5137                 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
5138                 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
5139                 [RTL_GIGA_MAC_VER_10] = NULL,
5140                 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
5141                 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
5142                 [RTL_GIGA_MAC_VER_13] = NULL,
5143                 [RTL_GIGA_MAC_VER_14] = NULL,
5144                 [RTL_GIGA_MAC_VER_15] = NULL,
5145                 [RTL_GIGA_MAC_VER_16] = NULL,
5146                 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
5147                 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
5148                 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
5149                 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
5150                 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
5151                 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
5152                 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
5153                 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
5154                 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
5155                 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
5156                 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
5157                 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
5158                 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
5159                 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
5160                 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
5161                 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
5162                 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
5163                 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
5164                 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
5165                 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
5166                 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
5167                 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
5168                 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
5169                 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
5170                 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
5171                 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
5172                 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
5173                 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
5174                 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
5175                 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
5176                 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
5177                 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
5178                 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
5179                 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
5180                 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
5181                 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
5182                 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1,
5183                 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2,
5184         };
5185
5186         if (hw_configs[tp->mac_version])
5187                 hw_configs[tp->mac_version](tp);
5188 }
5189
5190 static void rtl_hw_start_8125(struct rtl8169_private *tp)
5191 {
5192         int i;
5193
5194         /* disable interrupt coalescing */
5195         for (i = 0xa00; i < 0xb00; i += 4)
5196                 RTL_W32(tp, i, 0);
5197
5198         rtl_hw_config(tp);
5199 }
5200
5201 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5202 {
5203         if (rtl_is_8168evl_up(tp))
5204                 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5205         else
5206                 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5207
5208         rtl_hw_config(tp);
5209
5210         /* disable interrupt coalescing */
5211         RTL_W16(tp, IntrMitigate, 0x0000);
5212 }
5213
5214 static void rtl_hw_start_8169(struct rtl8169_private *tp)
5215 {
5216         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5217                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
5218
5219         RTL_W8(tp, EarlyTxThres, NoEarlyTx);
5220
5221         tp->cp_cmd |= PCIMulRW;
5222
5223         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5224             tp->mac_version == RTL_GIGA_MAC_VER_03) {
5225                 netif_dbg(tp, drv, tp->dev,
5226                           "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
5227                 tp->cp_cmd |= (1 << 14);
5228         }
5229
5230         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5231
5232         rtl8169_set_magic_reg(tp, tp->mac_version);
5233
5234         RTL_W32(tp, RxMissed, 0);
5235
5236         /* disable interrupt coalescing */
5237         RTL_W16(tp, IntrMitigate, 0x0000);
5238 }
5239
5240 static void rtl_hw_start(struct  rtl8169_private *tp)
5241 {
5242         rtl_unlock_config_regs(tp);
5243
5244         tp->cp_cmd &= CPCMD_MASK;
5245         RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5246
5247         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5248                 rtl_hw_start_8169(tp);
5249         else if (rtl_is_8125(tp))
5250                 rtl_hw_start_8125(tp);
5251         else
5252                 rtl_hw_start_8168(tp);
5253
5254         rtl_set_rx_max_size(tp);
5255         rtl_set_rx_tx_desc_registers(tp);
5256         rtl_lock_config_regs(tp);
5257
5258         rtl_jumbo_config(tp, tp->dev->mtu);
5259
5260         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5261         RTL_R16(tp, CPlusCmd);
5262         RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5263         rtl_init_rxcfg(tp);
5264         rtl_set_tx_config_registers(tp);
5265         rtl_set_rx_mode(tp->dev);
5266         rtl_irq_enable(tp);
5267 }
5268
5269 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5270 {
5271         struct rtl8169_private *tp = netdev_priv(dev);
5272
5273         rtl_jumbo_config(tp, new_mtu);
5274
5275         dev->mtu = new_mtu;
5276         netdev_update_features(dev);
5277
5278         return 0;
5279 }
5280
5281 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5282 {
5283         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5284         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5285 }
5286
5287 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5288 {
5289         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5290
5291         /* Force memory writes to complete before releasing descriptor */
5292         dma_wmb();
5293
5294         desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5295 }
5296
5297 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5298                                           struct RxDesc *desc)
5299 {
5300         struct device *d = tp_to_dev(tp);
5301         int node = dev_to_node(d);
5302         dma_addr_t mapping;
5303         struct page *data;
5304
5305         data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
5306         if (!data)
5307                 return NULL;
5308
5309         mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5310         if (unlikely(dma_mapping_error(d, mapping))) {
5311                 if (net_ratelimit())
5312                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5313                 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
5314                 return NULL;
5315         }
5316
5317         desc->addr = cpu_to_le64(mapping);
5318         rtl8169_mark_to_asic(desc);
5319
5320         return data;
5321 }
5322
5323 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5324 {
5325         unsigned int i;
5326
5327         for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
5328                 dma_unmap_page(tp_to_dev(tp),
5329                                le64_to_cpu(tp->RxDescArray[i].addr),
5330                                R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5331                 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
5332                 tp->Rx_databuff[i] = NULL;
5333                 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5334         }
5335 }
5336
5337 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5338 {
5339         desc->opts1 |= cpu_to_le32(RingEnd);
5340 }
5341
5342 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5343 {
5344         unsigned int i;
5345
5346         for (i = 0; i < NUM_RX_DESC; i++) {
5347                 struct page *data;
5348
5349                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5350                 if (!data) {
5351                         rtl8169_rx_clear(tp);
5352                         return -ENOMEM;
5353                 }
5354                 tp->Rx_databuff[i] = data;
5355         }
5356
5357         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5358
5359         return 0;
5360 }
5361
5362 static int rtl8169_init_ring(struct rtl8169_private *tp)
5363 {
5364         rtl8169_init_ring_indexes(tp);
5365
5366         memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5367         memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5368
5369         return rtl8169_rx_fill(tp);
5370 }
5371
5372 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5373                                  struct TxDesc *desc)
5374 {
5375         unsigned int len = tx_skb->len;
5376
5377         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5378
5379         desc->opts1 = 0x00;
5380         desc->opts2 = 0x00;
5381         desc->addr = 0x00;
5382         tx_skb->len = 0;
5383 }
5384
5385 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5386                                    unsigned int n)
5387 {
5388         unsigned int i;
5389
5390         for (i = 0; i < n; i++) {
5391                 unsigned int entry = (start + i) % NUM_TX_DESC;
5392                 struct ring_info *tx_skb = tp->tx_skb + entry;
5393                 unsigned int len = tx_skb->len;
5394
5395                 if (len) {
5396                         struct sk_buff *skb = tx_skb->skb;
5397
5398                         rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5399                                              tp->TxDescArray + entry);
5400                         if (skb) {
5401                                 dev_consume_skb_any(skb);
5402                                 tx_skb->skb = NULL;
5403                         }
5404                 }
5405         }
5406 }
5407
5408 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5409 {
5410         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5411         tp->cur_tx = tp->dirty_tx = 0;
5412         netdev_reset_queue(tp->dev);
5413 }
5414
5415 static void rtl_reset_work(struct rtl8169_private *tp)
5416 {
5417         struct net_device *dev = tp->dev;
5418         int i;
5419
5420         napi_disable(&tp->napi);
5421         netif_stop_queue(dev);
5422         synchronize_rcu();
5423
5424         rtl8169_hw_reset(tp);
5425
5426         for (i = 0; i < NUM_RX_DESC; i++)
5427                 rtl8169_mark_to_asic(tp->RxDescArray + i);
5428
5429         rtl8169_tx_clear(tp);
5430         rtl8169_init_ring_indexes(tp);
5431
5432         napi_enable(&tp->napi);
5433         rtl_hw_start(tp);
5434         netif_wake_queue(dev);
5435 }
5436
5437 static void rtl8169_tx_timeout(struct net_device *dev)
5438 {
5439         struct rtl8169_private *tp = netdev_priv(dev);
5440
5441         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5442 }
5443
5444 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
5445 {
5446         u32 status = opts0 | len;
5447
5448         if (entry == NUM_TX_DESC - 1)
5449                 status |= RingEnd;
5450
5451         return cpu_to_le32(status);
5452 }
5453
5454 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5455                               u32 *opts)
5456 {
5457         struct skb_shared_info *info = skb_shinfo(skb);
5458         unsigned int cur_frag, entry;
5459         struct TxDesc *uninitialized_var(txd);
5460         struct device *d = tp_to_dev(tp);
5461
5462         entry = tp->cur_tx;
5463         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5464                 const skb_frag_t *frag = info->frags + cur_frag;
5465                 dma_addr_t mapping;
5466                 u32 len;
5467                 void *addr;
5468
5469                 entry = (entry + 1) % NUM_TX_DESC;
5470
5471                 txd = tp->TxDescArray + entry;
5472                 len = skb_frag_size(frag);
5473                 addr = skb_frag_address(frag);
5474                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5475                 if (unlikely(dma_mapping_error(d, mapping))) {
5476                         if (net_ratelimit())
5477                                 netif_err(tp, drv, tp->dev,
5478                                           "Failed to map TX fragments DMA!\n");
5479                         goto err_out;
5480                 }
5481
5482                 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5483                 txd->opts2 = cpu_to_le32(opts[1]);
5484                 txd->addr = cpu_to_le64(mapping);
5485
5486                 tp->tx_skb[entry].len = len;
5487         }
5488
5489         if (cur_frag) {
5490                 tp->tx_skb[entry].skb = skb;
5491                 txd->opts1 |= cpu_to_le32(LastFrag);
5492         }
5493
5494         return cur_frag;
5495
5496 err_out:
5497         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5498         return -EIO;
5499 }
5500
5501 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5502 {
5503         return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5504 }
5505
5506 /* msdn_giant_send_check()
5507  * According to the document of microsoft, the TCP Pseudo Header excludes the
5508  * packet length for IPv6 TCP large packets.
5509  */
5510 static int msdn_giant_send_check(struct sk_buff *skb)
5511 {
5512         const struct ipv6hdr *ipv6h;
5513         struct tcphdr *th;
5514         int ret;
5515
5516         ret = skb_cow_head(skb, 0);
5517         if (ret)
5518                 return ret;
5519
5520         ipv6h = ipv6_hdr(skb);
5521         th = tcp_hdr(skb);
5522
5523         th->check = 0;
5524         th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
5525
5526         return ret;
5527 }
5528
5529 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
5530 {
5531         u32 mss = skb_shinfo(skb)->gso_size;
5532
5533         if (mss) {
5534                 opts[0] |= TD_LSO;
5535                 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
5536         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5537                 const struct iphdr *ip = ip_hdr(skb);
5538
5539                 if (ip->protocol == IPPROTO_TCP)
5540                         opts[0] |= TD0_IP_CS | TD0_TCP_CS;
5541                 else if (ip->protocol == IPPROTO_UDP)
5542                         opts[0] |= TD0_IP_CS | TD0_UDP_CS;
5543                 else
5544                         WARN_ON_ONCE(1);
5545         }
5546 }
5547
5548 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
5549                                 struct sk_buff *skb, u32 *opts)
5550 {
5551         u32 transport_offset = (u32)skb_transport_offset(skb);
5552         u32 mss = skb_shinfo(skb)->gso_size;
5553
5554         if (mss) {
5555                 switch (vlan_get_protocol(skb)) {
5556                 case htons(ETH_P_IP):
5557                         opts[0] |= TD1_GTSENV4;
5558                         break;
5559
5560                 case htons(ETH_P_IPV6):
5561                         if (msdn_giant_send_check(skb))
5562                                 return false;
5563
5564                         opts[0] |= TD1_GTSENV6;
5565                         break;
5566
5567                 default:
5568                         WARN_ON_ONCE(1);
5569                         break;
5570                 }
5571
5572                 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5573                 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
5574         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5575                 u8 ip_protocol;
5576
5577                 switch (vlan_get_protocol(skb)) {
5578                 case htons(ETH_P_IP):
5579                         opts[1] |= TD1_IPv4_CS;
5580                         ip_protocol = ip_hdr(skb)->protocol;
5581                         break;
5582
5583                 case htons(ETH_P_IPV6):
5584                         opts[1] |= TD1_IPv6_CS;
5585                         ip_protocol = ipv6_hdr(skb)->nexthdr;
5586                         break;
5587
5588                 default:
5589                         ip_protocol = IPPROTO_RAW;
5590                         break;
5591                 }
5592
5593                 if (ip_protocol == IPPROTO_TCP)
5594                         opts[1] |= TD1_TCP_CS;
5595                 else if (ip_protocol == IPPROTO_UDP)
5596                         opts[1] |= TD1_UDP_CS;
5597                 else
5598                         WARN_ON_ONCE(1);
5599
5600                 opts[1] |= transport_offset << TCPHO_SHIFT;
5601         } else {
5602                 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
5603                         return !eth_skb_pad(skb);
5604         }
5605
5606         return true;
5607 }
5608
5609 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
5610                                unsigned int nr_frags)
5611 {
5612         unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
5613
5614         /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
5615         return slots_avail > nr_frags;
5616 }
5617
5618 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
5619 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
5620 {
5621         switch (tp->mac_version) {
5622         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5623         case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
5624                 return false;
5625         default:
5626                 return true;
5627         }
5628 }
5629
5630 static void rtl8169_doorbell(struct rtl8169_private *tp)
5631 {
5632         if (rtl_is_8125(tp))
5633                 RTL_W16(tp, TxPoll_8125, BIT(0));
5634         else
5635                 RTL_W8(tp, TxPoll, NPQ);
5636 }
5637
5638 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5639                                       struct net_device *dev)
5640 {
5641         struct rtl8169_private *tp = netdev_priv(dev);
5642         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5643         struct TxDesc *txd = tp->TxDescArray + entry;
5644         struct device *d = tp_to_dev(tp);
5645         dma_addr_t mapping;
5646         u32 opts[2], len;
5647         bool stop_queue;
5648         bool door_bell;
5649         int frags;
5650
5651         if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
5652                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5653                 goto err_stop_0;
5654         }
5655
5656         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5657                 goto err_stop_0;
5658
5659         opts[1] = rtl8169_tx_vlan_tag(skb);
5660         opts[0] = DescOwn;
5661
5662         if (rtl_chip_supports_csum_v2(tp)) {
5663                 if (!rtl8169_tso_csum_v2(tp, skb, opts))
5664                         goto err_dma_0;
5665         } else {
5666                 rtl8169_tso_csum_v1(skb, opts);
5667         }
5668
5669         len = skb_headlen(skb);
5670         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5671         if (unlikely(dma_mapping_error(d, mapping))) {
5672                 if (net_ratelimit())
5673                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5674                 goto err_dma_0;
5675         }
5676
5677         tp->tx_skb[entry].len = len;
5678         txd->addr = cpu_to_le64(mapping);
5679
5680         frags = rtl8169_xmit_frags(tp, skb, opts);
5681         if (frags < 0)
5682                 goto err_dma_1;
5683         else if (frags)
5684                 opts[0] |= FirstFrag;
5685         else {
5686                 opts[0] |= FirstFrag | LastFrag;
5687                 tp->tx_skb[entry].skb = skb;
5688         }
5689
5690         txd->opts2 = cpu_to_le32(opts[1]);
5691
5692         skb_tx_timestamp(skb);
5693
5694         /* Force memory writes to complete before releasing descriptor */
5695         dma_wmb();
5696
5697         door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
5698
5699         txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
5700
5701         /* Force all memory writes to complete before notifying device */
5702         wmb();
5703
5704         tp->cur_tx += frags + 1;
5705
5706         stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
5707         if (unlikely(stop_queue)) {
5708                 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5709                  * not miss a ring update when it notices a stopped queue.
5710                  */
5711                 smp_wmb();
5712                 netif_stop_queue(dev);
5713                 door_bell = true;
5714         }
5715
5716         if (door_bell)
5717                 rtl8169_doorbell(tp);
5718
5719         if (unlikely(stop_queue)) {
5720                 /* Sync with rtl_tx:
5721                  * - publish queue status and cur_tx ring index (write barrier)
5722                  * - refresh dirty_tx ring index (read barrier).
5723                  * May the current thread have a pessimistic view of the ring
5724                  * status and forget to wake up queue, a racing rtl_tx thread
5725                  * can't.
5726                  */
5727                 smp_mb();
5728                 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
5729                         netif_start_queue(dev);
5730         }
5731
5732         return NETDEV_TX_OK;
5733
5734 err_dma_1:
5735         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5736 err_dma_0:
5737         dev_kfree_skb_any(skb);
5738         dev->stats.tx_dropped++;
5739         return NETDEV_TX_OK;
5740
5741 err_stop_0:
5742         netif_stop_queue(dev);
5743         dev->stats.tx_dropped++;
5744         return NETDEV_TX_BUSY;
5745 }
5746
5747 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
5748                                                 struct net_device *dev,
5749                                                 netdev_features_t features)
5750 {
5751         int transport_offset = skb_transport_offset(skb);
5752         struct rtl8169_private *tp = netdev_priv(dev);
5753
5754         if (skb_is_gso(skb)) {
5755                 if (transport_offset > GTTCPHO_MAX &&
5756                     rtl_chip_supports_csum_v2(tp))
5757                         features &= ~NETIF_F_ALL_TSO;
5758         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5759                 if (skb->len < ETH_ZLEN) {
5760                         switch (tp->mac_version) {
5761                         case RTL_GIGA_MAC_VER_11:
5762                         case RTL_GIGA_MAC_VER_12:
5763                         case RTL_GIGA_MAC_VER_17:
5764                         case RTL_GIGA_MAC_VER_34:
5765                                 features &= ~NETIF_F_CSUM_MASK;
5766                                 break;
5767                         default:
5768                                 break;
5769                         }
5770                 }
5771
5772                 if (transport_offset > TCPHO_MAX &&
5773                     rtl_chip_supports_csum_v2(tp))
5774                         features &= ~NETIF_F_CSUM_MASK;
5775         }
5776
5777         return vlan_features_check(skb, features);
5778 }
5779
5780 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5781 {
5782         struct rtl8169_private *tp = netdev_priv(dev);
5783         struct pci_dev *pdev = tp->pci_dev;
5784         u16 pci_status, pci_cmd;
5785
5786         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5787         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5788
5789         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5790                   pci_cmd, pci_status);
5791
5792         /*
5793          * The recovery sequence below admits a very elaborated explanation:
5794          * - it seems to work;
5795          * - I did not see what else could be done;
5796          * - it makes iop3xx happy.
5797          *
5798          * Feel free to adjust to your needs.
5799          */
5800         if (pdev->broken_parity_status)
5801                 pci_cmd &= ~PCI_COMMAND_PARITY;
5802         else
5803                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5804
5805         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5806
5807         pci_write_config_word(pdev, PCI_STATUS,
5808                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5809                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5810                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5811
5812         rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5813 }
5814
5815 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
5816                    int budget)
5817 {
5818         unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
5819
5820         dirty_tx = tp->dirty_tx;
5821         smp_rmb();
5822         tx_left = tp->cur_tx - dirty_tx;
5823
5824         while (tx_left > 0) {
5825                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5826                 struct ring_info *tx_skb = tp->tx_skb + entry;
5827                 u32 status;
5828
5829                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5830                 if (status & DescOwn)
5831                         break;
5832
5833                 /* This barrier is needed to keep us from reading
5834                  * any other fields out of the Tx descriptor until
5835                  * we know the status of DescOwn
5836                  */
5837                 dma_rmb();
5838
5839                 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5840                                      tp->TxDescArray + entry);
5841                 if (tx_skb->skb) {
5842                         pkts_compl++;
5843                         bytes_compl += tx_skb->skb->len;
5844                         napi_consume_skb(tx_skb->skb, budget);
5845                         tx_skb->skb = NULL;
5846                 }
5847                 dirty_tx++;
5848                 tx_left--;
5849         }
5850
5851         if (tp->dirty_tx != dirty_tx) {
5852                 netdev_completed_queue(dev, pkts_compl, bytes_compl);
5853
5854                 u64_stats_update_begin(&tp->tx_stats.syncp);
5855                 tp->tx_stats.packets += pkts_compl;
5856                 tp->tx_stats.bytes += bytes_compl;
5857                 u64_stats_update_end(&tp->tx_stats.syncp);
5858
5859                 tp->dirty_tx = dirty_tx;
5860                 /* Sync with rtl8169_start_xmit:
5861                  * - publish dirty_tx ring index (write barrier)
5862                  * - refresh cur_tx ring index and queue status (read barrier)
5863                  * May the current thread miss the stopped queue condition,
5864                  * a racing xmit thread can only have a right view of the
5865                  * ring status.
5866                  */
5867                 smp_mb();
5868                 if (netif_queue_stopped(dev) &&
5869                     rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
5870                         netif_wake_queue(dev);
5871                 }
5872                 /*
5873                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5874                  * too close. Let's kick an extra TxPoll request when a burst
5875                  * of start_xmit activity is detected (if it is not detected,
5876                  * it is slow enough). -- FR
5877                  */
5878                 if (tp->cur_tx != dirty_tx)
5879                         rtl8169_doorbell(tp);
5880         }
5881 }
5882
5883 static inline int rtl8169_fragmented_frame(u32 status)
5884 {
5885         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5886 }
5887
5888 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5889 {
5890         u32 status = opts1 & RxProtoMask;
5891
5892         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5893             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5894                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5895         else
5896                 skb_checksum_none_assert(skb);
5897 }
5898
5899 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
5900 {
5901         unsigned int cur_rx, rx_left;
5902         unsigned int count;
5903
5904         cur_rx = tp->cur_rx;
5905
5906         for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
5907                 unsigned int entry = cur_rx % NUM_RX_DESC;
5908                 const void *rx_buf = page_address(tp->Rx_databuff[entry]);
5909                 struct RxDesc *desc = tp->RxDescArray + entry;
5910                 u32 status;
5911
5912                 status = le32_to_cpu(desc->opts1);
5913                 if (status & DescOwn)
5914                         break;
5915
5916                 /* This barrier is needed to keep us from reading
5917                  * any other fields out of the Rx descriptor until
5918                  * we know the status of DescOwn
5919                  */
5920                 dma_rmb();
5921
5922                 if (unlikely(status & RxRES)) {
5923                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5924                                    status);
5925                         dev->stats.rx_errors++;
5926                         if (status & (RxRWT | RxRUNT))
5927                                 dev->stats.rx_length_errors++;
5928                         if (status & RxCRC)
5929                                 dev->stats.rx_crc_errors++;
5930                         if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
5931                             dev->features & NETIF_F_RXALL) {
5932                                 goto process_pkt;
5933                         }
5934                 } else {
5935                         unsigned int pkt_size;
5936                         struct sk_buff *skb;
5937
5938 process_pkt:
5939                         pkt_size = status & GENMASK(13, 0);
5940                         if (likely(!(dev->features & NETIF_F_RXFCS)))
5941                                 pkt_size -= ETH_FCS_LEN;
5942                         /*
5943                          * The driver does not support incoming fragmented
5944                          * frames. They are seen as a symptom of over-mtu
5945                          * sized frames.
5946                          */
5947                         if (unlikely(rtl8169_fragmented_frame(status))) {
5948                                 dev->stats.rx_dropped++;
5949                                 dev->stats.rx_length_errors++;
5950                                 goto release_descriptor;
5951                         }
5952
5953                         skb = napi_alloc_skb(&tp->napi, pkt_size);
5954                         if (unlikely(!skb)) {
5955                                 dev->stats.rx_dropped++;
5956                                 goto release_descriptor;
5957                         }
5958
5959                         dma_sync_single_for_cpu(tp_to_dev(tp),
5960                                                 le64_to_cpu(desc->addr),
5961                                                 pkt_size, DMA_FROM_DEVICE);
5962                         prefetch(rx_buf);
5963                         skb_copy_to_linear_data(skb, rx_buf, pkt_size);
5964                         skb->tail += pkt_size;
5965                         skb->len = pkt_size;
5966
5967                         dma_sync_single_for_device(tp_to_dev(tp),
5968                                                    le64_to_cpu(desc->addr),
5969                                                    pkt_size, DMA_FROM_DEVICE);
5970
5971                         rtl8169_rx_csum(skb, status);
5972                         skb->protocol = eth_type_trans(skb, dev);
5973
5974                         rtl8169_rx_vlan_tag(desc, skb);
5975
5976                         if (skb->pkt_type == PACKET_MULTICAST)
5977                                 dev->stats.multicast++;
5978
5979                         napi_gro_receive(&tp->napi, skb);
5980
5981                         u64_stats_update_begin(&tp->rx_stats.syncp);
5982                         tp->rx_stats.packets++;
5983                         tp->rx_stats.bytes += pkt_size;
5984                         u64_stats_update_end(&tp->rx_stats.syncp);
5985                 }
5986 release_descriptor:
5987                 desc->opts2 = 0;
5988                 rtl8169_mark_to_asic(desc);
5989         }
5990
5991         count = cur_rx - tp->cur_rx;
5992         tp->cur_rx = cur_rx;
5993
5994         return count;
5995 }
5996
5997 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5998 {
5999         struct rtl8169_private *tp = dev_instance;
6000         u32 status = rtl_get_events(tp);
6001
6002         if (!tp->irq_enabled || (status & 0xffff) == 0xffff ||
6003             !(status & tp->irq_mask))
6004                 return IRQ_NONE;
6005
6006         if (unlikely(status & SYSErr)) {
6007                 rtl8169_pcierr_interrupt(tp->dev);
6008                 goto out;
6009         }
6010
6011         if (status & LinkChg)
6012                 phy_mac_interrupt(tp->phydev);
6013
6014         if (unlikely(status & RxFIFOOver &&
6015             tp->mac_version == RTL_GIGA_MAC_VER_11)) {
6016                 netif_stop_queue(tp->dev);
6017                 /* XXX - Hack alert. See rtl_task(). */
6018                 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6019         }
6020
6021         rtl_irq_disable(tp);
6022         napi_schedule_irqoff(&tp->napi);
6023 out:
6024         rtl_ack_events(tp, status);
6025
6026         return IRQ_HANDLED;
6027 }
6028
6029 static void rtl_task(struct work_struct *work)
6030 {
6031         static const struct {
6032                 int bitnr;
6033                 void (*action)(struct rtl8169_private *);
6034         } rtl_work[] = {
6035                 { RTL_FLAG_TASK_RESET_PENDING,  rtl_reset_work },
6036         };
6037         struct rtl8169_private *tp =
6038                 container_of(work, struct rtl8169_private, wk.work);
6039         struct net_device *dev = tp->dev;
6040         int i;
6041
6042         rtl_lock_work(tp);
6043
6044         if (!netif_running(dev) ||
6045             !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6046                 goto out_unlock;
6047
6048         for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6049                 bool pending;
6050
6051                 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6052                 if (pending)
6053                         rtl_work[i].action(tp);
6054         }
6055
6056 out_unlock:
6057         rtl_unlock_work(tp);
6058 }
6059
6060 static int rtl8169_poll(struct napi_struct *napi, int budget)
6061 {
6062         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6063         struct net_device *dev = tp->dev;
6064         int work_done;
6065
6066         work_done = rtl_rx(dev, tp, (u32) budget);
6067
6068         rtl_tx(dev, tp, budget);
6069
6070         if (work_done < budget) {
6071                 napi_complete_done(napi, work_done);
6072                 rtl_irq_enable(tp);
6073         }
6074
6075         return work_done;
6076 }
6077
6078 static void rtl8169_rx_missed(struct net_device *dev)
6079 {
6080         struct rtl8169_private *tp = netdev_priv(dev);
6081
6082         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6083                 return;
6084
6085         dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6086         RTL_W32(tp, RxMissed, 0);
6087 }
6088
6089 static void r8169_phylink_handler(struct net_device *ndev)
6090 {
6091         struct rtl8169_private *tp = netdev_priv(ndev);
6092
6093         if (netif_carrier_ok(ndev)) {
6094                 rtl_link_chg_patch(tp);
6095                 pm_request_resume(&tp->pci_dev->dev);
6096         } else {
6097                 pm_runtime_idle(&tp->pci_dev->dev);
6098         }
6099
6100         if (net_ratelimit())
6101                 phy_print_status(tp->phydev);
6102 }
6103
6104 static int r8169_phy_connect(struct rtl8169_private *tp)
6105 {
6106         struct phy_device *phydev = tp->phydev;
6107         phy_interface_t phy_mode;
6108         int ret;
6109
6110         phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6111                    PHY_INTERFACE_MODE_MII;
6112
6113         ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6114                                  phy_mode);
6115         if (ret)
6116                 return ret;
6117
6118         if (!tp->supports_gmii)
6119                 phy_set_max_speed(phydev, SPEED_100);
6120
6121         phy_support_asym_pause(phydev);
6122
6123         phy_attached_info(phydev);
6124
6125         return 0;
6126 }
6127
6128 static void rtl8169_down(struct net_device *dev)
6129 {
6130         struct rtl8169_private *tp = netdev_priv(dev);
6131
6132         phy_stop(tp->phydev);
6133
6134         napi_disable(&tp->napi);
6135         netif_stop_queue(dev);
6136
6137         rtl8169_hw_reset(tp);
6138         /*
6139          * At this point device interrupts can not be enabled in any function,
6140          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6141          * and napi is disabled (rtl8169_poll).
6142          */
6143         rtl8169_rx_missed(dev);
6144
6145         /* Give a racing hard_start_xmit a few cycles to complete. */
6146         synchronize_rcu();
6147
6148         rtl8169_tx_clear(tp);
6149
6150         rtl8169_rx_clear(tp);
6151
6152         rtl_pll_power_down(tp);
6153 }
6154
6155 static int rtl8169_close(struct net_device *dev)
6156 {
6157         struct rtl8169_private *tp = netdev_priv(dev);
6158         struct pci_dev *pdev = tp->pci_dev;
6159
6160         pm_runtime_get_sync(&pdev->dev);
6161
6162         /* Update counters before going down */
6163         rtl8169_update_counters(tp);
6164
6165         rtl_lock_work(tp);
6166         /* Clear all task flags */
6167         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6168
6169         rtl8169_down(dev);
6170         rtl_unlock_work(tp);
6171
6172         cancel_work_sync(&tp->wk.work);
6173
6174         phy_disconnect(tp->phydev);
6175
6176         pci_free_irq(pdev, 0, tp);
6177
6178         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6179                           tp->RxPhyAddr);
6180         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6181                           tp->TxPhyAddr);
6182         tp->TxDescArray = NULL;
6183         tp->RxDescArray = NULL;
6184
6185         pm_runtime_put_sync(&pdev->dev);
6186
6187         return 0;
6188 }
6189
6190 #ifdef CONFIG_NET_POLL_CONTROLLER
6191 static void rtl8169_netpoll(struct net_device *dev)
6192 {
6193         struct rtl8169_private *tp = netdev_priv(dev);
6194
6195         rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6196 }
6197 #endif
6198
6199 static int rtl_open(struct net_device *dev)
6200 {
6201         struct rtl8169_private *tp = netdev_priv(dev);
6202         struct pci_dev *pdev = tp->pci_dev;
6203         int retval = -ENOMEM;
6204
6205         pm_runtime_get_sync(&pdev->dev);
6206
6207         /*
6208          * Rx and Tx descriptors needs 256 bytes alignment.
6209          * dma_alloc_coherent provides more.
6210          */
6211         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6212                                              &tp->TxPhyAddr, GFP_KERNEL);
6213         if (!tp->TxDescArray)
6214                 goto err_pm_runtime_put;
6215
6216         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6217                                              &tp->RxPhyAddr, GFP_KERNEL);
6218         if (!tp->RxDescArray)
6219                 goto err_free_tx_0;
6220
6221         retval = rtl8169_init_ring(tp);
6222         if (retval < 0)
6223                 goto err_free_rx_1;
6224
6225         rtl_request_firmware(tp);
6226
6227         retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6228                                  dev->name);
6229         if (retval < 0)
6230                 goto err_release_fw_2;
6231
6232         retval = r8169_phy_connect(tp);
6233         if (retval)
6234                 goto err_free_irq;
6235
6236         rtl_lock_work(tp);
6237
6238         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6239
6240         napi_enable(&tp->napi);
6241
6242         rtl8169_init_phy(dev, tp);
6243
6244         rtl_pll_power_up(tp);
6245
6246         rtl_hw_start(tp);
6247
6248         if (!rtl8169_init_counter_offsets(tp))
6249                 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6250
6251         phy_start(tp->phydev);
6252         netif_start_queue(dev);
6253
6254         rtl_unlock_work(tp);
6255
6256         pm_runtime_put_sync(&pdev->dev);
6257 out:
6258         return retval;
6259
6260 err_free_irq:
6261         pci_free_irq(pdev, 0, tp);
6262 err_release_fw_2:
6263         rtl_release_firmware(tp);
6264         rtl8169_rx_clear(tp);
6265 err_free_rx_1:
6266         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6267                           tp->RxPhyAddr);
6268         tp->RxDescArray = NULL;
6269 err_free_tx_0:
6270         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6271                           tp->TxPhyAddr);
6272         tp->TxDescArray = NULL;
6273 err_pm_runtime_put:
6274         pm_runtime_put_noidle(&pdev->dev);
6275         goto out;
6276 }
6277
6278 static void
6279 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6280 {
6281         struct rtl8169_private *tp = netdev_priv(dev);
6282         struct pci_dev *pdev = tp->pci_dev;
6283         struct rtl8169_counters *counters = tp->counters;
6284         unsigned int start;
6285
6286         pm_runtime_get_noresume(&pdev->dev);
6287
6288         if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6289                 rtl8169_rx_missed(dev);
6290
6291         do {
6292                 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6293                 stats->rx_packets = tp->rx_stats.packets;
6294                 stats->rx_bytes = tp->rx_stats.bytes;
6295         } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6296
6297         do {
6298                 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6299                 stats->tx_packets = tp->tx_stats.packets;
6300                 stats->tx_bytes = tp->tx_stats.bytes;
6301         } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6302
6303         stats->rx_dropped       = dev->stats.rx_dropped;
6304         stats->tx_dropped       = dev->stats.tx_dropped;
6305         stats->rx_length_errors = dev->stats.rx_length_errors;
6306         stats->rx_errors        = dev->stats.rx_errors;
6307         stats->rx_crc_errors    = dev->stats.rx_crc_errors;
6308         stats->rx_fifo_errors   = dev->stats.rx_fifo_errors;
6309         stats->rx_missed_errors = dev->stats.rx_missed_errors;
6310         stats->multicast        = dev->stats.multicast;
6311
6312         /*
6313          * Fetch additional counter values missing in stats collected by driver
6314          * from tally counters.
6315          */
6316         if (pm_runtime_active(&pdev->dev))
6317                 rtl8169_update_counters(tp);
6318
6319         /*
6320          * Subtract values fetched during initalization.
6321          * See rtl8169_init_counter_offsets for a description why we do that.
6322          */
6323         stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6324                 le64_to_cpu(tp->tc_offset.tx_errors);
6325         stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6326                 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6327         stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6328                 le16_to_cpu(tp->tc_offset.tx_aborted);
6329
6330         pm_runtime_put_noidle(&pdev->dev);
6331 }
6332
6333 static void rtl8169_net_suspend(struct net_device *dev)
6334 {
6335         struct rtl8169_private *tp = netdev_priv(dev);
6336
6337         if (!netif_running(dev))
6338                 return;
6339
6340         phy_stop(tp->phydev);
6341         netif_device_detach(dev);
6342
6343         rtl_lock_work(tp);
6344         napi_disable(&tp->napi);
6345         /* Clear all task flags */
6346         bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6347
6348         rtl_unlock_work(tp);
6349
6350         rtl_pll_power_down(tp);
6351 }
6352
6353 #ifdef CONFIG_PM
6354
6355 static int rtl8169_suspend(struct device *device)
6356 {
6357         struct net_device *dev = dev_get_drvdata(device);
6358         struct rtl8169_private *tp = netdev_priv(dev);
6359
6360         rtl8169_net_suspend(dev);
6361         clk_disable_unprepare(tp->clk);
6362
6363         return 0;
6364 }
6365
6366 static void __rtl8169_resume(struct net_device *dev)
6367 {
6368         struct rtl8169_private *tp = netdev_priv(dev);
6369
6370         netif_device_attach(dev);
6371
6372         rtl_pll_power_up(tp);
6373         rtl8169_init_phy(dev, tp);
6374
6375         phy_start(tp->phydev);
6376
6377         rtl_lock_work(tp);
6378         napi_enable(&tp->napi);
6379         set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6380         rtl_reset_work(tp);
6381         rtl_unlock_work(tp);
6382 }
6383
6384 static int rtl8169_resume(struct device *device)
6385 {
6386         struct net_device *dev = dev_get_drvdata(device);
6387         struct rtl8169_private *tp = netdev_priv(dev);
6388
6389         rtl_rar_set(tp, dev->dev_addr);
6390
6391         clk_prepare_enable(tp->clk);
6392
6393         if (netif_running(dev))
6394                 __rtl8169_resume(dev);
6395
6396         return 0;
6397 }
6398
6399 static int rtl8169_runtime_suspend(struct device *device)
6400 {
6401         struct net_device *dev = dev_get_drvdata(device);
6402         struct rtl8169_private *tp = netdev_priv(dev);
6403
6404         if (!tp->TxDescArray)
6405                 return 0;
6406
6407         rtl_lock_work(tp);
6408         __rtl8169_set_wol(tp, WAKE_ANY);
6409         rtl_unlock_work(tp);
6410
6411         rtl8169_net_suspend(dev);
6412
6413         /* Update counters before going runtime suspend */
6414         rtl8169_rx_missed(dev);
6415         rtl8169_update_counters(tp);
6416
6417         return 0;
6418 }
6419
6420 static int rtl8169_runtime_resume(struct device *device)
6421 {
6422         struct net_device *dev = dev_get_drvdata(device);
6423         struct rtl8169_private *tp = netdev_priv(dev);
6424
6425         rtl_rar_set(tp, dev->dev_addr);
6426
6427         if (!tp->TxDescArray)
6428                 return 0;
6429
6430         rtl_lock_work(tp);
6431         __rtl8169_set_wol(tp, tp->saved_wolopts);
6432         rtl_unlock_work(tp);
6433
6434         __rtl8169_resume(dev);
6435
6436         return 0;
6437 }
6438
6439 static int rtl8169_runtime_idle(struct device *device)
6440 {
6441         struct net_device *dev = dev_get_drvdata(device);
6442
6443         if (!netif_running(dev) || !netif_carrier_ok(dev))
6444                 pm_schedule_suspend(device, 10000);
6445
6446         return -EBUSY;
6447 }
6448
6449 static const struct dev_pm_ops rtl8169_pm_ops = {
6450         .suspend                = rtl8169_suspend,
6451         .resume                 = rtl8169_resume,
6452         .freeze                 = rtl8169_suspend,
6453         .thaw                   = rtl8169_resume,
6454         .poweroff               = rtl8169_suspend,
6455         .restore                = rtl8169_resume,
6456         .runtime_suspend        = rtl8169_runtime_suspend,
6457         .runtime_resume         = rtl8169_runtime_resume,
6458         .runtime_idle           = rtl8169_runtime_idle,
6459 };
6460
6461 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6462
6463 #else /* !CONFIG_PM */
6464
6465 #define RTL8169_PM_OPS  NULL
6466
6467 #endif /* !CONFIG_PM */
6468
6469 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6470 {
6471         /* WoL fails with 8168b when the receiver is disabled. */
6472         switch (tp->mac_version) {
6473         case RTL_GIGA_MAC_VER_11:
6474         case RTL_GIGA_MAC_VER_12:
6475         case RTL_GIGA_MAC_VER_17:
6476                 pci_clear_master(tp->pci_dev);
6477
6478                 RTL_W8(tp, ChipCmd, CmdRxEnb);
6479                 /* PCI commit */
6480                 RTL_R8(tp, ChipCmd);
6481                 break;
6482         default:
6483                 break;
6484         }
6485 }
6486
6487 static void rtl_shutdown(struct pci_dev *pdev)
6488 {
6489         struct net_device *dev = pci_get_drvdata(pdev);
6490         struct rtl8169_private *tp = netdev_priv(dev);
6491
6492         rtl8169_net_suspend(dev);
6493
6494         /* Restore original MAC address */
6495         rtl_rar_set(tp, dev->perm_addr);
6496
6497         rtl8169_hw_reset(tp);
6498
6499         if (system_state == SYSTEM_POWER_OFF) {
6500                 if (tp->saved_wolopts) {
6501                         rtl_wol_suspend_quirk(tp);
6502                         rtl_wol_shutdown_quirk(tp);
6503                 }
6504
6505                 pci_wake_from_d3(pdev, true);
6506                 pci_set_power_state(pdev, PCI_D3hot);
6507         }
6508 }
6509
6510 static void rtl_remove_one(struct pci_dev *pdev)
6511 {
6512         struct net_device *dev = pci_get_drvdata(pdev);
6513         struct rtl8169_private *tp = netdev_priv(dev);
6514
6515         if (r8168_check_dash(tp))
6516                 rtl8168_driver_stop(tp);
6517
6518         netif_napi_del(&tp->napi);
6519
6520         unregister_netdev(dev);
6521         mdiobus_unregister(tp->phydev->mdio.bus);
6522
6523         rtl_release_firmware(tp);
6524
6525         if (pci_dev_run_wake(pdev))
6526                 pm_runtime_get_noresume(&pdev->dev);
6527
6528         /* restore original MAC address */
6529         rtl_rar_set(tp, dev->perm_addr);
6530 }
6531
6532 static const struct net_device_ops rtl_netdev_ops = {
6533         .ndo_open               = rtl_open,
6534         .ndo_stop               = rtl8169_close,
6535         .ndo_get_stats64        = rtl8169_get_stats64,
6536         .ndo_start_xmit         = rtl8169_start_xmit,
6537         .ndo_features_check     = rtl8169_features_check,
6538         .ndo_tx_timeout         = rtl8169_tx_timeout,
6539         .ndo_validate_addr      = eth_validate_addr,
6540         .ndo_change_mtu         = rtl8169_change_mtu,
6541         .ndo_fix_features       = rtl8169_fix_features,
6542         .ndo_set_features       = rtl8169_set_features,
6543         .ndo_set_mac_address    = rtl_set_mac_address,
6544         .ndo_do_ioctl           = rtl8169_ioctl,
6545         .ndo_set_rx_mode        = rtl_set_rx_mode,
6546 #ifdef CONFIG_NET_POLL_CONTROLLER
6547         .ndo_poll_controller    = rtl8169_netpoll,
6548 #endif
6549
6550 };
6551
6552 static void rtl_set_irq_mask(struct rtl8169_private *tp)
6553 {
6554         tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
6555
6556         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
6557                 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
6558         else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
6559                 /* special workaround needed */
6560                 tp->irq_mask |= RxFIFOOver;
6561         else
6562                 tp->irq_mask |= RxOverflow;
6563 }
6564
6565 static int rtl_alloc_irq(struct rtl8169_private *tp)
6566 {
6567         unsigned int flags;
6568
6569         switch (tp->mac_version) {
6570         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6571                 rtl_unlock_config_regs(tp);
6572                 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
6573                 rtl_lock_config_regs(tp);
6574                 /* fall through */
6575         case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24:
6576                 flags = PCI_IRQ_LEGACY;
6577                 break;
6578         default:
6579                 flags = PCI_IRQ_ALL_TYPES;
6580                 break;
6581         }
6582
6583         return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
6584 }
6585
6586 static void rtl_read_mac_address(struct rtl8169_private *tp,
6587                                  u8 mac_addr[ETH_ALEN])
6588 {
6589         /* Get MAC address */
6590         if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
6591                 u32 value = rtl_eri_read(tp, 0xe0);
6592
6593                 mac_addr[0] = (value >>  0) & 0xff;
6594                 mac_addr[1] = (value >>  8) & 0xff;
6595                 mac_addr[2] = (value >> 16) & 0xff;
6596                 mac_addr[3] = (value >> 24) & 0xff;
6597
6598                 value = rtl_eri_read(tp, 0xe4);
6599                 mac_addr[4] = (value >>  0) & 0xff;
6600                 mac_addr[5] = (value >>  8) & 0xff;
6601         } else if (rtl_is_8125(tp)) {
6602                 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
6603         }
6604 }
6605
6606 DECLARE_RTL_COND(rtl_link_list_ready_cond)
6607 {
6608         return RTL_R8(tp, MCU) & LINK_LIST_RDY;
6609 }
6610
6611 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
6612 {
6613         return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
6614 }
6615
6616 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
6617 {
6618         struct rtl8169_private *tp = mii_bus->priv;
6619
6620         if (phyaddr > 0)
6621                 return -ENODEV;
6622
6623         return rtl_readphy(tp, phyreg);
6624 }
6625
6626 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
6627                                 int phyreg, u16 val)
6628 {
6629         struct rtl8169_private *tp = mii_bus->priv;
6630
6631         if (phyaddr > 0)
6632                 return -ENODEV;
6633
6634         rtl_writephy(tp, phyreg, val);
6635
6636         return 0;
6637 }
6638
6639 static int r8169_mdio_register(struct rtl8169_private *tp)
6640 {
6641         struct pci_dev *pdev = tp->pci_dev;
6642         struct mii_bus *new_bus;
6643         int ret;
6644
6645         new_bus = devm_mdiobus_alloc(&pdev->dev);
6646         if (!new_bus)
6647                 return -ENOMEM;
6648
6649         new_bus->name = "r8169";
6650         new_bus->priv = tp;
6651         new_bus->parent = &pdev->dev;
6652         new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
6653         snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
6654
6655         new_bus->read = r8169_mdio_read_reg;
6656         new_bus->write = r8169_mdio_write_reg;
6657
6658         ret = mdiobus_register(new_bus);
6659         if (ret)
6660                 return ret;
6661
6662         tp->phydev = mdiobus_get_phy(new_bus, 0);
6663         if (!tp->phydev) {
6664                 mdiobus_unregister(new_bus);
6665                 return -ENODEV;
6666         }
6667
6668         /* PHY will be woken up in rtl_open() */
6669         phy_suspend(tp->phydev);
6670
6671         return 0;
6672 }
6673
6674 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
6675 {
6676         tp->ocp_base = OCP_STD_PHY_BASE;
6677
6678         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6679
6680         if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
6681                 return;
6682
6683         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6684                 return;
6685
6686         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6687         msleep(1);
6688         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6689
6690         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6691
6692         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6693                 return;
6694
6695         r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
6696
6697         rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6698 }
6699
6700 static void rtl_hw_init_8125(struct rtl8169_private *tp)
6701 {
6702         tp->ocp_base = OCP_STD_PHY_BASE;
6703
6704         RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
6705
6706         if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
6707                 return;
6708
6709         RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
6710         msleep(1);
6711         RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
6712
6713         r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
6714
6715         if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
6716                 return;
6717
6718         r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
6719         r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
6720         r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
6721
6722         rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
6723 }
6724
6725 static void rtl_hw_initialize(struct rtl8169_private *tp)
6726 {
6727         switch (tp->mac_version) {
6728         case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
6729                 rtl8168ep_stop_cmac(tp);
6730                 /* fall through */
6731         case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
6732                 rtl_hw_init_8168g(tp);
6733                 break;
6734         case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
6735                 rtl_hw_init_8125(tp);
6736                 break;
6737         default:
6738                 break;
6739         }
6740 }
6741
6742 static int rtl_jumbo_max(struct rtl8169_private *tp)
6743 {
6744         /* Non-GBit versions don't support jumbo frames */
6745         if (!tp->supports_gmii)
6746                 return JUMBO_1K;
6747
6748         switch (tp->mac_version) {
6749         /* RTL8169 */
6750         case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
6751                 return JUMBO_7K;
6752         /* RTL8168b */
6753         case RTL_GIGA_MAC_VER_11:
6754         case RTL_GIGA_MAC_VER_12:
6755         case RTL_GIGA_MAC_VER_17:
6756                 return JUMBO_4K;
6757         /* RTL8168c */
6758         case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
6759                 return JUMBO_6K;
6760         default:
6761                 return JUMBO_9K;
6762         }
6763 }
6764
6765 static void rtl_disable_clk(void *data)
6766 {
6767         clk_disable_unprepare(data);
6768 }
6769
6770 static int rtl_get_ether_clk(struct rtl8169_private *tp)
6771 {
6772         struct device *d = tp_to_dev(tp);
6773         struct clk *clk;
6774         int rc;
6775
6776         clk = devm_clk_get(d, "ether_clk");
6777         if (IS_ERR(clk)) {
6778                 rc = PTR_ERR(clk);
6779                 if (rc == -ENOENT)
6780                         /* clk-core allows NULL (for suspend / resume) */
6781                         rc = 0;
6782                 else if (rc != -EPROBE_DEFER)
6783                         dev_err(d, "failed to get clk: %d\n", rc);
6784         } else {
6785                 tp->clk = clk;
6786                 rc = clk_prepare_enable(clk);
6787                 if (rc)
6788                         dev_err(d, "failed to enable clk: %d\n", rc);
6789                 else
6790                         rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
6791         }
6792
6793         return rc;
6794 }
6795
6796 static void rtl_init_mac_address(struct rtl8169_private *tp)
6797 {
6798         struct net_device *dev = tp->dev;
6799         u8 *mac_addr = dev->dev_addr;
6800         int rc;
6801
6802         rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
6803         if (!rc)
6804                 goto done;
6805
6806         rtl_read_mac_address(tp, mac_addr);
6807         if (is_valid_ether_addr(mac_addr))
6808                 goto done;
6809
6810         rtl_read_mac_from_reg(tp, mac_addr, MAC0);
6811         if (is_valid_ether_addr(mac_addr))
6812                 goto done;
6813
6814         eth_hw_addr_random(dev);
6815         dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
6816 done:
6817         rtl_rar_set(tp, mac_addr);
6818 }
6819
6820 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6821 {
6822         struct rtl8169_private *tp;
6823         struct net_device *dev;
6824         int chipset, region;
6825         int jumbo_max, rc;
6826
6827         dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
6828         if (!dev)
6829                 return -ENOMEM;
6830
6831         SET_NETDEV_DEV(dev, &pdev->dev);
6832         dev->netdev_ops = &rtl_netdev_ops;
6833         tp = netdev_priv(dev);
6834         tp->dev = dev;
6835         tp->pci_dev = pdev;
6836         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
6837         tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
6838         tp->eee_adv = -1;
6839
6840         /* Get the *optional* external "ether_clk" used on some boards */
6841         rc = rtl_get_ether_clk(tp);
6842         if (rc)
6843                 return rc;
6844
6845         /* Disable ASPM completely as that cause random device stop working
6846          * problems as well as full system hangs for some PCIe devices users.
6847          */
6848         rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
6849                                           PCIE_LINK_STATE_L1);
6850         tp->aspm_manageable = !rc;
6851
6852         /* enable device (incl. PCI PM wakeup and hotplug setup) */
6853         rc = pcim_enable_device(pdev);
6854         if (rc < 0) {
6855                 dev_err(&pdev->dev, "enable failure\n");
6856                 return rc;
6857         }
6858
6859         if (pcim_set_mwi(pdev) < 0)
6860                 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
6861
6862         /* use first MMIO region */
6863         region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
6864         if (region < 0) {
6865                 dev_err(&pdev->dev, "no MMIO resource found\n");
6866                 return -ENODEV;
6867         }
6868
6869         /* check for weird/broken PCI region reporting */
6870         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
6871                 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
6872                 return -ENODEV;
6873         }
6874
6875         rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
6876         if (rc < 0) {
6877                 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
6878                 return rc;
6879         }
6880
6881         tp->mmio_addr = pcim_iomap_table(pdev)[region];
6882
6883         /* Identify chip attached to board */
6884         rtl8169_get_mac_version(tp);
6885         if (tp->mac_version == RTL_GIGA_MAC_NONE)
6886                 return -ENODEV;
6887
6888         tp->cp_cmd = RTL_R16(tp, CPlusCmd);
6889
6890         if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
6891             !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
6892                 dev->features |= NETIF_F_HIGHDMA;
6893
6894         rtl_init_rxcfg(tp);
6895
6896         rtl8169_irq_mask_and_ack(tp);
6897
6898         rtl_hw_initialize(tp);
6899
6900         rtl_hw_reset(tp);
6901
6902         pci_set_master(pdev);
6903
6904         chipset = tp->mac_version;
6905
6906         rc = rtl_alloc_irq(tp);
6907         if (rc < 0) {
6908                 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6909                 return rc;
6910         }
6911
6912         mutex_init(&tp->wk.mutex);
6913         INIT_WORK(&tp->wk.work, rtl_task);
6914         u64_stats_init(&tp->rx_stats.syncp);
6915         u64_stats_init(&tp->tx_stats.syncp);
6916
6917         rtl_init_mac_address(tp);
6918
6919         dev->ethtool_ops = &rtl8169_ethtool_ops;
6920
6921         netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
6922
6923         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6924                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6925                 NETIF_F_HW_VLAN_CTAG_RX;
6926         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6927                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
6928                 NETIF_F_HW_VLAN_CTAG_RX;
6929         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
6930                 NETIF_F_HIGHDMA;
6931         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
6932
6933         tp->cp_cmd |= RxChkSum;
6934         /* RTL8125 uses register RxConfig for VLAN offloading config */
6935         if (!rtl_is_8125(tp))
6936                 tp->cp_cmd |= RxVlan;
6937         /*
6938          * Pretend we are using VLANs; This bypasses a nasty bug where
6939          * Interrupts stop flowing on high load on 8110SCd controllers.
6940          */
6941         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
6942                 /* Disallow toggling */
6943                 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
6944
6945         if (rtl_chip_supports_csum_v2(tp)) {
6946                 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6947                 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
6948                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
6949                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
6950         } else {
6951                 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
6952                 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
6953         }
6954
6955         /* RTL8168e-vl and one RTL8168c variant are known to have a
6956          * HW issue with TSO.
6957          */
6958         if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
6959             tp->mac_version == RTL_GIGA_MAC_VER_22) {
6960                 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
6961                 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
6962                 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
6963         }
6964
6965         dev->hw_features |= NETIF_F_RXALL;
6966         dev->hw_features |= NETIF_F_RXFCS;
6967
6968         /* MTU range: 60 - hw-specific max */
6969         dev->min_mtu = ETH_ZLEN;
6970         jumbo_max = rtl_jumbo_max(tp);
6971         dev->max_mtu = jumbo_max;
6972
6973         rtl_set_irq_mask(tp);
6974
6975         tp->fw_name = rtl_chip_infos[chipset].fw_name;
6976
6977         tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
6978                                             &tp->counters_phys_addr,
6979                                             GFP_KERNEL);
6980         if (!tp->counters)
6981                 return -ENOMEM;
6982
6983         pci_set_drvdata(pdev, dev);
6984
6985         rc = r8169_mdio_register(tp);
6986         if (rc)
6987                 return rc;
6988
6989         /* chip gets powered up in rtl_open() */
6990         rtl_pll_power_down(tp);
6991
6992         rc = register_netdev(dev);
6993         if (rc)
6994                 goto err_mdio_unregister;
6995
6996         netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
6997                    rtl_chip_infos[chipset].name, dev->dev_addr,
6998                    (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
6999                    pci_irq_vector(pdev, 0));
7000
7001         if (jumbo_max > JUMBO_1K)
7002                 netif_info(tp, probe, dev,
7003                            "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7004                            jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7005                            "ok" : "ko");
7006
7007         if (r8168_check_dash(tp))
7008                 rtl8168_driver_start(tp);
7009
7010         if (pci_dev_run_wake(pdev))
7011                 pm_runtime_put_sync(&pdev->dev);
7012
7013         return 0;
7014
7015 err_mdio_unregister:
7016         mdiobus_unregister(tp->phydev->mdio.bus);
7017         return rc;
7018 }
7019
7020 static struct pci_driver rtl8169_pci_driver = {
7021         .name           = MODULENAME,
7022         .id_table       = rtl8169_pci_tbl,
7023         .probe          = rtl_init_one,
7024         .remove         = rtl_remove_one,
7025         .shutdown       = rtl_shutdown,
7026         .driver.pm      = RTL8169_PM_OPS,
7027 };
7028
7029 module_pci_driver(rtl8169_pci_driver);