1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
3 * Microsemi Ocelot Switch driver
5 * Copyright (c) 2017 Microsemi Corporation
8 #ifndef _MSCC_OCELOT_H_
9 #define _MSCC_OCELOT_H_
11 #include <linux/bitops.h>
12 #include <linux/etherdevice.h>
13 #include <linux/if_vlan.h>
14 #include <linux/net_tstamp.h>
15 #include <linux/phy.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/ptp_clock_kernel.h>
19 #include <linux/regmap.h>
21 #include "ocelot_ana.h"
22 #include "ocelot_dev.h"
23 #include "ocelot_qsys.h"
24 #include "ocelot_rew.h"
25 #include "ocelot_sys.h"
26 #include "ocelot_qs.h"
27 #include "ocelot_tc.h"
28 #include "ocelot_ptp.h"
34 #define PGID_CPU (PGID_AGGR - 5)
35 #define PGID_UC (PGID_AGGR - 4)
36 #define PGID_MC (PGID_AGGR - 3)
37 #define PGID_MCIPV4 (PGID_AGGR - 2)
38 #define PGID_MCIPV6 (PGID_AGGR - 1)
40 #define OCELOT_BUFFER_CELL_SZ 60
42 #define OCELOT_STATS_CHECK_DELAY (2 * HZ)
44 #define OCELOT_PTP_QUEUE_SZ 128
54 u32 timestamp; /* rew_val */
57 #define IFH_INJ_BYPASS BIT(31)
58 #define IFH_INJ_POP_CNT_DISABLE (3 << 28)
60 #define IFH_TAG_TYPE_C 0
61 #define IFH_TAG_TYPE_S 1
63 #define IFH_REW_OP_NOOP 0x0
64 #define IFH_REW_OP_DSCP 0x1
65 #define IFH_REW_OP_ONE_STEP_PTP 0x2
66 #define IFH_REW_OP_TWO_STEP_PTP 0x3
67 #define IFH_REW_OP_ORIGIN_PTP 0x5
69 #define OCELOT_SPEED_2500 0
70 #define OCELOT_SPEED_1000 1
71 #define OCELOT_SPEED_100 2
72 #define OCELOT_SPEED_10 3
74 #define TARGET_OFFSET 24
75 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
76 #define REG(reg, offset) [reg & REG_MASK] = offset
91 ANA_ADVLEARN = ANA << TARGET_OFFSET,
115 ANA_TABLES_STREAMDATA,
116 ANA_TABLES_MACACCESS,
118 ANA_TABLES_VLANACCESS,
120 ANA_TABLES_ISDXACCESS,
123 ANA_TABLES_PTP_ID_HIGH,
124 ANA_TABLES_PTP_ID_LOW,
125 ANA_TABLES_STREAMACCESS,
126 ANA_TABLES_STREAMTIDX,
127 ANA_TABLES_SEQ_HISTORY,
129 ANA_TABLES_SFID_MASK,
130 ANA_TABLES_SFIDACCESS,
140 ANA_SG_GCL_GS_CONFIG,
141 ANA_SG_GCL_TI_CONFIG,
149 ANA_PORT_VCAP_S1_KEY_CFG,
150 ANA_PORT_VCAP_S2_CFG,
151 ANA_PORT_PCP_DEI_MAP,
152 ANA_PORT_CPU_FWD_CFG,
153 ANA_PORT_CPU_FWD_BPDU_CFG,
154 ANA_PORT_CPU_FWD_GARP_CFG,
155 ANA_PORT_CPU_FWD_CCM_CFG,
159 ANA_PORT_PTP_DLY1_CFG,
160 ANA_PORT_PTP_DLY2_CFG,
174 ANA_VCAP_RNG_TYPE_CFG,
175 ANA_VCAP_RNG_VAL_CFG,
190 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
202 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
203 QSYS_SWITCH_PORT_MODE,
215 QSYS_TIMED_FRAME_ENTRY,
218 QSYS_TFRM_TIMER_CFG_1,
219 QSYS_TFRM_TIMER_CFG_2,
220 QSYS_TFRM_TIMER_CFG_3,
221 QSYS_TFRM_TIMER_CFG_4,
222 QSYS_TFRM_TIMER_CFG_5,
223 QSYS_TFRM_TIMER_CFG_6,
224 QSYS_TFRM_TIMER_CFG_7,
225 QSYS_TFRM_TIMER_CFG_8,
253 QSYS_TAS_PARAM_CFG_CTRL,
255 QSYS_PARAM_CFG_REG_1,
256 QSYS_PARAM_CFG_REG_2,
257 QSYS_PARAM_CFG_REG_3,
258 QSYS_PARAM_CFG_REG_4,
259 QSYS_PARAM_CFG_REG_5,
262 QSYS_PARAM_STATUS_REG_1,
263 QSYS_PARAM_STATUS_REG_2,
264 QSYS_PARAM_STATUS_REG_3,
265 QSYS_PARAM_STATUS_REG_4,
266 QSYS_PARAM_STATUS_REG_5,
267 QSYS_PARAM_STATUS_REG_6,
268 QSYS_PARAM_STATUS_REG_7,
269 QSYS_PARAM_STATUS_REG_8,
270 QSYS_PARAM_STATUS_REG_9,
271 QSYS_GCL_STATUS_REG_1,
272 QSYS_GCL_STATUS_REG_2,
273 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
277 REW_PCP_DEI_QOS_MAP_CFG,
281 REW_DSCP_REMAP_DP1_CFG,
286 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
287 SYS_COUNT_RX_UNICAST,
288 SYS_COUNT_RX_MULTICAST,
289 SYS_COUNT_RX_BROADCAST,
291 SYS_COUNT_RX_FRAGMENTS,
292 SYS_COUNT_RX_JABBERS,
293 SYS_COUNT_RX_CRC_ALIGN_ERRS,
294 SYS_COUNT_RX_SYM_ERRS,
297 SYS_COUNT_RX_128_255,
298 SYS_COUNT_RX_256_1023,
299 SYS_COUNT_RX_1024_1526,
300 SYS_COUNT_RX_1527_MAX,
302 SYS_COUNT_RX_CONTROL,
304 SYS_COUNT_RX_CLASSIFIED_DROPS,
306 SYS_COUNT_TX_UNICAST,
307 SYS_COUNT_TX_MULTICAST,
308 SYS_COUNT_TX_BROADCAST,
309 SYS_COUNT_TX_COLLISION,
314 SYS_COUNT_TX_128_511,
315 SYS_COUNT_TX_512_1023,
316 SYS_COUNT_TX_1024_1526,
317 SYS_COUNT_TX_1527_MAX,
328 SYS_REW_MAC_HIGH_CFG,
330 SYS_TIMESTAMP_OFFSET,
352 S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
359 PTP_PIN_CFG = PTP << TARGET_OFFSET,
365 PTP_CLK_CFG_ADJ_FREQ,
368 enum ocelot_regfield {
369 ANA_ADVLEARN_VLAN_CHK,
370 ANA_ADVLEARN_LEARN_MIRROR,
371 ANA_ANEVENTS_FLOOD_DISCARD,
372 ANA_ANEVENTS_MSTI_DROP,
373 ANA_ANEVENTS_ACLKILL,
374 ANA_ANEVENTS_ACLUSED,
375 ANA_ANEVENTS_AUTOAGE,
376 ANA_ANEVENTS_VS2TTL1,
377 ANA_ANEVENTS_STORM_DROP,
378 ANA_ANEVENTS_LEARN_DROP,
379 ANA_ANEVENTS_AGED_ENTRY,
380 ANA_ANEVENTS_CPU_LEARN_FAILED,
381 ANA_ANEVENTS_AUTO_LEARN_FAILED,
382 ANA_ANEVENTS_LEARN_REMOVE,
383 ANA_ANEVENTS_AUTO_LEARNED,
384 ANA_ANEVENTS_AUTO_MOVED,
385 ANA_ANEVENTS_DROPPED,
386 ANA_ANEVENTS_CLASSIFIED_DROP,
387 ANA_ANEVENTS_CLASSIFIED_COPY,
388 ANA_ANEVENTS_VLAN_DISCARD,
389 ANA_ANEVENTS_FWD_DISCARD,
390 ANA_ANEVENTS_MULTICAST_FLOOD,
391 ANA_ANEVENTS_UNICAST_FLOOD,
392 ANA_ANEVENTS_DEST_KNOWN,
393 ANA_ANEVENTS_BUCKET3_MATCH,
394 ANA_ANEVENTS_BUCKET2_MATCH,
395 ANA_ANEVENTS_BUCKET1_MATCH,
396 ANA_ANEVENTS_BUCKET0_MATCH,
397 ANA_ANEVENTS_CPU_OPERATION,
398 ANA_ANEVENTS_DMAC_LOOKUP,
399 ANA_ANEVENTS_SMAC_LOOKUP,
400 ANA_ANEVENTS_SEQ_GEN_ERR_0,
401 ANA_ANEVENTS_SEQ_GEN_ERR_1,
402 ANA_TABLES_MACACCESS_B_DOM,
403 ANA_TABLES_MACTINDX_BUCKET,
404 ANA_TABLES_MACTINDX_M_INDEX,
405 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
406 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
407 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
408 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
409 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
410 SYS_RESET_CFG_CORE_ENA,
411 SYS_RESET_CFG_MEM_ENA,
412 SYS_RESET_CFG_MEM_INIT,
416 enum ocelot_clk_pins {
423 struct ocelot_multicast {
424 struct list_head list;
425 unsigned char addr[ETH_ALEN];
432 struct ocelot_stat_layout {
434 char name[ETH_GSTRING_LEN];
440 struct regmap *targets[TARGET_MAX];
441 struct regmap_field *regfields[REGFIELD_MAX];
442 const u32 *const *map;
443 const struct ocelot_stat_layout *stats_layout;
444 unsigned int num_stats;
446 u8 base_mac[ETH_ALEN];
448 struct net_device *hw_bridge_dev;
452 struct workqueue_struct *ocelot_owq;
458 struct ocelot_port **ports;
462 /* Keep track of the vlan port masks */
463 u32 vlan_mask[VLAN_N_VID];
465 struct list_head multicast;
467 /* Workqueue to check statistics for overflow with its lock */
468 struct mutex stats_lock;
470 struct delayed_work stats_work;
471 struct workqueue_struct *stats_queue;
474 struct ptp_clock *ptp_clock;
475 struct ptp_clock_info ptp_info;
476 struct hwtstamp_config hwtstamp_config;
477 struct mutex ptp_lock; /* Protects the PTP interface state */
478 spinlock_t ptp_clock_lock; /* Protects the PTP clock */
482 struct net_device *dev;
483 struct ocelot *ocelot;
484 struct phy_device *phy;
488 /* Ingress default VLAN (pvid) */
491 /* Egress default VLAN (vid) */
498 phy_interface_t phy_mode;
501 struct ocelot_port_tc tc;
504 struct list_head skbs;
509 struct list_head head;
514 u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
515 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
516 #define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
517 #define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
518 #define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
520 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
521 #define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
522 #define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
523 #define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
524 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
526 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
528 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
529 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
530 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
531 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
533 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
534 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
536 int ocelot_regfields_init(struct ocelot *ocelot,
537 const struct reg_field *const regfields);
538 struct regmap *ocelot_io_platform_init(struct ocelot *ocelot,
539 struct platform_device *pdev,
542 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
543 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
545 int ocelot_init(struct ocelot *ocelot);
546 void ocelot_deinit(struct ocelot *ocelot);
547 int ocelot_chip_init(struct ocelot *ocelot);
548 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
550 struct phy_device *phy);
552 extern struct notifier_block ocelot_netdevice_nb;
553 extern struct notifier_block ocelot_switchdev_nb;
554 extern struct notifier_block ocelot_switchdev_blocking_nb;
556 int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
557 void ocelot_get_hwtimestamp(struct ocelot *ocelot, struct timespec64 *ts);