1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018 Intel Corporation */
7 #include <linux/types.h>
8 #include <linux/if_ether.h>
9 #include <linux/netdevice.h>
12 #include "igc_defines.h"
19 #define IGC_DEV_ID_I225_LM 0x15F2
20 #define IGC_DEV_ID_I225_V 0x15F3
21 #define IGC_DEV_ID_I225_I 0x15F8
22 #define IGC_DEV_ID_I220_V 0x15F7
23 #define IGC_DEV_ID_I225_K 0x3100
27 /* Function pointers for the MAC. */
28 struct igc_mac_operations {
29 s32 (*check_for_link)(struct igc_hw *hw);
30 s32 (*reset_hw)(struct igc_hw *hw);
31 s32 (*init_hw)(struct igc_hw *hw);
32 s32 (*setup_physical_interface)(struct igc_hw *hw);
33 void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index);
34 s32 (*read_mac_addr)(struct igc_hw *hw);
35 s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed,
37 s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask);
38 void (*release_swfw_sync)(struct igc_hw *hw, u16 mask);
44 igc_num_macs /* List is 1-based, so subtract 1 for true count. */
54 igc_media_type_unknown = 0,
55 igc_media_type_copper = 1,
67 s32 (*get_invariants)(struct igc_hw *hw);
68 struct igc_mac_operations *mac_ops;
69 const struct igc_phy_operations *phy_ops;
70 struct igc_nvm_operations *nvm_ops;
73 extern const struct igc_info igc_base_info;
76 struct igc_mac_operations ops;
79 u8 perm_addr[ETH_ALEN];
81 enum igc_mac_type type;
96 u8 forced_speed_duplex;
100 bool asf_firmware_present;
101 bool arc_subsystem_valid;
105 bool get_link_status;
108 struct igc_nvm_operations {
109 s32 (*acquire)(struct igc_hw *hw);
110 s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);
111 void (*release)(struct igc_hw *hw);
112 s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);
113 s32 (*update)(struct igc_hw *hw);
114 s32 (*validate)(struct igc_hw *hw);
115 s32 (*valid_led_default)(struct igc_hw *hw, u16 *data);
118 struct igc_phy_operations {
119 s32 (*acquire)(struct igc_hw *hw);
120 s32 (*check_reset_block)(struct igc_hw *hw);
121 s32 (*force_speed_duplex)(struct igc_hw *hw);
122 s32 (*get_phy_info)(struct igc_hw *hw);
123 s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data);
124 void (*release)(struct igc_hw *hw);
125 s32 (*reset)(struct igc_hw *hw);
126 s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data);
129 struct igc_nvm_info {
130 struct igc_nvm_operations ops;
131 enum igc_nvm_type type;
143 struct igc_phy_info {
144 struct igc_phy_operations ops;
146 enum igc_phy_type type;
150 u32 reset_delay_us; /* in usec */
153 enum igc_media_type media_type;
155 u16 autoneg_advertised;
162 bool speed_downgraded;
163 bool autoneg_wait_to_complete;
166 struct igc_bus_info {
176 igc_fc_default = 0xFF
180 u32 high_water; /* Flow control high-water mark */
181 u32 low_water; /* Flow control low-water mark */
182 u16 pause_time; /* Flow control pause timer */
183 bool send_xon; /* Flow control send XON */
184 bool strict_ieee; /* Strict IEEE mode */
185 enum igc_fc_mode current_mode; /* Type of flow control */
186 enum igc_fc_mode requested_mode;
189 struct igc_dev_spec_base {
190 bool clear_semaphore_once;
197 unsigned long io_base;
199 struct igc_mac_info mac;
200 struct igc_fc_info fc;
201 struct igc_nvm_info nvm;
202 struct igc_phy_info phy;
204 struct igc_bus_info bus;
207 struct igc_dev_spec_base _base;
211 u16 subsystem_vendor_id;
212 u16 subsystem_device_id;
218 /* Statistics counters collected by the MAC */
219 struct igc_hw_stats {
302 struct net_device *igc_get_hw_dev(struct igc_hw *hw);
303 #define hw_dbg(format, arg...) \
304 netdev_dbg(igc_get_hw_dev(hw), format, ##arg)
306 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
307 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
308 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
309 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
311 #endif /* _IGC_HW_H_ */