drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #ifndef __HCLGE_CMD_H
   5 #define __HCLGE_CMD_H
   6 #include <linux/types.h>
   7 #include <linux/io.h>
   8
   9 #define HCLGE_CMDQ_TX_TIMEOUT           30000
  10
  11 struct hclge_dev;
  12 struct hclge_desc {
  13         __le16 opcode;
  14
  15 #define HCLGE_CMDQ_RX_INVLD_B           0
  16 #define HCLGE_CMDQ_RX_OUTVLD_B          1
  17
  18         __le16 flag;
  19         __le16 retval;
  20         __le16 rsv;
  21         __le32 data[6];
  22 };
  23
  24 struct hclge_cmq_ring {
  25         dma_addr_t desc_dma_addr;
  26         struct hclge_desc *desc;
  27         struct hclge_dev *dev;
  28         u32 head;
  29         u32 tail;
  30
  31         u16 buf_size;
  32         u16 desc_num;
  33         int next_to_use;
  34         int next_to_clean;
  35         u8 ring_type; /* cmq ring type */
  36         spinlock_t lock; /* Command queue lock */
  37 };
  38
  39 enum hclge_cmd_return_status {
  40         HCLGE_CMD_EXEC_SUCCESS  = 0,
  41         HCLGE_CMD_NO_AUTH       = 1,
  42         HCLGE_CMD_NOT_SUPPORTED = 2,
  43         HCLGE_CMD_QUEUE_FULL    = 3,
  44         HCLGE_CMD_NEXT_ERR      = 4,
  45         HCLGE_CMD_UNEXE_ERR     = 5,
  46         HCLGE_CMD_PARA_ERR      = 6,
  47         HCLGE_CMD_RESULT_ERR    = 7,
  48         HCLGE_CMD_TIMEOUT       = 8,
  49         HCLGE_CMD_HILINK_ERR    = 9,
  50         HCLGE_CMD_QUEUE_ILLEGAL = 10,
  51         HCLGE_CMD_INVALID       = 11,
  52 };
  53
  54 enum hclge_cmd_status {
  55         HCLGE_STATUS_SUCCESS    = 0,
  56         HCLGE_ERR_CSQ_FULL      = -1,
  57         HCLGE_ERR_CSQ_TIMEOUT   = -2,
  58         HCLGE_ERR_CSQ_ERROR     = -3,
  59 };
  60
  61 struct hclge_misc_vector {
  62         u8 __iomem *addr;
  63         int vector_irq;
  64 };
  65
  66 struct hclge_cmq {
  67         struct hclge_cmq_ring csq;
  68         struct hclge_cmq_ring crq;
  69         u16 tx_timeout;
  70         enum hclge_cmd_status last_status;
  71 };
  72
  73 #define HCLGE_CMD_FLAG_IN       BIT(0)
  74 #define HCLGE_CMD_FLAG_OUT      BIT(1)
  75 #define HCLGE_CMD_FLAG_NEXT     BIT(2)
  76 #define HCLGE_CMD_FLAG_WR       BIT(3)
  77 #define HCLGE_CMD_FLAG_NO_INTR  BIT(4)
  78 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
  79
  80 enum hclge_opcode_type {
  81         /* Generic commands */
  82         HCLGE_OPC_QUERY_FW_VER          = 0x0001,
  83         HCLGE_OPC_CFG_RST_TRIGGER       = 0x0020,
  84         HCLGE_OPC_GBL_RST_STATUS        = 0x0021,
  85         HCLGE_OPC_QUERY_FUNC_STATUS     = 0x0022,
  86         HCLGE_OPC_QUERY_PF_RSRC         = 0x0023,
  87         HCLGE_OPC_QUERY_VF_RSRC         = 0x0024,
  88         HCLGE_OPC_GET_CFG_PARAM         = 0x0025,
  89         HCLGE_OPC_PF_RST_DONE           = 0x0026,
  90         HCLGE_OPC_QUERY_VF_RST_RDY      = 0x0027,
  91
  92         HCLGE_OPC_STATS_64_BIT          = 0x0030,
  93         HCLGE_OPC_STATS_32_BIT          = 0x0031,
  94         HCLGE_OPC_STATS_MAC             = 0x0032,
  95         HCLGE_OPC_QUERY_MAC_REG_NUM     = 0x0033,
  96         HCLGE_OPC_STATS_MAC_ALL         = 0x0034,
  97
  98         HCLGE_OPC_QUERY_REG_NUM         = 0x0040,
  99         HCLGE_OPC_QUERY_32_BIT_REG      = 0x0041,
 100         HCLGE_OPC_QUERY_64_BIT_REG      = 0x0042,
 101         HCLGE_OPC_DFX_BD_NUM            = 0x0043,
 102         HCLGE_OPC_DFX_BIOS_COMMON_REG   = 0x0044,
 103         HCLGE_OPC_DFX_SSU_REG_0         = 0x0045,
 104         HCLGE_OPC_DFX_SSU_REG_1         = 0x0046,
 105         HCLGE_OPC_DFX_IGU_EGU_REG       = 0x0047,
 106         HCLGE_OPC_DFX_RPU_REG_0         = 0x0048,
 107         HCLGE_OPC_DFX_RPU_REG_1         = 0x0049,
 108         HCLGE_OPC_DFX_NCSI_REG          = 0x004A,
 109         HCLGE_OPC_DFX_RTC_REG           = 0x004B,
 110         HCLGE_OPC_DFX_PPP_REG           = 0x004C,
 111         HCLGE_OPC_DFX_RCB_REG           = 0x004D,
 112         HCLGE_OPC_DFX_TQP_REG           = 0x004E,
 113         HCLGE_OPC_DFX_SSU_REG_2         = 0x004F,
 114         HCLGE_OPC_DFX_QUERY_CHIP_CAP    = 0x0050,
 115
 116         /* MAC command */
 117         HCLGE_OPC_CONFIG_MAC_MODE       = 0x0301,
 118         HCLGE_OPC_CONFIG_AN_MODE        = 0x0304,
 119         HCLGE_OPC_QUERY_LINK_STATUS     = 0x0307,
 120         HCLGE_OPC_CONFIG_MAX_FRM_SIZE   = 0x0308,
 121         HCLGE_OPC_CONFIG_SPEED_DUP      = 0x0309,
 122         HCLGE_OPC_QUERY_MAC_TNL_INT     = 0x0310,
 123         HCLGE_OPC_MAC_TNL_INT_EN        = 0x0311,
 124         HCLGE_OPC_CLEAR_MAC_TNL_INT     = 0x0312,
 125         HCLGE_OPC_SERDES_LOOPBACK       = 0x0315,
 126         HCLGE_OPC_CONFIG_FEC_MODE       = 0x031A,
 127
 128         /* PFC/Pause commands */
 129         HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
 130         HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
 131         HCLGE_OPC_CFG_MAC_PARA          = 0x0703,
 132         HCLGE_OPC_CFG_PFC_PARA          = 0x0704,
 133         HCLGE_OPC_QUERY_MAC_TX_PKT_CNT  = 0x0705,
 134         HCLGE_OPC_QUERY_MAC_RX_PKT_CNT  = 0x0706,
 135         HCLGE_OPC_QUERY_PFC_TX_PKT_CNT  = 0x0707,
 136         HCLGE_OPC_QUERY_PFC_RX_PKT_CNT  = 0x0708,
 137         HCLGE_OPC_PRI_TO_TC_MAPPING     = 0x0709,
 138         HCLGE_OPC_QOS_MAP               = 0x070A,
 139
 140         /* ETS/scheduler commands */
 141         HCLGE_OPC_TM_PG_TO_PRI_LINK     = 0x0804,
 142         HCLGE_OPC_TM_QS_TO_PRI_LINK     = 0x0805,
 143         HCLGE_OPC_TM_NQ_TO_QS_LINK      = 0x0806,
 144         HCLGE_OPC_TM_RQ_TO_QS_LINK      = 0x0807,
 145         HCLGE_OPC_TM_PORT_WEIGHT        = 0x0808,
 146         HCLGE_OPC_TM_PG_WEIGHT          = 0x0809,
 147         HCLGE_OPC_TM_QS_WEIGHT          = 0x080A,
 148         HCLGE_OPC_TM_PRI_WEIGHT         = 0x080B,
 149         HCLGE_OPC_TM_PRI_C_SHAPPING     = 0x080C,
 150         HCLGE_OPC_TM_PRI_P_SHAPPING     = 0x080D,
 151         HCLGE_OPC_TM_PG_C_SHAPPING      = 0x080E,
 152         HCLGE_OPC_TM_PG_P_SHAPPING      = 0x080F,
 153         HCLGE_OPC_TM_PORT_SHAPPING      = 0x0810,
 154         HCLGE_OPC_TM_PG_SCH_MODE_CFG    = 0x0812,
 155         HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
 156         HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
 157         HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
 158         HCLGE_OPC_ETS_TC_WEIGHT         = 0x0843,
 159         HCLGE_OPC_QSET_DFX_STS          = 0x0844,
 160         HCLGE_OPC_PRI_DFX_STS           = 0x0845,
 161         HCLGE_OPC_PG_DFX_STS            = 0x0846,
 162         HCLGE_OPC_PORT_DFX_STS          = 0x0847,
 163         HCLGE_OPC_SCH_NQ_CNT            = 0x0848,
 164         HCLGE_OPC_SCH_RQ_CNT            = 0x0849,
 165         HCLGE_OPC_TM_INTERNAL_STS       = 0x0850,
 166         HCLGE_OPC_TM_INTERNAL_CNT       = 0x0851,
 167         HCLGE_OPC_TM_INTERNAL_STS_1     = 0x0852,
 168
 169         /* Packet buffer allocate commands */
 170         HCLGE_OPC_TX_BUFF_ALLOC         = 0x0901,
 171         HCLGE_OPC_RX_PRIV_BUFF_ALLOC    = 0x0902,
 172         HCLGE_OPC_RX_PRIV_WL_ALLOC      = 0x0903,
 173         HCLGE_OPC_RX_COM_THRD_ALLOC     = 0x0904,
 174         HCLGE_OPC_RX_COM_WL_ALLOC       = 0x0905,
 175         HCLGE_OPC_RX_GBL_PKT_CNT        = 0x0906,
 176
 177         /* TQP management command */
 178         HCLGE_OPC_SET_TQP_MAP           = 0x0A01,
 179
 180         /* TQP commands */
 181         HCLGE_OPC_CFG_TX_QUEUE          = 0x0B01,
 182         HCLGE_OPC_QUERY_TX_POINTER      = 0x0B02,
 183         HCLGE_OPC_QUERY_TX_STATUS       = 0x0B03,
 184         HCLGE_OPC_TQP_TX_QUEUE_TC       = 0x0B04,
 185         HCLGE_OPC_CFG_RX_QUEUE          = 0x0B11,
 186         HCLGE_OPC_QUERY_RX_POINTER      = 0x0B12,
 187         HCLGE_OPC_QUERY_RX_STATUS       = 0x0B13,
 188         HCLGE_OPC_STASH_RX_QUEUE_LRO    = 0x0B16,
 189         HCLGE_OPC_CFG_RX_QUEUE_LRO      = 0x0B17,
 190         HCLGE_OPC_CFG_COM_TQP_QUEUE     = 0x0B20,
 191         HCLGE_OPC_RESET_TQP_QUEUE       = 0x0B22,
 192
 193         /* PPU commands */
 194         HCLGE_OPC_PPU_PF_OTHER_INT_DFX  = 0x0B4A,
 195
 196         /* TSO command */
 197         HCLGE_OPC_TSO_GENERIC_CONFIG    = 0x0C01,
 198         HCLGE_OPC_GRO_GENERIC_CONFIG    = 0x0C10,
 199
 200         /* RSS commands */
 201         HCLGE_OPC_RSS_GENERIC_CONFIG    = 0x0D01,
 202         HCLGE_OPC_RSS_INDIR_TABLE       = 0x0D07,
 203         HCLGE_OPC_RSS_TC_MODE           = 0x0D08,
 204         HCLGE_OPC_RSS_INPUT_TUPLE       = 0x0D02,
 205
 206         /* Promisuous mode command */
 207         HCLGE_OPC_CFG_PROMISC_MODE      = 0x0E01,
 208
 209         /* Vlan offload commands */
 210         HCLGE_OPC_VLAN_PORT_TX_CFG      = 0x0F01,
 211         HCLGE_OPC_VLAN_PORT_RX_CFG      = 0x0F02,
 212
 213         /* Interrupts commands */
 214         HCLGE_OPC_ADD_RING_TO_VECTOR    = 0x1503,
 215         HCLGE_OPC_DEL_RING_TO_VECTOR    = 0x1504,
 216
 217         /* MAC commands */
 218         HCLGE_OPC_MAC_VLAN_ADD              = 0x1000,
 219         HCLGE_OPC_MAC_VLAN_REMOVE           = 0x1001,
 220         HCLGE_OPC_MAC_VLAN_TYPE_ID          = 0x1002,
 221         HCLGE_OPC_MAC_VLAN_INSERT           = 0x1003,
 222         HCLGE_OPC_MAC_VLAN_ALLOCATE         = 0x1004,
 223         HCLGE_OPC_MAC_ETHTYPE_ADD           = 0x1010,
 224         HCLGE_OPC_MAC_ETHTYPE_REMOVE    = 0x1011,
 225
 226         /* MAC VLAN commands */
 227         HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
 228
 229         /* VLAN commands */
 230         HCLGE_OPC_VLAN_FILTER_CTRL          = 0x1100,
 231         HCLGE_OPC_VLAN_FILTER_PF_CFG    = 0x1101,
 232         HCLGE_OPC_VLAN_FILTER_VF_CFG    = 0x1102,
 233
 234         /* Flow Director commands */
 235         HCLGE_OPC_FD_MODE_CTRL          = 0x1200,
 236         HCLGE_OPC_FD_GET_ALLOCATION     = 0x1201,
 237         HCLGE_OPC_FD_KEY_CONFIG         = 0x1202,
 238         HCLGE_OPC_FD_TCAM_OP            = 0x1203,
 239         HCLGE_OPC_FD_AD_OP              = 0x1204,
 240
 241         /* MDIO command */
 242         HCLGE_OPC_MDIO_CONFIG           = 0x1900,
 243
 244         /* QCN commands */
 245         HCLGE_OPC_QCN_MOD_CFG           = 0x1A01,
 246         HCLGE_OPC_QCN_GRP_TMPLT_CFG     = 0x1A02,
 247         HCLGE_OPC_QCN_SHAPPING_IR_CFG   = 0x1A03,
 248         HCLGE_OPC_QCN_SHAPPING_BS_CFG   = 0x1A04,
 249         HCLGE_OPC_QCN_QSET_LINK_CFG     = 0x1A05,
 250         HCLGE_OPC_QCN_RP_STATUS_GET     = 0x1A06,
 251         HCLGE_OPC_QCN_AJUST_INIT        = 0x1A07,
 252         HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,
 253
 254         /* Mailbox command */
 255         HCLGEVF_OPC_MBX_PF_TO_VF        = 0x2000,
 256
 257         /* Led command */
 258         HCLGE_OPC_LED_STATUS_CFG        = 0xB000,
 259
 260         /* NCL config command */
 261         HCLGE_OPC_QUERY_NCL_CONFIG      = 0x7011,
 262         /* M7 stats command */
 263         HCLGE_OPC_M7_STATS_BD           = 0x7012,
 264         HCLGE_OPC_M7_STATS_INFO         = 0x7013,
 265         HCLGE_OPC_M7_COMPAT_CFG         = 0x701A,
 266
 267         /* SFP command */
 268         HCLGE_OPC_GET_SFP_INFO          = 0x7104,
 269
 270         /* Error INT commands */
 271         HCLGE_MAC_COMMON_INT_EN         = 0x030E,
 272         HCLGE_TM_SCH_ECC_INT_EN         = 0x0829,
 273         HCLGE_SSU_ECC_INT_CMD           = 0x0989,
 274         HCLGE_SSU_COMMON_INT_CMD        = 0x098C,
 275         HCLGE_PPU_MPF_ECC_INT_CMD       = 0x0B40,
 276         HCLGE_PPU_MPF_OTHER_INT_CMD     = 0x0B41,
 277         HCLGE_PPU_PF_OTHER_INT_CMD      = 0x0B42,
 278         HCLGE_COMMON_ECC_INT_CFG        = 0x1505,
 279         HCLGE_QUERY_RAS_INT_STS_BD_NUM  = 0x1510,
 280         HCLGE_QUERY_CLEAR_MPF_RAS_INT   = 0x1511,
 281         HCLGE_QUERY_CLEAR_PF_RAS_INT    = 0x1512,
 282         HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
 283         HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT      = 0x1514,
 284         HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT       = 0x1515,
 285         HCLGE_CONFIG_ROCEE_RAS_INT_EN   = 0x1580,
 286         HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
 287         HCLGE_ROCEE_PF_RAS_INT_CMD      = 0x1584,
 288         HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD      = 0x1585,
 289         HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD      = 0x1586,
 290         HCLGE_IGU_EGU_TNL_INT_EN        = 0x1803,
 291         HCLGE_IGU_COMMON_INT_EN         = 0x1806,
 292         HCLGE_TM_QCN_MEM_INT_CFG        = 0x1A14,
 293         HCLGE_PPP_CMD0_INT_CMD          = 0x2100,
 294         HCLGE_PPP_CMD1_INT_CMD          = 0x2101,
 295         HCLGE_MAC_ETHERTYPE_IDX_RD      = 0x2105,
 296         HCLGE_NCSI_INT_EN               = 0x2401,
 297 };
 298
 299 #define HCLGE_TQP_REG_OFFSET            0x80000
 300 #define HCLGE_TQP_REG_SIZE              0x200
 301
 302 #define HCLGE_RCB_INIT_QUERY_TIMEOUT    10
 303 #define HCLGE_RCB_INIT_FLAG_EN_B        0
 304 #define HCLGE_RCB_INIT_FLAG_FINI_B      8
 305 struct hclge_config_rcb_init_cmd {
 306         __le16 rcb_init_flag;
 307         u8 rsv[22];
 308 };
 309
 310 struct hclge_tqp_map_cmd {
 311         __le16 tqp_id;  /* Absolute tqp id for in this pf */
 312         u8 tqp_vf;      /* VF id */
 313 #define HCLGE_TQP_MAP_TYPE_PF           0
 314 #define HCLGE_TQP_MAP_TYPE_VF           1
 315 #define HCLGE_TQP_MAP_TYPE_B            0
 316 #define HCLGE_TQP_MAP_EN_B              1
 317         u8 tqp_flag;    /* Indicate it's pf or vf tqp */
 318         __le16 tqp_vid; /* Virtual id in this pf/vf */
 319         u8 rsv[18];
 320 };
 321
 322 #define HCLGE_VECTOR_ELEMENTS_PER_CMD   10
 323
 324 enum hclge_int_type {
 325         HCLGE_INT_TX,
 326         HCLGE_INT_RX,
 327         HCLGE_INT_EVENT,
 328 };
 329
 330 struct hclge_ctrl_vector_chain_cmd {
 331         u8 int_vector_id;
 332         u8 int_cause_num;
 333 #define HCLGE_INT_TYPE_S        0
 334 #define HCLGE_INT_TYPE_M        GENMASK(1, 0)
 335 #define HCLGE_TQP_ID_S          2
 336 #define HCLGE_TQP_ID_M          GENMASK(12, 2)
 337 #define HCLGE_INT_GL_IDX_S      13
 338 #define HCLGE_INT_GL_IDX_M      GENMASK(14, 13)
 339         __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
 340         u8 vfid;
 341         u8 rsv;
 342 };
 343
 344 #define HCLGE_MAX_TC_NUM                8
 345 #define HCLGE_TC0_PRI_BUF_EN_B  15 /* Bit 15 indicate enable or not */
 346 #define HCLGE_BUF_UNIT_S        7  /* Buf size is united by 128 bytes */
 347 struct hclge_tx_buff_alloc_cmd {
 348         __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
 349         u8 tx_buff_rsv[8];
 350 };
 351
 352 struct hclge_rx_priv_buff_cmd {
 353         __le16 buf_num[HCLGE_MAX_TC_NUM];
 354         __le16 shared_buf;
 355         u8 rsv[6];
 356 };
 357
 358 struct hclge_query_version_cmd {
 359         __le32 firmware;
 360         __le32 firmware_rsv[5];
 361 };
 362
 363 #define HCLGE_RX_PRIV_EN_B      15
 364 #define HCLGE_TC_NUM_ONE_DESC   4
 365 struct hclge_priv_wl {
 366         __le16 high;
 367         __le16 low;
 368 };
 369
 370 struct hclge_rx_priv_wl_buf {
 371         struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
 372 };
 373
 374 struct hclge_rx_com_thrd {
 375         struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
 376 };
 377
 378 struct hclge_rx_com_wl {
 379         struct hclge_priv_wl com_wl;
 380 };
 381
 382 struct hclge_waterline {
 383         u32 low;
 384         u32 high;
 385 };
 386
 387 struct hclge_tc_thrd {
 388         u32 low;
 389         u32 high;
 390 };
 391
 392 struct hclge_priv_buf {
 393         struct hclge_waterline wl;      /* Waterline for low and high*/
 394         u32 buf_size;   /* TC private buffer size */
 395         u32 tx_buf_size;
 396         u32 enable;     /* Enable TC private buffer or not */
 397 };
 398
 399 struct hclge_shared_buf {
 400         struct hclge_waterline self;
 401         struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
 402         u32 buf_size;
 403 };
 404
 405 struct hclge_pkt_buf_alloc {
 406         struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
 407         struct hclge_shared_buf s_buf;
 408 };
 409
 410 #define HCLGE_RX_COM_WL_EN_B    15
 411 struct hclge_rx_com_wl_buf_cmd {
 412         __le16 high_wl;
 413         __le16 low_wl;
 414         u8 rsv[20];
 415 };
 416
 417 #define HCLGE_RX_PKT_EN_B       15
 418 struct hclge_rx_pkt_buf_cmd {
 419         __le16 high_pkt;
 420         __le16 low_pkt;
 421         u8 rsv[20];
 422 };
 423
 424 #define HCLGE_PF_STATE_DONE_B   0
 425 #define HCLGE_PF_STATE_MAIN_B   1
 426 #define HCLGE_PF_STATE_BOND_B   2
 427 #define HCLGE_PF_STATE_MAC_N_B  6
 428 #define HCLGE_PF_MAC_NUM_MASK   0x3
 429 #define HCLGE_PF_STATE_MAIN     BIT(HCLGE_PF_STATE_MAIN_B)
 430 #define HCLGE_PF_STATE_DONE     BIT(HCLGE_PF_STATE_DONE_B)
 431 struct hclge_func_status_cmd {
 432         __le32  vf_rst_state[4];
 433         u8 pf_state;
 434         u8 mac_id;
 435         u8 rsv1;
 436         u8 pf_cnt_in_mac;
 437         u8 pf_num;
 438         u8 vf_num;
 439         u8 rsv[2];
 440 };
 441
 442 struct hclge_pf_res_cmd {
 443         __le16 tqp_num;
 444         __le16 buf_size;
 445         __le16 msixcap_localid_ba_nic;
 446         __le16 msixcap_localid_ba_rocee;
 447 #define HCLGE_MSIX_OFT_ROCEE_S          0
 448 #define HCLGE_MSIX_OFT_ROCEE_M          GENMASK(15, 0)
 449 #define HCLGE_PF_VEC_NUM_S              0
 450 #define HCLGE_PF_VEC_NUM_M              GENMASK(7, 0)
 451         __le16 pf_intr_vector_number;
 452         __le16 pf_own_fun_number;
 453         __le16 tx_buf_size;
 454         __le16 dv_buf_size;
 455         __le32 rsv[2];
 456 };
 457
 458 #define HCLGE_CFG_OFFSET_S      0
 459 #define HCLGE_CFG_OFFSET_M      GENMASK(19, 0)
 460 #define HCLGE_CFG_RD_LEN_S      24
 461 #define HCLGE_CFG_RD_LEN_M      GENMASK(27, 24)
 462 #define HCLGE_CFG_RD_LEN_BYTES  16
 463 #define HCLGE_CFG_RD_LEN_UNIT   4
 464
 465 #define HCLGE_CFG_VMDQ_S        0
 466 #define HCLGE_CFG_VMDQ_M        GENMASK(7, 0)
 467 #define HCLGE_CFG_TC_NUM_S      8
 468 #define HCLGE_CFG_TC_NUM_M      GENMASK(15, 8)
 469 #define HCLGE_CFG_TQP_DESC_N_S  16
 470 #define HCLGE_CFG_TQP_DESC_N_M  GENMASK(31, 16)
 471 #define HCLGE_CFG_PHY_ADDR_S    0
 472 #define HCLGE_CFG_PHY_ADDR_M    GENMASK(7, 0)
 473 #define HCLGE_CFG_MEDIA_TP_S    8
 474 #define HCLGE_CFG_MEDIA_TP_M    GENMASK(15, 8)
 475 #define HCLGE_CFG_RX_BUF_LEN_S  16
 476 #define HCLGE_CFG_RX_BUF_LEN_M  GENMASK(31, 16)
 477 #define HCLGE_CFG_MAC_ADDR_H_S  0
 478 #define HCLGE_CFG_MAC_ADDR_H_M  GENMASK(15, 0)
 479 #define HCLGE_CFG_DEFAULT_SPEED_S       16
 480 #define HCLGE_CFG_DEFAULT_SPEED_M       GENMASK(23, 16)
 481 #define HCLGE_CFG_RSS_SIZE_S    24
 482 #define HCLGE_CFG_RSS_SIZE_M    GENMASK(31, 24)
 483 #define HCLGE_CFG_SPEED_ABILITY_S       0
 484 #define HCLGE_CFG_SPEED_ABILITY_M       GENMASK(7, 0)
 485 #define HCLGE_CFG_UMV_TBL_SPACE_S       16
 486 #define HCLGE_CFG_UMV_TBL_SPACE_M       GENMASK(31, 16)
 487
 488 struct hclge_cfg_param_cmd {
 489         __le32 offset;
 490         __le32 rsv;
 491         __le32 param[4];
 492 };
 493
 494 #define HCLGE_MAC_MODE          0x0
 495 #define HCLGE_DESC_NUM          0x40
 496
 497 #define HCLGE_ALLOC_VALID_B     0
 498 struct hclge_vf_num_cmd {
 499         u8 alloc_valid;
 500         u8 rsv[23];
 501 };
 502
 503 #define HCLGE_RSS_DEFAULT_OUTPORT_B     4
 504 #define HCLGE_RSS_HASH_KEY_OFFSET_B     4
 505 #define HCLGE_RSS_HASH_KEY_NUM          16
 506 struct hclge_rss_config_cmd {
 507         u8 hash_config;
 508         u8 rsv[7];
 509         u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
 510 };
 511
 512 struct hclge_rss_input_tuple_cmd {
 513         u8 ipv4_tcp_en;
 514         u8 ipv4_udp_en;
 515         u8 ipv4_sctp_en;
 516         u8 ipv4_fragment_en;
 517         u8 ipv6_tcp_en;
 518         u8 ipv6_udp_en;
 519         u8 ipv6_sctp_en;
 520         u8 ipv6_fragment_en;
 521         u8 rsv[16];
 522 };
 523
 524 #define HCLGE_RSS_CFG_TBL_SIZE  16
 525
 526 struct hclge_rss_indirection_table_cmd {
 527         __le16 start_table_index;
 528         __le16 rss_set_bitmap;
 529         u8 rsv[4];
 530         u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE];
 531 };
 532
 533 #define HCLGE_RSS_TC_OFFSET_S           0
 534 #define HCLGE_RSS_TC_OFFSET_M           GENMASK(9, 0)
 535 #define HCLGE_RSS_TC_SIZE_S             12
 536 #define HCLGE_RSS_TC_SIZE_M             GENMASK(14, 12)
 537 #define HCLGE_RSS_TC_VALID_B            15
 538 struct hclge_rss_tc_mode_cmd {
 539         __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
 540         u8 rsv[8];
 541 };
 542
 543 #define HCLGE_LINK_STATUS_UP_B  0
 544 #define HCLGE_LINK_STATUS_UP_M  BIT(HCLGE_LINK_STATUS_UP_B)
 545 struct hclge_link_status_cmd {
 546         u8 status;
 547         u8 rsv[23];
 548 };
 549
 550 struct hclge_promisc_param {
 551         u8 vf_id;
 552         u8 enable;
 553 };
 554
 555 #define HCLGE_PROMISC_TX_EN_B   BIT(4)
 556 #define HCLGE_PROMISC_RX_EN_B   BIT(5)
 557 #define HCLGE_PROMISC_EN_B      1
 558 #define HCLGE_PROMISC_EN_ALL    0x7
 559 #define HCLGE_PROMISC_EN_UC     0x1
 560 #define HCLGE_PROMISC_EN_MC     0x2
 561 #define HCLGE_PROMISC_EN_BC     0x4
 562 struct hclge_promisc_cfg_cmd {
 563         u8 flag;
 564         u8 vf_id;
 565         __le16 rsv0;
 566         u8 rsv1[20];
 567 };
 568
 569 enum hclge_promisc_type {
 570         HCLGE_UNICAST   = 1,
 571         HCLGE_MULTICAST = 2,
 572         HCLGE_BROADCAST = 3,
 573 };
 574
 575 #define HCLGE_MAC_TX_EN_B       6
 576 #define HCLGE_MAC_RX_EN_B       7
 577 #define HCLGE_MAC_PAD_TX_B      11
 578 #define HCLGE_MAC_PAD_RX_B      12
 579 #define HCLGE_MAC_1588_TX_B     13
 580 #define HCLGE_MAC_1588_RX_B     14
 581 #define HCLGE_MAC_APP_LP_B      15
 582 #define HCLGE_MAC_LINE_LP_B     16
 583 #define HCLGE_MAC_FCS_TX_B      17
 584 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B        18
 585 #define HCLGE_MAC_RX_FCS_STRIP_B        19
 586 #define HCLGE_MAC_RX_FCS_B      20
 587 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B            21
 588 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B        22
 589
 590 struct hclge_config_mac_mode_cmd {
 591         __le32 txrx_pad_fcs_loop_en;
 592         u8 rsv[20];
 593 };
 594
 595 struct hclge_pf_rst_sync_cmd {
 596 #define HCLGE_PF_RST_ALL_VF_RDY_B       0
 597         u8 all_vf_ready;
 598         u8 rsv[23];
 599 };
 600
 601 #define HCLGE_CFG_SPEED_S               0
 602 #define HCLGE_CFG_SPEED_M               GENMASK(5, 0)
 603
 604 #define HCLGE_CFG_DUPLEX_B              7
 605 #define HCLGE_CFG_DUPLEX_M              BIT(HCLGE_CFG_DUPLEX_B)
 606
 607 struct hclge_config_mac_speed_dup_cmd {
 608         u8 speed_dup;
 609
 610 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
 611         u8 mac_change_fec_en;
 612         u8 rsv[22];
 613 };
 614
 615 #define HCLGE_RING_ID_MASK              GENMASK(9, 0)
 616 #define HCLGE_TQP_ENABLE_B              0
 617
 618 #define HCLGE_MAC_CFG_AN_EN_B           0
 619 #define HCLGE_MAC_CFG_AN_INT_EN_B       1
 620 #define HCLGE_MAC_CFG_AN_INT_MSK_B      2
 621 #define HCLGE_MAC_CFG_AN_INT_CLR_B      3
 622 #define HCLGE_MAC_CFG_AN_RST_B          4
 623
 624 #define HCLGE_MAC_CFG_AN_EN     BIT(HCLGE_MAC_CFG_AN_EN_B)
 625
 626 struct hclge_config_auto_neg_cmd {
 627         __le32  cfg_an_cmd_flag;
 628         u8      rsv[20];
 629 };
 630
 631 struct hclge_sfp_info_cmd {
 632         __le32 speed;
 633         u8 query_type; /* 0: sfp speed, 1: active speed */
 634         u8 active_fec;
 635         u8 autoneg; /* autoneg state */
 636         u8 autoneg_ability; /* whether support autoneg */
 637         __le32 speed_ability; /* speed ability for current media */
 638         __le32 module_type;
 639         u8 rsv[8];
 640 };
 641
 642 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B     0
 643 #define HCLGE_MAC_CFG_FEC_MODE_S        1
 644 #define HCLGE_MAC_CFG_FEC_MODE_M        GENMASK(3, 1)
 645 #define HCLGE_MAC_CFG_FEC_SET_DEF_B     0
 646 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B     1
 647
 648 #define HCLGE_MAC_FEC_OFF               0
 649 #define HCLGE_MAC_FEC_BASER             1
 650 #define HCLGE_MAC_FEC_RS                2
 651 struct hclge_config_fec_cmd {
 652         u8 fec_mode;
 653         u8 default_config;
 654         u8 rsv[22];
 655 };
 656
 657 #define HCLGE_MAC_UPLINK_PORT           0x100
 658
 659 struct hclge_config_max_frm_size_cmd {
 660         __le16  max_frm_size;
 661         u8      min_frm_size;
 662         u8      rsv[21];
 663 };
 664
 665 enum hclge_mac_vlan_tbl_opcode {
 666         HCLGE_MAC_VLAN_ADD,     /* Add new or modify mac_vlan */
 667         HCLGE_MAC_VLAN_UPDATE,  /* Modify other fields of this table */
 668         HCLGE_MAC_VLAN_REMOVE,  /* Remove a entry through mac_vlan key */
 669         HCLGE_MAC_VLAN_LKUP,    /* Lookup a entry through mac_vlan key */
 670 };
 671
 672 enum hclge_mac_vlan_add_resp_code {
 673         HCLGE_ADD_UC_OVERFLOW = 2,      /* ADD failed for UC overflow */
 674         HCLGE_ADD_MC_OVERFLOW,          /* ADD failed for MC overflow */
 675 };
 676
 677 #define HCLGE_MAC_VLAN_BIT0_EN_B        0
 678 #define HCLGE_MAC_VLAN_BIT1_EN_B        1
 679 #define HCLGE_MAC_EPORT_SW_EN_B         12
 680 #define HCLGE_MAC_EPORT_TYPE_B          11
 681 #define HCLGE_MAC_EPORT_VFID_S          3
 682 #define HCLGE_MAC_EPORT_VFID_M          GENMASK(10, 3)
 683 #define HCLGE_MAC_EPORT_PFID_S          0
 684 #define HCLGE_MAC_EPORT_PFID_M          GENMASK(2, 0)
 685 struct hclge_mac_vlan_tbl_entry_cmd {
 686         u8      flags;
 687         u8      resp_code;
 688         __le16  vlan_tag;
 689         __le32  mac_addr_hi32;
 690         __le16  mac_addr_lo16;
 691         __le16  rsv1;
 692         u8      entry_type;
 693         u8      mc_mac_en;
 694         __le16  egress_port;
 695         __le16  egress_queue;
 696         u8      rsv2[6];
 697 };
 698
 699 #define HCLGE_UMV_SPC_ALC_B     0
 700 struct hclge_umv_spc_alc_cmd {
 701         u8 allocate;
 702         u8 rsv1[3];
 703         __le32 space_size;
 704         u8 rsv2[16];
 705 };
 706
 707 #define HCLGE_MAC_MGR_MASK_VLAN_B               BIT(0)
 708 #define HCLGE_MAC_MGR_MASK_MAC_B                BIT(1)
 709 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B          BIT(2)
 710
 711 struct hclge_mac_mgr_tbl_entry_cmd {
 712         u8      flags;
 713         u8      resp_code;
 714         __le16  vlan_tag;
 715         __le32  mac_addr_hi32;
 716         __le16  mac_addr_lo16;
 717         __le16  rsv1;
 718         __le16  ethter_type;
 719         __le16  egress_port;
 720         __le16  egress_queue;
 721         u8      sw_port_id_aware;
 722         u8      rsv2;
 723         u8      i_port_bitmap;
 724         u8      i_port_direction;
 725         u8      rsv3[2];
 726 };
 727
 728 struct hclge_mac_vlan_add_cmd {
 729         __le16  flags;
 730         __le16  mac_addr_hi16;
 731         __le32  mac_addr_lo32;
 732         __le32  mac_addr_msk_hi32;
 733         __le16  mac_addr_msk_lo16;
 734         __le16  vlan_tag;
 735         __le16  ingress_port;
 736         __le16  egress_port;
 737         u8      rsv[4];
 738 };
 739
 740 #define HNS3_MAC_VLAN_CFG_FLAG_BIT 0
 741 struct hclge_mac_vlan_remove_cmd {
 742         __le16  flags;
 743         __le16  mac_addr_hi16;
 744         __le32  mac_addr_lo32;
 745         __le32  mac_addr_msk_hi32;
 746         __le16  mac_addr_msk_lo16;
 747         __le16  vlan_tag;
 748         __le16  ingress_port;
 749         __le16  egress_port;
 750         u8      rsv[4];
 751 };
 752
 753 struct hclge_vlan_filter_ctrl_cmd {
 754         u8 vlan_type;
 755         u8 vlan_fe;
 756         u8 rsv1[2];
 757         u8 vf_id;
 758         u8 rsv2[19];
 759 };
 760
 761 struct hclge_vlan_filter_pf_cfg_cmd {
 762         u8 vlan_offset;
 763         u8 vlan_cfg;
 764         u8 rsv[2];
 765         u8 vlan_offset_bitmap[20];
 766 };
 767
 768 struct hclge_vlan_filter_vf_cfg_cmd {
 769         __le16 vlan_id;
 770         u8  resp_code;
 771         u8  rsv;
 772         u8  vlan_cfg;
 773         u8  rsv1[3];
 774         u8  vf_bitmap[16];
 775 };
 776
 777 #define HCLGE_SWITCH_ANTI_SPOOF_B       0U
 778 #define HCLGE_SWITCH_ALW_LPBK_B         1U
 779 #define HCLGE_SWITCH_ALW_LCL_LPBK_B     2U
 780 #define HCLGE_SWITCH_ALW_DST_OVRD_B     3U
 781 #define HCLGE_SWITCH_NO_MASK            0x0
 782 #define HCLGE_SWITCH_ANTI_SPOOF_MASK    0xFE
 783 #define HCLGE_SWITCH_ALW_LPBK_MASK      0xFD
 784 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK  0xFB
 785 #define HCLGE_SWITCH_LW_DST_OVRD_MASK   0xF7
 786
 787 struct hclge_mac_vlan_switch_cmd {
 788         u8 roce_sel;
 789         u8 rsv1[3];
 790         __le32 func_id;
 791         u8 switch_param;
 792         u8 rsv2[3];
 793         u8 param_mask;
 794         u8 rsv3[11];
 795 };
 796
 797 enum hclge_mac_vlan_cfg_sel {
 798         HCLGE_MAC_VLAN_NIC_SEL = 0,
 799         HCLGE_MAC_VLAN_ROCE_SEL,
 800 };
 801
 802 #define HCLGE_ACCEPT_TAG1_B             0
 803 #define HCLGE_ACCEPT_UNTAG1_B           1
 804 #define HCLGE_PORT_INS_TAG1_EN_B        2
 805 #define HCLGE_PORT_INS_TAG2_EN_B        3
 806 #define HCLGE_CFG_NIC_ROCE_SEL_B        4
 807 #define HCLGE_ACCEPT_TAG2_B             5
 808 #define HCLGE_ACCEPT_UNTAG2_B           6
 809
 810 struct hclge_vport_vtag_tx_cfg_cmd {
 811         u8 vport_vlan_cfg;
 812         u8 vf_offset;
 813         u8 rsv1[2];
 814         __le16 def_vlan_tag1;
 815         __le16 def_vlan_tag2;
 816         u8 vf_bitmap[8];
 817         u8 rsv2[8];
 818 };
 819
 820 #define HCLGE_REM_TAG1_EN_B             0
 821 #define HCLGE_REM_TAG2_EN_B             1
 822 #define HCLGE_SHOW_TAG1_EN_B            2
 823 #define HCLGE_SHOW_TAG2_EN_B            3
 824 struct hclge_vport_vtag_rx_cfg_cmd {
 825         u8 vport_vlan_cfg;
 826         u8 vf_offset;
 827         u8 rsv1[6];
 828         u8 vf_bitmap[8];
 829         u8 rsv2[8];
 830 };
 831
 832 struct hclge_tx_vlan_type_cfg_cmd {
 833         __le16 ot_vlan_type;
 834         __le16 in_vlan_type;
 835         u8 rsv[20];
 836 };
 837
 838 struct hclge_rx_vlan_type_cfg_cmd {
 839         __le16 ot_fst_vlan_type;
 840         __le16 ot_sec_vlan_type;
 841         __le16 in_fst_vlan_type;
 842         __le16 in_sec_vlan_type;
 843         u8 rsv[16];
 844 };
 845
 846 struct hclge_cfg_com_tqp_queue_cmd {
 847         __le16 tqp_id;
 848         __le16 stream_id;
 849         u8 enable;
 850         u8 rsv[19];
 851 };
 852
 853 struct hclge_cfg_tx_queue_pointer_cmd {
 854         __le16 tqp_id;
 855         __le16 tx_tail;
 856         __le16 tx_head;
 857         __le16 fbd_num;
 858         __le16 ring_offset;
 859         u8 rsv[14];
 860 };
 861
 862 #pragma pack(1)
 863 struct hclge_mac_ethertype_idx_rd_cmd {
 864         u8      flags;
 865         u8      resp_code;
 866         __le16  vlan_tag;
 867         u8      mac_addr[6];
 868         __le16  index;
 869         __le16  ethter_type;
 870         __le16  egress_port;
 871         __le16  egress_queue;
 872         __le16  rev0;
 873         u8      i_port_bitmap;
 874         u8      i_port_direction;
 875         u8      rev1[2];
 876 };
 877
 878 #pragma pack()
 879
 880 #define HCLGE_TSO_MSS_MIN_S     0
 881 #define HCLGE_TSO_MSS_MIN_M     GENMASK(13, 0)
 882
 883 #define HCLGE_TSO_MSS_MAX_S     16
 884 #define HCLGE_TSO_MSS_MAX_M     GENMASK(29, 16)
 885
 886 struct hclge_cfg_tso_status_cmd {
 887         __le16 tso_mss_min;
 888         __le16 tso_mss_max;
 889         u8 rsv[20];
 890 };
 891
 892 #define HCLGE_GRO_EN_B          0
 893 struct hclge_cfg_gro_status_cmd {
 894         __le16 gro_en;
 895         u8 rsv[22];
 896 };
 897
 898 #define HCLGE_TSO_MSS_MIN       256
 899 #define HCLGE_TSO_MSS_MAX       9668
 900
 901 #define HCLGE_TQP_RESET_B       0
 902 struct hclge_reset_tqp_queue_cmd {
 903         __le16 tqp_id;
 904         u8 reset_req;
 905         u8 ready_to_reset;
 906         u8 rsv[20];
 907 };
 908
 909 #define HCLGE_CFG_RESET_MAC_B           3
 910 #define HCLGE_CFG_RESET_FUNC_B          7
 911 struct hclge_reset_cmd {
 912         u8 mac_func_reset;
 913         u8 fun_reset_vfid;
 914         u8 rsv[22];
 915 };
 916
 917 #define HCLGE_PF_RESET_DONE_BIT         BIT(0)
 918
 919 struct hclge_pf_rst_done_cmd {
 920         u8 pf_rst_done;
 921         u8 rsv[23];
 922 };
 923
 924 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B    BIT(0)
 925 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B  BIT(2)
 926 #define HCLGE_CMD_SERDES_DONE_B                 BIT(0)
 927 #define HCLGE_CMD_SERDES_SUCCESS_B              BIT(1)
 928 struct hclge_serdes_lb_cmd {
 929         u8 mask;
 930         u8 enable;
 931         u8 result;
 932         u8 rsv[21];
 933 };
 934
 935 #define HCLGE_DEFAULT_TX_BUF            0x4000   /* 16k  bytes */
 936 #define HCLGE_TOTAL_PKT_BUF             0x108000 /* 1.03125M bytes */
 937 #define HCLGE_DEFAULT_DV                0xA000   /* 40k byte */
 938 #define HCLGE_DEFAULT_NON_DCB_DV        0x7800  /* 30K byte */
 939 #define HCLGE_NON_DCB_ADDITIONAL_BUF    0x1400  /* 5120 byte */
 940
 941 #define HCLGE_TYPE_CRQ                  0
 942 #define HCLGE_TYPE_CSQ                  1
 943 #define HCLGE_NIC_CSQ_BASEADDR_L_REG    0x27000
 944 #define HCLGE_NIC_CSQ_BASEADDR_H_REG    0x27004
 945 #define HCLGE_NIC_CSQ_DEPTH_REG         0x27008
 946 #define HCLGE_NIC_CSQ_TAIL_REG          0x27010
 947 #define HCLGE_NIC_CSQ_HEAD_REG          0x27014
 948 #define HCLGE_NIC_CRQ_BASEADDR_L_REG    0x27018
 949 #define HCLGE_NIC_CRQ_BASEADDR_H_REG    0x2701c
 950 #define HCLGE_NIC_CRQ_DEPTH_REG         0x27020
 951 #define HCLGE_NIC_CRQ_TAIL_REG          0x27024
 952 #define HCLGE_NIC_CRQ_HEAD_REG          0x27028
 953
 954 /* this bit indicates that the driver is ready for hardware reset */
 955 #define HCLGE_NIC_SW_RST_RDY_B          16
 956 #define HCLGE_NIC_SW_RST_RDY            BIT(HCLGE_NIC_SW_RST_RDY_B)
 957
 958 #define HCLGE_NIC_CMQ_DESC_NUM          1024
 959 #define HCLGE_NIC_CMQ_DESC_NUM_S        3
 960
 961 #define HCLGE_LED_LOCATE_STATE_S        0
 962 #define HCLGE_LED_LOCATE_STATE_M        GENMASK(1, 0)
 963
 964 struct hclge_set_led_state_cmd {
 965         u8 rsv1[3];
 966         u8 locate_led_config;
 967         u8 rsv2[20];
 968 };
 969
 970 struct hclge_get_fd_mode_cmd {
 971         u8 mode;
 972         u8 enable;
 973         u8 rsv[22];
 974 };
 975
 976 struct hclge_get_fd_allocation_cmd {
 977         __le32 stage1_entry_num;
 978         __le32 stage2_entry_num;
 979         __le16 stage1_counter_num;
 980         __le16 stage2_counter_num;
 981         u8 rsv[12];
 982 };
 983
 984 struct hclge_set_fd_key_config_cmd {
 985         u8 stage;
 986         u8 key_select;
 987         u8 inner_sipv6_word_en;
 988         u8 inner_dipv6_word_en;
 989         u8 outer_sipv6_word_en;
 990         u8 outer_dipv6_word_en;
 991         u8 rsv1[2];
 992         __le32 tuple_mask;
 993         __le32 meta_data_mask;
 994         u8 rsv2[8];
 995 };
 996
 997 #define HCLGE_FD_EPORT_SW_EN_B          0
 998 struct hclge_fd_tcam_config_1_cmd {
 999         u8 stage;
1000         u8 xy_sel;
1001         u8 port_info;
1002         u8 rsv1[1];
1003         __le32 index;
1004         u8 entry_vld;
1005         u8 rsv2[7];
1006         u8 tcam_data[8];
1007 };
1008
1009 struct hclge_fd_tcam_config_2_cmd {
1010         u8 tcam_data[24];
1011 };
1012
1013 struct hclge_fd_tcam_config_3_cmd {
1014         u8 tcam_data[20];
1015         u8 rsv[4];
1016 };
1017
1018 #define HCLGE_FD_AD_DROP_B              0
1019 #define HCLGE_FD_AD_DIRECT_QID_B        1
1020 #define HCLGE_FD_AD_QID_S               2
1021 #define HCLGE_FD_AD_QID_M               GENMASK(12, 2)
1022 #define HCLGE_FD_AD_USE_COUNTER_B       12
1023 #define HCLGE_FD_AD_COUNTER_NUM_S       13
1024 #define HCLGE_FD_AD_COUNTER_NUM_M       GENMASK(20, 13)
1025 #define HCLGE_FD_AD_NXT_STEP_B          20
1026 #define HCLGE_FD_AD_NXT_KEY_S           21
1027 #define HCLGE_FD_AD_NXT_KEY_M           GENMASK(26, 21)
1028 #define HCLGE_FD_AD_WR_RULE_ID_B        0
1029 #define HCLGE_FD_AD_RULE_ID_S           1
1030 #define HCLGE_FD_AD_RULE_ID_M           GENMASK(13, 1)
1031
1032 struct hclge_fd_ad_config_cmd {
1033         u8 stage;
1034         u8 rsv1[3];
1035         __le32 index;
1036         __le64 ad_data;
1037         u8 rsv2[8];
1038 };
1039
1040 struct hclge_get_m7_bd_cmd {
1041         __le32 bd_num;
1042         u8 rsv[20];
1043 };
1044
1045 struct hclge_query_ppu_pf_other_int_dfx_cmd {
1046         __le16 over_8bd_no_fe_qid;
1047         __le16 over_8bd_no_fe_vf_id;
1048         __le16 tso_mss_cmp_min_err_qid;
1049         __le16 tso_mss_cmp_min_err_vf_id;
1050         __le16 tso_mss_cmp_max_err_qid;
1051         __le16 tso_mss_cmp_max_err_vf_id;
1052         __le16 tx_rd_fbd_poison_qid;
1053         __le16 tx_rd_fbd_poison_vf_id;
1054         __le16 rx_rd_fbd_poison_qid;
1055         __le16 rx_rd_fbd_poison_vf_id;
1056         u8 rsv[4];
1057 };
1058
1059 #define HCLGE_LINK_EVENT_REPORT_EN_B    0
1060 #define HCLGE_NCSI_ERROR_REPORT_EN_B    1
1061 struct hclge_firmware_compat_cmd {
1062         __le32 compat;
1063         u8 rsv[20];
1064 };
1065
1066 int hclge_cmd_init(struct hclge_dev *hdev);
1067 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
1068 {
1069         writel(value, base + reg);
1070 }
1071
1072 #define hclge_write_dev(a, reg, value) \
1073         hclge_write_reg((a)->io_base, (reg), (value))
1074 #define hclge_read_dev(a, reg) \
1075         hclge_read_reg((a)->io_base, (reg))
1076
1077 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
1078 {
1079         u8 __iomem *reg_addr = READ_ONCE(base);
1080
1081         return readl(reg_addr + reg);
1082 }
1083
1084 #define HCLGE_SEND_SYNC(flag) \
1085         ((flag) & HCLGE_CMD_FLAG_NO_INTR)
1086
1087 struct hclge_hw;
1088 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
1089 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
1090                                 enum hclge_opcode_type opcode, bool is_read);
1091 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
1092
1093 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
1094                                struct hclge_promisc_param *param);
1095
1096 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
1097                                            struct hclge_desc *desc);
1098 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
1099                                           struct hclge_desc *desc);
1100
1101 void hclge_cmd_uninit(struct hclge_dev *hdev);
1102 int hclge_cmd_queue_init(struct hclge_dev *hdev);
1103 #endif