2 * Copyright (c) 2014-2015 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include "hns_dsaf_misc.h"
11 #include "hns_dsaf_mac.h"
12 #include "hns_dsaf_reg.h"
13 #include "hns_dsaf_ppe.h"
15 void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
22 pr_err("sfp_led_opt mac_dev is null!\n");
25 if (!mac_cb->cpld_vaddr) {
26 dev_err(mac_cb->dev, "mac_id=%d, cpld_vaddr is null !\n",
31 if (speed == MAC_SPEED_10000)
34 value = mac_cb->cpld_led_value;
37 dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
38 dsaf_set_field(value, DSAF_LED_SPEED_M,
39 DSAF_LED_SPEED_S, speed_reg);
40 dsaf_set_bit(value, DSAF_LED_DATA_B, data);
42 if (value != mac_cb->cpld_led_value) {
43 dsaf_write_b(mac_cb->cpld_vaddr, value);
44 mac_cb->cpld_led_value = value;
47 dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
48 mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
52 void cpld_led_reset(struct hns_mac_cb *mac_cb)
54 if (!mac_cb || !mac_cb->cpld_vaddr)
57 dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
58 mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
61 int cpld_set_led_id(struct hns_mac_cb *mac_cb,
62 enum hnae_led_state status)
66 mac_cb->cpld_led_value = dsaf_read_b(mac_cb->cpld_vaddr);
67 dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
69 dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
71 case HNAE_LED_INACTIVE:
72 dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
73 CPLD_LED_DEFAULT_VALUE);
74 dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
83 #define RESET_REQ_OR_DREQ 1
85 void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val)
91 xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
92 nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
94 xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
95 nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
98 dsaf_write_reg(dsaf_dev->sc_base, xbar_reg_addr,
100 dsaf_write_reg(dsaf_dev->sc_base, nt_reg_addr,
104 void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
109 if (port >= DSAF_XGE_NUM)
112 reg_val |= RESET_REQ_OR_DREQ;
113 reg_val |= 0x2082082 << port;
116 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
118 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
120 dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
123 void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
129 if (port >= DSAF_XGE_NUM)
132 reg_val |= XGMAC_TRX_CORE_SRST_M << port;
135 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
137 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
139 dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
142 void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
147 if (port >= DSAF_GE_NUM)
150 if (port < DSAF_SERVICE_NW_NUM) {
151 reg_val_1 = 0x1 << port;
152 /* there is difference between V1 and V2 in register.*/
153 if (AE_IS_VER1(dsaf_dev->dsaf_ver))
154 reg_val_2 = 0x1041041 << port;
156 reg_val_2 = 0x2082082 << port;
159 dsaf_write_reg(dsaf_dev->sc_base,
160 DSAF_SUB_SC_GE_RESET_REQ1_REG,
163 dsaf_write_reg(dsaf_dev->sc_base,
164 DSAF_SUB_SC_GE_RESET_REQ0_REG,
167 dsaf_write_reg(dsaf_dev->sc_base,
168 DSAF_SUB_SC_GE_RESET_DREQ0_REG,
171 dsaf_write_reg(dsaf_dev->sc_base,
172 DSAF_SUB_SC_GE_RESET_DREQ1_REG,
176 reg_val_1 = 0x15540 << (port - 6);
177 reg_val_2 = 0x100 << (port - 6);
180 dsaf_write_reg(dsaf_dev->sc_base,
181 DSAF_SUB_SC_GE_RESET_REQ1_REG,
184 dsaf_write_reg(dsaf_dev->sc_base,
185 DSAF_SUB_SC_PPE_RESET_REQ_REG,
188 dsaf_write_reg(dsaf_dev->sc_base,
189 DSAF_SUB_SC_GE_RESET_DREQ1_REG,
192 dsaf_write_reg(dsaf_dev->sc_base,
193 DSAF_SUB_SC_PPE_RESET_DREQ_REG,
199 void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
204 reg_val |= RESET_REQ_OR_DREQ << port;
207 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
209 reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
211 dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
214 void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
216 int comm_index = ppe_common->comm_index;
217 struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
221 if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX) {
222 reg_val = RESET_REQ_OR_DREQ;
224 reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
226 reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
229 reg_val = 0x100 << (comm_index - 1);
232 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
234 reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
237 dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
241 * hns_mac_get_sds_mode - get phy ifterface form serdes mode
242 * @mac_cb: mac control block
243 * retuen phy interface
245 phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
249 void __iomem *sys_ctl_vaddr = mac_cb->sys_ctl_vaddr;
250 int dev_id = mac_cb->mac_id;
251 phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
253 hilink3_mode = dsaf_read_reg(sys_ctl_vaddr, HNS_MAC_HILINK3_REG);
254 hilink4_mode = dsaf_read_reg(sys_ctl_vaddr, HNS_MAC_HILINK4_REG);
255 if (dev_id >= 0 && dev_id <= 3) {
256 if (hilink4_mode == 0)
257 phy_if = PHY_INTERFACE_MODE_SGMII;
259 phy_if = PHY_INTERFACE_MODE_XGMII;
260 } else if (dev_id >= 4 && dev_id <= 5) {
261 if (hilink3_mode == 0)
262 phy_if = PHY_INTERFACE_MODE_SGMII;
264 phy_if = PHY_INTERFACE_MODE_XGMII;
266 phy_if = PHY_INTERFACE_MODE_SGMII;
270 "hilink3_mode=%d, hilink4_mode=%d dev_id=%d, phy_if=%d\n",
271 hilink3_mode, hilink4_mode, dev_id, phy_if);
276 * hns_mac_config_sds_loopback - set loop back for serdes
277 * @mac_cb: mac control block
278 * retuen 0 == success
280 int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, u8 en)
282 /* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
283 * port 4-7 hilink3 base is serdes_vaddr + 0x00200000
285 u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
286 (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
287 const u8 lane_id[] = {
288 0, /* mac 0 -> lane 0 */
289 1, /* mac 1 -> lane 1 */
290 2, /* mac 2 -> lane 2 */
291 3, /* mac 3 -> lane 3 */
292 2, /* mac 4 -> lane 2 */
293 3, /* mac 5 -> lane 3 */
294 0, /* mac 6 -> lane 0 */
295 1 /* mac 7 -> lane 1 */
297 #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
298 u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);
301 int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);
303 if (!mac_cb->phy_node) {
305 pr_info("please confirm sfp is present or not\n");
308 pr_info("no sfp in this eth\n");
311 dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en);