drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (c) 2014-2015 Hisilicon Limited.
   4  */
   5
   6 #include <linux/acpi.h>
   7 #include <linux/device.h>
   8 #include <linux/init.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/vmalloc.h>
  20
  21 #include "hns_dsaf_mac.h"
  22 #include "hns_dsaf_main.h"
  23 #include "hns_dsaf_ppe.h"
  24 #include "hns_dsaf_rcb.h"
  25 #include "hns_dsaf_misc.h"
  26
  27 static const char *g_dsaf_mode_match[DSAF_MODE_MAX] = {
  28         [DSAF_MODE_DISABLE_2PORT_64VM] = "2port-64vf",
  29         [DSAF_MODE_DISABLE_6PORT_0VM] = "6port-16rss",
  30         [DSAF_MODE_DISABLE_6PORT_16VM] = "6port-16vf",
  31         [DSAF_MODE_DISABLE_SP] = "single-port",
  32 };
  33
  34 static const struct acpi_device_id hns_dsaf_acpi_match[] = {
  35         { "HISI00B1", 0 },
  36         { "HISI00B2", 0 },
  37         { },
  38 };
  39 MODULE_DEVICE_TABLE(acpi, hns_dsaf_acpi_match);
  40
  41 static int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev)
  42 {
  43         int ret, i;
  44         u32 desc_num;
  45         u32 buf_size;
  46         u32 reset_offset = 0;
  47         u32 res_idx = 0;
  48         const char *mode_str;
  49         struct regmap *syscon;
  50         struct resource *res;
  51         struct device_node *np = dsaf_dev->dev->of_node, *np_temp;
  52         struct platform_device *pdev = to_platform_device(dsaf_dev->dev);
  53
  54         if (dev_of_node(dsaf_dev->dev)) {
  55                 if (of_device_is_compatible(np, "hisilicon,hns-dsaf-v1"))
  56                         dsaf_dev->dsaf_ver = AE_VERSION_1;
  57                 else
  58                         dsaf_dev->dsaf_ver = AE_VERSION_2;
  59         } else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
  60                 if (acpi_dev_found(hns_dsaf_acpi_match[0].id))
  61                         dsaf_dev->dsaf_ver = AE_VERSION_1;
  62                 else if (acpi_dev_found(hns_dsaf_acpi_match[1].id))
  63                         dsaf_dev->dsaf_ver = AE_VERSION_2;
  64                 else
  65                         return -ENXIO;
  66         } else {
  67                 dev_err(dsaf_dev->dev, "cannot get cfg data from of or acpi\n");
  68                 return -ENXIO;
  69         }
  70
  71         ret = device_property_read_string(dsaf_dev->dev, "mode", &mode_str);
  72         if (ret) {
  73                 dev_err(dsaf_dev->dev, "get dsaf mode fail, ret=%d!\n", ret);
  74                 return ret;
  75         }
  76         for (i = 0; i < DSAF_MODE_MAX; i++) {
  77                 if (g_dsaf_mode_match[i] &&
  78                     !strcmp(mode_str, g_dsaf_mode_match[i]))
  79                         break;
  80         }
  81         if (i >= DSAF_MODE_MAX ||
  82             i == DSAF_MODE_INVALID || i == DSAF_MODE_ENABLE) {
  83                 dev_err(dsaf_dev->dev,
  84                         "%s prs mode str fail!\n", dsaf_dev->ae_dev.name);
  85                 return -EINVAL;
  86         }
  87         dsaf_dev->dsaf_mode = (enum dsaf_mode)i;
  88
  89         if (dsaf_dev->dsaf_mode > DSAF_MODE_ENABLE)
  90                 dsaf_dev->dsaf_en = HRD_DSAF_NO_DSAF_MODE;
  91         else
  92                 dsaf_dev->dsaf_en = HRD_DSAF_MODE;
  93
  94         if ((i == DSAF_MODE_ENABLE_16VM) ||
  95             (i == DSAF_MODE_DISABLE_2PORT_8VM) ||
  96             (i == DSAF_MODE_DISABLE_6PORT_2VM))
  97                 dsaf_dev->dsaf_tc_mode = HRD_DSAF_8TC_MODE;
  98         else
  99                 dsaf_dev->dsaf_tc_mode = HRD_DSAF_4TC_MODE;
 100
 101         if (dev_of_node(dsaf_dev->dev)) {
 102                 np_temp = of_parse_phandle(np, "subctrl-syscon", 0);
 103                 syscon = syscon_node_to_regmap(np_temp);
 104                 of_node_put(np_temp);
 105                 if (IS_ERR_OR_NULL(syscon)) {
 106                         res = platform_get_resource(pdev, IORESOURCE_MEM,
 107                                                     res_idx++);
 108                         if (!res) {
 109                                 dev_err(dsaf_dev->dev, "subctrl info is needed!\n");
 110                                 return -ENOMEM;
 111                         }
 112
 113                         dsaf_dev->sc_base = devm_ioremap_resource(&pdev->dev,
 114                                                                   res);
 115                         if (IS_ERR(dsaf_dev->sc_base))
 116                                 return PTR_ERR(dsaf_dev->sc_base);
 117
 118                         res = platform_get_resource(pdev, IORESOURCE_MEM,
 119                                                     res_idx++);
 120                         if (!res) {
 121                                 dev_err(dsaf_dev->dev, "serdes-ctrl info is needed!\n");
 122                                 return -ENOMEM;
 123                         }
 124
 125                         dsaf_dev->sds_base = devm_ioremap_resource(&pdev->dev,
 126                                                                    res);
 127                         if (IS_ERR(dsaf_dev->sds_base))
 128                                 return PTR_ERR(dsaf_dev->sds_base);
 129                 } else {
 130                         dsaf_dev->sub_ctrl = syscon;
 131                 }
 132         }
 133
 134         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppe-base");
 135         if (!res) {
 136                 res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx++);
 137                 if (!res) {
 138                         dev_err(dsaf_dev->dev, "ppe-base info is needed!\n");
 139                         return -ENOMEM;
 140                 }
 141         }
 142         dsaf_dev->ppe_base = devm_ioremap_resource(&pdev->dev, res);
 143         if (IS_ERR(dsaf_dev->ppe_base))
 144                 return PTR_ERR(dsaf_dev->ppe_base);
 145         dsaf_dev->ppe_paddr = res->start;
 146
 147         if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
 148                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 149                                                    "dsaf-base");
 150                 if (!res) {
 151                         res = platform_get_resource(pdev, IORESOURCE_MEM,
 152                                                     res_idx);
 153                         if (!res) {
 154                                 dev_err(dsaf_dev->dev,
 155                                         "dsaf-base info is needed!\n");
 156                                 return -ENOMEM;
 157                         }
 158                 }
 159                 dsaf_dev->io_base = devm_ioremap_resource(&pdev->dev, res);
 160                 if (IS_ERR(dsaf_dev->io_base))
 161                         return PTR_ERR(dsaf_dev->io_base);
 162         }
 163
 164         ret = device_property_read_u32(dsaf_dev->dev, "desc-num", &desc_num);
 165         if (ret < 0 || desc_num < HNS_DSAF_MIN_DESC_CNT ||
 166             desc_num > HNS_DSAF_MAX_DESC_CNT) {
 167                 dev_err(dsaf_dev->dev, "get desc-num(%d) fail, ret=%d!\n",
 168                         desc_num, ret);
 169                 return -EINVAL;
 170         }
 171         dsaf_dev->desc_num = desc_num;
 172
 173         ret = device_property_read_u32(dsaf_dev->dev, "reset-field-offset",
 174                                        &reset_offset);
 175         if (ret < 0) {
 176                 dev_dbg(dsaf_dev->dev,
 177                         "get reset-field-offset fail, ret=%d!\r\n", ret);
 178         }
 179         dsaf_dev->reset_offset = reset_offset;
 180
 181         ret = device_property_read_u32(dsaf_dev->dev, "buf-size", &buf_size);
 182         if (ret < 0) {
 183                 dev_err(dsaf_dev->dev,
 184                         "get buf-size fail, ret=%d!\r\n", ret);
 185                 return ret;
 186         }
 187         dsaf_dev->buf_size = buf_size;
 188
 189         dsaf_dev->buf_size_type = hns_rcb_buf_size2type(buf_size);
 190         if (dsaf_dev->buf_size_type < 0) {
 191                 dev_err(dsaf_dev->dev,
 192                         "buf_size(%d) is wrong!\n", buf_size);
 193                 return -EINVAL;
 194         }
 195
 196         dsaf_dev->misc_op = hns_misc_op_get(dsaf_dev);
 197         if (!dsaf_dev->misc_op)
 198                 return -ENOMEM;
 199
 200         if (!dma_set_mask_and_coherent(dsaf_dev->dev, DMA_BIT_MASK(64ULL)))
 201                 dev_dbg(dsaf_dev->dev, "set mask to 64bit\n");
 202         else
 203                 dev_err(dsaf_dev->dev, "set mask to 64bit fail!\n");
 204
 205         return 0;
 206 }
 207
 208 /**
 209  * hns_dsaf_sbm_link_sram_init_en - config dsaf_sbm_init_en
 210  * @dsaf_id: dsa fabric id
 211  */
 212 static void hns_dsaf_sbm_link_sram_init_en(struct dsaf_device *dsaf_dev)
 213 {
 214         dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_SBM_INIT_S, 1);
 215 }
 216
 217 /**
 218  * hns_dsaf_reg_cnt_clr_ce - config hns_dsaf_reg_cnt_clr_ce
 219  * @dsaf_id: dsa fabric id
 220  * @hns_dsaf_reg_cnt_clr_ce: config value
 221  */
 222 static void
 223 hns_dsaf_reg_cnt_clr_ce(struct dsaf_device *dsaf_dev, u32 reg_cnt_clr_ce)
 224 {
 225         dsaf_set_dev_bit(dsaf_dev, DSAF_DSA_REG_CNT_CLR_CE_REG,
 226                          DSAF_CNT_CLR_CE_S, reg_cnt_clr_ce);
 227 }
 228
 229 /**
 230  * hns_ppe_qid_cfg - config ppe qid
 231  * @dsaf_id: dsa fabric id
 232  * @pppe_qid_cfg: value array
 233  */
 234 static void
 235 hns_dsaf_ppe_qid_cfg(struct dsaf_device *dsaf_dev, u32 qid_cfg)
 236 {
 237         u32 i;
 238
 239         for (i = 0; i < DSAF_COMM_CHN; i++) {
 240                 dsaf_set_dev_field(dsaf_dev,
 241                                    DSAF_PPE_QID_CFG_0_REG + 0x0004 * i,
 242                                    DSAF_PPE_QID_CFG_M, DSAF_PPE_QID_CFG_S,
 243                                    qid_cfg);
 244         }
 245 }
 246
 247 static void hns_dsaf_mix_def_qid_cfg(struct dsaf_device *dsaf_dev)
 248 {
 249         u16 max_q_per_vf, max_vfn;
 250         u32 q_id, q_num_per_port;
 251         u32 i;
 252
 253         hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
 254         q_num_per_port = max_vfn * max_q_per_vf;
 255
 256         for (i = 0, q_id = 0; i < DSAF_SERVICE_NW_NUM; i++) {
 257                 dsaf_set_dev_field(dsaf_dev,
 258                                    DSAF_MIX_DEF_QID_0_REG + 0x0004 * i,
 259                                    0xff, 0, q_id);
 260                 q_id += q_num_per_port;
 261         }
 262 }
 263
 264 static void hns_dsaf_inner_qid_cfg(struct dsaf_device *dsaf_dev)
 265 {
 266         u16 max_q_per_vf, max_vfn;
 267         u32 q_id, q_num_per_port;
 268         u32 mac_id;
 269
 270         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
 271                 return;
 272
 273         hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
 274         q_num_per_port = max_vfn * max_q_per_vf;
 275
 276         for (mac_id = 0, q_id = 0; mac_id < DSAF_SERVICE_NW_NUM; mac_id++) {
 277                 dsaf_set_dev_field(dsaf_dev,
 278                                    DSAFV2_SERDES_LBK_0_REG + 4 * mac_id,
 279                                    DSAFV2_SERDES_LBK_QID_M,
 280                                    DSAFV2_SERDES_LBK_QID_S,
 281                                    q_id);
 282                 q_id += q_num_per_port;
 283         }
 284 }
 285
 286 /**
 287  * hns_dsaf_sw_port_type_cfg - cfg sw type
 288  * @dsaf_id: dsa fabric id
 289  * @psw_port_type: array
 290  */
 291 static void hns_dsaf_sw_port_type_cfg(struct dsaf_device *dsaf_dev,
 292                                       enum dsaf_sw_port_type port_type)
 293 {
 294         u32 i;
 295
 296         for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
 297                 dsaf_set_dev_field(dsaf_dev,
 298                                    DSAF_SW_PORT_TYPE_0_REG + 0x0004 * i,
 299                                    DSAF_SW_PORT_TYPE_M, DSAF_SW_PORT_TYPE_S,
 300                                    port_type);
 301         }
 302 }
 303
 304 /**
 305  * hns_dsaf_stp_port_type_cfg - cfg stp type
 306  * @dsaf_id: dsa fabric id
 307  * @pstp_port_type: array
 308  */
 309 static void hns_dsaf_stp_port_type_cfg(struct dsaf_device *dsaf_dev,
 310                                        enum dsaf_stp_port_type port_type)
 311 {
 312         u32 i;
 313
 314         for (i = 0; i < DSAF_COMM_CHN; i++) {
 315                 dsaf_set_dev_field(dsaf_dev,
 316                                    DSAF_STP_PORT_TYPE_0_REG + 0x0004 * i,
 317                                    DSAF_STP_PORT_TYPE_M, DSAF_STP_PORT_TYPE_S,
 318                                    port_type);
 319         }
 320 }
 321
 322 #define HNS_DSAF_SBM_NUM(dev) \
 323         (AE_IS_VER1((dev)->dsaf_ver) ? DSAF_SBM_NUM : DSAFV2_SBM_NUM)
 324 /**
 325  * hns_dsaf_sbm_cfg - config sbm
 326  * @dsaf_id: dsa fabric id
 327  */
 328 static void hns_dsaf_sbm_cfg(struct dsaf_device *dsaf_dev)
 329 {
 330         u32 o_sbm_cfg;
 331         u32 i;
 332
 333         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 334                 o_sbm_cfg = dsaf_read_dev(dsaf_dev,
 335                                           DSAF_SBM_CFG_REG_0_REG + 0x80 * i);
 336                 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_EN_S, 1);
 337                 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_SHCUT_EN_S, 0);
 338                 dsaf_write_dev(dsaf_dev,
 339                                DSAF_SBM_CFG_REG_0_REG + 0x80 * i, o_sbm_cfg);
 340         }
 341 }
 342
 343 /**
 344  * hns_dsaf_sbm_cfg_mib_en - config sbm
 345  * @dsaf_id: dsa fabric id
 346  */
 347 static int hns_dsaf_sbm_cfg_mib_en(struct dsaf_device *dsaf_dev)
 348 {
 349         u32 sbm_cfg_mib_en;
 350         u32 i;
 351         u32 reg;
 352         u32 read_cnt;
 353
 354         /* validate configure by setting SBM_CFG_MIB_EN bit from 0 to 1. */
 355         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 356                 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 357                 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0);
 358         }
 359
 360         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 361                 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 362                 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1);
 363         }
 364
 365         /* waitint for all sbm enable finished */
 366         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 367                 read_cnt = 0;
 368                 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 369                 do {
 370                         udelay(1);
 371                         sbm_cfg_mib_en = dsaf_get_dev_bit(
 372                                         dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S);
 373                         read_cnt++;
 374                 } while (sbm_cfg_mib_en == 0 &&
 375                         read_cnt < DSAF_CFG_READ_CNT);
 376
 377                 if (sbm_cfg_mib_en == 0) {
 378                         dev_err(dsaf_dev->dev,
 379                                 "sbm_cfg_mib_en fail,%s,sbm_num=%d\n",
 380                                 dsaf_dev->ae_dev.name, i);
 381                         return -ENODEV;
 382                 }
 383         }
 384
 385         return 0;
 386 }
 387
 388 /**
 389  * hns_dsaf_sbm_bp_wl_cfg - config sbm
 390  * @dsaf_id: dsa fabric id
 391  */
 392 static void hns_dsaf_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
 393 {
 394         u32 o_sbm_bp_cfg;
 395         u32 reg;
 396         u32 i;
 397
 398         /* XGE */
 399         for (i = 0; i < DSAF_XGE_NUM; i++) {
 400                 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
 401                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 402                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M,
 403                                DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S, 512);
 404                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M,
 405                                DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
 406                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M,
 407                                DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
 408                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 409
 410                 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
 411                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 412                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M,
 413                                DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
 414                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M,
 415                                DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
 416                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 417
 418                 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
 419                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 420                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 421                                DSAF_SBM_CFG2_SET_BUF_NUM_S, 104);
 422                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 423                                DSAF_SBM_CFG2_RESET_BUF_NUM_S, 128);
 424                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 425
 426                 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
 427                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 428                 dsaf_set_field(o_sbm_bp_cfg,
 429                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 430                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 110);
 431                 dsaf_set_field(o_sbm_bp_cfg,
 432                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 433                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 160);
 434                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 435
 436                 /* for no enable pfc mode */
 437                 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
 438                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 439                 dsaf_set_field(o_sbm_bp_cfg,
 440                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 441                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 128);
 442                 dsaf_set_field(o_sbm_bp_cfg,
 443                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 444                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 192);
 445                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 446         }
 447
 448         /* PPE */
 449         for (i = 0; i < DSAF_COMM_CHN; i++) {
 450                 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
 451                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 452                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 453                                DSAF_SBM_CFG2_SET_BUF_NUM_S, 10);
 454                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 455                                DSAF_SBM_CFG2_RESET_BUF_NUM_S, 12);
 456                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 457         }
 458
 459         /* RoCEE */
 460         for (i = 0; i < DSAF_COMM_CHN; i++) {
 461                 reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
 462                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 463                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 464                                DSAF_SBM_CFG2_SET_BUF_NUM_S, 2);
 465                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 466                                DSAF_SBM_CFG2_RESET_BUF_NUM_S, 4);
 467                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 468         }
 469 }
 470
 471 static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
 472 {
 473         u32 o_sbm_bp_cfg;
 474         u32 reg;
 475         u32 i;
 476
 477         /* XGE */
 478         for (i = 0; i < DSAFV2_SBM_XGE_CHN; i++) {
 479                 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
 480                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 481                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M,
 482                                DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S, 256);
 483                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M,
 484                                DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
 485                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M,
 486                                DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
 487                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 488
 489                 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
 490                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 491                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M,
 492                                DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
 493                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M,
 494                                DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
 495                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 496
 497                 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
 498                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 499                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M,
 500                                DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 104);
 501                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M,
 502                                DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 128);
 503                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 504
 505                 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
 506                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 507                 dsaf_set_field(o_sbm_bp_cfg,
 508                                DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 509                                DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 55);
 510                 dsaf_set_field(o_sbm_bp_cfg,
 511                                DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 512                                DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 110);
 513                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 514
 515                 /* for no enable pfc mode */
 516                 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
 517                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 518                 dsaf_set_field(o_sbm_bp_cfg,
 519                                DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M,
 520                                DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 128);
 521                 dsaf_set_field(o_sbm_bp_cfg,
 522                                DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M,
 523                                DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 192);
 524                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 525         }
 526
 527         /* PPE */
 528         for (i = 0; i < DSAFV2_SBM_PPE_CHN; i++) {
 529                 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
 530                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 531                 dsaf_set_field(o_sbm_bp_cfg,
 532                                DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M,
 533                                DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S, 2);
 534                 dsaf_set_field(o_sbm_bp_cfg,
 535                                DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M,
 536                                DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S, 3);
 537                 dsaf_set_field(o_sbm_bp_cfg,
 538                                DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M,
 539                                DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S, 52);
 540                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 541         }
 542
 543         /* RoCEE */
 544         for (i = 0; i < DASFV2_ROCEE_CRD_NUM; i++) {
 545                 reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
 546                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 547                 dsaf_set_field(o_sbm_bp_cfg,
 548                                DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M,
 549                                DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S, 2);
 550                 dsaf_set_field(o_sbm_bp_cfg,
 551                                DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M,
 552                                DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S, 4);
 553                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 554         }
 555 }
 556
 557 /**
 558  * hns_dsaf_voq_bp_all_thrd_cfg -  voq
 559  * @dsaf_id: dsa fabric id
 560  */
 561 static void hns_dsaf_voq_bp_all_thrd_cfg(struct dsaf_device *dsaf_dev)
 562 {
 563         u32 voq_bp_all_thrd;
 564         u32 i;
 565
 566         for (i = 0; i < DSAF_VOQ_NUM; i++) {
 567                 voq_bp_all_thrd = dsaf_read_dev(
 568                         dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i);
 569                 if (i < DSAF_XGE_NUM) {
 570                         dsaf_set_field(voq_bp_all_thrd,
 571                                        DSAF_VOQ_BP_ALL_DOWNTHRD_M,
 572                                        DSAF_VOQ_BP_ALL_DOWNTHRD_S, 930);
 573                         dsaf_set_field(voq_bp_all_thrd,
 574                                        DSAF_VOQ_BP_ALL_UPTHRD_M,
 575                                        DSAF_VOQ_BP_ALL_UPTHRD_S, 950);
 576                 } else {
 577                         dsaf_set_field(voq_bp_all_thrd,
 578                                        DSAF_VOQ_BP_ALL_DOWNTHRD_M,
 579                                        DSAF_VOQ_BP_ALL_DOWNTHRD_S, 220);
 580                         dsaf_set_field(voq_bp_all_thrd,
 581                                        DSAF_VOQ_BP_ALL_UPTHRD_M,
 582                                        DSAF_VOQ_BP_ALL_UPTHRD_S, 230);
 583                 }
 584                 dsaf_write_dev(
 585                         dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i,
 586                         voq_bp_all_thrd);
 587         }
 588 }
 589
 590 static void hns_dsaf_tbl_tcam_match_cfg(
 591         struct dsaf_device *dsaf_dev,
 592         struct dsaf_tbl_tcam_data *ptbl_tcam_data)
 593 {
 594         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_L_REG,
 595                        ptbl_tcam_data->tbl_tcam_data_low);
 596         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_H_REG,
 597                        ptbl_tcam_data->tbl_tcam_data_high);
 598 }
 599
 600 /**
 601  * hns_dsaf_tbl_tcam_data_cfg - tbl
 602  * @dsaf_id: dsa fabric id
 603  * @ptbl_tcam_data: addr
 604  */
 605 static void hns_dsaf_tbl_tcam_data_cfg(
 606         struct dsaf_device *dsaf_dev,
 607         struct dsaf_tbl_tcam_data *ptbl_tcam_data)
 608 {
 609         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_LOW_0_REG,
 610                        ptbl_tcam_data->tbl_tcam_data_low);
 611         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_HIGH_0_REG,
 612                        ptbl_tcam_data->tbl_tcam_data_high);
 613 }
 614
 615 /**
 616  * dsaf_tbl_tcam_mcast_cfg - tbl
 617  * @dsaf_id: dsa fabric id
 618  * @ptbl_tcam_mcast: addr
 619  */
 620 static void hns_dsaf_tbl_tcam_mcast_cfg(
 621         struct dsaf_device *dsaf_dev,
 622         struct dsaf_tbl_tcam_mcast_cfg *mcast)
 623 {
 624         u32 mcast_cfg4;
 625
 626         mcast_cfg4 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
 627         dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S,
 628                      mcast->tbl_mcast_item_vld);
 629         dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_OLD_EN_S,
 630                      mcast->tbl_mcast_old_en);
 631         dsaf_set_field(mcast_cfg4, DSAF_TBL_MCAST_CFG4_VM128_112_M,
 632                        DSAF_TBL_MCAST_CFG4_VM128_112_S,
 633                        mcast->tbl_mcast_port_msk[4]);
 634         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, mcast_cfg4);
 635
 636         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG,
 637                        mcast->tbl_mcast_port_msk[3]);
 638
 639         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG,
 640                        mcast->tbl_mcast_port_msk[2]);
 641
 642         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG,
 643                        mcast->tbl_mcast_port_msk[1]);
 644
 645         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG,
 646                        mcast->tbl_mcast_port_msk[0]);
 647 }
 648
 649 /**
 650  * hns_dsaf_tbl_tcam_ucast_cfg - tbl
 651  * @dsaf_id: dsa fabric id
 652  * @ptbl_tcam_ucast: addr
 653  */
 654 static void hns_dsaf_tbl_tcam_ucast_cfg(
 655         struct dsaf_device *dsaf_dev,
 656         struct dsaf_tbl_tcam_ucast_cfg *tbl_tcam_ucast)
 657 {
 658         u32 ucast_cfg1;
 659
 660         ucast_cfg1 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
 661         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S,
 662                      tbl_tcam_ucast->tbl_ucast_mac_discard);
 663         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_ITEM_VLD_S,
 664                      tbl_tcam_ucast->tbl_ucast_item_vld);
 665         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OLD_EN_S,
 666                      tbl_tcam_ucast->tbl_ucast_old_en);
 667         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_DVC_S,
 668                      tbl_tcam_ucast->tbl_ucast_dvc);
 669         dsaf_set_field(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
 670                        DSAF_TBL_UCAST_CFG1_OUT_PORT_S,
 671                        tbl_tcam_ucast->tbl_ucast_out_port);
 672         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG, ucast_cfg1);
 673 }
 674
 675 /**
 676  * hns_dsaf_tbl_line_cfg - tbl
 677  * @dsaf_id: dsa fabric id
 678  * @ptbl_lin: addr
 679  */
 680 static void hns_dsaf_tbl_line_cfg(struct dsaf_device *dsaf_dev,
 681                                   struct dsaf_tbl_line_cfg *tbl_lin)
 682 {
 683         u32 tbl_line;
 684
 685         tbl_line = dsaf_read_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG);
 686         dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_MAC_DISCARD_S,
 687                      tbl_lin->tbl_line_mac_discard);
 688         dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_DVC_S,
 689                      tbl_lin->tbl_line_dvc);
 690         dsaf_set_field(tbl_line, DSAF_TBL_LINE_CFG_OUT_PORT_M,
 691                        DSAF_TBL_LINE_CFG_OUT_PORT_S,
 692                        tbl_lin->tbl_line_out_port);
 693         dsaf_write_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG, tbl_line);
 694 }
 695
 696 /**
 697  * hns_dsaf_tbl_tcam_mcast_pul - tbl
 698  * @dsaf_id: dsa fabric id
 699  */
 700 static void hns_dsaf_tbl_tcam_mcast_pul(struct dsaf_device *dsaf_dev)
 701 {
 702         u32 o_tbl_pul;
 703
 704         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 705         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
 706         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 707         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
 708         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 709 }
 710
 711 /**
 712  * hns_dsaf_tbl_line_pul - tbl
 713  * @dsaf_id: dsa fabric id
 714  */
 715 static void hns_dsaf_tbl_line_pul(struct dsaf_device *dsaf_dev)
 716 {
 717         u32 tbl_pul;
 718
 719         tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 720         dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 1);
 721         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
 722         dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 0);
 723         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
 724 }
 725
 726 /**
 727  * hns_dsaf_tbl_tcam_data_mcast_pul - tbl
 728  * @dsaf_id: dsa fabric id
 729  */
 730 static void hns_dsaf_tbl_tcam_data_mcast_pul(
 731         struct dsaf_device *dsaf_dev)
 732 {
 733         u32 o_tbl_pul;
 734
 735         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 736         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
 737         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
 738         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 739         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
 740         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
 741         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 742 }
 743
 744 /**
 745  * hns_dsaf_tbl_tcam_data_ucast_pul - tbl
 746  * @dsaf_id: dsa fabric id
 747  */
 748 static void hns_dsaf_tbl_tcam_data_ucast_pul(
 749         struct dsaf_device *dsaf_dev)
 750 {
 751         u32 o_tbl_pul;
 752
 753         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 754         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
 755         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 1);
 756         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 757         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
 758         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 0);
 759         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 760 }
 761
 762 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en)
 763 {
 764         if (AE_IS_VER1(dsaf_dev->dsaf_ver) && !HNS_DSAF_IS_DEBUG(dsaf_dev))
 765                 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG,
 766                                  DSAF_CFG_MIX_MODE_S, !!en);
 767 }
 768
 769 /**
 770  * hns_dsaf_tbl_stat_en - tbl
 771  * @dsaf_id: dsa fabric id
 772  * @ptbl_stat_en: addr
 773  */
 774 static void hns_dsaf_tbl_stat_en(struct dsaf_device *dsaf_dev)
 775 {
 776         u32 o_tbl_ctrl;
 777
 778         o_tbl_ctrl = dsaf_read_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG);
 779         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S, 1);
 780         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_UC_LKUP_NUM_EN_S, 1);
 781         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_MC_LKUP_NUM_EN_S, 1);
 782         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_BC_LKUP_NUM_EN_S, 1);
 783         dsaf_write_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG, o_tbl_ctrl);
 784 }
 785
 786 /**
 787  * hns_dsaf_rocee_bp_en - rocee back press enable
 788  * @dsaf_id: dsa fabric id
 789  */
 790 static void hns_dsaf_rocee_bp_en(struct dsaf_device *dsaf_dev)
 791 {
 792         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
 793                 dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG,
 794                                  DSAF_FC_XGE_TX_PAUSE_S, 1);
 795 }
 796
 797 /* set msk for dsaf exception irq*/
 798 static void hns_dsaf_int_xge_msk_set(struct dsaf_device *dsaf_dev,
 799                                      u32 chnn_num, u32 mask_set)
 800 {
 801         dsaf_write_dev(dsaf_dev,
 802                        DSAF_XGE_INT_MSK_0_REG + 0x4 * chnn_num, mask_set);
 803 }
 804
 805 static void hns_dsaf_int_ppe_msk_set(struct dsaf_device *dsaf_dev,
 806                                      u32 chnn_num, u32 msk_set)
 807 {
 808         dsaf_write_dev(dsaf_dev,
 809                        DSAF_PPE_INT_MSK_0_REG + 0x4 * chnn_num, msk_set);
 810 }
 811
 812 static void hns_dsaf_int_rocee_msk_set(struct dsaf_device *dsaf_dev,
 813                                        u32 chnn, u32 msk_set)
 814 {
 815         dsaf_write_dev(dsaf_dev,
 816                        DSAF_ROCEE_INT_MSK_0_REG + 0x4 * chnn, msk_set);
 817 }
 818
 819 static void
 820 hns_dsaf_int_tbl_msk_set(struct dsaf_device *dsaf_dev, u32 msk_set)
 821 {
 822         dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_MSK_0_REG, msk_set);
 823 }
 824
 825 /* clr dsaf exception irq*/
 826 static void hns_dsaf_int_xge_src_clr(struct dsaf_device *dsaf_dev,
 827                                      u32 chnn_num, u32 int_src)
 828 {
 829         dsaf_write_dev(dsaf_dev,
 830                        DSAF_XGE_INT_SRC_0_REG + 0x4 * chnn_num, int_src);
 831 }
 832
 833 static void hns_dsaf_int_ppe_src_clr(struct dsaf_device *dsaf_dev,
 834                                      u32 chnn, u32 int_src)
 835 {
 836         dsaf_write_dev(dsaf_dev,
 837                        DSAF_PPE_INT_SRC_0_REG + 0x4 * chnn, int_src);
 838 }
 839
 840 static void hns_dsaf_int_rocee_src_clr(struct dsaf_device *dsaf_dev,
 841                                        u32 chnn, u32 int_src)
 842 {
 843         dsaf_write_dev(dsaf_dev,
 844                        DSAF_ROCEE_INT_SRC_0_REG + 0x4 * chnn, int_src);
 845 }
 846
 847 static void hns_dsaf_int_tbl_src_clr(struct dsaf_device *dsaf_dev,
 848                                      u32 int_src)
 849 {
 850         dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_SRC_0_REG, int_src);
 851 }
 852
 853 /**
 854  * hns_dsaf_single_line_tbl_cfg - INT
 855  * @dsaf_id: dsa fabric id
 856  * @address:
 857  * @ptbl_line:
 858  */
 859 static void hns_dsaf_single_line_tbl_cfg(
 860         struct dsaf_device *dsaf_dev,
 861         u32 address, struct dsaf_tbl_line_cfg *ptbl_line)
 862 {
 863         spin_lock_bh(&dsaf_dev->tcam_lock);
 864
 865         /*Write Addr*/
 866         hns_dsaf_tbl_line_addr_cfg(dsaf_dev, address);
 867
 868         /*Write Line*/
 869         hns_dsaf_tbl_line_cfg(dsaf_dev, ptbl_line);
 870
 871         /*Write Plus*/
 872         hns_dsaf_tbl_line_pul(dsaf_dev);
 873
 874         spin_unlock_bh(&dsaf_dev->tcam_lock);
 875 }
 876
 877 /**
 878  * hns_dsaf_tcam_uc_cfg - INT
 879  * @dsaf_id: dsa fabric id
 880  * @address,
 881  * @ptbl_tcam_data,
 882  */
 883 static void hns_dsaf_tcam_uc_cfg(
 884         struct dsaf_device *dsaf_dev, u32 address,
 885         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
 886         struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
 887 {
 888         spin_lock_bh(&dsaf_dev->tcam_lock);
 889
 890         /*Write Addr*/
 891         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 892         /*Write Tcam Data*/
 893         hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
 894         /*Write Tcam Ucast*/
 895         hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, ptbl_tcam_ucast);
 896         /*Write Plus*/
 897         hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev);
 898
 899         spin_unlock_bh(&dsaf_dev->tcam_lock);
 900 }
 901
 902 /**
 903  * hns_dsaf_tcam_mc_cfg - cfg the tcam for mc
 904  * @dsaf_dev: dsa fabric device struct pointer
 905  * @address: tcam index
 906  * @ptbl_tcam_data: tcam data struct pointer
 907  * @ptbl_tcam_mcast: tcam mask struct pointer, it must be null for HNSv1
 908  */
 909 static void hns_dsaf_tcam_mc_cfg(
 910         struct dsaf_device *dsaf_dev, u32 address,
 911         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
 912         struct dsaf_tbl_tcam_data *ptbl_tcam_mask,
 913         struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
 914 {
 915         spin_lock_bh(&dsaf_dev->tcam_lock);
 916
 917         /*Write Addr*/
 918         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 919         /*Write Tcam Data*/
 920         hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
 921         /*Write Tcam Mcast*/
 922         hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, ptbl_tcam_mcast);
 923         /* Write Match Data */
 924         if (ptbl_tcam_mask)
 925                 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, ptbl_tcam_mask);
 926
 927         /* Write Puls */
 928         hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev);
 929
 930         spin_unlock_bh(&dsaf_dev->tcam_lock);
 931 }
 932
 933 /**
 934  * hns_dsaf_tcam_uc_cfg_vague - INT
 935  * @dsaf_dev: dsa fabric device struct pointer
 936  * @address,
 937  * @ptbl_tcam_data,
 938  */
 939 static void hns_dsaf_tcam_uc_cfg_vague(struct dsaf_device *dsaf_dev,
 940                                        u32 address,
 941                                        struct dsaf_tbl_tcam_data *tcam_data,
 942                                        struct dsaf_tbl_tcam_data *tcam_mask,
 943                                        struct dsaf_tbl_tcam_ucast_cfg *tcam_uc)
 944 {
 945         spin_lock_bh(&dsaf_dev->tcam_lock);
 946         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 947         hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, tcam_data);
 948         hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, tcam_uc);
 949         hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
 950         hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev);
 951
 952         /*Restore Match Data*/
 953         tcam_mask->tbl_tcam_data_high = 0xffffffff;
 954         tcam_mask->tbl_tcam_data_low = 0xffffffff;
 955         hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
 956
 957         spin_unlock_bh(&dsaf_dev->tcam_lock);
 958 }
 959
 960 /**
 961  * hns_dsaf_tcam_mc_cfg_vague - INT
 962  * @dsaf_dev: dsa fabric device struct pointer
 963  * @address,
 964  * @ptbl_tcam_data,
 965  * @ptbl_tcam_mask
 966  * @ptbl_tcam_mcast
 967  */
 968 static void hns_dsaf_tcam_mc_cfg_vague(struct dsaf_device *dsaf_dev,
 969                                        u32 address,
 970                                        struct dsaf_tbl_tcam_data *tcam_data,
 971                                        struct dsaf_tbl_tcam_data *tcam_mask,
 972                                        struct dsaf_tbl_tcam_mcast_cfg *tcam_mc)
 973 {
 974         spin_lock_bh(&dsaf_dev->tcam_lock);
 975         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 976         hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, tcam_data);
 977         hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, tcam_mc);
 978         hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
 979         hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev);
 980
 981         /*Restore Match Data*/
 982         tcam_mask->tbl_tcam_data_high = 0xffffffff;
 983         tcam_mask->tbl_tcam_data_low = 0xffffffff;
 984         hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
 985
 986         spin_unlock_bh(&dsaf_dev->tcam_lock);
 987 }
 988
 989 /**
 990  * hns_dsaf_tcam_mc_invld - INT
 991  * @dsaf_id: dsa fabric id
 992  * @address
 993  */
 994 static void hns_dsaf_tcam_mc_invld(struct dsaf_device *dsaf_dev, u32 address)
 995 {
 996         spin_lock_bh(&dsaf_dev->tcam_lock);
 997
 998         /*Write Addr*/
 999         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1000
1001         /*write tcam mcast*/
1002         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0);
1003         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0);
1004         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0);
1005         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0);
1006         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0);
1007
1008         /*Write Plus*/
1009         hns_dsaf_tbl_tcam_mcast_pul(dsaf_dev);
1010
1011         spin_unlock_bh(&dsaf_dev->tcam_lock);
1012 }
1013
1014 static void
1015 hns_dsaf_tcam_addr_get(struct dsaf_drv_tbl_tcam_key *mac_key, u8 *addr)
1016 {
1017         addr[0] = mac_key->high.bits.mac_0;
1018         addr[1] = mac_key->high.bits.mac_1;
1019         addr[2] = mac_key->high.bits.mac_2;
1020         addr[3] = mac_key->high.bits.mac_3;
1021         addr[4] = mac_key->low.bits.mac_4;
1022         addr[5] = mac_key->low.bits.mac_5;
1023 }
1024
1025 /**
1026  * hns_dsaf_tcam_uc_get - INT
1027  * @dsaf_id: dsa fabric id
1028  * @address
1029  * @ptbl_tcam_data
1030  * @ptbl_tcam_ucast
1031  */
1032 static void hns_dsaf_tcam_uc_get(
1033         struct dsaf_device *dsaf_dev, u32 address,
1034         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
1035         struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
1036 {
1037         u32 tcam_read_data0;
1038         u32 tcam_read_data4;
1039
1040         spin_lock_bh(&dsaf_dev->tcam_lock);
1041
1042         /*Write Addr*/
1043         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1044
1045         /*read tcam item puls*/
1046         hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
1047
1048         /*read tcam data*/
1049         ptbl_tcam_data->tbl_tcam_data_high
1050                 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
1051         ptbl_tcam_data->tbl_tcam_data_low
1052                 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
1053
1054         /*read tcam mcast*/
1055         tcam_read_data0 = dsaf_read_dev(dsaf_dev,
1056                                         DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
1057         tcam_read_data4 = dsaf_read_dev(dsaf_dev,
1058                                         DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
1059
1060         ptbl_tcam_ucast->tbl_ucast_item_vld
1061                 = dsaf_get_bit(tcam_read_data4,
1062                                DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1063         ptbl_tcam_ucast->tbl_ucast_old_en
1064                 = dsaf_get_bit(tcam_read_data4, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1065         ptbl_tcam_ucast->tbl_ucast_mac_discard
1066                 = dsaf_get_bit(tcam_read_data0,
1067                                DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S);
1068         ptbl_tcam_ucast->tbl_ucast_out_port
1069                 = dsaf_get_field(tcam_read_data0,
1070                                  DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
1071                                  DSAF_TBL_UCAST_CFG1_OUT_PORT_S);
1072         ptbl_tcam_ucast->tbl_ucast_dvc
1073                 = dsaf_get_bit(tcam_read_data0, DSAF_TBL_UCAST_CFG1_DVC_S);
1074
1075         spin_unlock_bh(&dsaf_dev->tcam_lock);
1076 }
1077
1078 /**
1079  * hns_dsaf_tcam_mc_get - INT
1080  * @dsaf_id: dsa fabric id
1081  * @address
1082  * @ptbl_tcam_data
1083  * @ptbl_tcam_ucast
1084  */
1085 static void hns_dsaf_tcam_mc_get(
1086         struct dsaf_device *dsaf_dev, u32 address,
1087         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
1088         struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
1089 {
1090         u32 data_tmp;
1091
1092         spin_lock_bh(&dsaf_dev->tcam_lock);
1093
1094         /*Write Addr*/
1095         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1096
1097         /*read tcam item puls*/
1098         hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
1099
1100         /*read tcam data*/
1101         ptbl_tcam_data->tbl_tcam_data_high =
1102                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
1103         ptbl_tcam_data->tbl_tcam_data_low =
1104                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
1105
1106         /*read tcam mcast*/
1107         ptbl_tcam_mcast->tbl_mcast_port_msk[0] =
1108                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
1109         ptbl_tcam_mcast->tbl_mcast_port_msk[1] =
1110                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
1111         ptbl_tcam_mcast->tbl_mcast_port_msk[2] =
1112                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
1113         ptbl_tcam_mcast->tbl_mcast_port_msk[3] =
1114                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
1115
1116         data_tmp = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
1117         ptbl_tcam_mcast->tbl_mcast_item_vld =
1118                 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1119         ptbl_tcam_mcast->tbl_mcast_old_en =
1120                 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1121         ptbl_tcam_mcast->tbl_mcast_port_msk[4] =
1122                 dsaf_get_field(data_tmp, DSAF_TBL_MCAST_CFG4_VM128_112_M,
1123                                DSAF_TBL_MCAST_CFG4_VM128_112_S);
1124
1125         spin_unlock_bh(&dsaf_dev->tcam_lock);
1126 }
1127
1128 /**
1129  * hns_dsaf_tbl_line_init - INT
1130  * @dsaf_id: dsa fabric id
1131  */
1132 static void hns_dsaf_tbl_line_init(struct dsaf_device *dsaf_dev)
1133 {
1134         u32 i;
1135         /* defaultly set all lineal mac table entry resulting discard */
1136         struct dsaf_tbl_line_cfg tbl_line[] = {{1, 0, 0} };
1137
1138         for (i = 0; i < DSAF_LINE_SUM; i++)
1139                 hns_dsaf_single_line_tbl_cfg(dsaf_dev, i, tbl_line);
1140 }
1141
1142 /**
1143  * hns_dsaf_tbl_tcam_init - INT
1144  * @dsaf_id: dsa fabric id
1145  */
1146 static void hns_dsaf_tbl_tcam_init(struct dsaf_device *dsaf_dev)
1147 {
1148         u32 i;
1149         struct dsaf_tbl_tcam_data tcam_data[] = {{0, 0} };
1150         struct dsaf_tbl_tcam_ucast_cfg tcam_ucast[] = {{0, 0, 0, 0, 0} };
1151
1152         /*tcam tbl*/
1153         for (i = 0; i < DSAF_TCAM_SUM; i++)
1154                 hns_dsaf_tcam_uc_cfg(dsaf_dev, i, tcam_data, tcam_ucast);
1155 }
1156
1157 /**
1158  * hns_dsaf_pfc_en_cfg - dsaf pfc pause cfg
1159  * @mac_cb: mac contrl block
1160  */
1161 static void hns_dsaf_pfc_en_cfg(struct dsaf_device *dsaf_dev,
1162                                 int mac_id, int tc_en)
1163 {
1164         dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, tc_en);
1165 }
1166
1167 static void hns_dsaf_set_pfc_pause(struct dsaf_device *dsaf_dev,
1168                                    int mac_id, int tx_en, int rx_en)
1169 {
1170         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1171                 if (!tx_en || !rx_en)
1172                         dev_err(dsaf_dev->dev, "dsaf v1 can not close pfc!\n");
1173
1174                 return;
1175         }
1176
1177         dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1178                          DSAF_PFC_PAUSE_RX_EN_B, !!rx_en);
1179         dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1180                          DSAF_PFC_PAUSE_TX_EN_B, !!tx_en);
1181 }
1182
1183 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1184                                  u32 en)
1185 {
1186         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1187                 if (!en) {
1188                         dev_err(dsaf_dev->dev, "dsafv1 can't close rx_pause!\n");
1189                         return -EINVAL;
1190                 }
1191         }
1192
1193         dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1194                          DSAF_MAC_PAUSE_RX_EN_B, !!en);
1195
1196         return 0;
1197 }
1198
1199 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1200                                   u32 *en)
1201 {
1202         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1203                 *en = 1;
1204         else
1205                 *en = dsaf_get_dev_bit(dsaf_dev,
1206                                        DSAF_PAUSE_CFG_REG + mac_id * 4,
1207                                        DSAF_MAC_PAUSE_RX_EN_B);
1208 }
1209
1210 /**
1211  * hns_dsaf_tbl_tcam_init - INT
1212  * @dsaf_id: dsa fabric id
1213  * @dsaf_mode
1214  */
1215 static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev)
1216 {
1217         u32 i;
1218         u32 o_dsaf_cfg;
1219         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
1220
1221         o_dsaf_cfg = dsaf_read_dev(dsaf_dev, DSAF_CFG_0_REG);
1222         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_EN_S, dsaf_dev->dsaf_en);
1223         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_TC_MODE_S, dsaf_dev->dsaf_tc_mode);
1224         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_CRC_EN_S, 0);
1225         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_MIX_MODE_S, 0);
1226         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_LOCA_ADDR_EN_S, 0);
1227         dsaf_write_dev(dsaf_dev, DSAF_CFG_0_REG, o_dsaf_cfg);
1228
1229         hns_dsaf_reg_cnt_clr_ce(dsaf_dev, 1);
1230         hns_dsaf_stp_port_type_cfg(dsaf_dev, DSAF_STP_PORT_TYPE_FORWARD);
1231
1232         /* set 22 queue per tx ppe engine, only used in switch mode */
1233         hns_dsaf_ppe_qid_cfg(dsaf_dev, DSAF_DEFAUTL_QUEUE_NUM_PER_PPE);
1234
1235         /* set promisc def queue id */
1236         hns_dsaf_mix_def_qid_cfg(dsaf_dev);
1237
1238         /* set inner loopback queue id */
1239         hns_dsaf_inner_qid_cfg(dsaf_dev);
1240
1241         /* in non switch mode, set all port to access mode */
1242         hns_dsaf_sw_port_type_cfg(dsaf_dev, DSAF_SW_PORT_TYPE_NON_VLAN);
1243
1244         /*set dsaf pfc  to 0 for parseing rx pause*/
1245         for (i = 0; i < DSAF_COMM_CHN; i++) {
1246                 hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0);
1247                 hns_dsaf_set_pfc_pause(dsaf_dev, i, is_ver1, is_ver1);
1248         }
1249
1250         /*msk and  clr exception irqs */
1251         for (i = 0; i < DSAF_COMM_CHN; i++) {
1252                 hns_dsaf_int_xge_src_clr(dsaf_dev, i, 0xfffffffful);
1253                 hns_dsaf_int_ppe_src_clr(dsaf_dev, i, 0xfffffffful);
1254                 hns_dsaf_int_rocee_src_clr(dsaf_dev, i, 0xfffffffful);
1255
1256                 hns_dsaf_int_xge_msk_set(dsaf_dev, i, 0xfffffffful);
1257                 hns_dsaf_int_ppe_msk_set(dsaf_dev, i, 0xfffffffful);
1258                 hns_dsaf_int_rocee_msk_set(dsaf_dev, i, 0xfffffffful);
1259         }
1260         hns_dsaf_int_tbl_src_clr(dsaf_dev, 0xfffffffful);
1261         hns_dsaf_int_tbl_msk_set(dsaf_dev, 0xfffffffful);
1262 }
1263
1264 /**
1265  * hns_dsaf_inode_init - INT
1266  * @dsaf_id: dsa fabric id
1267  */
1268 static void hns_dsaf_inode_init(struct dsaf_device *dsaf_dev)
1269 {
1270         u32 reg;
1271         u32 tc_cfg;
1272         u32 i;
1273
1274         if (dsaf_dev->dsaf_tc_mode == HRD_DSAF_4TC_MODE)
1275                 tc_cfg = HNS_DSAF_I4TC_CFG;
1276         else
1277                 tc_cfg = HNS_DSAF_I8TC_CFG;
1278
1279         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1280                 for (i = 0; i < DSAF_INODE_NUM; i++) {
1281                         reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1282                         dsaf_set_dev_field(dsaf_dev, reg,
1283                                            DSAF_INODE_IN_PORT_NUM_M,
1284                                            DSAF_INODE_IN_PORT_NUM_S,
1285                                            i % DSAF_XGE_NUM);
1286                 }
1287         } else {
1288                 for (i = 0; i < DSAF_PORT_TYPE_NUM; i++) {
1289                         reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1290                         dsaf_set_dev_field(dsaf_dev, reg,
1291                                            DSAF_INODE_IN_PORT_NUM_M,
1292                                            DSAF_INODE_IN_PORT_NUM_S, 0);
1293                         dsaf_set_dev_field(dsaf_dev, reg,
1294                                            DSAFV2_INODE_IN_PORT1_NUM_M,
1295                                            DSAFV2_INODE_IN_PORT1_NUM_S, 1);
1296                         dsaf_set_dev_field(dsaf_dev, reg,
1297                                            DSAFV2_INODE_IN_PORT2_NUM_M,
1298                                            DSAFV2_INODE_IN_PORT2_NUM_S, 2);
1299                         dsaf_set_dev_field(dsaf_dev, reg,
1300                                            DSAFV2_INODE_IN_PORT3_NUM_M,
1301                                            DSAFV2_INODE_IN_PORT3_NUM_S, 3);
1302                         dsaf_set_dev_field(dsaf_dev, reg,
1303                                            DSAFV2_INODE_IN_PORT4_NUM_M,
1304                                            DSAFV2_INODE_IN_PORT4_NUM_S, 4);
1305                         dsaf_set_dev_field(dsaf_dev, reg,
1306                                            DSAFV2_INODE_IN_PORT5_NUM_M,
1307                                            DSAFV2_INODE_IN_PORT5_NUM_S, 5);
1308                 }
1309         }
1310         for (i = 0; i < DSAF_INODE_NUM; i++) {
1311                 reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i;
1312                 dsaf_write_dev(dsaf_dev, reg, tc_cfg);
1313         }
1314 }
1315
1316 /**
1317  * hns_dsaf_sbm_init - INT
1318  * @dsaf_id: dsa fabric id
1319  */
1320 static int hns_dsaf_sbm_init(struct dsaf_device *dsaf_dev)
1321 {
1322         u32 flag;
1323         u32 finish_msk;
1324         u32 cnt = 0;
1325         int ret;
1326
1327         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1328                 hns_dsaf_sbm_bp_wl_cfg(dsaf_dev);
1329                 finish_msk = DSAF_SRAM_INIT_OVER_M;
1330         } else {
1331                 hns_dsafv2_sbm_bp_wl_cfg(dsaf_dev);
1332                 finish_msk = DSAFV2_SRAM_INIT_OVER_M;
1333         }
1334
1335         /* enable sbm chanel, disable sbm chanel shcut function*/
1336         hns_dsaf_sbm_cfg(dsaf_dev);
1337
1338         /* enable sbm mib */
1339         ret = hns_dsaf_sbm_cfg_mib_en(dsaf_dev);
1340         if (ret) {
1341                 dev_err(dsaf_dev->dev,
1342                         "hns_dsaf_sbm_cfg_mib_en fail,%s, ret=%d\n",
1343                         dsaf_dev->ae_dev.name, ret);
1344                 return ret;
1345         }
1346
1347         /* enable sbm initial link sram */
1348         hns_dsaf_sbm_link_sram_init_en(dsaf_dev);
1349
1350         do {
1351                 usleep_range(200, 210);/*udelay(200);*/
1352                 flag = dsaf_get_dev_field(dsaf_dev, DSAF_SRAM_INIT_OVER_0_REG,
1353                                           finish_msk, DSAF_SRAM_INIT_OVER_S);
1354                 cnt++;
1355         } while (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S) &&
1356                  cnt < DSAF_CFG_READ_CNT);
1357
1358         if (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S)) {
1359                 dev_err(dsaf_dev->dev,
1360                         "hns_dsaf_sbm_init fail %s, flag=%d, cnt=%d\n",
1361                         dsaf_dev->ae_dev.name, flag, cnt);
1362                 return -ENODEV;
1363         }
1364
1365         hns_dsaf_rocee_bp_en(dsaf_dev);
1366
1367         return 0;
1368 }
1369
1370 /**
1371  * hns_dsaf_tbl_init - INT
1372  * @dsaf_id: dsa fabric id
1373  */
1374 static void hns_dsaf_tbl_init(struct dsaf_device *dsaf_dev)
1375 {
1376         hns_dsaf_tbl_stat_en(dsaf_dev);
1377
1378         hns_dsaf_tbl_tcam_init(dsaf_dev);
1379         hns_dsaf_tbl_line_init(dsaf_dev);
1380 }
1381
1382 /**
1383  * hns_dsaf_voq_init - INT
1384  * @dsaf_id: dsa fabric id
1385  */
1386 static void hns_dsaf_voq_init(struct dsaf_device *dsaf_dev)
1387 {
1388         hns_dsaf_voq_bp_all_thrd_cfg(dsaf_dev);
1389 }
1390
1391 /**
1392  * hns_dsaf_init_hw - init dsa fabric hardware
1393  * @dsaf_dev: dsa fabric device struct pointer
1394  */
1395 static int hns_dsaf_init_hw(struct dsaf_device *dsaf_dev)
1396 {
1397         int ret;
1398
1399         dev_dbg(dsaf_dev->dev,
1400                 "hns_dsaf_init_hw begin %s !\n", dsaf_dev->ae_dev.name);
1401
1402         dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1403         mdelay(10);
1404         dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 1);
1405
1406         hns_dsaf_comm_init(dsaf_dev);
1407
1408         /*init XBAR_INODE*/
1409         hns_dsaf_inode_init(dsaf_dev);
1410
1411         /*init SBM*/
1412         ret = hns_dsaf_sbm_init(dsaf_dev);
1413         if (ret)
1414                 return ret;
1415
1416         /*init TBL*/
1417         hns_dsaf_tbl_init(dsaf_dev);
1418
1419         /*init VOQ*/
1420         hns_dsaf_voq_init(dsaf_dev);
1421
1422         return 0;
1423 }
1424
1425 /**
1426  * hns_dsaf_remove_hw - uninit dsa fabric hardware
1427  * @dsaf_dev: dsa fabric device struct pointer
1428  */
1429 static void hns_dsaf_remove_hw(struct dsaf_device *dsaf_dev)
1430 {
1431         /*reset*/
1432         dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1433 }
1434
1435 /**
1436  * hns_dsaf_init - init dsa fabric
1437  * @dsaf_dev: dsa fabric device struct pointer
1438  * retuen 0 - success , negative --fail
1439  */
1440 static int hns_dsaf_init(struct dsaf_device *dsaf_dev)
1441 {
1442         struct dsaf_drv_priv *priv =
1443             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1444         u32 i;
1445         int ret;
1446
1447         if (HNS_DSAF_IS_DEBUG(dsaf_dev))
1448                 return 0;
1449
1450         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1451                 dsaf_dev->tcam_max_num = DSAF_TCAM_SUM;
1452         else
1453                 dsaf_dev->tcam_max_num =
1454                         DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM;
1455
1456         spin_lock_init(&dsaf_dev->tcam_lock);
1457         ret = hns_dsaf_init_hw(dsaf_dev);
1458         if (ret)
1459                 return ret;
1460
1461         /* malloc mem for tcam mac key(vlan+mac) */
1462         priv->soft_mac_tbl = vzalloc(array_size(DSAF_TCAM_SUM,
1463                                                 sizeof(*priv->soft_mac_tbl)));
1464         if (!priv->soft_mac_tbl) {
1465                 ret = -ENOMEM;
1466                 goto remove_hw;
1467         }
1468
1469         /*all entry invall */
1470         for (i = 0; i < DSAF_TCAM_SUM; i++)
1471                 (priv->soft_mac_tbl + i)->index = DSAF_INVALID_ENTRY_IDX;
1472
1473         return 0;
1474
1475 remove_hw:
1476         hns_dsaf_remove_hw(dsaf_dev);
1477         return ret;
1478 }
1479
1480 /**
1481  * hns_dsaf_free - free dsa fabric
1482  * @dsaf_dev: dsa fabric device struct pointer
1483  */
1484 static void hns_dsaf_free(struct dsaf_device *dsaf_dev)
1485 {
1486         struct dsaf_drv_priv *priv =
1487             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1488
1489         hns_dsaf_remove_hw(dsaf_dev);
1490
1491         /* free all mac mem */
1492         vfree(priv->soft_mac_tbl);
1493         priv->soft_mac_tbl = NULL;
1494 }
1495
1496 /**
1497  * hns_dsaf_find_soft_mac_entry - find dsa fabric soft entry
1498  * @dsaf_dev: dsa fabric device struct pointer
1499  * @mac_key: mac entry struct pointer
1500  */
1501 static u16 hns_dsaf_find_soft_mac_entry(
1502         struct dsaf_device *dsaf_dev,
1503         struct dsaf_drv_tbl_tcam_key *mac_key)
1504 {
1505         struct dsaf_drv_priv *priv =
1506             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1507         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1508         u32 i;
1509
1510         soft_mac_entry = priv->soft_mac_tbl;
1511         for (i = 0; i < dsaf_dev->tcam_max_num; i++) {
1512                 /* invall tab entry */
1513                 if ((soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX) &&
1514                     (soft_mac_entry->tcam_key.high.val == mac_key->high.val) &&
1515                     (soft_mac_entry->tcam_key.low.val == mac_key->low.val))
1516                         /* return find result --soft index */
1517                         return soft_mac_entry->index;
1518
1519                 soft_mac_entry++;
1520         }
1521         return DSAF_INVALID_ENTRY_IDX;
1522 }
1523
1524 /**
1525  * hns_dsaf_find_empty_mac_entry - search dsa fabric soft empty-entry
1526  * @dsaf_dev: dsa fabric device struct pointer
1527  */
1528 static u16 hns_dsaf_find_empty_mac_entry(struct dsaf_device *dsaf_dev)
1529 {
1530         struct dsaf_drv_priv *priv =
1531             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1532         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1533         u32 i;
1534
1535         soft_mac_entry = priv->soft_mac_tbl;
1536         for (i = 0; i < dsaf_dev->tcam_max_num; i++) {
1537                 /* inv all entry */
1538                 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX)
1539                         /* return find result --soft index */
1540                         return i;
1541
1542                 soft_mac_entry++;
1543         }
1544         return DSAF_INVALID_ENTRY_IDX;
1545 }
1546
1547 /**
1548  * hns_dsaf_find_empty_mac_entry_reverse
1549  * search dsa fabric soft empty-entry from the end
1550  * @dsaf_dev: dsa fabric device struct pointer
1551  */
1552 static u16 hns_dsaf_find_empty_mac_entry_reverse(struct dsaf_device *dsaf_dev)
1553 {
1554         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1555         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1556         int i;
1557
1558         soft_mac_entry = priv->soft_mac_tbl + (DSAF_TCAM_SUM - 1);
1559         for (i = (DSAF_TCAM_SUM - 1); i > 0; i--) {
1560                 /* search all entry from end to start.*/
1561                 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX)
1562                         return i;
1563                 soft_mac_entry--;
1564         }
1565         return DSAF_INVALID_ENTRY_IDX;
1566 }
1567
1568 /**
1569  * hns_dsaf_set_mac_key - set mac key
1570  * @dsaf_dev: dsa fabric device struct pointer
1571  * @mac_key: tcam key pointer
1572  * @vlan_id: vlan id
1573  * @in_port_num: input port num
1574  * @addr: mac addr
1575  */
1576 static void hns_dsaf_set_mac_key(
1577         struct dsaf_device *dsaf_dev,
1578         struct dsaf_drv_tbl_tcam_key *mac_key, u16 vlan_id, u8 in_port_num,
1579         u8 *addr)
1580 {
1581         u8 port;
1582
1583         if (dsaf_dev->dsaf_mode <= DSAF_MODE_ENABLE)
1584                 /*DSAF mode : in port id fixed 0*/
1585                 port = 0;
1586         else
1587                 /*non-dsaf mode*/
1588                 port = in_port_num;
1589
1590         mac_key->high.bits.mac_0 = addr[0];
1591         mac_key->high.bits.mac_1 = addr[1];
1592         mac_key->high.bits.mac_2 = addr[2];
1593         mac_key->high.bits.mac_3 = addr[3];
1594         mac_key->low.bits.mac_4 = addr[4];
1595         mac_key->low.bits.mac_5 = addr[5];
1596         mac_key->low.bits.port_vlan = 0;
1597         dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_VLAN_M,
1598                        DSAF_TBL_TCAM_KEY_VLAN_S, vlan_id);
1599         dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_PORT_M,
1600                        DSAF_TBL_TCAM_KEY_PORT_S, port);
1601 }
1602
1603 /**
1604  * hns_dsaf_set_mac_uc_entry - set mac uc-entry
1605  * @dsaf_dev: dsa fabric device struct pointer
1606  * @mac_entry: uc-mac entry
1607  */
1608 int hns_dsaf_set_mac_uc_entry(
1609         struct dsaf_device *dsaf_dev,
1610         struct dsaf_drv_mac_single_dest_entry *mac_entry)
1611 {
1612         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1613         struct dsaf_drv_tbl_tcam_key mac_key;
1614         struct dsaf_tbl_tcam_ucast_cfg mac_data;
1615         struct dsaf_drv_priv *priv =
1616             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1617         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1618         struct dsaf_tbl_tcam_data tcam_data;
1619
1620         /* mac addr check */
1621         if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
1622             MAC_IS_BROADCAST(mac_entry->addr) ||
1623             MAC_IS_MULTICAST(mac_entry->addr)) {
1624                 dev_err(dsaf_dev->dev, "set_uc %s Mac %pM err!\n",
1625                         dsaf_dev->ae_dev.name, mac_entry->addr);
1626                 return -EINVAL;
1627         }
1628
1629         /* config key */
1630         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1631                              mac_entry->in_port_num, mac_entry->addr);
1632
1633         /* entry ie exist? */
1634         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1635         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1636                 /*if has not inv entry,find a empty entry */
1637                 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1638                 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1639                         /* has not empty,return error */
1640                         dev_err(dsaf_dev->dev,
1641                                 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1642                                 dsaf_dev->ae_dev.name,
1643                                 mac_key.high.val, mac_key.low.val);
1644                         return -EINVAL;
1645                 }
1646         }
1647
1648         dev_dbg(dsaf_dev->dev,
1649                 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1650                 dsaf_dev->ae_dev.name, mac_key.high.val,
1651                 mac_key.low.val, entry_index);
1652
1653         /* config hardware entry */
1654         mac_data.tbl_ucast_item_vld = 1;
1655         mac_data.tbl_ucast_mac_discard = 0;
1656         mac_data.tbl_ucast_old_en = 0;
1657         /* default config dvc to 0 */
1658         mac_data.tbl_ucast_dvc = 0;
1659         mac_data.tbl_ucast_out_port = mac_entry->port_num;
1660         tcam_data.tbl_tcam_data_high = mac_key.high.val;
1661         tcam_data.tbl_tcam_data_low = mac_key.low.val;
1662
1663         hns_dsaf_tcam_uc_cfg(dsaf_dev, entry_index, &tcam_data, &mac_data);
1664
1665         /* config software entry */
1666         soft_mac_entry += entry_index;
1667         soft_mac_entry->index = entry_index;
1668         soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1669         soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1670
1671         return 0;
1672 }
1673
1674 int hns_dsaf_rm_mac_addr(
1675         struct dsaf_device *dsaf_dev,
1676         struct dsaf_drv_mac_single_dest_entry *mac_entry)
1677 {
1678         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1679         struct dsaf_tbl_tcam_ucast_cfg mac_data;
1680         struct dsaf_drv_tbl_tcam_key mac_key;
1681
1682         /* mac addr check */
1683         if (!is_valid_ether_addr(mac_entry->addr)) {
1684                 dev_err(dsaf_dev->dev, "rm_uc_addr %s Mac %pM err!\n",
1685                         dsaf_dev->ae_dev.name, mac_entry->addr);
1686                 return -EINVAL;
1687         }
1688
1689         /* config key */
1690         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1691                              mac_entry->in_port_num, mac_entry->addr);
1692
1693         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1694         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1695                 /* can not find the tcam entry, return 0 */
1696                 dev_info(dsaf_dev->dev,
1697                          "rm_uc_addr no tcam, %s Mac key(%#x:%#x)\n",
1698                          dsaf_dev->ae_dev.name,
1699                          mac_key.high.val, mac_key.low.val);
1700                 return 0;
1701         }
1702
1703         dev_dbg(dsaf_dev->dev,
1704                 "rm_uc_addr, %s Mac key(%#x:%#x) entry_index%d\n",
1705                 dsaf_dev->ae_dev.name, mac_key.high.val,
1706                 mac_key.low.val, entry_index);
1707
1708         hns_dsaf_tcam_uc_get(
1709                         dsaf_dev, entry_index,
1710                         (struct dsaf_tbl_tcam_data *)&mac_key,
1711                         &mac_data);
1712
1713         /* unicast entry not used locally should not clear */
1714         if (mac_entry->port_num != mac_data.tbl_ucast_out_port)
1715                 return -EFAULT;
1716
1717         return hns_dsaf_del_mac_entry(dsaf_dev,
1718                                       mac_entry->in_vlan_id,
1719                                       mac_entry->in_port_num,
1720                                       mac_entry->addr);
1721 }
1722
1723 static void hns_dsaf_setup_mc_mask(struct dsaf_device *dsaf_dev,
1724                                    u8 port_num, u8 *mask, u8 *addr)
1725 {
1726         if (MAC_IS_BROADCAST(addr))
1727                 memset(mask, 0xff, ETH_ALEN);
1728         else
1729                 memcpy(mask, dsaf_dev->mac_cb[port_num]->mc_mask, ETH_ALEN);
1730 }
1731
1732 static void hns_dsaf_mc_mask_bit_clear(char *dst, const char *src)
1733 {
1734         u16 *a = (u16 *)dst;
1735         const u16 *b = (const u16 *)src;
1736
1737         a[0] &= b[0];
1738         a[1] &= b[1];
1739         a[2] &= b[2];
1740 }
1741
1742 /**
1743  * hns_dsaf_add_mac_mc_port - add mac mc-port
1744  * @dsaf_dev: dsa fabric device struct pointer
1745  * @mac_entry: mc-mac entry
1746  */
1747 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
1748                              struct dsaf_drv_mac_single_dest_entry *mac_entry)
1749 {
1750         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1751         struct dsaf_drv_tbl_tcam_key mac_key;
1752         struct dsaf_drv_tbl_tcam_key mask_key;
1753         struct dsaf_tbl_tcam_data *pmask_key = NULL;
1754         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1755         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1756         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1757         struct dsaf_tbl_tcam_data tcam_data;
1758         u8 mc_addr[ETH_ALEN];
1759         int mskid;
1760
1761         /*chechk mac addr */
1762         if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1763                 dev_err(dsaf_dev->dev, "set_entry failed,addr %pM!\n",
1764                         mac_entry->addr);
1765                 return -EINVAL;
1766         }
1767
1768         ether_addr_copy(mc_addr, mac_entry->addr);
1769         if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1770                 u8 mc_mask[ETH_ALEN];
1771
1772                 /* prepare for key data setting */
1773                 hns_dsaf_setup_mc_mask(dsaf_dev, mac_entry->in_port_num,
1774                                        mc_mask, mac_entry->addr);
1775                 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask);
1776
1777                 /* config key mask */
1778                 hns_dsaf_set_mac_key(dsaf_dev, &mask_key,
1779                                      0x0,
1780                                      0xff,
1781                                      mc_mask);
1782
1783                 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key);
1784         }
1785
1786         /*config key */
1787         hns_dsaf_set_mac_key(
1788                 dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1789                 mac_entry->in_port_num, mc_addr);
1790
1791         memset(&mac_data, 0, sizeof(struct dsaf_tbl_tcam_mcast_cfg));
1792
1793         /* check if the tcam is exist */
1794         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1795         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1796                 /*if hasnot , find a empty*/
1797                 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1798                 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1799                         /*if hasnot empty, error*/
1800                         dev_err(dsaf_dev->dev,
1801                                 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1802                                 dsaf_dev->ae_dev.name, mac_key.high.val,
1803                                 mac_key.low.val);
1804                         return -EINVAL;
1805                 }
1806         } else {
1807                 /* if exist, add in */
1808                 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data,
1809                                      &mac_data);
1810         }
1811
1812         /* config hardware entry */
1813         if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1814                 mskid = mac_entry->port_num;
1815         } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1816                 mskid = mac_entry->port_num -
1817                         DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1818         } else {
1819                 dev_err(dsaf_dev->dev,
1820                         "%s,pnum(%d)error,key(%#x:%#x)\n",
1821                         dsaf_dev->ae_dev.name, mac_entry->port_num,
1822                         mac_key.high.val, mac_key.low.val);
1823                 return -EINVAL;
1824         }
1825         dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 1);
1826         mac_data.tbl_mcast_old_en = 0;
1827         mac_data.tbl_mcast_item_vld = 1;
1828
1829         dev_dbg(dsaf_dev->dev,
1830                 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1831                 dsaf_dev->ae_dev.name, mac_key.high.val,
1832                 mac_key.low.val, entry_index);
1833
1834         tcam_data.tbl_tcam_data_high = mac_key.high.val;
1835         tcam_data.tbl_tcam_data_low = mac_key.low.val;
1836
1837         /* config mc entry with mask */
1838         hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index, &tcam_data,
1839                              pmask_key, &mac_data);
1840
1841         /*config software entry */
1842         soft_mac_entry += entry_index;
1843         soft_mac_entry->index = entry_index;
1844         soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1845         soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1846
1847         return 0;
1848 }
1849
1850 /**
1851  * hns_dsaf_del_mac_entry - del mac mc-port
1852  * @dsaf_dev: dsa fabric device struct pointer
1853  * @vlan_id: vlian id
1854  * @in_port_num: input port num
1855  * @addr : mac addr
1856  */
1857 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
1858                            u8 in_port_num, u8 *addr)
1859 {
1860         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1861         struct dsaf_drv_tbl_tcam_key mac_key;
1862         struct dsaf_drv_priv *priv =
1863             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1864         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1865
1866         /*check mac addr */
1867         if (MAC_IS_ALL_ZEROS(addr) || MAC_IS_BROADCAST(addr)) {
1868                 dev_err(dsaf_dev->dev, "del_entry failed,addr %pM!\n",
1869                         addr);
1870                 return -EINVAL;
1871         }
1872
1873         /*config key */
1874         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, addr);
1875
1876         /*exist ?*/
1877         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1878         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1879                 /*not exist, error */
1880                 dev_err(dsaf_dev->dev,
1881                         "del_mac_entry failed, %s Mac key(%#x:%#x)\n",
1882                         dsaf_dev->ae_dev.name,
1883                         mac_key.high.val, mac_key.low.val);
1884                 return -EINVAL;
1885         }
1886         dev_dbg(dsaf_dev->dev,
1887                 "del_mac_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1888                 dsaf_dev->ae_dev.name, mac_key.high.val,
1889                 mac_key.low.val, entry_index);
1890
1891         /*do del opt*/
1892         hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
1893
1894         /*del soft emtry */
1895         soft_mac_entry += entry_index;
1896         soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
1897
1898         return 0;
1899 }
1900
1901 /**
1902  * hns_dsaf_del_mac_mc_port - del mac mc- port
1903  * @dsaf_dev: dsa fabric device struct pointer
1904  * @mac_entry: mac entry
1905  */
1906 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
1907                              struct dsaf_drv_mac_single_dest_entry *mac_entry)
1908 {
1909         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1910         struct dsaf_drv_tbl_tcam_key mac_key;
1911         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1912         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1913         u16 vlan_id;
1914         u8 in_port_num;
1915         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1916         struct dsaf_tbl_tcam_data tcam_data;
1917         int mskid;
1918         const u8 empty_msk[sizeof(mac_data.tbl_mcast_port_msk)] = {0};
1919         struct dsaf_drv_tbl_tcam_key mask_key;
1920         struct dsaf_tbl_tcam_data *pmask_key = NULL;
1921         u8 mc_addr[ETH_ALEN];
1922
1923         if (!(void *)mac_entry) {
1924                 dev_err(dsaf_dev->dev,
1925                         "hns_dsaf_del_mac_mc_port mac_entry is NULL\n");
1926                 return -EINVAL;
1927         }
1928
1929         /*check mac addr */
1930         if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1931                 dev_err(dsaf_dev->dev, "del_port failed, addr %pM!\n",
1932                         mac_entry->addr);
1933                 return -EINVAL;
1934         }
1935
1936         /* always mask vlan_id field */
1937         ether_addr_copy(mc_addr, mac_entry->addr);
1938
1939         if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1940                 u8 mc_mask[ETH_ALEN];
1941
1942                 /* prepare for key data setting */
1943                 hns_dsaf_setup_mc_mask(dsaf_dev, mac_entry->in_port_num,
1944                                        mc_mask, mac_entry->addr);
1945                 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask);
1946
1947                 /* config key mask */
1948                 hns_dsaf_set_mac_key(dsaf_dev, &mask_key, 0x00, 0xff, mc_mask);
1949
1950                 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key);
1951         }
1952
1953         /* get key info */
1954         vlan_id = mac_entry->in_vlan_id;
1955         in_port_num = mac_entry->in_port_num;
1956
1957         /* config key */
1958         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, mc_addr);
1959
1960         /* check if the tcam entry is exist */
1961         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1962         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1963                 /*find none */
1964                 dev_err(dsaf_dev->dev,
1965                         "find_soft_mac_entry failed, %s Mac key(%#x:%#x)\n",
1966                         dsaf_dev->ae_dev.name,
1967                         mac_key.high.val, mac_key.low.val);
1968                 return -EINVAL;
1969         }
1970
1971         dev_dbg(dsaf_dev->dev,
1972                 "del_mac_mc_port, %s key(%#x:%#x) index%d\n",
1973                 dsaf_dev->ae_dev.name, mac_key.high.val,
1974                 mac_key.low.val, entry_index);
1975
1976         /* read entry */
1977         hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data, &mac_data);
1978
1979         /*del the port*/
1980         if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1981                 mskid = mac_entry->port_num;
1982         } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1983                 mskid = mac_entry->port_num -
1984                         DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1985         } else {
1986                 dev_err(dsaf_dev->dev,
1987                         "%s,pnum(%d)error,key(%#x:%#x)\n",
1988                         dsaf_dev->ae_dev.name, mac_entry->port_num,
1989                         mac_key.high.val, mac_key.low.val);
1990                 return -EINVAL;
1991         }
1992         dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 0);
1993
1994         /*check non port, do del entry */
1995         if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
1996                     sizeof(mac_data.tbl_mcast_port_msk))) {
1997                 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
1998
1999                 /* del soft entry */
2000                 soft_mac_entry += entry_index;
2001                 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
2002         } else { /* not zero, just del port, update */
2003                 tcam_data.tbl_tcam_data_high = mac_key.high.val;
2004                 tcam_data.tbl_tcam_data_low = mac_key.low.val;
2005
2006                 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index,
2007                                      &tcam_data,
2008                                      pmask_key, &mac_data);
2009         }
2010
2011         return 0;
2012 }
2013
2014 int hns_dsaf_clr_mac_mc_port(struct dsaf_device *dsaf_dev, u8 mac_id,
2015                              u8 port_num)
2016 {
2017         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
2018         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
2019         struct dsaf_tbl_tcam_mcast_cfg mac_data;
2020         int ret = 0, i;
2021
2022         if (HNS_DSAF_IS_DEBUG(dsaf_dev))
2023                 return 0;
2024
2025         for (i = 0; i < DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM; i++) {
2026                 u8 addr[ETH_ALEN];
2027                 u8 port;
2028
2029                 soft_mac_entry = priv->soft_mac_tbl + i;
2030
2031                 hns_dsaf_tcam_addr_get(&soft_mac_entry->tcam_key, addr);
2032                 port = dsaf_get_field(
2033                                 soft_mac_entry->tcam_key.low.bits.port_vlan,
2034                                 DSAF_TBL_TCAM_KEY_PORT_M,
2035                                 DSAF_TBL_TCAM_KEY_PORT_S);
2036                 /* check valid tcam mc entry */
2037                 if (soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX &&
2038                     port == mac_id &&
2039                     is_multicast_ether_addr(addr) &&
2040                     !is_broadcast_ether_addr(addr)) {
2041                         const u32 empty_msk[DSAF_PORT_MSK_NUM] = {0};
2042                         struct dsaf_drv_mac_single_dest_entry mac_entry;
2043
2044                         /* disable receiving of this multicast address for
2045                          * the VF.
2046                          */
2047                         ether_addr_copy(mac_entry.addr, addr);
2048                         mac_entry.in_vlan_id = dsaf_get_field(
2049                                 soft_mac_entry->tcam_key.low.bits.port_vlan,
2050                                 DSAF_TBL_TCAM_KEY_VLAN_M,
2051                                 DSAF_TBL_TCAM_KEY_VLAN_S);
2052                         mac_entry.in_port_num = mac_id;
2053                         mac_entry.port_num = port_num;
2054                         if (hns_dsaf_del_mac_mc_port(dsaf_dev, &mac_entry)) {
2055                                 ret = -EINVAL;
2056                                 continue;
2057                         }
2058
2059                         /* disable receiving of this multicast address for
2060                          * the mac port if all VF are disable
2061                          */
2062                         hns_dsaf_tcam_mc_get(dsaf_dev, i,
2063                                              (struct dsaf_tbl_tcam_data *)
2064                                              (&soft_mac_entry->tcam_key),
2065                                              &mac_data);
2066                         dsaf_set_bit(mac_data.tbl_mcast_port_msk[mac_id / 32],
2067                                      mac_id % 32, 0);
2068                         if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
2069                                     sizeof(u32) * DSAF_PORT_MSK_NUM)) {
2070                                 mac_entry.port_num = mac_id;
2071                                 if (hns_dsaf_del_mac_mc_port(dsaf_dev,
2072                                                              &mac_entry)) {
2073                                         ret = -EINVAL;
2074                                         continue;
2075                                 }
2076                         }
2077                 }
2078         }
2079
2080         return ret;
2081 }
2082
2083 static struct dsaf_device *hns_dsaf_alloc_dev(struct device *dev,
2084                                               size_t sizeof_priv)
2085 {
2086         struct dsaf_device *dsaf_dev;
2087
2088         dsaf_dev = devm_kzalloc(dev,
2089                                 sizeof(*dsaf_dev) + sizeof_priv, GFP_KERNEL);
2090         if (unlikely(!dsaf_dev)) {
2091                 dsaf_dev = ERR_PTR(-ENOMEM);
2092         } else {
2093                 dsaf_dev->dev = dev;
2094                 dev_set_drvdata(dev, dsaf_dev);
2095         }
2096
2097         return dsaf_dev;
2098 }
2099
2100 /**
2101  * hns_dsaf_free_dev - free dev mem
2102  * @dev: struct device pointer
2103  */
2104 static void hns_dsaf_free_dev(struct dsaf_device *dsaf_dev)
2105 {
2106         (void)dev_set_drvdata(dsaf_dev->dev, NULL);
2107 }
2108
2109 /**
2110  * dsaf_pfc_unit_cnt - set pfc unit count
2111  * @dsaf_id: dsa fabric id
2112  * @pport_rate:  value array
2113  * @pdsaf_pfc_unit_cnt:  value array
2114  */
2115 static void hns_dsaf_pfc_unit_cnt(struct dsaf_device *dsaf_dev, int  mac_id,
2116                                   enum dsaf_port_rate_mode rate)
2117 {
2118         u32 unit_cnt;
2119
2120         switch (rate) {
2121         case DSAF_PORT_RATE_10000:
2122                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2123                 break;
2124         case DSAF_PORT_RATE_1000:
2125                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2126                 break;
2127         case DSAF_PORT_RATE_2500:
2128                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2129                 break;
2130         default:
2131                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2132         }
2133
2134         dsaf_set_dev_field(dsaf_dev,
2135                            (DSAF_PFC_UNIT_CNT_0_REG + 0x4 * (u64)mac_id),
2136                            DSAF_PFC_UNINT_CNT_M, DSAF_PFC_UNINT_CNT_S,
2137                            unit_cnt);
2138 }
2139
2140 /**
2141  * dsaf_port_work_rate_cfg - fifo
2142  * @dsaf_id: dsa fabric id
2143  * @xge_ge_work_mode
2144  */
2145 static void
2146 hns_dsaf_port_work_rate_cfg(struct dsaf_device *dsaf_dev, int mac_id,
2147                             enum dsaf_port_rate_mode rate_mode)
2148 {
2149         u32 port_work_mode;
2150
2151         port_work_mode = dsaf_read_dev(
2152                 dsaf_dev, DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id);
2153
2154         if (rate_mode == DSAF_PORT_RATE_10000)
2155                 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 1);
2156         else
2157                 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 0);
2158
2159         dsaf_write_dev(dsaf_dev,
2160                        DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id,
2161                        port_work_mode);
2162
2163         hns_dsaf_pfc_unit_cnt(dsaf_dev, mac_id, rate_mode);
2164 }
2165
2166 /**
2167  * hns_dsaf_fix_mac_mode - dsaf modify mac mode
2168  * @mac_cb: mac contrl block
2169  */
2170 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb)
2171 {
2172         enum dsaf_port_rate_mode mode;
2173         struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev;
2174         int mac_id = mac_cb->mac_id;
2175
2176         if (mac_cb->mac_type != HNAE_PORT_SERVICE)
2177                 return;
2178         if (mac_cb->phy_if == PHY_INTERFACE_MODE_XGMII)
2179                 mode = DSAF_PORT_RATE_10000;
2180         else
2181                 mode = DSAF_PORT_RATE_1000;
2182
2183         hns_dsaf_port_work_rate_cfg(dsaf_dev, mac_id, mode);
2184 }
2185
2186 static u32 hns_dsaf_get_inode_prio_reg(int index)
2187 {
2188         int base_index, offset;
2189         u32 base_addr = DSAF_INODE_IN_PRIO_PAUSE_BASE_REG;
2190
2191         base_index = (index + 1) / DSAF_REG_PER_ZONE;
2192         offset = (index + 1) % DSAF_REG_PER_ZONE;
2193
2194         return base_addr + DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET * base_index +
2195                 DSAF_INODE_IN_PRIO_PAUSE_OFFSET * offset;
2196 }
2197
2198 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num)
2199 {
2200         struct dsaf_hw_stats *hw_stats
2201                 = &dsaf_dev->hw_stats[node_num];
2202         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2203         int i;
2204         u32 reg_tmp;
2205
2206         hw_stats->pad_drop += dsaf_read_dev(dsaf_dev,
2207                 DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2208         hw_stats->man_pkts += dsaf_read_dev(dsaf_dev,
2209                 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + 0x80 * (u64)node_num);
2210         hw_stats->rx_pkts += dsaf_read_dev(dsaf_dev,
2211                 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num);
2212         hw_stats->rx_pkt_id += dsaf_read_dev(dsaf_dev,
2213                 DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num);
2214
2215         reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2216                             DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2217         hw_stats->rx_pause_frame +=
2218                 dsaf_read_dev(dsaf_dev, reg_tmp + 0x80 * (u64)node_num);
2219
2220         hw_stats->release_buf_num += dsaf_read_dev(dsaf_dev,
2221                 DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num);
2222         hw_stats->sbm_drop += dsaf_read_dev(dsaf_dev,
2223                 DSAF_INODE_SBM_DROP_NUM_0_REG + 0x80 * (u64)node_num);
2224         hw_stats->crc_false += dsaf_read_dev(dsaf_dev,
2225                 DSAF_INODE_CRC_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2226         hw_stats->bp_drop += dsaf_read_dev(dsaf_dev,
2227                 DSAF_INODE_BP_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2228         hw_stats->rslt_drop += dsaf_read_dev(dsaf_dev,
2229                 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2230         hw_stats->local_addr_false += dsaf_read_dev(dsaf_dev,
2231                 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2232
2233         hw_stats->vlan_drop += dsaf_read_dev(dsaf_dev,
2234                 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 4 * (u64)node_num);
2235         hw_stats->stp_drop += dsaf_read_dev(dsaf_dev,
2236                 DSAF_INODE_IN_DATA_STP_DISC_0_REG + 4 * (u64)node_num);
2237
2238         /* pfc pause frame statistics stored in dsaf inode*/
2239         if ((node_num < DSAF_SERVICE_NW_NUM) && !is_ver1) {
2240                 for (i = 0; i < DSAF_PRIO_NR; i++) {
2241                         reg_tmp = hns_dsaf_get_inode_prio_reg(i);
2242                         hw_stats->rx_pfc[i] += dsaf_read_dev(dsaf_dev,
2243                                 reg_tmp + 0x4 * (u64)node_num);
2244                         hw_stats->tx_pfc[i] += dsaf_read_dev(dsaf_dev,
2245                                 DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG +
2246                                 DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET * i +
2247                                 0xF0 * (u64)node_num);
2248                 }
2249         }
2250         hw_stats->tx_pkts += dsaf_read_dev(dsaf_dev,
2251                 DSAF_XOD_RCVPKT_CNT_0_REG + 0x90 * (u64)node_num);
2252 }
2253
2254 /**
2255  *hns_dsaf_get_regs - dump dsaf regs
2256  *@dsaf_dev: dsaf device
2257  *@data:data for value of regs
2258  */
2259 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data)
2260 {
2261         u32 i = 0;
2262         u32 j;
2263         u32 *p = data;
2264         u32 reg_tmp;
2265         bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2266
2267         /* dsaf common registers */
2268         p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG);
2269         p[1] = dsaf_read_dev(ddev, DSAF_CFG_0_REG);
2270         p[2] = dsaf_read_dev(ddev, DSAF_ECC_ERR_INVERT_0_REG);
2271         p[3] = dsaf_read_dev(ddev, DSAF_ABNORMAL_TIMEOUT_0_REG);
2272         p[4] = dsaf_read_dev(ddev, DSAF_FSM_TIMEOUT_0_REG);
2273         p[5] = dsaf_read_dev(ddev, DSAF_DSA_REG_CNT_CLR_CE_REG);
2274         p[6] = dsaf_read_dev(ddev, DSAF_DSA_SBM_INF_FIFO_THRD_REG);
2275         p[7] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_SEL_REG);
2276         p[8] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_CNT_REG);
2277
2278         p[9] = dsaf_read_dev(ddev, DSAF_PFC_EN_0_REG + port * 4);
2279         p[10] = dsaf_read_dev(ddev, DSAF_PFC_UNIT_CNT_0_REG + port * 4);
2280         p[11] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2281         p[12] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2282         p[13] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2283         p[14] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2284         p[15] = dsaf_read_dev(ddev, DSAF_PPE_INT_MSK_0_REG + port * 4);
2285         p[16] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_MSK_0_REG + port * 4);
2286         p[17] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2287         p[18] = dsaf_read_dev(ddev, DSAF_PPE_INT_SRC_0_REG + port * 4);
2288         p[19] =  dsaf_read_dev(ddev, DSAF_ROCEE_INT_SRC_0_REG + port * 4);
2289         p[20] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2290         p[21] = dsaf_read_dev(ddev, DSAF_PPE_INT_STS_0_REG + port * 4);
2291         p[22] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_STS_0_REG + port * 4);
2292         p[23] = dsaf_read_dev(ddev, DSAF_PPE_QID_CFG_0_REG + port * 4);
2293
2294         for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2295                 p[24 + i] = dsaf_read_dev(ddev,
2296                                 DSAF_SW_PORT_TYPE_0_REG + i * 4);
2297
2298         p[32] = dsaf_read_dev(ddev, DSAF_MIX_DEF_QID_0_REG + port * 4);
2299
2300         for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2301                 p[33 + i] = dsaf_read_dev(ddev,
2302                                 DSAF_PORT_DEF_VLAN_0_REG + i * 4);
2303
2304         for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++)
2305                 p[41 + i] = dsaf_read_dev(ddev,
2306                                 DSAF_VM_DEF_VLAN_0_REG + i * 4);
2307
2308         /* dsaf inode registers */
2309         p[170] = dsaf_read_dev(ddev, DSAF_INODE_CUT_THROUGH_CFG_0_REG);
2310
2311         p[171] = dsaf_read_dev(ddev,
2312                         DSAF_INODE_ECC_ERR_ADDR_0_REG + port * 0x80);
2313
2314         for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2315                 j = i * DSAF_COMM_CHN + port;
2316                 p[172 + i] = dsaf_read_dev(ddev,
2317                                 DSAF_INODE_IN_PORT_NUM_0_REG + j * 0x80);
2318                 p[175 + i] = dsaf_read_dev(ddev,
2319                                 DSAF_INODE_PRI_TC_CFG_0_REG + j * 0x80);
2320                 p[178 + i] = dsaf_read_dev(ddev,
2321                                 DSAF_INODE_BP_STATUS_0_REG + j * 0x80);
2322                 p[181 + i] = dsaf_read_dev(ddev,
2323                                 DSAF_INODE_PAD_DISCARD_NUM_0_REG + j * 0x80);
2324                 p[184 + i] = dsaf_read_dev(ddev,
2325                                 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + j * 0x80);
2326                 p[187 + i] = dsaf_read_dev(ddev,
2327                                 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80);
2328                 p[190 + i] = dsaf_read_dev(ddev,
2329                                 DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80);
2330                 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2331                                     DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2332                 p[193 + i] = dsaf_read_dev(ddev, reg_tmp + j * 0x80);
2333                 p[196 + i] = dsaf_read_dev(ddev,
2334                                 DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80);
2335                 p[199 + i] = dsaf_read_dev(ddev,
2336                                 DSAF_INODE_SBM_DROP_NUM_0_REG + j * 0x80);
2337                 p[202 + i] = dsaf_read_dev(ddev,
2338                                 DSAF_INODE_CRC_FALSE_NUM_0_REG + j * 0x80);
2339                 p[205 + i] = dsaf_read_dev(ddev,
2340                                 DSAF_INODE_BP_DISCARD_NUM_0_REG + j * 0x80);
2341                 p[208 + i] = dsaf_read_dev(ddev,
2342                                 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + j * 0x80);
2343                 p[211 + i] = dsaf_read_dev(ddev,
2344                         DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + j * 0x80);
2345                 p[214 + i] = dsaf_read_dev(ddev,
2346                                 DSAF_INODE_VOQ_OVER_NUM_0_REG + j * 0x80);
2347                 p[217 + i] = dsaf_read_dev(ddev,
2348                                 DSAF_INODE_BD_SAVE_STATUS_0_REG + j * 4);
2349                 p[220 + i] = dsaf_read_dev(ddev,
2350                                 DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4);
2351                 p[223 + i] = dsaf_read_dev(ddev,
2352                                 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4);
2353                 p[226 + i] = dsaf_read_dev(ddev,
2354                                 DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4);
2355         }
2356
2357         p[229] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4);
2358
2359         for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2360                 j = i * DSAF_COMM_CHN + port;
2361                 p[230 + i] = dsaf_read_dev(ddev,
2362                                 DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4);
2363         }
2364
2365         p[233] = dsaf_read_dev(ddev,
2366                 DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 0x80);
2367
2368         /* dsaf inode registers */
2369         for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) {
2370                 j = i * DSAF_COMM_CHN + port;
2371                 p[234 + i] = dsaf_read_dev(ddev,
2372                                 DSAF_SBM_CFG_REG_0_REG + j * 0x80);
2373                 p[237 + i] = dsaf_read_dev(ddev,
2374                                 DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80);
2375                 p[240 + i] = dsaf_read_dev(ddev,
2376                                 DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80);
2377                 p[243 + i] = dsaf_read_dev(ddev,
2378                                 DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80);
2379                 p[246 + i] = dsaf_read_dev(ddev,
2380                                 DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80);
2381                 p[249 + i] = dsaf_read_dev(ddev,
2382                                 DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80);
2383                 p[252 + i] = dsaf_read_dev(ddev,
2384                                 DSAF_SBM_BP_CNT_0_0_REG + j * 0x80);
2385                 p[255 + i] = dsaf_read_dev(ddev,
2386                                 DSAF_SBM_BP_CNT_1_0_REG + j * 0x80);
2387                 p[258 + i] = dsaf_read_dev(ddev,
2388                                 DSAF_SBM_BP_CNT_2_0_REG + j * 0x80);
2389                 p[261 + i] = dsaf_read_dev(ddev,
2390                                 DSAF_SBM_BP_CNT_3_0_REG + j * 0x80);
2391                 p[264 + i] = dsaf_read_dev(ddev,
2392                                 DSAF_SBM_INER_ST_0_REG + j * 0x80);
2393                 p[267 + i] = dsaf_read_dev(ddev,
2394                                 DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80);
2395                 p[270 + i] = dsaf_read_dev(ddev,
2396                                 DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80);
2397                 p[273 + i] = dsaf_read_dev(ddev,
2398                                 DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80);
2399                 p[276 + i] = dsaf_read_dev(ddev,
2400                                 DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80);
2401                 p[279 + i] = dsaf_read_dev(ddev,
2402                                 DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80);
2403                 p[282 + i] = dsaf_read_dev(ddev,
2404                                 DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80);
2405                 p[285 + i] = dsaf_read_dev(ddev,
2406                                 DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80);
2407                 p[288 + i] = dsaf_read_dev(ddev,
2408                                 DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80);
2409                 p[291 + i] = dsaf_read_dev(ddev,
2410                                 DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80);
2411                 p[294 + i] = dsaf_read_dev(ddev,
2412                                 DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80);
2413                 p[297 + i] = dsaf_read_dev(ddev,
2414                                 DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80);
2415                 p[300 + i] = dsaf_read_dev(ddev,
2416                                 DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80);
2417                 p[303 + i] = dsaf_read_dev(ddev,
2418                                 DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80);
2419                 p[306 + i] = dsaf_read_dev(ddev,
2420                                 DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80);
2421                 p[309 + i] = dsaf_read_dev(ddev,
2422                                 DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80);
2423                 p[312 + i] = dsaf_read_dev(ddev,
2424                                 DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80);
2425         }
2426
2427         /* dsaf onode registers */
2428         for (i = 0; i < DSAF_XOD_NUM; i++) {
2429                 p[315 + i] = dsaf_read_dev(ddev,
2430                                 DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90);
2431                 p[323 + i] = dsaf_read_dev(ddev,
2432                                 DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90);
2433                 p[331 + i] = dsaf_read_dev(ddev,
2434                                 DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90);
2435                 p[339 + i] = dsaf_read_dev(ddev,
2436                                 DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90);
2437                 p[347 + i] = dsaf_read_dev(ddev,
2438                                 DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90);
2439                 p[355 + i] = dsaf_read_dev(ddev,
2440                                 DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90);
2441         }
2442
2443         p[363] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90);
2444         p[364] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90);
2445         p[365] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90);
2446
2447         for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) {
2448                 j = i * DSAF_COMM_CHN + port;
2449                 p[366 + i] = dsaf_read_dev(ddev,
2450                                 DSAF_XOD_GNT_L_0_REG + j * 0x90);
2451                 p[369 + i] = dsaf_read_dev(ddev,
2452                                 DSAF_XOD_GNT_H_0_REG + j * 0x90);
2453                 p[372 + i] = dsaf_read_dev(ddev,
2454                                 DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90);
2455                 p[375 + i] = dsaf_read_dev(ddev,
2456                                 DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90);
2457                 p[378 + i] = dsaf_read_dev(ddev,
2458                                 DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90);
2459                 p[381 + i] = dsaf_read_dev(ddev,
2460                                 DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90);
2461                 p[384 + i] = dsaf_read_dev(ddev,
2462                                 DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90);
2463                 p[387 + i] = dsaf_read_dev(ddev,
2464                                 DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90);
2465                 p[390 + i] = dsaf_read_dev(ddev,
2466                                 DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90);
2467                 p[393 + i] = dsaf_read_dev(ddev,
2468                                 DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90);
2469         }
2470
2471         p[396] = dsaf_read_dev(ddev,
2472                 DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90);
2473         p[397] = dsaf_read_dev(ddev,
2474                 DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90);
2475         p[398] = dsaf_read_dev(ddev,
2476                 DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90);
2477         p[399] = dsaf_read_dev(ddev,
2478                 DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90);
2479         p[400] = dsaf_read_dev(ddev,
2480                 DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90);
2481         p[401] = dsaf_read_dev(ddev,
2482                 DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90);
2483         p[402] = dsaf_read_dev(ddev,
2484                 DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90);
2485         p[403] = dsaf_read_dev(ddev,
2486                 DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90);
2487         p[404] = dsaf_read_dev(ddev,
2488                 DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90);
2489         p[405] = dsaf_read_dev(ddev,
2490                 DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90);
2491         p[406] = dsaf_read_dev(ddev,
2492                 DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90);
2493         p[407] = dsaf_read_dev(ddev,
2494                 DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90);
2495         p[408] = dsaf_read_dev(ddev,
2496                 DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90);
2497
2498         /* dsaf voq registers */
2499         for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) {
2500                 j = (i * DSAF_COMM_CHN + port) * 0x90;
2501                 p[409 + i] = dsaf_read_dev(ddev,
2502                         DSAF_VOQ_ECC_INVERT_EN_0_REG + j);
2503                 p[412 + i] = dsaf_read_dev(ddev,
2504                         DSAF_VOQ_SRAM_PKT_NUM_0_REG + j);
2505                 p[415 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j);
2506                 p[418 + i] = dsaf_read_dev(ddev,
2507                         DSAF_VOQ_OUT_PKT_NUM_0_REG + j);
2508                 p[421 + i] = dsaf_read_dev(ddev,
2509                         DSAF_VOQ_ECC_ERR_ADDR_0_REG + j);
2510                 p[424 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j);
2511                 p[427 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j);
2512                 p[430 + i] = dsaf_read_dev(ddev,
2513                         DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j);
2514                 p[433 + i] = dsaf_read_dev(ddev,
2515                         DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j);
2516                 p[436 + i] = dsaf_read_dev(ddev,
2517                         DSAF_VOQ_PPE_XOD_REQ_0_REG + j);
2518                 p[439 + i] = dsaf_read_dev(ddev,
2519                         DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j);
2520                 p[442 + i] = dsaf_read_dev(ddev,
2521                         DSAF_VOQ_BP_ALL_THRD_0_REG + j);
2522         }
2523
2524         /* dsaf tbl registers */
2525         p[445] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG);
2526         p[446] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG);
2527         p[447] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG);
2528         p[448] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG);
2529         p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG);
2530         p[450] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG);
2531         p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG);
2532         p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG);
2533         p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
2534         p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG);
2535         p[455] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG);
2536         p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG);
2537         p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG);
2538         p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
2539         p[459] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG);
2540         p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
2541         p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
2542         p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
2543         p[463] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
2544         p[464] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
2545         p[465] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
2546         p[466] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
2547         p[467] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG);
2548
2549         for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
2550                 j = i * 0x8;
2551                 p[468 + 2 * i] = dsaf_read_dev(ddev,
2552                         DSAF_TBL_DA0_MIS_INFO1_0_REG + j);
2553                 p[469 + 2 * i] = dsaf_read_dev(ddev,
2554                         DSAF_TBL_DA0_MIS_INFO0_0_REG + j);
2555         }
2556
2557         p[484] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG);
2558         p[485] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG);
2559         p[486] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG);
2560         p[487] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG);
2561         p[488] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG);
2562         p[489] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG);
2563         p[490] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG);
2564         p[491] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG);
2565         p[492] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG);
2566         p[493] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG);
2567         p[494] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG);
2568         p[495] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG);
2569
2570         /* dsaf other registers */
2571         p[496] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4);
2572         p[497] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4);
2573         p[498] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4);
2574         p[499] = dsaf_read_dev(ddev,
2575                 DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4);
2576         p[500] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4);
2577         p[501] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4);
2578
2579         if (!is_ver1)
2580                 p[502] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4);
2581
2582         /* mark end of dsaf regs */
2583         for (i = 503; i < 504; i++)
2584                 p[i] = 0xdddddddd;
2585 }
2586
2587 static char *hns_dsaf_get_node_stats_strings(char *data, int node,
2588                                              struct dsaf_device *dsaf_dev)
2589 {
2590         char *buff = data;
2591         int i;
2592         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2593
2594         snprintf(buff, ETH_GSTRING_LEN, "innod%d_pad_drop_pkts", node);
2595         buff += ETH_GSTRING_LEN;
2596         snprintf(buff, ETH_GSTRING_LEN, "innod%d_manage_pkts", node);
2597         buff += ETH_GSTRING_LEN;
2598         snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkts", node);
2599         buff += ETH_GSTRING_LEN;
2600         snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkt_id", node);
2601         buff += ETH_GSTRING_LEN;
2602         snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pause_frame", node);
2603         buff += ETH_GSTRING_LEN;
2604         snprintf(buff, ETH_GSTRING_LEN, "innod%d_release_buf_num", node);
2605         buff += ETH_GSTRING_LEN;
2606         snprintf(buff, ETH_GSTRING_LEN, "innod%d_sbm_drop_pkts", node);
2607         buff += ETH_GSTRING_LEN;
2608         snprintf(buff, ETH_GSTRING_LEN, "innod%d_crc_false_pkts", node);
2609         buff += ETH_GSTRING_LEN;
2610         snprintf(buff, ETH_GSTRING_LEN, "innod%d_bp_drop_pkts", node);
2611         buff += ETH_GSTRING_LEN;
2612         snprintf(buff, ETH_GSTRING_LEN, "innod%d_lookup_rslt_drop_pkts", node);
2613         buff += ETH_GSTRING_LEN;
2614         snprintf(buff, ETH_GSTRING_LEN, "innod%d_local_rslt_fail_pkts", node);
2615         buff += ETH_GSTRING_LEN;
2616         snprintf(buff, ETH_GSTRING_LEN, "innod%d_vlan_drop_pkts", node);
2617         buff += ETH_GSTRING_LEN;
2618         snprintf(buff, ETH_GSTRING_LEN, "innod%d_stp_drop_pkts", node);
2619         buff += ETH_GSTRING_LEN;
2620         if (node < DSAF_SERVICE_NW_NUM && !is_ver1) {
2621                 for (i = 0; i < DSAF_PRIO_NR; i++) {
2622                         snprintf(buff + 0 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2623                                  ETH_GSTRING_LEN, "inod%d_pfc_prio%d_pkts",
2624                                  node, i);
2625                         snprintf(buff + 1 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2626                                  ETH_GSTRING_LEN, "onod%d_pfc_prio%d_pkts",
2627                                  node, i);
2628                         buff += ETH_GSTRING_LEN;
2629                 }
2630                 buff += 1 * DSAF_PRIO_NR * ETH_GSTRING_LEN;
2631         }
2632         snprintf(buff, ETH_GSTRING_LEN, "onnod%d_tx_pkts", node);
2633         buff += ETH_GSTRING_LEN;
2634
2635         return buff;
2636 }
2637
2638 static u64 *hns_dsaf_get_node_stats(struct dsaf_device *ddev, u64 *data,
2639                                     int node_num)
2640 {
2641         u64 *p = data;
2642         int i;
2643         struct dsaf_hw_stats *hw_stats = &ddev->hw_stats[node_num];
2644         bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2645
2646         p[0] = hw_stats->pad_drop;
2647         p[1] = hw_stats->man_pkts;
2648         p[2] = hw_stats->rx_pkts;
2649         p[3] = hw_stats->rx_pkt_id;
2650         p[4] = hw_stats->rx_pause_frame;
2651         p[5] = hw_stats->release_buf_num;
2652         p[6] = hw_stats->sbm_drop;
2653         p[7] = hw_stats->crc_false;
2654         p[8] = hw_stats->bp_drop;
2655         p[9] = hw_stats->rslt_drop;
2656         p[10] = hw_stats->local_addr_false;
2657         p[11] = hw_stats->vlan_drop;
2658         p[12] = hw_stats->stp_drop;
2659         if (node_num < DSAF_SERVICE_NW_NUM && !is_ver1) {
2660                 for (i = 0; i < DSAF_PRIO_NR; i++) {
2661                         p[13 + i + 0 * DSAF_PRIO_NR] = hw_stats->rx_pfc[i];
2662                         p[13 + i + 1 * DSAF_PRIO_NR] = hw_stats->tx_pfc[i];
2663                 }
2664                 p[29] = hw_stats->tx_pkts;
2665                 return &p[30];
2666         }
2667
2668         p[13] = hw_stats->tx_pkts;
2669         return &p[14];
2670 }
2671
2672 /**
2673  *hns_dsaf_get_stats - get dsaf statistic
2674  *@ddev: dsaf device
2675  *@data:statistic value
2676  *@port: port num
2677  */
2678 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port)
2679 {
2680         u64 *p = data;
2681         int node_num = port;
2682
2683         /* for ge/xge node info */
2684         p = hns_dsaf_get_node_stats(ddev, p, node_num);
2685
2686         /* for ppe node info */
2687         node_num = port + DSAF_PPE_INODE_BASE;
2688         (void)hns_dsaf_get_node_stats(ddev, p, node_num);
2689 }
2690
2691 /**
2692  *hns_dsaf_get_sset_count - get dsaf string set count
2693  *@stringset: type of values in data
2694  *return dsaf string name count
2695  */
2696 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset)
2697 {
2698         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2699
2700         if (stringset == ETH_SS_STATS) {
2701                 if (is_ver1)
2702                         return DSAF_STATIC_NUM;
2703                 else
2704                         return DSAF_V2_STATIC_NUM;
2705         }
2706         return 0;
2707 }
2708
2709 /**
2710  *hns_dsaf_get_strings - get dsaf string set
2711  *@stringset:srting set index
2712  *@data:strings name value
2713  *@port:port index
2714  */
2715 void hns_dsaf_get_strings(int stringset, u8 *data, int port,
2716                           struct dsaf_device *dsaf_dev)
2717 {
2718         char *buff = (char *)data;
2719         int node = port;
2720
2721         if (stringset != ETH_SS_STATS)
2722                 return;
2723
2724         /* for ge/xge node info */
2725         buff = hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2726
2727         /* for ppe node info */
2728         node = port + DSAF_PPE_INODE_BASE;
2729         (void)hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2730 }
2731
2732 /**
2733  *hns_dsaf_get_sset_count - get dsaf regs count
2734  *return dsaf regs count
2735  */
2736 int hns_dsaf_get_regs_count(void)
2737 {
2738         return DSAF_DUMP_REGS_NUM;
2739 }
2740
2741 static int hns_dsaf_get_port_id(u8 port)
2742 {
2743         if (port < DSAF_SERVICE_NW_NUM)
2744                 return port;
2745
2746         if (port >= DSAF_BASE_INNER_PORT_NUM)
2747                 return port - DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
2748
2749         return -EINVAL;
2750 }
2751
2752 static void set_promisc_tcam_enable(struct dsaf_device *dsaf_dev, u32 port)
2753 {
2754         struct dsaf_tbl_tcam_ucast_cfg tbl_tcam_ucast = {0, 1, 0, 0, 0x80};
2755         struct dsaf_tbl_tcam_data tbl_tcam_data_mc = {0x01000000, port};
2756         struct dsaf_tbl_tcam_data tbl_tcam_mask_uc = {0x01000000, 0xf};
2757         struct dsaf_tbl_tcam_mcast_cfg tbl_tcam_mcast = {0, 0, {0} };
2758         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
2759         struct dsaf_tbl_tcam_data tbl_tcam_data_uc = {0, port};
2760         struct dsaf_drv_mac_single_dest_entry mask_entry;
2761         struct dsaf_drv_tbl_tcam_key temp_key, mask_key;
2762         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
2763         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
2764         struct dsaf_drv_tbl_tcam_key mac_key;
2765         struct hns_mac_cb *mac_cb;
2766         u8 addr[ETH_ALEN] = {0};
2767         u8 port_num;
2768         int mskid;
2769
2770         /* promisc use vague table match with vlanid = 0 & macaddr = 0 */
2771         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr);
2772         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
2773         if (entry_index != DSAF_INVALID_ENTRY_IDX)
2774                 return;
2775
2776         /* put promisc tcam entry in the end. */
2777         /* 1. set promisc unicast vague tcam entry. */
2778         entry_index = hns_dsaf_find_empty_mac_entry_reverse(dsaf_dev);
2779         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
2780                 dev_err(dsaf_dev->dev,
2781                         "enable uc promisc failed (port:%#x)\n",
2782                         port);
2783                 return;
2784         }
2785
2786         mac_cb = dsaf_dev->mac_cb[port];
2787         (void)hns_mac_get_inner_port_num(mac_cb, 0, &port_num);
2788         tbl_tcam_ucast.tbl_ucast_out_port = port_num;
2789
2790         /* config uc vague table */
2791         hns_dsaf_tcam_uc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_uc,
2792                                    &tbl_tcam_mask_uc, &tbl_tcam_ucast);
2793
2794         /* update software entry */
2795         soft_mac_entry = priv->soft_mac_tbl;
2796         soft_mac_entry += entry_index;
2797         soft_mac_entry->index = entry_index;
2798         soft_mac_entry->tcam_key.high.val = mac_key.high.val;
2799         soft_mac_entry->tcam_key.low.val = mac_key.low.val;
2800         /* step back to the START for mc. */
2801         soft_mac_entry = priv->soft_mac_tbl;
2802
2803         /* 2. set promisc multicast vague tcam entry. */
2804         entry_index = hns_dsaf_find_empty_mac_entry_reverse(dsaf_dev);
2805         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
2806                 dev_err(dsaf_dev->dev,
2807                         "enable mc promisc failed (port:%#x)\n",
2808                         port);
2809                 return;
2810         }
2811
2812         memset(&mask_entry, 0x0, sizeof(mask_entry));
2813         memset(&mask_key, 0x0, sizeof(mask_key));
2814         memset(&temp_key, 0x0, sizeof(temp_key));
2815         mask_entry.addr[0] = 0x01;
2816         hns_dsaf_set_mac_key(dsaf_dev, &mask_key, mask_entry.in_vlan_id,
2817                              0xf, mask_entry.addr);
2818         tbl_tcam_mcast.tbl_mcast_item_vld = 1;
2819         tbl_tcam_mcast.tbl_mcast_old_en = 0;
2820
2821         /* set MAC port to handle multicast */
2822         mskid = hns_dsaf_get_port_id(port);
2823         if (mskid == -EINVAL) {
2824                 dev_err(dsaf_dev->dev, "%s,pnum(%d)error,key(%#x:%#x)\n",
2825                         dsaf_dev->ae_dev.name, port,
2826                         mask_key.high.val, mask_key.low.val);
2827                 return;
2828         }
2829         dsaf_set_bit(tbl_tcam_mcast.tbl_mcast_port_msk[mskid / 32],
2830                      mskid % 32, 1);
2831
2832         /* set pool bit map to handle multicast */
2833         mskid = hns_dsaf_get_port_id(port_num);
2834         if (mskid == -EINVAL) {
2835                 dev_err(dsaf_dev->dev,
2836                         "%s, pool bit map pnum(%d)error,key(%#x:%#x)\n",
2837                         dsaf_dev->ae_dev.name, port_num,
2838                         mask_key.high.val, mask_key.low.val);
2839                 return;
2840         }
2841         dsaf_set_bit(tbl_tcam_mcast.tbl_mcast_port_msk[mskid / 32],
2842                      mskid % 32, 1);
2843
2844         memcpy(&temp_key, &mask_key, sizeof(mask_key));
2845         hns_dsaf_tcam_mc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_mc,
2846                                    (struct dsaf_tbl_tcam_data *)(&mask_key),
2847                                    &tbl_tcam_mcast);
2848
2849         /* update software entry */
2850         soft_mac_entry += entry_index;
2851         soft_mac_entry->index = entry_index;
2852         soft_mac_entry->tcam_key.high.val = temp_key.high.val;
2853         soft_mac_entry->tcam_key.low.val = temp_key.low.val;
2854 }
2855
2856 static void set_promisc_tcam_disable(struct dsaf_device *dsaf_dev, u32 port)
2857 {
2858         struct dsaf_tbl_tcam_data tbl_tcam_data_mc = {0x01000000, port};
2859         struct dsaf_tbl_tcam_ucast_cfg tbl_tcam_ucast = {0, 0, 0, 0, 0};
2860         struct dsaf_tbl_tcam_mcast_cfg tbl_tcam_mcast = {0, 0, {0} };
2861         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
2862         struct dsaf_tbl_tcam_data tbl_tcam_data_uc = {0, 0};
2863         struct dsaf_tbl_tcam_data tbl_tcam_mask = {0, 0};
2864         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
2865         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
2866         struct dsaf_drv_tbl_tcam_key mac_key;
2867         u8 addr[ETH_ALEN] = {0};
2868
2869         /* 1. delete uc vague tcam entry. */
2870         /* promisc use vague table match with vlanid = 0 & macaddr = 0 */
2871         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr);
2872         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
2873
2874         if (entry_index == DSAF_INVALID_ENTRY_IDX)
2875                 return;
2876
2877         /* config uc vague table */
2878         hns_dsaf_tcam_uc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_uc,
2879                                    &tbl_tcam_mask, &tbl_tcam_ucast);
2880         /* update soft management table. */
2881         soft_mac_entry = priv->soft_mac_tbl;
2882         soft_mac_entry += entry_index;
2883         soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
2884         /* step back to the START for mc. */
2885         soft_mac_entry = priv->soft_mac_tbl;
2886
2887         /* 2. delete mc vague tcam entry. */
2888         addr[0] = 0x01;
2889         memset(&mac_key, 0x0, sizeof(mac_key));
2890         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr);
2891         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
2892
2893         if (entry_index == DSAF_INVALID_ENTRY_IDX)
2894                 return;
2895
2896         /* config mc vague table */
2897         hns_dsaf_tcam_mc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_mc,
2898                                    &tbl_tcam_mask, &tbl_tcam_mcast);
2899         /* update soft management table. */
2900         soft_mac_entry += entry_index;
2901         soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
2902 }
2903
2904 /* Reserve the last TCAM entry for promisc support */
2905 void hns_dsaf_set_promisc_tcam(struct dsaf_device *dsaf_dev,
2906                                u32 port, bool enable)
2907 {
2908         if (enable)
2909                 set_promisc_tcam_enable(dsaf_dev, port);
2910         else
2911                 set_promisc_tcam_disable(dsaf_dev, port);
2912 }
2913
2914 int hns_dsaf_wait_pkt_clean(struct dsaf_device *dsaf_dev, int port)
2915 {
2916         u32 val, val_tmp;
2917         int wait_cnt;
2918
2919         if (port >= DSAF_SERVICE_NW_NUM)
2920                 return 0;
2921
2922         wait_cnt = 0;
2923         while (wait_cnt++ < HNS_MAX_WAIT_CNT) {
2924                 val = dsaf_read_dev(dsaf_dev, DSAF_VOQ_IN_PKT_NUM_0_REG +
2925                         (port + DSAF_XGE_NUM) * 0x40);
2926                 val_tmp = dsaf_read_dev(dsaf_dev, DSAF_VOQ_OUT_PKT_NUM_0_REG +
2927                         (port + DSAF_XGE_NUM) * 0x40);
2928                 if (val == val_tmp)
2929                         break;
2930
2931                 usleep_range(100, 200);
2932         }
2933
2934         if (wait_cnt >= HNS_MAX_WAIT_CNT) {
2935                 dev_err(dsaf_dev->dev, "hns dsaf clean wait timeout(%u - %u).\n",
2936                         val, val_tmp);
2937                 return -EBUSY;
2938         }
2939
2940         return 0;
2941 }
2942
2943 /**
2944  * dsaf_probe - probo dsaf dev
2945  * @pdev: dasf platform device
2946  * retuen 0 - success , negative --fail
2947  */
2948 static int hns_dsaf_probe(struct platform_device *pdev)
2949 {
2950         struct dsaf_device *dsaf_dev;
2951         int ret;
2952
2953         dsaf_dev = hns_dsaf_alloc_dev(&pdev->dev, sizeof(struct dsaf_drv_priv));
2954         if (IS_ERR(dsaf_dev)) {
2955                 ret = PTR_ERR(dsaf_dev);
2956                 dev_err(&pdev->dev,
2957                         "dsaf_probe dsaf_alloc_dev failed, ret = %#x!\n", ret);
2958                 return ret;
2959         }
2960
2961         ret = hns_dsaf_get_cfg(dsaf_dev);
2962         if (ret)
2963                 goto free_dev;
2964
2965         ret = hns_dsaf_init(dsaf_dev);
2966         if (ret)
2967                 goto free_dev;
2968
2969         ret = hns_mac_init(dsaf_dev);
2970         if (ret)
2971                 goto uninit_dsaf;
2972
2973         ret = hns_ppe_init(dsaf_dev);
2974         if (ret)
2975                 goto uninit_mac;
2976
2977         ret = hns_dsaf_ae_init(dsaf_dev);
2978         if (ret)
2979                 goto uninit_ppe;
2980
2981         return 0;
2982
2983 uninit_ppe:
2984         hns_ppe_uninit(dsaf_dev);
2985
2986 uninit_mac:
2987         hns_mac_uninit(dsaf_dev);
2988
2989 uninit_dsaf:
2990         hns_dsaf_free(dsaf_dev);
2991
2992 free_dev:
2993         hns_dsaf_free_dev(dsaf_dev);
2994
2995         return ret;
2996 }
2997
2998 /**
2999  * dsaf_remove - remove dsaf dev
3000  * @pdev: dasf platform device
3001  */
3002 static int hns_dsaf_remove(struct platform_device *pdev)
3003 {
3004         struct dsaf_device *dsaf_dev = dev_get_drvdata(&pdev->dev);
3005
3006         hns_dsaf_ae_uninit(dsaf_dev);
3007
3008         hns_ppe_uninit(dsaf_dev);
3009
3010         hns_mac_uninit(dsaf_dev);
3011
3012         hns_dsaf_free(dsaf_dev);
3013
3014         hns_dsaf_free_dev(dsaf_dev);
3015
3016         return 0;
3017 }
3018
3019 static const struct of_device_id g_dsaf_match[] = {
3020         {.compatible = "hisilicon,hns-dsaf-v1"},
3021         {.compatible = "hisilicon,hns-dsaf-v2"},
3022         {}
3023 };
3024 MODULE_DEVICE_TABLE(of, g_dsaf_match);
3025
3026 static struct platform_driver g_dsaf_driver = {
3027         .probe = hns_dsaf_probe,
3028         .remove = hns_dsaf_remove,
3029         .driver = {
3030                 .name = DSAF_DRV_NAME,
3031                 .of_match_table = g_dsaf_match,
3032                 .acpi_match_table = hns_dsaf_acpi_match,
3033         },
3034 };
3035
3036 module_platform_driver(g_dsaf_driver);
3037
3038 /**
3039  * hns_dsaf_roce_reset - reset dsaf and roce
3040  * @dsaf_fwnode: Pointer to framework node for the dasf
3041  * @enable: false - request reset , true - drop reset
3042  * retuen 0 - success , negative -fail
3043  */
3044 int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset)
3045 {
3046         struct dsaf_device *dsaf_dev;
3047         struct platform_device *pdev;
3048         u32 mp;
3049         u32 sl;
3050         u32 credit;
3051         int i;
3052         static const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
3053                 {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
3054                 {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
3055                 {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
3056                 {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
3057                 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
3058                 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
3059                 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
3060                 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
3061         };
3062         static const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
3063                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
3064                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
3065                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
3066                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
3067                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
3068                 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
3069                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
3070                 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
3071         };
3072
3073         /* find the platform device corresponding to fwnode */
3074         if (is_of_node(dsaf_fwnode)) {
3075                 pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
3076         } else if (is_acpi_device_node(dsaf_fwnode)) {
3077                 pdev = hns_dsaf_find_platform_device(dsaf_fwnode);
3078         } else {
3079                 pr_err("fwnode is neither OF or ACPI type\n");
3080                 return -EINVAL;
3081         }
3082
3083         /* check if we were a success in fetching pdev */
3084         if (!pdev) {
3085                 pr_err("couldn't find platform device for node\n");
3086                 return -ENODEV;
3087         }
3088
3089         /* retrieve the dsaf_device from the driver data */
3090         dsaf_dev = dev_get_drvdata(&pdev->dev);
3091         if (!dsaf_dev) {
3092                 dev_err(&pdev->dev, "dsaf_dev is NULL\n");
3093                 put_device(&pdev->dev);
3094                 return -ENODEV;
3095         }
3096
3097         /* now, make sure we are running on compatible SoC */
3098         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
3099                 dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n",
3100                         dsaf_dev->ae_dev.name);
3101                 put_device(&pdev->dev);
3102                 return -ENODEV;
3103         }
3104
3105         /* do reset or de-reset according to the flag */
3106         if (!dereset) {
3107                 /* reset rocee-channels in dsaf and rocee */
3108                 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
3109                                                       false);
3110                 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, false);
3111         } else {
3112                 /* configure dsaf tx roce correspond to port map and sl map */
3113                 mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);
3114                 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
3115                         dsaf_set_field(mp, 7 << i * 3, i * 3,
3116                                        port_map[i][DSAF_ROCE_6PORT_MODE]);
3117                 dsaf_set_field(mp, 3 << i * 3, i * 3, 0);
3118                 dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp);
3119
3120                 sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG);
3121                 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
3122                         dsaf_set_field(sl, 3 << i * 2, i * 2,
3123                                        sl_map[i][DSAF_ROCE_6PORT_MODE]);
3124                 dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);
3125
3126                 /* de-reset rocee-channels in dsaf and rocee */
3127                 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
3128                                                       true);
3129                 msleep(SRST_TIME_INTERVAL);
3130                 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, true);
3131
3132                 /* enable dsaf channel rocee credit */
3133                 credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG);
3134                 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0);
3135                 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
3136
3137                 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1);
3138                 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
3139         }
3140
3141         put_device(&pdev->dev);
3142
3143         return 0;
3144 }
3145 EXPORT_SYMBOL(hns_dsaf_roce_reset);
3146
3147 MODULE_LICENSE("GPL");
3148 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3149 MODULE_DESCRIPTION("HNS DSAF driver");
3150 MODULE_VERSION(DSAF_MOD_VERSION);