drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/delay.h>
  74 #include <linux/netdevice.h>
  75 #include <linux/etherdevice.h>
  76 #include <linux/skbuff.h>
  77 #include <linux/if_vlan.h>
  78 #include <linux/spinlock.h>
  79 #include <linux/mm.h>
  80 #include <linux/of_address.h>
  81 #include <linux/of_irq.h>
  82 #include <linux/of_mdio.h>
  83 #include <linux/of_platform.h>
  84 #include <linux/ip.h>
  85 #include <linux/tcp.h>
  86 #include <linux/udp.h>
  87 #include <linux/in.h>
  88 #include <linux/net_tstamp.h>
  89
  90 #include <asm/io.h>
  91 #ifdef CONFIG_PPC
  92 #include <asm/reg.h>
  93 #include <asm/mpc85xx.h>
  94 #endif
  95 #include <asm/irq.h>
  96 #include <asm/uaccess.h>
  97 #include <linux/module.h>
  98 #include <linux/dma-mapping.h>
  99 #include <linux/crc32.h>
 100 #include <linux/mii.h>
 101 #include <linux/phy.h>
 102 #include <linux/phy_fixed.h>
 103 #include <linux/of.h>
 104 #include <linux/of_net.h>
 105 #include <linux/of_address.h>
 106 #include <linux/of_irq.h>
 107
 108 #include "gianfar.h"
 109
 110 #define TX_TIMEOUT      (5*HZ)
 111
 112 const char gfar_driver_version[] = "2.0";
 113
 114 static int gfar_enet_open(struct net_device *dev);
 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 116 static void gfar_reset_task(struct work_struct *work);
 117 static void gfar_timeout(struct net_device *dev);
 118 static int gfar_close(struct net_device *dev);
 119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
 120                                 int alloc_cnt);
 121 static int gfar_set_mac_address(struct net_device *dev);
 122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 123 static irqreturn_t gfar_error(int irq, void *dev_id);
 124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 126 static void adjust_link(struct net_device *dev);
 127 static noinline void gfar_update_link_state(struct gfar_private *priv);
 128 static int init_phy(struct net_device *dev);
 129 static int gfar_probe(struct platform_device *ofdev);
 130 static int gfar_remove(struct platform_device *ofdev);
 131 static void free_skb_resources(struct gfar_private *priv);
 132 static void gfar_set_multi(struct net_device *dev);
 133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 134 static void gfar_configure_serdes(struct net_device *dev);
 135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
 136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
 137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
 138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
 139 #ifdef CONFIG_NET_POLL_CONTROLLER
 140 static void gfar_netpoll(struct net_device *dev);
 141 #endif
 142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 144 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
 145 static void gfar_halt_nodisable(struct gfar_private *priv);
 146 static void gfar_clear_exact_match(struct net_device *dev);
 147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 148                                   const u8 *addr);
 149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 150
 151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 153 MODULE_LICENSE("GPL");
 154
 155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 156                             dma_addr_t buf)
 157 {
 158         u32 lstatus;
 159
 160         bdp->bufPtr = cpu_to_be32(buf);
 161
 162         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 163         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 164                 lstatus |= BD_LFLAG(RXBD_WRAP);
 165
 166         gfar_wmb();
 167
 168         bdp->lstatus = cpu_to_be32(lstatus);
 169 }
 170
 171 static void gfar_init_bds(struct net_device *ndev)
 172 {
 173         struct gfar_private *priv = netdev_priv(ndev);
 174         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 175         struct gfar_priv_tx_q *tx_queue = NULL;
 176         struct gfar_priv_rx_q *rx_queue = NULL;
 177         struct txbd8 *txbdp;
 178         u32 __iomem *rfbptr;
 179         int i, j;
 180
 181         for (i = 0; i < priv->num_tx_queues; i++) {
 182                 tx_queue = priv->tx_queue[i];
 183                 /* Initialize some variables in our dev structure */
 184                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 185                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 186                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 187                 tx_queue->skb_curtx = 0;
 188                 tx_queue->skb_dirtytx = 0;
 189
 190                 /* Initialize Transmit Descriptor Ring */
 191                 txbdp = tx_queue->tx_bd_base;
 192                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 193                         txbdp->lstatus = 0;
 194                         txbdp->bufPtr = 0;
 195                         txbdp++;
 196                 }
 197
 198                 /* Set the last descriptor in the ring to indicate wrap */
 199                 txbdp--;
 200                 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
 201                                             TXBD_WRAP);
 202         }
 203
 204         rfbptr = &regs->rfbptr0;
 205         for (i = 0; i < priv->num_rx_queues; i++) {
 206                 rx_queue = priv->rx_queue[i];
 207
 208                 rx_queue->next_to_clean = 0;
 209                 rx_queue->next_to_use = 0;
 210                 rx_queue->next_to_alloc = 0;
 211
 212                 /* make sure next_to_clean != next_to_use after this
 213                  * by leaving at least 1 unused descriptor
 214                  */
 215                 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
 216
 217                 rx_queue->rfbptr = rfbptr;
 218                 rfbptr += 2;
 219         }
 220 }
 221
 222 static int gfar_alloc_skb_resources(struct net_device *ndev)
 223 {
 224         void *vaddr;
 225         dma_addr_t addr;
 226         int i, j;
 227         struct gfar_private *priv = netdev_priv(ndev);
 228         struct device *dev = priv->dev;
 229         struct gfar_priv_tx_q *tx_queue = NULL;
 230         struct gfar_priv_rx_q *rx_queue = NULL;
 231
 232         priv->total_tx_ring_size = 0;
 233         for (i = 0; i < priv->num_tx_queues; i++)
 234                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 235
 236         priv->total_rx_ring_size = 0;
 237         for (i = 0; i < priv->num_rx_queues; i++)
 238                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 239
 240         /* Allocate memory for the buffer descriptors */
 241         vaddr = dma_alloc_coherent(dev,
 242                                    (priv->total_tx_ring_size *
 243                                     sizeof(struct txbd8)) +
 244                                    (priv->total_rx_ring_size *
 245                                     sizeof(struct rxbd8)),
 246                                    &addr, GFP_KERNEL);
 247         if (!vaddr)
 248                 return -ENOMEM;
 249
 250         for (i = 0; i < priv->num_tx_queues; i++) {
 251                 tx_queue = priv->tx_queue[i];
 252                 tx_queue->tx_bd_base = vaddr;
 253                 tx_queue->tx_bd_dma_base = addr;
 254                 tx_queue->dev = ndev;
 255                 /* enet DMA only understands physical addresses */
 256                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 257                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 258         }
 259
 260         /* Start the rx descriptor ring where the tx ring leaves off */
 261         for (i = 0; i < priv->num_rx_queues; i++) {
 262                 rx_queue = priv->rx_queue[i];
 263                 rx_queue->rx_bd_base = vaddr;
 264                 rx_queue->rx_bd_dma_base = addr;
 265                 rx_queue->ndev = ndev;
 266                 rx_queue->dev = dev;
 267                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 268                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 269         }
 270
 271         /* Setup the skbuff rings */
 272         for (i = 0; i < priv->num_tx_queues; i++) {
 273                 tx_queue = priv->tx_queue[i];
 274                 tx_queue->tx_skbuff =
 275                         kmalloc_array(tx_queue->tx_ring_size,
 276                                       sizeof(*tx_queue->tx_skbuff),
 277                                       GFP_KERNEL);
 278                 if (!tx_queue->tx_skbuff)
 279                         goto cleanup;
 280
 281                 for (j = 0; j < tx_queue->tx_ring_size; j++)
 282                         tx_queue->tx_skbuff[j] = NULL;
 283         }
 284
 285         for (i = 0; i < priv->num_rx_queues; i++) {
 286                 rx_queue = priv->rx_queue[i];
 287                 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
 288                                             sizeof(*rx_queue->rx_buff),
 289                                             GFP_KERNEL);
 290                 if (!rx_queue->rx_buff)
 291                         goto cleanup;
 292         }
 293
 294         gfar_init_bds(ndev);
 295
 296         return 0;
 297
 298 cleanup:
 299         free_skb_resources(priv);
 300         return -ENOMEM;
 301 }
 302
 303 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 304 {
 305         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 306         u32 __iomem *baddr;
 307         int i;
 308
 309         baddr = &regs->tbase0;
 310         for (i = 0; i < priv->num_tx_queues; i++) {
 311                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 312                 baddr += 2;
 313         }
 314
 315         baddr = &regs->rbase0;
 316         for (i = 0; i < priv->num_rx_queues; i++) {
 317                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 318                 baddr += 2;
 319         }
 320 }
 321
 322 static void gfar_init_rqprm(struct gfar_private *priv)
 323 {
 324         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 325         u32 __iomem *baddr;
 326         int i;
 327
 328         baddr = &regs->rqprm0;
 329         for (i = 0; i < priv->num_rx_queues; i++) {
 330                 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
 331                            (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
 332                 baddr++;
 333         }
 334 }
 335
 336 static void gfar_rx_offload_en(struct gfar_private *priv)
 337 {
 338         /* set this when rx hw offload (TOE) functions are being used */
 339         priv->uses_rxfcb = 0;
 340
 341         if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
 342                 priv->uses_rxfcb = 1;
 343
 344         if (priv->hwts_rx_en || priv->rx_filer_enable)
 345                 priv->uses_rxfcb = 1;
 346 }
 347
 348 static void gfar_mac_rx_config(struct gfar_private *priv)
 349 {
 350         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 351         u32 rctrl = 0;
 352
 353         if (priv->rx_filer_enable) {
 354                 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
 355                 /* Program the RIR0 reg with the required distribution */
 356                 if (priv->poll_mode == GFAR_SQ_POLLING)
 357                         gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
 358                 else /* GFAR_MQ_POLLING */
 359                         gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
 360         }
 361
 362         /* Restore PROMISC mode */
 363         if (priv->ndev->flags & IFF_PROMISC)
 364                 rctrl |= RCTRL_PROM;
 365
 366         if (priv->ndev->features & NETIF_F_RXCSUM)
 367                 rctrl |= RCTRL_CHECKSUMMING;
 368
 369         if (priv->extended_hash)
 370                 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Enable HW time stamping if requested from user space */
 378         if (priv->hwts_rx_en)
 379                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 380
 381         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
 382                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 383
 384         /* Clear the LFC bit */
 385         gfar_write(&regs->rctrl, rctrl);
 386         /* Init flow control threshold values */
 387         gfar_init_rqprm(priv);
 388         gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
 389         rctrl |= RCTRL_LFC;
 390
 391         /* Init rctrl based on our settings */
 392         gfar_write(&regs->rctrl, rctrl);
 393 }
 394
 395 static void gfar_mac_tx_config(struct gfar_private *priv)
 396 {
 397         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 398         u32 tctrl = 0;
 399
 400         if (priv->ndev->features & NETIF_F_IP_CSUM)
 401                 tctrl |= TCTRL_INIT_CSUM;
 402
 403         if (priv->prio_sched_en)
 404                 tctrl |= TCTRL_TXSCHED_PRIO;
 405         else {
 406                 tctrl |= TCTRL_TXSCHED_WRRS;
 407                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 408                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 409         }
 410
 411         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
 412                 tctrl |= TCTRL_VLINS;
 413
 414         gfar_write(&regs->tctrl, tctrl);
 415 }
 416
 417 static void gfar_configure_coalescing(struct gfar_private *priv,
 418                                unsigned long tx_mask, unsigned long rx_mask)
 419 {
 420         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 421         u32 __iomem *baddr;
 422
 423         if (priv->mode == MQ_MG_MODE) {
 424                 int i = 0;
 425
 426                 baddr = &regs->txic0;
 427                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
 428                         gfar_write(baddr + i, 0);
 429                         if (likely(priv->tx_queue[i]->txcoalescing))
 430                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
 431                 }
 432
 433                 baddr = &regs->rxic0;
 434                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
 435                         gfar_write(baddr + i, 0);
 436                         if (likely(priv->rx_queue[i]->rxcoalescing))
 437                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
 438                 }
 439         } else {
 440                 /* Backward compatible case -- even if we enable
 441                  * multiple queues, there's only single reg to program
 442                  */
 443                 gfar_write(&regs->txic, 0);
 444                 if (likely(priv->tx_queue[0]->txcoalescing))
 445                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
 446
 447                 gfar_write(&regs->rxic, 0);
 448                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
 449                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
 450         }
 451 }
 452
 453 void gfar_configure_coalescing_all(struct gfar_private *priv)
 454 {
 455         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 456 }
 457
 458 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 459 {
 460         struct gfar_private *priv = netdev_priv(dev);
 461         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 462         unsigned long tx_packets = 0, tx_bytes = 0;
 463         int i;
 464
 465         for (i = 0; i < priv->num_rx_queues; i++) {
 466                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 467                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 468                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 469         }
 470
 471         dev->stats.rx_packets = rx_packets;
 472         dev->stats.rx_bytes   = rx_bytes;
 473         dev->stats.rx_dropped = rx_dropped;
 474
 475         for (i = 0; i < priv->num_tx_queues; i++) {
 476                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 477                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 478         }
 479
 480         dev->stats.tx_bytes   = tx_bytes;
 481         dev->stats.tx_packets = tx_packets;
 482
 483         return &dev->stats;
 484 }
 485
 486 static int gfar_set_mac_addr(struct net_device *dev, void *p)
 487 {
 488         eth_mac_addr(dev, p);
 489
 490         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
 491
 492         return 0;
 493 }
 494
 495 static const struct net_device_ops gfar_netdev_ops = {
 496         .ndo_open = gfar_enet_open,
 497         .ndo_start_xmit = gfar_start_xmit,
 498         .ndo_stop = gfar_close,
 499         .ndo_change_mtu = gfar_change_mtu,
 500         .ndo_set_features = gfar_set_features,
 501         .ndo_set_rx_mode = gfar_set_multi,
 502         .ndo_tx_timeout = gfar_timeout,
 503         .ndo_do_ioctl = gfar_ioctl,
 504         .ndo_get_stats = gfar_get_stats,
 505         .ndo_set_mac_address = gfar_set_mac_addr,
 506         .ndo_validate_addr = eth_validate_addr,
 507 #ifdef CONFIG_NET_POLL_CONTROLLER
 508         .ndo_poll_controller = gfar_netpoll,
 509 #endif
 510 };
 511
 512 static void gfar_ints_disable(struct gfar_private *priv)
 513 {
 514         int i;
 515         for (i = 0; i < priv->num_grps; i++) {
 516                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 517                 /* Clear IEVENT */
 518                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 519
 520                 /* Initialize IMASK */
 521                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 522         }
 523 }
 524
 525 static void gfar_ints_enable(struct gfar_private *priv)
 526 {
 527         int i;
 528         for (i = 0; i < priv->num_grps; i++) {
 529                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 530                 /* Unmask the interrupts we look for */
 531                 gfar_write(&regs->imask, IMASK_DEFAULT);
 532         }
 533 }
 534
 535 static int gfar_alloc_tx_queues(struct gfar_private *priv)
 536 {
 537         int i;
 538
 539         for (i = 0; i < priv->num_tx_queues; i++) {
 540                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 541                                             GFP_KERNEL);
 542                 if (!priv->tx_queue[i])
 543                         return -ENOMEM;
 544
 545                 priv->tx_queue[i]->tx_skbuff = NULL;
 546                 priv->tx_queue[i]->qindex = i;
 547                 priv->tx_queue[i]->dev = priv->ndev;
 548                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 549         }
 550         return 0;
 551 }
 552
 553 static int gfar_alloc_rx_queues(struct gfar_private *priv)
 554 {
 555         int i;
 556
 557         for (i = 0; i < priv->num_rx_queues; i++) {
 558                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 559                                             GFP_KERNEL);
 560                 if (!priv->rx_queue[i])
 561                         return -ENOMEM;
 562
 563                 priv->rx_queue[i]->qindex = i;
 564                 priv->rx_queue[i]->ndev = priv->ndev;
 565         }
 566         return 0;
 567 }
 568
 569 static void gfar_free_tx_queues(struct gfar_private *priv)
 570 {
 571         int i;
 572
 573         for (i = 0; i < priv->num_tx_queues; i++)
 574                 kfree(priv->tx_queue[i]);
 575 }
 576
 577 static void gfar_free_rx_queues(struct gfar_private *priv)
 578 {
 579         int i;
 580
 581         for (i = 0; i < priv->num_rx_queues; i++)
 582                 kfree(priv->rx_queue[i]);
 583 }
 584
 585 static void unmap_group_regs(struct gfar_private *priv)
 586 {
 587         int i;
 588
 589         for (i = 0; i < MAXGROUPS; i++)
 590                 if (priv->gfargrp[i].regs)
 591                         iounmap(priv->gfargrp[i].regs);
 592 }
 593
 594 static void free_gfar_dev(struct gfar_private *priv)
 595 {
 596         int i, j;
 597
 598         for (i = 0; i < priv->num_grps; i++)
 599                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 600                         kfree(priv->gfargrp[i].irqinfo[j]);
 601                         priv->gfargrp[i].irqinfo[j] = NULL;
 602                 }
 603
 604         free_netdev(priv->ndev);
 605 }
 606
 607 static void disable_napi(struct gfar_private *priv)
 608 {
 609         int i;
 610
 611         for (i = 0; i < priv->num_grps; i++) {
 612                 napi_disable(&priv->gfargrp[i].napi_rx);
 613                 napi_disable(&priv->gfargrp[i].napi_tx);
 614         }
 615 }
 616
 617 static void enable_napi(struct gfar_private *priv)
 618 {
 619         int i;
 620
 621         for (i = 0; i < priv->num_grps; i++) {
 622                 napi_enable(&priv->gfargrp[i].napi_rx);
 623                 napi_enable(&priv->gfargrp[i].napi_tx);
 624         }
 625 }
 626
 627 static int gfar_parse_group(struct device_node *np,
 628                             struct gfar_private *priv, const char *model)
 629 {
 630         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 631         int i;
 632
 633         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 634                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 635                                           GFP_KERNEL);
 636                 if (!grp->irqinfo[i])
 637                         return -ENOMEM;
 638         }
 639
 640         grp->regs = of_iomap(np, 0);
 641         if (!grp->regs)
 642                 return -ENOMEM;
 643
 644         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 645
 646         /* If we aren't the FEC we have multiple interrupts */
 647         if (model && strcasecmp(model, "FEC")) {
 648                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 649                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 650                 if (!gfar_irq(grp, TX)->irq ||
 651                     !gfar_irq(grp, RX)->irq ||
 652                     !gfar_irq(grp, ER)->irq)
 653                         return -EINVAL;
 654         }
 655
 656         grp->priv = priv;
 657         spin_lock_init(&grp->grplock);
 658         if (priv->mode == MQ_MG_MODE) {
 659                 u32 rxq_mask, txq_mask;
 660                 int ret;
 661
 662                 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 663                 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 664
 665                 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
 666                 if (!ret) {
 667                         grp->rx_bit_map = rxq_mask ?
 668                         rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 669                 }
 670
 671                 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
 672                 if (!ret) {
 673                         grp->tx_bit_map = txq_mask ?
 674                         txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 675                 }
 676
 677                 if (priv->poll_mode == GFAR_SQ_POLLING) {
 678                         /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
 679                         grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 680                         grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 681                 }
 682         } else {
 683                 grp->rx_bit_map = 0xFF;
 684                 grp->tx_bit_map = 0xFF;
 685         }
 686
 687         /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
 688          * right to left, so we need to revert the 8 bits to get the q index
 689          */
 690         grp->rx_bit_map = bitrev8(grp->rx_bit_map);
 691         grp->tx_bit_map = bitrev8(grp->tx_bit_map);
 692
 693         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 694          * also assign queues to groups
 695          */
 696         for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
 697                 if (!grp->rx_queue)
 698                         grp->rx_queue = priv->rx_queue[i];
 699                 grp->num_rx_queues++;
 700                 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
 701                 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 702                 priv->rx_queue[i]->grp = grp;
 703         }
 704
 705         for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
 706                 if (!grp->tx_queue)
 707                         grp->tx_queue = priv->tx_queue[i];
 708                 grp->num_tx_queues++;
 709                 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
 710                 priv->tqueue |= (TQUEUE_EN0 >> i);
 711                 priv->tx_queue[i]->grp = grp;
 712         }
 713
 714         priv->num_grps++;
 715
 716         return 0;
 717 }
 718
 719 static int gfar_of_group_count(struct device_node *np)
 720 {
 721         struct device_node *child;
 722         int num = 0;
 723
 724         for_each_available_child_of_node(np, child)
 725                 if (!of_node_cmp(child->name, "queue-group"))
 726                         num++;
 727
 728         return num;
 729 }
 730
 731 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 732 {
 733         const char *model;
 734         const char *ctype;
 735         const void *mac_addr;
 736         int err = 0, i;
 737         struct net_device *dev = NULL;
 738         struct gfar_private *priv = NULL;
 739         struct device_node *np = ofdev->dev.of_node;
 740         struct device_node *child = NULL;
 741         u32 stash_len = 0;
 742         u32 stash_idx = 0;
 743         unsigned int num_tx_qs, num_rx_qs;
 744         unsigned short mode, poll_mode;
 745
 746         if (!np)
 747                 return -ENODEV;
 748
 749         if (of_device_is_compatible(np, "fsl,etsec2")) {
 750                 mode = MQ_MG_MODE;
 751                 poll_mode = GFAR_SQ_POLLING;
 752         } else {
 753                 mode = SQ_SG_MODE;
 754                 poll_mode = GFAR_SQ_POLLING;
 755         }
 756
 757         if (mode == SQ_SG_MODE) {
 758                 num_tx_qs = 1;
 759                 num_rx_qs = 1;
 760         } else { /* MQ_MG_MODE */
 761                 /* get the actual number of supported groups */
 762                 unsigned int num_grps = gfar_of_group_count(np);
 763
 764                 if (num_grps == 0 || num_grps > MAXGROUPS) {
 765                         dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
 766                                 num_grps);
 767                         pr_err("Cannot do alloc_etherdev, aborting\n");
 768                         return -EINVAL;
 769                 }
 770
 771                 if (poll_mode == GFAR_SQ_POLLING) {
 772                         num_tx_qs = num_grps; /* one txq per int group */
 773                         num_rx_qs = num_grps; /* one rxq per int group */
 774                 } else { /* GFAR_MQ_POLLING */
 775                         u32 tx_queues, rx_queues;
 776                         int ret;
 777
 778                         /* parse the num of HW tx and rx queues */
 779                         ret = of_property_read_u32(np, "fsl,num_tx_queues",
 780                                                    &tx_queues);
 781                         num_tx_qs = ret ? 1 : tx_queues;
 782
 783                         ret = of_property_read_u32(np, "fsl,num_rx_queues",
 784                                                    &rx_queues);
 785                         num_rx_qs = ret ? 1 : rx_queues;
 786                 }
 787         }
 788
 789         if (num_tx_qs > MAX_TX_QS) {
 790                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 791                        num_tx_qs, MAX_TX_QS);
 792                 pr_err("Cannot do alloc_etherdev, aborting\n");
 793                 return -EINVAL;
 794         }
 795
 796         if (num_rx_qs > MAX_RX_QS) {
 797                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 798                        num_rx_qs, MAX_RX_QS);
 799                 pr_err("Cannot do alloc_etherdev, aborting\n");
 800                 return -EINVAL;
 801         }
 802
 803         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 804         dev = *pdev;
 805         if (NULL == dev)
 806                 return -ENOMEM;
 807
 808         priv = netdev_priv(dev);
 809         priv->ndev = dev;
 810
 811         priv->mode = mode;
 812         priv->poll_mode = poll_mode;
 813
 814         priv->num_tx_queues = num_tx_qs;
 815         netif_set_real_num_rx_queues(dev, num_rx_qs);
 816         priv->num_rx_queues = num_rx_qs;
 817
 818         err = gfar_alloc_tx_queues(priv);
 819         if (err)
 820                 goto tx_alloc_failed;
 821
 822         err = gfar_alloc_rx_queues(priv);
 823         if (err)
 824                 goto rx_alloc_failed;
 825
 826         err = of_property_read_string(np, "model", &model);
 827         if (err) {
 828                 pr_err("Device model property missing, aborting\n");
 829                 goto rx_alloc_failed;
 830         }
 831
 832         /* Init Rx queue filer rule set linked list */
 833         INIT_LIST_HEAD(&priv->rx_list.list);
 834         priv->rx_list.count = 0;
 835         mutex_init(&priv->rx_queue_access);
 836
 837         for (i = 0; i < MAXGROUPS; i++)
 838                 priv->gfargrp[i].regs = NULL;
 839
 840         /* Parse and initialize group specific information */
 841         if (priv->mode == MQ_MG_MODE) {
 842                 for_each_available_child_of_node(np, child) {
 843                         if (of_node_cmp(child->name, "queue-group"))
 844                                 continue;
 845
 846                         err = gfar_parse_group(child, priv, model);
 847                         if (err)
 848                                 goto err_grp_init;
 849                 }
 850         } else { /* SQ_SG_MODE */
 851                 err = gfar_parse_group(np, priv, model);
 852                 if (err)
 853                         goto err_grp_init;
 854         }
 855
 856         if (of_property_read_bool(np, "bd-stash")) {
 857                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 858                 priv->bd_stash_en = 1;
 859         }
 860
 861         err = of_property_read_u32(np, "rx-stash-len", &stash_len);
 862
 863         if (err == 0)
 864                 priv->rx_stash_size = stash_len;
 865
 866         err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
 867
 868         if (err == 0)
 869                 priv->rx_stash_index = stash_idx;
 870
 871         if (stash_len || stash_idx)
 872                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 873
 874         mac_addr = of_get_mac_address(np);
 875
 876         if (mac_addr)
 877                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 878
 879         if (model && !strcasecmp(model, "TSEC"))
 880                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 881                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 882                                      FSL_GIANFAR_DEV_HAS_RMON |
 883                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 884
 885         if (model && !strcasecmp(model, "eTSEC"))
 886                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 887                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 888                                      FSL_GIANFAR_DEV_HAS_RMON |
 889                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 890                                      FSL_GIANFAR_DEV_HAS_CSUM |
 891                                      FSL_GIANFAR_DEV_HAS_VLAN |
 892                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 893                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 894                                      FSL_GIANFAR_DEV_HAS_TIMER |
 895                                      FSL_GIANFAR_DEV_HAS_RX_FILER;
 896
 897         err = of_property_read_string(np, "phy-connection-type", &ctype);
 898
 899         /* We only care about rgmii-id.  The rest are autodetected */
 900         if (err == 0 && !strcmp(ctype, "rgmii-id"))
 901                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 902         else
 903                 priv->interface = PHY_INTERFACE_MODE_MII;
 904
 905         if (of_find_property(np, "fsl,magic-packet", NULL))
 906                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 907
 908         if (of_get_property(np, "fsl,wake-on-filer", NULL))
 909                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
 910
 911         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 912
 913         /* In the case of a fixed PHY, the DT node associated
 914          * to the PHY is the Ethernet MAC DT node.
 915          */
 916         if (!priv->phy_node && of_phy_is_fixed_link(np)) {
 917                 err = of_phy_register_fixed_link(np);
 918                 if (err)
 919                         goto err_grp_init;
 920
 921                 priv->phy_node = of_node_get(np);
 922         }
 923
 924         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 925         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 926
 927         return 0;
 928
 929 err_grp_init:
 930         unmap_group_regs(priv);
 931 rx_alloc_failed:
 932         gfar_free_rx_queues(priv);
 933 tx_alloc_failed:
 934         gfar_free_tx_queues(priv);
 935         free_gfar_dev(priv);
 936         return err;
 937 }
 938
 939 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 940 {
 941         struct hwtstamp_config config;
 942         struct gfar_private *priv = netdev_priv(netdev);
 943
 944         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 945                 return -EFAULT;
 946
 947         /* reserved for future extensions */
 948         if (config.flags)
 949                 return -EINVAL;
 950
 951         switch (config.tx_type) {
 952         case HWTSTAMP_TX_OFF:
 953                 priv->hwts_tx_en = 0;
 954                 break;
 955         case HWTSTAMP_TX_ON:
 956                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 957                         return -ERANGE;
 958                 priv->hwts_tx_en = 1;
 959                 break;
 960         default:
 961                 return -ERANGE;
 962         }
 963
 964         switch (config.rx_filter) {
 965         case HWTSTAMP_FILTER_NONE:
 966                 if (priv->hwts_rx_en) {
 967                         priv->hwts_rx_en = 0;
 968                         reset_gfar(netdev);
 969                 }
 970                 break;
 971         default:
 972                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 973                         return -ERANGE;
 974                 if (!priv->hwts_rx_en) {
 975                         priv->hwts_rx_en = 1;
 976                         reset_gfar(netdev);
 977                 }
 978                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 979                 break;
 980         }
 981
 982         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 983                 -EFAULT : 0;
 984 }
 985
 986 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
 987 {
 988         struct hwtstamp_config config;
 989         struct gfar_private *priv = netdev_priv(netdev);
 990
 991         config.flags = 0;
 992         config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 993         config.rx_filter = (priv->hwts_rx_en ?
 994                             HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
 995
 996         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 997                 -EFAULT : 0;
 998 }
 999
1000 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1001 {
1002         struct gfar_private *priv = netdev_priv(dev);
1003
1004         if (!netif_running(dev))
1005                 return -EINVAL;
1006
1007         if (cmd == SIOCSHWTSTAMP)
1008                 return gfar_hwtstamp_set(dev, rq);
1009         if (cmd == SIOCGHWTSTAMP)
1010                 return gfar_hwtstamp_get(dev, rq);
1011
1012         if (!priv->phydev)
1013                 return -ENODEV;
1014
1015         return phy_mii_ioctl(priv->phydev, rq, cmd);
1016 }
1017
1018 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1019                                    u32 class)
1020 {
1021         u32 rqfpr = FPR_FILER_MASK;
1022         u32 rqfcr = 0x0;
1023
1024         rqfar--;
1025         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1026         priv->ftp_rqfpr[rqfar] = rqfpr;
1027         priv->ftp_rqfcr[rqfar] = rqfcr;
1028         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1029
1030         rqfar--;
1031         rqfcr = RQFCR_CMP_NOMATCH;
1032         priv->ftp_rqfpr[rqfar] = rqfpr;
1033         priv->ftp_rqfcr[rqfar] = rqfcr;
1034         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1035
1036         rqfar--;
1037         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1038         rqfpr = class;
1039         priv->ftp_rqfcr[rqfar] = rqfcr;
1040         priv->ftp_rqfpr[rqfar] = rqfpr;
1041         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1042
1043         rqfar--;
1044         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1045         rqfpr = class;
1046         priv->ftp_rqfcr[rqfar] = rqfcr;
1047         priv->ftp_rqfpr[rqfar] = rqfpr;
1048         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1049
1050         return rqfar;
1051 }
1052
1053 static void gfar_init_filer_table(struct gfar_private *priv)
1054 {
1055         int i = 0x0;
1056         u32 rqfar = MAX_FILER_IDX;
1057         u32 rqfcr = 0x0;
1058         u32 rqfpr = FPR_FILER_MASK;
1059
1060         /* Default rule */
1061         rqfcr = RQFCR_CMP_MATCH;
1062         priv->ftp_rqfcr[rqfar] = rqfcr;
1063         priv->ftp_rqfpr[rqfar] = rqfpr;
1064         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1065
1066         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1067         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1068         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1069         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1070         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1071         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1072
1073         /* cur_filer_idx indicated the first non-masked rule */
1074         priv->cur_filer_idx = rqfar;
1075
1076         /* Rest are masked rules */
1077         rqfcr = RQFCR_CMP_NOMATCH;
1078         for (i = 0; i < rqfar; i++) {
1079                 priv->ftp_rqfcr[i] = rqfcr;
1080                 priv->ftp_rqfpr[i] = rqfpr;
1081                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1082         }
1083 }
1084
1085 #ifdef CONFIG_PPC
1086 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1087 {
1088         unsigned int pvr = mfspr(SPRN_PVR);
1089         unsigned int svr = mfspr(SPRN_SVR);
1090         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1091         unsigned int rev = svr & 0xffff;
1092
1093         /* MPC8313 Rev 2.0 and higher; All MPC837x */
1094         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1095             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1096                 priv->errata |= GFAR_ERRATA_74;
1097
1098         /* MPC8313 and MPC837x all rev */
1099         if ((pvr == 0x80850010 && mod == 0x80b0) ||
1100             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1101                 priv->errata |= GFAR_ERRATA_76;
1102
1103         /* MPC8313 Rev < 2.0 */
1104         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1105                 priv->errata |= GFAR_ERRATA_12;
1106 }
1107
1108 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1109 {
1110         unsigned int svr = mfspr(SPRN_SVR);
1111
1112         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1113                 priv->errata |= GFAR_ERRATA_12;
1114         if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1115             ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1116                 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1117 }
1118 #endif
1119
1120 static void gfar_detect_errata(struct gfar_private *priv)
1121 {
1122         struct device *dev = &priv->ofdev->dev;
1123
1124         /* no plans to fix */
1125         priv->errata |= GFAR_ERRATA_A002;
1126
1127 #ifdef CONFIG_PPC
1128         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1129                 __gfar_detect_errata_85xx(priv);
1130         else /* non-mpc85xx parts, i.e. e300 core based */
1131                 __gfar_detect_errata_83xx(priv);
1132 #endif
1133
1134         if (priv->errata)
1135                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1136                          priv->errata);
1137 }
1138
1139 void gfar_mac_reset(struct gfar_private *priv)
1140 {
1141         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1142         u32 tempval;
1143
1144         /* Reset MAC layer */
1145         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1146
1147         /* We need to delay at least 3 TX clocks */
1148         udelay(3);
1149
1150         /* the soft reset bit is not self-resetting, so we need to
1151          * clear it before resuming normal operation
1152          */
1153         gfar_write(&regs->maccfg1, 0);
1154
1155         udelay(3);
1156
1157         gfar_rx_offload_en(priv);
1158
1159         /* Initialize the max receive frame/buffer lengths */
1160         gfar_write(&regs->maxfrm, GFAR_JUMBO_FRAME_SIZE);
1161         gfar_write(&regs->mrblr, GFAR_RXB_SIZE);
1162
1163         /* Initialize the Minimum Frame Length Register */
1164         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1165
1166         /* Initialize MACCFG2. */
1167         tempval = MACCFG2_INIT_SETTINGS;
1168
1169         /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
1170          * are marked as truncated.  Avoid this by MACCFG2[Huge Frame]=1,
1171          * and by checking RxBD[LG] and discarding larger than MAXFRM.
1172          */
1173         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1174                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1175
1176         gfar_write(&regs->maccfg2, tempval);
1177
1178         /* Clear mac addr hash registers */
1179         gfar_write(&regs->igaddr0, 0);
1180         gfar_write(&regs->igaddr1, 0);
1181         gfar_write(&regs->igaddr2, 0);
1182         gfar_write(&regs->igaddr3, 0);
1183         gfar_write(&regs->igaddr4, 0);
1184         gfar_write(&regs->igaddr5, 0);
1185         gfar_write(&regs->igaddr6, 0);
1186         gfar_write(&regs->igaddr7, 0);
1187
1188         gfar_write(&regs->gaddr0, 0);
1189         gfar_write(&regs->gaddr1, 0);
1190         gfar_write(&regs->gaddr2, 0);
1191         gfar_write(&regs->gaddr3, 0);
1192         gfar_write(&regs->gaddr4, 0);
1193         gfar_write(&regs->gaddr5, 0);
1194         gfar_write(&regs->gaddr6, 0);
1195         gfar_write(&regs->gaddr7, 0);
1196
1197         if (priv->extended_hash)
1198                 gfar_clear_exact_match(priv->ndev);
1199
1200         gfar_mac_rx_config(priv);
1201
1202         gfar_mac_tx_config(priv);
1203
1204         gfar_set_mac_address(priv->ndev);
1205
1206         gfar_set_multi(priv->ndev);
1207
1208         /* clear ievent and imask before configuring coalescing */
1209         gfar_ints_disable(priv);
1210
1211         /* Configure the coalescing support */
1212         gfar_configure_coalescing_all(priv);
1213 }
1214
1215 static void gfar_hw_init(struct gfar_private *priv)
1216 {
1217         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1218         u32 attrs;
1219
1220         /* Stop the DMA engine now, in case it was running before
1221          * (The firmware could have used it, and left it running).
1222          */
1223         gfar_halt(priv);
1224
1225         gfar_mac_reset(priv);
1226
1227         /* Zero out the rmon mib registers if it has them */
1228         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1229                 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1230
1231                 /* Mask off the CAM interrupts */
1232                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1233                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1234         }
1235
1236         /* Initialize ECNTRL */
1237         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1238
1239         /* Set the extraction length and index */
1240         attrs = ATTRELI_EL(priv->rx_stash_size) |
1241                 ATTRELI_EI(priv->rx_stash_index);
1242
1243         gfar_write(&regs->attreli, attrs);
1244
1245         /* Start with defaults, and add stashing
1246          * depending on driver parameters
1247          */
1248         attrs = ATTR_INIT_SETTINGS;
1249
1250         if (priv->bd_stash_en)
1251                 attrs |= ATTR_BDSTASH;
1252
1253         if (priv->rx_stash_size != 0)
1254                 attrs |= ATTR_BUFSTASH;
1255
1256         gfar_write(&regs->attr, attrs);
1257
1258         /* FIFO configs */
1259         gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1260         gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1261         gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1262
1263         /* Program the interrupt steering regs, only for MG devices */
1264         if (priv->num_grps > 1)
1265                 gfar_write_isrg(priv);
1266 }
1267
1268 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1269 {
1270         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1271
1272         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1273                 priv->extended_hash = 1;
1274                 priv->hash_width = 9;
1275
1276                 priv->hash_regs[0] = &regs->igaddr0;
1277                 priv->hash_regs[1] = &regs->igaddr1;
1278                 priv->hash_regs[2] = &regs->igaddr2;
1279                 priv->hash_regs[3] = &regs->igaddr3;
1280                 priv->hash_regs[4] = &regs->igaddr4;
1281                 priv->hash_regs[5] = &regs->igaddr5;
1282                 priv->hash_regs[6] = &regs->igaddr6;
1283                 priv->hash_regs[7] = &regs->igaddr7;
1284                 priv->hash_regs[8] = &regs->gaddr0;
1285                 priv->hash_regs[9] = &regs->gaddr1;
1286                 priv->hash_regs[10] = &regs->gaddr2;
1287                 priv->hash_regs[11] = &regs->gaddr3;
1288                 priv->hash_regs[12] = &regs->gaddr4;
1289                 priv->hash_regs[13] = &regs->gaddr5;
1290                 priv->hash_regs[14] = &regs->gaddr6;
1291                 priv->hash_regs[15] = &regs->gaddr7;
1292
1293         } else {
1294                 priv->extended_hash = 0;
1295                 priv->hash_width = 8;
1296
1297                 priv->hash_regs[0] = &regs->gaddr0;
1298                 priv->hash_regs[1] = &regs->gaddr1;
1299                 priv->hash_regs[2] = &regs->gaddr2;
1300                 priv->hash_regs[3] = &regs->gaddr3;
1301                 priv->hash_regs[4] = &regs->gaddr4;
1302                 priv->hash_regs[5] = &regs->gaddr5;
1303                 priv->hash_regs[6] = &regs->gaddr6;
1304                 priv->hash_regs[7] = &regs->gaddr7;
1305         }
1306 }
1307
1308 /* Set up the ethernet device structure, private data,
1309  * and anything else we need before we start
1310  */
1311 static int gfar_probe(struct platform_device *ofdev)
1312 {
1313         struct net_device *dev = NULL;
1314         struct gfar_private *priv = NULL;
1315         int err = 0, i;
1316
1317         err = gfar_of_init(ofdev, &dev);
1318
1319         if (err)
1320                 return err;
1321
1322         priv = netdev_priv(dev);
1323         priv->ndev = dev;
1324         priv->ofdev = ofdev;
1325         priv->dev = &ofdev->dev;
1326         SET_NETDEV_DEV(dev, &ofdev->dev);
1327
1328         INIT_WORK(&priv->reset_task, gfar_reset_task);
1329
1330         platform_set_drvdata(ofdev, priv);
1331
1332         gfar_detect_errata(priv);
1333
1334         /* Set the dev->base_addr to the gfar reg region */
1335         dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1336
1337         /* Fill in the dev structure */
1338         dev->watchdog_timeo = TX_TIMEOUT;
1339         dev->mtu = 1500;
1340         dev->netdev_ops = &gfar_netdev_ops;
1341         dev->ethtool_ops = &gfar_ethtool_ops;
1342
1343         /* Register for napi ...We are registering NAPI for each grp */
1344         for (i = 0; i < priv->num_grps; i++) {
1345                 if (priv->poll_mode == GFAR_SQ_POLLING) {
1346                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1347                                        gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1348                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1349                                        gfar_poll_tx_sq, 2);
1350                 } else {
1351                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1352                                        gfar_poll_rx, GFAR_DEV_WEIGHT);
1353                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1354                                        gfar_poll_tx, 2);
1355                 }
1356         }
1357
1358         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1359                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1360                                    NETIF_F_RXCSUM;
1361                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1362                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1363         }
1364
1365         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1366                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1367                                     NETIF_F_HW_VLAN_CTAG_RX;
1368                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1369         }
1370
1371         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1372
1373         gfar_init_addr_hash_table(priv);
1374
1375         /* Insert receive time stamps into padding alignment bytes */
1376         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1377                 priv->padding = 8;
1378
1379         if (dev->features & NETIF_F_IP_CSUM ||
1380             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1381                 dev->needed_headroom = GMAC_FCB_LEN;
1382
1383         /* Initializing some of the rx/tx queue level parameters */
1384         for (i = 0; i < priv->num_tx_queues; i++) {
1385                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1386                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1387                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1388                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1389         }
1390
1391         for (i = 0; i < priv->num_rx_queues; i++) {
1392                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1393                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1394                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1395         }
1396
1397         /* Always enable rx filer if available */
1398         priv->rx_filer_enable =
1399             (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
1400         /* Enable most messages by default */
1401         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1402         /* use pritority h/w tx queue scheduling for single queue devices */
1403         if (priv->num_tx_queues == 1)
1404                 priv->prio_sched_en = 1;
1405
1406         set_bit(GFAR_DOWN, &priv->state);
1407
1408         gfar_hw_init(priv);
1409
1410         /* Carrier starts down, phylib will bring it up */
1411         netif_carrier_off(dev);
1412
1413         err = register_netdev(dev);
1414
1415         if (err) {
1416                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1417                 goto register_fail;
1418         }
1419
1420         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
1421                 priv->wol_supported |= GFAR_WOL_MAGIC;
1422
1423         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
1424             priv->rx_filer_enable)
1425                 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
1426
1427         device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
1428
1429         /* fill out IRQ number and name fields */
1430         for (i = 0; i < priv->num_grps; i++) {
1431                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1432                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1433                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1434                                 dev->name, "_g", '0' + i, "_tx");
1435                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1436                                 dev->name, "_g", '0' + i, "_rx");
1437                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1438                                 dev->name, "_g", '0' + i, "_er");
1439                 } else
1440                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1441         }
1442
1443         /* Initialize the filer table */
1444         gfar_init_filer_table(priv);
1445
1446         /* Print out the device info */
1447         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1448
1449         /* Even more device info helps when determining which kernel
1450          * provided which set of benchmarks.
1451          */
1452         netdev_info(dev, "Running with NAPI enabled\n");
1453         for (i = 0; i < priv->num_rx_queues; i++)
1454                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1455                             i, priv->rx_queue[i]->rx_ring_size);
1456         for (i = 0; i < priv->num_tx_queues; i++)
1457                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1458                             i, priv->tx_queue[i]->tx_ring_size);
1459
1460         return 0;
1461
1462 register_fail:
1463         unmap_group_regs(priv);
1464         gfar_free_rx_queues(priv);
1465         gfar_free_tx_queues(priv);
1466         of_node_put(priv->phy_node);
1467         of_node_put(priv->tbi_node);
1468         free_gfar_dev(priv);
1469         return err;
1470 }
1471
1472 static int gfar_remove(struct platform_device *ofdev)
1473 {
1474         struct gfar_private *priv = platform_get_drvdata(ofdev);
1475
1476         of_node_put(priv->phy_node);
1477         of_node_put(priv->tbi_node);
1478
1479         unregister_netdev(priv->ndev);
1480         unmap_group_regs(priv);
1481         gfar_free_rx_queues(priv);
1482         gfar_free_tx_queues(priv);
1483         free_gfar_dev(priv);
1484
1485         return 0;
1486 }
1487
1488 #ifdef CONFIG_PM
1489
1490 static void __gfar_filer_disable(struct gfar_private *priv)
1491 {
1492         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1493         u32 temp;
1494
1495         temp = gfar_read(&regs->rctrl);
1496         temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
1497         gfar_write(&regs->rctrl, temp);
1498 }
1499
1500 static void __gfar_filer_enable(struct gfar_private *priv)
1501 {
1502         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1503         u32 temp;
1504
1505         temp = gfar_read(&regs->rctrl);
1506         temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
1507         gfar_write(&regs->rctrl, temp);
1508 }
1509
1510 /* Filer rules implementing wol capabilities */
1511 static void gfar_filer_config_wol(struct gfar_private *priv)
1512 {
1513         unsigned int i;
1514         u32 rqfcr;
1515
1516         __gfar_filer_disable(priv);
1517
1518         /* clear the filer table, reject any packet by default */
1519         rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
1520         for (i = 0; i <= MAX_FILER_IDX; i++)
1521                 gfar_write_filer(priv, i, rqfcr, 0);
1522
1523         i = 0;
1524         if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
1525                 /* unicast packet, accept it */
1526                 struct net_device *ndev = priv->ndev;
1527                 /* get the default rx queue index */
1528                 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
1529                 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
1530                                     (ndev->dev_addr[1] << 8) |
1531                                      ndev->dev_addr[2];
1532
1533                 rqfcr = (qindex << 10) | RQFCR_AND |
1534                         RQFCR_CMP_EXACT | RQFCR_PID_DAH;
1535
1536                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1537
1538                 dest_mac_addr = (ndev->dev_addr[3] << 16) |
1539                                 (ndev->dev_addr[4] << 8) |
1540                                  ndev->dev_addr[5];
1541                 rqfcr = (qindex << 10) | RQFCR_GPI |
1542                         RQFCR_CMP_EXACT | RQFCR_PID_DAL;
1543                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1544         }
1545
1546         __gfar_filer_enable(priv);
1547 }
1548
1549 static void gfar_filer_restore_table(struct gfar_private *priv)
1550 {
1551         u32 rqfcr, rqfpr;
1552         unsigned int i;
1553
1554         __gfar_filer_disable(priv);
1555
1556         for (i = 0; i <= MAX_FILER_IDX; i++) {
1557                 rqfcr = priv->ftp_rqfcr[i];
1558                 rqfpr = priv->ftp_rqfpr[i];
1559                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1560         }
1561
1562         __gfar_filer_enable(priv);
1563 }
1564
1565 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
1566 static void gfar_start_wol_filer(struct gfar_private *priv)
1567 {
1568         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1569         u32 tempval;
1570         int i = 0;
1571
1572         /* Enable Rx hw queues */
1573         gfar_write(&regs->rqueue, priv->rqueue);
1574
1575         /* Initialize DMACTRL to have WWR and WOP */
1576         tempval = gfar_read(&regs->dmactrl);
1577         tempval |= DMACTRL_INIT_SETTINGS;
1578         gfar_write(&regs->dmactrl, tempval);
1579
1580         /* Make sure we aren't stopped */
1581         tempval = gfar_read(&regs->dmactrl);
1582         tempval &= ~DMACTRL_GRS;
1583         gfar_write(&regs->dmactrl, tempval);
1584
1585         for (i = 0; i < priv->num_grps; i++) {
1586                 regs = priv->gfargrp[i].regs;
1587                 /* Clear RHLT, so that the DMA starts polling now */
1588                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1589                 /* enable the Filer General Purpose Interrupt */
1590                 gfar_write(&regs->imask, IMASK_FGPI);
1591         }
1592
1593         /* Enable Rx DMA */
1594         tempval = gfar_read(&regs->maccfg1);
1595         tempval |= MACCFG1_RX_EN;
1596         gfar_write(&regs->maccfg1, tempval);
1597 }
1598
1599 static int gfar_suspend(struct device *dev)
1600 {
1601         struct gfar_private *priv = dev_get_drvdata(dev);
1602         struct net_device *ndev = priv->ndev;
1603         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1604         u32 tempval;
1605         u16 wol = priv->wol_opts;
1606
1607         if (!netif_running(ndev))
1608                 return 0;
1609
1610         disable_napi(priv);
1611         netif_tx_lock(ndev);
1612         netif_device_detach(ndev);
1613         netif_tx_unlock(ndev);
1614
1615         gfar_halt(priv);
1616
1617         if (wol & GFAR_WOL_MAGIC) {
1618                 /* Enable interrupt on Magic Packet */
1619                 gfar_write(&regs->imask, IMASK_MAG);
1620
1621                 /* Enable Magic Packet mode */
1622                 tempval = gfar_read(&regs->maccfg2);
1623                 tempval |= MACCFG2_MPEN;
1624                 gfar_write(&regs->maccfg2, tempval);
1625
1626                 /* re-enable the Rx block */
1627                 tempval = gfar_read(&regs->maccfg1);
1628                 tempval |= MACCFG1_RX_EN;
1629                 gfar_write(&regs->maccfg1, tempval);
1630
1631         } else if (wol & GFAR_WOL_FILER_UCAST) {
1632                 gfar_filer_config_wol(priv);
1633                 gfar_start_wol_filer(priv);
1634
1635         } else {
1636                 phy_stop(priv->phydev);
1637         }
1638
1639         return 0;
1640 }
1641
1642 static int gfar_resume(struct device *dev)
1643 {
1644         struct gfar_private *priv = dev_get_drvdata(dev);
1645         struct net_device *ndev = priv->ndev;
1646         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1647         u32 tempval;
1648         u16 wol = priv->wol_opts;
1649
1650         if (!netif_running(ndev))
1651                 return 0;
1652
1653         if (wol & GFAR_WOL_MAGIC) {
1654                 /* Disable Magic Packet mode */
1655                 tempval = gfar_read(&regs->maccfg2);
1656                 tempval &= ~MACCFG2_MPEN;
1657                 gfar_write(&regs->maccfg2, tempval);
1658
1659         } else if (wol & GFAR_WOL_FILER_UCAST) {
1660                 /* need to stop rx only, tx is already down */
1661                 gfar_halt(priv);
1662                 gfar_filer_restore_table(priv);
1663
1664         } else {
1665                 phy_start(priv->phydev);
1666         }
1667
1668         gfar_start(priv);
1669
1670         netif_device_attach(ndev);
1671         enable_napi(priv);
1672
1673         return 0;
1674 }
1675
1676 static int gfar_restore(struct device *dev)
1677 {
1678         struct gfar_private *priv = dev_get_drvdata(dev);
1679         struct net_device *ndev = priv->ndev;
1680
1681         if (!netif_running(ndev)) {
1682                 netif_device_attach(ndev);
1683
1684                 return 0;
1685         }
1686
1687         gfar_init_bds(ndev);
1688
1689         gfar_mac_reset(priv);
1690
1691         gfar_init_tx_rx_base(priv);
1692
1693         gfar_start(priv);
1694
1695         priv->oldlink = 0;
1696         priv->oldspeed = 0;
1697         priv->oldduplex = -1;
1698
1699         if (priv->phydev)
1700                 phy_start(priv->phydev);
1701
1702         netif_device_attach(ndev);
1703         enable_napi(priv);
1704
1705         return 0;
1706 }
1707
1708 static struct dev_pm_ops gfar_pm_ops = {
1709         .suspend = gfar_suspend,
1710         .resume = gfar_resume,
1711         .freeze = gfar_suspend,
1712         .thaw = gfar_resume,
1713         .restore = gfar_restore,
1714 };
1715
1716 #define GFAR_PM_OPS (&gfar_pm_ops)
1717
1718 #else
1719
1720 #define GFAR_PM_OPS NULL
1721
1722 #endif
1723
1724 /* Reads the controller's registers to determine what interface
1725  * connects it to the PHY.
1726  */
1727 static phy_interface_t gfar_get_interface(struct net_device *dev)
1728 {
1729         struct gfar_private *priv = netdev_priv(dev);
1730         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1731         u32 ecntrl;
1732
1733         ecntrl = gfar_read(&regs->ecntrl);
1734
1735         if (ecntrl & ECNTRL_SGMII_MODE)
1736                 return PHY_INTERFACE_MODE_SGMII;
1737
1738         if (ecntrl & ECNTRL_TBI_MODE) {
1739                 if (ecntrl & ECNTRL_REDUCED_MODE)
1740                         return PHY_INTERFACE_MODE_RTBI;
1741                 else
1742                         return PHY_INTERFACE_MODE_TBI;
1743         }
1744
1745         if (ecntrl & ECNTRL_REDUCED_MODE) {
1746                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1747                         return PHY_INTERFACE_MODE_RMII;
1748                 }
1749                 else {
1750                         phy_interface_t interface = priv->interface;
1751
1752                         /* This isn't autodetected right now, so it must
1753                          * be set by the device tree or platform code.
1754                          */
1755                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1756                                 return PHY_INTERFACE_MODE_RGMII_ID;
1757
1758                         return PHY_INTERFACE_MODE_RGMII;
1759                 }
1760         }
1761
1762         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1763                 return PHY_INTERFACE_MODE_GMII;
1764
1765         return PHY_INTERFACE_MODE_MII;
1766 }
1767
1768
1769 /* Initializes driver's PHY state, and attaches to the PHY.
1770  * Returns 0 on success.
1771  */
1772 static int init_phy(struct net_device *dev)
1773 {
1774         struct gfar_private *priv = netdev_priv(dev);
1775         uint gigabit_support =
1776                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1777                 GFAR_SUPPORTED_GBIT : 0;
1778         phy_interface_t interface;
1779
1780         priv->oldlink = 0;
1781         priv->oldspeed = 0;
1782         priv->oldduplex = -1;
1783
1784         interface = gfar_get_interface(dev);
1785
1786         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1787                                       interface);
1788         if (!priv->phydev) {
1789                 dev_err(&dev->dev, "could not attach to PHY\n");
1790                 return -ENODEV;
1791         }
1792
1793         if (interface == PHY_INTERFACE_MODE_SGMII)
1794                 gfar_configure_serdes(dev);
1795
1796         /* Remove any features not supported by the controller */
1797         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1798         priv->phydev->advertising = priv->phydev->supported;
1799
1800         /* Add support for flow control, but don't advertise it by default */
1801         priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1802
1803         return 0;
1804 }
1805
1806 /* Initialize TBI PHY interface for communicating with the
1807  * SERDES lynx PHY on the chip.  We communicate with this PHY
1808  * through the MDIO bus on each controller, treating it as a
1809  * "normal" PHY at the address found in the TBIPA register.  We assume
1810  * that the TBIPA register is valid.  Either the MDIO bus code will set
1811  * it to a value that doesn't conflict with other PHYs on the bus, or the
1812  * value doesn't matter, as there are no other PHYs on the bus.
1813  */
1814 static void gfar_configure_serdes(struct net_device *dev)
1815 {
1816         struct gfar_private *priv = netdev_priv(dev);
1817         struct phy_device *tbiphy;
1818
1819         if (!priv->tbi_node) {
1820                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1821                                     "device tree specify a tbi-handle\n");
1822                 return;
1823         }
1824
1825         tbiphy = of_phy_find_device(priv->tbi_node);
1826         if (!tbiphy) {
1827                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1828                 return;
1829         }
1830
1831         /* If the link is already up, we must already be ok, and don't need to
1832          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1833          * everything for us?  Resetting it takes the link down and requires
1834          * several seconds for it to come back.
1835          */
1836         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1837                 put_device(&tbiphy->mdio.dev);
1838                 return;
1839         }
1840
1841         /* Single clk mode, mii mode off(for serdes communication) */
1842         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1843
1844         phy_write(tbiphy, MII_ADVERTISE,
1845                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1846                   ADVERTISE_1000XPSE_ASYM);
1847
1848         phy_write(tbiphy, MII_BMCR,
1849                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1850                   BMCR_SPEED1000);
1851
1852         put_device(&tbiphy->mdio.dev);
1853 }
1854
1855 static int __gfar_is_rx_idle(struct gfar_private *priv)
1856 {
1857         u32 res;
1858
1859         /* Normaly TSEC should not hang on GRS commands, so we should
1860          * actually wait for IEVENT_GRSC flag.
1861          */
1862         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1863                 return 0;
1864
1865         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1866          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1867          * and the Rx can be safely reset.
1868          */
1869         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1870         res &= 0x7f807f80;
1871         if ((res & 0xffff) == (res >> 16))
1872                 return 1;
1873
1874         return 0;
1875 }
1876
1877 /* Halt the receive and transmit queues */
1878 static void gfar_halt_nodisable(struct gfar_private *priv)
1879 {
1880         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1881         u32 tempval;
1882         unsigned int timeout;
1883         int stopped;
1884
1885         gfar_ints_disable(priv);
1886
1887         if (gfar_is_dma_stopped(priv))
1888                 return;
1889
1890         /* Stop the DMA, and wait for it to stop */
1891         tempval = gfar_read(&regs->dmactrl);
1892         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1893         gfar_write(&regs->dmactrl, tempval);
1894
1895 retry:
1896         timeout = 1000;
1897         while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1898                 cpu_relax();
1899                 timeout--;
1900         }
1901
1902         if (!timeout)
1903                 stopped = gfar_is_dma_stopped(priv);
1904
1905         if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1906             !__gfar_is_rx_idle(priv))
1907                 goto retry;
1908 }
1909
1910 /* Halt the receive and transmit queues */
1911 void gfar_halt(struct gfar_private *priv)
1912 {
1913         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1914         u32 tempval;
1915
1916         /* Dissable the Rx/Tx hw queues */
1917         gfar_write(&regs->rqueue, 0);
1918         gfar_write(&regs->tqueue, 0);
1919
1920         mdelay(10);
1921
1922         gfar_halt_nodisable(priv);
1923
1924         /* Disable Rx/Tx DMA */
1925         tempval = gfar_read(&regs->maccfg1);
1926         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1927         gfar_write(&regs->maccfg1, tempval);
1928 }
1929
1930 void stop_gfar(struct net_device *dev)
1931 {
1932         struct gfar_private *priv = netdev_priv(dev);
1933
1934         netif_tx_stop_all_queues(dev);
1935
1936         smp_mb__before_atomic();
1937         set_bit(GFAR_DOWN, &priv->state);
1938         smp_mb__after_atomic();
1939
1940         disable_napi(priv);
1941
1942         /* disable ints and gracefully shut down Rx/Tx DMA */
1943         gfar_halt(priv);
1944
1945         phy_stop(priv->phydev);
1946
1947         free_skb_resources(priv);
1948 }
1949
1950 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1951 {
1952         struct txbd8 *txbdp;
1953         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1954         int i, j;
1955
1956         txbdp = tx_queue->tx_bd_base;
1957
1958         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1959                 if (!tx_queue->tx_skbuff[i])
1960                         continue;
1961
1962                 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1963                                  be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1964                 txbdp->lstatus = 0;
1965                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1966                      j++) {
1967                         txbdp++;
1968                         dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1969                                        be16_to_cpu(txbdp->length),
1970                                        DMA_TO_DEVICE);
1971                 }
1972                 txbdp++;
1973                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1974                 tx_queue->tx_skbuff[i] = NULL;
1975         }
1976         kfree(tx_queue->tx_skbuff);
1977         tx_queue->tx_skbuff = NULL;
1978 }
1979
1980 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1981 {
1982         int i;
1983
1984         struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1985
1986         if (rx_queue->skb)
1987                 dev_kfree_skb(rx_queue->skb);
1988
1989         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1990                 struct  gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1991
1992                 rxbdp->lstatus = 0;
1993                 rxbdp->bufPtr = 0;
1994                 rxbdp++;
1995
1996                 if (!rxb->page)
1997                         continue;
1998
1999                 dma_unmap_single(rx_queue->dev, rxb->dma,
2000                                  PAGE_SIZE, DMA_FROM_DEVICE);
2001                 __free_page(rxb->page);
2002
2003                 rxb->page = NULL;
2004         }
2005
2006         kfree(rx_queue->rx_buff);
2007         rx_queue->rx_buff = NULL;
2008 }
2009
2010 /* If there are any tx skbs or rx skbs still around, free them.
2011  * Then free tx_skbuff and rx_skbuff
2012  */
2013 static void free_skb_resources(struct gfar_private *priv)
2014 {
2015         struct gfar_priv_tx_q *tx_queue = NULL;
2016         struct gfar_priv_rx_q *rx_queue = NULL;
2017         int i;
2018
2019         /* Go through all the buffer descriptors and free their data buffers */
2020         for (i = 0; i < priv->num_tx_queues; i++) {
2021                 struct netdev_queue *txq;
2022
2023                 tx_queue = priv->tx_queue[i];
2024                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
2025                 if (tx_queue->tx_skbuff)
2026                         free_skb_tx_queue(tx_queue);
2027                 netdev_tx_reset_queue(txq);
2028         }
2029
2030         for (i = 0; i < priv->num_rx_queues; i++) {
2031                 rx_queue = priv->rx_queue[i];
2032                 if (rx_queue->rx_buff)
2033                         free_skb_rx_queue(rx_queue);
2034         }
2035
2036         dma_free_coherent(priv->dev,
2037                           sizeof(struct txbd8) * priv->total_tx_ring_size +
2038                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
2039                           priv->tx_queue[0]->tx_bd_base,
2040                           priv->tx_queue[0]->tx_bd_dma_base);
2041 }
2042
2043 void gfar_start(struct gfar_private *priv)
2044 {
2045         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2046         u32 tempval;
2047         int i = 0;
2048
2049         /* Enable Rx/Tx hw queues */
2050         gfar_write(&regs->rqueue, priv->rqueue);
2051         gfar_write(&regs->tqueue, priv->tqueue);
2052
2053         /* Initialize DMACTRL to have WWR and WOP */
2054         tempval = gfar_read(&regs->dmactrl);
2055         tempval |= DMACTRL_INIT_SETTINGS;
2056         gfar_write(&regs->dmactrl, tempval);
2057
2058         /* Make sure we aren't stopped */
2059         tempval = gfar_read(&regs->dmactrl);
2060         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
2061         gfar_write(&regs->dmactrl, tempval);
2062
2063         for (i = 0; i < priv->num_grps; i++) {
2064                 regs = priv->gfargrp[i].regs;
2065                 /* Clear THLT/RHLT, so that the DMA starts polling now */
2066                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
2067                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
2068         }
2069
2070         /* Enable Rx/Tx DMA */
2071         tempval = gfar_read(&regs->maccfg1);
2072         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2073         gfar_write(&regs->maccfg1, tempval);
2074
2075         gfar_ints_enable(priv);
2076
2077         priv->ndev->trans_start = jiffies; /* prevent tx timeout */
2078 }
2079
2080 static void free_grp_irqs(struct gfar_priv_grp *grp)
2081 {
2082         free_irq(gfar_irq(grp, TX)->irq, grp);
2083         free_irq(gfar_irq(grp, RX)->irq, grp);
2084         free_irq(gfar_irq(grp, ER)->irq, grp);
2085 }
2086
2087 static int register_grp_irqs(struct gfar_priv_grp *grp)
2088 {
2089         struct gfar_private *priv = grp->priv;
2090         struct net_device *dev = priv->ndev;
2091         int err;
2092
2093         /* If the device has multiple interrupts, register for
2094          * them.  Otherwise, only register for the one
2095          */
2096         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2097                 /* Install our interrupt handlers for Error,
2098                  * Transmit, and Receive
2099                  */
2100                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2101                                   gfar_irq(grp, ER)->name, grp);
2102                 if (err < 0) {
2103                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2104                                   gfar_irq(grp, ER)->irq);
2105
2106                         goto err_irq_fail;
2107                 }
2108                 enable_irq_wake(gfar_irq(grp, ER)->irq);
2109
2110                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2111                                   gfar_irq(grp, TX)->name, grp);
2112                 if (err < 0) {
2113                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2114                                   gfar_irq(grp, TX)->irq);
2115                         goto tx_irq_fail;
2116                 }
2117                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2118                                   gfar_irq(grp, RX)->name, grp);
2119                 if (err < 0) {
2120                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2121                                   gfar_irq(grp, RX)->irq);
2122                         goto rx_irq_fail;
2123                 }
2124                 enable_irq_wake(gfar_irq(grp, RX)->irq);
2125
2126         } else {
2127                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2128                                   gfar_irq(grp, TX)->name, grp);
2129                 if (err < 0) {
2130                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2131                                   gfar_irq(grp, TX)->irq);
2132                         goto err_irq_fail;
2133                 }
2134                 enable_irq_wake(gfar_irq(grp, TX)->irq);
2135         }
2136
2137         return 0;
2138
2139 rx_irq_fail:
2140         free_irq(gfar_irq(grp, TX)->irq, grp);
2141 tx_irq_fail:
2142         free_irq(gfar_irq(grp, ER)->irq, grp);
2143 err_irq_fail:
2144         return err;
2145
2146 }
2147
2148 static void gfar_free_irq(struct gfar_private *priv)
2149 {
2150         int i;
2151
2152         /* Free the IRQs */
2153         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2154                 for (i = 0; i < priv->num_grps; i++)
2155                         free_grp_irqs(&priv->gfargrp[i]);
2156         } else {
2157                 for (i = 0; i < priv->num_grps; i++)
2158                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2159                                  &priv->gfargrp[i]);
2160         }
2161 }
2162
2163 static int gfar_request_irq(struct gfar_private *priv)
2164 {
2165         int err, i, j;
2166
2167         for (i = 0; i < priv->num_grps; i++) {
2168                 err = register_grp_irqs(&priv->gfargrp[i]);
2169                 if (err) {
2170                         for (j = 0; j < i; j++)
2171                                 free_grp_irqs(&priv->gfargrp[j]);
2172                         return err;
2173                 }
2174         }
2175
2176         return 0;
2177 }
2178
2179 /* Bring the controller up and running */
2180 int startup_gfar(struct net_device *ndev)
2181 {
2182         struct gfar_private *priv = netdev_priv(ndev);
2183         int err;
2184
2185         gfar_mac_reset(priv);
2186
2187         err = gfar_alloc_skb_resources(ndev);
2188         if (err)
2189                 return err;
2190
2191         gfar_init_tx_rx_base(priv);
2192
2193         smp_mb__before_atomic();
2194         clear_bit(GFAR_DOWN, &priv->state);
2195         smp_mb__after_atomic();
2196
2197         /* Start Rx/Tx DMA and enable the interrupts */
2198         gfar_start(priv);
2199
2200         /* force link state update after mac reset */
2201         priv->oldlink = 0;
2202         priv->oldspeed = 0;
2203         priv->oldduplex = -1;
2204
2205         phy_start(priv->phydev);
2206
2207         enable_napi(priv);
2208
2209         netif_tx_wake_all_queues(ndev);
2210
2211         return 0;
2212 }
2213
2214 /* Called when something needs to use the ethernet device
2215  * Returns 0 for success.
2216  */
2217 static int gfar_enet_open(struct net_device *dev)
2218 {
2219         struct gfar_private *priv = netdev_priv(dev);
2220         int err;
2221
2222         err = init_phy(dev);
2223         if (err)
2224                 return err;
2225
2226         err = gfar_request_irq(priv);
2227         if (err)
2228                 return err;
2229
2230         err = startup_gfar(dev);
2231         if (err)
2232                 return err;
2233
2234         return err;
2235 }
2236
2237 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2238 {
2239         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2240
2241         memset(fcb, 0, GMAC_FCB_LEN);
2242
2243         return fcb;
2244 }
2245
2246 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2247                                     int fcb_length)
2248 {
2249         /* If we're here, it's a IP packet with a TCP or UDP
2250          * payload.  We set it to checksum, using a pseudo-header
2251          * we provide
2252          */
2253         u8 flags = TXFCB_DEFAULT;
2254
2255         /* Tell the controller what the protocol is
2256          * And provide the already calculated phcs
2257          */
2258         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2259                 flags |= TXFCB_UDP;
2260                 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2261         } else
2262                 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2263
2264         /* l3os is the distance between the start of the
2265          * frame (skb->data) and the start of the IP hdr.
2266          * l4os is the distance between the start of the
2267          * l3 hdr and the l4 hdr
2268          */
2269         fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2270         fcb->l4os = skb_network_header_len(skb);
2271
2272         fcb->flags = flags;
2273 }
2274
2275 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2276 {
2277         fcb->flags |= TXFCB_VLN;
2278         fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2279 }
2280
2281 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2282                                       struct txbd8 *base, int ring_size)
2283 {
2284         struct txbd8 *new_bd = bdp + stride;
2285
2286         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2287 }
2288
2289 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2290                                       int ring_size)
2291 {
2292         return skip_txbd(bdp, 1, base, ring_size);
2293 }
2294
2295 /* eTSEC12: csum generation not supported for some fcb offsets */
2296 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2297                                        unsigned long fcb_addr)
2298 {
2299         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2300                (fcb_addr % 0x20) > 0x18);
2301 }
2302
2303 /* eTSEC76: csum generation for frames larger than 2500 may
2304  * cause excess delays before start of transmission
2305  */
2306 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2307                                        unsigned int len)
2308 {
2309         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2310                (len > 2500));
2311 }
2312
2313 /* This is called by the kernel when a frame is ready for transmission.
2314  * It is pointed to by the dev->hard_start_xmit function pointer
2315  */
2316 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2317 {
2318         struct gfar_private *priv = netdev_priv(dev);
2319         struct gfar_priv_tx_q *tx_queue = NULL;
2320         struct netdev_queue *txq;
2321         struct gfar __iomem *regs = NULL;
2322         struct txfcb *fcb = NULL;
2323         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2324         u32 lstatus;
2325         int i, rq = 0;
2326         int do_tstamp, do_csum, do_vlan;
2327         u32 bufaddr;
2328         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2329
2330         rq = skb->queue_mapping;
2331         tx_queue = priv->tx_queue[rq];
2332         txq = netdev_get_tx_queue(dev, rq);
2333         base = tx_queue->tx_bd_base;
2334         regs = tx_queue->grp->regs;
2335
2336         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2337         do_vlan = skb_vlan_tag_present(skb);
2338         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2339                     priv->hwts_tx_en;
2340
2341         if (do_csum || do_vlan)
2342                 fcb_len = GMAC_FCB_LEN;
2343
2344         /* check if time stamp should be generated */
2345         if (unlikely(do_tstamp))
2346                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2347
2348         /* make space for additional header when fcb is needed */
2349         if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2350                 struct sk_buff *skb_new;
2351
2352                 skb_new = skb_realloc_headroom(skb, fcb_len);
2353                 if (!skb_new) {
2354                         dev->stats.tx_errors++;
2355                         dev_kfree_skb_any(skb);
2356                         return NETDEV_TX_OK;
2357                 }
2358
2359                 if (skb->sk)
2360                         skb_set_owner_w(skb_new, skb->sk);
2361                 dev_consume_skb_any(skb);
2362                 skb = skb_new;
2363         }
2364
2365         /* total number of fragments in the SKB */
2366         nr_frags = skb_shinfo(skb)->nr_frags;
2367
2368         /* calculate the required number of TxBDs for this skb */
2369         if (unlikely(do_tstamp))
2370                 nr_txbds = nr_frags + 2;
2371         else
2372                 nr_txbds = nr_frags + 1;
2373
2374         /* check if there is space to queue this packet */
2375         if (nr_txbds > tx_queue->num_txbdfree) {
2376                 /* no space, stop the queue */
2377                 netif_tx_stop_queue(txq);
2378                 dev->stats.tx_fifo_errors++;
2379                 return NETDEV_TX_BUSY;
2380         }
2381
2382         /* Update transmit stats */
2383         bytes_sent = skb->len;
2384         tx_queue->stats.tx_bytes += bytes_sent;
2385         /* keep Tx bytes on wire for BQL accounting */
2386         GFAR_CB(skb)->bytes_sent = bytes_sent;
2387         tx_queue->stats.tx_packets++;
2388
2389         txbdp = txbdp_start = tx_queue->cur_tx;
2390         lstatus = be32_to_cpu(txbdp->lstatus);
2391
2392         /* Time stamp insertion requires one additional TxBD */
2393         if (unlikely(do_tstamp))
2394                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2395                                                  tx_queue->tx_ring_size);
2396
2397         if (nr_frags == 0) {
2398                 if (unlikely(do_tstamp)) {
2399                         u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2400
2401                         lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2402                         txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2403                 } else {
2404                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2405                 }
2406         } else {
2407                 /* Place the fragment addresses and lengths into the TxBDs */
2408                 for (i = 0; i < nr_frags; i++) {
2409                         unsigned int frag_len;
2410                         /* Point at the next BD, wrapping as needed */
2411                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2412
2413                         frag_len = skb_shinfo(skb)->frags[i].size;
2414
2415                         lstatus = be32_to_cpu(txbdp->lstatus) | frag_len |
2416                                   BD_LFLAG(TXBD_READY);
2417
2418                         /* Handle the last BD specially */
2419                         if (i == nr_frags - 1)
2420                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2421
2422                         bufaddr = skb_frag_dma_map(priv->dev,
2423                                                    &skb_shinfo(skb)->frags[i],
2424                                                    0,
2425                                                    frag_len,
2426                                                    DMA_TO_DEVICE);
2427                         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2428                                 goto dma_map_err;
2429
2430                         /* set the TxBD length and buffer pointer */
2431                         txbdp->bufPtr = cpu_to_be32(bufaddr);
2432                         txbdp->lstatus = cpu_to_be32(lstatus);
2433                 }
2434
2435                 lstatus = be32_to_cpu(txbdp_start->lstatus);
2436         }
2437
2438         /* Add TxPAL between FCB and frame if required */
2439         if (unlikely(do_tstamp)) {
2440                 skb_push(skb, GMAC_TXPAL_LEN);
2441                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2442         }
2443
2444         /* Add TxFCB if required */
2445         if (fcb_len) {
2446                 fcb = gfar_add_fcb(skb);
2447                 lstatus |= BD_LFLAG(TXBD_TOE);
2448         }
2449
2450         /* Set up checksumming */
2451         if (do_csum) {
2452                 gfar_tx_checksum(skb, fcb, fcb_len);
2453
2454                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2455                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
2456                         __skb_pull(skb, GMAC_FCB_LEN);
2457                         skb_checksum_help(skb);
2458                         if (do_vlan || do_tstamp) {
2459                                 /* put back a new fcb for vlan/tstamp TOE */
2460                                 fcb = gfar_add_fcb(skb);
2461                         } else {
2462                                 /* Tx TOE not used */
2463                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2464                                 fcb = NULL;
2465                         }
2466                 }
2467         }
2468
2469         if (do_vlan)
2470                 gfar_tx_vlan(skb, fcb);
2471
2472         /* Setup tx hardware time stamping if requested */
2473         if (unlikely(do_tstamp)) {
2474                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2475                 fcb->ptp = 1;
2476         }
2477
2478         bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2479                                  DMA_TO_DEVICE);
2480         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2481                 goto dma_map_err;
2482
2483         txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2484
2485         /* If time stamping is requested one additional TxBD must be set up. The
2486          * first TxBD points to the FCB and must have a data length of
2487          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2488          * the full frame length.
2489          */
2490         if (unlikely(do_tstamp)) {
2491                 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2492
2493                 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2494                 bufaddr += fcb_len;
2495                 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2496                               (skb_headlen(skb) - fcb_len);
2497
2498                 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2499                 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2500                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2501         } else {
2502                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2503         }
2504
2505         netdev_tx_sent_queue(txq, bytes_sent);
2506
2507         gfar_wmb();
2508
2509         txbdp_start->lstatus = cpu_to_be32(lstatus);
2510
2511         gfar_wmb(); /* force lstatus write before tx_skbuff */
2512
2513         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2514
2515         /* Update the current skb pointer to the next entry we will use
2516          * (wrapping if necessary)
2517          */
2518         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2519                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2520
2521         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2522
2523         /* We can work in parallel with gfar_clean_tx_ring(), except
2524          * when modifying num_txbdfree. Note that we didn't grab the lock
2525          * when we were reading the num_txbdfree and checking for available
2526          * space, that's because outside of this function it can only grow.
2527          */
2528         spin_lock_bh(&tx_queue->txlock);
2529         /* reduce TxBD free count */
2530         tx_queue->num_txbdfree -= (nr_txbds);
2531         spin_unlock_bh(&tx_queue->txlock);
2532
2533         /* If the next BD still needs to be cleaned up, then the bds
2534          * are full.  We need to tell the kernel to stop sending us stuff.
2535          */
2536         if (!tx_queue->num_txbdfree) {
2537                 netif_tx_stop_queue(txq);
2538
2539                 dev->stats.tx_fifo_errors++;
2540         }
2541
2542         /* Tell the DMA to go go go */
2543         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2544
2545         return NETDEV_TX_OK;
2546
2547 dma_map_err:
2548         txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2549         if (do_tstamp)
2550                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2551         for (i = 0; i < nr_frags; i++) {
2552                 lstatus = be32_to_cpu(txbdp->lstatus);
2553                 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2554                         break;
2555
2556                 lstatus &= ~BD_LFLAG(TXBD_READY);
2557                 txbdp->lstatus = cpu_to_be32(lstatus);
2558                 bufaddr = be32_to_cpu(txbdp->bufPtr);
2559                 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2560                                DMA_TO_DEVICE);
2561                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2562         }
2563         gfar_wmb();
2564         dev_kfree_skb_any(skb);
2565         return NETDEV_TX_OK;
2566 }
2567
2568 /* Stops the kernel queue, and halts the controller */
2569 static int gfar_close(struct net_device *dev)
2570 {
2571         struct gfar_private *priv = netdev_priv(dev);
2572
2573         cancel_work_sync(&priv->reset_task);
2574         stop_gfar(dev);
2575
2576         /* Disconnect from the PHY */
2577         phy_disconnect(priv->phydev);
2578         priv->phydev = NULL;
2579
2580         gfar_free_irq(priv);
2581
2582         return 0;
2583 }
2584
2585 /* Changes the mac address if the controller is not running. */
2586 static int gfar_set_mac_address(struct net_device *dev)
2587 {
2588         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2589
2590         return 0;
2591 }
2592
2593 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2594 {
2595         struct gfar_private *priv = netdev_priv(dev);
2596         int frame_size = new_mtu + ETH_HLEN;
2597
2598         if ((frame_size < 64) || (frame_size > GFAR_JUMBO_FRAME_SIZE)) {
2599                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2600                 return -EINVAL;
2601         }
2602
2603         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2604                 cpu_relax();
2605
2606         if (dev->flags & IFF_UP)
2607                 stop_gfar(dev);
2608
2609         dev->mtu = new_mtu;
2610
2611         if (dev->flags & IFF_UP)
2612                 startup_gfar(dev);
2613
2614         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2615
2616         return 0;
2617 }
2618
2619 void reset_gfar(struct net_device *ndev)
2620 {
2621         struct gfar_private *priv = netdev_priv(ndev);
2622
2623         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2624                 cpu_relax();
2625
2626         stop_gfar(ndev);
2627         startup_gfar(ndev);
2628
2629         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2630 }
2631
2632 /* gfar_reset_task gets scheduled when a packet has not been
2633  * transmitted after a set amount of time.
2634  * For now, assume that clearing out all the structures, and
2635  * starting over will fix the problem.
2636  */
2637 static void gfar_reset_task(struct work_struct *work)
2638 {
2639         struct gfar_private *priv = container_of(work, struct gfar_private,
2640                                                  reset_task);
2641         reset_gfar(priv->ndev);
2642 }
2643
2644 static void gfar_timeout(struct net_device *dev)
2645 {
2646         struct gfar_private *priv = netdev_priv(dev);
2647
2648         dev->stats.tx_errors++;
2649         schedule_work(&priv->reset_task);
2650 }
2651
2652 /* Interrupt Handler for Transmit complete */
2653 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2654 {
2655         struct net_device *dev = tx_queue->dev;
2656         struct netdev_queue *txq;
2657         struct gfar_private *priv = netdev_priv(dev);
2658         struct txbd8 *bdp, *next = NULL;
2659         struct txbd8 *lbdp = NULL;
2660         struct txbd8 *base = tx_queue->tx_bd_base;
2661         struct sk_buff *skb;
2662         int skb_dirtytx;
2663         int tx_ring_size = tx_queue->tx_ring_size;
2664         int frags = 0, nr_txbds = 0;
2665         int i;
2666         int howmany = 0;
2667         int tqi = tx_queue->qindex;
2668         unsigned int bytes_sent = 0;
2669         u32 lstatus;
2670         size_t buflen;
2671
2672         txq = netdev_get_tx_queue(dev, tqi);
2673         bdp = tx_queue->dirty_tx;
2674         skb_dirtytx = tx_queue->skb_dirtytx;
2675
2676         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2677
2678                 frags = skb_shinfo(skb)->nr_frags;
2679
2680                 /* When time stamping, one additional TxBD must be freed.
2681                  * Also, we need to dma_unmap_single() the TxPAL.
2682                  */
2683                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2684                         nr_txbds = frags + 2;
2685                 else
2686                         nr_txbds = frags + 1;
2687
2688                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2689
2690                 lstatus = be32_to_cpu(lbdp->lstatus);
2691
2692                 /* Only clean completed frames */
2693                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2694                     (lstatus & BD_LENGTH_MASK))
2695                         break;
2696
2697                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2698                         next = next_txbd(bdp, base, tx_ring_size);
2699                         buflen = be16_to_cpu(next->length) +
2700                                  GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2701                 } else
2702                         buflen = be16_to_cpu(bdp->length);
2703
2704                 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2705                                  buflen, DMA_TO_DEVICE);
2706
2707                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2708                         struct skb_shared_hwtstamps shhwtstamps;
2709                         u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2710                                           ~0x7UL);
2711
2712                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2713                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2714                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2715                         skb_tstamp_tx(skb, &shhwtstamps);
2716                         gfar_clear_txbd_status(bdp);
2717                         bdp = next;
2718                 }
2719
2720                 gfar_clear_txbd_status(bdp);
2721                 bdp = next_txbd(bdp, base, tx_ring_size);
2722
2723                 for (i = 0; i < frags; i++) {
2724                         dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2725                                        be16_to_cpu(bdp->length),
2726                                        DMA_TO_DEVICE);
2727                         gfar_clear_txbd_status(bdp);
2728                         bdp = next_txbd(bdp, base, tx_ring_size);
2729                 }
2730
2731                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2732
2733                 dev_kfree_skb_any(skb);
2734
2735                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2736
2737                 skb_dirtytx = (skb_dirtytx + 1) &
2738                               TX_RING_MOD_MASK(tx_ring_size);
2739
2740                 howmany++;
2741                 spin_lock(&tx_queue->txlock);
2742                 tx_queue->num_txbdfree += nr_txbds;
2743                 spin_unlock(&tx_queue->txlock);
2744         }
2745
2746         /* If we freed a buffer, we can restart transmission, if necessary */
2747         if (tx_queue->num_txbdfree &&
2748             netif_tx_queue_stopped(txq) &&
2749             !(test_bit(GFAR_DOWN, &priv->state)))
2750                 netif_wake_subqueue(priv->ndev, tqi);
2751
2752         /* Update dirty indicators */
2753         tx_queue->skb_dirtytx = skb_dirtytx;
2754         tx_queue->dirty_tx = bdp;
2755
2756         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2757 }
2758
2759 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
2760 {
2761         struct page *page;
2762         dma_addr_t addr;
2763
2764         page = dev_alloc_page();
2765         if (unlikely(!page))
2766                 return false;
2767
2768         addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
2769         if (unlikely(dma_mapping_error(rxq->dev, addr))) {
2770                 __free_page(page);
2771
2772                 return false;
2773         }
2774
2775         rxb->dma = addr;
2776         rxb->page = page;
2777         rxb->page_offset = 0;
2778
2779         return true;
2780 }
2781
2782 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2783 {
2784         struct gfar_private *priv = netdev_priv(rx_queue->ndev);
2785         struct gfar_extra_stats *estats = &priv->extra_stats;
2786
2787         netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
2788         atomic64_inc(&estats->rx_alloc_err);
2789 }
2790
2791 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2792                                 int alloc_cnt)
2793 {
2794         struct rxbd8 *bdp;
2795         struct gfar_rx_buff *rxb;
2796         int i;
2797
2798         i = rx_queue->next_to_use;
2799         bdp = &rx_queue->rx_bd_base[i];
2800         rxb = &rx_queue->rx_buff[i];
2801
2802         while (alloc_cnt--) {
2803                 /* try reuse page */
2804                 if (unlikely(!rxb->page)) {
2805                         if (unlikely(!gfar_new_page(rx_queue, rxb))) {
2806                                 gfar_rx_alloc_err(rx_queue);
2807                                 break;
2808                         }
2809                 }
2810
2811                 /* Setup the new RxBD */
2812                 gfar_init_rxbdp(rx_queue, bdp,
2813                                 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
2814
2815                 /* Update to the next pointer */
2816                 bdp++;
2817                 rxb++;
2818
2819                 if (unlikely(++i == rx_queue->rx_ring_size)) {
2820                         i = 0;
2821                         bdp = rx_queue->rx_bd_base;
2822                         rxb = rx_queue->rx_buff;
2823                 }
2824         }
2825
2826         rx_queue->next_to_use = i;
2827         rx_queue->next_to_alloc = i;
2828 }
2829
2830 static void count_errors(u32 lstatus, struct net_device *ndev)
2831 {
2832         struct gfar_private *priv = netdev_priv(ndev);
2833         struct net_device_stats *stats = &ndev->stats;
2834         struct gfar_extra_stats *estats = &priv->extra_stats;
2835
2836         /* If the packet was truncated, none of the other errors matter */
2837         if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2838                 stats->rx_length_errors++;
2839
2840                 atomic64_inc(&estats->rx_trunc);
2841
2842                 return;
2843         }
2844         /* Count the errors, if there were any */
2845         if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2846                 stats->rx_length_errors++;
2847
2848                 if (lstatus & BD_LFLAG(RXBD_LARGE))
2849                         atomic64_inc(&estats->rx_large);
2850                 else
2851                         atomic64_inc(&estats->rx_short);
2852         }
2853         if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2854                 stats->rx_frame_errors++;
2855                 atomic64_inc(&estats->rx_nonoctet);
2856         }
2857         if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2858                 atomic64_inc(&estats->rx_crcerr);
2859                 stats->rx_crc_errors++;
2860         }
2861         if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2862                 atomic64_inc(&estats->rx_overrun);
2863                 stats->rx_over_errors++;
2864         }
2865 }
2866
2867 irqreturn_t gfar_receive(int irq, void *grp_id)
2868 {
2869         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2870         unsigned long flags;
2871         u32 imask, ievent;
2872
2873         ievent = gfar_read(&grp->regs->ievent);
2874
2875         if (unlikely(ievent & IEVENT_FGPI)) {
2876                 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2877                 return IRQ_HANDLED;
2878         }
2879
2880         if (likely(napi_schedule_prep(&grp->napi_rx))) {
2881                 spin_lock_irqsave(&grp->grplock, flags);
2882                 imask = gfar_read(&grp->regs->imask);
2883                 imask &= IMASK_RX_DISABLED;
2884                 gfar_write(&grp->regs->imask, imask);
2885                 spin_unlock_irqrestore(&grp->grplock, flags);
2886                 __napi_schedule(&grp->napi_rx);
2887         } else {
2888                 /* Clear IEVENT, so interrupts aren't called again
2889                  * because of the packets that have already arrived.
2890                  */
2891                 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2892         }
2893
2894         return IRQ_HANDLED;
2895 }
2896
2897 /* Interrupt Handler for Transmit complete */
2898 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2899 {
2900         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2901         unsigned long flags;
2902         u32 imask;
2903
2904         if (likely(napi_schedule_prep(&grp->napi_tx))) {
2905                 spin_lock_irqsave(&grp->grplock, flags);
2906                 imask = gfar_read(&grp->regs->imask);
2907                 imask &= IMASK_TX_DISABLED;
2908                 gfar_write(&grp->regs->imask, imask);
2909                 spin_unlock_irqrestore(&grp->grplock, flags);
2910                 __napi_schedule(&grp->napi_tx);
2911         } else {
2912                 /* Clear IEVENT, so interrupts aren't called again
2913                  * because of the packets that have already arrived.
2914                  */
2915                 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2916         }
2917
2918         return IRQ_HANDLED;
2919 }
2920
2921 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2922                              struct sk_buff *skb, bool first)
2923 {
2924         unsigned int size = lstatus & BD_LENGTH_MASK;
2925         struct page *page = rxb->page;
2926
2927         /* Remove the FCS from the packet length */
2928         if (likely(lstatus & BD_LFLAG(RXBD_LAST)))
2929                 size -= ETH_FCS_LEN;
2930
2931         if (likely(first))
2932                 skb_put(skb, size);
2933         else
2934                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2935                                 rxb->page_offset + RXBUF_ALIGNMENT,
2936                                 size, GFAR_RXB_TRUESIZE);
2937
2938         /* try reuse page */
2939         if (unlikely(page_count(page) != 1))
2940                 return false;
2941
2942         /* change offset to the other half */
2943         rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2944
2945         atomic_inc(&page->_count);
2946
2947         return true;
2948 }
2949
2950 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2951                                struct gfar_rx_buff *old_rxb)
2952 {
2953         struct gfar_rx_buff *new_rxb;
2954         u16 nta = rxq->next_to_alloc;
2955
2956         new_rxb = &rxq->rx_buff[nta];
2957
2958         /* find next buf that can reuse a page */
2959         nta++;
2960         rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2961
2962         /* copy page reference */
2963         *new_rxb = *old_rxb;
2964
2965         /* sync for use by the device */
2966         dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2967                                          old_rxb->page_offset,
2968                                          GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2969 }
2970
2971 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2972                                             u32 lstatus, struct sk_buff *skb)
2973 {
2974         struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2975         struct page *page = rxb->page;
2976         bool first = false;
2977
2978         if (likely(!skb)) {
2979                 void *buff_addr = page_address(page) + rxb->page_offset;
2980
2981                 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2982                 if (unlikely(!skb)) {
2983                         gfar_rx_alloc_err(rx_queue);
2984                         return NULL;
2985                 }
2986                 skb_reserve(skb, RXBUF_ALIGNMENT);
2987                 first = true;
2988         }
2989
2990         dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2991                                       GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2992
2993         if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2994                 /* reuse the free half of the page */
2995                 gfar_reuse_rx_page(rx_queue, rxb);
2996         } else {
2997                 /* page cannot be reused, unmap it */
2998                 dma_unmap_page(rx_queue->dev, rxb->dma,
2999                                PAGE_SIZE, DMA_FROM_DEVICE);
3000         }
3001
3002         /* clear rxb content */
3003         rxb->page = NULL;
3004
3005         return skb;
3006 }
3007
3008 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
3009 {
3010         /* If valid headers were found, and valid sums
3011          * were verified, then we tell the kernel that no
3012          * checksumming is necessary.  Otherwise, it is [FIXME]
3013          */
3014         if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
3015             (RXFCB_CIP | RXFCB_CTU))
3016                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3017         else
3018                 skb_checksum_none_assert(skb);
3019 }
3020
3021 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
3022 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
3023 {
3024         struct gfar_private *priv = netdev_priv(ndev);
3025         struct rxfcb *fcb = NULL;
3026
3027         /* fcb is at the beginning if exists */
3028         fcb = (struct rxfcb *)skb->data;
3029
3030         /* Remove the FCB from the skb
3031          * Remove the padded bytes, if there are any
3032          */
3033         if (priv->uses_rxfcb)
3034                 skb_pull(skb, GMAC_FCB_LEN);
3035
3036         /* Get receive timestamp from the skb */
3037         if (priv->hwts_rx_en) {
3038                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
3039                 u64 *ns = (u64 *) skb->data;
3040
3041                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3042                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
3043         }
3044
3045         if (priv->padding)
3046                 skb_pull(skb, priv->padding);
3047
3048         if (ndev->features & NETIF_F_RXCSUM)
3049                 gfar_rx_checksum(skb, fcb);
3050
3051         /* Tell the skb what kind of packet this is */
3052         skb->protocol = eth_type_trans(skb, ndev);
3053
3054         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
3055          * Even if vlan rx accel is disabled, on some chips
3056          * RXFCB_VLN is pseudo randomly set.
3057          */
3058         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
3059             be16_to_cpu(fcb->flags) & RXFCB_VLN)
3060                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3061                                        be16_to_cpu(fcb->vlctl));
3062 }
3063
3064 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
3065  * until the budget/quota has been reached. Returns the number
3066  * of frames handled
3067  */
3068 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
3069 {
3070         struct net_device *ndev = rx_queue->ndev;
3071         struct gfar_private *priv = netdev_priv(ndev);
3072         struct rxbd8 *bdp;
3073         int i, howmany = 0;
3074         struct sk_buff *skb = rx_queue->skb;
3075         int cleaned_cnt = gfar_rxbd_unused(rx_queue);
3076         unsigned int total_bytes = 0, total_pkts = 0;
3077
3078         /* Get the first full descriptor */
3079         i = rx_queue->next_to_clean;
3080
3081         while (rx_work_limit--) {
3082                 u32 lstatus;
3083
3084                 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
3085                         gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3086                         cleaned_cnt = 0;
3087                 }
3088
3089                 bdp = &rx_queue->rx_bd_base[i];
3090                 lstatus = be32_to_cpu(bdp->lstatus);
3091                 if (lstatus & BD_LFLAG(RXBD_EMPTY))
3092                         break;
3093
3094                 /* order rx buffer descriptor reads */
3095                 rmb();
3096
3097                 /* fetch next to clean buffer from the ring */
3098                 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
3099                 if (unlikely(!skb))
3100                         break;
3101
3102                 cleaned_cnt++;
3103                 howmany++;
3104
3105                 if (unlikely(++i == rx_queue->rx_ring_size))
3106                         i = 0;
3107
3108                 rx_queue->next_to_clean = i;
3109
3110                 /* fetch next buffer if not the last in frame */
3111                 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
3112                         continue;
3113
3114                 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
3115                         count_errors(lstatus, ndev);
3116
3117                         /* discard faulty buffer */
3118                         dev_kfree_skb(skb);
3119                         skb = NULL;
3120                         rx_queue->stats.rx_dropped++;
3121                         continue;
3122                 }
3123
3124                 /* Increment the number of packets */
3125                 total_pkts++;
3126                 total_bytes += skb->len;
3127
3128                 skb_record_rx_queue(skb, rx_queue->qindex);
3129
3130                 gfar_process_frame(ndev, skb);
3131
3132                 /* Send the packet up the stack */
3133                 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
3134
3135                 skb = NULL;
3136         }
3137
3138         /* Store incomplete frames for completion */
3139         rx_queue->skb = skb;
3140
3141         rx_queue->stats.rx_packets += total_pkts;
3142         rx_queue->stats.rx_bytes += total_bytes;
3143
3144         if (cleaned_cnt)
3145                 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3146
3147         /* Update Last Free RxBD pointer for LFC */
3148         if (unlikely(priv->tx_actual_en)) {
3149                 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3150
3151                 gfar_write(rx_queue->rfbptr, bdp_dma);
3152         }
3153
3154         return howmany;
3155 }
3156
3157 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
3158 {
3159         struct gfar_priv_grp *gfargrp =
3160                 container_of(napi, struct gfar_priv_grp, napi_rx);
3161         struct gfar __iomem *regs = gfargrp->regs;
3162         struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
3163         int work_done = 0;
3164
3165         /* Clear IEVENT, so interrupts aren't called again
3166          * because of the packets that have already arrived
3167          */
3168         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3169
3170         work_done = gfar_clean_rx_ring(rx_queue, budget);
3171
3172         if (work_done < budget) {
3173                 u32 imask;
3174                 napi_complete(napi);
3175                 /* Clear the halt bit in RSTAT */
3176                 gfar_write(&regs->rstat, gfargrp->rstat);
3177
3178                 spin_lock_irq(&gfargrp->grplock);
3179                 imask = gfar_read(&regs->imask);
3180                 imask |= IMASK_RX_DEFAULT;
3181                 gfar_write(&regs->imask, imask);
3182                 spin_unlock_irq(&gfargrp->grplock);
3183         }
3184
3185         return work_done;
3186 }
3187
3188 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3189 {
3190         struct gfar_priv_grp *gfargrp =
3191                 container_of(napi, struct gfar_priv_grp, napi_tx);
3192         struct gfar __iomem *regs = gfargrp->regs;
3193         struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3194         u32 imask;
3195
3196         /* Clear IEVENT, so interrupts aren't called again
3197          * because of the packets that have already arrived
3198          */
3199         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3200
3201         /* run Tx cleanup to completion */
3202         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3203                 gfar_clean_tx_ring(tx_queue);
3204
3205         napi_complete(napi);
3206
3207         spin_lock_irq(&gfargrp->grplock);
3208         imask = gfar_read(&regs->imask);
3209         imask |= IMASK_TX_DEFAULT;
3210         gfar_write(&regs->imask, imask);
3211         spin_unlock_irq(&gfargrp->grplock);
3212
3213         return 0;
3214 }
3215
3216 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3217 {
3218         struct gfar_priv_grp *gfargrp =
3219                 container_of(napi, struct gfar_priv_grp, napi_rx);
3220         struct gfar_private *priv = gfargrp->priv;
3221         struct gfar __iomem *regs = gfargrp->regs;
3222         struct gfar_priv_rx_q *rx_queue = NULL;
3223         int work_done = 0, work_done_per_q = 0;
3224         int i, budget_per_q = 0;
3225         unsigned long rstat_rxf;
3226         int num_act_queues;
3227
3228         /* Clear IEVENT, so interrupts aren't called again
3229          * because of the packets that have already arrived
3230          */
3231         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3232
3233         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3234
3235         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3236         if (num_act_queues)
3237                 budget_per_q = budget/num_act_queues;
3238
3239         for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3240                 /* skip queue if not active */
3241                 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3242                         continue;
3243
3244                 rx_queue = priv->rx_queue[i];
3245                 work_done_per_q =
3246                         gfar_clean_rx_ring(rx_queue, budget_per_q);
3247                 work_done += work_done_per_q;
3248
3249                 /* finished processing this queue */
3250                 if (work_done_per_q < budget_per_q) {
3251                         /* clear active queue hw indication */
3252                         gfar_write(&regs->rstat,
3253                                    RSTAT_CLEAR_RXF0 >> i);
3254                         num_act_queues--;
3255
3256                         if (!num_act_queues)
3257                                 break;
3258                 }
3259         }
3260
3261         if (!num_act_queues) {
3262                 u32 imask;
3263                 napi_complete(napi);
3264
3265                 /* Clear the halt bit in RSTAT */
3266                 gfar_write(&regs->rstat, gfargrp->rstat);
3267
3268                 spin_lock_irq(&gfargrp->grplock);
3269                 imask = gfar_read(&regs->imask);
3270                 imask |= IMASK_RX_DEFAULT;
3271                 gfar_write(&regs->imask, imask);
3272                 spin_unlock_irq(&gfargrp->grplock);
3273         }
3274
3275         return work_done;
3276 }
3277
3278 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3279 {
3280         struct gfar_priv_grp *gfargrp =
3281                 container_of(napi, struct gfar_priv_grp, napi_tx);
3282         struct gfar_private *priv = gfargrp->priv;
3283         struct gfar __iomem *regs = gfargrp->regs;
3284         struct gfar_priv_tx_q *tx_queue = NULL;
3285         int has_tx_work = 0;
3286         int i;
3287
3288         /* Clear IEVENT, so interrupts aren't called again
3289          * because of the packets that have already arrived
3290          */
3291         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3292
3293         for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3294                 tx_queue = priv->tx_queue[i];
3295                 /* run Tx cleanup to completion */
3296                 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3297                         gfar_clean_tx_ring(tx_queue);
3298                         has_tx_work = 1;
3299                 }
3300         }
3301
3302         if (!has_tx_work) {
3303                 u32 imask;
3304                 napi_complete(napi);
3305
3306                 spin_lock_irq(&gfargrp->grplock);
3307                 imask = gfar_read(&regs->imask);
3308                 imask |= IMASK_TX_DEFAULT;
3309                 gfar_write(&regs->imask, imask);
3310                 spin_unlock_irq(&gfargrp->grplock);
3311         }
3312
3313         return 0;
3314 }
3315
3316
3317 #ifdef CONFIG_NET_POLL_CONTROLLER
3318 /* Polling 'interrupt' - used by things like netconsole to send skbs
3319  * without having to re-enable interrupts. It's not called while
3320  * the interrupt routine is executing.
3321  */
3322 static void gfar_netpoll(struct net_device *dev)
3323 {
3324         struct gfar_private *priv = netdev_priv(dev);
3325         int i;
3326
3327         /* If the device has multiple interrupts, run tx/rx */
3328         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3329                 for (i = 0; i < priv->num_grps; i++) {
3330                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3331
3332                         disable_irq(gfar_irq(grp, TX)->irq);
3333                         disable_irq(gfar_irq(grp, RX)->irq);
3334                         disable_irq(gfar_irq(grp, ER)->irq);
3335                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3336                         enable_irq(gfar_irq(grp, ER)->irq);
3337                         enable_irq(gfar_irq(grp, RX)->irq);
3338                         enable_irq(gfar_irq(grp, TX)->irq);
3339                 }
3340         } else {
3341                 for (i = 0; i < priv->num_grps; i++) {
3342                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3343
3344                         disable_irq(gfar_irq(grp, TX)->irq);
3345                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3346                         enable_irq(gfar_irq(grp, TX)->irq);
3347                 }
3348         }
3349 }
3350 #endif
3351
3352 /* The interrupt handler for devices with one interrupt */
3353 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3354 {
3355         struct gfar_priv_grp *gfargrp = grp_id;
3356
3357         /* Save ievent for future reference */
3358         u32 events = gfar_read(&gfargrp->regs->ievent);
3359
3360         /* Check for reception */
3361         if (events & IEVENT_RX_MASK)
3362                 gfar_receive(irq, grp_id);
3363
3364         /* Check for transmit completion */
3365         if (events & IEVENT_TX_MASK)
3366                 gfar_transmit(irq, grp_id);
3367
3368         /* Check for errors */
3369         if (events & IEVENT_ERR_MASK)
3370                 gfar_error(irq, grp_id);
3371
3372         return IRQ_HANDLED;
3373 }
3374
3375 /* Called every time the controller might need to be made
3376  * aware of new link state.  The PHY code conveys this
3377  * information through variables in the phydev structure, and this
3378  * function converts those variables into the appropriate
3379  * register values, and can bring down the device if needed.
3380  */
3381 static void adjust_link(struct net_device *dev)
3382 {
3383         struct gfar_private *priv = netdev_priv(dev);
3384         struct phy_device *phydev = priv->phydev;
3385
3386         if (unlikely(phydev->link != priv->oldlink ||
3387                      (phydev->link && (phydev->duplex != priv->oldduplex ||
3388                                        phydev->speed != priv->oldspeed))))
3389                 gfar_update_link_state(priv);
3390 }
3391
3392 /* Update the hash table based on the current list of multicast
3393  * addresses we subscribe to.  Also, change the promiscuity of
3394  * the device based on the flags (this function is called
3395  * whenever dev->flags is changed
3396  */
3397 static void gfar_set_multi(struct net_device *dev)
3398 {
3399         struct netdev_hw_addr *ha;
3400         struct gfar_private *priv = netdev_priv(dev);
3401         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3402         u32 tempval;
3403
3404         if (dev->flags & IFF_PROMISC) {
3405                 /* Set RCTRL to PROM */
3406                 tempval = gfar_read(&regs->rctrl);
3407                 tempval |= RCTRL_PROM;
3408                 gfar_write(&regs->rctrl, tempval);
3409         } else {
3410                 /* Set RCTRL to not PROM */
3411                 tempval = gfar_read(&regs->rctrl);
3412                 tempval &= ~(RCTRL_PROM);
3413                 gfar_write(&regs->rctrl, tempval);
3414         }
3415
3416         if (dev->flags & IFF_ALLMULTI) {
3417                 /* Set the hash to rx all multicast frames */
3418                 gfar_write(&regs->igaddr0, 0xffffffff);
3419                 gfar_write(&regs->igaddr1, 0xffffffff);
3420                 gfar_write(&regs->igaddr2, 0xffffffff);
3421                 gfar_write(&regs->igaddr3, 0xffffffff);
3422                 gfar_write(&regs->igaddr4, 0xffffffff);
3423                 gfar_write(&regs->igaddr5, 0xffffffff);
3424                 gfar_write(&regs->igaddr6, 0xffffffff);
3425                 gfar_write(&regs->igaddr7, 0xffffffff);
3426                 gfar_write(&regs->gaddr0, 0xffffffff);
3427                 gfar_write(&regs->gaddr1, 0xffffffff);
3428                 gfar_write(&regs->gaddr2, 0xffffffff);
3429                 gfar_write(&regs->gaddr3, 0xffffffff);
3430                 gfar_write(&regs->gaddr4, 0xffffffff);
3431                 gfar_write(&regs->gaddr5, 0xffffffff);
3432                 gfar_write(&regs->gaddr6, 0xffffffff);
3433                 gfar_write(&regs->gaddr7, 0xffffffff);
3434         } else {
3435                 int em_num;
3436                 int idx;
3437
3438                 /* zero out the hash */
3439                 gfar_write(&regs->igaddr0, 0x0);
3440                 gfar_write(&regs->igaddr1, 0x0);
3441                 gfar_write(&regs->igaddr2, 0x0);
3442                 gfar_write(&regs->igaddr3, 0x0);
3443                 gfar_write(&regs->igaddr4, 0x0);
3444                 gfar_write(&regs->igaddr5, 0x0);
3445                 gfar_write(&regs->igaddr6, 0x0);
3446                 gfar_write(&regs->igaddr7, 0x0);
3447                 gfar_write(&regs->gaddr0, 0x0);
3448                 gfar_write(&regs->gaddr1, 0x0);
3449                 gfar_write(&regs->gaddr2, 0x0);
3450                 gfar_write(&regs->gaddr3, 0x0);
3451                 gfar_write(&regs->gaddr4, 0x0);
3452                 gfar_write(&regs->gaddr5, 0x0);
3453                 gfar_write(&regs->gaddr6, 0x0);
3454                 gfar_write(&regs->gaddr7, 0x0);
3455
3456                 /* If we have extended hash tables, we need to
3457                  * clear the exact match registers to prepare for
3458                  * setting them
3459                  */
3460                 if (priv->extended_hash) {
3461                         em_num = GFAR_EM_NUM + 1;
3462                         gfar_clear_exact_match(dev);
3463                         idx = 1;
3464                 } else {
3465                         idx = 0;
3466                         em_num = 0;
3467                 }
3468
3469                 if (netdev_mc_empty(dev))
3470                         return;
3471
3472                 /* Parse the list, and set the appropriate bits */
3473                 netdev_for_each_mc_addr(ha, dev) {
3474                         if (idx < em_num) {
3475                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3476                                 idx++;
3477                         } else
3478                                 gfar_set_hash_for_addr(dev, ha->addr);
3479                 }
3480         }
3481 }
3482
3483
3484 /* Clears each of the exact match registers to zero, so they
3485  * don't interfere with normal reception
3486  */
3487 static void gfar_clear_exact_match(struct net_device *dev)
3488 {
3489         int idx;
3490         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3491
3492         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3493                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3494 }
3495
3496 /* Set the appropriate hash bit for the given addr */
3497 /* The algorithm works like so:
3498  * 1) Take the Destination Address (ie the multicast address), and
3499  * do a CRC on it (little endian), and reverse the bits of the
3500  * result.
3501  * 2) Use the 8 most significant bits as a hash into a 256-entry
3502  * table.  The table is controlled through 8 32-bit registers:
3503  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3504  * gaddr7.  This means that the 3 most significant bits in the
3505  * hash index which gaddr register to use, and the 5 other bits
3506  * indicate which bit (assuming an IBM numbering scheme, which
3507  * for PowerPC (tm) is usually the case) in the register holds
3508  * the entry.
3509  */
3510 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3511 {
3512         u32 tempval;
3513         struct gfar_private *priv = netdev_priv(dev);
3514         u32 result = ether_crc(ETH_ALEN, addr);
3515         int width = priv->hash_width;
3516         u8 whichbit = (result >> (32 - width)) & 0x1f;
3517         u8 whichreg = result >> (32 - width + 5);
3518         u32 value = (1 << (31-whichbit));
3519
3520         tempval = gfar_read(priv->hash_regs[whichreg]);
3521         tempval |= value;
3522         gfar_write(priv->hash_regs[whichreg], tempval);
3523 }
3524
3525
3526 /* There are multiple MAC Address register pairs on some controllers
3527  * This function sets the numth pair to a given address
3528  */
3529 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3530                                   const u8 *addr)
3531 {
3532         struct gfar_private *priv = netdev_priv(dev);
3533         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3534         u32 tempval;
3535         u32 __iomem *macptr = &regs->macstnaddr1;
3536
3537         macptr += num*2;
3538
3539         /* For a station address of 0x12345678ABCD in transmission
3540          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3541          * MACnADDR2 is set to 0x34120000.
3542          */
3543         tempval = (addr[5] << 24) | (addr[4] << 16) |
3544                   (addr[3] << 8)  |  addr[2];
3545
3546         gfar_write(macptr, tempval);
3547
3548         tempval = (addr[1] << 24) | (addr[0] << 16);
3549
3550         gfar_write(macptr+1, tempval);
3551 }
3552
3553 /* GFAR error interrupt handler */
3554 static irqreturn_t gfar_error(int irq, void *grp_id)
3555 {
3556         struct gfar_priv_grp *gfargrp = grp_id;
3557         struct gfar __iomem *regs = gfargrp->regs;
3558         struct gfar_private *priv= gfargrp->priv;
3559         struct net_device *dev = priv->ndev;
3560
3561         /* Save ievent for future reference */
3562         u32 events = gfar_read(&regs->ievent);
3563
3564         /* Clear IEVENT */
3565         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3566
3567         /* Magic Packet is not an error. */
3568         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3569             (events & IEVENT_MAG))
3570                 events &= ~IEVENT_MAG;
3571
3572         /* Hmm... */
3573         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3574                 netdev_dbg(dev,
3575                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3576                            events, gfar_read(&regs->imask));
3577
3578         /* Update the error counters */
3579         if (events & IEVENT_TXE) {
3580                 dev->stats.tx_errors++;
3581
3582                 if (events & IEVENT_LC)
3583                         dev->stats.tx_window_errors++;
3584                 if (events & IEVENT_CRL)
3585                         dev->stats.tx_aborted_errors++;
3586                 if (events & IEVENT_XFUN) {
3587                         netif_dbg(priv, tx_err, dev,
3588                                   "TX FIFO underrun, packet dropped\n");
3589                         dev->stats.tx_dropped++;
3590                         atomic64_inc(&priv->extra_stats.tx_underrun);
3591
3592                         schedule_work(&priv->reset_task);
3593                 }
3594                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3595         }
3596         if (events & IEVENT_BSY) {
3597                 dev->stats.rx_over_errors++;
3598                 atomic64_inc(&priv->extra_stats.rx_bsy);
3599
3600                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3601                           gfar_read(&regs->rstat));
3602         }
3603         if (events & IEVENT_BABR) {
3604                 dev->stats.rx_errors++;
3605                 atomic64_inc(&priv->extra_stats.rx_babr);
3606
3607                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3608         }
3609         if (events & IEVENT_EBERR) {
3610                 atomic64_inc(&priv->extra_stats.eberr);
3611                 netif_dbg(priv, rx_err, dev, "bus error\n");
3612         }
3613         if (events & IEVENT_RXC)
3614                 netif_dbg(priv, rx_status, dev, "control frame\n");
3615
3616         if (events & IEVENT_BABT) {
3617                 atomic64_inc(&priv->extra_stats.tx_babt);
3618                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3619         }
3620         return IRQ_HANDLED;
3621 }
3622
3623 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3624 {
3625         struct phy_device *phydev = priv->phydev;
3626         u32 val = 0;
3627
3628         if (!phydev->duplex)
3629                 return val;
3630
3631         if (!priv->pause_aneg_en) {
3632                 if (priv->tx_pause_en)
3633                         val |= MACCFG1_TX_FLOW;
3634                 if (priv->rx_pause_en)
3635                         val |= MACCFG1_RX_FLOW;
3636         } else {
3637                 u16 lcl_adv, rmt_adv;
3638                 u8 flowctrl;
3639                 /* get link partner capabilities */
3640                 rmt_adv = 0;
3641                 if (phydev->pause)
3642                         rmt_adv = LPA_PAUSE_CAP;
3643                 if (phydev->asym_pause)
3644                         rmt_adv |= LPA_PAUSE_ASYM;
3645
3646                 lcl_adv = 0;
3647                 if (phydev->advertising & ADVERTISED_Pause)
3648                         lcl_adv |= ADVERTISE_PAUSE_CAP;
3649                 if (phydev->advertising & ADVERTISED_Asym_Pause)
3650                         lcl_adv |= ADVERTISE_PAUSE_ASYM;
3651
3652                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3653                 if (flowctrl & FLOW_CTRL_TX)
3654                         val |= MACCFG1_TX_FLOW;
3655                 if (flowctrl & FLOW_CTRL_RX)
3656                         val |= MACCFG1_RX_FLOW;
3657         }
3658
3659         return val;
3660 }
3661
3662 static noinline void gfar_update_link_state(struct gfar_private *priv)
3663 {
3664         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3665         struct phy_device *phydev = priv->phydev;
3666         struct gfar_priv_rx_q *rx_queue = NULL;
3667         int i;
3668
3669         if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3670                 return;
3671
3672         if (phydev->link) {
3673                 u32 tempval1 = gfar_read(&regs->maccfg1);
3674                 u32 tempval = gfar_read(&regs->maccfg2);
3675                 u32 ecntrl = gfar_read(&regs->ecntrl);
3676                 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
3677
3678                 if (phydev->duplex != priv->oldduplex) {
3679                         if (!(phydev->duplex))
3680                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3681                         else
3682                                 tempval |= MACCFG2_FULL_DUPLEX;
3683
3684                         priv->oldduplex = phydev->duplex;
3685                 }
3686
3687                 if (phydev->speed != priv->oldspeed) {
3688                         switch (phydev->speed) {
3689                         case 1000:
3690                                 tempval =
3691                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3692
3693                                 ecntrl &= ~(ECNTRL_R100);
3694                                 break;
3695                         case 100:
3696                         case 10:
3697                                 tempval =
3698                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3699
3700                                 /* Reduced mode distinguishes
3701                                  * between 10 and 100
3702                                  */
3703                                 if (phydev->speed == SPEED_100)
3704                                         ecntrl |= ECNTRL_R100;
3705                                 else
3706                                         ecntrl &= ~(ECNTRL_R100);
3707                                 break;
3708                         default:
3709                                 netif_warn(priv, link, priv->ndev,
3710                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3711                                            phydev->speed);
3712                                 break;
3713                         }
3714
3715                         priv->oldspeed = phydev->speed;
3716                 }
3717
3718                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3719                 tempval1 |= gfar_get_flowctrl_cfg(priv);
3720
3721                 /* Turn last free buffer recording on */
3722                 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3723                         for (i = 0; i < priv->num_rx_queues; i++) {
3724                                 u32 bdp_dma;
3725
3726                                 rx_queue = priv->rx_queue[i];
3727                                 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3728                                 gfar_write(rx_queue->rfbptr, bdp_dma);
3729                         }
3730
3731                         priv->tx_actual_en = 1;
3732                 }
3733
3734                 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3735                         priv->tx_actual_en = 0;
3736
3737                 gfar_write(&regs->maccfg1, tempval1);
3738                 gfar_write(&regs->maccfg2, tempval);
3739                 gfar_write(&regs->ecntrl, ecntrl);
3740
3741                 if (!priv->oldlink)
3742                         priv->oldlink = 1;
3743
3744         } else if (priv->oldlink) {
3745                 priv->oldlink = 0;
3746                 priv->oldspeed = 0;
3747                 priv->oldduplex = -1;
3748         }
3749
3750         if (netif_msg_link(priv))
3751                 phy_print_status(phydev);
3752 }
3753
3754 static const struct of_device_id gfar_match[] =
3755 {
3756         {
3757                 .type = "network",
3758                 .compatible = "gianfar",
3759         },
3760         {
3761                 .compatible = "fsl,etsec2",
3762         },
3763         {},
3764 };
3765 MODULE_DEVICE_TABLE(of, gfar_match);
3766
3767 /* Structure for a device driver */
3768 static struct platform_driver gfar_driver = {
3769         .driver = {
3770                 .name = "fsl-gianfar",
3771                 .pm = GFAR_PM_OPS,
3772                 .of_match_table = gfar_match,
3773         },
3774         .probe = gfar_probe,
3775         .remove = gfar_remove,
3776 };
3777
3778 module_platform_driver(gfar_driver);