drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * aQuantia Corporation Network Driver
   4  * Copyright (C) 2014-2019 aQuantia Corporation. All rights reserved
   5  */
   6
   7 /* File hw_atl_llh.c: Definitions of bitfield and register access functions for
   8  * Atlantic registers.
   9  */
  10
  11 #include "hw_atl_llh.h"
  12 #include "hw_atl_llh_internal.h"
  13 #include "../aq_hw_utils.h"
  14
  15 /* global */
  16 void hw_atl_reg_glb_cpu_sem_set(struct aq_hw_s *aq_hw, u32 glb_cpu_sem,
  17                                 u32 semaphore)
  18 {
  19         aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore), glb_cpu_sem);
  20 }
  21
  22 u32 hw_atl_reg_glb_cpu_sem_get(struct aq_hw_s *aq_hw, u32 semaphore)
  23 {
  24         return aq_hw_read_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore));
  25 }
  26
  27 void hw_atl_glb_glb_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 glb_reg_res_dis)
  28 {
  29         aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_REG_RES_DIS_ADR,
  30                             HW_ATL_GLB_REG_RES_DIS_MSK,
  31                             HW_ATL_GLB_REG_RES_DIS_SHIFT,
  32                             glb_reg_res_dis);
  33 }
  34
  35 void hw_atl_glb_soft_res_set(struct aq_hw_s *aq_hw, u32 soft_res)
  36 {
  37         aq_hw_write_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
  38                             HW_ATL_GLB_SOFT_RES_MSK,
  39                             HW_ATL_GLB_SOFT_RES_SHIFT, soft_res);
  40 }
  41
  42 u32 hw_atl_glb_soft_res_get(struct aq_hw_s *aq_hw)
  43 {
  44         return aq_hw_read_reg_bit(aq_hw, HW_ATL_GLB_SOFT_RES_ADR,
  45                                   HW_ATL_GLB_SOFT_RES_MSK,
  46                                   HW_ATL_GLB_SOFT_RES_SHIFT);
  47 }
  48
  49 u32 hw_atl_reg_glb_mif_id_get(struct aq_hw_s *aq_hw)
  50 {
  51         return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR);
  52 }
  53
  54 /* stats */
  55 u32 hw_atl_rpb_rx_dma_drop_pkt_cnt_get(struct aq_hw_s *aq_hw)
  56 {
  57         return aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR);
  58 }
  59
  60 u64 hw_atl_stats_rx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw)
  61 {
  62         return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW);
  63 }
  64
  65 u64 hw_atl_stats_rx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw)
  66 {
  67         return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW);
  68 }
  69
  70 u64 hw_atl_stats_tx_dma_good_octet_counter_get(struct aq_hw_s *aq_hw)
  71 {
  72         return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW);
  73 }
  74
  75 u64 hw_atl_stats_tx_dma_good_pkt_counter_get(struct aq_hw_s *aq_hw)
  76 {
  77         return aq_hw_read_reg64(aq_hw, HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW);
  78 }
  79
  80 /* interrupt */
  81 void hw_atl_itr_irq_auto_masklsw_set(struct aq_hw_s *aq_hw,
  82                                      u32 irq_auto_masklsw)
  83 {
  84         aq_hw_write_reg(aq_hw, HW_ATL_ITR_IAMRLSW_ADR, irq_auto_masklsw);
  85 }
  86
  87 void hw_atl_itr_irq_map_en_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_rx,
  88                                   u32 rx)
  89 {
  90 /* register address for bitfield imr_rx{r}_en */
  91         static u32 itr_imr_rxren_adr[32] = {
  92                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
  93                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
  94                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
  95                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
  96                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
  97                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
  98                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
  99                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 100                 };
 101
 102 /* bitmask for bitfield imr_rx{r}_en */
 103         static u32 itr_imr_rxren_msk[32] = {
 104                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 105                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 106                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 107                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 108                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 109                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 110                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U,
 111                         0x00008000U, 0x00000080U, 0x00008000U, 0x00000080U
 112                 };
 113
 114 /* lower bit position of bitfield imr_rx{r}_en */
 115         static u32 itr_imr_rxren_shift[32] = {
 116                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
 117                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
 118                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U,
 119                         15U, 7U, 15U, 7U, 15U, 7U, 15U, 7U
 120                 };
 121
 122         aq_hw_write_reg_bit(aq_hw, itr_imr_rxren_adr[rx],
 123                             itr_imr_rxren_msk[rx],
 124                             itr_imr_rxren_shift[rx],
 125                             irq_map_en_rx);
 126 }
 127
 128 void hw_atl_itr_irq_map_en_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_en_tx,
 129                                   u32 tx)
 130 {
 131 /* register address for bitfield imr_tx{t}_en */
 132         static u32 itr_imr_txten_adr[32] = {
 133                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 134                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 135                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 136                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 137                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 138                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 139                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 140                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 141                 };
 142
 143 /* bitmask for bitfield imr_tx{t}_en */
 144         static u32 itr_imr_txten_msk[32] = {
 145                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 146                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 147                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 148                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 149                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 150                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 151                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U,
 152                         0x80000000U, 0x00800000U, 0x80000000U, 0x00800000U
 153                 };
 154
 155 /* lower bit position of bitfield imr_tx{t}_en */
 156         static u32 itr_imr_txten_shift[32] = {
 157                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
 158                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
 159                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U,
 160                         31U, 23U, 31U, 23U, 31U, 23U, 31U, 23U
 161                 };
 162
 163         aq_hw_write_reg_bit(aq_hw, itr_imr_txten_adr[tx],
 164                             itr_imr_txten_msk[tx],
 165                             itr_imr_txten_shift[tx],
 166                             irq_map_en_tx);
 167 }
 168
 169 void hw_atl_itr_irq_map_rx_set(struct aq_hw_s *aq_hw, u32 irq_map_rx, u32 rx)
 170 {
 171 /* register address for bitfield imr_rx{r}[4:0] */
 172         static u32 itr_imr_rxr_adr[32] = {
 173                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 174                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 175                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 176                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 177                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 178                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 179                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 180                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 181                 };
 182
 183 /* bitmask for bitfield imr_rx{r}[4:0] */
 184         static u32 itr_imr_rxr_msk[32] = {
 185                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 186                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 187                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 188                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 189                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 190                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 191                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU,
 192                         0x00001f00U, 0x0000001FU, 0x00001F00U, 0x0000001FU
 193                 };
 194
 195 /* lower bit position of bitfield imr_rx{r}[4:0] */
 196         static u32 itr_imr_rxr_shift[32] = {
 197                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
 198                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
 199                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U,
 200                         8U, 0U, 8U, 0U, 8U, 0U, 8U, 0U
 201                 };
 202
 203         aq_hw_write_reg_bit(aq_hw, itr_imr_rxr_adr[rx],
 204                             itr_imr_rxr_msk[rx],
 205                             itr_imr_rxr_shift[rx],
 206                             irq_map_rx);
 207 }
 208
 209 void hw_atl_itr_irq_map_tx_set(struct aq_hw_s *aq_hw, u32 irq_map_tx, u32 tx)
 210 {
 211 /* register address for bitfield imr_tx{t}[4:0] */
 212         static u32 itr_imr_txt_adr[32] = {
 213                         0x00002100U, 0x00002100U, 0x00002104U, 0x00002104U,
 214                         0x00002108U, 0x00002108U, 0x0000210CU, 0x0000210CU,
 215                         0x00002110U, 0x00002110U, 0x00002114U, 0x00002114U,
 216                         0x00002118U, 0x00002118U, 0x0000211CU, 0x0000211CU,
 217                         0x00002120U, 0x00002120U, 0x00002124U, 0x00002124U,
 218                         0x00002128U, 0x00002128U, 0x0000212CU, 0x0000212CU,
 219                         0x00002130U, 0x00002130U, 0x00002134U, 0x00002134U,
 220                         0x00002138U, 0x00002138U, 0x0000213CU, 0x0000213CU
 221                 };
 222
 223 /* bitmask for bitfield imr_tx{t}[4:0] */
 224         static u32 itr_imr_txt_msk[32] = {
 225                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 226                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 227                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 228                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 229                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 230                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 231                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U,
 232                         0x1f000000U, 0x001F0000U, 0x1F000000U, 0x001F0000U
 233                 };
 234
 235 /* lower bit position of bitfield imr_tx{t}[4:0] */
 236         static u32 itr_imr_txt_shift[32] = {
 237                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
 238                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
 239                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U,
 240                         24U, 16U, 24U, 16U, 24U, 16U, 24U, 16U
 241                 };
 242
 243         aq_hw_write_reg_bit(aq_hw, itr_imr_txt_adr[tx],
 244                             itr_imr_txt_msk[tx],
 245                             itr_imr_txt_shift[tx],
 246                             irq_map_tx);
 247 }
 248
 249 void hw_atl_itr_irq_msk_clearlsw_set(struct aq_hw_s *aq_hw,
 250                                      u32 irq_msk_clearlsw)
 251 {
 252         aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMCRLSW_ADR, irq_msk_clearlsw);
 253 }
 254
 255 void hw_atl_itr_irq_msk_setlsw_set(struct aq_hw_s *aq_hw, u32 irq_msk_setlsw)
 256 {
 257         aq_hw_write_reg(aq_hw, HW_ATL_ITR_IMSRLSW_ADR, irq_msk_setlsw);
 258 }
 259
 260 void hw_atl_itr_irq_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 irq_reg_res_dis)
 261 {
 262         aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_REG_RES_DSBL_ADR,
 263                             HW_ATL_ITR_REG_RES_DSBL_MSK,
 264                             HW_ATL_ITR_REG_RES_DSBL_SHIFT, irq_reg_res_dis);
 265 }
 266
 267 void hw_atl_itr_irq_status_clearlsw_set(struct aq_hw_s *aq_hw,
 268                                         u32 irq_status_clearlsw)
 269 {
 270         aq_hw_write_reg(aq_hw, HW_ATL_ITR_ISCRLSW_ADR, irq_status_clearlsw);
 271 }
 272
 273 u32 hw_atl_itr_irq_statuslsw_get(struct aq_hw_s *aq_hw)
 274 {
 275         return aq_hw_read_reg(aq_hw, HW_ATL_ITR_ISRLSW_ADR);
 276 }
 277
 278 u32 hw_atl_itr_res_irq_get(struct aq_hw_s *aq_hw)
 279 {
 280         return aq_hw_read_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
 281                                   HW_ATL_ITR_RES_SHIFT);
 282 }
 283
 284 void hw_atl_itr_res_irq_set(struct aq_hw_s *aq_hw, u32 res_irq)
 285 {
 286         aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RES_ADR, HW_ATL_ITR_RES_MSK,
 287                             HW_ATL_ITR_RES_SHIFT, res_irq);
 288 }
 289
 290 /* set RSC interrupt */
 291 void hw_atl_itr_rsc_en_set(struct aq_hw_s *aq_hw, u32 enable)
 292 {
 293         aq_hw_write_reg(aq_hw, HW_ATL_ITR_RSC_EN_ADR, enable);
 294 }
 295
 296 /* set RSC delay */
 297 void hw_atl_itr_rsc_delay_set(struct aq_hw_s *aq_hw, u32 delay)
 298 {
 299         aq_hw_write_reg_bit(aq_hw, HW_ATL_ITR_RSC_DELAY_ADR,
 300                             HW_ATL_ITR_RSC_DELAY_MSK,
 301                             HW_ATL_ITR_RSC_DELAY_SHIFT,
 302                             delay);
 303 }
 304
 305 /* rdm */
 306 void hw_atl_rdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
 307 {
 308         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADCPUID_ADR(dca),
 309                             HW_ATL_RDM_DCADCPUID_MSK,
 310                             HW_ATL_RDM_DCADCPUID_SHIFT, cpuid);
 311 }
 312
 313 void hw_atl_rdm_rx_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_dca_en)
 314 {
 315         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_EN_ADR, HW_ATL_RDM_DCA_EN_MSK,
 316                             HW_ATL_RDM_DCA_EN_SHIFT, rx_dca_en);
 317 }
 318
 319 void hw_atl_rdm_rx_dca_mode_set(struct aq_hw_s *aq_hw, u32 rx_dca_mode)
 320 {
 321         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCA_MODE_ADR,
 322                             HW_ATL_RDM_DCA_MODE_MSK,
 323                             HW_ATL_RDM_DCA_MODE_SHIFT, rx_dca_mode);
 324 }
 325
 326 void hw_atl_rdm_rx_desc_data_buff_size_set(struct aq_hw_s *aq_hw,
 327                                            u32 rx_desc_data_buff_size,
 328                                            u32 descriptor)
 329 {
 330         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor),
 331                             HW_ATL_RDM_DESCDDATA_SIZE_MSK,
 332                             HW_ATL_RDM_DESCDDATA_SIZE_SHIFT,
 333                             rx_desc_data_buff_size);
 334 }
 335
 336 void hw_atl_rdm_rx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_dca_en,
 337                                    u32 dca)
 338 {
 339         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADDESC_EN_ADR(dca),
 340                             HW_ATL_RDM_DCADDESC_EN_MSK,
 341                             HW_ATL_RDM_DCADDESC_EN_SHIFT,
 342                             rx_desc_dca_en);
 343 }
 344
 345 void hw_atl_rdm_rx_desc_en_set(struct aq_hw_s *aq_hw, u32 rx_desc_en,
 346                                u32 descriptor)
 347 {
 348         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDEN_ADR(descriptor),
 349                             HW_ATL_RDM_DESCDEN_MSK,
 350                             HW_ATL_RDM_DESCDEN_SHIFT,
 351                             rx_desc_en);
 352 }
 353
 354 void hw_atl_rdm_rx_desc_head_buff_size_set(struct aq_hw_s *aq_hw,
 355                                            u32 rx_desc_head_buff_size,
 356                                            u32 descriptor)
 357 {
 358         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor),
 359                             HW_ATL_RDM_DESCDHDR_SIZE_MSK,
 360                             HW_ATL_RDM_DESCDHDR_SIZE_SHIFT,
 361                             rx_desc_head_buff_size);
 362 }
 363
 364 void hw_atl_rdm_rx_desc_head_splitting_set(struct aq_hw_s *aq_hw,
 365                                            u32 rx_desc_head_splitting,
 366                                            u32 descriptor)
 367 {
 368         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor),
 369                             HW_ATL_RDM_DESCDHDR_SPLIT_MSK,
 370                             HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT,
 371                             rx_desc_head_splitting);
 372 }
 373
 374 u32 hw_atl_rdm_rx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
 375 {
 376         return aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_DESCDHD_ADR(descriptor),
 377                                   HW_ATL_RDM_DESCDHD_MSK,
 378                                   HW_ATL_RDM_DESCDHD_SHIFT);
 379 }
 380
 381 void hw_atl_rdm_rx_desc_len_set(struct aq_hw_s *aq_hw, u32 rx_desc_len,
 382                                 u32 descriptor)
 383 {
 384         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDLEN_ADR(descriptor),
 385                             HW_ATL_RDM_DESCDLEN_MSK, HW_ATL_RDM_DESCDLEN_SHIFT,
 386                             rx_desc_len);
 387 }
 388
 389 void hw_atl_rdm_rx_desc_res_set(struct aq_hw_s *aq_hw, u32 rx_desc_res,
 390                                 u32 descriptor)
 391 {
 392         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DESCDRESET_ADR(descriptor),
 393                             HW_ATL_RDM_DESCDRESET_MSK,
 394                             HW_ATL_RDM_DESCDRESET_SHIFT,
 395                             rx_desc_res);
 396 }
 397
 398 void hw_atl_rdm_rx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
 399                                          u32 rx_desc_wr_wb_irq_en)
 400 {
 401         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_DESC_WRB_EN_ADR,
 402                             HW_ATL_RDM_INT_DESC_WRB_EN_MSK,
 403                             HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT,
 404                             rx_desc_wr_wb_irq_en);
 405 }
 406
 407 void hw_atl_rdm_rx_head_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_head_dca_en,
 408                                    u32 dca)
 409 {
 410         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADHDR_EN_ADR(dca),
 411                             HW_ATL_RDM_DCADHDR_EN_MSK,
 412                             HW_ATL_RDM_DCADHDR_EN_SHIFT,
 413                             rx_head_dca_en);
 414 }
 415
 416 void hw_atl_rdm_rx_pld_dca_en_set(struct aq_hw_s *aq_hw, u32 rx_pld_dca_en,
 417                                   u32 dca)
 418 {
 419         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_DCADPAY_EN_ADR(dca),
 420                             HW_ATL_RDM_DCADPAY_EN_MSK,
 421                             HW_ATL_RDM_DCADPAY_EN_SHIFT,
 422                             rx_pld_dca_en);
 423 }
 424
 425 void hw_atl_rdm_rdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
 426                                       u32 rdm_intr_moder_en)
 427 {
 428         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_INT_RIM_EN_ADR,
 429                             HW_ATL_RDM_INT_RIM_EN_MSK,
 430                             HW_ATL_RDM_INT_RIM_EN_SHIFT,
 431                             rdm_intr_moder_en);
 432 }
 433
 434 /* reg */
 435 void hw_atl_reg_gen_irq_map_set(struct aq_hw_s *aq_hw, u32 gen_intr_map,
 436                                 u32 regidx)
 437 {
 438         aq_hw_write_reg(aq_hw, HW_ATL_GEN_INTR_MAP_ADR(regidx), gen_intr_map);
 439 }
 440
 441 u32 hw_atl_reg_gen_irq_status_get(struct aq_hw_s *aq_hw)
 442 {
 443         return aq_hw_read_reg(aq_hw, HW_ATL_GEN_INTR_STAT_ADR);
 444 }
 445
 446 void hw_atl_reg_irq_glb_ctl_set(struct aq_hw_s *aq_hw, u32 intr_glb_ctl)
 447 {
 448         aq_hw_write_reg(aq_hw, HW_ATL_INTR_GLB_CTL_ADR, intr_glb_ctl);
 449 }
 450
 451 void hw_atl_reg_irq_thr_set(struct aq_hw_s *aq_hw, u32 intr_thr, u32 throttle)
 452 {
 453         aq_hw_write_reg(aq_hw, HW_ATL_INTR_THR_ADR(throttle), intr_thr);
 454 }
 455
 456 void hw_atl_reg_rx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
 457                                                u32 rx_dma_desc_base_addrlsw,
 458                                                u32 descriptor)
 459 {
 460         aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
 461                         rx_dma_desc_base_addrlsw);
 462 }
 463
 464 void hw_atl_reg_rx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
 465                                                u32 rx_dma_desc_base_addrmsw,
 466                                                u32 descriptor)
 467 {
 468         aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
 469                         rx_dma_desc_base_addrmsw);
 470 }
 471
 472 u32 hw_atl_reg_rx_dma_desc_status_get(struct aq_hw_s *aq_hw, u32 descriptor)
 473 {
 474         return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor));
 475 }
 476
 477 void hw_atl_reg_rx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
 478                                          u32 rx_dma_desc_tail_ptr,
 479                                          u32 descriptor)
 480 {
 481         aq_hw_write_reg(aq_hw, HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor),
 482                         rx_dma_desc_tail_ptr);
 483 }
 484
 485 void hw_atl_reg_rx_flr_mcst_flr_msk_set(struct aq_hw_s *aq_hw,
 486                                         u32 rx_flr_mcst_flr_msk)
 487 {
 488         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_MSK_ADR,
 489                         rx_flr_mcst_flr_msk);
 490 }
 491
 492 void hw_atl_reg_rx_flr_mcst_flr_set(struct aq_hw_s *aq_hw, u32 rx_flr_mcst_flr,
 493                                     u32 filter)
 494 {
 495         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_MCST_FLR_ADR(filter),
 496                         rx_flr_mcst_flr);
 497 }
 498
 499 void hw_atl_reg_rx_flr_rss_control1set(struct aq_hw_s *aq_hw,
 500                                        u32 rx_flr_rss_control1)
 501 {
 502         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_RSS_CONTROL1_ADR,
 503                         rx_flr_rss_control1);
 504 }
 505
 506 void hw_atl_reg_rx_flr_control2_set(struct aq_hw_s *aq_hw,
 507                                     u32 rx_filter_control2)
 508 {
 509         aq_hw_write_reg(aq_hw, HW_ATL_RX_FLR_CONTROL2_ADR, rx_filter_control2);
 510 }
 511
 512 void hw_atl_reg_rx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
 513                                        u32 rx_intr_moderation_ctl,
 514                                        u32 queue)
 515 {
 516         aq_hw_write_reg(aq_hw, HW_ATL_RX_INTR_MODERATION_CTL_ADR(queue),
 517                         rx_intr_moderation_ctl);
 518 }
 519
 520 void hw_atl_reg_tx_dma_debug_ctl_set(struct aq_hw_s *aq_hw,
 521                                      u32 tx_dma_debug_ctl)
 522 {
 523         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DEBUG_CTL_ADR, tx_dma_debug_ctl);
 524 }
 525
 526 void hw_atl_reg_tx_dma_desc_base_addresslswset(struct aq_hw_s *aq_hw,
 527                                                u32 tx_dma_desc_base_addrlsw,
 528                                                u32 descriptor)
 529 {
 530         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor),
 531                         tx_dma_desc_base_addrlsw);
 532 }
 533
 534 void hw_atl_reg_tx_dma_desc_base_addressmswset(struct aq_hw_s *aq_hw,
 535                                                u32 tx_dma_desc_base_addrmsw,
 536                                                u32 descriptor)
 537 {
 538         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor),
 539                         tx_dma_desc_base_addrmsw);
 540 }
 541
 542 void hw_atl_reg_tx_dma_desc_tail_ptr_set(struct aq_hw_s *aq_hw,
 543                                          u32 tx_dma_desc_tail_ptr,
 544                                          u32 descriptor)
 545 {
 546         aq_hw_write_reg(aq_hw, HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor),
 547                         tx_dma_desc_tail_ptr);
 548 }
 549
 550 void hw_atl_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
 551                                        u32 tx_intr_moderation_ctl,
 552                                        u32 queue)
 553 {
 554         aq_hw_write_reg(aq_hw, HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue),
 555                         tx_intr_moderation_ctl);
 556 }
 557
 558 /* RPB: rx packet buffer */
 559 void hw_atl_rpb_dma_sys_lbk_set(struct aq_hw_s *aq_hw, u32 dma_sys_lbk)
 560 {
 561         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_SYS_LBK_ADR,
 562                             HW_ATL_RPB_DMA_SYS_LBK_MSK,
 563                             HW_ATL_RPB_DMA_SYS_LBK_SHIFT, dma_sys_lbk);
 564 }
 565
 566 void hw_atl_rpb_dma_net_lbk_set(struct aq_hw_s *aq_hw, u32 dma_net_lbk)
 567 {
 568         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_DMA_NET_LBK_ADR,
 569                             HW_ATL_RPB_DMA_NET_LBK_MSK,
 570                             HW_ATL_RPB_DMA_NET_LBK_SHIFT, dma_net_lbk);
 571 }
 572
 573 void hw_atl_rpb_rpf_rx_traf_class_mode_set(struct aq_hw_s *aq_hw,
 574                                            u32 rx_traf_class_mode)
 575 {
 576         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR,
 577                             HW_ATL_RPB_RPF_RX_TC_MODE_MSK,
 578                             HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT,
 579                             rx_traf_class_mode);
 580 }
 581
 582 u32 hw_atl_rpb_rpf_rx_traf_class_mode_get(struct aq_hw_s *aq_hw)
 583 {
 584         return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPB_RPF_RX_TC_MODE_ADR,
 585                         HW_ATL_RPB_RPF_RX_TC_MODE_MSK,
 586                         HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT);
 587 }
 588
 589 void hw_atl_rpb_rx_buff_en_set(struct aq_hw_s *aq_hw, u32 rx_buff_en)
 590 {
 591         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_BUF_EN_ADR,
 592                             HW_ATL_RPB_RX_BUF_EN_MSK,
 593                             HW_ATL_RPB_RX_BUF_EN_SHIFT, rx_buff_en);
 594 }
 595
 596 void hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
 597                                                 u32 rx_buff_hi_threshold_per_tc,
 598                                                 u32 buffer)
 599 {
 600         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBHI_THRESH_ADR(buffer),
 601                             HW_ATL_RPB_RXBHI_THRESH_MSK,
 602                             HW_ATL_RPB_RXBHI_THRESH_SHIFT,
 603                             rx_buff_hi_threshold_per_tc);
 604 }
 605
 606 void hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
 607                                                 u32 rx_buff_lo_threshold_per_tc,
 608                                                 u32 buffer)
 609 {
 610         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBLO_THRESH_ADR(buffer),
 611                             HW_ATL_RPB_RXBLO_THRESH_MSK,
 612                             HW_ATL_RPB_RXBLO_THRESH_SHIFT,
 613                             rx_buff_lo_threshold_per_tc);
 614 }
 615
 616 void hw_atl_rpb_rx_flow_ctl_mode_set(struct aq_hw_s *aq_hw, u32 rx_flow_ctl_mode)
 617 {
 618         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RX_FC_MODE_ADR,
 619                             HW_ATL_RPB_RX_FC_MODE_MSK,
 620                             HW_ATL_RPB_RX_FC_MODE_SHIFT, rx_flow_ctl_mode);
 621 }
 622
 623 void hw_atl_rdm_rx_dma_desc_cache_init_tgl(struct aq_hw_s *aq_hw)
 624 {
 625         u32 val;
 626
 627         val = aq_hw_read_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR,
 628                                  HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK,
 629                                  HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT);
 630
 631         aq_hw_write_reg_bit(aq_hw, HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR,
 632                             HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK,
 633                             HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT,
 634                             val ^ 1);
 635 }
 636
 637 u32 hw_atl_rdm_rx_dma_desc_cache_init_done_get(struct aq_hw_s *aq_hw)
 638 {
 639         return aq_hw_read_reg_bit(aq_hw, RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR,
 640                                   RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK,
 641                                   RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT);
 642 }
 643
 644 void hw_atl_rpb_rx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
 645                                             u32 rx_pkt_buff_size_per_tc, u32 buffer)
 646 {
 647         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer),
 648                             HW_ATL_RPB_RXBBUF_SIZE_MSK,
 649                             HW_ATL_RPB_RXBBUF_SIZE_SHIFT,
 650                             rx_pkt_buff_size_per_tc);
 651 }
 652
 653 void hw_atl_rpb_rx_xoff_en_per_tc_set(struct aq_hw_s *aq_hw,
 654                                       u32 rx_xoff_en_per_tc, u32 buffer)
 655 {
 656         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPB_RXBXOFF_EN_ADR(buffer),
 657                             HW_ATL_RPB_RXBXOFF_EN_MSK,
 658                             HW_ATL_RPB_RXBXOFF_EN_SHIFT,
 659                             rx_xoff_en_per_tc);
 660 }
 661
 662 /* rpf */
 663
 664 void hw_atl_rpfl2broadcast_count_threshold_set(struct aq_hw_s *aq_hw,
 665                                                u32 l2broadcast_count_threshold)
 666 {
 667         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_THRESH_ADR,
 668                             HW_ATL_RPFL2BC_THRESH_MSK,
 669                             HW_ATL_RPFL2BC_THRESH_SHIFT,
 670                             l2broadcast_count_threshold);
 671 }
 672
 673 void hw_atl_rpfl2broadcast_en_set(struct aq_hw_s *aq_hw, u32 l2broadcast_en)
 674 {
 675         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_EN_ADR, HW_ATL_RPFL2BC_EN_MSK,
 676                             HW_ATL_RPFL2BC_EN_SHIFT, l2broadcast_en);
 677 }
 678
 679 void hw_atl_rpfl2broadcast_flr_act_set(struct aq_hw_s *aq_hw,
 680                                        u32 l2broadcast_flr_act)
 681 {
 682         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2BC_ACT_ADR,
 683                             HW_ATL_RPFL2BC_ACT_MSK,
 684                             HW_ATL_RPFL2BC_ACT_SHIFT, l2broadcast_flr_act);
 685 }
 686
 687 void hw_atl_rpfl2multicast_flr_en_set(struct aq_hw_s *aq_hw,
 688                                       u32 l2multicast_flr_en,
 689                                       u32 filter)
 690 {
 691         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ENF_ADR(filter),
 692                             HW_ATL_RPFL2MC_ENF_MSK,
 693                             HW_ATL_RPFL2MC_ENF_SHIFT, l2multicast_flr_en);
 694 }
 695
 696 void hw_atl_rpfl2promiscuous_mode_en_set(struct aq_hw_s *aq_hw,
 697                                          u32 l2promiscuous_mode_en)
 698 {
 699         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2PROMIS_MODE_ADR,
 700                             HW_ATL_RPFL2PROMIS_MODE_MSK,
 701                             HW_ATL_RPFL2PROMIS_MODE_SHIFT,
 702                             l2promiscuous_mode_en);
 703 }
 704
 705 void hw_atl_rpfl2unicast_flr_act_set(struct aq_hw_s *aq_hw,
 706                                      u32 l2unicast_flr_act,
 707                                      u32 filter)
 708 {
 709         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ACTF_ADR(filter),
 710                             HW_ATL_RPFL2UC_ACTF_MSK, HW_ATL_RPFL2UC_ACTF_SHIFT,
 711                             l2unicast_flr_act);
 712 }
 713
 714 void hw_atl_rpfl2_uc_flr_en_set(struct aq_hw_s *aq_hw, u32 l2unicast_flr_en,
 715                                 u32 filter)
 716 {
 717         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_ENF_ADR(filter),
 718                             HW_ATL_RPFL2UC_ENF_MSK,
 719                             HW_ATL_RPFL2UC_ENF_SHIFT, l2unicast_flr_en);
 720 }
 721
 722 void hw_atl_rpfl2unicast_dest_addresslsw_set(struct aq_hw_s *aq_hw,
 723                                              u32 l2unicast_dest_addresslsw,
 724                                              u32 filter)
 725 {
 726         aq_hw_write_reg(aq_hw, HW_ATL_RPFL2UC_DAFLSW_ADR(filter),
 727                         l2unicast_dest_addresslsw);
 728 }
 729
 730 void hw_atl_rpfl2unicast_dest_addressmsw_set(struct aq_hw_s *aq_hw,
 731                                              u32 l2unicast_dest_addressmsw,
 732                                              u32 filter)
 733 {
 734         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2UC_DAFMSW_ADR(filter),
 735                             HW_ATL_RPFL2UC_DAFMSW_MSK,
 736                             HW_ATL_RPFL2UC_DAFMSW_SHIFT,
 737                             l2unicast_dest_addressmsw);
 738 }
 739
 740 void hw_atl_rpfl2_accept_all_mc_packets_set(struct aq_hw_s *aq_hw,
 741                                             u32 l2_accept_all_mc_packets)
 742 {
 743         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPFL2MC_ACCEPT_ALL_ADR,
 744                             HW_ATL_RPFL2MC_ACCEPT_ALL_MSK,
 745                             HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT,
 746                             l2_accept_all_mc_packets);
 747 }
 748
 749 void hw_atl_rpf_rpb_user_priority_tc_map_set(struct aq_hw_s *aq_hw,
 750                                              u32 user_priority_tc_map, u32 tc)
 751 {
 752 /* register address for bitfield rx_tc_up{t}[2:0] */
 753         static u32 rpf_rpb_rx_tc_upt_adr[8] = {
 754                         0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U,
 755                         0x000054c4U, 0x000054C4U, 0x000054C4U, 0x000054C4U
 756                 };
 757
 758 /* bitmask for bitfield rx_tc_up{t}[2:0] */
 759         static u32 rpf_rpb_rx_tc_upt_msk[8] = {
 760                         0x00000007U, 0x00000070U, 0x00000700U, 0x00007000U,
 761                         0x00070000U, 0x00700000U, 0x07000000U, 0x70000000U
 762                 };
 763
 764 /* lower bit position of bitfield rx_tc_up{t}[2:0] */
 765         static u32 rpf_rpb_rx_tc_upt_shft[8] = {
 766                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
 767                 };
 768
 769         aq_hw_write_reg_bit(aq_hw, rpf_rpb_rx_tc_upt_adr[tc],
 770                             rpf_rpb_rx_tc_upt_msk[tc],
 771                             rpf_rpb_rx_tc_upt_shft[tc],
 772                             user_priority_tc_map);
 773 }
 774
 775 void hw_atl_rpf_rss_key_addr_set(struct aq_hw_s *aq_hw, u32 rss_key_addr)
 776 {
 777         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_ADDR_ADR,
 778                             HW_ATL_RPF_RSS_KEY_ADDR_MSK,
 779                             HW_ATL_RPF_RSS_KEY_ADDR_SHIFT,
 780                             rss_key_addr);
 781 }
 782
 783 void hw_atl_rpf_rss_key_wr_data_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_data)
 784 {
 785         aq_hw_write_reg(aq_hw, HW_ATL_RPF_RSS_KEY_WR_DATA_ADR,
 786                         rss_key_wr_data);
 787 }
 788
 789 u32 hw_atl_rpf_rss_key_wr_en_get(struct aq_hw_s *aq_hw)
 790 {
 791         return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
 792                                   HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
 793                                   HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT);
 794 }
 795
 796 void hw_atl_rpf_rss_key_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_key_wr_en)
 797 {
 798         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_KEY_WR_ENI_ADR,
 799                             HW_ATL_RPF_RSS_KEY_WR_ENI_MSK,
 800                             HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT,
 801                             rss_key_wr_en);
 802 }
 803
 804 void hw_atl_rpf_rss_redir_tbl_addr_set(struct aq_hw_s *aq_hw,
 805                                        u32 rss_redir_tbl_addr)
 806 {
 807         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_ADDR_ADR,
 808                             HW_ATL_RPF_RSS_REDIR_ADDR_MSK,
 809                             HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT,
 810                             rss_redir_tbl_addr);
 811 }
 812
 813 void hw_atl_rpf_rss_redir_tbl_wr_data_set(struct aq_hw_s *aq_hw,
 814                                           u32 rss_redir_tbl_wr_data)
 815 {
 816         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR,
 817                             HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK,
 818                             HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT,
 819                             rss_redir_tbl_wr_data);
 820 }
 821
 822 u32 hw_atl_rpf_rss_redir_wr_en_get(struct aq_hw_s *aq_hw)
 823 {
 824         return aq_hw_read_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
 825                                   HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
 826                                   HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT);
 827 }
 828
 829 void hw_atl_rpf_rss_redir_wr_en_set(struct aq_hw_s *aq_hw, u32 rss_redir_wr_en)
 830 {
 831         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR,
 832                             HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK,
 833                             HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT, rss_redir_wr_en);
 834 }
 835
 836 void hw_atl_rpf_tpo_to_rpf_sys_lbk_set(struct aq_hw_s *aq_hw,
 837                                        u32 tpo_to_rpf_sys_lbk)
 838 {
 839         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR,
 840                             HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK,
 841                             HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT,
 842                             tpo_to_rpf_sys_lbk);
 843 }
 844
 845 void hw_atl_rpf_vlan_inner_etht_set(struct aq_hw_s *aq_hw, u32 vlan_inner_etht)
 846 {
 847         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_INNER_TPID_ADR,
 848                             HW_ATL_RPF_VL_INNER_TPID_MSK,
 849                             HW_ATL_RPF_VL_INNER_TPID_SHIFT,
 850                             vlan_inner_etht);
 851 }
 852
 853 void hw_atl_rpf_vlan_outer_etht_set(struct aq_hw_s *aq_hw, u32 vlan_outer_etht)
 854 {
 855         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_OUTER_TPID_ADR,
 856                             HW_ATL_RPF_VL_OUTER_TPID_MSK,
 857                             HW_ATL_RPF_VL_OUTER_TPID_SHIFT,
 858                             vlan_outer_etht);
 859 }
 860
 861 void hw_atl_rpf_vlan_prom_mode_en_set(struct aq_hw_s *aq_hw,
 862                                       u32 vlan_prom_mode_en)
 863 {
 864         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_PROMIS_MODE_ADR,
 865                             HW_ATL_RPF_VL_PROMIS_MODE_MSK,
 866                             HW_ATL_RPF_VL_PROMIS_MODE_SHIFT,
 867                             vlan_prom_mode_en);
 868 }
 869
 870 void hw_atl_rpf_vlan_accept_untagged_packets_set(struct aq_hw_s *aq_hw,
 871                                                  u32 vlan_acc_untagged_packets)
 872 {
 873         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR,
 874                             HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK,
 875                             HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT,
 876                             vlan_acc_untagged_packets);
 877 }
 878
 879 void hw_atl_rpf_vlan_untagged_act_set(struct aq_hw_s *aq_hw,
 880                                       u32 vlan_untagged_act)
 881 {
 882         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_UNTAGGED_ACT_ADR,
 883                             HW_ATL_RPF_VL_UNTAGGED_ACT_MSK,
 884                             HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT,
 885                             vlan_untagged_act);
 886 }
 887
 888 void hw_atl_rpf_vlan_flr_en_set(struct aq_hw_s *aq_hw, u32 vlan_flr_en,
 889                                 u32 filter)
 890 {
 891         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_EN_F_ADR(filter),
 892                             HW_ATL_RPF_VL_EN_F_MSK,
 893                             HW_ATL_RPF_VL_EN_F_SHIFT,
 894                             vlan_flr_en);
 895 }
 896
 897 void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_flr_act,
 898                                  u32 filter)
 899 {
 900         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ACT_F_ADR(filter),
 901                             HW_ATL_RPF_VL_ACT_F_MSK,
 902                             HW_ATL_RPF_VL_ACT_F_SHIFT,
 903                             vlan_flr_act);
 904 }
 905
 906 void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
 907                                 u32 filter)
 908 {
 909         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_ID_F_ADR(filter),
 910                             HW_ATL_RPF_VL_ID_F_MSK,
 911                             HW_ATL_RPF_VL_ID_F_SHIFT,
 912                             vlan_id_flr);
 913 }
 914
 915 void hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq_en,
 916                                     u32 filter)
 917 {
 918         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter),
 919                             HW_ATL_RPF_VL_RXQ_EN_F_MSK,
 920                             HW_ATL_RPF_VL_RXQ_EN_F_SHIFT,
 921                             vlan_rxq_en);
 922 }
 923
 924 void hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq,
 925                                  u32 filter)
 926 {
 927         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_F_ADR(filter),
 928                             HW_ATL_RPF_VL_RXQ_F_MSK,
 929                             HW_ATL_RPF_VL_RXQ_F_SHIFT,
 930                             vlan_rxq);
 931 };
 932
 933 void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
 934                                 u32 filter)
 935 {
 936         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ENF_ADR(filter),
 937                             HW_ATL_RPF_ET_ENF_MSK,
 938                             HW_ATL_RPF_ET_ENF_SHIFT, etht_flr_en);
 939 }
 940
 941 void hw_atl_rpf_etht_user_priority_en_set(struct aq_hw_s *aq_hw,
 942                                           u32 etht_user_priority_en, u32 filter)
 943 {
 944         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPFEN_ADR(filter),
 945                             HW_ATL_RPF_ET_UPFEN_MSK, HW_ATL_RPF_ET_UPFEN_SHIFT,
 946                             etht_user_priority_en);
 947 }
 948
 949 void hw_atl_rpf_etht_rx_queue_en_set(struct aq_hw_s *aq_hw,
 950                                      u32 etht_rx_queue_en,
 951                                      u32 filter)
 952 {
 953         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQFEN_ADR(filter),
 954                             HW_ATL_RPF_ET_RXQFEN_MSK,
 955                             HW_ATL_RPF_ET_RXQFEN_SHIFT,
 956                             etht_rx_queue_en);
 957 }
 958
 959 void hw_atl_rpf_etht_user_priority_set(struct aq_hw_s *aq_hw,
 960                                        u32 etht_user_priority,
 961                                        u32 filter)
 962 {
 963         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_UPF_ADR(filter),
 964                             HW_ATL_RPF_ET_UPF_MSK,
 965                             HW_ATL_RPF_ET_UPF_SHIFT, etht_user_priority);
 966 }
 967
 968 void hw_atl_rpf_etht_rx_queue_set(struct aq_hw_s *aq_hw, u32 etht_rx_queue,
 969                                   u32 filter)
 970 {
 971         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_RXQF_ADR(filter),
 972                             HW_ATL_RPF_ET_RXQF_MSK,
 973                             HW_ATL_RPF_ET_RXQF_SHIFT, etht_rx_queue);
 974 }
 975
 976 void hw_atl_rpf_etht_mgt_queue_set(struct aq_hw_s *aq_hw, u32 etht_mgt_queue,
 977                                    u32 filter)
 978 {
 979         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_MNG_RXQF_ADR(filter),
 980                             HW_ATL_RPF_ET_MNG_RXQF_MSK,
 981                             HW_ATL_RPF_ET_MNG_RXQF_SHIFT,
 982                             etht_mgt_queue);
 983 }
 984
 985 void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
 986                                  u32 filter)
 987 {
 988         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_ACTF_ADR(filter),
 989                             HW_ATL_RPF_ET_ACTF_MSK,
 990                             HW_ATL_RPF_ET_ACTF_SHIFT, etht_flr_act);
 991 }
 992
 993 void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter)
 994 {
 995         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_ET_VALF_ADR(filter),
 996                             HW_ATL_RPF_ET_VALF_MSK,
 997                             HW_ATL_RPF_ET_VALF_SHIFT, etht_flr);
 998 }
 999
1000 void hw_atl_rpf_l4_spd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)
1001 {
1002         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_SPD_ADR(filter),
1003                             HW_ATL_RPF_L4_SPD_MSK,
1004                             HW_ATL_RPF_L4_SPD_SHIFT, val);
1005 }
1006
1007 void hw_atl_rpf_l4_dpd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)
1008 {
1009         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_DPD_ADR(filter),
1010                             HW_ATL_RPF_L4_DPD_MSK,
1011                             HW_ATL_RPF_L4_DPD_SHIFT, val);
1012 }
1013
1014 /* RPO: rx packet offload */
1015 void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
1016                                               u32 ipv4header_crc_offload_en)
1017 {
1018         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_IPV4CHK_EN_ADR,
1019                             HW_ATL_RPO_IPV4CHK_EN_MSK,
1020                             HW_ATL_RPO_IPV4CHK_EN_SHIFT,
1021                             ipv4header_crc_offload_en);
1022 }
1023
1024 void hw_atl_rpo_rx_desc_vlan_stripping_set(struct aq_hw_s *aq_hw,
1025                                            u32 rx_desc_vlan_stripping,
1026                                            u32 descriptor)
1027 {
1028         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor),
1029                             HW_ATL_RPO_DESCDVL_STRIP_MSK,
1030                             HW_ATL_RPO_DESCDVL_STRIP_SHIFT,
1031                             rx_desc_vlan_stripping);
1032 }
1033
1034 void hw_atl_rpo_outer_vlan_tag_mode_set(void *context,
1035                                         u32 outervlantagmode)
1036 {
1037         aq_hw_write_reg_bit(context, HW_ATL_RPO_OUTER_VL_INS_MODE_ADR,
1038                             HW_ATL_RPO_OUTER_VL_INS_MODE_MSK,
1039                             HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT,
1040                             outervlantagmode);
1041 }
1042
1043 u32 hw_atl_rpo_outer_vlan_tag_mode_get(void *context)
1044 {
1045         return aq_hw_read_reg_bit(context, HW_ATL_RPO_OUTER_VL_INS_MODE_ADR,
1046                                   HW_ATL_RPO_OUTER_VL_INS_MODE_MSK,
1047                                   HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT);
1048 }
1049
1050 void hw_atl_rpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
1051                                            u32 tcp_udp_crc_offload_en)
1052 {
1053         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPOL4CHK_EN_ADR,
1054                             HW_ATL_RPOL4CHK_EN_MSK,
1055                             HW_ATL_RPOL4CHK_EN_SHIFT, tcp_udp_crc_offload_en);
1056 }
1057
1058 void hw_atl_rpo_lro_en_set(struct aq_hw_s *aq_hw, u32 lro_en)
1059 {
1060         aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_EN_ADR, lro_en);
1061 }
1062
1063 void hw_atl_rpo_lro_patch_optimization_en_set(struct aq_hw_s *aq_hw,
1064                                               u32 lro_patch_optimization_en)
1065 {
1066         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PTOPT_EN_ADR,
1067                             HW_ATL_RPO_LRO_PTOPT_EN_MSK,
1068                             HW_ATL_RPO_LRO_PTOPT_EN_SHIFT,
1069                             lro_patch_optimization_en);
1070 }
1071
1072 void hw_atl_rpo_lro_qsessions_lim_set(struct aq_hw_s *aq_hw,
1073                                       u32 lro_qsessions_lim)
1074 {
1075         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_QSES_LMT_ADR,
1076                             HW_ATL_RPO_LRO_QSES_LMT_MSK,
1077                             HW_ATL_RPO_LRO_QSES_LMT_SHIFT,
1078                             lro_qsessions_lim);
1079 }
1080
1081 void hw_atl_rpo_lro_total_desc_lim_set(struct aq_hw_s *aq_hw,
1082                                        u32 lro_total_desc_lim)
1083 {
1084         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR,
1085                             HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK,
1086                             HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT,
1087                             lro_total_desc_lim);
1088 }
1089
1090 void hw_atl_rpo_lro_min_pay_of_first_pkt_set(struct aq_hw_s *aq_hw,
1091                                              u32 lro_min_pld_of_first_pkt)
1092 {
1093         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_PKT_MIN_ADR,
1094                             HW_ATL_RPO_LRO_PKT_MIN_MSK,
1095                             HW_ATL_RPO_LRO_PKT_MIN_SHIFT,
1096                             lro_min_pld_of_first_pkt);
1097 }
1098
1099 void hw_atl_rpo_lro_pkt_lim_set(struct aq_hw_s *aq_hw, u32 lro_pkt_lim)
1100 {
1101         aq_hw_write_reg(aq_hw, HW_ATL_RPO_LRO_RSC_MAX_ADR, lro_pkt_lim);
1102 }
1103
1104 void hw_atl_rpo_lro_max_num_of_descriptors_set(struct aq_hw_s *aq_hw,
1105                                                u32 lro_max_number_of_descriptors,
1106                                                u32 lro)
1107 {
1108 /* Register address for bitfield lro{L}_des_max[1:0] */
1109         static u32 rpo_lro_ldes_max_adr[32] = {
1110                         0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
1111                         0x000055A0U, 0x000055A0U, 0x000055A0U, 0x000055A0U,
1112                         0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
1113                         0x000055A4U, 0x000055A4U, 0x000055A4U, 0x000055A4U,
1114                         0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
1115                         0x000055A8U, 0x000055A8U, 0x000055A8U, 0x000055A8U,
1116                         0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU,
1117                         0x000055ACU, 0x000055ACU, 0x000055ACU, 0x000055ACU
1118                 };
1119
1120 /* Bitmask for bitfield lro{L}_des_max[1:0] */
1121         static u32 rpo_lro_ldes_max_msk[32] = {
1122                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1123                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1124                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1125                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1126                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1127                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U,
1128                         0x00000003U, 0x00000030U, 0x00000300U, 0x00003000U,
1129                         0x00030000U, 0x00300000U, 0x03000000U, 0x30000000U
1130                 };
1131
1132 /* Lower bit position of bitfield lro{L}_des_max[1:0] */
1133         static u32 rpo_lro_ldes_max_shift[32] = {
1134                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1135                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1136                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U,
1137                         0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U
1138                 };
1139
1140         aq_hw_write_reg_bit(aq_hw, rpo_lro_ldes_max_adr[lro],
1141                             rpo_lro_ldes_max_msk[lro],
1142                             rpo_lro_ldes_max_shift[lro],
1143                             lro_max_number_of_descriptors);
1144 }
1145
1146 void hw_atl_rpo_lro_time_base_divider_set(struct aq_hw_s *aq_hw,
1147                                           u32 lro_time_base_divider)
1148 {
1149         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_TB_DIV_ADR,
1150                             HW_ATL_RPO_LRO_TB_DIV_MSK,
1151                             HW_ATL_RPO_LRO_TB_DIV_SHIFT,
1152                             lro_time_base_divider);
1153 }
1154
1155 void hw_atl_rpo_lro_inactive_interval_set(struct aq_hw_s *aq_hw,
1156                                           u32 lro_inactive_interval)
1157 {
1158         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_INA_IVAL_ADR,
1159                             HW_ATL_RPO_LRO_INA_IVAL_MSK,
1160                             HW_ATL_RPO_LRO_INA_IVAL_SHIFT,
1161                             lro_inactive_interval);
1162 }
1163
1164 void hw_atl_rpo_lro_max_coalescing_interval_set(struct aq_hw_s *aq_hw,
1165                                                 u32 lro_max_coal_interval)
1166 {
1167         aq_hw_write_reg_bit(aq_hw, HW_ATL_RPO_LRO_MAX_IVAL_ADR,
1168                             HW_ATL_RPO_LRO_MAX_IVAL_MSK,
1169                             HW_ATL_RPO_LRO_MAX_IVAL_SHIFT,
1170                             lro_max_coal_interval);
1171 }
1172
1173 /* rx */
1174 void hw_atl_rx_rx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 rx_reg_res_dis)
1175 {
1176         aq_hw_write_reg_bit(aq_hw, HW_ATL_RX_REG_RES_DSBL_ADR,
1177                             HW_ATL_RX_REG_RES_DSBL_MSK,
1178                             HW_ATL_RX_REG_RES_DSBL_SHIFT,
1179                             rx_reg_res_dis);
1180 }
1181
1182 /* tdm */
1183 void hw_atl_tdm_cpu_id_set(struct aq_hw_s *aq_hw, u32 cpuid, u32 dca)
1184 {
1185         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADCPUID_ADR(dca),
1186                             HW_ATL_TDM_DCADCPUID_MSK,
1187                             HW_ATL_TDM_DCADCPUID_SHIFT, cpuid);
1188 }
1189
1190 void hw_atl_tdm_large_send_offload_en_set(struct aq_hw_s *aq_hw,
1191                                           u32 large_send_offload_en)
1192 {
1193         aq_hw_write_reg(aq_hw, HW_ATL_TDM_LSO_EN_ADR, large_send_offload_en);
1194 }
1195
1196 void hw_atl_tdm_tx_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_dca_en)
1197 {
1198         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_EN_ADR, HW_ATL_TDM_DCA_EN_MSK,
1199                             HW_ATL_TDM_DCA_EN_SHIFT, tx_dca_en);
1200 }
1201
1202 void hw_atl_tdm_tx_dca_mode_set(struct aq_hw_s *aq_hw, u32 tx_dca_mode)
1203 {
1204         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCA_MODE_ADR,
1205                             HW_ATL_TDM_DCA_MODE_MSK,
1206                             HW_ATL_TDM_DCA_MODE_SHIFT, tx_dca_mode);
1207 }
1208
1209 void hw_atl_tdm_tx_desc_dca_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_dca_en,
1210                                    u32 dca)
1211 {
1212         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DCADDESC_EN_ADR(dca),
1213                             HW_ATL_TDM_DCADDESC_EN_MSK,
1214                             HW_ATL_TDM_DCADDESC_EN_SHIFT,
1215                             tx_desc_dca_en);
1216 }
1217
1218 void hw_atl_tdm_tx_desc_en_set(struct aq_hw_s *aq_hw, u32 tx_desc_en,
1219                                u32 descriptor)
1220 {
1221         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDEN_ADR(descriptor),
1222                             HW_ATL_TDM_DESCDEN_MSK,
1223                             HW_ATL_TDM_DESCDEN_SHIFT,
1224                             tx_desc_en);
1225 }
1226
1227 u32 hw_atl_tdm_tx_desc_head_ptr_get(struct aq_hw_s *aq_hw, u32 descriptor)
1228 {
1229         return aq_hw_read_reg_bit(aq_hw, HW_ATL_TDM_DESCDHD_ADR(descriptor),
1230                                   HW_ATL_TDM_DESCDHD_MSK,
1231                                   HW_ATL_TDM_DESCDHD_SHIFT);
1232 }
1233
1234 void hw_atl_tdm_tx_desc_len_set(struct aq_hw_s *aq_hw, u32 tx_desc_len,
1235                                 u32 descriptor)
1236 {
1237         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDLEN_ADR(descriptor),
1238                             HW_ATL_TDM_DESCDLEN_MSK,
1239                             HW_ATL_TDM_DESCDLEN_SHIFT,
1240                             tx_desc_len);
1241 }
1242
1243 void hw_atl_tdm_tx_desc_wr_wb_irq_en_set(struct aq_hw_s *aq_hw,
1244                                          u32 tx_desc_wr_wb_irq_en)
1245 {
1246         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_DESC_WRB_EN_ADR,
1247                             HW_ATL_TDM_INT_DESC_WRB_EN_MSK,
1248                             HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT,
1249                             tx_desc_wr_wb_irq_en);
1250 }
1251
1252 void hw_atl_tdm_tx_desc_wr_wb_threshold_set(struct aq_hw_s *aq_hw,
1253                                             u32 tx_desc_wr_wb_threshold,
1254                                             u32 descriptor)
1255 {
1256         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor),
1257                             HW_ATL_TDM_DESCDWRB_THRESH_MSK,
1258                             HW_ATL_TDM_DESCDWRB_THRESH_SHIFT,
1259                             tx_desc_wr_wb_threshold);
1260 }
1261
1262 void hw_atl_tdm_tdm_intr_moder_en_set(struct aq_hw_s *aq_hw,
1263                                       u32 tdm_irq_moderation_en)
1264 {
1265         aq_hw_write_reg_bit(aq_hw, HW_ATL_TDM_INT_MOD_EN_ADR,
1266                             HW_ATL_TDM_INT_MOD_EN_MSK,
1267                             HW_ATL_TDM_INT_MOD_EN_SHIFT,
1268                             tdm_irq_moderation_en);
1269 }
1270
1271 /* thm */
1272 void hw_atl_thm_lso_tcp_flag_of_first_pkt_set(struct aq_hw_s *aq_hw,
1273                                               u32 lso_tcp_flag_of_first_pkt)
1274 {
1275         aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR,
1276                             HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK,
1277                             HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT,
1278                             lso_tcp_flag_of_first_pkt);
1279 }
1280
1281 void hw_atl_thm_lso_tcp_flag_of_last_pkt_set(struct aq_hw_s *aq_hw,
1282                                              u32 lso_tcp_flag_of_last_pkt)
1283 {
1284         aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR,
1285                             HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK,
1286                             HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT,
1287                             lso_tcp_flag_of_last_pkt);
1288 }
1289
1290 void hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(struct aq_hw_s *aq_hw,
1291                                                u32 lso_tcp_flag_of_middle_pkt)
1292 {
1293         aq_hw_write_reg_bit(aq_hw, HW_ATL_THM_LSO_TCP_FLAG_MID_ADR,
1294                             HW_ATL_THM_LSO_TCP_FLAG_MID_MSK,
1295                             HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT,
1296                             lso_tcp_flag_of_middle_pkt);
1297 }
1298
1299 /* TPB: tx packet buffer */
1300 void hw_atl_tpb_tx_buff_en_set(struct aq_hw_s *aq_hw, u32 tx_buff_en)
1301 {
1302         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_BUF_EN_ADR,
1303                             HW_ATL_TPB_TX_BUF_EN_MSK,
1304                             HW_ATL_TPB_TX_BUF_EN_SHIFT, tx_buff_en);
1305 }
1306
1307 u32 hw_atl_rpb_tps_tx_tc_mode_get(struct aq_hw_s *aq_hw)
1308 {
1309         return aq_hw_read_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR,
1310                         HW_ATL_TPB_TX_TC_MODE_MSK,
1311                         HW_ATL_TPB_TX_TC_MODE_SHIFT);
1312 }
1313
1314 void hw_atl_rpb_tps_tx_tc_mode_set(struct aq_hw_s *aq_hw,
1315                                    u32 tx_traf_class_mode)
1316 {
1317         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_TC_MODE_ADDR,
1318                         HW_ATL_TPB_TX_TC_MODE_MSK,
1319                         HW_ATL_TPB_TX_TC_MODE_SHIFT,
1320                         tx_traf_class_mode);
1321 }
1322
1323 void hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1324                                                 u32 tx_buff_hi_threshold_per_tc,
1325                                          u32 buffer)
1326 {
1327         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBHI_THRESH_ADR(buffer),
1328                             HW_ATL_TPB_TXBHI_THRESH_MSK,
1329                             HW_ATL_TPB_TXBHI_THRESH_SHIFT,
1330                             tx_buff_hi_threshold_per_tc);
1331 }
1332
1333 void hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(struct aq_hw_s *aq_hw,
1334                                                 u32 tx_buff_lo_threshold_per_tc,
1335                                          u32 buffer)
1336 {
1337         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBLO_THRESH_ADR(buffer),
1338                             HW_ATL_TPB_TXBLO_THRESH_MSK,
1339                             HW_ATL_TPB_TXBLO_THRESH_SHIFT,
1340                             tx_buff_lo_threshold_per_tc);
1341 }
1342
1343 void hw_atl_tpb_tx_dma_sys_lbk_en_set(struct aq_hw_s *aq_hw, u32 tx_dma_sys_lbk_en)
1344 {
1345         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_SYS_LBK_ADR,
1346                             HW_ATL_TPB_DMA_SYS_LBK_MSK,
1347                             HW_ATL_TPB_DMA_SYS_LBK_SHIFT,
1348                             tx_dma_sys_lbk_en);
1349 }
1350
1351 void hw_atl_tpb_tx_dma_net_lbk_en_set(struct aq_hw_s *aq_hw,
1352                                       u32 tx_dma_net_lbk_en)
1353 {
1354         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_DMA_NET_LBK_ADR,
1355                             HW_ATL_TPB_DMA_NET_LBK_MSK,
1356                             HW_ATL_TPB_DMA_NET_LBK_SHIFT,
1357                             tx_dma_net_lbk_en);
1358 }
1359
1360 void hw_atl_tpb_tx_tx_clk_gate_en_set(struct aq_hw_s *aq_hw,
1361                                       u32 tx_clk_gate_en)
1362 {
1363         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_CLK_GATE_EN_ADR,
1364                             HW_ATL_TPB_TX_CLK_GATE_EN_MSK,
1365                             HW_ATL_TPB_TX_CLK_GATE_EN_SHIFT,
1366                             tx_clk_gate_en);
1367 }
1368
1369 void hw_atl_tpb_tx_pkt_buff_size_per_tc_set(struct aq_hw_s *aq_hw,
1370
1371                                             u32 tx_pkt_buff_size_per_tc, u32 buffer)
1372 {
1373         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer),
1374                             HW_ATL_TPB_TXBBUF_SIZE_MSK,
1375                             HW_ATL_TPB_TXBBUF_SIZE_SHIFT,
1376                             tx_pkt_buff_size_per_tc);
1377 }
1378
1379 void hw_atl_tpb_tx_path_scp_ins_en_set(struct aq_hw_s *aq_hw, u32 tx_path_scp_ins_en)
1380 {
1381         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPB_TX_SCP_INS_EN_ADR,
1382                             HW_ATL_TPB_TX_SCP_INS_EN_MSK,
1383                             HW_ATL_TPB_TX_SCP_INS_EN_SHIFT,
1384                             tx_path_scp_ins_en);
1385 }
1386
1387 /* TPO: tx packet offload */
1388 void hw_atl_tpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
1389                                               u32 ipv4header_crc_offload_en)
1390 {
1391         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_IPV4CHK_EN_ADR,
1392                             HW_ATL_TPO_IPV4CHK_EN_MSK,
1393                             HW_ATL_TPO_IPV4CHK_EN_SHIFT,
1394                             ipv4header_crc_offload_en);
1395 }
1396
1397 void hw_atl_tpo_tcp_udp_crc_offload_en_set(struct aq_hw_s *aq_hw,
1398                                            u32 tcp_udp_crc_offload_en)
1399 {
1400         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPOL4CHK_EN_ADR,
1401                             HW_ATL_TPOL4CHK_EN_MSK,
1402                             HW_ATL_TPOL4CHK_EN_SHIFT,
1403                             tcp_udp_crc_offload_en);
1404 }
1405
1406 void hw_atl_tpo_tx_pkt_sys_lbk_en_set(struct aq_hw_s *aq_hw,
1407                                       u32 tx_pkt_sys_lbk_en)
1408 {
1409         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPO_PKT_SYS_LBK_ADR,
1410                             HW_ATL_TPO_PKT_SYS_LBK_MSK,
1411                             HW_ATL_TPO_PKT_SYS_LBK_SHIFT,
1412                             tx_pkt_sys_lbk_en);
1413 }
1414
1415 /* TPS: tx packet scheduler */
1416 void hw_atl_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
1417                                               u32 tx_pkt_shed_data_arb_mode)
1418 {
1419         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TC_ARB_MODE_ADR,
1420                             HW_ATL_TPS_DATA_TC_ARB_MODE_MSK,
1421                             HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT,
1422                             tx_pkt_shed_data_arb_mode);
1423 }
1424
1425 void hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(struct aq_hw_s *aq_hw,
1426                                                         u32 curr_time_res)
1427 {
1428         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_TA_RST_ADR,
1429                             HW_ATL_TPS_DESC_RATE_TA_RST_MSK,
1430                             HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT,
1431                             curr_time_res);
1432 }
1433
1434 void hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(struct aq_hw_s *aq_hw,
1435                                               u32 tx_pkt_shed_desc_rate_lim)
1436 {
1437         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_RATE_LIM_ADR,
1438                             HW_ATL_TPS_DESC_RATE_LIM_MSK,
1439                             HW_ATL_TPS_DESC_RATE_LIM_SHIFT,
1440                             tx_pkt_shed_desc_rate_lim);
1441 }
1442
1443 void hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(struct aq_hw_s *aq_hw,
1444                                                  u32 arb_mode)
1445 {
1446         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TC_ARB_MODE_ADR,
1447                             HW_ATL_TPS_DESC_TC_ARB_MODE_MSK,
1448                             HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT,
1449                             arb_mode);
1450 }
1451
1452 void hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(struct aq_hw_s *aq_hw,
1453                                                    u32 max_credit,
1454                                                    u32 tc)
1455 {
1456         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc),
1457                             HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK,
1458                             HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT,
1459                             max_credit);
1460 }
1461
1462 void hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(struct aq_hw_s *aq_hw,
1463                                                u32 tx_pkt_shed_desc_tc_weight,
1464                                                u32 tc)
1465 {
1466         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc),
1467                             HW_ATL_TPS_DESC_TCTWEIGHT_MSK,
1468                             HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT,
1469                             tx_pkt_shed_desc_tc_weight);
1470 }
1471
1472 void hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(struct aq_hw_s *aq_hw,
1473                                                  u32 arb_mode)
1474 {
1475         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DESC_VM_ARB_MODE_ADR,
1476                             HW_ATL_TPS_DESC_VM_ARB_MODE_MSK,
1477                             HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT,
1478                             arb_mode);
1479 }
1480
1481 void hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
1482                                                    u32 max_credit,
1483                                                    u32 tc)
1484 {
1485         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc),
1486                             HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK,
1487                             HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT,
1488                             max_credit);
1489 }
1490
1491 void hw_atl_tps_tx_pkt_shed_tc_data_weight_set(struct aq_hw_s *aq_hw,
1492                                                u32 tx_pkt_shed_tc_data_weight,
1493                                                u32 tc)
1494 {
1495         aq_hw_write_reg_bit(aq_hw, HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc),
1496                             HW_ATL_TPS_DATA_TCTWEIGHT_MSK,
1497                             HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT,
1498                             tx_pkt_shed_tc_data_weight);
1499 }
1500
1501 /* tx */
1502 void hw_atl_tx_tx_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 tx_reg_res_dis)
1503 {
1504         aq_hw_write_reg_bit(aq_hw, HW_ATL_TX_REG_RES_DSBL_ADR,
1505                             HW_ATL_TX_REG_RES_DSBL_MSK,
1506                             HW_ATL_TX_REG_RES_DSBL_SHIFT, tx_reg_res_dis);
1507 }
1508
1509 /* msm */
1510 u32 hw_atl_msm_reg_access_status_get(struct aq_hw_s *aq_hw)
1511 {
1512         return aq_hw_read_reg_bit(aq_hw, HW_ATL_MSM_REG_ACCESS_BUSY_ADR,
1513                                   HW_ATL_MSM_REG_ACCESS_BUSY_MSK,
1514                                   HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT);
1515 }
1516
1517 void hw_atl_msm_reg_addr_for_indirect_addr_set(struct aq_hw_s *aq_hw,
1518                                                u32 reg_addr_for_indirect_addr)
1519 {
1520         aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_ADDR_ADR,
1521                             HW_ATL_MSM_REG_ADDR_MSK,
1522                             HW_ATL_MSM_REG_ADDR_SHIFT,
1523                             reg_addr_for_indirect_addr);
1524 }
1525
1526 void hw_atl_msm_reg_rd_strobe_set(struct aq_hw_s *aq_hw, u32 reg_rd_strobe)
1527 {
1528         aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_RD_STROBE_ADR,
1529                             HW_ATL_MSM_REG_RD_STROBE_MSK,
1530                             HW_ATL_MSM_REG_RD_STROBE_SHIFT,
1531                             reg_rd_strobe);
1532 }
1533
1534 u32 hw_atl_msm_reg_rd_data_get(struct aq_hw_s *aq_hw)
1535 {
1536         return aq_hw_read_reg(aq_hw, HW_ATL_MSM_REG_RD_DATA_ADR);
1537 }
1538
1539 void hw_atl_msm_reg_wr_data_set(struct aq_hw_s *aq_hw, u32 reg_wr_data)
1540 {
1541         aq_hw_write_reg(aq_hw, HW_ATL_MSM_REG_WR_DATA_ADR, reg_wr_data);
1542 }
1543
1544 void hw_atl_msm_reg_wr_strobe_set(struct aq_hw_s *aq_hw, u32 reg_wr_strobe)
1545 {
1546         aq_hw_write_reg_bit(aq_hw, HW_ATL_MSM_REG_WR_STROBE_ADR,
1547                             HW_ATL_MSM_REG_WR_STROBE_MSK,
1548                             HW_ATL_MSM_REG_WR_STROBE_SHIFT,
1549                             reg_wr_strobe);
1550 }
1551
1552 /* pci */
1553 void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis)
1554 {
1555         aq_hw_write_reg_bit(aq_hw, HW_ATL_PCI_REG_RES_DSBL_ADR,
1556                             HW_ATL_PCI_REG_RES_DSBL_MSK,
1557                             HW_ATL_PCI_REG_RES_DSBL_SHIFT,
1558                             pci_reg_res_dis);
1559 }
1560
1561 void hw_atl_reg_glb_cpu_scratch_scp_set(struct aq_hw_s *aq_hw,
1562                                         u32 glb_cpu_scratch_scp,
1563                                         u32 scratch_scp)
1564 {
1565         aq_hw_write_reg(aq_hw, HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp),
1566                         glb_cpu_scratch_scp);
1567 }
1568
1569 void hw_atl_pcs_ptp_clock_read_enable(struct aq_hw_s *aq_hw,
1570                                       u32 ptp_clock_read_enable)
1571 {
1572         aq_hw_write_reg_bit(aq_hw, HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_ADR,
1573                             HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_MSK,
1574                             HW_ATL_PCS_PTP_CLOCK_READ_ENABLE_SHIFT,
1575                             ptp_clock_read_enable);
1576 }
1577
1578 u32 hw_atl_pcs_ptp_clock_get(struct aq_hw_s *aq_hw, u32 index)
1579 {
1580         return aq_hw_read_reg(aq_hw, HW_ATL_PCS_PTP_TS_VAL_ADDR(index));
1581 }
1582
1583 void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr)
1584 {
1585         aq_hw_write_reg_bit(aq_hw, HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR,
1586                             HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK,
1587                             HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT,
1588                             up_force_intr);
1589 }
1590
1591 void hw_atl_rpfl3l4_ipv4_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1592 {
1593         aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location), 0U);
1594 }
1595
1596 void hw_atl_rpfl3l4_ipv4_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1597 {
1598         aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_SRCA_ADR(location), 0U);
1599 }
1600
1601 void hw_atl_rpfl3l4_cmd_clear(struct aq_hw_s *aq_hw, u8 location)
1602 {
1603         aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), 0U);
1604 }
1605
1606 void hw_atl_rpfl3l4_ipv6_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1607 {
1608         int i;
1609
1610         for (i = 0; i < 4; ++i)
1611                 aq_hw_write_reg(aq_hw,
1612                                 HW_ATL_RPF_L3_DSTA_ADR(location + i),
1613                                 0U);
1614 }
1615
1616 void hw_atl_rpfl3l4_ipv6_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)
1617 {
1618         int i;
1619
1620         for (i = 0; i < 4; ++i)
1621                 aq_hw_write_reg(aq_hw,
1622                                 HW_ATL_RPF_L3_SRCA_ADR(location + i),
1623                                 0U);
1624 }
1625
1626 void hw_atl_rpfl3l4_ipv4_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
1627                                        u32 ipv4_dest)
1628 {
1629         aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location),
1630                         ipv4_dest);
1631 }
1632
1633 void hw_atl_rpfl3l4_ipv4_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
1634                                       u32 ipv4_src)
1635 {
1636         aq_hw_write_reg(aq_hw,
1637                         HW_ATL_RPF_L3_SRCA_ADR(location),
1638                         ipv4_src);
1639 }
1640
1641 void hw_atl_rpfl3l4_cmd_set(struct aq_hw_s *aq_hw, u8 location, u32 cmd)
1642 {
1643         aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), cmd);
1644 }
1645
1646 void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
1647                                       u32 *ipv6_src)
1648 {
1649         int i;
1650
1651         for (i = 0; i < 4; ++i)
1652                 aq_hw_write_reg(aq_hw,
1653                                 HW_ATL_RPF_L3_SRCA_ADR(location + i),
1654                                 ipv6_src[i]);
1655 }
1656
1657 void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
1658                                        u32 *ipv6_dest)
1659 {
1660         int i;
1661
1662         for (i = 0; i < 4; ++i)
1663                 aq_hw_write_reg(aq_hw,
1664                                 HW_ATL_RPF_L3_DSTA_ADR(location + i),
1665                                 ipv6_dest[i]);
1666 }
1667
1668 u32 hw_atl_sem_ram_get(struct aq_hw_s *self)
1669 {
1670         return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
1671 }
1672
1673 u32 hw_atl_sem_mdio_get(struct aq_hw_s *self)
1674 {
1675         return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_MDIO);
1676 }
1677
1678 u32 hw_atl_scrpad_get(struct aq_hw_s *aq_hw, u32 scratch_scp)
1679 {
1680         return aq_hw_read_reg(aq_hw,
1681                               HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp));
1682 }
1683
1684 u32 hw_atl_scrpad12_get(struct aq_hw_s *self)
1685 {
1686         return  hw_atl_scrpad_get(self, 0xB);
1687 }
1688
1689 u32 hw_atl_scrpad25_get(struct aq_hw_s *self)
1690 {
1691         return hw_atl_scrpad_get(self, 0x18);
1692 }
1693
1694 void hw_atl_glb_mdio_iface1_set(struct aq_hw_s *aq_hw, u32 value)
1695 {
1696         aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(1), value);
1697 }
1698
1699 u32 hw_atl_glb_mdio_iface1_get(struct aq_hw_s *aq_hw)
1700 {
1701         return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(1));
1702 }
1703
1704 void hw_atl_glb_mdio_iface2_set(struct aq_hw_s *aq_hw, u32 value)
1705 {
1706         aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(2), value);
1707 }
1708
1709 u32 hw_atl_glb_mdio_iface2_get(struct aq_hw_s *aq_hw)
1710 {
1711         return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(2));
1712 }
1713
1714 void hw_atl_glb_mdio_iface3_set(struct aq_hw_s *aq_hw, u32 value)
1715 {
1716         aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(3), value);
1717 }
1718
1719 u32 hw_atl_glb_mdio_iface3_get(struct aq_hw_s *aq_hw)
1720 {
1721         return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(3));
1722 }
1723
1724 void hw_atl_glb_mdio_iface4_set(struct aq_hw_s *aq_hw, u32 value)
1725 {
1726         aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(4), value);
1727 }
1728
1729 u32 hw_atl_glb_mdio_iface4_get(struct aq_hw_s *aq_hw)
1730 {
1731         return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(4));
1732 }
1733
1734 void hw_atl_glb_mdio_iface5_set(struct aq_hw_s *aq_hw, u32 value)
1735 {
1736         aq_hw_write_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(5), value);
1737 }
1738
1739 u32 hw_atl_glb_mdio_iface5_get(struct aq_hw_s *aq_hw)
1740 {
1741         return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(5));
1742 }
1743
1744 u32 hw_atl_mdio_busy_get(struct aq_hw_s *aq_hw)
1745 {
1746         return aq_hw_read_reg_bit(aq_hw, HW_ATL_MDIO_BUSY_ADR,
1747                                   HW_ATL_MDIO_BUSY_MSK,
1748                                   HW_ATL_MDIO_BUSY_SHIFT);
1749 }