drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * aQuantia Corporation Network Driver
   4  * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
   5  */
   6
   7 /* File hw_atl_a0.c: Definition of Atlantic hardware specific functions. */
   8
   9 #include "../aq_hw.h"
  10 #include "../aq_hw_utils.h"
  11 #include "../aq_ring.h"
  12 #include "../aq_nic.h"
  13 #include "hw_atl_a0.h"
  14 #include "hw_atl_utils.h"
  15 #include "hw_atl_llh.h"
  16 #include "hw_atl_a0_internal.h"
  17
  18 #define DEFAULT_A0_BOARD_BASIC_CAPABILITIES \
  19         .is_64_dma = true,                \
  20         .msix_irqs = 4U,                  \
  21         .irq_mask = ~0U,                  \
  22         .vecs = HW_ATL_A0_RSS_MAX,        \
  23         .tcs = HW_ATL_A0_TC_MAX,          \
  24         .rxd_alignment = 1U,              \
  25         .rxd_size = HW_ATL_A0_RXD_SIZE,   \
  26         .rxds_max = HW_ATL_A0_MAX_RXD,    \
  27         .rxds_min = HW_ATL_A0_MIN_RXD,    \
  28         .txd_alignment = 1U,              \
  29         .txd_size = HW_ATL_A0_TXD_SIZE,   \
  30         .txds_max = HW_ATL_A0_MAX_TXD,    \
  31         .txds_min = HW_ATL_A0_MIN_RXD,    \
  32         .txhwb_alignment = 4096U,         \
  33         .tx_rings = HW_ATL_A0_TX_RINGS,   \
  34         .rx_rings = HW_ATL_A0_RX_RINGS,   \
  35         .hw_features = NETIF_F_HW_CSUM |  \
  36                         NETIF_F_RXHASH |  \
  37                         NETIF_F_RXCSUM |  \
  38                         NETIF_F_SG |      \
  39                         NETIF_F_TSO,      \
  40         .hw_priv_flags = IFF_UNICAST_FLT, \
  41         .flow_control = true,             \
  42         .mtu = HW_ATL_A0_MTU_JUMBO,       \
  43         .mac_regs_count = 88,             \
  44         .hw_alive_check_addr = 0x10U
  45
  46 const struct aq_hw_caps_s hw_atl_a0_caps_aqc100 = {
  47         DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
  48         .media_type = AQ_HW_MEDIA_TYPE_FIBRE,
  49         .link_speed_msk = AQ_NIC_RATE_5G |
  50                           AQ_NIC_RATE_2GS |
  51                           AQ_NIC_RATE_1G |
  52                           AQ_NIC_RATE_100M,
  53 };
  54
  55 const struct aq_hw_caps_s hw_atl_a0_caps_aqc107 = {
  56         DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
  57         .media_type = AQ_HW_MEDIA_TYPE_TP,
  58         .link_speed_msk = AQ_NIC_RATE_10G |
  59                           AQ_NIC_RATE_5G |
  60                           AQ_NIC_RATE_2GS |
  61                           AQ_NIC_RATE_1G |
  62                           AQ_NIC_RATE_100M,
  63 };
  64
  65 const struct aq_hw_caps_s hw_atl_a0_caps_aqc108 = {
  66         DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
  67         .media_type = AQ_HW_MEDIA_TYPE_TP,
  68         .link_speed_msk = AQ_NIC_RATE_5G |
  69                           AQ_NIC_RATE_2GS |
  70                           AQ_NIC_RATE_1G |
  71                           AQ_NIC_RATE_100M,
  72 };
  73
  74 const struct aq_hw_caps_s hw_atl_a0_caps_aqc109 = {
  75         DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
  76         .media_type = AQ_HW_MEDIA_TYPE_TP,
  77         .link_speed_msk = AQ_NIC_RATE_2GS |
  78                           AQ_NIC_RATE_1G |
  79                           AQ_NIC_RATE_100M,
  80 };
  81
  82 static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
  83 {
  84         int err = 0;
  85         u32 val;
  86
  87         hw_atl_glb_glb_reg_res_dis_set(self, 1U);
  88         hw_atl_pci_pci_reg_res_dis_set(self, 0U);
  89         hw_atl_rx_rx_reg_res_dis_set(self, 0U);
  90         hw_atl_tx_tx_reg_res_dis_set(self, 0U);
  91
  92         HW_ATL_FLUSH();
  93         hw_atl_glb_soft_res_set(self, 1);
  94
  95         /* check 10 times by 1ms */
  96         err = readx_poll_timeout_atomic(hw_atl_glb_soft_res_get,
  97                                         self, val, val == 0,
  98                                         1000U, 10000U);
  99         if (err < 0)
 100                 goto err_exit;
 101
 102         hw_atl_itr_irq_reg_res_dis_set(self, 0U);
 103         hw_atl_itr_res_irq_set(self, 1U);
 104
 105         /* check 10 times by 1ms */
 106         err = readx_poll_timeout_atomic(hw_atl_itr_res_irq_get,
 107                                         self, val, val == 0,
 108                                         1000U, 10000U);
 109         if (err < 0)
 110                 goto err_exit;
 111
 112         self->aq_fw_ops->set_state(self, MPI_RESET);
 113
 114         err = aq_hw_err_from_flags(self);
 115
 116 err_exit:
 117         return err;
 118 }
 119
 120 static int hw_atl_a0_hw_qos_set(struct aq_hw_s *self)
 121 {
 122         bool is_rx_flow_control = false;
 123         unsigned int i_priority = 0U;
 124         u32 buff_size = 0U;
 125         u32 tc = 0U;
 126
 127         /* TPS Descriptor rate init */
 128         hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
 129         hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
 130
 131         /* TPS VM init */
 132         hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
 133
 134         /* TPS TC credits init */
 135         hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
 136         hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
 137
 138         hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
 139         hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
 140         hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
 141         hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
 142
 143         /* Tx buf size */
 144         buff_size = HW_ATL_A0_TXBUF_MAX;
 145
 146         hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
 147         hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self,
 148                                                    (buff_size *
 149                                                    (1024 / 32U) * 66U) /
 150                                                    100U, tc);
 151         hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self,
 152                                                    (buff_size *
 153                                                    (1024 / 32U) * 50U) /
 154                                                    100U, tc);
 155
 156         /* QoS Rx buf size per TC */
 157         tc = 0;
 158         is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->fc.req);
 159         buff_size = HW_ATL_A0_RXBUF_MAX;
 160
 161         hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
 162         hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self,
 163                                                    (buff_size *
 164                                                    (1024U / 32U) * 66U) /
 165                                                    100U, tc);
 166         hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self,
 167                                                    (buff_size *
 168                                                    (1024U / 32U) * 50U) /
 169                                                    100U, tc);
 170         hw_atl_rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
 171
 172         /* QoS 802.1p priority -> TC mapping */
 173         for (i_priority = 8U; i_priority--;)
 174                 hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
 175
 176         return aq_hw_err_from_flags(self);
 177 }
 178
 179 static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *self,
 180                                      struct aq_rss_parameters *rss_params)
 181 {
 182         struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
 183         unsigned int addr = 0U;
 184         unsigned int i = 0U;
 185         int err = 0;
 186         u32 val;
 187
 188         for (i = 10, addr = 0U; i--; ++addr) {
 189                 u32 key_data = cfg->is_rss ?
 190                         __swab32(rss_params->hash_secret_key[i]) : 0U;
 191                 hw_atl_rpf_rss_key_wr_data_set(self, key_data);
 192                 hw_atl_rpf_rss_key_addr_set(self, addr);
 193                 hw_atl_rpf_rss_key_wr_en_set(self, 1U);
 194                 err = readx_poll_timeout_atomic(hw_atl_rpf_rss_key_wr_en_get,
 195                                                 self, val, val == 0,
 196                                                 1000U, 10000U);
 197                 if (err < 0)
 198                         goto err_exit;
 199         }
 200
 201         err = aq_hw_err_from_flags(self);
 202
 203 err_exit:
 204         return err;
 205 }
 206
 207 static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self,
 208                                 struct aq_rss_parameters *rss_params)
 209 {
 210         u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
 211         u8 *indirection_table = rss_params->indirection_table;
 212         u16 bitary[1 + (HW_ATL_A0_RSS_REDIRECTION_MAX *
 213                    HW_ATL_A0_RSS_REDIRECTION_BITS / 16U)];
 214         int err = 0;
 215         u32 i = 0U;
 216         u32 val;
 217
 218         memset(bitary, 0, sizeof(bitary));
 219
 220         for (i = HW_ATL_A0_RSS_REDIRECTION_MAX; i--; ) {
 221                 (*(u32 *)(bitary + ((i * 3U) / 16U))) |=
 222                         ((indirection_table[i] % num_rss_queues) <<
 223                         ((i * 3U) & 0xFU));
 224         }
 225
 226         for (i = ARRAY_SIZE(bitary); i--;) {
 227                 hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
 228                 hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
 229                 hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
 230                 err = readx_poll_timeout_atomic(hw_atl_rpf_rss_redir_wr_en_get,
 231                                                 self, val, val == 0,
 232                                                 1000U, 10000U);
 233                 if (err < 0)
 234                         goto err_exit;
 235         }
 236
 237         err = aq_hw_err_from_flags(self);
 238
 239 err_exit:
 240         return err;
 241 }
 242
 243 static int hw_atl_a0_hw_offload_set(struct aq_hw_s *self,
 244                                     struct aq_nic_cfg_s *aq_nic_cfg)
 245 {
 246         /* TX checksums offloads*/
 247         hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1);
 248         hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1);
 249
 250         /* RX checksums offloads*/
 251         hw_atl_rpo_ipv4header_crc_offload_en_set(self, 1);
 252         hw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1);
 253
 254         /* LSO offloads*/
 255         hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
 256
 257         return aq_hw_err_from_flags(self);
 258 }
 259
 260 static int hw_atl_a0_hw_init_tx_path(struct aq_hw_s *self)
 261 {
 262         hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
 263         hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
 264         hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
 265
 266         /* Tx interrupts */
 267         hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
 268
 269         /* misc */
 270         aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
 271                         0x00010000U : 0x00000000U);
 272         hw_atl_tdm_tx_dca_en_set(self, 0U);
 273         hw_atl_tdm_tx_dca_mode_set(self, 0U);
 274
 275         hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U);
 276
 277         return aq_hw_err_from_flags(self);
 278 }
 279
 280 static int hw_atl_a0_hw_init_rx_path(struct aq_hw_s *self)
 281 {
 282         struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
 283         int i;
 284
 285         /* Rx TC/RSS number config */
 286         hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U);
 287
 288         /* Rx flow control */
 289         hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);
 290
 291         /* RSS Ring selection */
 292         hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?
 293                                           0xB3333333U : 0x00000000U);
 294
 295         /* Multicast filters */
 296         for (i = HW_ATL_A0_MAC_MAX; i--;) {
 297                 hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
 298                 hw_atl_rpfl2unicast_flr_act_set(self, 1U, i);
 299         }
 300
 301         hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
 302         hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
 303
 304         /* Vlan filters */
 305         hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U);
 306         hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U);
 307         hw_atl_rpf_vlan_prom_mode_en_set(self, 1);
 308
 309         /* Rx Interrupts */
 310         hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
 311
 312         /* misc */
 313         hw_atl_rpfl2broadcast_flr_act_set(self, 1U);
 314         hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
 315
 316         hw_atl_rdm_rx_dca_en_set(self, 0U);
 317         hw_atl_rdm_rx_dca_mode_set(self, 0U);
 318
 319         return aq_hw_err_from_flags(self);
 320 }
 321
 322 static int hw_atl_a0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
 323 {
 324         unsigned int h = 0U;
 325         unsigned int l = 0U;
 326         int err = 0;
 327
 328         if (!mac_addr) {
 329                 err = -EINVAL;
 330                 goto err_exit;
 331         }
 332         h = (mac_addr[0] << 8) | (mac_addr[1]);
 333         l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
 334             (mac_addr[4] << 8) | mac_addr[5];
 335
 336         hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC);
 337         hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_A0_MAC);
 338         hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_A0_MAC);
 339         hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_A0_MAC);
 340
 341         err = aq_hw_err_from_flags(self);
 342
 343 err_exit:
 344         return err;
 345 }
 346
 347 static int hw_atl_a0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
 348 {
 349         static u32 aq_hw_atl_igcr_table_[4][2] = {
 350                 [AQ_HW_IRQ_INVALID] = { 0x20000000U, 0x20000000U },
 351                 [AQ_HW_IRQ_LEGACY]  = { 0x20000080U, 0x20000080U },
 352                 [AQ_HW_IRQ_MSI]     = { 0x20000021U, 0x20000025U },
 353                 [AQ_HW_IRQ_MSIX]    = { 0x20000022U, 0x20000026U },
 354         };
 355         struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg;
 356         int err = 0;
 357
 358
 359         hw_atl_a0_hw_init_tx_path(self);
 360         hw_atl_a0_hw_init_rx_path(self);
 361
 362         hw_atl_a0_hw_mac_addr_set(self, mac_addr);
 363
 364         self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk);
 365         self->aq_fw_ops->set_state(self, MPI_INIT);
 366
 367         hw_atl_reg_tx_dma_debug_ctl_set(self, 0x800000b8U);
 368         hw_atl_reg_tx_dma_debug_ctl_set(self, 0x000000b8U);
 369
 370         hw_atl_a0_hw_qos_set(self);
 371         hw_atl_a0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
 372         hw_atl_a0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
 373
 374         /* Reset link status and read out initial hardware counters */
 375         self->aq_link_status.mbps = 0;
 376         self->aq_fw_ops->update_stats(self);
 377
 378         err = aq_hw_err_from_flags(self);
 379         if (err < 0)
 380                 goto err_exit;
 381
 382         /* Interrupts */
 383         hw_atl_reg_irq_glb_ctl_set(self,
 384                                    aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
 385                                         [(aq_nic_cfg->vecs > 1U) ? 1 : 0]);
 386
 387         hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
 388
 389         /* Interrupts */
 390         hw_atl_reg_gen_irq_map_set(self,
 391                                    ((HW_ATL_A0_ERR_INT << 0x18) | (1U << 0x1F)) |
 392                                    ((HW_ATL_A0_ERR_INT << 0x10) | (1U << 0x17)) |
 393                                    ((HW_ATL_A0_ERR_INT << 8) | (1U << 0xF)) |
 394                                    ((HW_ATL_A0_ERR_INT) | (1U << 0x7)), 0U);
 395
 396         hw_atl_a0_hw_offload_set(self, aq_nic_cfg);
 397
 398 err_exit:
 399         return err;
 400 }
 401
 402 static int hw_atl_a0_hw_ring_tx_start(struct aq_hw_s *self,
 403                                       struct aq_ring_s *ring)
 404 {
 405         hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx);
 406
 407         return aq_hw_err_from_flags(self);
 408 }
 409
 410 static int hw_atl_a0_hw_ring_rx_start(struct aq_hw_s *self,
 411                                       struct aq_ring_s *ring)
 412 {
 413         hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx);
 414
 415         return aq_hw_err_from_flags(self);
 416 }
 417
 418 static int hw_atl_a0_hw_start(struct aq_hw_s *self)
 419 {
 420         hw_atl_tpb_tx_buff_en_set(self, 1);
 421         hw_atl_rpb_rx_buff_en_set(self, 1);
 422
 423         return aq_hw_err_from_flags(self);
 424 }
 425
 426 static int hw_atl_a0_hw_tx_ring_tail_update(struct aq_hw_s *self,
 427                                             struct aq_ring_s *ring)
 428 {
 429         hw_atl_reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
 430
 431         return 0;
 432 }
 433
 434 static int hw_atl_a0_hw_ring_tx_xmit(struct aq_hw_s *self,
 435                                      struct aq_ring_s *ring,
 436                                      unsigned int frags)
 437 {
 438         struct aq_ring_buff_s *buff = NULL;
 439         struct hw_atl_txd_s *txd = NULL;
 440         unsigned int buff_pa_len = 0U;
 441         unsigned int frag_count = 0U;
 442         unsigned int pkt_len = 0U;
 443         bool is_gso = false;
 444
 445         buff = &ring->buff_ring[ring->sw_tail];
 446         pkt_len = (buff->is_eop && buff->is_sop) ? buff->len : buff->len_pkt;
 447
 448         for (frag_count = 0; frag_count < frags; frag_count++) {
 449                 txd = (struct hw_atl_txd_s *)&ring->dx_ring[ring->sw_tail *
 450                                                 HW_ATL_A0_TXD_SIZE];
 451                 txd->ctl = 0;
 452                 txd->ctl2 = 0;
 453                 txd->buf_addr = 0;
 454
 455                 buff = &ring->buff_ring[ring->sw_tail];
 456
 457                 if (buff->is_gso_tcp) {
 458                         txd->ctl |= (buff->len_l3 << 31) |
 459                                 (buff->len_l2 << 24) |
 460                                 HW_ATL_A0_TXD_CTL_CMD_TCP |
 461                                 HW_ATL_A0_TXD_CTL_DESC_TYPE_TXC;
 462                         txd->ctl2 |= (buff->mss << 16) |
 463                                 (buff->len_l4 << 8) |
 464                                 (buff->len_l3 >> 1);
 465
 466                         pkt_len -= (buff->len_l4 +
 467                                     buff->len_l3 +
 468                                     buff->len_l2);
 469                         is_gso = true;
 470
 471                         if (buff->is_ipv6)
 472                                 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_IPV6;
 473                 } else {
 474                         buff_pa_len = buff->len;
 475
 476                         txd->buf_addr = buff->pa;
 477                         txd->ctl |= (HW_ATL_A0_TXD_CTL_BLEN &
 478                                                 ((u32)buff_pa_len << 4));
 479                         txd->ctl |= HW_ATL_A0_TXD_CTL_DESC_TYPE_TXD;
 480                         /* PAY_LEN */
 481                         txd->ctl2 |= HW_ATL_A0_TXD_CTL2_LEN & (pkt_len << 14);
 482
 483                         if (is_gso) {
 484                                 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_LSO;
 485                                 txd->ctl2 |= HW_ATL_A0_TXD_CTL2_CTX_EN;
 486                         }
 487
 488                         /* Tx checksum offloads */
 489                         if (buff->is_ip_cso)
 490                                 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_IPCSO;
 491
 492                         if (buff->is_udp_cso || buff->is_tcp_cso)
 493                                 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_TUCSO;
 494
 495                         if (unlikely(buff->is_eop)) {
 496                                 txd->ctl |= HW_ATL_A0_TXD_CTL_EOP;
 497                                 txd->ctl |= HW_ATL_A0_TXD_CTL_CMD_WB;
 498                                 is_gso = false;
 499                         }
 500                 }
 501
 502                 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail);
 503         }
 504
 505         hw_atl_a0_hw_tx_ring_tail_update(self, ring);
 506
 507         return aq_hw_err_from_flags(self);
 508 }
 509
 510 static int hw_atl_a0_hw_ring_rx_init(struct aq_hw_s *self,
 511                                      struct aq_ring_s *aq_ring,
 512                                      struct aq_ring_param_s *aq_ring_param)
 513 {
 514         u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
 515         u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
 516
 517         hw_atl_rdm_rx_desc_en_set(self, false, aq_ring->idx);
 518
 519         hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
 520
 521         hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
 522                                                   aq_ring->idx);
 523
 524         hw_atl_reg_rx_dma_desc_base_addressmswset(self,
 525                                                   dma_desc_addr_msw,
 526                                                   aq_ring->idx);
 527
 528         hw_atl_rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
 529
 530         hw_atl_rdm_rx_desc_data_buff_size_set(self,
 531                                               AQ_CFG_RX_FRAME_MAX / 1024U,
 532                                               aq_ring->idx);
 533
 534         hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
 535         hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
 536         hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
 537
 538         /* Rx ring set mode */
 539
 540         /* Mapping interrupt vector */
 541         hw_atl_itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
 542         hw_atl_itr_irq_map_en_rx_set(self, true, aq_ring->idx);
 543
 544         hw_atl_rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
 545         hw_atl_rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
 546         hw_atl_rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
 547         hw_atl_rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
 548
 549         return aq_hw_err_from_flags(self);
 550 }
 551
 552 static int hw_atl_a0_hw_ring_tx_init(struct aq_hw_s *self,
 553                                      struct aq_ring_s *aq_ring,
 554                                      struct aq_ring_param_s *aq_ring_param)
 555 {
 556         u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
 557         u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
 558
 559         hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
 560                                                   aq_ring->idx);
 561
 562         hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
 563                                                   aq_ring->idx);
 564
 565         hw_atl_tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
 566
 567         hw_atl_a0_hw_tx_ring_tail_update(self, aq_ring);
 568
 569         /* Set Tx threshold */
 570         hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
 571
 572         /* Mapping interrupt vector */
 573         hw_atl_itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
 574         hw_atl_itr_irq_map_en_tx_set(self, true, aq_ring->idx);
 575
 576         hw_atl_tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
 577         hw_atl_tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
 578
 579         return aq_hw_err_from_flags(self);
 580 }
 581
 582 static int hw_atl_a0_hw_ring_rx_fill(struct aq_hw_s *self,
 583                                      struct aq_ring_s *ring,
 584                                      unsigned int sw_tail_old)
 585 {
 586         for (; sw_tail_old != ring->sw_tail;
 587                 sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) {
 588                 struct hw_atl_rxd_s *rxd =
 589                         (struct hw_atl_rxd_s *)&ring->dx_ring[sw_tail_old *
 590                                                         HW_ATL_A0_RXD_SIZE];
 591
 592                 struct aq_ring_buff_s *buff = &ring->buff_ring[sw_tail_old];
 593
 594                 rxd->buf_addr = buff->pa;
 595                 rxd->hdr_addr = 0U;
 596         }
 597
 598         hw_atl_reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
 599
 600         return aq_hw_err_from_flags(self);
 601 }
 602
 603 static int hw_atl_a0_hw_ring_tx_head_update(struct aq_hw_s *self,
 604                                             struct aq_ring_s *ring)
 605 {
 606         unsigned int hw_head = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx);
 607         int err = 0;
 608
 609         if (aq_utils_obj_test(&self->flags, AQ_HW_FLAG_ERR_UNPLUG)) {
 610                 err = -ENXIO;
 611                 goto err_exit;
 612         }
 613         ring->hw_head = hw_head;
 614         err = aq_hw_err_from_flags(self);
 615
 616 err_exit:
 617         return err;
 618 }
 619
 620 static int hw_atl_a0_hw_ring_rx_receive(struct aq_hw_s *self,
 621                                         struct aq_ring_s *ring)
 622 {
 623         for (; ring->hw_head != ring->sw_tail;
 624                 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
 625                 struct aq_ring_buff_s *buff = NULL;
 626                 struct hw_atl_rxd_wb_s *rxd_wb = (struct hw_atl_rxd_wb_s *)
 627                         &ring->dx_ring[ring->hw_head * HW_ATL_A0_RXD_SIZE];
 628
 629                 unsigned int is_err = 1U;
 630                 unsigned int is_rx_check_sum_enabled = 0U;
 631                 unsigned int pkt_type = 0U;
 632
 633                 if (!(rxd_wb->status & 0x5U)) { /* RxD is not done */
 634                         if ((1U << 4) &
 635                         hw_atl_reg_rx_dma_desc_status_get(self, ring->idx)) {
 636                                 hw_atl_rdm_rx_desc_en_set(self, false, ring->idx);
 637                                 hw_atl_rdm_rx_desc_res_set(self, true, ring->idx);
 638                                 hw_atl_rdm_rx_desc_res_set(self, false, ring->idx);
 639                                 hw_atl_rdm_rx_desc_en_set(self, true, ring->idx);
 640                         }
 641
 642                         if (ring->hw_head ||
 643                             (hw_atl_rdm_rx_desc_head_ptr_get(self,
 644                                                              ring->idx) < 2U)) {
 645                                 break;
 646                         } else if (!(rxd_wb->status & 0x1U)) {
 647                                 struct hw_atl_rxd_wb_s *rxd_wb1 =
 648                                         (struct hw_atl_rxd_wb_s *)
 649                                         (&ring->dx_ring[(1U) *
 650                                                 HW_ATL_A0_RXD_SIZE]);
 651
 652                                 if ((rxd_wb1->status & 0x1U)) {
 653                                         rxd_wb->pkt_len = 1514U;
 654                                         rxd_wb->status = 3U;
 655                                 } else {
 656                                         break;
 657                                 }
 658                         }
 659                 }
 660
 661                 buff = &ring->buff_ring[ring->hw_head];
 662
 663                 if (0x3U != (rxd_wb->status & 0x3U))
 664                         rxd_wb->status |= 4;
 665
 666                 is_err = (0x0000001CU & rxd_wb->status);
 667                 is_rx_check_sum_enabled = (rxd_wb->type) & (0x3U << 19);
 668                 pkt_type = 0xFFU & (rxd_wb->type >> 4);
 669
 670                 if (is_rx_check_sum_enabled) {
 671                         if (0x0U == (pkt_type & 0x3U))
 672                                 buff->is_ip_cso = (is_err & 0x08U) ? 0 : 1;
 673
 674                         if (0x4U == (pkt_type & 0x1CU))
 675                                 buff->is_udp_cso = (is_err & 0x10U) ? 0 : 1;
 676                         else if (0x0U == (pkt_type & 0x1CU))
 677                                 buff->is_tcp_cso = (is_err & 0x10U) ? 0 : 1;
 678
 679                         /* Checksum offload workaround for small packets */
 680                         if (rxd_wb->pkt_len <= 60) {
 681                                 buff->is_ip_cso = 0U;
 682                                 buff->is_cso_err = 0U;
 683                         }
 684                 }
 685
 686                 is_err &= ~0x18U;
 687                 is_err &= ~0x04U;
 688
 689                 if (is_err || rxd_wb->type & 0x1000U) {
 690                         /* status error or DMA error */
 691                         buff->is_error = 1U;
 692                 } else {
 693                         if (self->aq_nic_cfg->is_rss) {
 694                                 /* last 4 byte */
 695                                 u16 rss_type = rxd_wb->type & 0xFU;
 696
 697                                 if (rss_type && rss_type < 0x8U) {
 698                                         buff->is_hash_l4 = (rss_type == 0x4 ||
 699                                                         rss_type == 0x5);
 700                                         buff->rss_hash = rxd_wb->rss_hash;
 701                                 }
 702                         }
 703
 704                         if (HW_ATL_A0_RXD_WB_STAT2_EOP & rxd_wb->status) {
 705                                 buff->len = rxd_wb->pkt_len %
 706                                         AQ_CFG_RX_FRAME_MAX;
 707                                 buff->len = buff->len ?
 708                                         buff->len : AQ_CFG_RX_FRAME_MAX;
 709                                 buff->next = 0U;
 710                                 buff->is_eop = 1U;
 711                         } else {
 712                                 /* jumbo */
 713                                 buff->next = aq_ring_next_dx(ring,
 714                                                              ring->hw_head);
 715                                 ++ring->stats.rx.jumbo_packets;
 716                         }
 717                 }
 718         }
 719
 720         return aq_hw_err_from_flags(self);
 721 }
 722
 723 static int hw_atl_a0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
 724 {
 725         hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask) |
 726                                (1U << HW_ATL_A0_ERR_INT));
 727
 728         return aq_hw_err_from_flags(self);
 729 }
 730
 731 static int hw_atl_a0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
 732 {
 733         hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask));
 734         hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask));
 735
 736         if ((1U << 16) & hw_atl_reg_gen_irq_status_get(self))
 737                 atomic_inc(&self->dpc);
 738
 739         return aq_hw_err_from_flags(self);
 740 }
 741
 742 static int hw_atl_a0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
 743 {
 744         *mask = hw_atl_itr_irq_statuslsw_get(self);
 745
 746         return aq_hw_err_from_flags(self);
 747 }
 748
 749 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
 750
 751 static int hw_atl_a0_hw_packet_filter_set(struct aq_hw_s *self,
 752                                           unsigned int packet_filter)
 753 {
 754         unsigned int i = 0U;
 755
 756         hw_atl_rpfl2promiscuous_mode_en_set(self,
 757                                             IS_FILTER_ENABLED(IFF_PROMISC));
 758         hw_atl_rpfl2multicast_flr_en_set(self,
 759                                          IS_FILTER_ENABLED(IFF_MULTICAST), 0);
 760         hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
 761
 762         self->aq_nic_cfg->is_mc_list_enabled =
 763                         IS_FILTER_ENABLED(IFF_MULTICAST);
 764
 765         for (i = HW_ATL_A0_MAC_MIN; i < HW_ATL_A0_MAC_MAX; ++i)
 766                 hw_atl_rpfl2_uc_flr_en_set(self,
 767                                            (self->aq_nic_cfg->is_mc_list_enabled &&
 768                                            (i <= self->aq_nic_cfg->mc_list_count)) ?
 769                                            1U : 0U, i);
 770
 771         return aq_hw_err_from_flags(self);
 772 }
 773
 774 #undef IS_FILTER_ENABLED
 775
 776 static int hw_atl_a0_hw_multicast_list_set(struct aq_hw_s *self,
 777                                            u8 ar_mac
 778                                            [AQ_HW_MULTICAST_ADDRESS_MAX]
 779                                            [ETH_ALEN],
 780                                            u32 count)
 781 {
 782         int err = 0;
 783
 784         if (count > (HW_ATL_A0_MAC_MAX - HW_ATL_A0_MAC_MIN)) {
 785                 err = EBADRQC;
 786                 goto err_exit;
 787         }
 788         for (self->aq_nic_cfg->mc_list_count = 0U;
 789                         self->aq_nic_cfg->mc_list_count < count;
 790                         ++self->aq_nic_cfg->mc_list_count) {
 791                 u32 i = self->aq_nic_cfg->mc_list_count;
 792                 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
 793                 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
 794                                         (ar_mac[i][4] << 8) | ar_mac[i][5];
 795
 796                 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_A0_MAC_MIN + i);
 797
 798                 hw_atl_rpfl2unicast_dest_addresslsw_set(self,
 799                                                         l,
 800                                                         HW_ATL_A0_MAC_MIN + i);
 801
 802                 hw_atl_rpfl2unicast_dest_addressmsw_set(self,
 803                                                         h,
 804                                                         HW_ATL_A0_MAC_MIN + i);
 805
 806                 hw_atl_rpfl2_uc_flr_en_set(self,
 807                                            (self->aq_nic_cfg->is_mc_list_enabled),
 808                                            HW_ATL_A0_MAC_MIN + i);
 809         }
 810
 811         err = aq_hw_err_from_flags(self);
 812
 813 err_exit:
 814         return err;
 815 }
 816
 817 static int hw_atl_a0_hw_interrupt_moderation_set(struct aq_hw_s *self)
 818 {
 819         unsigned int i = 0U;
 820         u32 itr_rx;
 821
 822         if (self->aq_nic_cfg->itr) {
 823                 if (self->aq_nic_cfg->itr != AQ_CFG_INTERRUPT_MODERATION_AUTO) {
 824                         u32 itr_ = (self->aq_nic_cfg->itr >> 1);
 825
 826                         itr_ = min(AQ_CFG_IRQ_MASK, itr_);
 827
 828                         itr_rx = 0x80000000U | (itr_ << 0x10);
 829                 } else  {
 830                         u32 n = 0xFFFFU & aq_hw_read_reg(self, 0x00002A00U);
 831
 832                         if (n < self->aq_link_status.mbps) {
 833                                 itr_rx = 0U;
 834                         } else {
 835                                 static unsigned int hw_timers_tbl_[] = {
 836                                         0x01CU, /* 10Gbit */
 837                                         0x039U, /* 5Gbit */
 838                                         0x039U, /* 5Gbit 5GS */
 839                                         0x073U, /* 2.5Gbit */
 840                                         0x120U, /* 1Gbit */
 841                                         0x1FFU, /* 100Mbit */
 842                                 };
 843
 844                                 unsigned int speed_index =
 845                                         hw_atl_utils_mbps_2_speed_index(
 846                                                 self->aq_link_status.mbps);
 847
 848                                 itr_rx = 0x80000000U |
 849                                         (hw_timers_tbl_[speed_index] << 0x10U);
 850                         }
 851
 852                         aq_hw_write_reg(self, 0x00002A00U, 0x40000000U);
 853                         aq_hw_write_reg(self, 0x00002A00U, 0x8D000000U);
 854                 }
 855         } else {
 856                 itr_rx = 0U;
 857         }
 858
 859         for (i = HW_ATL_A0_RINGS_MAX; i--;)
 860                 hw_atl_reg_irq_thr_set(self, itr_rx, i);
 861
 862         return aq_hw_err_from_flags(self);
 863 }
 864
 865 static int hw_atl_a0_hw_stop(struct aq_hw_s *self)
 866 {
 867         hw_atl_a0_hw_irq_disable(self, HW_ATL_A0_INT_MASK);
 868
 869         return aq_hw_err_from_flags(self);
 870 }
 871
 872 static int hw_atl_a0_hw_ring_tx_stop(struct aq_hw_s *self,
 873                                      struct aq_ring_s *ring)
 874 {
 875         hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx);
 876
 877         return aq_hw_err_from_flags(self);
 878 }
 879
 880 static int hw_atl_a0_hw_ring_rx_stop(struct aq_hw_s *self,
 881                                      struct aq_ring_s *ring)
 882 {
 883         hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx);
 884
 885         return aq_hw_err_from_flags(self);
 886 }
 887
 888 const struct aq_hw_ops hw_atl_ops_a0 = {
 889         .hw_set_mac_address   = hw_atl_a0_hw_mac_addr_set,
 890         .hw_init              = hw_atl_a0_hw_init,
 891         .hw_reset             = hw_atl_a0_hw_reset,
 892         .hw_start             = hw_atl_a0_hw_start,
 893         .hw_ring_tx_start     = hw_atl_a0_hw_ring_tx_start,
 894         .hw_ring_tx_stop      = hw_atl_a0_hw_ring_tx_stop,
 895         .hw_ring_rx_start     = hw_atl_a0_hw_ring_rx_start,
 896         .hw_ring_rx_stop      = hw_atl_a0_hw_ring_rx_stop,
 897         .hw_stop              = hw_atl_a0_hw_stop,
 898
 899         .hw_ring_tx_xmit         = hw_atl_a0_hw_ring_tx_xmit,
 900         .hw_ring_tx_head_update  = hw_atl_a0_hw_ring_tx_head_update,
 901
 902         .hw_ring_rx_receive      = hw_atl_a0_hw_ring_rx_receive,
 903         .hw_ring_rx_fill         = hw_atl_a0_hw_ring_rx_fill,
 904
 905         .hw_irq_enable           = hw_atl_a0_hw_irq_enable,
 906         .hw_irq_disable          = hw_atl_a0_hw_irq_disable,
 907         .hw_irq_read             = hw_atl_a0_hw_irq_read,
 908
 909         .hw_ring_rx_init             = hw_atl_a0_hw_ring_rx_init,
 910         .hw_ring_tx_init             = hw_atl_a0_hw_ring_tx_init,
 911         .hw_packet_filter_set        = hw_atl_a0_hw_packet_filter_set,
 912         .hw_multicast_list_set       = hw_atl_a0_hw_multicast_list_set,
 913         .hw_interrupt_moderation_set = hw_atl_a0_hw_interrupt_moderation_set,
 914         .hw_rss_set                  = hw_atl_a0_hw_rss_set,
 915         .hw_rss_hash_set             = hw_atl_a0_hw_rss_hash_set,
 916         .hw_get_regs                 = hw_atl_utils_hw_get_regs,
 917         .hw_get_hw_stats             = hw_atl_utils_get_hw_stats,
 918         .hw_get_fw_version           = hw_atl_utils_get_fw_version,
 919 };