drivers/media/dvb-frontends/rtl2832.c

   1 /*
   2  * Realtek RTL2832 DVB-T demodulator driver
   3  *
   4  * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
   5  * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
   6  *
   7  *      This program is free software; you can redistribute it and/or modify
   8  *      it under the terms of the GNU General Public License as published by
   9  *      the Free Software Foundation; either version 2 of the License, or
  10  *      (at your option) any later version.
  11  *
  12  *      This program is distributed in the hope that it will be useful,
  13  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *      GNU General Public License for more details.
  16  *
  17  *      You should have received a copy of the GNU General Public License along
  18  *      with this program; if not, write to the Free Software Foundation, Inc.,
  19  *      51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  20  */
  21
  22 #include "rtl2832_priv.h"
  23
  24 #define REG_MASK(b) (BIT(b + 1) - 1)
  25
  26 static const struct rtl2832_reg_entry registers[] = {
  27         [DVBT_SOFT_RST]         = {0x101,  2, 2},
  28         [DVBT_IIC_REPEAT]       = {0x101,  3, 3},
  29         [DVBT_TR_WAIT_MIN_8K]   = {0x188, 11, 2},
  30         [DVBT_RSD_BER_FAIL_VAL] = {0x18f, 15, 0},
  31         [DVBT_EN_BK_TRK]        = {0x1a6,  7, 7},
  32         [DVBT_AD_EN_REG]        = {0x008,  7, 7},
  33         [DVBT_AD_EN_REG1]       = {0x008,  6, 6},
  34         [DVBT_EN_BBIN]          = {0x1b1,  0, 0},
  35         [DVBT_MGD_THD0]         = {0x195,  7, 0},
  36         [DVBT_MGD_THD1]         = {0x196,  7, 0},
  37         [DVBT_MGD_THD2]         = {0x197,  7, 0},
  38         [DVBT_MGD_THD3]         = {0x198,  7, 0},
  39         [DVBT_MGD_THD4]         = {0x199,  7, 0},
  40         [DVBT_MGD_THD5]         = {0x19a,  7, 0},
  41         [DVBT_MGD_THD6]         = {0x19b,  7, 0},
  42         [DVBT_MGD_THD7]         = {0x19c,  7, 0},
  43         [DVBT_EN_CACQ_NOTCH]    = {0x161,  4, 4},
  44         [DVBT_AD_AV_REF]        = {0x009,  6, 0},
  45         [DVBT_REG_PI]           = {0x00a,  2, 0},
  46         [DVBT_PIP_ON]           = {0x021,  3, 3},
  47         [DVBT_SCALE1_B92]       = {0x292,  7, 0},
  48         [DVBT_SCALE1_B93]       = {0x293,  7, 0},
  49         [DVBT_SCALE1_BA7]       = {0x2a7,  7, 0},
  50         [DVBT_SCALE1_BA9]       = {0x2a9,  7, 0},
  51         [DVBT_SCALE1_BAA]       = {0x2aa,  7, 0},
  52         [DVBT_SCALE1_BAB]       = {0x2ab,  7, 0},
  53         [DVBT_SCALE1_BAC]       = {0x2ac,  7, 0},
  54         [DVBT_SCALE1_BB0]       = {0x2b0,  7, 0},
  55         [DVBT_SCALE1_BB1]       = {0x2b1,  7, 0},
  56         [DVBT_KB_P1]            = {0x164,  3, 1},
  57         [DVBT_KB_P2]            = {0x164,  6, 4},
  58         [DVBT_KB_P3]            = {0x165,  2, 0},
  59         [DVBT_OPT_ADC_IQ]       = {0x006,  5, 4},
  60         [DVBT_AD_AVI]           = {0x009,  1, 0},
  61         [DVBT_AD_AVQ]           = {0x009,  3, 2},
  62         [DVBT_K1_CR_STEP12]     = {0x2ad,  9, 4},
  63         [DVBT_TRK_KS_P2]        = {0x16f,  2, 0},
  64         [DVBT_TRK_KS_I2]        = {0x170,  5, 3},
  65         [DVBT_TR_THD_SET2]      = {0x172,  3, 0},
  66         [DVBT_TRK_KC_P2]        = {0x173,  5, 3},
  67         [DVBT_TRK_KC_I2]        = {0x175,  2, 0},
  68         [DVBT_CR_THD_SET2]      = {0x176,  7, 6},
  69         [DVBT_PSET_IFFREQ]      = {0x119, 21, 0},
  70         [DVBT_SPEC_INV]         = {0x115,  0, 0},
  71         [DVBT_RSAMP_RATIO]      = {0x19f, 27, 2},
  72         [DVBT_CFREQ_OFF_RATIO]  = {0x19d, 23, 4},
  73         [DVBT_FSM_STAGE]        = {0x351,  6, 3},
  74         [DVBT_RX_CONSTEL]       = {0x33c,  3, 2},
  75         [DVBT_RX_HIER]          = {0x33c,  6, 4},
  76         [DVBT_RX_C_RATE_LP]     = {0x33d,  2, 0},
  77         [DVBT_RX_C_RATE_HP]     = {0x33d,  5, 3},
  78         [DVBT_GI_IDX]           = {0x351,  1, 0},
  79         [DVBT_FFT_MODE_IDX]     = {0x351,  2, 2},
  80         [DVBT_RSD_BER_EST]      = {0x34e, 15, 0},
  81         [DVBT_CE_EST_EVM]       = {0x40c, 15, 0},
  82         [DVBT_RF_AGC_VAL]       = {0x35b, 13, 0},
  83         [DVBT_IF_AGC_VAL]       = {0x359, 13, 0},
  84         [DVBT_DAGC_VAL]         = {0x305,  7, 0},
  85         [DVBT_SFREQ_OFF]        = {0x318, 13, 0},
  86         [DVBT_CFREQ_OFF]        = {0x35f, 17, 0},
  87         [DVBT_POLAR_RF_AGC]     = {0x00e,  1, 1},
  88         [DVBT_POLAR_IF_AGC]     = {0x00e,  0, 0},
  89         [DVBT_AAGC_HOLD]        = {0x104,  5, 5},
  90         [DVBT_EN_RF_AGC]        = {0x104,  6, 6},
  91         [DVBT_EN_IF_AGC]        = {0x104,  7, 7},
  92         [DVBT_IF_AGC_MIN]       = {0x108,  7, 0},
  93         [DVBT_IF_AGC_MAX]       = {0x109,  7, 0},
  94         [DVBT_RF_AGC_MIN]       = {0x10a,  7, 0},
  95         [DVBT_RF_AGC_MAX]       = {0x10b,  7, 0},
  96         [DVBT_IF_AGC_MAN]       = {0x10c,  6, 6},
  97         [DVBT_IF_AGC_MAN_VAL]   = {0x10c, 13, 0},
  98         [DVBT_RF_AGC_MAN]       = {0x10e,  6, 6},
  99         [DVBT_RF_AGC_MAN_VAL]   = {0x10e, 13, 0},
 100         [DVBT_DAGC_TRG_VAL]     = {0x112,  7, 0},
 101         [DVBT_AGC_TARG_VAL_0]   = {0x102,  0, 0},
 102         [DVBT_AGC_TARG_VAL_8_1] = {0x103,  7, 0},
 103         [DVBT_AAGC_LOOP_GAIN]   = {0x1c7,  5, 1},
 104         [DVBT_LOOP_GAIN2_3_0]   = {0x104,  4, 1},
 105         [DVBT_LOOP_GAIN2_4]     = {0x105,  7, 7},
 106         [DVBT_LOOP_GAIN3]       = {0x1c8,  4, 0},
 107         [DVBT_VTOP1]            = {0x106,  5, 0},
 108         [DVBT_VTOP2]            = {0x1c9,  5, 0},
 109         [DVBT_VTOP3]            = {0x1ca,  5, 0},
 110         [DVBT_KRF1]             = {0x1cb,  7, 0},
 111         [DVBT_KRF2]             = {0x107,  7, 0},
 112         [DVBT_KRF3]             = {0x1cd,  7, 0},
 113         [DVBT_KRF4]             = {0x1ce,  7, 0},
 114         [DVBT_EN_GI_PGA]        = {0x1e5,  0, 0},
 115         [DVBT_THD_LOCK_UP]      = {0x1d9,  8, 0},
 116         [DVBT_THD_LOCK_DW]      = {0x1db,  8, 0},
 117         [DVBT_THD_UP1]          = {0x1dd,  7, 0},
 118         [DVBT_THD_DW1]          = {0x1de,  7, 0},
 119         [DVBT_INTER_CNT_LEN]    = {0x1d8,  3, 0},
 120         [DVBT_GI_PGA_STATE]     = {0x1e6,  3, 3},
 121         [DVBT_EN_AGC_PGA]       = {0x1d7,  0, 0},
 122         [DVBT_CKOUTPAR]         = {0x17b,  5, 5},
 123         [DVBT_CKOUT_PWR]        = {0x17b,  6, 6},
 124         [DVBT_SYNC_DUR]         = {0x17b,  7, 7},
 125         [DVBT_ERR_DUR]          = {0x17c,  0, 0},
 126         [DVBT_SYNC_LVL]         = {0x17c,  1, 1},
 127         [DVBT_ERR_LVL]          = {0x17c,  2, 2},
 128         [DVBT_VAL_LVL]          = {0x17c,  3, 3},
 129         [DVBT_SERIAL]           = {0x17c,  4, 4},
 130         [DVBT_SER_LSB]          = {0x17c,  5, 5},
 131         [DVBT_CDIV_PH0]         = {0x17d,  3, 0},
 132         [DVBT_CDIV_PH1]         = {0x17d,  7, 4},
 133         [DVBT_MPEG_IO_OPT_2_2]  = {0x006,  7, 7},
 134         [DVBT_MPEG_IO_OPT_1_0]  = {0x007,  7, 6},
 135         [DVBT_CKOUTPAR_PIP]     = {0x0b7,  4, 4},
 136         [DVBT_CKOUT_PWR_PIP]    = {0x0b7,  3, 3},
 137         [DVBT_SYNC_LVL_PIP]     = {0x0b7,  2, 2},
 138         [DVBT_ERR_LVL_PIP]      = {0x0b7,  1, 1},
 139         [DVBT_VAL_LVL_PIP]      = {0x0b7,  0, 0},
 140         [DVBT_CKOUTPAR_PID]     = {0x0b9,  4, 4},
 141         [DVBT_CKOUT_PWR_PID]    = {0x0b9,  3, 3},
 142         [DVBT_SYNC_LVL_PID]     = {0x0b9,  2, 2},
 143         [DVBT_ERR_LVL_PID]      = {0x0b9,  1, 1},
 144         [DVBT_VAL_LVL_PID]      = {0x0b9,  0, 0},
 145         [DVBT_SM_PASS]          = {0x193, 11, 0},
 146         [DVBT_AD7_SETTING]      = {0x011, 15, 0},
 147         [DVBT_RSSI_R]           = {0x301,  6, 0},
 148         [DVBT_ACI_DET_IND]      = {0x312,  0, 0},
 149         [DVBT_REG_MON]          = {0x00d,  1, 0},
 150         [DVBT_REG_MONSEL]       = {0x00d,  2, 2},
 151         [DVBT_REG_GPE]          = {0x00d,  7, 7},
 152         [DVBT_REG_GPO]          = {0x010,  0, 0},
 153         [DVBT_REG_4MSEL]        = {0x013,  0, 0},
 154 };
 155
 156 /* Our regmap is bypassing I2C adapter lock, thus we do it! */
 157 static int rtl2832_bulk_write(struct i2c_client *client, unsigned int reg,
 158                               const void *val, size_t val_count)
 159 {
 160         struct rtl2832_dev *dev = i2c_get_clientdata(client);
 161         int ret;
 162
 163         i2c_lock_adapter(client->adapter);
 164         ret = regmap_bulk_write(dev->regmap, reg, val, val_count);
 165         i2c_unlock_adapter(client->adapter);
 166         return ret;
 167 }
 168
 169 static int rtl2832_update_bits(struct i2c_client *client, unsigned int reg,
 170                                unsigned int mask, unsigned int val)
 171 {
 172         struct rtl2832_dev *dev = i2c_get_clientdata(client);
 173         int ret;
 174
 175         i2c_lock_adapter(client->adapter);
 176         ret = regmap_update_bits(dev->regmap, reg, mask, val);
 177         i2c_unlock_adapter(client->adapter);
 178         return ret;
 179 }
 180
 181 static int rtl2832_bulk_read(struct i2c_client *client, unsigned int reg,
 182                              void *val, size_t val_count)
 183 {
 184         struct rtl2832_dev *dev = i2c_get_clientdata(client);
 185         int ret;
 186
 187         i2c_lock_adapter(client->adapter);
 188         ret = regmap_bulk_read(dev->regmap, reg, val, val_count);
 189         i2c_unlock_adapter(client->adapter);
 190         return ret;
 191 }
 192
 193 static int rtl2832_rd_demod_reg(struct rtl2832_dev *dev, int reg, u32 *val)
 194 {
 195         struct i2c_client *client = dev->client;
 196         int ret, i;
 197         u16 reg_start_addr;
 198         u8 msb, lsb, reading[4], len;
 199         u32 reading_tmp, mask;
 200
 201         reg_start_addr = registers[reg].start_address;
 202         msb = registers[reg].msb;
 203         lsb = registers[reg].lsb;
 204         len = (msb >> 3) + 1;
 205         mask = REG_MASK(msb - lsb);
 206
 207         ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
 208         if (ret)
 209                 goto err;
 210
 211         reading_tmp = 0;
 212         for (i = 0; i < len; i++)
 213                 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
 214
 215         *val = (reading_tmp >> lsb) & mask;
 216
 217         return 0;
 218 err:
 219         dev_dbg(&client->dev, "failed=%d\n", ret);
 220         return ret;
 221 }
 222
 223 static int rtl2832_wr_demod_reg(struct rtl2832_dev *dev, int reg, u32 val)
 224 {
 225         struct i2c_client *client = dev->client;
 226         int ret, i;
 227         u16 reg_start_addr;
 228         u8 msb, lsb, reading[4], writing[4], len;
 229         u32 reading_tmp, writing_tmp, mask;
 230
 231         reg_start_addr = registers[reg].start_address;
 232         msb = registers[reg].msb;
 233         lsb = registers[reg].lsb;
 234         len = (msb >> 3) + 1;
 235         mask = REG_MASK(msb - lsb);
 236
 237         ret = rtl2832_bulk_read(client, reg_start_addr, reading, len);
 238         if (ret)
 239                 goto err;
 240
 241         reading_tmp = 0;
 242         for (i = 0; i < len; i++)
 243                 reading_tmp |= reading[i] << ((len - 1 - i) * 8);
 244
 245         writing_tmp = reading_tmp & ~(mask << lsb);
 246         writing_tmp |= ((val & mask) << lsb);
 247
 248         for (i = 0; i < len; i++)
 249                 writing[i] = (writing_tmp >> ((len - 1 - i) * 8)) & 0xff;
 250
 251         ret = rtl2832_bulk_write(client, reg_start_addr, writing, len);
 252         if (ret)
 253                 goto err;
 254
 255         return 0;
 256 err:
 257         dev_dbg(&client->dev, "failed=%d\n", ret);
 258         return ret;
 259 }
 260
 261 static int rtl2832_set_if(struct dvb_frontend *fe, u32 if_freq)
 262 {
 263         struct rtl2832_dev *dev = fe->demodulator_priv;
 264         struct i2c_client *client = dev->client;
 265         int ret;
 266         u64 pset_iffreq;
 267         u8 en_bbin = (if_freq == 0 ? 0x1 : 0x0);
 268
 269         /*
 270         * PSET_IFFREQ = - floor((IfFreqHz % CrystalFreqHz) * pow(2, 22)
 271         *               / CrystalFreqHz)
 272         */
 273         pset_iffreq = if_freq % dev->pdata->clk;
 274         pset_iffreq *= 0x400000;
 275         pset_iffreq = div_u64(pset_iffreq, dev->pdata->clk);
 276         pset_iffreq = -pset_iffreq;
 277         pset_iffreq = pset_iffreq & 0x3fffff;
 278         dev_dbg(&client->dev, "if_frequency=%d pset_iffreq=%08x\n",
 279                 if_freq, (unsigned)pset_iffreq);
 280
 281         ret = rtl2832_wr_demod_reg(dev, DVBT_EN_BBIN, en_bbin);
 282         if (ret)
 283                 goto err;
 284
 285         ret = rtl2832_wr_demod_reg(dev, DVBT_PSET_IFFREQ, pset_iffreq);
 286         if (ret)
 287                 goto err;
 288
 289         return 0;
 290 err:
 291         dev_dbg(&client->dev, "failed=%d\n", ret);
 292         return ret;
 293 }
 294
 295 static int rtl2832_init(struct dvb_frontend *fe)
 296 {
 297         struct rtl2832_dev *dev = fe->demodulator_priv;
 298         struct i2c_client *client = dev->client;
 299         struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
 300         const struct rtl2832_reg_value *init;
 301         int i, ret, len;
 302         /* initialization values for the demodulator registers */
 303         struct rtl2832_reg_value rtl2832_initial_regs[] = {
 304                 {DVBT_AD_EN_REG,                0x1},
 305                 {DVBT_AD_EN_REG1,               0x1},
 306                 {DVBT_RSD_BER_FAIL_VAL,         0x2800},
 307                 {DVBT_MGD_THD0,                 0x10},
 308                 {DVBT_MGD_THD1,                 0x20},
 309                 {DVBT_MGD_THD2,                 0x20},
 310                 {DVBT_MGD_THD3,                 0x40},
 311                 {DVBT_MGD_THD4,                 0x22},
 312                 {DVBT_MGD_THD5,                 0x32},
 313                 {DVBT_MGD_THD6,                 0x37},
 314                 {DVBT_MGD_THD7,                 0x39},
 315                 {DVBT_EN_BK_TRK,                0x0},
 316                 {DVBT_EN_CACQ_NOTCH,            0x0},
 317                 {DVBT_AD_AV_REF,                0x2a},
 318                 {DVBT_REG_PI,                   0x6},
 319                 {DVBT_PIP_ON,                   0x0},
 320                 {DVBT_CDIV_PH0,                 0x8},
 321                 {DVBT_CDIV_PH1,                 0x8},
 322                 {DVBT_SCALE1_B92,               0x4},
 323                 {DVBT_SCALE1_B93,               0xb0},
 324                 {DVBT_SCALE1_BA7,               0x78},
 325                 {DVBT_SCALE1_BA9,               0x28},
 326                 {DVBT_SCALE1_BAA,               0x59},
 327                 {DVBT_SCALE1_BAB,               0x83},
 328                 {DVBT_SCALE1_BAC,               0xd4},
 329                 {DVBT_SCALE1_BB0,               0x65},
 330                 {DVBT_SCALE1_BB1,               0x43},
 331                 {DVBT_KB_P1,                    0x1},
 332                 {DVBT_KB_P2,                    0x4},
 333                 {DVBT_KB_P3,                    0x7},
 334                 {DVBT_K1_CR_STEP12,             0xa},
 335                 {DVBT_REG_GPE,                  0x1},
 336                 {DVBT_SERIAL,                   0x0},
 337                 {DVBT_CDIV_PH0,                 0x9},
 338                 {DVBT_CDIV_PH1,                 0x9},
 339                 {DVBT_MPEG_IO_OPT_2_2,          0x0},
 340                 {DVBT_MPEG_IO_OPT_1_0,          0x0},
 341                 {DVBT_TRK_KS_P2,                0x4},
 342                 {DVBT_TRK_KS_I2,                0x7},
 343                 {DVBT_TR_THD_SET2,              0x6},
 344                 {DVBT_TRK_KC_I2,                0x5},
 345                 {DVBT_CR_THD_SET2,              0x1},
 346         };
 347
 348         dev_dbg(&client->dev, "\n");
 349
 350         ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
 351         if (ret)
 352                 goto err;
 353
 354         for (i = 0; i < ARRAY_SIZE(rtl2832_initial_regs); i++) {
 355                 ret = rtl2832_wr_demod_reg(dev, rtl2832_initial_regs[i].reg,
 356                         rtl2832_initial_regs[i].value);
 357                 if (ret)
 358                         goto err;
 359         }
 360
 361         /* load tuner specific settings */
 362         dev_dbg(&client->dev, "load settings for tuner=%02x\n",
 363                 dev->pdata->tuner);
 364         switch (dev->pdata->tuner) {
 365         case RTL2832_TUNER_FC2580:
 366                 len = ARRAY_SIZE(rtl2832_tuner_init_fc2580);
 367                 init = rtl2832_tuner_init_fc2580;
 368                 break;
 369         case RTL2832_TUNER_FC0012:
 370         case RTL2832_TUNER_FC0013:
 371                 len = ARRAY_SIZE(rtl2832_tuner_init_fc0012);
 372                 init = rtl2832_tuner_init_fc0012;
 373                 break;
 374         case RTL2832_TUNER_TUA9001:
 375                 len = ARRAY_SIZE(rtl2832_tuner_init_tua9001);
 376                 init = rtl2832_tuner_init_tua9001;
 377                 break;
 378         case RTL2832_TUNER_E4000:
 379                 len = ARRAY_SIZE(rtl2832_tuner_init_e4000);
 380                 init = rtl2832_tuner_init_e4000;
 381                 break;
 382         case RTL2832_TUNER_R820T:
 383         case RTL2832_TUNER_R828D:
 384                 len = ARRAY_SIZE(rtl2832_tuner_init_r820t);
 385                 init = rtl2832_tuner_init_r820t;
 386                 break;
 387         case RTL2832_TUNER_SI2157:
 388                 len = ARRAY_SIZE(rtl2832_tuner_init_si2157);
 389                 init = rtl2832_tuner_init_si2157;
 390                 break;
 391         default:
 392                 ret = -EINVAL;
 393                 goto err;
 394         }
 395
 396         for (i = 0; i < len; i++) {
 397                 ret = rtl2832_wr_demod_reg(dev, init[i].reg, init[i].value);
 398                 if (ret)
 399                         goto err;
 400         }
 401
 402         /* init stats here in order signal app which stats are supported */
 403         c->strength.len = 1;
 404         c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 405         c->cnr.len = 1;
 406         c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 407         c->post_bit_error.len = 1;
 408         c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 409         c->post_bit_count.len = 1;
 410         c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 411         dev->sleeping = false;
 412
 413         return 0;
 414 err:
 415         dev_dbg(&client->dev, "failed=%d\n", ret);
 416         return ret;
 417 }
 418
 419 static int rtl2832_sleep(struct dvb_frontend *fe)
 420 {
 421         struct rtl2832_dev *dev = fe->demodulator_priv;
 422         struct i2c_client *client = dev->client;
 423         int ret;
 424
 425         dev_dbg(&client->dev, "\n");
 426
 427         dev->sleeping = true;
 428         dev->fe_status = 0;
 429
 430         ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
 431         if (ret)
 432                 goto err;
 433
 434         return 0;
 435 err:
 436         dev_dbg(&client->dev, "failed=%d\n", ret);
 437         return ret;
 438 }
 439
 440 static int rtl2832_get_tune_settings(struct dvb_frontend *fe,
 441         struct dvb_frontend_tune_settings *s)
 442 {
 443         struct rtl2832_dev *dev = fe->demodulator_priv;
 444         struct i2c_client *client = dev->client;
 445
 446         dev_dbg(&client->dev, "\n");
 447         s->min_delay_ms = 1000;
 448         s->step_size = fe->ops.info.frequency_stepsize * 2;
 449         s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
 450         return 0;
 451 }
 452
 453 static int rtl2832_set_frontend(struct dvb_frontend *fe)
 454 {
 455         struct rtl2832_dev *dev = fe->demodulator_priv;
 456         struct i2c_client *client = dev->client;
 457         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 458         int ret, i, j;
 459         u64 bw_mode, num, num2;
 460         u32 resamp_ratio, cfreq_off_ratio;
 461         static u8 bw_params[3][32] = {
 462         /* 6 MHz bandwidth */
 463                 {
 464                 0xf5, 0xff, 0x15, 0x38, 0x5d, 0x6d, 0x52, 0x07, 0xfa, 0x2f,
 465                 0x53, 0xf5, 0x3f, 0xca, 0x0b, 0x91, 0xea, 0x30, 0x63, 0xb2,
 466                 0x13, 0xda, 0x0b, 0xc4, 0x18, 0x7e, 0x16, 0x66, 0x08, 0x67,
 467                 0x19, 0xe0,
 468                 },
 469
 470         /*  7 MHz bandwidth */
 471                 {
 472                 0xe7, 0xcc, 0xb5, 0xba, 0xe8, 0x2f, 0x67, 0x61, 0x00, 0xaf,
 473                 0x86, 0xf2, 0xbf, 0x59, 0x04, 0x11, 0xb6, 0x33, 0xa4, 0x30,
 474                 0x15, 0x10, 0x0a, 0x42, 0x18, 0xf8, 0x17, 0xd9, 0x07, 0x22,
 475                 0x19, 0x10,
 476                 },
 477
 478         /*  8 MHz bandwidth */
 479                 {
 480                 0x09, 0xf6, 0xd2, 0xa7, 0x9a, 0xc9, 0x27, 0x77, 0x06, 0xbf,
 481                 0xec, 0xf4, 0x4f, 0x0b, 0xfc, 0x01, 0x63, 0x35, 0x54, 0xa7,
 482                 0x16, 0x66, 0x08, 0xb4, 0x19, 0x6e, 0x19, 0x65, 0x05, 0xc8,
 483                 0x19, 0xe0,
 484                 },
 485         };
 486
 487         dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u inversion=%u\n",
 488                 c->frequency, c->bandwidth_hz, c->inversion);
 489
 490         /* program tuner */
 491         if (fe->ops.tuner_ops.set_params)
 492                 fe->ops.tuner_ops.set_params(fe);
 493
 494         /* If the frontend has get_if_frequency(), use it */
 495         if (fe->ops.tuner_ops.get_if_frequency) {
 496                 u32 if_freq;
 497
 498                 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_freq);
 499                 if (ret)
 500                         goto err;
 501
 502                 ret = rtl2832_set_if(fe, if_freq);
 503                 if (ret)
 504                         goto err;
 505         }
 506
 507         switch (c->bandwidth_hz) {
 508         case 6000000:
 509                 i = 0;
 510                 bw_mode = 48000000;
 511                 break;
 512         case 7000000:
 513                 i = 1;
 514                 bw_mode = 56000000;
 515                 break;
 516         case 8000000:
 517                 i = 2;
 518                 bw_mode = 64000000;
 519                 break;
 520         default:
 521                 dev_err(&client->dev, "invalid bandwidth_hz %u\n",
 522                         c->bandwidth_hz);
 523                 ret = -EINVAL;
 524                 goto err;
 525         }
 526
 527         for (j = 0; j < sizeof(bw_params[0]); j++) {
 528                 ret = rtl2832_bulk_write(client, 0x11c + j, &bw_params[i][j], 1);
 529                 if (ret)
 530                         goto err;
 531         }
 532
 533         /* calculate and set resample ratio
 534         * RSAMP_RATIO = floor(CrystalFreqHz * 7 * pow(2, 22)
 535         *       / ConstWithBandwidthMode)
 536         */
 537         num = dev->pdata->clk * 7;
 538         num *= 0x400000;
 539         num = div_u64(num, bw_mode);
 540         resamp_ratio =  num & 0x3ffffff;
 541         ret = rtl2832_wr_demod_reg(dev, DVBT_RSAMP_RATIO, resamp_ratio);
 542         if (ret)
 543                 goto err;
 544
 545         /* calculate and set cfreq off ratio
 546         * CFREQ_OFF_RATIO = - floor(ConstWithBandwidthMode * pow(2, 20)
 547         *       / (CrystalFreqHz * 7))
 548         */
 549         num = bw_mode << 20;
 550         num2 = dev->pdata->clk * 7;
 551         num = div_u64(num, num2);
 552         num = -num;
 553         cfreq_off_ratio = num & 0xfffff;
 554         ret = rtl2832_wr_demod_reg(dev, DVBT_CFREQ_OFF_RATIO, cfreq_off_ratio);
 555         if (ret)
 556                 goto err;
 557
 558         /* soft reset */
 559         ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
 560         if (ret)
 561                 goto err;
 562
 563         ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
 564         if (ret)
 565                 goto err;
 566
 567         return 0;
 568 err:
 569         dev_dbg(&client->dev, "failed=%d\n", ret);
 570         return ret;
 571 }
 572
 573 static int rtl2832_get_frontend(struct dvb_frontend *fe,
 574                                 struct dtv_frontend_properties *c)
 575 {
 576         struct rtl2832_dev *dev = fe->demodulator_priv;
 577         struct i2c_client *client = dev->client;
 578         int ret;
 579         u8 buf[3];
 580
 581         if (dev->sleeping)
 582                 return 0;
 583
 584         ret = rtl2832_bulk_read(client, 0x33c, buf, 2);
 585         if (ret)
 586                 goto err;
 587
 588         ret = rtl2832_bulk_read(client, 0x351, &buf[2], 1);
 589         if (ret)
 590                 goto err;
 591
 592         dev_dbg(&client->dev, "TPS=%*ph\n", 3, buf);
 593
 594         switch ((buf[0] >> 2) & 3) {
 595         case 0:
 596                 c->modulation = QPSK;
 597                 break;
 598         case 1:
 599                 c->modulation = QAM_16;
 600                 break;
 601         case 2:
 602                 c->modulation = QAM_64;
 603                 break;
 604         }
 605
 606         switch ((buf[2] >> 2) & 1) {
 607         case 0:
 608                 c->transmission_mode = TRANSMISSION_MODE_2K;
 609                 break;
 610         case 1:
 611                 c->transmission_mode = TRANSMISSION_MODE_8K;
 612         }
 613
 614         switch ((buf[2] >> 0) & 3) {
 615         case 0:
 616                 c->guard_interval = GUARD_INTERVAL_1_32;
 617                 break;
 618         case 1:
 619                 c->guard_interval = GUARD_INTERVAL_1_16;
 620                 break;
 621         case 2:
 622                 c->guard_interval = GUARD_INTERVAL_1_8;
 623                 break;
 624         case 3:
 625                 c->guard_interval = GUARD_INTERVAL_1_4;
 626                 break;
 627         }
 628
 629         switch ((buf[0] >> 4) & 7) {
 630         case 0:
 631                 c->hierarchy = HIERARCHY_NONE;
 632                 break;
 633         case 1:
 634                 c->hierarchy = HIERARCHY_1;
 635                 break;
 636         case 2:
 637                 c->hierarchy = HIERARCHY_2;
 638                 break;
 639         case 3:
 640                 c->hierarchy = HIERARCHY_4;
 641                 break;
 642         }
 643
 644         switch ((buf[1] >> 3) & 7) {
 645         case 0:
 646                 c->code_rate_HP = FEC_1_2;
 647                 break;
 648         case 1:
 649                 c->code_rate_HP = FEC_2_3;
 650                 break;
 651         case 2:
 652                 c->code_rate_HP = FEC_3_4;
 653                 break;
 654         case 3:
 655                 c->code_rate_HP = FEC_5_6;
 656                 break;
 657         case 4:
 658                 c->code_rate_HP = FEC_7_8;
 659                 break;
 660         }
 661
 662         switch ((buf[1] >> 0) & 7) {
 663         case 0:
 664                 c->code_rate_LP = FEC_1_2;
 665                 break;
 666         case 1:
 667                 c->code_rate_LP = FEC_2_3;
 668                 break;
 669         case 2:
 670                 c->code_rate_LP = FEC_3_4;
 671                 break;
 672         case 3:
 673                 c->code_rate_LP = FEC_5_6;
 674                 break;
 675         case 4:
 676                 c->code_rate_LP = FEC_7_8;
 677                 break;
 678         }
 679
 680         return 0;
 681 err:
 682         dev_dbg(&client->dev, "failed=%d\n", ret);
 683         return ret;
 684 }
 685
 686 static int rtl2832_read_status(struct dvb_frontend *fe, enum fe_status *status)
 687 {
 688         struct rtl2832_dev *dev = fe->demodulator_priv;
 689         struct i2c_client *client = dev->client;
 690         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 691         int ret;
 692         u32 uninitialized_var(tmp);
 693         u8 u8tmp, buf[2];
 694         u16 u16tmp;
 695
 696         dev_dbg(&client->dev, "\n");
 697
 698         *status = 0;
 699         if (dev->sleeping)
 700                 return 0;
 701
 702         ret = rtl2832_rd_demod_reg(dev, DVBT_FSM_STAGE, &tmp);
 703         if (ret)
 704                 goto err;
 705
 706         if (tmp == 11) {
 707                 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
 708                                 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
 709         } else if (tmp == 10) {
 710                 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
 711                                 FE_HAS_VITERBI;
 712         }
 713
 714         dev->fe_status = *status;
 715
 716         /* signal strength */
 717         if (dev->fe_status & FE_HAS_SIGNAL) {
 718                 /* read digital AGC */
 719                 ret = rtl2832_bulk_read(client, 0x305, &u8tmp, 1);
 720                 if (ret)
 721                         goto err;
 722
 723                 dev_dbg(&client->dev, "digital agc=%02x", u8tmp);
 724
 725                 u8tmp = ~u8tmp;
 726                 u16tmp = u8tmp << 8 | u8tmp << 0;
 727
 728                 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
 729                 c->strength.stat[0].uvalue = u16tmp;
 730         } else {
 731                 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 732         }
 733
 734         /* CNR */
 735         if (dev->fe_status & FE_HAS_VITERBI) {
 736                 unsigned hierarchy, constellation;
 737                 #define CONSTELLATION_NUM 3
 738                 #define HIERARCHY_NUM 4
 739                 static const u32 constant[CONSTELLATION_NUM][HIERARCHY_NUM] = {
 740                         {85387325, 85387325, 85387325, 85387325},
 741                         {86676178, 86676178, 87167949, 87795660},
 742                         {87659938, 87659938, 87885178, 88241743},
 743                 };
 744
 745                 ret = rtl2832_bulk_read(client, 0x33c, &u8tmp, 1);
 746                 if (ret)
 747                         goto err;
 748
 749                 constellation = (u8tmp >> 2) & 0x03; /* [3:2] */
 750                 if (constellation > CONSTELLATION_NUM - 1)
 751                         goto err;
 752
 753                 hierarchy = (u8tmp >> 4) & 0x07; /* [6:4] */
 754                 if (hierarchy > HIERARCHY_NUM - 1)
 755                         goto err;
 756
 757                 ret = rtl2832_bulk_read(client, 0x40c, buf, 2);
 758                 if (ret)
 759                         goto err;
 760
 761                 u16tmp = buf[0] << 8 | buf[1] << 0;
 762                 if (u16tmp)
 763                         tmp = (constant[constellation][hierarchy] -
 764                                intlog10(u16tmp)) / ((1 << 24) / 10000);
 765                 else
 766                         tmp = 0;
 767
 768                 dev_dbg(&client->dev, "cnr raw=%u\n", u16tmp);
 769
 770                 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
 771                 c->cnr.stat[0].svalue = tmp;
 772         } else {
 773                 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 774         }
 775
 776         /* BER */
 777         if (dev->fe_status & FE_HAS_LOCK) {
 778                 ret = rtl2832_bulk_read(client, 0x34e, buf, 2);
 779                 if (ret)
 780                         goto err;
 781
 782                 u16tmp = buf[0] << 8 | buf[1] << 0;
 783                 dev->post_bit_error += u16tmp;
 784                 dev->post_bit_count += 1000000;
 785
 786                 dev_dbg(&client->dev, "ber errors=%u total=1000000\n", u16tmp);
 787
 788                 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
 789                 c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
 790                 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
 791                 c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
 792         } else {
 793                 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 794                 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 795         }
 796
 797         return 0;
 798 err:
 799         dev_dbg(&client->dev, "failed=%d\n", ret);
 800         return ret;
 801 }
 802
 803 static int rtl2832_read_snr(struct dvb_frontend *fe, u16 *snr)
 804 {
 805         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 806
 807         /* report SNR in resolution of 0.1 dB */
 808         if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
 809                 *snr = div_s64(c->cnr.stat[0].svalue, 100);
 810         else
 811                 *snr = 0;
 812
 813         return 0;
 814 }
 815
 816 static int rtl2832_read_ber(struct dvb_frontend *fe, u32 *ber)
 817 {
 818         struct rtl2832_dev *dev = fe->demodulator_priv;
 819
 820         *ber = (dev->post_bit_error - dev->post_bit_error_prev);
 821         dev->post_bit_error_prev = dev->post_bit_error;
 822
 823         return 0;
 824 }
 825
 826 /*
 827  * I2C gate/mux/repeater logic
 828  * We must use unlocked __i2c_transfer() here (through regmap) because of I2C
 829  * adapter lock is already taken by tuner driver.
 830  * There is delay mechanism to avoid unneeded I2C gate open / close. Gate close
 831  * is delayed here a little bit in order to see if there is sequence of I2C
 832  * messages sent to same I2C bus.
 833  */
 834 static void rtl2832_i2c_gate_work(struct work_struct *work)
 835 {
 836         struct rtl2832_dev *dev = container_of(work, struct rtl2832_dev, i2c_gate_work.work);
 837         struct i2c_client *client = dev->client;
 838         int ret;
 839
 840         /* close gate */
 841         ret = rtl2832_update_bits(dev->client, 0x101, 0x08, 0x00);
 842         if (ret)
 843                 goto err;
 844
 845         return;
 846 err:
 847         dev_dbg(&client->dev, "failed=%d\n", ret);
 848 }
 849
 850 static int rtl2832_select(struct i2c_adapter *adap, void *mux_priv, u32 chan_id)
 851 {
 852         struct rtl2832_dev *dev = mux_priv;
 853         struct i2c_client *client = dev->client;
 854         int ret;
 855
 856         /* terminate possible gate closing */
 857         cancel_delayed_work(&dev->i2c_gate_work);
 858
 859         /*
 860          * I2C adapter lock is already taken and due to that we will use
 861          * regmap_update_bits() which does not lock again I2C adapter.
 862          */
 863         ret = regmap_update_bits(dev->regmap, 0x101, 0x08, 0x08);
 864         if (ret)
 865                 goto err;
 866
 867         return 0;
 868 err:
 869         dev_dbg(&client->dev, "failed=%d\n", ret);
 870         return ret;
 871 }
 872
 873 static int rtl2832_deselect(struct i2c_adapter *adap, void *mux_priv,
 874                             u32 chan_id)
 875 {
 876         struct rtl2832_dev *dev = mux_priv;
 877
 878         schedule_delayed_work(&dev->i2c_gate_work, usecs_to_jiffies(100));
 879         return 0;
 880 }
 881
 882 static struct dvb_frontend_ops rtl2832_ops = {
 883         .delsys = { SYS_DVBT },
 884         .info = {
 885                 .name = "Realtek RTL2832 (DVB-T)",
 886                 .frequency_min    = 174000000,
 887                 .frequency_max    = 862000000,
 888                 .frequency_stepsize = 166667,
 889                 .caps = FE_CAN_FEC_1_2 |
 890                         FE_CAN_FEC_2_3 |
 891                         FE_CAN_FEC_3_4 |
 892                         FE_CAN_FEC_5_6 |
 893                         FE_CAN_FEC_7_8 |
 894                         FE_CAN_FEC_AUTO |
 895                         FE_CAN_QPSK |
 896                         FE_CAN_QAM_16 |
 897                         FE_CAN_QAM_64 |
 898                         FE_CAN_QAM_AUTO |
 899                         FE_CAN_TRANSMISSION_MODE_AUTO |
 900                         FE_CAN_GUARD_INTERVAL_AUTO |
 901                         FE_CAN_HIERARCHY_AUTO |
 902                         FE_CAN_RECOVER |
 903                         FE_CAN_MUTE_TS
 904          },
 905
 906         .init = rtl2832_init,
 907         .sleep = rtl2832_sleep,
 908
 909         .get_tune_settings = rtl2832_get_tune_settings,
 910
 911         .set_frontend = rtl2832_set_frontend,
 912         .get_frontend = rtl2832_get_frontend,
 913
 914         .read_status = rtl2832_read_status,
 915         .read_snr = rtl2832_read_snr,
 916         .read_ber = rtl2832_read_ber,
 917 };
 918
 919 static bool rtl2832_volatile_reg(struct device *dev, unsigned int reg)
 920 {
 921         switch (reg) {
 922         case 0x305:
 923         case 0x33c:
 924         case 0x34e:
 925         case 0x351:
 926         case 0x40c ... 0x40d:
 927                 return true;
 928         default:
 929                 break;
 930         }
 931
 932         return false;
 933 }
 934
 935 /*
 936  * We implement own I2C access routines for regmap in order to get manual access
 937  * to I2C adapter lock, which is needed for I2C mux adapter.
 938  */
 939 static int rtl2832_regmap_read(void *context, const void *reg_buf,
 940                                size_t reg_size, void *val_buf, size_t val_size)
 941 {
 942         struct i2c_client *client = context;
 943         int ret;
 944         struct i2c_msg msg[2] = {
 945                 {
 946                         .addr = client->addr,
 947                         .flags = 0,
 948                         .len = reg_size,
 949                         .buf = (u8 *)reg_buf,
 950                 }, {
 951                         .addr = client->addr,
 952                         .flags = I2C_M_RD,
 953                         .len = val_size,
 954                         .buf = val_buf,
 955                 }
 956         };
 957
 958         ret = __i2c_transfer(client->adapter, msg, 2);
 959         if (ret != 2) {
 960                 dev_warn(&client->dev, "i2c reg read failed %d reg %02x\n",
 961                          ret, *(u8 *)reg_buf);
 962                 if (ret >= 0)
 963                         ret = -EREMOTEIO;
 964                 return ret;
 965         }
 966         return 0;
 967 }
 968
 969 static int rtl2832_regmap_write(void *context, const void *data, size_t count)
 970 {
 971         struct i2c_client *client = context;
 972         int ret;
 973         struct i2c_msg msg[1] = {
 974                 {
 975                         .addr = client->addr,
 976                         .flags = 0,
 977                         .len = count,
 978                         .buf = (u8 *)data,
 979                 }
 980         };
 981
 982         ret = __i2c_transfer(client->adapter, msg, 1);
 983         if (ret != 1) {
 984                 dev_warn(&client->dev, "i2c reg write failed %d reg %02x\n",
 985                          ret, *(u8 *)data);
 986                 if (ret >= 0)
 987                         ret = -EREMOTEIO;
 988                 return ret;
 989         }
 990         return 0;
 991 }
 992
 993 static int rtl2832_regmap_gather_write(void *context, const void *reg,
 994                                        size_t reg_len, const void *val,
 995                                        size_t val_len)
 996 {
 997         struct i2c_client *client = context;
 998         int ret;
 999         u8 buf[256];
1000         struct i2c_msg msg[1] = {
1001                 {
1002                         .addr = client->addr,
1003                         .flags = 0,
1004                         .len = 1 + val_len,
1005                         .buf = buf,
1006                 }
1007         };
1008
1009         buf[0] = *(u8 const *)reg;
1010         memcpy(&buf[1], val, val_len);
1011
1012         ret = __i2c_transfer(client->adapter, msg, 1);
1013         if (ret != 1) {
1014                 dev_warn(&client->dev, "i2c reg write failed %d reg %02x\n",
1015                          ret, *(u8 const *)reg);
1016                 if (ret >= 0)
1017                         ret = -EREMOTEIO;
1018                 return ret;
1019         }
1020         return 0;
1021 }
1022
1023 /*
1024  * FIXME: Hack. Implement own regmap locking in order to silence lockdep
1025  * recursive lock warning. That happens when regmap I2C client calls I2C mux
1026  * adapter, which leads demod I2C repeater enable via demod regmap. Operation
1027  * takes two regmap locks recursively - but those are different regmap instances
1028  * in a two different I2C drivers, so it is not deadlock. Proper fix is to make
1029  * regmap aware of lockdep.
1030  */
1031 static void rtl2832_regmap_lock(void *__dev)
1032 {
1033         struct rtl2832_dev *dev = __dev;
1034         struct i2c_client *client = dev->client;
1035
1036         dev_dbg(&client->dev, "\n");
1037         mutex_lock(&dev->regmap_mutex);
1038 }
1039
1040 static void rtl2832_regmap_unlock(void *__dev)
1041 {
1042         struct rtl2832_dev *dev = __dev;
1043         struct i2c_client *client = dev->client;
1044
1045         dev_dbg(&client->dev, "\n");
1046         mutex_unlock(&dev->regmap_mutex);
1047 }
1048
1049 static struct dvb_frontend *rtl2832_get_dvb_frontend(struct i2c_client *client)
1050 {
1051         struct rtl2832_dev *dev = i2c_get_clientdata(client);
1052
1053         dev_dbg(&client->dev, "\n");
1054         return &dev->fe;
1055 }
1056
1057 static struct i2c_adapter *rtl2832_get_i2c_adapter(struct i2c_client *client)
1058 {
1059         struct rtl2832_dev *dev = i2c_get_clientdata(client);
1060
1061         dev_dbg(&client->dev, "\n");
1062         return dev->i2c_adapter_tuner;
1063 }
1064
1065 static int rtl2832_slave_ts_ctrl(struct i2c_client *client, bool enable)
1066 {
1067         struct rtl2832_dev *dev = i2c_get_clientdata(client);
1068         int ret;
1069
1070         dev_dbg(&client->dev, "enable=%d\n", enable);
1071
1072         if (enable) {
1073                 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x0);
1074                 if (ret)
1075                         goto err;
1076                 ret = rtl2832_bulk_write(client, 0x10c, "\x5f\xff", 2);
1077                 if (ret)
1078                         goto err;
1079                 ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x1);
1080                 if (ret)
1081                         goto err;
1082                 ret = rtl2832_bulk_write(client, 0x0bc, "\x18", 1);
1083                 if (ret)
1084                         goto err;
1085                 ret = rtl2832_bulk_write(client, 0x192, "\x7f\xf7\xff", 3);
1086                 if (ret)
1087                         goto err;
1088         } else {
1089                 ret = rtl2832_bulk_write(client, 0x192, "\x00\x0f\xff", 3);
1090                 if (ret)
1091                         goto err;
1092                 ret = rtl2832_bulk_write(client, 0x0bc, "\x08", 1);
1093                 if (ret)
1094                         goto err;
1095                 ret = rtl2832_wr_demod_reg(dev, DVBT_PIP_ON, 0x0);
1096                 if (ret)
1097                         goto err;
1098                 ret = rtl2832_bulk_write(client, 0x10c, "\x00\x00", 2);
1099                 if (ret)
1100                         goto err;
1101                 ret = rtl2832_wr_demod_reg(dev, DVBT_SOFT_RST, 0x1);
1102                 if (ret)
1103                         goto err;
1104         }
1105
1106         return 0;
1107 err:
1108         dev_dbg(&client->dev, "failed=%d\n", ret);
1109         return ret;
1110 }
1111
1112 static int rtl2832_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
1113 {
1114         struct rtl2832_dev *dev = fe->demodulator_priv;
1115         struct i2c_client *client = dev->client;
1116         int ret;
1117         u8 u8tmp;
1118
1119         dev_dbg(&client->dev, "onoff=%d\n", onoff);
1120
1121         /* enable / disable PID filter */
1122         if (onoff)
1123                 u8tmp = 0x80;
1124         else
1125                 u8tmp = 0x00;
1126
1127         ret = rtl2832_update_bits(client, 0x061, 0xc0, u8tmp);
1128         if (ret)
1129                 goto err;
1130
1131         return 0;
1132 err:
1133         dev_dbg(&client->dev, "failed=%d\n", ret);
1134         return ret;
1135 }
1136
1137 static int rtl2832_pid_filter(struct dvb_frontend *fe, u8 index, u16 pid,
1138                               int onoff)
1139 {
1140         struct rtl2832_dev *dev = fe->demodulator_priv;
1141         struct i2c_client *client = dev->client;
1142         int ret;
1143         u8 buf[4];
1144
1145         dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
1146                 index, pid, onoff);
1147
1148         /* skip invalid PIDs (0x2000) */
1149         if (pid > 0x1fff || index > 32)
1150                 return 0;
1151
1152         if (onoff)
1153                 set_bit(index, &dev->filters);
1154         else
1155                 clear_bit(index, &dev->filters);
1156
1157         /* enable / disable PIDs */
1158         buf[0] = (dev->filters >>  0) & 0xff;
1159         buf[1] = (dev->filters >>  8) & 0xff;
1160         buf[2] = (dev->filters >> 16) & 0xff;
1161         buf[3] = (dev->filters >> 24) & 0xff;
1162         ret = rtl2832_bulk_write(client, 0x062, buf, 4);
1163         if (ret)
1164                 goto err;
1165
1166         /* add PID */
1167         buf[0] = (pid >> 8) & 0xff;
1168         buf[1] = (pid >> 0) & 0xff;
1169         ret = rtl2832_bulk_write(client, 0x066 + 2 * index, buf, 2);
1170         if (ret)
1171                 goto err;
1172
1173         return 0;
1174 err:
1175         dev_dbg(&client->dev, "failed=%d\n", ret);
1176         return ret;
1177 }
1178
1179 static int rtl2832_probe(struct i2c_client *client,
1180                 const struct i2c_device_id *id)
1181 {
1182         struct rtl2832_platform_data *pdata = client->dev.platform_data;
1183         struct i2c_adapter *i2c = client->adapter;
1184         struct rtl2832_dev *dev;
1185         int ret;
1186         u8 tmp;
1187         static const struct regmap_bus regmap_bus = {
1188                 .read = rtl2832_regmap_read,
1189                 .write = rtl2832_regmap_write,
1190                 .gather_write = rtl2832_regmap_gather_write,
1191                 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
1192         };
1193         static const struct regmap_range_cfg regmap_range_cfg[] = {
1194                 {
1195                         .selector_reg     = 0x00,
1196                         .selector_mask    = 0xff,
1197                         .selector_shift   = 0,
1198                         .window_start     = 0,
1199                         .window_len       = 0x100,
1200                         .range_min        = 0 * 0x100,
1201                         .range_max        = 5 * 0x100,
1202                 },
1203         };
1204
1205         dev_dbg(&client->dev, "\n");
1206
1207         /* allocate memory for the internal state */
1208         dev = kzalloc(sizeof(struct rtl2832_dev), GFP_KERNEL);
1209         if (dev == NULL) {
1210                 ret = -ENOMEM;
1211                 goto err;
1212         }
1213
1214         /* setup the state */
1215         i2c_set_clientdata(client, dev);
1216         dev->client = client;
1217         dev->pdata = client->dev.platform_data;
1218         dev->sleeping = true;
1219         INIT_DELAYED_WORK(&dev->i2c_gate_work, rtl2832_i2c_gate_work);
1220         /* create regmap */
1221         mutex_init(&dev->regmap_mutex);
1222         dev->regmap_config.reg_bits =  8,
1223         dev->regmap_config.val_bits =  8,
1224         dev->regmap_config.lock = rtl2832_regmap_lock,
1225         dev->regmap_config.unlock = rtl2832_regmap_unlock,
1226         dev->regmap_config.lock_arg = dev,
1227         dev->regmap_config.volatile_reg = rtl2832_volatile_reg,
1228         dev->regmap_config.max_register = 5 * 0x100,
1229         dev->regmap_config.ranges = regmap_range_cfg,
1230         dev->regmap_config.num_ranges = ARRAY_SIZE(regmap_range_cfg),
1231         dev->regmap_config.cache_type = REGCACHE_NONE,
1232         dev->regmap = regmap_init(&client->dev, &regmap_bus, client,
1233                                   &dev->regmap_config);
1234         if (IS_ERR(dev->regmap)) {
1235                 ret = PTR_ERR(dev->regmap);
1236                 goto err_kfree;
1237         }
1238
1239         /* check if the demod is there */
1240         ret = rtl2832_bulk_read(client, 0x000, &tmp, 1);
1241         if (ret)
1242                 goto err_regmap_exit;
1243
1244         /* create muxed i2c adapter for demod tuner bus */
1245         dev->i2c_adapter_tuner = i2c_add_mux_adapter(i2c, &i2c->dev, dev,
1246                         0, 0, 0, rtl2832_select, rtl2832_deselect);
1247         if (dev->i2c_adapter_tuner == NULL) {
1248                 ret = -ENODEV;
1249                 goto err_regmap_exit;
1250         }
1251
1252         /* create dvb_frontend */
1253         memcpy(&dev->fe.ops, &rtl2832_ops, sizeof(struct dvb_frontend_ops));
1254         dev->fe.demodulator_priv = dev;
1255
1256         /* setup callbacks */
1257         pdata->get_dvb_frontend = rtl2832_get_dvb_frontend;
1258         pdata->get_i2c_adapter = rtl2832_get_i2c_adapter;
1259         pdata->slave_ts_ctrl = rtl2832_slave_ts_ctrl;
1260         pdata->pid_filter = rtl2832_pid_filter;
1261         pdata->pid_filter_ctrl = rtl2832_pid_filter_ctrl;
1262         pdata->bulk_read = rtl2832_bulk_read;
1263         pdata->bulk_write = rtl2832_bulk_write;
1264         pdata->update_bits = rtl2832_update_bits;
1265
1266         dev_info(&client->dev, "Realtek RTL2832 successfully attached\n");
1267         return 0;
1268 err_regmap_exit:
1269         regmap_exit(dev->regmap);
1270 err_kfree:
1271         kfree(dev);
1272 err:
1273         dev_dbg(&client->dev, "failed=%d\n", ret);
1274         return ret;
1275 }
1276
1277 static int rtl2832_remove(struct i2c_client *client)
1278 {
1279         struct rtl2832_dev *dev = i2c_get_clientdata(client);
1280
1281         dev_dbg(&client->dev, "\n");
1282
1283         cancel_delayed_work_sync(&dev->i2c_gate_work);
1284
1285         i2c_del_mux_adapter(dev->i2c_adapter_tuner);
1286
1287         regmap_exit(dev->regmap);
1288
1289         kfree(dev);
1290
1291         return 0;
1292 }
1293
1294 static const struct i2c_device_id rtl2832_id_table[] = {
1295         {"rtl2832", 0},
1296         {}
1297 };
1298 MODULE_DEVICE_TABLE(i2c, rtl2832_id_table);
1299
1300 static struct i2c_driver rtl2832_driver = {
1301         .driver = {
1302                 .name   = "rtl2832",
1303         },
1304         .probe          = rtl2832_probe,
1305         .remove         = rtl2832_remove,
1306         .id_table       = rtl2832_id_table,
1307 };
1308
1309 module_i2c_driver(rtl2832_driver);
1310
1311 MODULE_AUTHOR("Thomas Mair <mair.thomas86@gmail.com>");
1312 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1313 MODULE_DESCRIPTION("Realtek RTL2832 DVB-T demodulator driver");
1314 MODULE_LICENSE("GPL");