drivers/media/dvb-frontends/m88ds3103.c

   1 /*
   2  * Montage M88DS3103/M88RS6000 demodulator driver
   3  *
   4  * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
   5  *
   6  *    This program is free software; you can redistribute it and/or modify
   7  *    it under the terms of the GNU General Public License as published by
   8  *    the Free Software Foundation; either version 2 of the License, or
   9  *    (at your option) any later version.
  10  *
  11  *    This program is distributed in the hope that it will be useful,
  12  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *    GNU General Public License for more details.
  15  */
  16
  17 #include "m88ds3103_priv.h"
  18
  19 static struct dvb_frontend_ops m88ds3103_ops;
  20
  21 /* write multiple registers */
  22 static int m88ds3103_wr_regs(struct m88ds3103_priv *priv,
  23                 u8 reg, const u8 *val, int len)
  24 {
  25 #define MAX_WR_LEN 32
  26 #define MAX_WR_XFER_LEN (MAX_WR_LEN + 1)
  27         int ret;
  28         u8 buf[MAX_WR_XFER_LEN];
  29         struct i2c_msg msg[1] = {
  30                 {
  31                         .addr = priv->cfg->i2c_addr,
  32                         .flags = 0,
  33                         .len = 1 + len,
  34                         .buf = buf,
  35                 }
  36         };
  37
  38         if (WARN_ON(len > MAX_WR_LEN))
  39                 return -EINVAL;
  40
  41         buf[0] = reg;
  42         memcpy(&buf[1], val, len);
  43
  44         mutex_lock(&priv->i2c_mutex);
  45         ret = i2c_transfer(priv->i2c, msg, 1);
  46         mutex_unlock(&priv->i2c_mutex);
  47         if (ret == 1) {
  48                 ret = 0;
  49         } else {
  50                 dev_warn(&priv->i2c->dev,
  51                                 "%s: i2c wr failed=%d reg=%02x len=%d\n",
  52                                 KBUILD_MODNAME, ret, reg, len);
  53                 ret = -EREMOTEIO;
  54         }
  55
  56         return ret;
  57 }
  58
  59 /* read multiple registers */
  60 static int m88ds3103_rd_regs(struct m88ds3103_priv *priv,
  61                 u8 reg, u8 *val, int len)
  62 {
  63 #define MAX_RD_LEN 3
  64 #define MAX_RD_XFER_LEN (MAX_RD_LEN)
  65         int ret;
  66         u8 buf[MAX_RD_XFER_LEN];
  67         struct i2c_msg msg[2] = {
  68                 {
  69                         .addr = priv->cfg->i2c_addr,
  70                         .flags = 0,
  71                         .len = 1,
  72                         .buf = &reg,
  73                 }, {
  74                         .addr = priv->cfg->i2c_addr,
  75                         .flags = I2C_M_RD,
  76                         .len = len,
  77                         .buf = buf,
  78                 }
  79         };
  80
  81         if (WARN_ON(len > MAX_RD_LEN))
  82                 return -EINVAL;
  83
  84         mutex_lock(&priv->i2c_mutex);
  85         ret = i2c_transfer(priv->i2c, msg, 2);
  86         mutex_unlock(&priv->i2c_mutex);
  87         if (ret == 2) {
  88                 memcpy(val, buf, len);
  89                 ret = 0;
  90         } else {
  91                 dev_warn(&priv->i2c->dev,
  92                                 "%s: i2c rd failed=%d reg=%02x len=%d\n",
  93                                 KBUILD_MODNAME, ret, reg, len);
  94                 ret = -EREMOTEIO;
  95         }
  96
  97         return ret;
  98 }
  99
 100 /* write single register */
 101 static int m88ds3103_wr_reg(struct m88ds3103_priv *priv, u8 reg, u8 val)
 102 {
 103         return m88ds3103_wr_regs(priv, reg, &val, 1);
 104 }
 105
 106 /* read single register */
 107 static int m88ds3103_rd_reg(struct m88ds3103_priv *priv, u8 reg, u8 *val)
 108 {
 109         return m88ds3103_rd_regs(priv, reg, val, 1);
 110 }
 111
 112 /* write single register with mask */
 113 static int m88ds3103_wr_reg_mask(struct m88ds3103_priv *priv,
 114                 u8 reg, u8 val, u8 mask)
 115 {
 116         int ret;
 117         u8 u8tmp;
 118
 119         /* no need for read if whole reg is written */
 120         if (mask != 0xff) {
 121                 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
 122                 if (ret)
 123                         return ret;
 124
 125                 val &= mask;
 126                 u8tmp &= ~mask;
 127                 val |= u8tmp;
 128         }
 129
 130         return m88ds3103_wr_regs(priv, reg, &val, 1);
 131 }
 132
 133 /* read single register with mask */
 134 static int m88ds3103_rd_reg_mask(struct m88ds3103_priv *priv,
 135                 u8 reg, u8 *val, u8 mask)
 136 {
 137         int ret, i;
 138         u8 u8tmp;
 139
 140         ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
 141         if (ret)
 142                 return ret;
 143
 144         u8tmp &= mask;
 145
 146         /* find position of the first bit */
 147         for (i = 0; i < 8; i++) {
 148                 if ((mask >> i) & 0x01)
 149                         break;
 150         }
 151         *val = u8tmp >> i;
 152
 153         return 0;
 154 }
 155
 156 /* write reg val table using reg addr auto increment */
 157 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_priv *priv,
 158                 const struct m88ds3103_reg_val *tab, int tab_len)
 159 {
 160         int ret, i, j;
 161         u8 buf[83];
 162
 163         dev_dbg(&priv->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len);
 164
 165         if (tab_len > 86) {
 166                 ret = -EINVAL;
 167                 goto err;
 168         }
 169
 170         for (i = 0, j = 0; i < tab_len; i++, j++) {
 171                 buf[j] = tab[i].val;
 172
 173                 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
 174                                 !((j + 1) % (priv->cfg->i2c_wr_max - 1))) {
 175                         ret = m88ds3103_wr_regs(priv, tab[i].reg - j, buf, j + 1);
 176                         if (ret)
 177                                 goto err;
 178
 179                         j = -1;
 180                 }
 181         }
 182
 183         return 0;
 184 err:
 185         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
 186         return ret;
 187 }
 188
 189 static int m88ds3103_read_status(struct dvb_frontend *fe, fe_status_t *status)
 190 {
 191         struct m88ds3103_priv *priv = fe->demodulator_priv;
 192         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 193         int ret, i, itmp;
 194         u8 u8tmp;
 195         u8 buf[3];
 196
 197         *status = 0;
 198
 199         if (!priv->warm) {
 200                 ret = -EAGAIN;
 201                 goto err;
 202         }
 203
 204         switch (c->delivery_system) {
 205         case SYS_DVBS:
 206                 ret = m88ds3103_rd_reg_mask(priv, 0xd1, &u8tmp, 0x07);
 207                 if (ret)
 208                         goto err;
 209
 210                 if (u8tmp == 0x07)
 211                         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
 212                                         FE_HAS_VITERBI | FE_HAS_SYNC |
 213                                         FE_HAS_LOCK;
 214                 break;
 215         case SYS_DVBS2:
 216                 ret = m88ds3103_rd_reg_mask(priv, 0x0d, &u8tmp, 0x8f);
 217                 if (ret)
 218                         goto err;
 219
 220                 if (u8tmp == 0x8f)
 221                         *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
 222                                         FE_HAS_VITERBI | FE_HAS_SYNC |
 223                                         FE_HAS_LOCK;
 224                 break;
 225         default:
 226                 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
 227                                 __func__);
 228                 ret = -EINVAL;
 229                 goto err;
 230         }
 231
 232         priv->fe_status = *status;
 233
 234         dev_dbg(&priv->i2c->dev, "%s: lock=%02x status=%02x\n",
 235                         __func__, u8tmp, *status);
 236
 237         /* CNR */
 238         if (priv->fe_status & FE_HAS_VITERBI) {
 239                 unsigned int cnr, noise, signal, noise_tot, signal_tot;
 240
 241                 cnr = 0;
 242                 /* more iterations for more accurate estimation */
 243                 #define M88DS3103_SNR_ITERATIONS 3
 244
 245                 switch (c->delivery_system) {
 246                 case SYS_DVBS:
 247                         itmp = 0;
 248
 249                         for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
 250                                 ret = m88ds3103_rd_reg(priv, 0xff, &buf[0]);
 251                                 if (ret)
 252                                         goto err;
 253
 254                                 itmp += buf[0];
 255                         }
 256
 257                         /* use of single register limits max value to 15 dB */
 258                         /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
 259                         itmp = DIV_ROUND_CLOSEST(itmp, 8 * M88DS3103_SNR_ITERATIONS);
 260                         if (itmp)
 261                                 cnr = div_u64((u64) 10000 * intlog2(itmp), intlog2(10));
 262                         break;
 263                 case SYS_DVBS2:
 264                         noise_tot = 0;
 265                         signal_tot = 0;
 266
 267                         for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
 268                                 ret = m88ds3103_rd_regs(priv, 0x8c, buf, 3);
 269                                 if (ret)
 270                                         goto err;
 271
 272                                 noise = buf[1] << 6;    /* [13:6] */
 273                                 noise |= buf[0] & 0x3f; /*  [5:0] */
 274                                 noise >>= 2;
 275                                 signal = buf[2] * buf[2];
 276                                 signal >>= 1;
 277
 278                                 noise_tot += noise;
 279                                 signal_tot += signal;
 280                         }
 281
 282                         noise = noise_tot / M88DS3103_SNR_ITERATIONS;
 283                         signal = signal_tot / M88DS3103_SNR_ITERATIONS;
 284
 285                         /* SNR(X) dB = 10 * log10(X) dB */
 286                         if (signal > noise) {
 287                                 itmp = signal / noise;
 288                                 cnr = div_u64((u64) 10000 * intlog10(itmp), (1 << 24));
 289                         }
 290                         break;
 291                 default:
 292                         dev_dbg(&priv->i2c->dev,
 293                                 "%s: invalid delivery_system\n", __func__);
 294                         ret = -EINVAL;
 295                         goto err;
 296                 }
 297
 298                 if (cnr) {
 299                         c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
 300                         c->cnr.stat[0].svalue = cnr;
 301                 } else {
 302                         c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 303                 }
 304         } else {
 305                 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 306         }
 307
 308         /* BER */
 309         if (priv->fe_status & FE_HAS_LOCK) {
 310                 unsigned int utmp, post_bit_error, post_bit_count;
 311
 312                 switch (c->delivery_system) {
 313                 case SYS_DVBS:
 314                         ret = m88ds3103_wr_reg(priv, 0xf9, 0x04);
 315                         if (ret)
 316                                 goto err;
 317
 318                         ret = m88ds3103_rd_reg(priv, 0xf8, &u8tmp);
 319                         if (ret)
 320                                 goto err;
 321
 322                         /* measurement ready? */
 323                         if (!(u8tmp & 0x10)) {
 324                                 ret = m88ds3103_rd_regs(priv, 0xf6, buf, 2);
 325                                 if (ret)
 326                                         goto err;
 327
 328                                 post_bit_error = buf[1] << 8 | buf[0] << 0;
 329                                 post_bit_count = 0x800000;
 330                                 priv->post_bit_error += post_bit_error;
 331                                 priv->post_bit_count += post_bit_count;
 332                                 priv->dvbv3_ber = post_bit_error;
 333
 334                                 /* restart measurement */
 335                                 u8tmp |= 0x10;
 336                                 ret = m88ds3103_wr_reg(priv, 0xf8, u8tmp);
 337                                 if (ret)
 338                                         goto err;
 339                         }
 340                         break;
 341                 case SYS_DVBS2:
 342                         ret = m88ds3103_rd_regs(priv, 0xd5, buf, 3);
 343                         if (ret)
 344                                 goto err;
 345
 346                         utmp = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
 347
 348                         /* enough data? */
 349                         if (utmp > 4000) {
 350                                 ret = m88ds3103_rd_regs(priv, 0xf7, buf, 2);
 351                                 if (ret)
 352                                         goto err;
 353
 354                                 post_bit_error = buf[1] << 8 | buf[0] << 0;
 355                                 post_bit_count = 32 * utmp; /* TODO: FEC */
 356                                 priv->post_bit_error += post_bit_error;
 357                                 priv->post_bit_count += post_bit_count;
 358                                 priv->dvbv3_ber = post_bit_error;
 359
 360                                 /* restart measurement */
 361                                 ret = m88ds3103_wr_reg(priv, 0xd1, 0x01);
 362                                 if (ret)
 363                                         goto err;
 364
 365                                 ret = m88ds3103_wr_reg(priv, 0xf9, 0x01);
 366                                 if (ret)
 367                                         goto err;
 368
 369                                 ret = m88ds3103_wr_reg(priv, 0xf9, 0x00);
 370                                 if (ret)
 371                                         goto err;
 372
 373                                 ret = m88ds3103_wr_reg(priv, 0xd1, 0x00);
 374                                 if (ret)
 375                                         goto err;
 376                         }
 377                         break;
 378                 default:
 379                         dev_dbg(&priv->i2c->dev,
 380                                 "%s: invalid delivery_system\n", __func__);
 381                         ret = -EINVAL;
 382                         goto err;
 383                 }
 384
 385                 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
 386                 c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
 387                 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
 388                 c->post_bit_count.stat[0].uvalue = priv->post_bit_count;
 389         } else {
 390                 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 391                 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 392         }
 393
 394         return 0;
 395 err:
 396         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
 397         return ret;
 398 }
 399
 400 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
 401 {
 402         struct m88ds3103_priv *priv = fe->demodulator_priv;
 403         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 404         int ret, len;
 405         const struct m88ds3103_reg_val *init;
 406         u8 u8tmp, u8tmp1 = 0, u8tmp2 = 0; /* silence compiler warning */
 407         u8 buf[3];
 408         u16 u16tmp, divide_ratio = 0;
 409         u32 tuner_frequency, target_mclk;
 410         s32 s32tmp;
 411
 412         dev_dbg(&priv->i2c->dev,
 413                         "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
 414                         __func__, c->delivery_system,
 415                         c->modulation, c->frequency, c->symbol_rate,
 416                         c->inversion, c->pilot, c->rolloff);
 417
 418         if (!priv->warm) {
 419                 ret = -EAGAIN;
 420                 goto err;
 421         }
 422
 423         /* reset */
 424         ret = m88ds3103_wr_reg(priv, 0x07, 0x80);
 425         if (ret)
 426                 goto err;
 427
 428         ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
 429         if (ret)
 430                 goto err;
 431
 432         /* Disable demod clock path */
 433         if (priv->chip_id == M88RS6000_CHIP_ID) {
 434                 ret = m88ds3103_wr_reg(priv, 0x06, 0xe0);
 435                 if (ret)
 436                         goto err;
 437         }
 438
 439         /* program tuner */
 440         if (fe->ops.tuner_ops.set_params) {
 441                 ret = fe->ops.tuner_ops.set_params(fe);
 442                 if (ret)
 443                         goto err;
 444         }
 445
 446         if (fe->ops.tuner_ops.get_frequency) {
 447                 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
 448                 if (ret)
 449                         goto err;
 450         } else {
 451                 /*
 452                  * Use nominal target frequency as tuner driver does not provide
 453                  * actual frequency used. Carrier offset calculation is not
 454                  * valid.
 455                  */
 456                 tuner_frequency = c->frequency;
 457         }
 458
 459         /* select M88RS6000 demod main mclk and ts mclk from tuner die. */
 460         if (priv->chip_id == M88RS6000_CHIP_ID) {
 461                 if (c->symbol_rate > 45010000)
 462                         priv->mclk_khz = 110250;
 463                 else
 464                         priv->mclk_khz = 96000;
 465
 466                 if (c->delivery_system == SYS_DVBS)
 467                         target_mclk = 96000;
 468                 else
 469                         target_mclk = 144000;
 470
 471                 /* Enable demod clock path */
 472                 ret = m88ds3103_wr_reg(priv, 0x06, 0x00);
 473                 if (ret)
 474                         goto err;
 475                 usleep_range(10000, 20000);
 476         } else {
 477         /* set M88DS3103 mclk and ts mclk. */
 478                 priv->mclk_khz = 96000;
 479
 480                 switch (priv->cfg->ts_mode) {
 481                 case M88DS3103_TS_SERIAL:
 482                 case M88DS3103_TS_SERIAL_D7:
 483                         target_mclk = priv->cfg->ts_clk;
 484                         break;
 485                 case M88DS3103_TS_PARALLEL:
 486                 case M88DS3103_TS_CI:
 487                         if (c->delivery_system == SYS_DVBS)
 488                                 target_mclk = 96000;
 489                         else {
 490                                 if (c->symbol_rate < 18000000)
 491                                         target_mclk = 96000;
 492                                 else if (c->symbol_rate < 28000000)
 493                                         target_mclk = 144000;
 494                                 else
 495                                         target_mclk = 192000;
 496                         }
 497                         break;
 498                 default:
 499                         dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n",
 500                                         __func__);
 501                         ret = -EINVAL;
 502                         goto err;
 503                 }
 504
 505                 switch (target_mclk) {
 506                 case 96000:
 507                         u8tmp1 = 0x02; /* 0b10 */
 508                         u8tmp2 = 0x01; /* 0b01 */
 509                         break;
 510                 case 144000:
 511                         u8tmp1 = 0x00; /* 0b00 */
 512                         u8tmp2 = 0x01; /* 0b01 */
 513                         break;
 514                 case 192000:
 515                         u8tmp1 = 0x03; /* 0b11 */
 516                         u8tmp2 = 0x00; /* 0b00 */
 517                         break;
 518                 }
 519                 ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0);
 520                 if (ret)
 521                         goto err;
 522                 ret = m88ds3103_wr_reg_mask(priv, 0x24, u8tmp2 << 6, 0xc0);
 523                 if (ret)
 524                         goto err;
 525         }
 526
 527         ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
 528         if (ret)
 529                 goto err;
 530
 531         ret = m88ds3103_wr_reg(priv, 0x00, 0x01);
 532         if (ret)
 533                 goto err;
 534
 535         switch (c->delivery_system) {
 536         case SYS_DVBS:
 537                 if (priv->chip_id == M88RS6000_CHIP_ID) {
 538                         len = ARRAY_SIZE(m88rs6000_dvbs_init_reg_vals);
 539                         init = m88rs6000_dvbs_init_reg_vals;
 540                 } else {
 541                         len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
 542                         init = m88ds3103_dvbs_init_reg_vals;
 543                 }
 544                 break;
 545         case SYS_DVBS2:
 546                 if (priv->chip_id == M88RS6000_CHIP_ID) {
 547                         len = ARRAY_SIZE(m88rs6000_dvbs2_init_reg_vals);
 548                         init = m88rs6000_dvbs2_init_reg_vals;
 549                 } else {
 550                         len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
 551                         init = m88ds3103_dvbs2_init_reg_vals;
 552                 }
 553                 break;
 554         default:
 555                 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
 556                                 __func__);
 557                 ret = -EINVAL;
 558                 goto err;
 559         }
 560
 561         /* program init table */
 562         if (c->delivery_system != priv->delivery_system) {
 563                 ret = m88ds3103_wr_reg_val_tab(priv, init, len);
 564                 if (ret)
 565                         goto err;
 566         }
 567
 568         if (priv->chip_id == M88RS6000_CHIP_ID) {
 569                 if ((c->delivery_system == SYS_DVBS2)
 570                         && ((c->symbol_rate / 1000) <= 5000)) {
 571                         ret = m88ds3103_wr_reg(priv, 0xc0, 0x04);
 572                         if (ret)
 573                                 goto err;
 574                         buf[0] = 0x09;
 575                         buf[1] = 0x22;
 576                         buf[2] = 0x88;
 577                         ret = m88ds3103_wr_regs(priv, 0x8a, buf, 3);
 578                         if (ret)
 579                                 goto err;
 580                 }
 581                 ret = m88ds3103_wr_reg_mask(priv, 0x9d, 0x08, 0x08);
 582                 if (ret)
 583                         goto err;
 584                 ret = m88ds3103_wr_reg(priv, 0xf1, 0x01);
 585                 if (ret)
 586                         goto err;
 587                 ret = m88ds3103_wr_reg_mask(priv, 0x30, 0x80, 0x80);
 588                 if (ret)
 589                         goto err;
 590         }
 591
 592         switch (priv->cfg->ts_mode) {
 593         case M88DS3103_TS_SERIAL:
 594                 u8tmp1 = 0x00;
 595                 u8tmp = 0x06;
 596                 break;
 597         case M88DS3103_TS_SERIAL_D7:
 598                 u8tmp1 = 0x20;
 599                 u8tmp = 0x06;
 600                 break;
 601         case M88DS3103_TS_PARALLEL:
 602                 u8tmp = 0x02;
 603                 break;
 604         case M88DS3103_TS_CI:
 605                 u8tmp = 0x03;
 606                 break;
 607         default:
 608                 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", __func__);
 609                 ret = -EINVAL;
 610                 goto err;
 611         }
 612
 613         if (priv->cfg->ts_clk_pol)
 614                 u8tmp |= 0x40;
 615
 616         /* TS mode */
 617         ret = m88ds3103_wr_reg(priv, 0xfd, u8tmp);
 618         if (ret)
 619                 goto err;
 620
 621         switch (priv->cfg->ts_mode) {
 622         case M88DS3103_TS_SERIAL:
 623         case M88DS3103_TS_SERIAL_D7:
 624                 ret = m88ds3103_wr_reg_mask(priv, 0x29, u8tmp1, 0x20);
 625                 if (ret)
 626                         goto err;
 627                 u8tmp1 = 0;
 628                 u8tmp2 = 0;
 629                 break;
 630         default:
 631                 if (priv->cfg->ts_clk) {
 632                         divide_ratio = DIV_ROUND_UP(target_mclk, priv->cfg->ts_clk);
 633                         u8tmp1 = divide_ratio / 2;
 634                         u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
 635                 }
 636         }
 637
 638         dev_dbg(&priv->i2c->dev,
 639                         "%s: target_mclk=%d ts_clk=%d divide_ratio=%d\n",
 640                         __func__, target_mclk, priv->cfg->ts_clk, divide_ratio);
 641
 642         u8tmp1--;
 643         u8tmp2--;
 644         /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
 645         u8tmp1 &= 0x3f;
 646         /* u8tmp2[5:0] => ea[5:0] */
 647         u8tmp2 &= 0x3f;
 648
 649         ret = m88ds3103_rd_reg(priv, 0xfe, &u8tmp);
 650         if (ret)
 651                 goto err;
 652
 653         u8tmp = ((u8tmp  & 0xf0) << 0) | u8tmp1 >> 2;
 654         ret = m88ds3103_wr_reg(priv, 0xfe, u8tmp);
 655         if (ret)
 656                 goto err;
 657
 658         u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
 659         ret = m88ds3103_wr_reg(priv, 0xea, u8tmp);
 660         if (ret)
 661                 goto err;
 662
 663         if (c->symbol_rate <= 3000000)
 664                 u8tmp = 0x20;
 665         else if (c->symbol_rate <= 10000000)
 666                 u8tmp = 0x10;
 667         else
 668                 u8tmp = 0x06;
 669
 670         ret = m88ds3103_wr_reg(priv, 0xc3, 0x08);
 671         if (ret)
 672                 goto err;
 673
 674         ret = m88ds3103_wr_reg(priv, 0xc8, u8tmp);
 675         if (ret)
 676                 goto err;
 677
 678         ret = m88ds3103_wr_reg(priv, 0xc4, 0x08);
 679         if (ret)
 680                 goto err;
 681
 682         ret = m88ds3103_wr_reg(priv, 0xc7, 0x00);
 683         if (ret)
 684                 goto err;
 685
 686         u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, priv->mclk_khz / 2);
 687         buf[0] = (u16tmp >> 0) & 0xff;
 688         buf[1] = (u16tmp >> 8) & 0xff;
 689         ret = m88ds3103_wr_regs(priv, 0x61, buf, 2);
 690         if (ret)
 691                 goto err;
 692
 693         ret = m88ds3103_wr_reg_mask(priv, 0x4d, priv->cfg->spec_inv << 1, 0x02);
 694         if (ret)
 695                 goto err;
 696
 697         ret = m88ds3103_wr_reg_mask(priv, 0x30, priv->cfg->agc_inv << 4, 0x10);
 698         if (ret)
 699                 goto err;
 700
 701         ret = m88ds3103_wr_reg(priv, 0x33, priv->cfg->agc);
 702         if (ret)
 703                 goto err;
 704
 705         dev_dbg(&priv->i2c->dev, "%s: carrier offset=%d\n", __func__,
 706                         (tuner_frequency - c->frequency));
 707
 708         s32tmp = 0x10000 * (tuner_frequency - c->frequency);
 709         s32tmp = DIV_ROUND_CLOSEST(s32tmp, priv->mclk_khz);
 710         if (s32tmp < 0)
 711                 s32tmp += 0x10000;
 712
 713         buf[0] = (s32tmp >> 0) & 0xff;
 714         buf[1] = (s32tmp >> 8) & 0xff;
 715         ret = m88ds3103_wr_regs(priv, 0x5e, buf, 2);
 716         if (ret)
 717                 goto err;
 718
 719         ret = m88ds3103_wr_reg(priv, 0x00, 0x00);
 720         if (ret)
 721                 goto err;
 722
 723         ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
 724         if (ret)
 725                 goto err;
 726
 727         priv->delivery_system = c->delivery_system;
 728
 729         return 0;
 730 err:
 731         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
 732         return ret;
 733 }
 734
 735 static int m88ds3103_init(struct dvb_frontend *fe)
 736 {
 737         struct m88ds3103_priv *priv = fe->demodulator_priv;
 738         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 739         int ret, len, remaining;
 740         const struct firmware *fw = NULL;
 741         u8 *fw_file;
 742         u8 u8tmp;
 743
 744         dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
 745
 746         /* set cold state by default */
 747         priv->warm = false;
 748
 749         /* wake up device from sleep */
 750         ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x01, 0x01);
 751         if (ret)
 752                 goto err;
 753
 754         ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x00, 0x01);
 755         if (ret)
 756                 goto err;
 757
 758         ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x00, 0x10);
 759         if (ret)
 760                 goto err;
 761
 762         /* firmware status */
 763         ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
 764         if (ret)
 765                 goto err;
 766
 767         dev_dbg(&priv->i2c->dev, "%s: firmware=%02x\n", __func__, u8tmp);
 768
 769         if (u8tmp)
 770                 goto skip_fw_download;
 771
 772         /* global reset, global diseqc reset, golbal fec reset */
 773         ret = m88ds3103_wr_reg(priv, 0x07, 0xe0);
 774         if (ret)
 775                 goto err;
 776
 777         ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
 778         if (ret)
 779                 goto err;
 780
 781         /* cold state - try to download firmware */
 782         dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state\n",
 783                         KBUILD_MODNAME, m88ds3103_ops.info.name);
 784
 785         if (priv->chip_id == M88RS6000_CHIP_ID)
 786                 fw_file = M88RS6000_FIRMWARE;
 787         else
 788                 fw_file = M88DS3103_FIRMWARE;
 789         /* request the firmware, this will block and timeout */
 790         ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent);
 791         if (ret) {
 792                 dev_err(&priv->i2c->dev, "%s: firmware file '%s' not found\n",
 793                                 KBUILD_MODNAME, fw_file);
 794                 goto err;
 795         }
 796
 797         dev_info(&priv->i2c->dev, "%s: downloading firmware from file '%s'\n",
 798                         KBUILD_MODNAME, fw_file);
 799
 800         ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
 801         if (ret)
 802                 goto error_fw_release;
 803
 804         for (remaining = fw->size; remaining > 0;
 805                         remaining -= (priv->cfg->i2c_wr_max - 1)) {
 806                 len = remaining;
 807                 if (len > (priv->cfg->i2c_wr_max - 1))
 808                         len = (priv->cfg->i2c_wr_max - 1);
 809
 810                 ret = m88ds3103_wr_regs(priv, 0xb0,
 811                                 &fw->data[fw->size - remaining], len);
 812                 if (ret) {
 813                         dev_err(&priv->i2c->dev,
 814                                         "%s: firmware download failed=%d\n",
 815                                         KBUILD_MODNAME, ret);
 816                         goto error_fw_release;
 817                 }
 818         }
 819
 820         ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
 821         if (ret)
 822                 goto error_fw_release;
 823
 824         release_firmware(fw);
 825         fw = NULL;
 826
 827         ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
 828         if (ret)
 829                 goto err;
 830
 831         if (!u8tmp) {
 832                 dev_info(&priv->i2c->dev, "%s: firmware did not run\n",
 833                                 KBUILD_MODNAME);
 834                 ret = -EFAULT;
 835                 goto err;
 836         }
 837
 838         dev_info(&priv->i2c->dev, "%s: found a '%s' in warm state\n",
 839                         KBUILD_MODNAME, m88ds3103_ops.info.name);
 840         dev_info(&priv->i2c->dev, "%s: firmware version %X.%X\n",
 841                         KBUILD_MODNAME, (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf));
 842
 843 skip_fw_download:
 844         /* warm state */
 845         priv->warm = true;
 846         /* init stats here in order signal app which stats are supported */
 847         c->cnr.len = 1;
 848         c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 849         c->post_bit_error.len = 1;
 850         c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 851         c->post_bit_count.len = 1;
 852         c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 853         return 0;
 854
 855 error_fw_release:
 856         release_firmware(fw);
 857 err:
 858         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
 859         return ret;
 860 }
 861
 862 static int m88ds3103_sleep(struct dvb_frontend *fe)
 863 {
 864         struct m88ds3103_priv *priv = fe->demodulator_priv;
 865         int ret;
 866         u8 u8tmp;
 867
 868         dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
 869
 870         priv->fe_status = 0;
 871         priv->delivery_system = SYS_UNDEFINED;
 872
 873         /* TS Hi-Z */
 874         if (priv->chip_id == M88RS6000_CHIP_ID)
 875                 u8tmp = 0x29;
 876         else
 877                 u8tmp = 0x27;
 878         ret = m88ds3103_wr_reg_mask(priv, u8tmp, 0x00, 0x01);
 879         if (ret)
 880                 goto err;
 881
 882         /* sleep */
 883         ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
 884         if (ret)
 885                 goto err;
 886
 887         ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
 888         if (ret)
 889                 goto err;
 890
 891         ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
 892         if (ret)
 893                 goto err;
 894
 895         return 0;
 896 err:
 897         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
 898         return ret;
 899 }
 900
 901 static int m88ds3103_get_frontend(struct dvb_frontend *fe)
 902 {
 903         struct m88ds3103_priv *priv = fe->demodulator_priv;
 904         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 905         int ret;
 906         u8 buf[3];
 907
 908         dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
 909
 910         if (!priv->warm || !(priv->fe_status & FE_HAS_LOCK)) {
 911                 ret = 0;
 912                 goto err;
 913         }
 914
 915         switch (c->delivery_system) {
 916         case SYS_DVBS:
 917                 ret = m88ds3103_rd_reg(priv, 0xe0, &buf[0]);
 918                 if (ret)
 919                         goto err;
 920
 921                 ret = m88ds3103_rd_reg(priv, 0xe6, &buf[1]);
 922                 if (ret)
 923                         goto err;
 924
 925                 switch ((buf[0] >> 2) & 0x01) {
 926                 case 0:
 927                         c->inversion = INVERSION_OFF;
 928                         break;
 929                 case 1:
 930                         c->inversion = INVERSION_ON;
 931                         break;
 932                 }
 933
 934                 switch ((buf[1] >> 5) & 0x07) {
 935                 case 0:
 936                         c->fec_inner = FEC_7_8;
 937                         break;
 938                 case 1:
 939                         c->fec_inner = FEC_5_6;
 940                         break;
 941                 case 2:
 942                         c->fec_inner = FEC_3_4;
 943                         break;
 944                 case 3:
 945                         c->fec_inner = FEC_2_3;
 946                         break;
 947                 case 4:
 948                         c->fec_inner = FEC_1_2;
 949                         break;
 950                 default:
 951                         dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
 952                                         __func__);
 953                 }
 954
 955                 c->modulation = QPSK;
 956
 957                 break;
 958         case SYS_DVBS2:
 959                 ret = m88ds3103_rd_reg(priv, 0x7e, &buf[0]);
 960                 if (ret)
 961                         goto err;
 962
 963                 ret = m88ds3103_rd_reg(priv, 0x89, &buf[1]);
 964                 if (ret)
 965                         goto err;
 966
 967                 ret = m88ds3103_rd_reg(priv, 0xf2, &buf[2]);
 968                 if (ret)
 969                         goto err;
 970
 971                 switch ((buf[0] >> 0) & 0x0f) {
 972                 case 2:
 973                         c->fec_inner = FEC_2_5;
 974                         break;
 975                 case 3:
 976                         c->fec_inner = FEC_1_2;
 977                         break;
 978                 case 4:
 979                         c->fec_inner = FEC_3_5;
 980                         break;
 981                 case 5:
 982                         c->fec_inner = FEC_2_3;
 983                         break;
 984                 case 6:
 985                         c->fec_inner = FEC_3_4;
 986                         break;
 987                 case 7:
 988                         c->fec_inner = FEC_4_5;
 989                         break;
 990                 case 8:
 991                         c->fec_inner = FEC_5_6;
 992                         break;
 993                 case 9:
 994                         c->fec_inner = FEC_8_9;
 995                         break;
 996                 case 10:
 997                         c->fec_inner = FEC_9_10;
 998                         break;
 999                 default:
1000                         dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
1001                                         __func__);
1002                 }
1003
1004                 switch ((buf[0] >> 5) & 0x01) {
1005                 case 0:
1006                         c->pilot = PILOT_OFF;
1007                         break;
1008                 case 1:
1009                         c->pilot = PILOT_ON;
1010                         break;
1011                 }
1012
1013                 switch ((buf[0] >> 6) & 0x07) {
1014                 case 0:
1015                         c->modulation = QPSK;
1016                         break;
1017                 case 1:
1018                         c->modulation = PSK_8;
1019                         break;
1020                 case 2:
1021                         c->modulation = APSK_16;
1022                         break;
1023                 case 3:
1024                         c->modulation = APSK_32;
1025                         break;
1026                 default:
1027                         dev_dbg(&priv->i2c->dev, "%s: invalid modulation\n",
1028                                         __func__);
1029                 }
1030
1031                 switch ((buf[1] >> 7) & 0x01) {
1032                 case 0:
1033                         c->inversion = INVERSION_OFF;
1034                         break;
1035                 case 1:
1036                         c->inversion = INVERSION_ON;
1037                         break;
1038                 }
1039
1040                 switch ((buf[2] >> 0) & 0x03) {
1041                 case 0:
1042                         c->rolloff = ROLLOFF_35;
1043                         break;
1044                 case 1:
1045                         c->rolloff = ROLLOFF_25;
1046                         break;
1047                 case 2:
1048                         c->rolloff = ROLLOFF_20;
1049                         break;
1050                 default:
1051                         dev_dbg(&priv->i2c->dev, "%s: invalid rolloff\n",
1052                                         __func__);
1053                 }
1054                 break;
1055         default:
1056                 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
1057                                 __func__);
1058                 ret = -EINVAL;
1059                 goto err;
1060         }
1061
1062         ret = m88ds3103_rd_regs(priv, 0x6d, buf, 2);
1063         if (ret)
1064                 goto err;
1065
1066         c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
1067                         priv->mclk_khz * 1000 / 0x10000;
1068
1069         return 0;
1070 err:
1071         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1072         return ret;
1073 }
1074
1075 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
1076 {
1077         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1078
1079         if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)
1080                 *snr = div_s64(c->cnr.stat[0].svalue, 100);
1081         else
1082                 *snr = 0;
1083
1084         return 0;
1085 }
1086
1087 static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
1088 {
1089         struct m88ds3103_priv *priv = fe->demodulator_priv;
1090
1091         *ber = priv->dvbv3_ber;
1092
1093         return 0;
1094 }
1095
1096 static int m88ds3103_set_tone(struct dvb_frontend *fe,
1097         fe_sec_tone_mode_t fe_sec_tone_mode)
1098 {
1099         struct m88ds3103_priv *priv = fe->demodulator_priv;
1100         int ret;
1101         u8 u8tmp, tone, reg_a1_mask;
1102
1103         dev_dbg(&priv->i2c->dev, "%s: fe_sec_tone_mode=%d\n", __func__,
1104                         fe_sec_tone_mode);
1105
1106         if (!priv->warm) {
1107                 ret = -EAGAIN;
1108                 goto err;
1109         }
1110
1111         switch (fe_sec_tone_mode) {
1112         case SEC_TONE_ON:
1113                 tone = 0;
1114                 reg_a1_mask = 0x47;
1115                 break;
1116         case SEC_TONE_OFF:
1117                 tone = 1;
1118                 reg_a1_mask = 0x00;
1119                 break;
1120         default:
1121                 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_tone_mode\n",
1122                                 __func__);
1123                 ret = -EINVAL;
1124                 goto err;
1125         }
1126
1127         u8tmp = tone << 7 | priv->cfg->envelope_mode << 5;
1128         ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1129         if (ret)
1130                 goto err;
1131
1132         u8tmp = 1 << 2;
1133         ret = m88ds3103_wr_reg_mask(priv, 0xa1, u8tmp, reg_a1_mask);
1134         if (ret)
1135                 goto err;
1136
1137         return 0;
1138 err:
1139         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1140         return ret;
1141 }
1142
1143 static int m88ds3103_set_voltage(struct dvb_frontend *fe,
1144         fe_sec_voltage_t fe_sec_voltage)
1145 {
1146         struct m88ds3103_priv *priv = fe->demodulator_priv;
1147         int ret;
1148         u8 u8tmp;
1149         bool voltage_sel, voltage_dis;
1150
1151         dev_dbg(&priv->i2c->dev, "%s: fe_sec_voltage=%d\n", __func__,
1152                         fe_sec_voltage);
1153
1154         if (!priv->warm) {
1155                 ret = -EAGAIN;
1156                 goto err;
1157         }
1158
1159         switch (fe_sec_voltage) {
1160         case SEC_VOLTAGE_18:
1161                 voltage_sel = true;
1162                 voltage_dis = false;
1163                 break;
1164         case SEC_VOLTAGE_13:
1165                 voltage_sel = false;
1166                 voltage_dis = false;
1167                 break;
1168         case SEC_VOLTAGE_OFF:
1169                 voltage_sel = false;
1170                 voltage_dis = true;
1171                 break;
1172         default:
1173                 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_voltage\n",
1174                                 __func__);
1175                 ret = -EINVAL;
1176                 goto err;
1177         }
1178
1179         /* output pin polarity */
1180         voltage_sel ^= priv->cfg->lnb_hv_pol;
1181         voltage_dis ^= priv->cfg->lnb_en_pol;
1182
1183         u8tmp = voltage_dis << 1 | voltage_sel << 0;
1184         ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0x03);
1185         if (ret)
1186                 goto err;
1187
1188         return 0;
1189 err:
1190         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1191         return ret;
1192 }
1193
1194 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
1195                 struct dvb_diseqc_master_cmd *diseqc_cmd)
1196 {
1197         struct m88ds3103_priv *priv = fe->demodulator_priv;
1198         int ret;
1199         unsigned long timeout;
1200         u8 u8tmp;
1201
1202         dev_dbg(&priv->i2c->dev, "%s: msg=%*ph\n", __func__,
1203                         diseqc_cmd->msg_len, diseqc_cmd->msg);
1204
1205         if (!priv->warm) {
1206                 ret = -EAGAIN;
1207                 goto err;
1208         }
1209
1210         if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1211                 ret = -EINVAL;
1212                 goto err;
1213         }
1214
1215         u8tmp = priv->cfg->envelope_mode << 5;
1216         ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1217         if (ret)
1218                 goto err;
1219
1220         ret = m88ds3103_wr_regs(priv, 0xa3, diseqc_cmd->msg,
1221                         diseqc_cmd->msg_len);
1222         if (ret)
1223                 goto err;
1224
1225         ret = m88ds3103_wr_reg(priv, 0xa1,
1226                         (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1227         if (ret)
1228                 goto err;
1229
1230         /* wait DiSEqC TX ready */
1231         #define SEND_MASTER_CMD_TIMEOUT 120
1232         timeout = jiffies + msecs_to_jiffies(SEND_MASTER_CMD_TIMEOUT);
1233
1234         /* DiSEqC message typical period is 54 ms */
1235         usleep_range(50000, 54000);
1236
1237         for (u8tmp = 1; !time_after(jiffies, timeout) && u8tmp;) {
1238                 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1239                 if (ret)
1240                         goto err;
1241         }
1242
1243         if (u8tmp == 0) {
1244                 dev_dbg(&priv->i2c->dev, "%s: diseqc tx took %u ms\n", __func__,
1245                         jiffies_to_msecs(jiffies) -
1246                         (jiffies_to_msecs(timeout) - SEND_MASTER_CMD_TIMEOUT));
1247         } else {
1248                 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1249
1250                 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0);
1251                 if (ret)
1252                         goto err;
1253         }
1254
1255         ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1256         if (ret)
1257                 goto err;
1258
1259         if (u8tmp == 1) {
1260                 ret = -ETIMEDOUT;
1261                 goto err;
1262         }
1263
1264         return 0;
1265 err:
1266         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1267         return ret;
1268 }
1269
1270 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1271         fe_sec_mini_cmd_t fe_sec_mini_cmd)
1272 {
1273         struct m88ds3103_priv *priv = fe->demodulator_priv;
1274         int ret;
1275         unsigned long timeout;
1276         u8 u8tmp, burst;
1277
1278         dev_dbg(&priv->i2c->dev, "%s: fe_sec_mini_cmd=%d\n", __func__,
1279                         fe_sec_mini_cmd);
1280
1281         if (!priv->warm) {
1282                 ret = -EAGAIN;
1283                 goto err;
1284         }
1285
1286         u8tmp = priv->cfg->envelope_mode << 5;
1287         ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1288         if (ret)
1289                 goto err;
1290
1291         switch (fe_sec_mini_cmd) {
1292         case SEC_MINI_A:
1293                 burst = 0x02;
1294                 break;
1295         case SEC_MINI_B:
1296                 burst = 0x01;
1297                 break;
1298         default:
1299                 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_mini_cmd\n",
1300                                 __func__);
1301                 ret = -EINVAL;
1302                 goto err;
1303         }
1304
1305         ret = m88ds3103_wr_reg(priv, 0xa1, burst);
1306         if (ret)
1307                 goto err;
1308
1309         /* wait DiSEqC TX ready */
1310         #define SEND_BURST_TIMEOUT 40
1311         timeout = jiffies + msecs_to_jiffies(SEND_BURST_TIMEOUT);
1312
1313         /* DiSEqC ToneBurst period is 12.5 ms */
1314         usleep_range(8500, 12500);
1315
1316         for (u8tmp = 1; !time_after(jiffies, timeout) && u8tmp;) {
1317                 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1318                 if (ret)
1319                         goto err;
1320         }
1321
1322         if (u8tmp == 0) {
1323                 dev_dbg(&priv->i2c->dev, "%s: diseqc tx took %u ms\n", __func__,
1324                         jiffies_to_msecs(jiffies) -
1325                         (jiffies_to_msecs(timeout) - SEND_BURST_TIMEOUT));
1326         } else {
1327                 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1328
1329                 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0);
1330                 if (ret)
1331                         goto err;
1332         }
1333
1334         ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1335         if (ret)
1336                 goto err;
1337
1338         if (u8tmp == 1) {
1339                 ret = -ETIMEDOUT;
1340                 goto err;
1341         }
1342
1343         return 0;
1344 err:
1345         dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1346         return ret;
1347 }
1348
1349 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1350         struct dvb_frontend_tune_settings *s)
1351 {
1352         s->min_delay_ms = 3000;
1353
1354         return 0;
1355 }
1356
1357 static void m88ds3103_release(struct dvb_frontend *fe)
1358 {
1359         struct m88ds3103_priv *priv = fe->demodulator_priv;
1360         struct i2c_client *client = priv->client;
1361
1362         i2c_unregister_device(client);
1363 }
1364
1365 static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan)
1366 {
1367         struct m88ds3103_priv *priv = mux_priv;
1368         int ret;
1369         struct i2c_msg gate_open_msg[1] = {
1370                 {
1371                         .addr = priv->cfg->i2c_addr,
1372                         .flags = 0,
1373                         .len = 2,
1374                         .buf = "\x03\x11",
1375                 }
1376         };
1377
1378         mutex_lock(&priv->i2c_mutex);
1379
1380         /* open tuner I2C repeater for 1 xfer, closes automatically */
1381         ret = __i2c_transfer(priv->i2c, gate_open_msg, 1);
1382         if (ret != 1) {
1383                 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d\n",
1384                                 KBUILD_MODNAME, ret);
1385                 if (ret >= 0)
1386                         ret = -EREMOTEIO;
1387
1388                 return ret;
1389         }
1390
1391         return 0;
1392 }
1393
1394 static int m88ds3103_deselect(struct i2c_adapter *adap, void *mux_priv,
1395                 u32 chan)
1396 {
1397         struct m88ds3103_priv *priv = mux_priv;
1398
1399         mutex_unlock(&priv->i2c_mutex);
1400
1401         return 0;
1402 }
1403
1404 /*
1405  * XXX: That is wrapper to m88ds3103_probe() via driver core in order to provide
1406  * proper I2C client for legacy media attach binding.
1407  * New users must use I2C client binding directly!
1408  */
1409 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1410                 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1411 {
1412         struct i2c_client *client;
1413         struct i2c_board_info board_info;
1414         struct m88ds3103_platform_data pdata;
1415
1416         pdata.clk = cfg->clock;
1417         pdata.i2c_wr_max = cfg->i2c_wr_max;
1418         pdata.ts_mode = cfg->ts_mode;
1419         pdata.ts_clk = cfg->ts_clk;
1420         pdata.ts_clk_pol = cfg->ts_clk_pol;
1421         pdata.spec_inv = cfg->spec_inv;
1422         pdata.agc = cfg->agc;
1423         pdata.agc_inv = cfg->agc_inv;
1424         pdata.clk_out = cfg->clock_out;
1425         pdata.envelope_mode = cfg->envelope_mode;
1426         pdata.lnb_hv_pol = cfg->lnb_hv_pol;
1427         pdata.lnb_en_pol = cfg->lnb_en_pol;
1428         pdata.attach_in_use = true;
1429
1430         memset(&board_info, 0, sizeof(board_info));
1431         strlcpy(board_info.type, "m88ds3103", I2C_NAME_SIZE);
1432         board_info.addr = cfg->i2c_addr;
1433         board_info.platform_data = &pdata;
1434         client = i2c_new_device(i2c, &board_info);
1435         if (!client || !client->dev.driver)
1436                 return NULL;
1437
1438         *tuner_i2c_adapter = pdata.get_i2c_adapter(client);
1439         return pdata.get_dvb_frontend(client);
1440 }
1441 EXPORT_SYMBOL(m88ds3103_attach);
1442
1443 static struct dvb_frontend_ops m88ds3103_ops = {
1444         .delsys = { SYS_DVBS, SYS_DVBS2 },
1445         .info = {
1446                 .name = "Montage M88DS3103",
1447                 .frequency_min =  950000,
1448                 .frequency_max = 2150000,
1449                 .frequency_tolerance = 5000,
1450                 .symbol_rate_min =  1000000,
1451                 .symbol_rate_max = 45000000,
1452                 .caps = FE_CAN_INVERSION_AUTO |
1453                         FE_CAN_FEC_1_2 |
1454                         FE_CAN_FEC_2_3 |
1455                         FE_CAN_FEC_3_4 |
1456                         FE_CAN_FEC_4_5 |
1457                         FE_CAN_FEC_5_6 |
1458                         FE_CAN_FEC_6_7 |
1459                         FE_CAN_FEC_7_8 |
1460                         FE_CAN_FEC_8_9 |
1461                         FE_CAN_FEC_AUTO |
1462                         FE_CAN_QPSK |
1463                         FE_CAN_RECOVER |
1464                         FE_CAN_2G_MODULATION
1465         },
1466
1467         .release = m88ds3103_release,
1468
1469         .get_tune_settings = m88ds3103_get_tune_settings,
1470
1471         .init = m88ds3103_init,
1472         .sleep = m88ds3103_sleep,
1473
1474         .set_frontend = m88ds3103_set_frontend,
1475         .get_frontend = m88ds3103_get_frontend,
1476
1477         .read_status = m88ds3103_read_status,
1478         .read_snr = m88ds3103_read_snr,
1479         .read_ber = m88ds3103_read_ber,
1480
1481         .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1482         .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1483
1484         .set_tone = m88ds3103_set_tone,
1485         .set_voltage = m88ds3103_set_voltage,
1486 };
1487
1488 static struct dvb_frontend *m88ds3103_get_dvb_frontend(struct i2c_client *client)
1489 {
1490         struct m88ds3103_priv *dev = i2c_get_clientdata(client);
1491
1492         dev_dbg(&client->dev, "\n");
1493
1494         return &dev->fe;
1495 }
1496
1497 static struct i2c_adapter *m88ds3103_get_i2c_adapter(struct i2c_client *client)
1498 {
1499         struct m88ds3103_priv *dev = i2c_get_clientdata(client);
1500
1501         dev_dbg(&client->dev, "\n");
1502
1503         return dev->i2c_adapter;
1504 }
1505
1506 static int m88ds3103_probe(struct i2c_client *client,
1507                         const struct i2c_device_id *id)
1508 {
1509         struct m88ds3103_priv *dev;
1510         struct m88ds3103_platform_data *pdata = client->dev.platform_data;
1511         int ret;
1512         u8 chip_id, u8tmp;
1513
1514         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1515         if (!dev) {
1516                 ret = -ENOMEM;
1517                 goto err;
1518         }
1519
1520         dev->client = client;
1521         dev->i2c = client->adapter;
1522         dev->config.i2c_addr = client->addr;
1523         dev->config.clock = pdata->clk;
1524         dev->config.i2c_wr_max = pdata->i2c_wr_max;
1525         dev->config.ts_mode = pdata->ts_mode;
1526         dev->config.ts_clk = pdata->ts_clk;
1527         dev->config.ts_clk_pol = pdata->ts_clk_pol;
1528         dev->config.spec_inv = pdata->spec_inv;
1529         dev->config.agc_inv = pdata->agc_inv;
1530         dev->config.clock_out = pdata->clk_out;
1531         dev->config.envelope_mode = pdata->envelope_mode;
1532         dev->config.agc = pdata->agc;
1533         dev->config.lnb_hv_pol = pdata->lnb_hv_pol;
1534         dev->config.lnb_en_pol = pdata->lnb_en_pol;
1535         dev->cfg = &dev->config;
1536         mutex_init(&dev->i2c_mutex);
1537
1538         /* 0x00: chip id[6:0], 0x01: chip ver[7:0], 0x02: chip ver[15:8] */
1539         ret = m88ds3103_rd_reg(dev, 0x00, &chip_id);
1540         if (ret)
1541                 goto err_kfree;
1542
1543         chip_id >>= 1;
1544         dev_dbg(&client->dev, "chip_id=%02x\n", chip_id);
1545
1546         switch (chip_id) {
1547         case M88RS6000_CHIP_ID:
1548         case M88DS3103_CHIP_ID:
1549                 break;
1550         default:
1551                 goto err_kfree;
1552         }
1553         dev->chip_id = chip_id;
1554
1555         switch (dev->cfg->clock_out) {
1556         case M88DS3103_CLOCK_OUT_DISABLED:
1557                 u8tmp = 0x80;
1558                 break;
1559         case M88DS3103_CLOCK_OUT_ENABLED:
1560                 u8tmp = 0x00;
1561                 break;
1562         case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1563                 u8tmp = 0x10;
1564                 break;
1565         default:
1566                 ret = -EINVAL;
1567                 goto err_kfree;
1568         }
1569
1570         /* 0x29 register is defined differently for m88rs6000. */
1571         /* set internal tuner address to 0x21 */
1572         if (chip_id == M88RS6000_CHIP_ID)
1573                 u8tmp = 0x00;
1574
1575         ret = m88ds3103_wr_reg(dev, 0x29, u8tmp);
1576         if (ret)
1577                 goto err_kfree;
1578
1579         /* sleep */
1580         ret = m88ds3103_wr_reg_mask(dev, 0x08, 0x00, 0x01);
1581         if (ret)
1582                 goto err_kfree;
1583         ret = m88ds3103_wr_reg_mask(dev, 0x04, 0x01, 0x01);
1584         if (ret)
1585                 goto err_kfree;
1586         ret = m88ds3103_wr_reg_mask(dev, 0x23, 0x10, 0x10);
1587         if (ret)
1588                 goto err_kfree;
1589
1590         /* create mux i2c adapter for tuner */
1591         dev->i2c_adapter = i2c_add_mux_adapter(client->adapter, &client->dev,
1592                                                dev, 0, 0, 0, m88ds3103_select,
1593                                                m88ds3103_deselect);
1594         if (dev->i2c_adapter == NULL) {
1595                 ret = -ENOMEM;
1596                 goto err_kfree;
1597         }
1598
1599         /* create dvb_frontend */
1600         memcpy(&dev->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1601         if (dev->chip_id == M88RS6000_CHIP_ID)
1602                 strncpy(dev->fe.ops.info.name,
1603                         "Montage M88RS6000", sizeof(dev->fe.ops.info.name));
1604         if (!pdata->attach_in_use)
1605                 dev->fe.ops.release = NULL;
1606         dev->fe.demodulator_priv = dev;
1607         i2c_set_clientdata(client, dev);
1608
1609         /* setup callbacks */
1610         pdata->get_dvb_frontend = m88ds3103_get_dvb_frontend;
1611         pdata->get_i2c_adapter = m88ds3103_get_i2c_adapter;
1612         return 0;
1613 err_kfree:
1614         kfree(dev);
1615 err:
1616         dev_dbg(&client->dev, "failed=%d\n", ret);
1617         return ret;
1618 }
1619
1620 static int m88ds3103_remove(struct i2c_client *client)
1621 {
1622         struct m88ds3103_priv *dev = i2c_get_clientdata(client);
1623
1624         dev_dbg(&client->dev, "\n");
1625
1626         i2c_del_mux_adapter(dev->i2c_adapter);
1627
1628         kfree(dev);
1629         return 0;
1630 }
1631
1632 static const struct i2c_device_id m88ds3103_id_table[] = {
1633         {"m88ds3103", 0},
1634         {}
1635 };
1636 MODULE_DEVICE_TABLE(i2c, m88ds3103_id_table);
1637
1638 static struct i2c_driver m88ds3103_driver = {
1639         .driver = {
1640                 .owner  = THIS_MODULE,
1641                 .name   = "m88ds3103",
1642                 .suppress_bind_attrs = true,
1643         },
1644         .probe          = m88ds3103_probe,
1645         .remove         = m88ds3103_remove,
1646         .id_table       = m88ds3103_id_table,
1647 };
1648
1649 module_i2c_driver(m88ds3103_driver);
1650
1651 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1652 MODULE_DESCRIPTION("Montage M88DS3103 DVB-S/S2 demodulator driver");
1653 MODULE_LICENSE("GPL");
1654 MODULE_FIRMWARE(M88DS3103_FIRMWARE);
1655 MODULE_FIRMWARE(M88RS6000_FIRMWARE);