drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39 #include <linux/string.h>
  40 #include <linux/slab.h>
  41
  42 #include <rdma/ib_verbs.h>
  43 #include <rdma/ib_cache.h>
  44 #include <rdma/ib_pack.h>
  45
  46 #include "mthca_dev.h"
  47 #include "mthca_cmd.h"
  48 #include "mthca_memfree.h"
  49 #include "mthca_wqe.h"
  50
  51 enum {
  52         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  53         MTHCA_ACK_REQ_FREQ       = 10,
  54         MTHCA_FLIGHT_LIMIT       = 9,
  55         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  56         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  57         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  58 };
  59
  60 enum {
  61         MTHCA_QP_STATE_RST  = 0,
  62         MTHCA_QP_STATE_INIT = 1,
  63         MTHCA_QP_STATE_RTR  = 2,
  64         MTHCA_QP_STATE_RTS  = 3,
  65         MTHCA_QP_STATE_SQE  = 4,
  66         MTHCA_QP_STATE_SQD  = 5,
  67         MTHCA_QP_STATE_ERR  = 6,
  68         MTHCA_QP_STATE_DRAINING = 7
  69 };
  70
  71 enum {
  72         MTHCA_QP_ST_RC  = 0x0,
  73         MTHCA_QP_ST_UC  = 0x1,
  74         MTHCA_QP_ST_RD  = 0x2,
  75         MTHCA_QP_ST_UD  = 0x3,
  76         MTHCA_QP_ST_MLX = 0x7
  77 };
  78
  79 enum {
  80         MTHCA_QP_PM_MIGRATED = 0x3,
  81         MTHCA_QP_PM_ARMED    = 0x0,
  82         MTHCA_QP_PM_REARM    = 0x1
  83 };
  84
  85 enum {
  86         /* qp_context flags */
  87         MTHCA_QP_BIT_DE  = 1 <<  8,
  88         /* params1 */
  89         MTHCA_QP_BIT_SRE = 1 << 15,
  90         MTHCA_QP_BIT_SWE = 1 << 14,
  91         MTHCA_QP_BIT_SAE = 1 << 13,
  92         MTHCA_QP_BIT_SIC = 1 <<  4,
  93         MTHCA_QP_BIT_SSC = 1 <<  3,
  94         /* params2 */
  95         MTHCA_QP_BIT_RRE = 1 << 15,
  96         MTHCA_QP_BIT_RWE = 1 << 14,
  97         MTHCA_QP_BIT_RAE = 1 << 13,
  98         MTHCA_QP_BIT_RIC = 1 <<  4,
  99         MTHCA_QP_BIT_RSC = 1 <<  3
 100 };
 101
 102 struct mthca_qp_path {
 103         __be32 port_pkey;
 104         u8     rnr_retry;
 105         u8     g_mylmc;
 106         __be16 rlid;
 107         u8     ackto;
 108         u8     mgid_index;
 109         u8     static_rate;
 110         u8     hop_limit;
 111         __be32 sl_tclass_flowlabel;
 112         u8     rgid[16];
 113 } __attribute__((packed));
 114
 115 struct mthca_qp_context {
 116         __be32 flags;
 117         __be32 tavor_sched_queue; /* Reserved on Arbel */
 118         u8     mtu_msgmax;
 119         u8     rq_size_stride;  /* Reserved on Tavor */
 120         u8     sq_size_stride;  /* Reserved on Tavor */
 121         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 122         __be32 usr_page;
 123         __be32 local_qpn;
 124         __be32 remote_qpn;
 125         u32    reserved1[2];
 126         struct mthca_qp_path pri_path;
 127         struct mthca_qp_path alt_path;
 128         __be32 rdd;
 129         __be32 pd;
 130         __be32 wqe_base;
 131         __be32 wqe_lkey;
 132         __be32 params1;
 133         __be32 reserved2;
 134         __be32 next_send_psn;
 135         __be32 cqn_snd;
 136         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 137         __be32 snd_db_index;    /* (debugging only entries) */
 138         __be32 last_acked_psn;
 139         __be32 ssn;
 140         __be32 params2;
 141         __be32 rnr_nextrecvpsn;
 142         __be32 ra_buff_indx;
 143         __be32 cqn_rcv;
 144         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 145         __be32 rcv_db_index;    /* (debugging only entries) */
 146         __be32 qkey;
 147         __be32 srqn;
 148         __be32 rmsn;
 149         __be16 rq_wqe_counter;  /* reserved on Tavor */
 150         __be16 sq_wqe_counter;  /* reserved on Tavor */
 151         u32    reserved3[18];
 152 } __attribute__((packed));
 153
 154 struct mthca_qp_param {
 155         __be32 opt_param_mask;
 156         u32    reserved1;
 157         struct mthca_qp_context context;
 158         u32    reserved2[62];
 159 } __attribute__((packed));
 160
 161 enum {
 162         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 163         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 164         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 165         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 166         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 167         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 168         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 169         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 170         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 171         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 172         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 173         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 174         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 175         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 176         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 177         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 178         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 179 };
 180
 181 static const u8 mthca_opcode[] = {
 182         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 183         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 184         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 185         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 186         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 187         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 188         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 189 };
 190
 191 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 192 {
 193         return qp->qpn >= dev->qp_table.sqp_start &&
 194                 qp->qpn <= dev->qp_table.sqp_start + 3;
 195 }
 196
 197 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 198 {
 199         return qp->qpn >= dev->qp_table.sqp_start &&
 200                 qp->qpn <= dev->qp_table.sqp_start + 1;
 201 }
 202
 203 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 204 {
 205         if (qp->is_direct)
 206                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 207         else
 208                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 209                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 210 }
 211
 212 static void *get_send_wqe(struct mthca_qp *qp, int n)
 213 {
 214         if (qp->is_direct)
 215                 return qp->queue.direct.buf + qp->send_wqe_offset +
 216                         (n << qp->sq.wqe_shift);
 217         else
 218                 return qp->queue.page_list[(qp->send_wqe_offset +
 219                                             (n << qp->sq.wqe_shift)) >>
 220                                            PAGE_SHIFT].buf +
 221                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 222                          (PAGE_SIZE - 1));
 223 }
 224
 225 static void mthca_wq_init(struct mthca_wq *wq)
 226 {
 227         spin_lock_init(&wq->lock);
 228         wq->next_ind  = 0;
 229         wq->last_comp = wq->max - 1;
 230         wq->head      = 0;
 231         wq->tail      = 0;
 232 }
 233
 234 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 235                     enum ib_event_type event_type)
 236 {
 237         struct mthca_qp *qp;
 238         struct ib_event event;
 239
 240         spin_lock(&dev->qp_table.lock);
 241         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 242         if (qp)
 243                 atomic_inc(&qp->refcount);
 244         spin_unlock(&dev->qp_table.lock);
 245
 246         if (!qp) {
 247                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 248                 return;
 249         }
 250
 251         event.device      = &dev->ib_dev;
 252         event.event       = event_type;
 253         event.element.qp  = &qp->ibqp;
 254         if (qp->ibqp.event_handler)
 255                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 256
 257         if (atomic_dec_and_test(&qp->refcount))
 258                 wake_up(&qp->wait);
 259 }
 260
 261 static int to_mthca_state(enum ib_qp_state ib_state)
 262 {
 263         switch (ib_state) {
 264         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 265         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 266         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 267         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 268         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 269         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 270         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 271         default:                return -1;
 272         }
 273 }
 274
 275 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 276
 277 static int to_mthca_st(int transport)
 278 {
 279         switch (transport) {
 280         case RC:  return MTHCA_QP_ST_RC;
 281         case UC:  return MTHCA_QP_ST_UC;
 282         case UD:  return MTHCA_QP_ST_UD;
 283         case RD:  return MTHCA_QP_ST_RD;
 284         case MLX: return MTHCA_QP_ST_MLX;
 285         default:  return -1;
 286         }
 287 }
 288
 289 static const struct {
 290         int trans;
 291         u32 req_param[NUM_TRANS];
 292         u32 opt_param[NUM_TRANS];
 293 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
 294         [IB_QPS_RESET] = {
 295                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 296                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 297                 [IB_QPS_INIT]  = {
 298                         .trans = MTHCA_TRANS_RST2INIT,
 299                         .req_param = {
 300                                 [UD]  = (IB_QP_PKEY_INDEX |
 301                                          IB_QP_PORT       |
 302                                          IB_QP_QKEY),
 303                                 [UC]  = (IB_QP_PKEY_INDEX |
 304                                          IB_QP_PORT       |
 305                                          IB_QP_ACCESS_FLAGS),
 306                                 [RC]  = (IB_QP_PKEY_INDEX |
 307                                          IB_QP_PORT       |
 308                                          IB_QP_ACCESS_FLAGS),
 309                                 [MLX] = (IB_QP_PKEY_INDEX |
 310                                          IB_QP_QKEY),
 311                         },
 312                         /* bug-for-bug compatibility with VAPI: */
 313                         .opt_param = {
 314                                 [MLX] = IB_QP_PORT
 315                         }
 316                 },
 317         },
 318         [IB_QPS_INIT]  = {
 319                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 320                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 321                 [IB_QPS_INIT]  = {
 322                         .trans = MTHCA_TRANS_INIT2INIT,
 323                         .opt_param = {
 324                                 [UD]  = (IB_QP_PKEY_INDEX |
 325                                          IB_QP_PORT       |
 326                                          IB_QP_QKEY),
 327                                 [UC]  = (IB_QP_PKEY_INDEX |
 328                                          IB_QP_PORT       |
 329                                          IB_QP_ACCESS_FLAGS),
 330                                 [RC]  = (IB_QP_PKEY_INDEX |
 331                                          IB_QP_PORT       |
 332                                          IB_QP_ACCESS_FLAGS),
 333                                 [MLX] = (IB_QP_PKEY_INDEX |
 334                                          IB_QP_QKEY),
 335                         }
 336                 },
 337                 [IB_QPS_RTR]   = {
 338                         .trans = MTHCA_TRANS_INIT2RTR,
 339                         .req_param = {
 340                                 [UC]  = (IB_QP_AV                  |
 341                                          IB_QP_PATH_MTU            |
 342                                          IB_QP_DEST_QPN            |
 343                                          IB_QP_RQ_PSN),
 344                                 [RC]  = (IB_QP_AV                  |
 345                                          IB_QP_PATH_MTU            |
 346                                          IB_QP_DEST_QPN            |
 347                                          IB_QP_RQ_PSN              |
 348                                          IB_QP_MAX_DEST_RD_ATOMIC  |
 349                                          IB_QP_MIN_RNR_TIMER),
 350                         },
 351                         .opt_param = {
 352                                 [UD]  = (IB_QP_PKEY_INDEX |
 353                                          IB_QP_QKEY),
 354                                 [UC]  = (IB_QP_ALT_PATH     |
 355                                          IB_QP_ACCESS_FLAGS |
 356                                          IB_QP_PKEY_INDEX),
 357                                 [RC]  = (IB_QP_ALT_PATH     |
 358                                          IB_QP_ACCESS_FLAGS |
 359                                          IB_QP_PKEY_INDEX),
 360                                 [MLX] = (IB_QP_PKEY_INDEX |
 361                                          IB_QP_QKEY),
 362                         }
 363                 }
 364         },
 365         [IB_QPS_RTR]   = {
 366                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 367                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 368                 [IB_QPS_RTS]   = {
 369                         .trans = MTHCA_TRANS_RTR2RTS,
 370                         .req_param = {
 371                                 [UD]  = IB_QP_SQ_PSN,
 372                                 [UC]  = IB_QP_SQ_PSN,
 373                                 [RC]  = (IB_QP_TIMEOUT           |
 374                                          IB_QP_RETRY_CNT         |
 375                                          IB_QP_RNR_RETRY         |
 376                                          IB_QP_SQ_PSN            |
 377                                          IB_QP_MAX_QP_RD_ATOMIC),
 378                                 [MLX] = IB_QP_SQ_PSN,
 379                         },
 380                         .opt_param = {
 381                                 [UD]  = (IB_QP_CUR_STATE             |
 382                                          IB_QP_QKEY),
 383                                 [UC]  = (IB_QP_CUR_STATE             |
 384                                          IB_QP_ALT_PATH              |
 385                                          IB_QP_ACCESS_FLAGS          |
 386                                          IB_QP_PKEY_INDEX            |
 387                                          IB_QP_PATH_MIG_STATE),
 388                                 [RC]  = (IB_QP_CUR_STATE             |
 389                                          IB_QP_ALT_PATH              |
 390                                          IB_QP_ACCESS_FLAGS          |
 391                                          IB_QP_PKEY_INDEX            |
 392                                          IB_QP_MIN_RNR_TIMER         |
 393                                          IB_QP_PATH_MIG_STATE),
 394                                 [MLX] = (IB_QP_CUR_STATE             |
 395                                          IB_QP_QKEY),
 396                         }
 397                 }
 398         },
 399         [IB_QPS_RTS]   = {
 400                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 401                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 402                 [IB_QPS_RTS]   = {
 403                         .trans = MTHCA_TRANS_RTS2RTS,
 404                         .opt_param = {
 405                                 [UD]  = (IB_QP_CUR_STATE             |
 406                                          IB_QP_QKEY),
 407                                 [UC]  = (IB_QP_ACCESS_FLAGS          |
 408                                          IB_QP_ALT_PATH              |
 409                                          IB_QP_PATH_MIG_STATE),
 410                                 [RC]  = (IB_QP_ACCESS_FLAGS          |
 411                                          IB_QP_ALT_PATH              |
 412                                          IB_QP_PATH_MIG_STATE        |
 413                                          IB_QP_MIN_RNR_TIMER),
 414                                 [MLX] = (IB_QP_CUR_STATE             |
 415                                          IB_QP_QKEY),
 416                         }
 417                 },
 418                 [IB_QPS_SQD]   = {
 419                         .trans = MTHCA_TRANS_RTS2SQD,
 420                 },
 421         },
 422         [IB_QPS_SQD]   = {
 423                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 424                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 425                 [IB_QPS_RTS]   = {
 426                         .trans = MTHCA_TRANS_SQD2RTS,
 427                         .opt_param = {
 428                                 [UD]  = (IB_QP_CUR_STATE             |
 429                                          IB_QP_QKEY),
 430                                 [UC]  = (IB_QP_CUR_STATE             |
 431                                          IB_QP_ALT_PATH              |
 432                                          IB_QP_ACCESS_FLAGS          |
 433                                          IB_QP_PATH_MIG_STATE),
 434                                 [RC]  = (IB_QP_CUR_STATE             |
 435                                          IB_QP_ALT_PATH              |
 436                                          IB_QP_ACCESS_FLAGS          |
 437                                          IB_QP_MIN_RNR_TIMER         |
 438                                          IB_QP_PATH_MIG_STATE),
 439                                 [MLX] = (IB_QP_CUR_STATE             |
 440                                          IB_QP_QKEY),
 441                         }
 442                 },
 443                 [IB_QPS_SQD]   = {
 444                         .trans = MTHCA_TRANS_SQD2SQD,
 445                         .opt_param = {
 446                                 [UD]  = (IB_QP_PKEY_INDEX            |
 447                                          IB_QP_QKEY),
 448                                 [UC]  = (IB_QP_AV                    |
 449                                          IB_QP_CUR_STATE             |
 450                                          IB_QP_ALT_PATH              |
 451                                          IB_QP_ACCESS_FLAGS          |
 452                                          IB_QP_PKEY_INDEX            |
 453                                          IB_QP_PATH_MIG_STATE),
 454                                 [RC]  = (IB_QP_AV                    |
 455                                          IB_QP_TIMEOUT               |
 456                                          IB_QP_RETRY_CNT             |
 457                                          IB_QP_RNR_RETRY             |
 458                                          IB_QP_MAX_QP_RD_ATOMIC      |
 459                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 460                                          IB_QP_CUR_STATE             |
 461                                          IB_QP_ALT_PATH              |
 462                                          IB_QP_ACCESS_FLAGS          |
 463                                          IB_QP_PKEY_INDEX            |
 464                                          IB_QP_MIN_RNR_TIMER         |
 465                                          IB_QP_PATH_MIG_STATE),
 466                                 [MLX] = (IB_QP_PKEY_INDEX            |
 467                                          IB_QP_QKEY),
 468                         }
 469                 }
 470         },
 471         [IB_QPS_SQE]   = {
 472                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 473                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 474                 [IB_QPS_RTS]   = {
 475                         .trans = MTHCA_TRANS_SQERR2RTS,
 476                         .opt_param = {
 477                                 [UD]  = (IB_QP_CUR_STATE             |
 478                                          IB_QP_QKEY),
 479                                 [UC]  = IB_QP_CUR_STATE,
 480                                 [RC]  = (IB_QP_CUR_STATE             |
 481                                          IB_QP_MIN_RNR_TIMER),
 482                                 [MLX] = (IB_QP_CUR_STATE             |
 483                                          IB_QP_QKEY),
 484                         }
 485                 }
 486         },
 487         [IB_QPS_ERR] = {
 488                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 489                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
 490         }
 491 };
 492
 493 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 494                         int attr_mask)
 495 {
 496         if (attr_mask & IB_QP_PKEY_INDEX)
 497                 sqp->pkey_index = attr->pkey_index;
 498         if (attr_mask & IB_QP_QKEY)
 499                 sqp->qkey = attr->qkey;
 500         if (attr_mask & IB_QP_SQ_PSN)
 501                 sqp->send_psn = attr->sq_psn;
 502 }
 503
 504 static void init_port(struct mthca_dev *dev, int port)
 505 {
 506         int err;
 507         u8 status;
 508         struct mthca_init_ib_param param;
 509
 510         memset(&param, 0, sizeof param);
 511
 512         param.port_width = dev->limits.port_width_cap;
 513         param.vl_cap     = dev->limits.vl_cap;
 514         param.mtu_cap    = dev->limits.mtu_cap;
 515         param.gid_cap    = dev->limits.gid_table_len;
 516         param.pkey_cap   = dev->limits.pkey_table_len;
 517
 518         err = mthca_INIT_IB(dev, &param, port, &status);
 519         if (err)
 520                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 521         if (status)
 522                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 523 }
 524
 525 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 526 {
 527         struct mthca_dev *dev = to_mdev(ibqp->device);
 528         struct mthca_qp *qp = to_mqp(ibqp);
 529         enum ib_qp_state cur_state, new_state;
 530         struct mthca_mailbox *mailbox;
 531         struct mthca_qp_param *qp_param;
 532         struct mthca_qp_context *qp_context;
 533         u32 req_param, opt_param;
 534         u8 status;
 535         int err;
 536
 537         if (attr_mask & IB_QP_CUR_STATE) {
 538                 if (attr->cur_qp_state != IB_QPS_RTR &&
 539                     attr->cur_qp_state != IB_QPS_RTS &&
 540                     attr->cur_qp_state != IB_QPS_SQD &&
 541                     attr->cur_qp_state != IB_QPS_SQE)
 542                         return -EINVAL;
 543                 else
 544                         cur_state = attr->cur_qp_state;
 545         } else {
 546                 spin_lock_irq(&qp->sq.lock);
 547                 spin_lock(&qp->rq.lock);
 548                 cur_state = qp->state;
 549                 spin_unlock(&qp->rq.lock);
 550                 spin_unlock_irq(&qp->sq.lock);
 551         }
 552
 553         if (attr_mask & IB_QP_STATE) {
 554                if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
 555                         return -EINVAL;
 556                 new_state = attr->qp_state;
 557         } else
 558                 new_state = cur_state;
 559
 560         if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
 561                 mthca_dbg(dev, "Illegal QP transition "
 562                           "%d->%d\n", cur_state, new_state);
 563                 return -EINVAL;
 564         }
 565
 566         req_param = state_table[cur_state][new_state].req_param[qp->transport];
 567         opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
 568
 569         if ((req_param & attr_mask) != req_param) {
 570                 mthca_dbg(dev, "QP transition "
 571                           "%d->%d missing req attr 0x%08x\n",
 572                           cur_state, new_state,
 573                           req_param & ~attr_mask);
 574                 return -EINVAL;
 575         }
 576
 577         if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
 578                 mthca_dbg(dev, "QP transition (transport %d) "
 579                           "%d->%d has extra attr 0x%08x\n",
 580                           qp->transport,
 581                           cur_state, new_state,
 582                           attr_mask & ~(req_param | opt_param |
 583                                                  IB_QP_STATE));
 584                 return -EINVAL;
 585         }
 586
 587         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 588              attr->pkey_index >= dev->limits.pkey_table_len) {
 589                 mthca_dbg(dev, "PKey index (%u) too large. max is %d\n",
 590                           attr->pkey_index,dev->limits.pkey_table_len-1);
 591                 return -EINVAL;
 592         }
 593
 594         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 595         if (IS_ERR(mailbox))
 596                 return PTR_ERR(mailbox);
 597         qp_param = mailbox->buf;
 598         qp_context = &qp_param->context;
 599         memset(qp_param, 0, sizeof *qp_param);
 600
 601         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 602                                              (to_mthca_st(qp->transport) << 16));
 603         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 604         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 605                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 606         else {
 607                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 608                 switch (attr->path_mig_state) {
 609                 case IB_MIG_MIGRATED:
 610                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 611                         break;
 612                 case IB_MIG_REARM:
 613                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 614                         break;
 615                 case IB_MIG_ARMED:
 616                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 617                         break;
 618                 }
 619         }
 620
 621         /* leave tavor_sched_queue as 0 */
 622
 623         if (qp->transport == MLX || qp->transport == UD)
 624                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 625         else if (attr_mask & IB_QP_PATH_MTU)
 626                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 627
 628         if (mthca_is_memfree(dev)) {
 629                 if (qp->rq.max)
 630                         qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
 631                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 632
 633                 if (qp->sq.max)
 634                         qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
 635                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 636         }
 637
 638         /* leave arbel_sched_queue as 0 */
 639
 640         if (qp->ibqp.uobject)
 641                 qp_context->usr_page =
 642                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 643         else
 644                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 645         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 646         if (attr_mask & IB_QP_DEST_QPN) {
 647                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 648         }
 649
 650         if (qp->transport == MLX)
 651                 qp_context->pri_path.port_pkey |=
 652                         cpu_to_be32(to_msqp(qp)->port << 24);
 653         else {
 654                 if (attr_mask & IB_QP_PORT) {
 655                         qp_context->pri_path.port_pkey |=
 656                                 cpu_to_be32(attr->port_num << 24);
 657                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 658                 }
 659         }
 660
 661         if (attr_mask & IB_QP_PKEY_INDEX) {
 662                 qp_context->pri_path.port_pkey |=
 663                         cpu_to_be32(attr->pkey_index);
 664                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 665         }
 666
 667         if (attr_mask & IB_QP_RNR_RETRY) {
 668                 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
 669                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
 670         }
 671
 672         if (attr_mask & IB_QP_AV) {
 673                 qp_context->pri_path.g_mylmc     = attr->ah_attr.src_path_bits & 0x7f;
 674                 qp_context->pri_path.rlid        = cpu_to_be16(attr->ah_attr.dlid);
 675                 qp_context->pri_path.static_rate = !!attr->ah_attr.static_rate;
 676                 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
 677                         qp_context->pri_path.g_mylmc |= 1 << 7;
 678                         qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
 679                         qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
 680                         qp_context->pri_path.sl_tclass_flowlabel =
 681                                 cpu_to_be32((attr->ah_attr.sl << 28)                |
 682                                             (attr->ah_attr.grh.traffic_class << 20) |
 683                                             (attr->ah_attr.grh.flow_label));
 684                         memcpy(qp_context->pri_path.rgid,
 685                                attr->ah_attr.grh.dgid.raw, 16);
 686                 } else {
 687                         qp_context->pri_path.sl_tclass_flowlabel =
 688                                 cpu_to_be32(attr->ah_attr.sl << 28);
 689                 }
 690                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 691         }
 692
 693         if (attr_mask & IB_QP_TIMEOUT) {
 694                 qp_context->pri_path.ackto = attr->timeout << 3;
 695                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 696         }
 697
 698         /* XXX alt_path */
 699
 700         /* leave rdd as 0 */
 701         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 702         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 703         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 704         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 705                                              (MTHCA_FLIGHT_LIMIT << 24) |
 706                                              MTHCA_QP_BIT_SRE           |
 707                                              MTHCA_QP_BIT_SWE           |
 708                                              MTHCA_QP_BIT_SAE);
 709         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 710                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 711         if (attr_mask & IB_QP_RETRY_CNT) {
 712                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 713                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 714         }
 715
 716         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 717                 qp_context->params1 |= cpu_to_be32(min(attr->max_rd_atomic ?
 718                                                        ffs(attr->max_rd_atomic) - 1 : 0,
 719                                                        7) << 21);
 720                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 721         }
 722
 723         if (attr_mask & IB_QP_SQ_PSN)
 724                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 725         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 726
 727         if (mthca_is_memfree(dev)) {
 728                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 729                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 730         }
 731
 732         if (attr_mask & IB_QP_ACCESS_FLAGS) {
 733                 qp_context->params2 |=
 734                         cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE ?
 735                                     MTHCA_QP_BIT_RWE : 0);
 736
 737                 /*
 738                  * Only enable RDMA reads and atomics if we have
 739                  * responder resources set to a non-zero value.
 740                  */
 741                 if (qp->resp_depth) {
 742                         qp_context->params2 |=
 743                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_READ ?
 744                                             MTHCA_QP_BIT_RRE : 0);
 745                         qp_context->params2 |=
 746                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC ?
 747                                             MTHCA_QP_BIT_RAE : 0);
 748                 }
 749
 750                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 751                                                         MTHCA_QP_OPTPAR_RRE |
 752                                                         MTHCA_QP_OPTPAR_RAE);
 753
 754                 qp->atomic_rd_en = attr->qp_access_flags;
 755         }
 756
 757         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 758                 u8 rra_max;
 759
 760                 if (qp->resp_depth && !attr->max_dest_rd_atomic) {
 761                         /*
 762                          * Lowering our responder resources to zero.
 763                          * Turn off reads RDMA and atomics as responder.
 764                          * (RRE/RAE in params2 already zero)
 765                          */
 766                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRE |
 767                                                                 MTHCA_QP_OPTPAR_RAE);
 768                 }
 769
 770                 if (!qp->resp_depth && attr->max_dest_rd_atomic) {
 771                         /*
 772                          * Increasing our responder resources from
 773                          * zero.  Turn on RDMA reads and atomics as
 774                          * appropriate.
 775                          */
 776                         qp_context->params2 |=
 777                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_READ ?
 778                                             MTHCA_QP_BIT_RRE : 0);
 779                         qp_context->params2 |=
 780                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_ATOMIC ?
 781                                             MTHCA_QP_BIT_RAE : 0);
 782
 783                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRE |
 784                                                                 MTHCA_QP_OPTPAR_RAE);
 785                 }
 786
 787                 for (rra_max = 0;
 788                      1 << rra_max < attr->max_dest_rd_atomic &&
 789                              rra_max < dev->qp_table.rdb_shift;
 790                      ++rra_max)
 791                         ; /* nothing */
 792
 793                 qp_context->params2      |= cpu_to_be32(rra_max << 21);
 794                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 795
 796                 qp->resp_depth = attr->max_dest_rd_atomic;
 797         }
 798
 799         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 800
 801         if (ibqp->srq)
 802                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 803
 804         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 805                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 806                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 807         }
 808         if (attr_mask & IB_QP_RQ_PSN)
 809                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 810
 811         qp_context->ra_buff_indx =
 812                 cpu_to_be32(dev->qp_table.rdb_base +
 813                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 814                              dev->qp_table.rdb_shift));
 815
 816         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 817
 818         if (mthca_is_memfree(dev))
 819                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 820
 821         if (attr_mask & IB_QP_QKEY) {
 822                 qp_context->qkey = cpu_to_be32(attr->qkey);
 823                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 824         }
 825
 826         if (ibqp->srq)
 827                 qp_context->srqn = cpu_to_be32(1 << 24 |
 828                                                to_msrq(ibqp->srq)->srqn);
 829
 830         err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
 831                               qp->qpn, 0, mailbox, 0, &status);
 832         if (status) {
 833                 mthca_warn(dev, "modify QP %d returned status %02x.\n",
 834                            state_table[cur_state][new_state].trans, status);
 835                 err = -EINVAL;
 836         }
 837
 838         if (!err)
 839                 qp->state = new_state;
 840
 841         mthca_free_mailbox(dev, mailbox);
 842
 843         if (is_sqp(dev, qp))
 844                 store_attrs(to_msqp(qp), attr, attr_mask);
 845
 846         /*
 847          * If we moved QP0 to RTR, bring the IB link up; if we moved
 848          * QP0 to RESET or ERROR, bring the link back down.
 849          */
 850         if (is_qp0(dev, qp)) {
 851                 if (cur_state != IB_QPS_RTR &&
 852                     new_state == IB_QPS_RTR)
 853                         init_port(dev, to_msqp(qp)->port);
 854
 855                 if (cur_state != IB_QPS_RESET &&
 856                     cur_state != IB_QPS_ERR &&
 857                     (new_state == IB_QPS_RESET ||
 858                      new_state == IB_QPS_ERR))
 859                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 860         }
 861
 862         /*
 863          * If we moved a kernel QP to RESET, clean up all old CQ
 864          * entries and reinitialize the QP.
 865          */
 866         if (!err && new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 867                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
 868                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 869                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 870                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
 871                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 872
 873                 mthca_wq_init(&qp->sq);
 874                 mthca_wq_init(&qp->rq);
 875
 876                 if (mthca_is_memfree(dev)) {
 877                         *qp->sq.db = 0;
 878                         *qp->rq.db = 0;
 879                 }
 880         }
 881
 882         return err;
 883 }
 884
 885 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 886                                  struct mthca_pd *pd,
 887                                  struct mthca_qp *qp)
 888 {
 889         int max_data_size;
 890
 891         /*
 892          * Calculate the maximum size of WQE s/g segments, excluding
 893          * the next segment and other non-data segments.
 894          */
 895         max_data_size = min(dev->limits.max_desc_sz, 1 << qp->sq.wqe_shift) -
 896                 sizeof (struct mthca_next_seg);
 897
 898         switch (qp->transport) {
 899         case MLX:
 900                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 901                 break;
 902
 903         case UD:
 904                 if (mthca_is_memfree(dev))
 905                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 906                 else
 907                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 908                 break;
 909
 910         default:
 911                 max_data_size -= sizeof (struct mthca_raddr_seg);
 912                 break;
 913         }
 914
 915         /* We don't support inline data for kernel QPs (yet). */
 916         if (!pd->ibpd.uobject)
 917                 qp->max_inline_data = 0;
 918         else
 919                 qp->max_inline_data = max_data_size - MTHCA_INLINE_HEADER_SIZE;
 920
 921         qp->sq.max_gs = max_data_size / sizeof (struct mthca_data_seg);
 922         qp->rq.max_gs = (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 923                         sizeof (struct mthca_next_seg)) /
 924                         sizeof (struct mthca_data_seg);
 925 }
 926
 927 /*
 928  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 929  * rq.max_gs and sq.max_gs must all be assigned.
 930  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 931  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 932  * queue)
 933  */
 934 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 935                                struct mthca_pd *pd,
 936                                struct mthca_qp *qp)
 937 {
 938         int size;
 939         int err = -ENOMEM;
 940
 941         size = sizeof (struct mthca_next_seg) +
 942                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 943
 944         if (size > dev->limits.max_desc_sz)
 945                 return -EINVAL;
 946
 947         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 948              qp->rq.wqe_shift++)
 949                 ; /* nothing */
 950
 951         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 952         switch (qp->transport) {
 953         case MLX:
 954                 size += 2 * sizeof (struct mthca_data_seg);
 955                 break;
 956
 957         case UD:
 958                 size += mthca_is_memfree(dev) ?
 959                         sizeof (struct mthca_arbel_ud_seg) :
 960                         sizeof (struct mthca_tavor_ud_seg);
 961                 break;
 962
 963         case UC:
 964                 size += sizeof (struct mthca_raddr_seg);
 965                 break;
 966
 967         case RC:
 968                 size += sizeof (struct mthca_raddr_seg);
 969                 /*
 970                  * An atomic op will require an atomic segment, a
 971                  * remote address segment and one scatter entry.
 972                  */
 973                 size = max_t(int, size,
 974                              sizeof (struct mthca_atomic_seg) +
 975                              sizeof (struct mthca_raddr_seg) +
 976                              sizeof (struct mthca_data_seg));
 977                 break;
 978
 979         default:
 980                 break;
 981         }
 982
 983         /* Make sure that we have enough space for a bind request */
 984         size = max_t(int, size, sizeof (struct mthca_bind_seg));
 985
 986         size += sizeof (struct mthca_next_seg);
 987
 988         if (size > dev->limits.max_desc_sz)
 989                 return -EINVAL;
 990
 991         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 992              qp->sq.wqe_shift++)
 993                 ; /* nothing */
 994
 995         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 996                                     1 << qp->sq.wqe_shift);
 997
 998         /*
 999          * If this is a userspace QP, we don't actually have to
1000          * allocate anything.  All we need is to calculate the WQE
1001          * sizes and the send_wqe_offset, so we're done now.
1002          */
1003         if (pd->ibpd.uobject)
1004                 return 0;
1005
1006         size = PAGE_ALIGN(qp->send_wqe_offset +
1007                           (qp->sq.max << qp->sq.wqe_shift));
1008
1009         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1010                            GFP_KERNEL);
1011         if (!qp->wrid)
1012                 goto err_out;
1013
1014         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1015                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1016         if (err)
1017                 goto err_out;
1018
1019         return 0;
1020
1021 err_out:
1022         kfree(qp->wrid);
1023         return err;
1024 }
1025
1026 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1027                                struct mthca_qp *qp)
1028 {
1029         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1030                                        (qp->sq.max << qp->sq.wqe_shift)),
1031                        &qp->queue, qp->is_direct, &qp->mr);
1032         kfree(qp->wrid);
1033 }
1034
1035 static int mthca_map_memfree(struct mthca_dev *dev,
1036                              struct mthca_qp *qp)
1037 {
1038         int ret;
1039
1040         if (mthca_is_memfree(dev)) {
1041                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1042                 if (ret)
1043                         return ret;
1044
1045                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1046                 if (ret)
1047                         goto err_qpc;
1048
1049                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1050                                       qp->qpn << dev->qp_table.rdb_shift);
1051                 if (ret)
1052                         goto err_eqpc;
1053
1054         }
1055
1056         return 0;
1057
1058 err_eqpc:
1059         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1060
1061 err_qpc:
1062         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1063
1064         return ret;
1065 }
1066
1067 static void mthca_unmap_memfree(struct mthca_dev *dev,
1068                                 struct mthca_qp *qp)
1069 {
1070         mthca_table_put(dev, dev->qp_table.rdb_table,
1071                         qp->qpn << dev->qp_table.rdb_shift);
1072         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1073         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1074 }
1075
1076 static int mthca_alloc_memfree(struct mthca_dev *dev,
1077                                struct mthca_qp *qp)
1078 {
1079         int ret = 0;
1080
1081         if (mthca_is_memfree(dev)) {
1082                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1083                                                  qp->qpn, &qp->rq.db);
1084                 if (qp->rq.db_index < 0)
1085                         return ret;
1086
1087                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1088                                                  qp->qpn, &qp->sq.db);
1089                 if (qp->sq.db_index < 0)
1090                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1091         }
1092
1093         return ret;
1094 }
1095
1096 static void mthca_free_memfree(struct mthca_dev *dev,
1097                                struct mthca_qp *qp)
1098 {
1099         if (mthca_is_memfree(dev)) {
1100                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1101                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1102         }
1103 }
1104
1105 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1106                                  struct mthca_pd *pd,
1107                                  struct mthca_cq *send_cq,
1108                                  struct mthca_cq *recv_cq,
1109                                  enum ib_sig_type send_policy,
1110                                  struct mthca_qp *qp)
1111 {
1112         int ret;
1113         int i;
1114
1115         atomic_set(&qp->refcount, 1);
1116         init_waitqueue_head(&qp->wait);
1117         qp->state        = IB_QPS_RESET;
1118         qp->atomic_rd_en = 0;
1119         qp->resp_depth   = 0;
1120         qp->sq_policy    = send_policy;
1121         mthca_wq_init(&qp->sq);
1122         mthca_wq_init(&qp->rq);
1123
1124         ret = mthca_map_memfree(dev, qp);
1125         if (ret)
1126                 return ret;
1127
1128         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1129         if (ret) {
1130                 mthca_unmap_memfree(dev, qp);
1131                 return ret;
1132         }
1133
1134         mthca_adjust_qp_caps(dev, pd, qp);
1135
1136         /*
1137          * If this is a userspace QP, we're done now.  The doorbells
1138          * will be allocated and buffers will be initialized in
1139          * userspace.
1140          */
1141         if (pd->ibpd.uobject)
1142                 return 0;
1143
1144         ret = mthca_alloc_memfree(dev, qp);
1145         if (ret) {
1146                 mthca_free_wqe_buf(dev, qp);
1147                 mthca_unmap_memfree(dev, qp);
1148                 return ret;
1149         }
1150
1151         if (mthca_is_memfree(dev)) {
1152                 struct mthca_next_seg *next;
1153                 struct mthca_data_seg *scatter;
1154                 int size = (sizeof (struct mthca_next_seg) +
1155                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1156
1157                 for (i = 0; i < qp->rq.max; ++i) {
1158                         next = get_recv_wqe(qp, i);
1159                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1160                                                    qp->rq.wqe_shift);
1161                         next->ee_nds = cpu_to_be32(size);
1162
1163                         for (scatter = (void *) (next + 1);
1164                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1165                              ++scatter)
1166                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1167                 }
1168
1169                 for (i = 0; i < qp->sq.max; ++i) {
1170                         next = get_send_wqe(qp, i);
1171                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1172                                                     qp->sq.wqe_shift) +
1173                                                    qp->send_wqe_offset);
1174                 }
1175         }
1176
1177         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1178         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1179
1180         return 0;
1181 }
1182
1183 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1184                              struct mthca_qp *qp)
1185 {
1186         /* Sanity check QP size before proceeding */
1187         if (cap->max_send_wr  > dev->limits.max_wqes ||
1188             cap->max_recv_wr  > dev->limits.max_wqes ||
1189             cap->max_send_sge > dev->limits.max_sg   ||
1190             cap->max_recv_sge > dev->limits.max_sg)
1191                 return -EINVAL;
1192
1193         if (mthca_is_memfree(dev)) {
1194                 qp->rq.max = cap->max_recv_wr ?
1195                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1196                 qp->sq.max = cap->max_send_wr ?
1197                         roundup_pow_of_two(cap->max_send_wr) : 0;
1198         } else {
1199                 qp->rq.max = cap->max_recv_wr;
1200                 qp->sq.max = cap->max_send_wr;
1201         }
1202
1203         qp->rq.max_gs = cap->max_recv_sge;
1204         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1205                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1206                                     MTHCA_INLINE_CHUNK_SIZE) /
1207                               sizeof (struct mthca_data_seg));
1208
1209         /*
1210          * For MLX transport we need 2 extra S/G entries:
1211          * one for the header and one for the checksum at the end
1212          */
1213         if ((qp->transport == MLX && qp->sq.max_gs + 2 > dev->limits.max_sg) ||
1214             qp->sq.max_gs > dev->limits.max_sg || qp->rq.max_gs > dev->limits.max_sg)
1215                 return -EINVAL;
1216
1217         return 0;
1218 }
1219
1220 int mthca_alloc_qp(struct mthca_dev *dev,
1221                    struct mthca_pd *pd,
1222                    struct mthca_cq *send_cq,
1223                    struct mthca_cq *recv_cq,
1224                    enum ib_qp_type type,
1225                    enum ib_sig_type send_policy,
1226                    struct ib_qp_cap *cap,
1227                    struct mthca_qp *qp)
1228 {
1229         int err;
1230
1231         err = mthca_set_qp_size(dev, cap, qp);
1232         if (err)
1233                 return err;
1234
1235         switch (type) {
1236         case IB_QPT_RC: qp->transport = RC; break;
1237         case IB_QPT_UC: qp->transport = UC; break;
1238         case IB_QPT_UD: qp->transport = UD; break;
1239         default: return -EINVAL;
1240         }
1241
1242         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1243         if (qp->qpn == -1)
1244                 return -ENOMEM;
1245
1246         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1247                                     send_policy, qp);
1248         if (err) {
1249                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1250                 return err;
1251         }
1252
1253         spin_lock_irq(&dev->qp_table.lock);
1254         mthca_array_set(&dev->qp_table.qp,
1255                         qp->qpn & (dev->limits.num_qps - 1), qp);
1256         spin_unlock_irq(&dev->qp_table.lock);
1257
1258         return 0;
1259 }
1260
1261 int mthca_alloc_sqp(struct mthca_dev *dev,
1262                     struct mthca_pd *pd,
1263                     struct mthca_cq *send_cq,
1264                     struct mthca_cq *recv_cq,
1265                     enum ib_sig_type send_policy,
1266                     struct ib_qp_cap *cap,
1267                     int qpn,
1268                     int port,
1269                     struct mthca_sqp *sqp)
1270 {
1271         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1272         int err;
1273
1274         err = mthca_set_qp_size(dev, cap, &sqp->qp);
1275         if (err)
1276                 return err;
1277
1278         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1279         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1280                                              &sqp->header_dma, GFP_KERNEL);
1281         if (!sqp->header_buf)
1282                 return -ENOMEM;
1283
1284         spin_lock_irq(&dev->qp_table.lock);
1285         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1286                 err = -EBUSY;
1287         else
1288                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1289         spin_unlock_irq(&dev->qp_table.lock);
1290
1291         if (err)
1292                 goto err_out;
1293
1294         sqp->port = port;
1295         sqp->qp.qpn       = mqpn;
1296         sqp->qp.transport = MLX;
1297
1298         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1299                                     send_policy, &sqp->qp);
1300         if (err)
1301                 goto err_out_free;
1302
1303         atomic_inc(&pd->sqp_count);
1304
1305         return 0;
1306
1307  err_out_free:
1308         /*
1309          * Lock CQs here, so that CQ polling code can do QP lookup
1310          * without taking a lock.
1311          */
1312         spin_lock_irq(&send_cq->lock);
1313         if (send_cq != recv_cq)
1314                 spin_lock(&recv_cq->lock);
1315
1316         spin_lock(&dev->qp_table.lock);
1317         mthca_array_clear(&dev->qp_table.qp, mqpn);
1318         spin_unlock(&dev->qp_table.lock);
1319
1320         if (send_cq != recv_cq)
1321                 spin_unlock(&recv_cq->lock);
1322         spin_unlock_irq(&send_cq->lock);
1323
1324  err_out:
1325         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1326                           sqp->header_buf, sqp->header_dma);
1327
1328         return err;
1329 }
1330
1331 void mthca_free_qp(struct mthca_dev *dev,
1332                    struct mthca_qp *qp)
1333 {
1334         u8 status;
1335         struct mthca_cq *send_cq;
1336         struct mthca_cq *recv_cq;
1337
1338         send_cq = to_mcq(qp->ibqp.send_cq);
1339         recv_cq = to_mcq(qp->ibqp.recv_cq);
1340
1341         /*
1342          * Lock CQs here, so that CQ polling code can do QP lookup
1343          * without taking a lock.
1344          */
1345         spin_lock_irq(&send_cq->lock);
1346         if (send_cq != recv_cq)
1347                 spin_lock(&recv_cq->lock);
1348
1349         spin_lock(&dev->qp_table.lock);
1350         mthca_array_clear(&dev->qp_table.qp,
1351                           qp->qpn & (dev->limits.num_qps - 1));
1352         spin_unlock(&dev->qp_table.lock);
1353
1354         if (send_cq != recv_cq)
1355                 spin_unlock(&recv_cq->lock);
1356         spin_unlock_irq(&send_cq->lock);
1357
1358         atomic_dec(&qp->refcount);
1359         wait_event(qp->wait, !atomic_read(&qp->refcount));
1360
1361         if (qp->state != IB_QPS_RESET)
1362                 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1363
1364         /*
1365          * If this is a userspace QP, the buffers, MR, CQs and so on
1366          * will be cleaned up in userspace, so all we have to do is
1367          * unref the mem-free tables and free the QPN in our table.
1368          */
1369         if (!qp->ibqp.uobject) {
1370                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
1371                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1372                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1373                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
1374                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1375
1376                 mthca_free_memfree(dev, qp);
1377                 mthca_free_wqe_buf(dev, qp);
1378         }
1379
1380         mthca_unmap_memfree(dev, qp);
1381
1382         if (is_sqp(dev, qp)) {
1383                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1384                 dma_free_coherent(&dev->pdev->dev,
1385                                   to_msqp(qp)->header_buf_size,
1386                                   to_msqp(qp)->header_buf,
1387                                   to_msqp(qp)->header_dma);
1388         } else
1389                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1390 }
1391
1392 /* Create UD header for an MLX send and build a data segment for it */
1393 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1394                             int ind, struct ib_send_wr *wr,
1395                             struct mthca_mlx_seg *mlx,
1396                             struct mthca_data_seg *data)
1397 {
1398         int header_size;
1399         int err;
1400         u16 pkey;
1401
1402         ib_ud_header_init(256, /* assume a MAD */
1403                           sqp->ud_header.grh_present,
1404                           &sqp->ud_header);
1405
1406         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1407         if (err)
1408                 return err;
1409         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1410         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1411                                   (sqp->ud_header.lrh.destination_lid ==
1412                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1413                                   (sqp->ud_header.lrh.service_level << 8));
1414         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1415         mlx->vcrc = 0;
1416
1417         switch (wr->opcode) {
1418         case IB_WR_SEND:
1419                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1420                 sqp->ud_header.immediate_present = 0;
1421                 break;
1422         case IB_WR_SEND_WITH_IMM:
1423                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1424                 sqp->ud_header.immediate_present = 1;
1425                 sqp->ud_header.immediate_data = wr->imm_data;
1426                 break;
1427         default:
1428                 return -EINVAL;
1429         }
1430
1431         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1432         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1433                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1434         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1435         if (!sqp->qp.ibqp.qp_num)
1436                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1437                                    sqp->pkey_index, &pkey);
1438         else
1439                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1440                                    wr->wr.ud.pkey_index, &pkey);
1441         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1442         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1443         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1444         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1445                                                sqp->qkey : wr->wr.ud.remote_qkey);
1446         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1447
1448         header_size = ib_ud_header_pack(&sqp->ud_header,
1449                                         sqp->header_buf +
1450                                         ind * MTHCA_UD_HEADER_SIZE);
1451
1452         data->byte_count = cpu_to_be32(header_size);
1453         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1454         data->addr       = cpu_to_be64(sqp->header_dma +
1455                                        ind * MTHCA_UD_HEADER_SIZE);
1456
1457         return 0;
1458 }
1459
1460 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1461                                     struct ib_cq *ib_cq)
1462 {
1463         unsigned cur;
1464         struct mthca_cq *cq;
1465
1466         cur = wq->head - wq->tail;
1467         if (likely(cur + nreq < wq->max))
1468                 return 0;
1469
1470         cq = to_mcq(ib_cq);
1471         spin_lock(&cq->lock);
1472         cur = wq->head - wq->tail;
1473         spin_unlock(&cq->lock);
1474
1475         return cur + nreq >= wq->max;
1476 }
1477
1478 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1479                           struct ib_send_wr **bad_wr)
1480 {
1481         struct mthca_dev *dev = to_mdev(ibqp->device);
1482         struct mthca_qp *qp = to_mqp(ibqp);
1483         void *wqe;
1484         void *prev_wqe;
1485         unsigned long flags;
1486         int err = 0;
1487         int nreq;
1488         int i;
1489         int size;
1490         int size0 = 0;
1491         u32 f0 = 0;
1492         int ind;
1493         u8 op0 = 0;
1494
1495         spin_lock_irqsave(&qp->sq.lock, flags);
1496
1497         /* XXX check that state is OK to post send */
1498
1499         ind = qp->sq.next_ind;
1500
1501         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1502                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1503                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1504                                         " %d max, %d nreq)\n", qp->qpn,
1505                                         qp->sq.head, qp->sq.tail,
1506                                         qp->sq.max, nreq);
1507                         err = -ENOMEM;
1508                         *bad_wr = wr;
1509                         goto out;
1510                 }
1511
1512                 wqe = get_send_wqe(qp, ind);
1513                 prev_wqe = qp->sq.last;
1514                 qp->sq.last = wqe;
1515
1516                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1517                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1518                 ((struct mthca_next_seg *) wqe)->flags =
1519                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1520                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1521                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1522                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1523                         cpu_to_be32(1);
1524                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1525                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1526                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1527
1528                 wqe += sizeof (struct mthca_next_seg);
1529                 size = sizeof (struct mthca_next_seg) / 16;
1530
1531                 switch (qp->transport) {
1532                 case RC:
1533                         switch (wr->opcode) {
1534                         case IB_WR_ATOMIC_CMP_AND_SWP:
1535                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1536                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1537                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1538                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1539                                         cpu_to_be32(wr->wr.atomic.rkey);
1540                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1541
1542                                 wqe += sizeof (struct mthca_raddr_seg);
1543
1544                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1545                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1546                                                 cpu_to_be64(wr->wr.atomic.swap);
1547                                         ((struct mthca_atomic_seg *) wqe)->compare =
1548                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1549                                 } else {
1550                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1551                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1552                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1553                                 }
1554
1555                                 wqe += sizeof (struct mthca_atomic_seg);
1556                                 size += (sizeof (struct mthca_raddr_seg) +
1557                                          sizeof (struct mthca_atomic_seg)) / 16;
1558                                 break;
1559
1560                         case IB_WR_RDMA_WRITE:
1561                         case IB_WR_RDMA_WRITE_WITH_IMM:
1562                         case IB_WR_RDMA_READ:
1563                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1564                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1565                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1566                                         cpu_to_be32(wr->wr.rdma.rkey);
1567                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1568                                 wqe += sizeof (struct mthca_raddr_seg);
1569                                 size += sizeof (struct mthca_raddr_seg) / 16;
1570                                 break;
1571
1572                         default:
1573                                 /* No extra segments required for sends */
1574                                 break;
1575                         }
1576
1577                         break;
1578
1579                 case UC:
1580                         switch (wr->opcode) {
1581                         case IB_WR_RDMA_WRITE:
1582                         case IB_WR_RDMA_WRITE_WITH_IMM:
1583                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1584                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1585                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1586                                         cpu_to_be32(wr->wr.rdma.rkey);
1587                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1588                                 wqe += sizeof (struct mthca_raddr_seg);
1589                                 size += sizeof (struct mthca_raddr_seg) / 16;
1590                                 break;
1591
1592                         default:
1593                                 /* No extra segments required for sends */
1594                                 break;
1595                         }
1596
1597                         break;
1598
1599                 case UD:
1600                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1601                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1602                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1603                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1604                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1605                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1606                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1607                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1608
1609                         wqe += sizeof (struct mthca_tavor_ud_seg);
1610                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1611                         break;
1612
1613                 case MLX:
1614                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1615                                                wqe - sizeof (struct mthca_next_seg),
1616                                                wqe);
1617                         if (err) {
1618                                 *bad_wr = wr;
1619                                 goto out;
1620                         }
1621                         wqe += sizeof (struct mthca_data_seg);
1622                         size += sizeof (struct mthca_data_seg) / 16;
1623                         break;
1624                 }
1625
1626                 if (wr->num_sge > qp->sq.max_gs) {
1627                         mthca_err(dev, "too many gathers\n");
1628                         err = -EINVAL;
1629                         *bad_wr = wr;
1630                         goto out;
1631                 }
1632
1633                 for (i = 0; i < wr->num_sge; ++i) {
1634                         ((struct mthca_data_seg *) wqe)->byte_count =
1635                                 cpu_to_be32(wr->sg_list[i].length);
1636                         ((struct mthca_data_seg *) wqe)->lkey =
1637                                 cpu_to_be32(wr->sg_list[i].lkey);
1638                         ((struct mthca_data_seg *) wqe)->addr =
1639                                 cpu_to_be64(wr->sg_list[i].addr);
1640                         wqe += sizeof (struct mthca_data_seg);
1641                         size += sizeof (struct mthca_data_seg) / 16;
1642                 }
1643
1644                 /* Add one more inline data segment for ICRC */
1645                 if (qp->transport == MLX) {
1646                         ((struct mthca_data_seg *) wqe)->byte_count =
1647                                 cpu_to_be32((1 << 31) | 4);
1648                         ((u32 *) wqe)[1] = 0;
1649                         wqe += sizeof (struct mthca_data_seg);
1650                         size += sizeof (struct mthca_data_seg) / 16;
1651                 }
1652
1653                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1654
1655                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1656                         mthca_err(dev, "opcode invalid\n");
1657                         err = -EINVAL;
1658                         *bad_wr = wr;
1659                         goto out;
1660                 }
1661
1662                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1663                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1664                                      qp->send_wqe_offset) |
1665                                     mthca_opcode[wr->opcode]);
1666                 wmb();
1667                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1668                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1669
1670                 if (!size0) {
1671                         size0 = size;
1672                         op0   = mthca_opcode[wr->opcode];
1673                 }
1674
1675                 ++ind;
1676                 if (unlikely(ind >= qp->sq.max))
1677                         ind -= qp->sq.max;
1678         }
1679
1680 out:
1681         if (likely(nreq)) {
1682                 __be32 doorbell[2];
1683
1684                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1685                                            qp->send_wqe_offset) | f0 | op0);
1686                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1687
1688                 wmb();
1689
1690                 mthca_write64(doorbell,
1691                               dev->kar + MTHCA_SEND_DOORBELL,
1692                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1693         }
1694
1695         qp->sq.next_ind = ind;
1696         qp->sq.head    += nreq;
1697
1698         spin_unlock_irqrestore(&qp->sq.lock, flags);
1699         return err;
1700 }
1701
1702 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1703                              struct ib_recv_wr **bad_wr)
1704 {
1705         struct mthca_dev *dev = to_mdev(ibqp->device);
1706         struct mthca_qp *qp = to_mqp(ibqp);
1707         __be32 doorbell[2];
1708         unsigned long flags;
1709         int err = 0;
1710         int nreq;
1711         int i;
1712         int size;
1713         int size0 = 0;
1714         int ind;
1715         void *wqe;
1716         void *prev_wqe;
1717
1718         spin_lock_irqsave(&qp->rq.lock, flags);
1719
1720         /* XXX check that state is OK to post receive */
1721
1722         ind = qp->rq.next_ind;
1723
1724         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1725                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1726                         nreq = 0;
1727
1728                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1729                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1730
1731                         wmb();
1732
1733                         mthca_write64(doorbell,
1734                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1735                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1736
1737                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1738                         size0 = 0;
1739                 }
1740
1741                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1742                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1743                                         " %d max, %d nreq)\n", qp->qpn,
1744                                         qp->rq.head, qp->rq.tail,
1745                                         qp->rq.max, nreq);
1746                         err = -ENOMEM;
1747                         *bad_wr = wr;
1748                         goto out;
1749                 }
1750
1751                 wqe = get_recv_wqe(qp, ind);
1752                 prev_wqe = qp->rq.last;
1753                 qp->rq.last = wqe;
1754
1755                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1756                 ((struct mthca_next_seg *) wqe)->ee_nds =
1757                         cpu_to_be32(MTHCA_NEXT_DBD);
1758                 ((struct mthca_next_seg *) wqe)->flags = 0;
1759
1760                 wqe += sizeof (struct mthca_next_seg);
1761                 size = sizeof (struct mthca_next_seg) / 16;
1762
1763                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1764                         err = -EINVAL;
1765                         *bad_wr = wr;
1766                         goto out;
1767                 }
1768
1769                 for (i = 0; i < wr->num_sge; ++i) {
1770                         ((struct mthca_data_seg *) wqe)->byte_count =
1771                                 cpu_to_be32(wr->sg_list[i].length);
1772                         ((struct mthca_data_seg *) wqe)->lkey =
1773                                 cpu_to_be32(wr->sg_list[i].lkey);
1774                         ((struct mthca_data_seg *) wqe)->addr =
1775                                 cpu_to_be64(wr->sg_list[i].addr);
1776                         wqe += sizeof (struct mthca_data_seg);
1777                         size += sizeof (struct mthca_data_seg) / 16;
1778                 }
1779
1780                 qp->wrid[ind] = wr->wr_id;
1781
1782                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1783                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1784                 wmb();
1785                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1786                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1787
1788                 if (!size0)
1789                         size0 = size;
1790
1791                 ++ind;
1792                 if (unlikely(ind >= qp->rq.max))
1793                         ind -= qp->rq.max;
1794         }
1795
1796 out:
1797         if (likely(nreq)) {
1798                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1799                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1800
1801                 wmb();
1802
1803                 mthca_write64(doorbell,
1804                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1805                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1806         }
1807
1808         qp->rq.next_ind = ind;
1809         qp->rq.head    += nreq;
1810
1811         spin_unlock_irqrestore(&qp->rq.lock, flags);
1812         return err;
1813 }
1814
1815 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1816                           struct ib_send_wr **bad_wr)
1817 {
1818         struct mthca_dev *dev = to_mdev(ibqp->device);
1819         struct mthca_qp *qp = to_mqp(ibqp);
1820         void *wqe;
1821         void *prev_wqe;
1822         unsigned long flags;
1823         int err = 0;
1824         int nreq;
1825         int i;
1826         int size;
1827         int size0 = 0;
1828         u32 f0 = 0;
1829         int ind;
1830         u8 op0 = 0;
1831
1832         spin_lock_irqsave(&qp->sq.lock, flags);
1833
1834         /* XXX check that state is OK to post send */
1835
1836         ind = qp->sq.head & (qp->sq.max - 1);
1837
1838         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1839                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1840                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1841                                         " %d max, %d nreq)\n", qp->qpn,
1842                                         qp->sq.head, qp->sq.tail,
1843                                         qp->sq.max, nreq);
1844                         err = -ENOMEM;
1845                         *bad_wr = wr;
1846                         goto out;
1847                 }
1848
1849                 wqe = get_send_wqe(qp, ind);
1850                 prev_wqe = qp->sq.last;
1851                 qp->sq.last = wqe;
1852
1853                 ((struct mthca_next_seg *) wqe)->flags =
1854                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1855                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1856                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1857                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1858                         cpu_to_be32(1);
1859                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1860                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1861                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1862
1863                 wqe += sizeof (struct mthca_next_seg);
1864                 size = sizeof (struct mthca_next_seg) / 16;
1865
1866                 switch (qp->transport) {
1867                 case RC:
1868                         switch (wr->opcode) {
1869                         case IB_WR_ATOMIC_CMP_AND_SWP:
1870                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1871                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1872                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1873                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1874                                         cpu_to_be32(wr->wr.atomic.rkey);
1875                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1876
1877                                 wqe += sizeof (struct mthca_raddr_seg);
1878
1879                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1880                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1881                                                 cpu_to_be64(wr->wr.atomic.swap);
1882                                         ((struct mthca_atomic_seg *) wqe)->compare =
1883                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1884                                 } else {
1885                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1886                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1887                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1888                                 }
1889
1890                                 wqe += sizeof (struct mthca_atomic_seg);
1891                                 size += (sizeof (struct mthca_raddr_seg) +
1892                                          sizeof (struct mthca_atomic_seg)) / 16;
1893                                 break;
1894
1895                         case IB_WR_RDMA_READ:
1896                         case IB_WR_RDMA_WRITE:
1897                         case IB_WR_RDMA_WRITE_WITH_IMM:
1898                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1899                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1900                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1901                                         cpu_to_be32(wr->wr.rdma.rkey);
1902                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1903                                 wqe += sizeof (struct mthca_raddr_seg);
1904                                 size += sizeof (struct mthca_raddr_seg) / 16;
1905                                 break;
1906
1907                         default:
1908                                 /* No extra segments required for sends */
1909                                 break;
1910                         }
1911
1912                         break;
1913
1914                 case UC:
1915                         switch (wr->opcode) {
1916                         case IB_WR_RDMA_WRITE:
1917                         case IB_WR_RDMA_WRITE_WITH_IMM:
1918                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1919                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1920                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1921                                         cpu_to_be32(wr->wr.rdma.rkey);
1922                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1923                                 wqe += sizeof (struct mthca_raddr_seg);
1924                                 size += sizeof (struct mthca_raddr_seg) / 16;
1925                                 break;
1926
1927                         default:
1928                                 /* No extra segments required for sends */
1929                                 break;
1930                         }
1931
1932                         break;
1933
1934                 case UD:
1935                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1936                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1937                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1938                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1939                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1940                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1941
1942                         wqe += sizeof (struct mthca_arbel_ud_seg);
1943                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1944                         break;
1945
1946                 case MLX:
1947                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1948                                                wqe - sizeof (struct mthca_next_seg),
1949                                                wqe);
1950                         if (err) {
1951                                 *bad_wr = wr;
1952                                 goto out;
1953                         }
1954                         wqe += sizeof (struct mthca_data_seg);
1955                         size += sizeof (struct mthca_data_seg) / 16;
1956                         break;
1957                 }
1958
1959                 if (wr->num_sge > qp->sq.max_gs) {
1960                         mthca_err(dev, "too many gathers\n");
1961                         err = -EINVAL;
1962                         *bad_wr = wr;
1963                         goto out;
1964                 }
1965
1966                 for (i = 0; i < wr->num_sge; ++i) {
1967                         ((struct mthca_data_seg *) wqe)->byte_count =
1968                                 cpu_to_be32(wr->sg_list[i].length);
1969                         ((struct mthca_data_seg *) wqe)->lkey =
1970                                 cpu_to_be32(wr->sg_list[i].lkey);
1971                         ((struct mthca_data_seg *) wqe)->addr =
1972                                 cpu_to_be64(wr->sg_list[i].addr);
1973                         wqe += sizeof (struct mthca_data_seg);
1974                         size += sizeof (struct mthca_data_seg) / 16;
1975                 }
1976
1977                 /* Add one more inline data segment for ICRC */
1978                 if (qp->transport == MLX) {
1979                         ((struct mthca_data_seg *) wqe)->byte_count =
1980                                 cpu_to_be32((1 << 31) | 4);
1981                         ((u32 *) wqe)[1] = 0;
1982                         wqe += sizeof (struct mthca_data_seg);
1983                         size += sizeof (struct mthca_data_seg) / 16;
1984                 }
1985
1986                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1987
1988                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1989                         mthca_err(dev, "opcode invalid\n");
1990                         err = -EINVAL;
1991                         *bad_wr = wr;
1992                         goto out;
1993                 }
1994
1995                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1996                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1997                                      qp->send_wqe_offset) |
1998                                     mthca_opcode[wr->opcode]);
1999                 wmb();
2000                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2001                         cpu_to_be32(MTHCA_NEXT_DBD | size);
2002
2003                 if (!size0) {
2004                         size0 = size;
2005                         op0   = mthca_opcode[wr->opcode];
2006                 }
2007
2008                 ++ind;
2009                 if (unlikely(ind >= qp->sq.max))
2010                         ind -= qp->sq.max;
2011         }
2012
2013 out:
2014         if (likely(nreq)) {
2015                 __be32 doorbell[2];
2016
2017                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2018                                           ((qp->sq.head & 0xffff) << 8) |
2019                                           f0 | op0);
2020                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2021
2022                 qp->sq.head += nreq;
2023
2024                 /*
2025                  * Make sure that descriptors are written before
2026                  * doorbell record.
2027                  */
2028                 wmb();
2029                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2030
2031                 /*
2032                  * Make sure doorbell record is written before we
2033                  * write MMIO send doorbell.
2034                  */
2035                 wmb();
2036                 mthca_write64(doorbell,
2037                               dev->kar + MTHCA_SEND_DOORBELL,
2038                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2039         }
2040
2041         spin_unlock_irqrestore(&qp->sq.lock, flags);
2042         return err;
2043 }
2044
2045 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2046                              struct ib_recv_wr **bad_wr)
2047 {
2048         struct mthca_dev *dev = to_mdev(ibqp->device);
2049         struct mthca_qp *qp = to_mqp(ibqp);
2050         unsigned long flags;
2051         int err = 0;
2052         int nreq;
2053         int ind;
2054         int i;
2055         void *wqe;
2056
2057         spin_lock_irqsave(&qp->rq.lock, flags);
2058
2059         /* XXX check that state is OK to post receive */
2060
2061         ind = qp->rq.head & (qp->rq.max - 1);
2062
2063         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2064                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2065                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2066                                         " %d max, %d nreq)\n", qp->qpn,
2067                                         qp->rq.head, qp->rq.tail,
2068                                         qp->rq.max, nreq);
2069                         err = -ENOMEM;
2070                         *bad_wr = wr;
2071                         goto out;
2072                 }
2073
2074                 wqe = get_recv_wqe(qp, ind);
2075
2076                 ((struct mthca_next_seg *) wqe)->flags = 0;
2077
2078                 wqe += sizeof (struct mthca_next_seg);
2079
2080                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2081                         err = -EINVAL;
2082                         *bad_wr = wr;
2083                         goto out;
2084                 }
2085
2086                 for (i = 0; i < wr->num_sge; ++i) {
2087                         ((struct mthca_data_seg *) wqe)->byte_count =
2088                                 cpu_to_be32(wr->sg_list[i].length);
2089                         ((struct mthca_data_seg *) wqe)->lkey =
2090                                 cpu_to_be32(wr->sg_list[i].lkey);
2091                         ((struct mthca_data_seg *) wqe)->addr =
2092                                 cpu_to_be64(wr->sg_list[i].addr);
2093                         wqe += sizeof (struct mthca_data_seg);
2094                 }
2095
2096                 if (i < qp->rq.max_gs) {
2097                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2098                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2099                         ((struct mthca_data_seg *) wqe)->addr = 0;
2100                 }
2101
2102                 qp->wrid[ind] = wr->wr_id;
2103
2104                 ++ind;
2105                 if (unlikely(ind >= qp->rq.max))
2106                         ind -= qp->rq.max;
2107         }
2108 out:
2109         if (likely(nreq)) {
2110                 qp->rq.head += nreq;
2111
2112                 /*
2113                  * Make sure that descriptors are written before
2114                  * doorbell record.
2115                  */
2116                 wmb();
2117                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2118         }
2119
2120         spin_unlock_irqrestore(&qp->rq.lock, flags);
2121         return err;
2122 }
2123
2124 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2125                        int index, int *dbd, __be32 *new_wqe)
2126 {
2127         struct mthca_next_seg *next;
2128
2129         /*
2130          * For SRQs, all WQEs generate a CQE, so we're always at the
2131          * end of the doorbell chain.
2132          */
2133         if (qp->ibqp.srq) {
2134                 *new_wqe = 0;
2135                 return 0;
2136         }
2137
2138         if (is_send)
2139                 next = get_send_wqe(qp, index);
2140         else
2141                 next = get_recv_wqe(qp, index);
2142
2143         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2144         if (next->ee_nds & cpu_to_be32(0x3f))
2145                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2146                         (next->ee_nds & cpu_to_be32(0x3f));
2147         else
2148                 *new_wqe = 0;
2149
2150         return 0;
2151 }
2152
2153 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2154 {
2155         int err;
2156         u8 status;
2157         int i;
2158
2159         spin_lock_init(&dev->qp_table.lock);
2160
2161         /*
2162          * We reserve 2 extra QPs per port for the special QPs.  The
2163          * special QP for port 1 has to be even, so round up.
2164          */
2165         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2166         err = mthca_alloc_init(&dev->qp_table.alloc,
2167                                dev->limits.num_qps,
2168                                (1 << 24) - 1,
2169                                dev->qp_table.sqp_start +
2170                                MTHCA_MAX_PORTS * 2);
2171         if (err)
2172                 return err;
2173
2174         err = mthca_array_init(&dev->qp_table.qp,
2175                                dev->limits.num_qps);
2176         if (err) {
2177                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2178                 return err;
2179         }
2180
2181         for (i = 0; i < 2; ++i) {
2182                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2183                                             dev->qp_table.sqp_start + i * 2,
2184                                             &status);
2185                 if (err)
2186                         goto err_out;
2187                 if (status) {
2188                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2189                                    "status %02x, aborting.\n",
2190                                    status);
2191                         err = -EINVAL;
2192                         goto err_out;
2193                 }
2194         }
2195         return 0;
2196
2197  err_out:
2198         for (i = 0; i < 2; ++i)
2199                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2200
2201         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2202         mthca_alloc_cleanup(&dev->qp_table.alloc);
2203
2204         return err;
2205 }
2206
2207 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2208 {
2209         int i;
2210         u8 status;
2211
2212         for (i = 0; i < 2; ++i)
2213                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2214
2215         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2216         mthca_alloc_cleanup(&dev->qp_table.alloc);
2217 }