drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39 #include <linux/string.h>
  40 #include <linux/slab.h>
  41
  42 #include <rdma/ib_verbs.h>
  43 #include <rdma/ib_cache.h>
  44 #include <rdma/ib_pack.h>
  45
  46 #include "mthca_dev.h"
  47 #include "mthca_cmd.h"
  48 #include "mthca_memfree.h"
  49 #include "mthca_wqe.h"
  50
  51 enum {
  52         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  53         MTHCA_ACK_REQ_FREQ       = 10,
  54         MTHCA_FLIGHT_LIMIT       = 9,
  55         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  56         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  57         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  58 };
  59
  60 enum {
  61         MTHCA_QP_STATE_RST  = 0,
  62         MTHCA_QP_STATE_INIT = 1,
  63         MTHCA_QP_STATE_RTR  = 2,
  64         MTHCA_QP_STATE_RTS  = 3,
  65         MTHCA_QP_STATE_SQE  = 4,
  66         MTHCA_QP_STATE_SQD  = 5,
  67         MTHCA_QP_STATE_ERR  = 6,
  68         MTHCA_QP_STATE_DRAINING = 7
  69 };
  70
  71 enum {
  72         MTHCA_QP_ST_RC  = 0x0,
  73         MTHCA_QP_ST_UC  = 0x1,
  74         MTHCA_QP_ST_RD  = 0x2,
  75         MTHCA_QP_ST_UD  = 0x3,
  76         MTHCA_QP_ST_MLX = 0x7
  77 };
  78
  79 enum {
  80         MTHCA_QP_PM_MIGRATED = 0x3,
  81         MTHCA_QP_PM_ARMED    = 0x0,
  82         MTHCA_QP_PM_REARM    = 0x1
  83 };
  84
  85 enum {
  86         /* qp_context flags */
  87         MTHCA_QP_BIT_DE  = 1 <<  8,
  88         /* params1 */
  89         MTHCA_QP_BIT_SRE = 1 << 15,
  90         MTHCA_QP_BIT_SWE = 1 << 14,
  91         MTHCA_QP_BIT_SAE = 1 << 13,
  92         MTHCA_QP_BIT_SIC = 1 <<  4,
  93         MTHCA_QP_BIT_SSC = 1 <<  3,
  94         /* params2 */
  95         MTHCA_QP_BIT_RRE = 1 << 15,
  96         MTHCA_QP_BIT_RWE = 1 << 14,
  97         MTHCA_QP_BIT_RAE = 1 << 13,
  98         MTHCA_QP_BIT_RIC = 1 <<  4,
  99         MTHCA_QP_BIT_RSC = 1 <<  3
 100 };
 101
 102 struct mthca_qp_path {
 103         __be32 port_pkey;
 104         u8     rnr_retry;
 105         u8     g_mylmc;
 106         __be16 rlid;
 107         u8     ackto;
 108         u8     mgid_index;
 109         u8     static_rate;
 110         u8     hop_limit;
 111         __be32 sl_tclass_flowlabel;
 112         u8     rgid[16];
 113 } __attribute__((packed));
 114
 115 struct mthca_qp_context {
 116         __be32 flags;
 117         __be32 tavor_sched_queue; /* Reserved on Arbel */
 118         u8     mtu_msgmax;
 119         u8     rq_size_stride;  /* Reserved on Tavor */
 120         u8     sq_size_stride;  /* Reserved on Tavor */
 121         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 122         __be32 usr_page;
 123         __be32 local_qpn;
 124         __be32 remote_qpn;
 125         u32    reserved1[2];
 126         struct mthca_qp_path pri_path;
 127         struct mthca_qp_path alt_path;
 128         __be32 rdd;
 129         __be32 pd;
 130         __be32 wqe_base;
 131         __be32 wqe_lkey;
 132         __be32 params1;
 133         __be32 reserved2;
 134         __be32 next_send_psn;
 135         __be32 cqn_snd;
 136         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 137         __be32 snd_db_index;    /* (debugging only entries) */
 138         __be32 last_acked_psn;
 139         __be32 ssn;
 140         __be32 params2;
 141         __be32 rnr_nextrecvpsn;
 142         __be32 ra_buff_indx;
 143         __be32 cqn_rcv;
 144         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 145         __be32 rcv_db_index;    /* (debugging only entries) */
 146         __be32 qkey;
 147         __be32 srqn;
 148         __be32 rmsn;
 149         __be16 rq_wqe_counter;  /* reserved on Tavor */
 150         __be16 sq_wqe_counter;  /* reserved on Tavor */
 151         u32    reserved3[18];
 152 } __attribute__((packed));
 153
 154 struct mthca_qp_param {
 155         __be32 opt_param_mask;
 156         u32    reserved1;
 157         struct mthca_qp_context context;
 158         u32    reserved2[62];
 159 } __attribute__((packed));
 160
 161 enum {
 162         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 163         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 164         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 165         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 166         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 167         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 168         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 169         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 170         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 171         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 172         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 173         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 174         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 175         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 176         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 177         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 178         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 179 };
 180
 181 static const u8 mthca_opcode[] = {
 182         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 183         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 184         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 185         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 186         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 187         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 188         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 189 };
 190
 191 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 192 {
 193         return qp->qpn >= dev->qp_table.sqp_start &&
 194                 qp->qpn <= dev->qp_table.sqp_start + 3;
 195 }
 196
 197 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 198 {
 199         return qp->qpn >= dev->qp_table.sqp_start &&
 200                 qp->qpn <= dev->qp_table.sqp_start + 1;
 201 }
 202
 203 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 204 {
 205         if (qp->is_direct)
 206                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 207         else
 208                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 209                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 210 }
 211
 212 static void *get_send_wqe(struct mthca_qp *qp, int n)
 213 {
 214         if (qp->is_direct)
 215                 return qp->queue.direct.buf + qp->send_wqe_offset +
 216                         (n << qp->sq.wqe_shift);
 217         else
 218                 return qp->queue.page_list[(qp->send_wqe_offset +
 219                                             (n << qp->sq.wqe_shift)) >>
 220                                            PAGE_SHIFT].buf +
 221                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 222                          (PAGE_SIZE - 1));
 223 }
 224
 225 static void mthca_wq_init(struct mthca_wq *wq)
 226 {
 227         spin_lock_init(&wq->lock);
 228         wq->next_ind  = 0;
 229         wq->last_comp = wq->max - 1;
 230         wq->head      = 0;
 231         wq->tail      = 0;
 232 }
 233
 234 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 235                     enum ib_event_type event_type)
 236 {
 237         struct mthca_qp *qp;
 238         struct ib_event event;
 239
 240         spin_lock(&dev->qp_table.lock);
 241         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 242         if (qp)
 243                 atomic_inc(&qp->refcount);
 244         spin_unlock(&dev->qp_table.lock);
 245
 246         if (!qp) {
 247                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 248                 return;
 249         }
 250
 251         event.device      = &dev->ib_dev;
 252         event.event       = event_type;
 253         event.element.qp  = &qp->ibqp;
 254         if (qp->ibqp.event_handler)
 255                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 256
 257         if (atomic_dec_and_test(&qp->refcount))
 258                 wake_up(&qp->wait);
 259 }
 260
 261 static int to_mthca_state(enum ib_qp_state ib_state)
 262 {
 263         switch (ib_state) {
 264         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 265         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 266         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 267         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 268         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 269         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 270         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 271         default:                return -1;
 272         }
 273 }
 274
 275 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 276
 277 static int to_mthca_st(int transport)
 278 {
 279         switch (transport) {
 280         case RC:  return MTHCA_QP_ST_RC;
 281         case UC:  return MTHCA_QP_ST_UC;
 282         case UD:  return MTHCA_QP_ST_UD;
 283         case RD:  return MTHCA_QP_ST_RD;
 284         case MLX: return MTHCA_QP_ST_MLX;
 285         default:  return -1;
 286         }
 287 }
 288
 289 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 290                         int attr_mask)
 291 {
 292         if (attr_mask & IB_QP_PKEY_INDEX)
 293                 sqp->pkey_index = attr->pkey_index;
 294         if (attr_mask & IB_QP_QKEY)
 295                 sqp->qkey = attr->qkey;
 296         if (attr_mask & IB_QP_SQ_PSN)
 297                 sqp->send_psn = attr->sq_psn;
 298 }
 299
 300 static void init_port(struct mthca_dev *dev, int port)
 301 {
 302         int err;
 303         u8 status;
 304         struct mthca_init_ib_param param;
 305
 306         memset(&param, 0, sizeof param);
 307
 308         param.port_width = dev->limits.port_width_cap;
 309         param.vl_cap     = dev->limits.vl_cap;
 310         param.mtu_cap    = dev->limits.mtu_cap;
 311         param.gid_cap    = dev->limits.gid_table_len;
 312         param.pkey_cap   = dev->limits.pkey_table_len;
 313
 314         err = mthca_INIT_IB(dev, &param, port, &status);
 315         if (err)
 316                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 317         if (status)
 318                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 319 }
 320
 321 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
 322                                   int attr_mask)
 323 {
 324         u8 dest_rd_atomic;
 325         u32 access_flags;
 326         u32 hw_access_flags = 0;
 327
 328         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 329                 dest_rd_atomic = attr->max_dest_rd_atomic;
 330         else
 331                 dest_rd_atomic = qp->resp_depth;
 332
 333         if (attr_mask & IB_QP_ACCESS_FLAGS)
 334                 access_flags = attr->qp_access_flags;
 335         else
 336                 access_flags = qp->atomic_rd_en;
 337
 338         if (!dest_rd_atomic)
 339                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 340
 341         if (access_flags & IB_ACCESS_REMOTE_READ)
 342                 hw_access_flags |= MTHCA_QP_BIT_RRE;
 343         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 344                 hw_access_flags |= MTHCA_QP_BIT_RAE;
 345         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 346                 hw_access_flags |= MTHCA_QP_BIT_RWE;
 347
 348         return cpu_to_be32(hw_access_flags);
 349 }
 350
 351 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
 352 {
 353         switch (mthca_state) {
 354         case MTHCA_QP_STATE_RST:      return IB_QPS_RESET;
 355         case MTHCA_QP_STATE_INIT:     return IB_QPS_INIT;
 356         case MTHCA_QP_STATE_RTR:      return IB_QPS_RTR;
 357         case MTHCA_QP_STATE_RTS:      return IB_QPS_RTS;
 358         case MTHCA_QP_STATE_DRAINING:
 359         case MTHCA_QP_STATE_SQD:      return IB_QPS_SQD;
 360         case MTHCA_QP_STATE_SQE:      return IB_QPS_SQE;
 361         case MTHCA_QP_STATE_ERR:      return IB_QPS_ERR;
 362         default:                      return -1;
 363         }
 364 }
 365
 366 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
 367 {
 368         switch (mthca_mig_state) {
 369         case 0:  return IB_MIG_ARMED;
 370         case 1:  return IB_MIG_REARM;
 371         case 3:  return IB_MIG_MIGRATED;
 372         default: return -1;
 373         }
 374 }
 375
 376 static int to_ib_qp_access_flags(int mthca_flags)
 377 {
 378         int ib_flags = 0;
 379
 380         if (mthca_flags & MTHCA_QP_BIT_RRE)
 381                 ib_flags |= IB_ACCESS_REMOTE_READ;
 382         if (mthca_flags & MTHCA_QP_BIT_RWE)
 383                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
 384         if (mthca_flags & MTHCA_QP_BIT_RAE)
 385                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
 386
 387         return ib_flags;
 388 }
 389
 390 static void to_ib_ah_attr(struct mthca_dev *dev, struct ib_ah_attr *ib_ah_attr,
 391                                 struct mthca_qp_path *path)
 392 {
 393         memset(ib_ah_attr, 0, sizeof *path);
 394         ib_ah_attr->port_num      = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
 395         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
 396         ib_ah_attr->sl            = be32_to_cpu(path->sl_tclass_flowlabel) >> 28;
 397         ib_ah_attr->src_path_bits = path->g_mylmc & 0x7f;
 398         ib_ah_attr->static_rate   = path->static_rate & 0x7;
 399         ib_ah_attr->ah_flags      = (path->g_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
 400         if (ib_ah_attr->ah_flags) {
 401                 ib_ah_attr->grh.sgid_index = path->mgid_index & (dev->limits.gid_table_len - 1);
 402                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
 403                 ib_ah_attr->grh.traffic_class =
 404                         (be32_to_cpu(path->sl_tclass_flowlabel) >> 20) & 0xff;
 405                 ib_ah_attr->grh.flow_label =
 406                         be32_to_cpu(path->sl_tclass_flowlabel) & 0xfffff;
 407                 memcpy(ib_ah_attr->grh.dgid.raw,
 408                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
 409         }
 410 }
 411
 412 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
 413                    struct ib_qp_init_attr *qp_init_attr)
 414 {
 415         struct mthca_dev *dev = to_mdev(ibqp->device);
 416         struct mthca_qp *qp = to_mqp(ibqp);
 417         int err;
 418         struct mthca_mailbox *mailbox;
 419         struct mthca_qp_param *qp_param;
 420         struct mthca_qp_context *context;
 421         int mthca_state;
 422         u8 status;
 423
 424         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 425         if (IS_ERR(mailbox))
 426                 return PTR_ERR(mailbox);
 427
 428         err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox, &status);
 429         if (err)
 430                 goto out;
 431         if (status) {
 432                 mthca_warn(dev, "QUERY_QP returned status %02x\n", status);
 433                 err = -EINVAL;
 434                 goto out;
 435         }
 436
 437         qp_param    = mailbox->buf;
 438         context     = &qp_param->context;
 439         mthca_state = be32_to_cpu(context->flags) >> 28;
 440
 441         qp_attr->qp_state            = to_ib_qp_state(mthca_state);
 442         qp_attr->cur_qp_state        = qp_attr->qp_state;
 443         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
 444         qp_attr->path_mig_state      =
 445                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
 446         qp_attr->qkey                = be32_to_cpu(context->qkey);
 447         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
 448         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
 449         qp_attr->dest_qp_num         = be32_to_cpu(context->remote_qpn) & 0xffffff;
 450         qp_attr->qp_access_flags     =
 451                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
 452         qp_attr->cap.max_send_wr     = qp->sq.max;
 453         qp_attr->cap.max_recv_wr     = qp->rq.max;
 454         qp_attr->cap.max_send_sge    = qp->sq.max_gs;
 455         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
 456         qp_attr->cap.max_inline_data = qp->max_inline_data;
 457
 458         to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
 459         to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
 460
 461         qp_attr->pkey_index     = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
 462         qp_attr->alt_pkey_index = be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
 463
 464         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
 465         qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
 466
 467         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
 468
 469         qp_attr->max_dest_rd_atomic =
 470                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
 471         qp_attr->min_rnr_timer      =
 472                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
 473         qp_attr->port_num           = qp_attr->ah_attr.port_num;
 474         qp_attr->timeout            = context->pri_path.ackto >> 3;
 475         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
 476         qp_attr->rnr_retry          = context->pri_path.rnr_retry >> 5;
 477         qp_attr->alt_port_num       = qp_attr->alt_ah_attr.port_num;
 478         qp_attr->alt_timeout        = context->alt_path.ackto >> 3;
 479         qp_init_attr->cap           = qp_attr->cap;
 480
 481 out:
 482         mthca_free_mailbox(dev, mailbox);
 483         return err;
 484 }
 485
 486 static int mthca_path_set(struct mthca_dev *dev, struct ib_ah_attr *ah,
 487                           struct mthca_qp_path *path)
 488 {
 489         path->g_mylmc     = ah->src_path_bits & 0x7f;
 490         path->rlid        = cpu_to_be16(ah->dlid);
 491         path->static_rate = !!ah->static_rate;
 492
 493         if (ah->ah_flags & IB_AH_GRH) {
 494                 if (ah->grh.sgid_index >= dev->limits.gid_table_len) {
 495                         mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
 496                                   ah->grh.sgid_index, dev->limits.gid_table_len-1);
 497                         return -1;
 498                 }
 499
 500                 path->g_mylmc   |= 1 << 7;
 501                 path->mgid_index = ah->grh.sgid_index;
 502                 path->hop_limit  = ah->grh.hop_limit;
 503                 path->sl_tclass_flowlabel =
 504                         cpu_to_be32((ah->sl << 28)                |
 505                                     (ah->grh.traffic_class << 20) |
 506                                     (ah->grh.flow_label));
 507                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
 508         } else
 509                 path->sl_tclass_flowlabel = cpu_to_be32(ah->sl << 28);
 510
 511         return 0;
 512 }
 513
 514 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 515 {
 516         struct mthca_dev *dev = to_mdev(ibqp->device);
 517         struct mthca_qp *qp = to_mqp(ibqp);
 518         enum ib_qp_state cur_state, new_state;
 519         struct mthca_mailbox *mailbox;
 520         struct mthca_qp_param *qp_param;
 521         struct mthca_qp_context *qp_context;
 522         u32 sqd_event = 0;
 523         u8 status;
 524         int err;
 525
 526         if (attr_mask & IB_QP_CUR_STATE) {
 527                 cur_state = attr->cur_qp_state;
 528         } else {
 529                 spin_lock_irq(&qp->sq.lock);
 530                 spin_lock(&qp->rq.lock);
 531                 cur_state = qp->state;
 532                 spin_unlock(&qp->rq.lock);
 533                 spin_unlock_irq(&qp->sq.lock);
 534         }
 535
 536         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
 537
 538         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
 539                 mthca_dbg(dev, "Bad QP transition (transport %d) "
 540                           "%d->%d with attr 0x%08x\n",
 541                           qp->transport, cur_state, new_state,
 542                           attr_mask);
 543                 return -EINVAL;
 544         }
 545
 546         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 547              attr->pkey_index >= dev->limits.pkey_table_len) {
 548                 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
 549                           attr->pkey_index, dev->limits.pkey_table_len-1);
 550                 return -EINVAL;
 551         }
 552
 553         if ((attr_mask & IB_QP_PORT) &&
 554             (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
 555                 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
 556                 return -EINVAL;
 557         }
 558
 559         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 560             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 561                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 562                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 563                 return -EINVAL;
 564         }
 565
 566         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 567             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 568                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 569                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 570                 return -EINVAL;
 571         }
 572
 573         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 574         if (IS_ERR(mailbox))
 575                 return PTR_ERR(mailbox);
 576         qp_param = mailbox->buf;
 577         qp_context = &qp_param->context;
 578         memset(qp_param, 0, sizeof *qp_param);
 579
 580         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 581                                              (to_mthca_st(qp->transport) << 16));
 582         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 583         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 584                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 585         else {
 586                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 587                 switch (attr->path_mig_state) {
 588                 case IB_MIG_MIGRATED:
 589                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 590                         break;
 591                 case IB_MIG_REARM:
 592                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 593                         break;
 594                 case IB_MIG_ARMED:
 595                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 596                         break;
 597                 }
 598         }
 599
 600         /* leave tavor_sched_queue as 0 */
 601
 602         if (qp->transport == MLX || qp->transport == UD)
 603                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 604         else if (attr_mask & IB_QP_PATH_MTU) {
 605                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
 606                         mthca_dbg(dev, "path MTU (%u) is invalid\n",
 607                                   attr->path_mtu);
 608                         return -EINVAL;
 609                 }
 610                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 611         }
 612
 613         if (mthca_is_memfree(dev)) {
 614                 if (qp->rq.max)
 615                         qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
 616                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 617
 618                 if (qp->sq.max)
 619                         qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
 620                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 621         }
 622
 623         /* leave arbel_sched_queue as 0 */
 624
 625         if (qp->ibqp.uobject)
 626                 qp_context->usr_page =
 627                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 628         else
 629                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 630         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 631         if (attr_mask & IB_QP_DEST_QPN) {
 632                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 633         }
 634
 635         if (qp->transport == MLX)
 636                 qp_context->pri_path.port_pkey |=
 637                         cpu_to_be32(to_msqp(qp)->port << 24);
 638         else {
 639                 if (attr_mask & IB_QP_PORT) {
 640                         qp_context->pri_path.port_pkey |=
 641                                 cpu_to_be32(attr->port_num << 24);
 642                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 643                 }
 644         }
 645
 646         if (attr_mask & IB_QP_PKEY_INDEX) {
 647                 qp_context->pri_path.port_pkey |=
 648                         cpu_to_be32(attr->pkey_index);
 649                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 650         }
 651
 652         if (attr_mask & IB_QP_RNR_RETRY) {
 653                 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
 654                         attr->rnr_retry << 5;
 655                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
 656                                                         MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
 657         }
 658
 659         if (attr_mask & IB_QP_AV) {
 660                 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path))
 661                         return -EINVAL;
 662
 663                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 664         }
 665
 666         if (attr_mask & IB_QP_TIMEOUT) {
 667                 qp_context->pri_path.ackto = attr->timeout << 3;
 668                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 669         }
 670
 671         if (attr_mask & IB_QP_ALT_PATH) {
 672                 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
 673                         mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
 674                                   attr->alt_pkey_index, dev->limits.pkey_table_len-1);
 675                         return -EINVAL;
 676                 }
 677
 678                 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
 679                         mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
 680                                 attr->alt_port_num);
 681                         return -EINVAL;
 682                 }
 683
 684                 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path))
 685                         return -EINVAL;
 686
 687                 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
 688                                                               attr->alt_port_num << 24);
 689                 qp_context->alt_path.ackto = attr->alt_timeout << 3;
 690                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
 691         }
 692
 693         /* leave rdd as 0 */
 694         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 695         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 696         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 697         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 698                                              (MTHCA_FLIGHT_LIMIT << 24) |
 699                                              MTHCA_QP_BIT_SWE);
 700         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 701                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 702         if (attr_mask & IB_QP_RETRY_CNT) {
 703                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 704                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 705         }
 706
 707         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 708                 if (attr->max_rd_atomic) {
 709                         qp_context->params1 |=
 710                                 cpu_to_be32(MTHCA_QP_BIT_SRE |
 711                                             MTHCA_QP_BIT_SAE);
 712                         qp_context->params1 |=
 713                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 714                 }
 715                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 716         }
 717
 718         if (attr_mask & IB_QP_SQ_PSN)
 719                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 720         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 721
 722         if (mthca_is_memfree(dev)) {
 723                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 724                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 725         }
 726
 727         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 728                 if (attr->max_dest_rd_atomic)
 729                         qp_context->params2 |=
 730                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 731
 732                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 733         }
 734
 735         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 736                 qp_context->params2      |= get_hw_access_flags(qp, attr, attr_mask);
 737                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 738                                                         MTHCA_QP_OPTPAR_RRE |
 739                                                         MTHCA_QP_OPTPAR_RAE);
 740         }
 741
 742         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 743
 744         if (ibqp->srq)
 745                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 746
 747         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 748                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 749                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 750         }
 751         if (attr_mask & IB_QP_RQ_PSN)
 752                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 753
 754         qp_context->ra_buff_indx =
 755                 cpu_to_be32(dev->qp_table.rdb_base +
 756                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 757                              dev->qp_table.rdb_shift));
 758
 759         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 760
 761         if (mthca_is_memfree(dev))
 762                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 763
 764         if (attr_mask & IB_QP_QKEY) {
 765                 qp_context->qkey = cpu_to_be32(attr->qkey);
 766                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 767         }
 768
 769         if (ibqp->srq)
 770                 qp_context->srqn = cpu_to_be32(1 << 24 |
 771                                                to_msrq(ibqp->srq)->srqn);
 772
 773         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
 774             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY               &&
 775             attr->en_sqd_async_notify)
 776                 sqd_event = 1 << 31;
 777
 778         err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
 779                               mailbox, sqd_event, &status);
 780         if (status) {
 781                 mthca_warn(dev, "modify QP %d->%d returned status %02x.\n",
 782                            cur_state, new_state, status);
 783                 err = -EINVAL;
 784         }
 785
 786         if (!err) {
 787                 qp->state = new_state;
 788                 if (attr_mask & IB_QP_ACCESS_FLAGS)
 789                         qp->atomic_rd_en = attr->qp_access_flags;
 790                 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 791                         qp->resp_depth = attr->max_dest_rd_atomic;
 792         }
 793
 794         mthca_free_mailbox(dev, mailbox);
 795
 796         if (is_sqp(dev, qp))
 797                 store_attrs(to_msqp(qp), attr, attr_mask);
 798
 799         /*
 800          * If we moved QP0 to RTR, bring the IB link up; if we moved
 801          * QP0 to RESET or ERROR, bring the link back down.
 802          */
 803         if (is_qp0(dev, qp)) {
 804                 if (cur_state != IB_QPS_RTR &&
 805                     new_state == IB_QPS_RTR)
 806                         init_port(dev, to_msqp(qp)->port);
 807
 808                 if (cur_state != IB_QPS_RESET &&
 809                     cur_state != IB_QPS_ERR &&
 810                     (new_state == IB_QPS_RESET ||
 811                      new_state == IB_QPS_ERR))
 812                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 813         }
 814
 815         /*
 816          * If we moved a kernel QP to RESET, clean up all old CQ
 817          * entries and reinitialize the QP.
 818          */
 819         if (!err && new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 820                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
 821                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 822                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 823                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
 824                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 825
 826                 mthca_wq_init(&qp->sq);
 827                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 828
 829                 mthca_wq_init(&qp->rq);
 830                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 831
 832                 if (mthca_is_memfree(dev)) {
 833                         *qp->sq.db = 0;
 834                         *qp->rq.db = 0;
 835                 }
 836         }
 837
 838         return err;
 839 }
 840
 841 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
 842 {
 843         /*
 844          * Calculate the maximum size of WQE s/g segments, excluding
 845          * the next segment and other non-data segments.
 846          */
 847         int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
 848
 849         switch (qp->transport) {
 850         case MLX:
 851                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 852                 break;
 853
 854         case UD:
 855                 if (mthca_is_memfree(dev))
 856                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 857                 else
 858                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 859                 break;
 860
 861         default:
 862                 max_data_size -= sizeof (struct mthca_raddr_seg);
 863                 break;
 864         }
 865
 866         return max_data_size;
 867 }
 868
 869 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
 870 {
 871         /* We don't support inline data for kernel QPs (yet). */
 872         return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
 873 }
 874
 875 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 876                                  struct mthca_pd *pd,
 877                                  struct mthca_qp *qp)
 878 {
 879         int max_data_size = mthca_max_data_size(dev, qp,
 880                                                 min(dev->limits.max_desc_sz,
 881                                                     1 << qp->sq.wqe_shift));
 882
 883         qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
 884
 885         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 886                               max_data_size / sizeof (struct mthca_data_seg));
 887         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 888                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 889                                 sizeof (struct mthca_next_seg)) /
 890                                sizeof (struct mthca_data_seg));
 891 }
 892
 893 /*
 894  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 895  * rq.max_gs and sq.max_gs must all be assigned.
 896  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 897  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 898  * queue)
 899  */
 900 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 901                                struct mthca_pd *pd,
 902                                struct mthca_qp *qp)
 903 {
 904         int size;
 905         int err = -ENOMEM;
 906
 907         size = sizeof (struct mthca_next_seg) +
 908                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 909
 910         if (size > dev->limits.max_desc_sz)
 911                 return -EINVAL;
 912
 913         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 914              qp->rq.wqe_shift++)
 915                 ; /* nothing */
 916
 917         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 918         switch (qp->transport) {
 919         case MLX:
 920                 size += 2 * sizeof (struct mthca_data_seg);
 921                 break;
 922
 923         case UD:
 924                 size += mthca_is_memfree(dev) ?
 925                         sizeof (struct mthca_arbel_ud_seg) :
 926                         sizeof (struct mthca_tavor_ud_seg);
 927                 break;
 928
 929         case UC:
 930                 size += sizeof (struct mthca_raddr_seg);
 931                 break;
 932
 933         case RC:
 934                 size += sizeof (struct mthca_raddr_seg);
 935                 /*
 936                  * An atomic op will require an atomic segment, a
 937                  * remote address segment and one scatter entry.
 938                  */
 939                 size = max_t(int, size,
 940                              sizeof (struct mthca_atomic_seg) +
 941                              sizeof (struct mthca_raddr_seg) +
 942                              sizeof (struct mthca_data_seg));
 943                 break;
 944
 945         default:
 946                 break;
 947         }
 948
 949         /* Make sure that we have enough space for a bind request */
 950         size = max_t(int, size, sizeof (struct mthca_bind_seg));
 951
 952         size += sizeof (struct mthca_next_seg);
 953
 954         if (size > dev->limits.max_desc_sz)
 955                 return -EINVAL;
 956
 957         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 958              qp->sq.wqe_shift++)
 959                 ; /* nothing */
 960
 961         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 962                                     1 << qp->sq.wqe_shift);
 963
 964         /*
 965          * If this is a userspace QP, we don't actually have to
 966          * allocate anything.  All we need is to calculate the WQE
 967          * sizes and the send_wqe_offset, so we're done now.
 968          */
 969         if (pd->ibpd.uobject)
 970                 return 0;
 971
 972         size = PAGE_ALIGN(qp->send_wqe_offset +
 973                           (qp->sq.max << qp->sq.wqe_shift));
 974
 975         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
 976                            GFP_KERNEL);
 977         if (!qp->wrid)
 978                 goto err_out;
 979
 980         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
 981                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
 982         if (err)
 983                 goto err_out;
 984
 985         return 0;
 986
 987 err_out:
 988         kfree(qp->wrid);
 989         return err;
 990 }
 991
 992 static void mthca_free_wqe_buf(struct mthca_dev *dev,
 993                                struct mthca_qp *qp)
 994 {
 995         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
 996                                        (qp->sq.max << qp->sq.wqe_shift)),
 997                        &qp->queue, qp->is_direct, &qp->mr);
 998         kfree(qp->wrid);
 999 }
1000
1001 static int mthca_map_memfree(struct mthca_dev *dev,
1002                              struct mthca_qp *qp)
1003 {
1004         int ret;
1005
1006         if (mthca_is_memfree(dev)) {
1007                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1008                 if (ret)
1009                         return ret;
1010
1011                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1012                 if (ret)
1013                         goto err_qpc;
1014
1015                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1016                                       qp->qpn << dev->qp_table.rdb_shift);
1017                 if (ret)
1018                         goto err_eqpc;
1019
1020         }
1021
1022         return 0;
1023
1024 err_eqpc:
1025         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1026
1027 err_qpc:
1028         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1029
1030         return ret;
1031 }
1032
1033 static void mthca_unmap_memfree(struct mthca_dev *dev,
1034                                 struct mthca_qp *qp)
1035 {
1036         mthca_table_put(dev, dev->qp_table.rdb_table,
1037                         qp->qpn << dev->qp_table.rdb_shift);
1038         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1039         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1040 }
1041
1042 static int mthca_alloc_memfree(struct mthca_dev *dev,
1043                                struct mthca_qp *qp)
1044 {
1045         int ret = 0;
1046
1047         if (mthca_is_memfree(dev)) {
1048                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1049                                                  qp->qpn, &qp->rq.db);
1050                 if (qp->rq.db_index < 0)
1051                         return ret;
1052
1053                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1054                                                  qp->qpn, &qp->sq.db);
1055                 if (qp->sq.db_index < 0)
1056                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1057         }
1058
1059         return ret;
1060 }
1061
1062 static void mthca_free_memfree(struct mthca_dev *dev,
1063                                struct mthca_qp *qp)
1064 {
1065         if (mthca_is_memfree(dev)) {
1066                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1067                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1068         }
1069 }
1070
1071 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1072                                  struct mthca_pd *pd,
1073                                  struct mthca_cq *send_cq,
1074                                  struct mthca_cq *recv_cq,
1075                                  enum ib_sig_type send_policy,
1076                                  struct mthca_qp *qp)
1077 {
1078         int ret;
1079         int i;
1080
1081         atomic_set(&qp->refcount, 1);
1082         init_waitqueue_head(&qp->wait);
1083         qp->state        = IB_QPS_RESET;
1084         qp->atomic_rd_en = 0;
1085         qp->resp_depth   = 0;
1086         qp->sq_policy    = send_policy;
1087         mthca_wq_init(&qp->sq);
1088         mthca_wq_init(&qp->rq);
1089
1090         ret = mthca_map_memfree(dev, qp);
1091         if (ret)
1092                 return ret;
1093
1094         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1095         if (ret) {
1096                 mthca_unmap_memfree(dev, qp);
1097                 return ret;
1098         }
1099
1100         mthca_adjust_qp_caps(dev, pd, qp);
1101
1102         /*
1103          * If this is a userspace QP, we're done now.  The doorbells
1104          * will be allocated and buffers will be initialized in
1105          * userspace.
1106          */
1107         if (pd->ibpd.uobject)
1108                 return 0;
1109
1110         ret = mthca_alloc_memfree(dev, qp);
1111         if (ret) {
1112                 mthca_free_wqe_buf(dev, qp);
1113                 mthca_unmap_memfree(dev, qp);
1114                 return ret;
1115         }
1116
1117         if (mthca_is_memfree(dev)) {
1118                 struct mthca_next_seg *next;
1119                 struct mthca_data_seg *scatter;
1120                 int size = (sizeof (struct mthca_next_seg) +
1121                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1122
1123                 for (i = 0; i < qp->rq.max; ++i) {
1124                         next = get_recv_wqe(qp, i);
1125                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1126                                                    qp->rq.wqe_shift);
1127                         next->ee_nds = cpu_to_be32(size);
1128
1129                         for (scatter = (void *) (next + 1);
1130                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1131                              ++scatter)
1132                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1133                 }
1134
1135                 for (i = 0; i < qp->sq.max; ++i) {
1136                         next = get_send_wqe(qp, i);
1137                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1138                                                     qp->sq.wqe_shift) +
1139                                                    qp->send_wqe_offset);
1140                 }
1141         }
1142
1143         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1144         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1145
1146         return 0;
1147 }
1148
1149 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1150                              struct mthca_pd *pd, struct mthca_qp *qp)
1151 {
1152         int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1153
1154         /* Sanity check QP size before proceeding */
1155         if (cap->max_send_wr     > dev->limits.max_wqes ||
1156             cap->max_recv_wr     > dev->limits.max_wqes ||
1157             cap->max_send_sge    > dev->limits.max_sg   ||
1158             cap->max_recv_sge    > dev->limits.max_sg   ||
1159             cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1160                 return -EINVAL;
1161
1162         /*
1163          * For MLX transport we need 2 extra S/G entries:
1164          * one for the header and one for the checksum at the end
1165          */
1166         if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1167                 return -EINVAL;
1168
1169         if (mthca_is_memfree(dev)) {
1170                 qp->rq.max = cap->max_recv_wr ?
1171                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1172                 qp->sq.max = cap->max_send_wr ?
1173                         roundup_pow_of_two(cap->max_send_wr) : 0;
1174         } else {
1175                 qp->rq.max = cap->max_recv_wr;
1176                 qp->sq.max = cap->max_send_wr;
1177         }
1178
1179         qp->rq.max_gs = cap->max_recv_sge;
1180         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1181                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1182                                     MTHCA_INLINE_CHUNK_SIZE) /
1183                               sizeof (struct mthca_data_seg));
1184
1185         return 0;
1186 }
1187
1188 int mthca_alloc_qp(struct mthca_dev *dev,
1189                    struct mthca_pd *pd,
1190                    struct mthca_cq *send_cq,
1191                    struct mthca_cq *recv_cq,
1192                    enum ib_qp_type type,
1193                    enum ib_sig_type send_policy,
1194                    struct ib_qp_cap *cap,
1195                    struct mthca_qp *qp)
1196 {
1197         int err;
1198
1199         err = mthca_set_qp_size(dev, cap, pd, qp);
1200         if (err)
1201                 return err;
1202
1203         switch (type) {
1204         case IB_QPT_RC: qp->transport = RC; break;
1205         case IB_QPT_UC: qp->transport = UC; break;
1206         case IB_QPT_UD: qp->transport = UD; break;
1207         default: return -EINVAL;
1208         }
1209
1210         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1211         if (qp->qpn == -1)
1212                 return -ENOMEM;
1213
1214         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1215                                     send_policy, qp);
1216         if (err) {
1217                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1218                 return err;
1219         }
1220
1221         spin_lock_irq(&dev->qp_table.lock);
1222         mthca_array_set(&dev->qp_table.qp,
1223                         qp->qpn & (dev->limits.num_qps - 1), qp);
1224         spin_unlock_irq(&dev->qp_table.lock);
1225
1226         return 0;
1227 }
1228
1229 int mthca_alloc_sqp(struct mthca_dev *dev,
1230                     struct mthca_pd *pd,
1231                     struct mthca_cq *send_cq,
1232                     struct mthca_cq *recv_cq,
1233                     enum ib_sig_type send_policy,
1234                     struct ib_qp_cap *cap,
1235                     int qpn,
1236                     int port,
1237                     struct mthca_sqp *sqp)
1238 {
1239         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1240         int err;
1241
1242         err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1243         if (err)
1244                 return err;
1245
1246         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1247         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1248                                              &sqp->header_dma, GFP_KERNEL);
1249         if (!sqp->header_buf)
1250                 return -ENOMEM;
1251
1252         spin_lock_irq(&dev->qp_table.lock);
1253         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1254                 err = -EBUSY;
1255         else
1256                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1257         spin_unlock_irq(&dev->qp_table.lock);
1258
1259         if (err)
1260                 goto err_out;
1261
1262         sqp->port = port;
1263         sqp->qp.qpn       = mqpn;
1264         sqp->qp.transport = MLX;
1265
1266         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1267                                     send_policy, &sqp->qp);
1268         if (err)
1269                 goto err_out_free;
1270
1271         atomic_inc(&pd->sqp_count);
1272
1273         return 0;
1274
1275  err_out_free:
1276         /*
1277          * Lock CQs here, so that CQ polling code can do QP lookup
1278          * without taking a lock.
1279          */
1280         spin_lock_irq(&send_cq->lock);
1281         if (send_cq != recv_cq)
1282                 spin_lock(&recv_cq->lock);
1283
1284         spin_lock(&dev->qp_table.lock);
1285         mthca_array_clear(&dev->qp_table.qp, mqpn);
1286         spin_unlock(&dev->qp_table.lock);
1287
1288         if (send_cq != recv_cq)
1289                 spin_unlock(&recv_cq->lock);
1290         spin_unlock_irq(&send_cq->lock);
1291
1292  err_out:
1293         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1294                           sqp->header_buf, sqp->header_dma);
1295
1296         return err;
1297 }
1298
1299 void mthca_free_qp(struct mthca_dev *dev,
1300                    struct mthca_qp *qp)
1301 {
1302         u8 status;
1303         struct mthca_cq *send_cq;
1304         struct mthca_cq *recv_cq;
1305
1306         send_cq = to_mcq(qp->ibqp.send_cq);
1307         recv_cq = to_mcq(qp->ibqp.recv_cq);
1308
1309         /*
1310          * Lock CQs here, so that CQ polling code can do QP lookup
1311          * without taking a lock.
1312          */
1313         spin_lock_irq(&send_cq->lock);
1314         if (send_cq != recv_cq)
1315                 spin_lock(&recv_cq->lock);
1316
1317         spin_lock(&dev->qp_table.lock);
1318         mthca_array_clear(&dev->qp_table.qp,
1319                           qp->qpn & (dev->limits.num_qps - 1));
1320         spin_unlock(&dev->qp_table.lock);
1321
1322         if (send_cq != recv_cq)
1323                 spin_unlock(&recv_cq->lock);
1324         spin_unlock_irq(&send_cq->lock);
1325
1326         atomic_dec(&qp->refcount);
1327         wait_event(qp->wait, !atomic_read(&qp->refcount));
1328
1329         if (qp->state != IB_QPS_RESET)
1330                 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1331                                 NULL, 0, &status);
1332
1333         /*
1334          * If this is a userspace QP, the buffers, MR, CQs and so on
1335          * will be cleaned up in userspace, so all we have to do is
1336          * unref the mem-free tables and free the QPN in our table.
1337          */
1338         if (!qp->ibqp.uobject) {
1339                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
1340                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1341                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1342                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
1343                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1344
1345                 mthca_free_memfree(dev, qp);
1346                 mthca_free_wqe_buf(dev, qp);
1347         }
1348
1349         mthca_unmap_memfree(dev, qp);
1350
1351         if (is_sqp(dev, qp)) {
1352                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1353                 dma_free_coherent(&dev->pdev->dev,
1354                                   to_msqp(qp)->header_buf_size,
1355                                   to_msqp(qp)->header_buf,
1356                                   to_msqp(qp)->header_dma);
1357         } else
1358                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1359 }
1360
1361 /* Create UD header for an MLX send and build a data segment for it */
1362 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1363                             int ind, struct ib_send_wr *wr,
1364                             struct mthca_mlx_seg *mlx,
1365                             struct mthca_data_seg *data)
1366 {
1367         int header_size;
1368         int err;
1369         u16 pkey;
1370
1371         ib_ud_header_init(256, /* assume a MAD */
1372                           mthca_ah_grh_present(to_mah(wr->wr.ud.ah)),
1373                           &sqp->ud_header);
1374
1375         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1376         if (err)
1377                 return err;
1378         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1379         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1380                                   (sqp->ud_header.lrh.destination_lid ==
1381                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1382                                   (sqp->ud_header.lrh.service_level << 8));
1383         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1384         mlx->vcrc = 0;
1385
1386         switch (wr->opcode) {
1387         case IB_WR_SEND:
1388                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1389                 sqp->ud_header.immediate_present = 0;
1390                 break;
1391         case IB_WR_SEND_WITH_IMM:
1392                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1393                 sqp->ud_header.immediate_present = 1;
1394                 sqp->ud_header.immediate_data = wr->imm_data;
1395                 break;
1396         default:
1397                 return -EINVAL;
1398         }
1399
1400         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1401         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1402                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1403         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1404         if (!sqp->qp.ibqp.qp_num)
1405                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1406                                    sqp->pkey_index, &pkey);
1407         else
1408                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1409                                    wr->wr.ud.pkey_index, &pkey);
1410         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1411         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1412         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1413         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1414                                                sqp->qkey : wr->wr.ud.remote_qkey);
1415         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1416
1417         header_size = ib_ud_header_pack(&sqp->ud_header,
1418                                         sqp->header_buf +
1419                                         ind * MTHCA_UD_HEADER_SIZE);
1420
1421         data->byte_count = cpu_to_be32(header_size);
1422         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1423         data->addr       = cpu_to_be64(sqp->header_dma +
1424                                        ind * MTHCA_UD_HEADER_SIZE);
1425
1426         return 0;
1427 }
1428
1429 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1430                                     struct ib_cq *ib_cq)
1431 {
1432         unsigned cur;
1433         struct mthca_cq *cq;
1434
1435         cur = wq->head - wq->tail;
1436         if (likely(cur + nreq < wq->max))
1437                 return 0;
1438
1439         cq = to_mcq(ib_cq);
1440         spin_lock(&cq->lock);
1441         cur = wq->head - wq->tail;
1442         spin_unlock(&cq->lock);
1443
1444         return cur + nreq >= wq->max;
1445 }
1446
1447 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1448                           struct ib_send_wr **bad_wr)
1449 {
1450         struct mthca_dev *dev = to_mdev(ibqp->device);
1451         struct mthca_qp *qp = to_mqp(ibqp);
1452         void *wqe;
1453         void *prev_wqe;
1454         unsigned long flags;
1455         int err = 0;
1456         int nreq;
1457         int i;
1458         int size;
1459         int size0 = 0;
1460         u32 f0 = 0;
1461         int ind;
1462         u8 op0 = 0;
1463
1464         spin_lock_irqsave(&qp->sq.lock, flags);
1465
1466         /* XXX check that state is OK to post send */
1467
1468         ind = qp->sq.next_ind;
1469
1470         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1471                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1472                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1473                                         " %d max, %d nreq)\n", qp->qpn,
1474                                         qp->sq.head, qp->sq.tail,
1475                                         qp->sq.max, nreq);
1476                         err = -ENOMEM;
1477                         *bad_wr = wr;
1478                         goto out;
1479                 }
1480
1481                 wqe = get_send_wqe(qp, ind);
1482                 prev_wqe = qp->sq.last;
1483                 qp->sq.last = wqe;
1484
1485                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1486                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1487                 ((struct mthca_next_seg *) wqe)->flags =
1488                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1489                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1490                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1491                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1492                         cpu_to_be32(1);
1493                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1494                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1495                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1496
1497                 wqe += sizeof (struct mthca_next_seg);
1498                 size = sizeof (struct mthca_next_seg) / 16;
1499
1500                 switch (qp->transport) {
1501                 case RC:
1502                         switch (wr->opcode) {
1503                         case IB_WR_ATOMIC_CMP_AND_SWP:
1504                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1505                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1506                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1507                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1508                                         cpu_to_be32(wr->wr.atomic.rkey);
1509                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1510
1511                                 wqe += sizeof (struct mthca_raddr_seg);
1512
1513                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1514                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1515                                                 cpu_to_be64(wr->wr.atomic.swap);
1516                                         ((struct mthca_atomic_seg *) wqe)->compare =
1517                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1518                                 } else {
1519                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1520                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1521                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1522                                 }
1523
1524                                 wqe += sizeof (struct mthca_atomic_seg);
1525                                 size += (sizeof (struct mthca_raddr_seg) +
1526                                          sizeof (struct mthca_atomic_seg)) / 16;
1527                                 break;
1528
1529                         case IB_WR_RDMA_WRITE:
1530                         case IB_WR_RDMA_WRITE_WITH_IMM:
1531                         case IB_WR_RDMA_READ:
1532                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1533                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1534                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1535                                         cpu_to_be32(wr->wr.rdma.rkey);
1536                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1537                                 wqe += sizeof (struct mthca_raddr_seg);
1538                                 size += sizeof (struct mthca_raddr_seg) / 16;
1539                                 break;
1540
1541                         default:
1542                                 /* No extra segments required for sends */
1543                                 break;
1544                         }
1545
1546                         break;
1547
1548                 case UC:
1549                         switch (wr->opcode) {
1550                         case IB_WR_RDMA_WRITE:
1551                         case IB_WR_RDMA_WRITE_WITH_IMM:
1552                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1553                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1554                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1555                                         cpu_to_be32(wr->wr.rdma.rkey);
1556                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1557                                 wqe += sizeof (struct mthca_raddr_seg);
1558                                 size += sizeof (struct mthca_raddr_seg) / 16;
1559                                 break;
1560
1561                         default:
1562                                 /* No extra segments required for sends */
1563                                 break;
1564                         }
1565
1566                         break;
1567
1568                 case UD:
1569                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1570                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1571                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1572                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1573                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1574                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1575                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1576                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1577
1578                         wqe += sizeof (struct mthca_tavor_ud_seg);
1579                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1580                         break;
1581
1582                 case MLX:
1583                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1584                                                wqe - sizeof (struct mthca_next_seg),
1585                                                wqe);
1586                         if (err) {
1587                                 *bad_wr = wr;
1588                                 goto out;
1589                         }
1590                         wqe += sizeof (struct mthca_data_seg);
1591                         size += sizeof (struct mthca_data_seg) / 16;
1592                         break;
1593                 }
1594
1595                 if (wr->num_sge > qp->sq.max_gs) {
1596                         mthca_err(dev, "too many gathers\n");
1597                         err = -EINVAL;
1598                         *bad_wr = wr;
1599                         goto out;
1600                 }
1601
1602                 for (i = 0; i < wr->num_sge; ++i) {
1603                         ((struct mthca_data_seg *) wqe)->byte_count =
1604                                 cpu_to_be32(wr->sg_list[i].length);
1605                         ((struct mthca_data_seg *) wqe)->lkey =
1606                                 cpu_to_be32(wr->sg_list[i].lkey);
1607                         ((struct mthca_data_seg *) wqe)->addr =
1608                                 cpu_to_be64(wr->sg_list[i].addr);
1609                         wqe += sizeof (struct mthca_data_seg);
1610                         size += sizeof (struct mthca_data_seg) / 16;
1611                 }
1612
1613                 /* Add one more inline data segment for ICRC */
1614                 if (qp->transport == MLX) {
1615                         ((struct mthca_data_seg *) wqe)->byte_count =
1616                                 cpu_to_be32((1 << 31) | 4);
1617                         ((u32 *) wqe)[1] = 0;
1618                         wqe += sizeof (struct mthca_data_seg);
1619                         size += sizeof (struct mthca_data_seg) / 16;
1620                 }
1621
1622                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1623
1624                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1625                         mthca_err(dev, "opcode invalid\n");
1626                         err = -EINVAL;
1627                         *bad_wr = wr;
1628                         goto out;
1629                 }
1630
1631                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1632                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1633                                      qp->send_wqe_offset) |
1634                                     mthca_opcode[wr->opcode]);
1635                 wmb();
1636                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1637                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size |
1638                                     ((wr->send_flags & IB_SEND_FENCE) ?
1639                                     MTHCA_NEXT_FENCE : 0));
1640
1641                 if (!size0) {
1642                         size0 = size;
1643                         op0   = mthca_opcode[wr->opcode];
1644                 }
1645
1646                 ++ind;
1647                 if (unlikely(ind >= qp->sq.max))
1648                         ind -= qp->sq.max;
1649         }
1650
1651 out:
1652         if (likely(nreq)) {
1653                 __be32 doorbell[2];
1654
1655                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1656                                            qp->send_wqe_offset) | f0 | op0);
1657                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1658
1659                 wmb();
1660
1661                 mthca_write64(doorbell,
1662                               dev->kar + MTHCA_SEND_DOORBELL,
1663                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1664         }
1665
1666         qp->sq.next_ind = ind;
1667         qp->sq.head    += nreq;
1668
1669         spin_unlock_irqrestore(&qp->sq.lock, flags);
1670         return err;
1671 }
1672
1673 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1674                              struct ib_recv_wr **bad_wr)
1675 {
1676         struct mthca_dev *dev = to_mdev(ibqp->device);
1677         struct mthca_qp *qp = to_mqp(ibqp);
1678         __be32 doorbell[2];
1679         unsigned long flags;
1680         int err = 0;
1681         int nreq;
1682         int i;
1683         int size;
1684         int size0 = 0;
1685         int ind;
1686         void *wqe;
1687         void *prev_wqe;
1688
1689         spin_lock_irqsave(&qp->rq.lock, flags);
1690
1691         /* XXX check that state is OK to post receive */
1692
1693         ind = qp->rq.next_ind;
1694
1695         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1696                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1697                         nreq = 0;
1698
1699                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1700                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1701
1702                         wmb();
1703
1704                         mthca_write64(doorbell,
1705                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1706                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1707
1708                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1709                         size0 = 0;
1710                 }
1711
1712                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1713                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1714                                         " %d max, %d nreq)\n", qp->qpn,
1715                                         qp->rq.head, qp->rq.tail,
1716                                         qp->rq.max, nreq);
1717                         err = -ENOMEM;
1718                         *bad_wr = wr;
1719                         goto out;
1720                 }
1721
1722                 wqe = get_recv_wqe(qp, ind);
1723                 prev_wqe = qp->rq.last;
1724                 qp->rq.last = wqe;
1725
1726                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1727                 ((struct mthca_next_seg *) wqe)->ee_nds =
1728                         cpu_to_be32(MTHCA_NEXT_DBD);
1729                 ((struct mthca_next_seg *) wqe)->flags = 0;
1730
1731                 wqe += sizeof (struct mthca_next_seg);
1732                 size = sizeof (struct mthca_next_seg) / 16;
1733
1734                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1735                         err = -EINVAL;
1736                         *bad_wr = wr;
1737                         goto out;
1738                 }
1739
1740                 for (i = 0; i < wr->num_sge; ++i) {
1741                         ((struct mthca_data_seg *) wqe)->byte_count =
1742                                 cpu_to_be32(wr->sg_list[i].length);
1743                         ((struct mthca_data_seg *) wqe)->lkey =
1744                                 cpu_to_be32(wr->sg_list[i].lkey);
1745                         ((struct mthca_data_seg *) wqe)->addr =
1746                                 cpu_to_be64(wr->sg_list[i].addr);
1747                         wqe += sizeof (struct mthca_data_seg);
1748                         size += sizeof (struct mthca_data_seg) / 16;
1749                 }
1750
1751                 qp->wrid[ind] = wr->wr_id;
1752
1753                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1754                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1755                 wmb();
1756                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1757                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1758
1759                 if (!size0)
1760                         size0 = size;
1761
1762                 ++ind;
1763                 if (unlikely(ind >= qp->rq.max))
1764                         ind -= qp->rq.max;
1765         }
1766
1767 out:
1768         if (likely(nreq)) {
1769                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1770                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1771
1772                 wmb();
1773
1774                 mthca_write64(doorbell,
1775                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1776                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1777         }
1778
1779         qp->rq.next_ind = ind;
1780         qp->rq.head    += nreq;
1781
1782         spin_unlock_irqrestore(&qp->rq.lock, flags);
1783         return err;
1784 }
1785
1786 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1787                           struct ib_send_wr **bad_wr)
1788 {
1789         struct mthca_dev *dev = to_mdev(ibqp->device);
1790         struct mthca_qp *qp = to_mqp(ibqp);
1791         __be32 doorbell[2];
1792         void *wqe;
1793         void *prev_wqe;
1794         unsigned long flags;
1795         int err = 0;
1796         int nreq;
1797         int i;
1798         int size;
1799         int size0 = 0;
1800         u32 f0 = 0;
1801         int ind;
1802         u8 op0 = 0;
1803
1804         spin_lock_irqsave(&qp->sq.lock, flags);
1805
1806         /* XXX check that state is OK to post send */
1807
1808         ind = qp->sq.head & (qp->sq.max - 1);
1809
1810         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1811                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1812                         nreq = 0;
1813
1814                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1815                                                   ((qp->sq.head & 0xffff) << 8) |
1816                                                   f0 | op0);
1817                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1818
1819                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1820                         size0 = 0;
1821
1822                         /*
1823                          * Make sure that descriptors are written before
1824                          * doorbell record.
1825                          */
1826                         wmb();
1827                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1828
1829                         /*
1830                          * Make sure doorbell record is written before we
1831                          * write MMIO send doorbell.
1832                          */
1833                         wmb();
1834                         mthca_write64(doorbell,
1835                                       dev->kar + MTHCA_SEND_DOORBELL,
1836                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1837                 }
1838
1839                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1840                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1841                                         " %d max, %d nreq)\n", qp->qpn,
1842                                         qp->sq.head, qp->sq.tail,
1843                                         qp->sq.max, nreq);
1844                         err = -ENOMEM;
1845                         *bad_wr = wr;
1846                         goto out;
1847                 }
1848
1849                 wqe = get_send_wqe(qp, ind);
1850                 prev_wqe = qp->sq.last;
1851                 qp->sq.last = wqe;
1852
1853                 ((struct mthca_next_seg *) wqe)->flags =
1854                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1855                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1856                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1857                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1858                         cpu_to_be32(1);
1859                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1860                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1861                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1862
1863                 wqe += sizeof (struct mthca_next_seg);
1864                 size = sizeof (struct mthca_next_seg) / 16;
1865
1866                 switch (qp->transport) {
1867                 case RC:
1868                         switch (wr->opcode) {
1869                         case IB_WR_ATOMIC_CMP_AND_SWP:
1870                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1871                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1872                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1873                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1874                                         cpu_to_be32(wr->wr.atomic.rkey);
1875                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1876
1877                                 wqe += sizeof (struct mthca_raddr_seg);
1878
1879                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1880                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1881                                                 cpu_to_be64(wr->wr.atomic.swap);
1882                                         ((struct mthca_atomic_seg *) wqe)->compare =
1883                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1884                                 } else {
1885                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1886                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1887                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1888                                 }
1889
1890                                 wqe += sizeof (struct mthca_atomic_seg);
1891                                 size += (sizeof (struct mthca_raddr_seg) +
1892                                          sizeof (struct mthca_atomic_seg)) / 16;
1893                                 break;
1894
1895                         case IB_WR_RDMA_READ:
1896                         case IB_WR_RDMA_WRITE:
1897                         case IB_WR_RDMA_WRITE_WITH_IMM:
1898                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1899                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1900                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1901                                         cpu_to_be32(wr->wr.rdma.rkey);
1902                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1903                                 wqe += sizeof (struct mthca_raddr_seg);
1904                                 size += sizeof (struct mthca_raddr_seg) / 16;
1905                                 break;
1906
1907                         default:
1908                                 /* No extra segments required for sends */
1909                                 break;
1910                         }
1911
1912                         break;
1913
1914                 case UC:
1915                         switch (wr->opcode) {
1916                         case IB_WR_RDMA_WRITE:
1917                         case IB_WR_RDMA_WRITE_WITH_IMM:
1918                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1919                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1920                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1921                                         cpu_to_be32(wr->wr.rdma.rkey);
1922                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1923                                 wqe += sizeof (struct mthca_raddr_seg);
1924                                 size += sizeof (struct mthca_raddr_seg) / 16;
1925                                 break;
1926
1927                         default:
1928                                 /* No extra segments required for sends */
1929                                 break;
1930                         }
1931
1932                         break;
1933
1934                 case UD:
1935                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1936                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1937                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1938                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1939                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1940                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1941
1942                         wqe += sizeof (struct mthca_arbel_ud_seg);
1943                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1944                         break;
1945
1946                 case MLX:
1947                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1948                                                wqe - sizeof (struct mthca_next_seg),
1949                                                wqe);
1950                         if (err) {
1951                                 *bad_wr = wr;
1952                                 goto out;
1953                         }
1954                         wqe += sizeof (struct mthca_data_seg);
1955                         size += sizeof (struct mthca_data_seg) / 16;
1956                         break;
1957                 }
1958
1959                 if (wr->num_sge > qp->sq.max_gs) {
1960                         mthca_err(dev, "too many gathers\n");
1961                         err = -EINVAL;
1962                         *bad_wr = wr;
1963                         goto out;
1964                 }
1965
1966                 for (i = 0; i < wr->num_sge; ++i) {
1967                         ((struct mthca_data_seg *) wqe)->byte_count =
1968                                 cpu_to_be32(wr->sg_list[i].length);
1969                         ((struct mthca_data_seg *) wqe)->lkey =
1970                                 cpu_to_be32(wr->sg_list[i].lkey);
1971                         ((struct mthca_data_seg *) wqe)->addr =
1972                                 cpu_to_be64(wr->sg_list[i].addr);
1973                         wqe += sizeof (struct mthca_data_seg);
1974                         size += sizeof (struct mthca_data_seg) / 16;
1975                 }
1976
1977                 /* Add one more inline data segment for ICRC */
1978                 if (qp->transport == MLX) {
1979                         ((struct mthca_data_seg *) wqe)->byte_count =
1980                                 cpu_to_be32((1 << 31) | 4);
1981                         ((u32 *) wqe)[1] = 0;
1982                         wqe += sizeof (struct mthca_data_seg);
1983                         size += sizeof (struct mthca_data_seg) / 16;
1984                 }
1985
1986                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1987
1988                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1989                         mthca_err(dev, "opcode invalid\n");
1990                         err = -EINVAL;
1991                         *bad_wr = wr;
1992                         goto out;
1993                 }
1994
1995                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1996                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1997                                      qp->send_wqe_offset) |
1998                                     mthca_opcode[wr->opcode]);
1999                 wmb();
2000                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2001                         cpu_to_be32(MTHCA_NEXT_DBD | size |
2002                                     ((wr->send_flags & IB_SEND_FENCE) ?
2003                                     MTHCA_NEXT_FENCE : 0));
2004
2005                 if (!size0) {
2006                         size0 = size;
2007                         op0   = mthca_opcode[wr->opcode];
2008                 }
2009
2010                 ++ind;
2011                 if (unlikely(ind >= qp->sq.max))
2012                         ind -= qp->sq.max;
2013         }
2014
2015 out:
2016         if (likely(nreq)) {
2017                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2018                                           ((qp->sq.head & 0xffff) << 8) |
2019                                           f0 | op0);
2020                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2021
2022                 qp->sq.head += nreq;
2023
2024                 /*
2025                  * Make sure that descriptors are written before
2026                  * doorbell record.
2027                  */
2028                 wmb();
2029                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2030
2031                 /*
2032                  * Make sure doorbell record is written before we
2033                  * write MMIO send doorbell.
2034                  */
2035                 wmb();
2036                 mthca_write64(doorbell,
2037                               dev->kar + MTHCA_SEND_DOORBELL,
2038                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2039         }
2040
2041         spin_unlock_irqrestore(&qp->sq.lock, flags);
2042         return err;
2043 }
2044
2045 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2046                              struct ib_recv_wr **bad_wr)
2047 {
2048         struct mthca_dev *dev = to_mdev(ibqp->device);
2049         struct mthca_qp *qp = to_mqp(ibqp);
2050         unsigned long flags;
2051         int err = 0;
2052         int nreq;
2053         int ind;
2054         int i;
2055         void *wqe;
2056
2057         spin_lock_irqsave(&qp->rq.lock, flags);
2058
2059         /* XXX check that state is OK to post receive */
2060
2061         ind = qp->rq.head & (qp->rq.max - 1);
2062
2063         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2064                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2065                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2066                                         " %d max, %d nreq)\n", qp->qpn,
2067                                         qp->rq.head, qp->rq.tail,
2068                                         qp->rq.max, nreq);
2069                         err = -ENOMEM;
2070                         *bad_wr = wr;
2071                         goto out;
2072                 }
2073
2074                 wqe = get_recv_wqe(qp, ind);
2075
2076                 ((struct mthca_next_seg *) wqe)->flags = 0;
2077
2078                 wqe += sizeof (struct mthca_next_seg);
2079
2080                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2081                         err = -EINVAL;
2082                         *bad_wr = wr;
2083                         goto out;
2084                 }
2085
2086                 for (i = 0; i < wr->num_sge; ++i) {
2087                         ((struct mthca_data_seg *) wqe)->byte_count =
2088                                 cpu_to_be32(wr->sg_list[i].length);
2089                         ((struct mthca_data_seg *) wqe)->lkey =
2090                                 cpu_to_be32(wr->sg_list[i].lkey);
2091                         ((struct mthca_data_seg *) wqe)->addr =
2092                                 cpu_to_be64(wr->sg_list[i].addr);
2093                         wqe += sizeof (struct mthca_data_seg);
2094                 }
2095
2096                 if (i < qp->rq.max_gs) {
2097                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2098                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2099                         ((struct mthca_data_seg *) wqe)->addr = 0;
2100                 }
2101
2102                 qp->wrid[ind] = wr->wr_id;
2103
2104                 ++ind;
2105                 if (unlikely(ind >= qp->rq.max))
2106                         ind -= qp->rq.max;
2107         }
2108 out:
2109         if (likely(nreq)) {
2110                 qp->rq.head += nreq;
2111
2112                 /*
2113                  * Make sure that descriptors are written before
2114                  * doorbell record.
2115                  */
2116                 wmb();
2117                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2118         }
2119
2120         spin_unlock_irqrestore(&qp->rq.lock, flags);
2121         return err;
2122 }
2123
2124 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2125                         int index, int *dbd, __be32 *new_wqe)
2126 {
2127         struct mthca_next_seg *next;
2128
2129         /*
2130          * For SRQs, all WQEs generate a CQE, so we're always at the
2131          * end of the doorbell chain.
2132          */
2133         if (qp->ibqp.srq) {
2134                 *new_wqe = 0;
2135                 return;
2136         }
2137
2138         if (is_send)
2139                 next = get_send_wqe(qp, index);
2140         else
2141                 next = get_recv_wqe(qp, index);
2142
2143         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2144         if (next->ee_nds & cpu_to_be32(0x3f))
2145                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2146                         (next->ee_nds & cpu_to_be32(0x3f));
2147         else
2148                 *new_wqe = 0;
2149 }
2150
2151 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2152 {
2153         int err;
2154         u8 status;
2155         int i;
2156
2157         spin_lock_init(&dev->qp_table.lock);
2158
2159         /*
2160          * We reserve 2 extra QPs per port for the special QPs.  The
2161          * special QP for port 1 has to be even, so round up.
2162          */
2163         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2164         err = mthca_alloc_init(&dev->qp_table.alloc,
2165                                dev->limits.num_qps,
2166                                (1 << 24) - 1,
2167                                dev->qp_table.sqp_start +
2168                                MTHCA_MAX_PORTS * 2);
2169         if (err)
2170                 return err;
2171
2172         err = mthca_array_init(&dev->qp_table.qp,
2173                                dev->limits.num_qps);
2174         if (err) {
2175                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2176                 return err;
2177         }
2178
2179         for (i = 0; i < 2; ++i) {
2180                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2181                                             dev->qp_table.sqp_start + i * 2,
2182                                             &status);
2183                 if (err)
2184                         goto err_out;
2185                 if (status) {
2186                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2187                                    "status %02x, aborting.\n",
2188                                    status);
2189                         err = -EINVAL;
2190                         goto err_out;
2191                 }
2192         }
2193         return 0;
2194
2195  err_out:
2196         for (i = 0; i < 2; ++i)
2197                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2198
2199         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2200         mthca_alloc_cleanup(&dev->qp_table.alloc);
2201
2202         return err;
2203 }
2204
2205 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2206 {
2207         int i;
2208         u8 status;
2209
2210         for (i = 0; i < 2; ++i)
2211                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2212
2213         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2214         mthca_alloc_cleanup(&dev->qp_table.alloc);
2215 }