2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/sched.h>
38 #include <rdma/ib_verbs.h>
39 #include <rdma/ib_smi.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/srq.h>
44 #include <linux/types.h>
45 #include <linux/mlx5/transobj.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/mlx5-abi.h>
48 #include <rdma/uverbs_ioctl.h>
49 #include <rdma/mlx5_user_ioctl_cmds.h>
51 #define mlx5_ib_dbg(dev, format, arg...) \
52 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
53 __LINE__, current->pid, ##arg)
55 #define mlx5_ib_err(dev, format, arg...) \
56 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
57 __LINE__, current->pid, ##arg)
59 #define mlx5_ib_warn(dev, format, arg...) \
60 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
61 __LINE__, current->pid, ##arg)
63 #define field_avail(type, fld, sz) (offsetof(type, fld) + \
64 sizeof(((type *)0)->fld) <= (sz))
65 #define MLX5_IB_DEFAULT_UIDX 0xffffff
66 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
68 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size)
71 MLX5_IB_MMAP_CMD_SHIFT = 8,
72 MLX5_IB_MMAP_CMD_MASK = 0xff,
76 MLX5_RES_SCAT_DATA32_CQE = 0x1,
77 MLX5_RES_SCAT_DATA64_CQE = 0x2,
78 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
79 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
82 enum mlx5_ib_mad_ifc_flags {
83 MLX5_MAD_IFC_IGNORE_MKEY = 1,
84 MLX5_MAD_IFC_IGNORE_BKEY = 2,
85 MLX5_MAD_IFC_NET_VIEW = 4,
89 MLX5_CROSS_CHANNEL_BFREG = 0,
98 MLX5_TM_MAX_RNDV_MSG_SIZE = 64,
103 MLX5_IB_INVALID_UAR_INDEX = BIT(31),
104 MLX5_IB_INVALID_BFREG = BIT(31),
108 MLX5_MAX_MEMIC_PAGES = 0x100,
109 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
113 MLX5_MEMIC_BASE_ALIGN = 6,
114 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN,
117 struct mlx5_ib_vma_private_data {
118 struct list_head list;
119 struct vm_area_struct *vma;
120 /* protect vma_private_list add/del */
121 struct mutex *vma_private_list_mutex;
124 struct mlx5_ib_ucontext {
125 struct ib_ucontext ibucontext;
126 struct list_head db_page_list;
128 /* protect doorbell record alloc/free
130 struct mutex db_page_mutex;
131 struct mlx5_bfreg_info bfregi;
133 /* Transport Domain number */
135 struct list_head vma_private_list;
136 /* protect vma_private_list add/del */
137 struct mutex vma_private_list_mutex;
140 DECLARE_BITMAP(dm_pages, MLX5_MAX_MEMIC_PAGES);
144 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
146 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
155 MLX5_IB_FLOW_ACTION_MODIFY_HEADER,
156 MLX5_IB_FLOW_ACTION_DECAP,
159 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
160 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
161 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
162 #error "Invalid number of bypass priorities"
164 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
166 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
167 #define MLX5_IB_NUM_SNIFFER_FTS 2
168 #define MLX5_IB_NUM_EGRESS_FTS 1
169 struct mlx5_ib_flow_prio {
170 struct mlx5_flow_table *flow_table;
171 unsigned int refcount;
174 struct mlx5_ib_flow_handler {
175 struct list_head list;
176 struct ib_flow ibflow;
177 struct mlx5_ib_flow_prio *prio;
178 struct mlx5_flow_handle *rule;
179 struct ib_counters *ibcounters;
180 struct mlx5_ib_dev *dev;
181 struct mlx5_ib_flow_matcher *flow_matcher;
184 struct mlx5_ib_flow_matcher {
185 struct mlx5_ib_match_params matcher_mask;
187 enum mlx5_ib_flow_type flow_type;
189 struct mlx5_core_dev *mdev;
191 u8 match_criteria_enable;
194 struct mlx5_ib_flow_db {
195 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
196 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
197 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS];
198 struct mlx5_flow_table *lag_demux_ft;
199 /* Protect flow steering bypass flow tables
200 * when add/del flow rules.
201 * only single add/removal of flow steering rule could be done
207 /* Use macros here so that don't have to duplicate
208 * enum ib_send_flags and enum ib_qp_type for low-level driver
211 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0)
212 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1)
213 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2)
214 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3)
215 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4)
216 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END
218 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
220 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
221 * creates the actual hardware QP.
223 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
224 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3
225 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4
226 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
228 #define MLX5_IB_UMR_OCTOWORD 16
229 #define MLX5_IB_UMR_XLT_ALIGNMENT 64
231 #define MLX5_IB_UPD_XLT_ZAP BIT(0)
232 #define MLX5_IB_UPD_XLT_ENABLE BIT(1)
233 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
234 #define MLX5_IB_UPD_XLT_ADDR BIT(3)
235 #define MLX5_IB_UPD_XLT_PD BIT(4)
236 #define MLX5_IB_UPD_XLT_ACCESS BIT(5)
237 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
239 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
241 * These flags are intended for internal use by the mlx5_ib driver, and they
242 * rely on the range reserved for that use in the ib_qp_create_flags enum.
245 /* Create a UD QP whose source QP number is 1 */
246 static inline enum ib_qp_create_flags mlx5_ib_create_qp_sqpn_qp1(void)
248 return IB_QP_CREATE_RESERVED_START;
256 enum mlx5_ib_rq_flags {
257 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0,
258 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1,
264 struct wr_list *w_list;
268 /* serialize post to the work queue
283 enum mlx5_ib_wq_flags {
284 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
285 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
288 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
289 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
290 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
291 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
295 struct mlx5_core_qp core_qp;
302 u32 two_byte_shift_en;
303 u32 single_stride_log_num_of_bytes;
304 struct ib_umem *umem;
306 unsigned int page_shift;
313 u32 create_flags; /* Use enum mlx5_ib_wq_flags */
327 struct mlx5_ib_rwq_ind_table {
328 struct ib_rwq_ind_table ib_rwq_ind_tbl;
332 struct mlx5_ib_ubuffer {
333 struct ib_umem *umem;
338 struct mlx5_ib_qp_base {
339 struct mlx5_ib_qp *container_mibqp;
340 struct mlx5_core_qp mqp;
341 struct mlx5_ib_ubuffer ubuffer;
344 struct mlx5_ib_qp_trans {
345 struct mlx5_ib_qp_base base;
352 struct mlx5_ib_rss_qp {
357 struct mlx5_ib_qp_base base;
358 struct mlx5_ib_wq *rq;
359 struct mlx5_ib_ubuffer ubuffer;
360 struct mlx5_db *doorbell;
367 struct mlx5_ib_qp_base base;
368 struct mlx5_ib_wq *sq;
369 struct mlx5_ib_ubuffer ubuffer;
370 struct mlx5_db *doorbell;
371 struct mlx5_flow_handle *flow_rule;
376 struct mlx5_ib_raw_packet_qp {
377 struct mlx5_ib_sq sq;
378 struct mlx5_ib_rq rq;
383 unsigned long offset;
384 struct mlx5_sq_bfreg *bfreg;
388 struct mlx5_core_dct mdct;
395 struct mlx5_ib_qp_trans trans_qp;
396 struct mlx5_ib_raw_packet_qp raw_packet_qp;
397 struct mlx5_ib_rss_qp rss_qp;
398 struct mlx5_ib_dct dct;
400 struct mlx5_frag_buf buf;
403 struct mlx5_ib_wq rq;
407 struct mlx5_ib_wq sq;
409 /* serialize qp state modifications
421 /* only for user space QPs. For kernel
422 * we have it from the bf object
428 /* Store signature errors */
431 struct list_head qps_list;
432 struct list_head cq_recv_list;
433 struct list_head cq_send_list;
434 struct mlx5_rate_limit rl;
436 bool tunnel_offload_en;
437 /* storage for qp sub type when core qp type is IB_QPT_DRIVER */
438 enum ib_qp_type qp_sub_type;
441 struct mlx5_ib_cq_buf {
442 struct mlx5_frag_buf_ctrl fbc;
443 struct ib_umem *umem;
448 enum mlx5_ib_qp_flags {
449 MLX5_IB_QP_LSO = IB_QP_CREATE_IPOIB_UD_LSO,
450 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK = IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK,
451 MLX5_IB_QP_CROSS_CHANNEL = IB_QP_CREATE_CROSS_CHANNEL,
452 MLX5_IB_QP_MANAGED_SEND = IB_QP_CREATE_MANAGED_SEND,
453 MLX5_IB_QP_MANAGED_RECV = IB_QP_CREATE_MANAGED_RECV,
454 MLX5_IB_QP_SIGNATURE_HANDLING = 1 << 5,
455 /* QP uses 1 as its source QP number */
456 MLX5_IB_QP_SQPN_QP1 = 1 << 6,
457 MLX5_IB_QP_CAP_SCATTER_FCS = 1 << 7,
458 MLX5_IB_QP_RSS = 1 << 8,
459 MLX5_IB_QP_CVLAN_STRIPPING = 1 << 9,
460 MLX5_IB_QP_UNDERLAY = 1 << 10,
461 MLX5_IB_QP_PCI_WRITE_END_PADDING = 1 << 11,
462 MLX5_IB_QP_TUNNEL_OFFLOAD = 1 << 12,
466 struct ib_send_wr wr;
470 unsigned int page_shift;
471 unsigned int xlt_size;
477 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr)
479 return container_of(wr, struct mlx5_umr_wr, wr);
482 struct mlx5_shared_mr_info {
484 struct ib_umem *umem;
487 enum mlx5_ib_cq_pr_flags {
488 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0,
493 struct mlx5_core_cq mcq;
494 struct mlx5_ib_cq_buf buf;
497 /* serialize access to the CQ
503 struct mutex resize_mutex;
504 struct mlx5_ib_cq_buf *resize_buf;
505 struct ib_umem *resize_umem;
507 struct list_head list_send_qp;
508 struct list_head list_recv_qp;
510 struct list_head wc_list;
511 enum ib_cq_notify_flags notify_flags;
512 struct work_struct notify_work;
513 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */
518 struct list_head list;
523 struct mlx5_core_srq msrq;
524 struct mlx5_frag_buf buf;
527 /* protect SRQ hanlding
533 struct ib_umem *umem;
534 /* serialize arming a SRQ
540 struct mlx5_ib_xrcd {
541 struct ib_xrcd ibxrcd;
545 enum mlx5_ib_mtt_access_flags {
546 MLX5_IB_MTT_READ = (1 << 0),
547 MLX5_IB_MTT_WRITE = (1 << 1),
552 phys_addr_t dev_addr;
555 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
557 #define MLX5_IB_DM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
558 IB_ACCESS_REMOTE_WRITE |\
559 IB_ACCESS_REMOTE_READ |\
560 IB_ACCESS_REMOTE_ATOMIC |\
571 struct mlx5_core_mkey mmkey;
572 struct ib_umem *umem;
573 struct mlx5_shared_mr_info *smr_info;
574 struct list_head list;
576 bool allocated_from_cache;
578 struct mlx5_ib_dev *dev;
579 u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
580 struct mlx5_core_sig_ctx *sig;
583 int access_flags; /* Needed for rereg MR */
585 struct mlx5_ib_mr *parent;
586 atomic_t num_leaf_free;
587 wait_queue_head_t q_leaf_free;
592 struct mlx5_core_mkey mmkey;
596 struct mlx5_ib_umr_context {
598 enum ib_wc_status status;
599 struct completion done;
606 /* control access to UMR QP
608 struct semaphore sem;
617 struct mlx5_cache_ent {
618 struct list_head head;
619 /* sync access to the cahce entry
636 struct dentry *fsize;
638 struct dentry *fmiss;
639 struct dentry *flimit;
641 struct mlx5_ib_dev *dev;
642 struct work_struct work;
643 struct delayed_work dwork;
645 struct completion compl;
648 struct mlx5_mr_cache {
649 struct workqueue_struct *wq;
650 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
653 unsigned long last_add;
656 struct mlx5_ib_gsi_qp;
658 struct mlx5_ib_port_resources {
659 struct mlx5_ib_resources *devr;
660 struct mlx5_ib_gsi_qp *gsi;
661 struct work_struct pkey_change_work;
664 struct mlx5_ib_resources {
671 struct mlx5_ib_port_resources ports[2];
672 /* Protects changes to the port resources */
676 struct mlx5_ib_counters {
680 u32 num_cong_counters;
681 u32 num_ext_ppcnt_counters;
686 struct mlx5_ib_multiport_info;
688 struct mlx5_ib_multiport {
689 struct mlx5_ib_multiport_info *mpi;
690 /* To be held when accessing the multiport info */
694 struct mlx5_ib_port {
695 struct mlx5_ib_counters cnts;
696 struct mlx5_ib_multiport mp;
697 struct mlx5_ib_dbg_cc_params *dbg_cc_params;
701 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
704 rwlock_t netdev_lock;
705 struct net_device *netdev;
706 struct notifier_block nb;
708 enum ib_port_state last_port_state;
709 struct mlx5_ib_dev *dev;
713 struct mlx5_ib_dbg_param {
715 struct mlx5_ib_dev *dev;
716 struct dentry *dentry;
720 enum mlx5_ib_dbg_cc_types {
721 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE,
722 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI,
723 MLX5_IB_DBG_CC_RP_TIME_RESET,
724 MLX5_IB_DBG_CC_RP_BYTE_RESET,
725 MLX5_IB_DBG_CC_RP_THRESHOLD,
726 MLX5_IB_DBG_CC_RP_AI_RATE,
727 MLX5_IB_DBG_CC_RP_HAI_RATE,
728 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC,
729 MLX5_IB_DBG_CC_RP_MIN_RATE,
730 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP,
731 MLX5_IB_DBG_CC_RP_DCE_TCP_G,
732 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT,
733 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD,
734 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE,
735 MLX5_IB_DBG_CC_RP_GD,
736 MLX5_IB_DBG_CC_NP_CNP_DSCP,
737 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,
738 MLX5_IB_DBG_CC_NP_CNP_PRIO,
742 struct mlx5_ib_dbg_cc_params {
744 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX];
748 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100,
751 struct mlx5_ib_dbg_delay_drop {
752 struct dentry *dir_debugfs;
753 struct dentry *rqs_cnt_debugfs;
754 struct dentry *events_cnt_debugfs;
755 struct dentry *timeout_debugfs;
758 struct mlx5_ib_delay_drop {
759 struct mlx5_ib_dev *dev;
760 struct work_struct delay_drop_work;
761 /* serialize setting of delay drop */
767 struct mlx5_ib_dbg_delay_drop *dbg;
770 enum mlx5_ib_stages {
772 MLX5_IB_STAGE_FLOW_DB,
774 MLX5_IB_STAGE_NON_DEFAULT_CB,
776 MLX5_IB_STAGE_DEVICE_RESOURCES,
778 MLX5_IB_STAGE_COUNTERS,
779 MLX5_IB_STAGE_CONG_DEBUGFS,
782 MLX5_IB_STAGE_PRE_IB_REG_UMR,
784 MLX5_IB_STAGE_IB_REG,
785 MLX5_IB_STAGE_POST_IB_REG_UMR,
786 MLX5_IB_STAGE_DELAY_DROP,
787 MLX5_IB_STAGE_CLASS_ATTR,
788 MLX5_IB_STAGE_REP_REG,
792 struct mlx5_ib_stage {
793 int (*init)(struct mlx5_ib_dev *dev);
794 void (*cleanup)(struct mlx5_ib_dev *dev);
797 #define STAGE_CREATE(_stage, _init, _cleanup) \
798 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
800 struct mlx5_ib_profile {
801 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX];
804 struct mlx5_ib_multiport_info {
805 struct list_head list;
806 struct mlx5_ib_dev *ibdev;
807 struct mlx5_core_dev *mdev;
808 struct completion unref_comp;
815 struct mlx5_ib_flow_action {
816 struct ib_flow_action ib_action;
820 struct mlx5_accel_esp_xfrm *ctx;
823 struct mlx5_ib_dev *dev;
831 struct mlx5_core_dev *dev;
832 spinlock_t memic_lock;
833 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
836 struct mlx5_read_counters_attr {
837 struct mlx5_fc *hw_cntrs_hndl;
842 enum mlx5_ib_counters_type {
843 MLX5_IB_COUNTERS_FLOW,
846 struct mlx5_ib_mcounters {
847 struct ib_counters ibcntrs;
848 enum mlx5_ib_counters_type type;
849 /* number of counters supported for this counters type */
851 struct mlx5_fc *hw_cntrs_hndl;
852 /* read function for this counters type */
853 int (*read_counters)(struct ib_device *ibdev,
854 struct mlx5_read_counters_attr *read_attr);
855 /* max index set as part of create_flow */
857 /* number of counters data entries (<description,index> pair) */
859 /* counters data array for descriptions and indexes */
860 struct mlx5_ib_flow_counters_desc *counters_data;
861 /* protects access to mcounters internal data */
862 struct mutex mcntrs_mutex;
865 static inline struct mlx5_ib_mcounters *
866 to_mcounters(struct ib_counters *ibcntrs)
868 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs);
872 struct ib_device ib_dev;
873 const struct uverbs_object_tree_def *driver_trees[7];
874 struct mlx5_core_dev *mdev;
875 struct mlx5_roce roce[MLX5_MAX_PORTS];
877 /* serialize update of capability mask
879 struct mutex cap_mask_mutex;
881 struct umr_common umrc;
882 /* sync used page count stats
884 struct mlx5_ib_resources devr;
885 struct mlx5_mr_cache cache;
886 struct timer_list delay_timer;
887 /* Prevents soft lock on massive reg MRs */
888 struct mutex slow_path_mutex;
890 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
891 struct ib_odp_caps odp_caps;
894 * Sleepable RCU that prevents destruction of MRs while they are still
895 * being used by a page fault handler.
897 struct srcu_struct mr_srcu;
900 struct mlx5_ib_flow_db *flow_db;
901 /* protect resources needed as part of reset flow */
902 spinlock_t reset_flow_resource_lock;
903 struct list_head qp_list;
904 /* Array with num_ports elements */
905 struct mlx5_ib_port *port;
906 struct mlx5_sq_bfreg bfreg;
907 struct mlx5_sq_bfreg fp_bfreg;
908 struct mlx5_ib_delay_drop delay_drop;
909 const struct mlx5_ib_profile *profile;
910 struct mlx5_eswitch_rep *rep;
912 /* protect the user_td */
913 struct mutex lb_mutex;
916 struct list_head ib_dev_list;
918 struct mlx5_memic memic;
921 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
923 return container_of(mcq, struct mlx5_ib_cq, mcq);
926 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
928 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
931 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
933 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
936 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
938 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
941 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
943 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
946 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
948 return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
951 static inline struct mlx5_ib_mr *to_mibmr(struct mlx5_core_mkey *mmkey)
953 return container_of(mmkey, struct mlx5_ib_mr, mmkey);
956 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
958 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
961 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
963 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
966 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
968 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
971 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
973 return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
976 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
978 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
981 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
983 return container_of(msrq, struct mlx5_ib_srq, msrq);
986 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm)
988 return container_of(ibdm, struct mlx5_ib_dm, ibdm);
991 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
993 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
996 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
998 return container_of(ibmw, struct mlx5_ib_mw, ibmw);
1001 static inline struct mlx5_ib_flow_action *
1002 to_mflow_act(struct ib_flow_action *ibact)
1004 return container_of(ibact, struct mlx5_ib_flow_action, ib_action);
1007 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
1008 struct mlx5_db *db);
1009 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
1010 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1011 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1012 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
1013 int mlx5_MAD_IFC(struct mlx5_ib_dev *dev, int ignore_mkey, int ignore_bkey,
1014 u8 port, const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1015 const void *in_mad, void *response_mad);
1016 struct ib_ah *mlx5_ib_create_ah(struct ib_pd *pd, struct rdma_ah_attr *ah_attr,
1017 struct ib_udata *udata);
1018 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1019 int mlx5_ib_destroy_ah(struct ib_ah *ah);
1020 struct ib_srq *mlx5_ib_create_srq(struct ib_pd *pd,
1021 struct ib_srq_init_attr *init_attr,
1022 struct ib_udata *udata);
1023 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1024 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
1025 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
1026 int mlx5_ib_destroy_srq(struct ib_srq *srq);
1027 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
1028 const struct ib_recv_wr **bad_wr);
1029 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1030 struct ib_qp_init_attr *init_attr,
1031 struct ib_udata *udata);
1032 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1033 int attr_mask, struct ib_udata *udata);
1034 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1035 struct ib_qp_init_attr *qp_init_attr);
1036 int mlx5_ib_destroy_qp(struct ib_qp *qp);
1037 void mlx5_ib_drain_sq(struct ib_qp *qp);
1038 void mlx5_ib_drain_rq(struct ib_qp *qp);
1039 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
1040 const struct ib_send_wr **bad_wr);
1041 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
1042 const struct ib_recv_wr **bad_wr);
1043 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n);
1044 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
1045 void *buffer, u32 length,
1046 struct mlx5_ib_qp_base *base);
1047 struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
1048 const struct ib_cq_init_attr *attr,
1049 struct ib_ucontext *context,
1050 struct ib_udata *udata);
1051 int mlx5_ib_destroy_cq(struct ib_cq *cq);
1052 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1053 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1054 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
1055 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
1056 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
1057 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1058 u64 virt_addr, int access_flags,
1059 struct ib_udata *udata);
1060 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
1061 struct ib_udata *udata);
1062 int mlx5_ib_dealloc_mw(struct ib_mw *mw);
1063 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
1064 int page_shift, int flags);
1065 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
1067 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
1068 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1069 u64 length, u64 virt_addr, int access_flags,
1070 struct ib_pd *pd, struct ib_udata *udata);
1071 int mlx5_ib_dereg_mr(struct ib_mr *ibmr);
1072 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd,
1073 enum ib_mr_type mr_type,
1075 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1076 unsigned int *sg_offset);
1077 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
1078 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1079 const struct ib_mad_hdr *in, size_t in_mad_size,
1080 struct ib_mad_hdr *out, size_t *out_mad_size,
1081 u16 *out_mad_pkey_index);
1082 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
1083 struct ib_ucontext *context,
1084 struct ib_udata *udata);
1085 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd);
1086 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
1087 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
1088 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev,
1089 struct ib_smp *out_mad);
1090 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
1091 __be64 *sys_image_guid);
1092 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
1094 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
1096 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
1097 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
1098 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index,
1100 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index,
1102 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port,
1103 struct ib_port_attr *props);
1104 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1105 struct ib_port_attr *props);
1106 int mlx5_ib_init_fmr(struct mlx5_ib_dev *dev);
1107 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev *dev);
1108 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr,
1109 unsigned long max_page_shift,
1110 int *count, int *shift,
1111 int *ncont, int *order);
1112 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1113 int page_shift, size_t offset, size_t num_pages,
1114 __be64 *pas, int access_flags);
1115 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1116 int page_shift, __be64 *pas, int access_flags);
1117 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
1118 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq);
1119 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
1120 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
1122 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry);
1123 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
1124 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1125 struct ib_mr_status *mr_status);
1126 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
1127 struct ib_wq_init_attr *init_attr,
1128 struct ib_udata *udata);
1129 int mlx5_ib_destroy_wq(struct ib_wq *wq);
1130 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
1131 u32 wq_attr_mask, struct ib_udata *udata);
1132 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
1133 struct ib_rwq_ind_table_init_attr *init_attr,
1134 struct ib_udata *udata);
1135 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
1136 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev);
1137 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
1138 struct ib_ucontext *context,
1139 struct ib_dm_alloc_attr *attr,
1140 struct uverbs_attr_bundle *attrs);
1141 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm);
1142 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1143 struct ib_dm_mr_attr *attr,
1144 struct uverbs_attr_bundle *attrs);
1146 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1147 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev);
1148 void mlx5_ib_pfault(struct mlx5_core_dev *mdev, void *context,
1149 struct mlx5_pagefault *pfault);
1150 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
1151 int __init mlx5_ib_odp_init(void);
1152 void mlx5_ib_odp_cleanup(void);
1153 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start,
1155 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent);
1156 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
1157 size_t nentries, struct mlx5_ib_mr *mr, int flags);
1158 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1159 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
1164 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
1165 static inline int mlx5_ib_odp_init(void) { return 0; }
1166 static inline void mlx5_ib_odp_cleanup(void) {}
1167 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {}
1168 static inline void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
1169 size_t nentries, struct mlx5_ib_mr *mr,
1172 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1174 /* Needed for rep profile */
1175 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev);
1176 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev);
1177 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev);
1178 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev);
1179 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev);
1180 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev);
1181 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev);
1182 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev);
1183 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev);
1184 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev);
1185 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev);
1186 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev);
1187 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev);
1188 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev);
1189 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev);
1190 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev);
1191 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev);
1192 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev);
1193 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
1194 const struct mlx5_ib_profile *profile,
1196 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
1197 const struct mlx5_ib_profile *profile);
1199 int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
1200 u8 port, struct ifla_vf_info *info);
1201 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
1202 u8 port, int state);
1203 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
1204 u8 port, struct ifla_vf_stats *stats);
1205 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port,
1206 u64 guid, int type);
1208 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
1209 const struct ib_gid_attr *attr);
1211 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1212 int mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1214 /* GSI QP helper functions */
1215 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd,
1216 struct ib_qp_init_attr *init_attr);
1217 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp);
1218 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
1220 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
1222 struct ib_qp_init_attr *qp_init_attr);
1223 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr,
1224 const struct ib_send_wr **bad_wr);
1225 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr,
1226 const struct ib_recv_wr **bad_wr);
1227 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
1229 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
1231 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi,
1233 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi);
1234 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev,
1236 u8 *native_port_num);
1237 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev,
1240 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
1241 int mlx5_ib_devx_create(struct mlx5_ib_dev *dev,
1242 struct mlx5_ib_ucontext *context);
1243 void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev,
1244 struct mlx5_ib_ucontext *context);
1245 const struct uverbs_object_tree_def *mlx5_ib_get_devx_tree(void);
1246 struct mlx5_ib_flow_handler *mlx5_ib_raw_fs_rule_add(
1247 struct mlx5_ib_dev *dev, struct mlx5_ib_flow_matcher *fs_matcher,
1248 void *cmd_in, int inlen, int dest_id, int dest_type);
1249 bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id, int *dest_type);
1250 int mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def **root);
1251 void mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction);
1254 mlx5_ib_devx_create(struct mlx5_ib_dev *dev,
1255 struct mlx5_ib_ucontext *context) { return -EOPNOTSUPP; };
1256 static inline void mlx5_ib_devx_destroy(struct mlx5_ib_dev *dev,
1257 struct mlx5_ib_ucontext *context) {}
1258 static inline const struct uverbs_object_tree_def *
1259 mlx5_ib_get_devx_tree(void) { return NULL; }
1260 static inline bool mlx5_ib_devx_is_flow_dest(void *obj, int *dest_id,
1266 mlx5_ib_get_flow_trees(const struct uverbs_object_tree_def **root)
1271 mlx5_ib_destroy_flow_action_raw(struct mlx5_ib_flow_action *maction)
1276 static inline void init_query_mad(struct ib_smp *mad)
1278 mad->base_version = 1;
1279 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
1280 mad->class_version = 1;
1281 mad->method = IB_MGMT_METHOD_GET;
1284 static inline u8 convert_access(int acc)
1286 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
1287 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
1288 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
1289 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
1290 MLX5_PERM_LOCAL_READ;
1293 static inline int is_qp1(enum ib_qp_type qp_type)
1295 return qp_type == MLX5_IB_QPT_HW_GSI;
1298 #define MLX5_MAX_UMR_SHIFT 16
1299 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
1301 static inline u32 check_cq_create_flags(u32 flags)
1304 * It returns non-zero value for unsupported CQ
1305 * create flags, otherwise it returns zero.
1307 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN |
1308 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION));
1311 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1315 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1316 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1318 *user_index = cmd_uidx;
1320 *user_index = MLX5_IB_DEFAULT_UIDX;
1326 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1327 struct mlx5_ib_create_qp *ucmd,
1331 u8 cqe_version = ucontext->cqe_version;
1333 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) &&
1334 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1337 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) !=
1341 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1344 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1345 struct mlx5_ib_create_srq *ucmd,
1349 u8 cqe_version = ucontext->cqe_version;
1351 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) &&
1352 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1355 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) !=
1359 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1362 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
1364 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1365 MLX5_UARS_IN_PAGE : 1;
1368 static inline int get_num_static_uars(struct mlx5_ib_dev *dev,
1369 struct mlx5_bfreg_info *bfregi)
1371 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages;
1374 unsigned long mlx5_ib_get_xlt_emergency_page(void);
1375 void mlx5_ib_put_xlt_emergency_page(void);
1377 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1378 struct mlx5_bfreg_info *bfregi, u32 bfregn,
1380 #endif /* MLX5_IB_H */