drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/slab.h>
  36 #include <linux/netdevice.h>
  37
  38 #include <rdma/ib_cache.h>
  39 #include <rdma/ib_pack.h>
  40 #include <rdma/ib_addr.h>
  41 #include <rdma/ib_mad.h>
  42
  43 #include <linux/mlx4/driver.h>
  44 #include <linux/mlx4/qp.h>
  45
  46 #include "mlx4_ib.h"
  47 #include "user.h"
  48
  49 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
  50                              struct mlx4_ib_cq *recv_cq);
  51 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
  52                                struct mlx4_ib_cq *recv_cq);
  53
  54 enum {
  55         MLX4_IB_ACK_REQ_FREQ    = 8,
  56 };
  57
  58 enum {
  59         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  60         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  61         MLX4_IB_LINK_TYPE_IB            = 0,
  62         MLX4_IB_LINK_TYPE_ETH           = 1
  63 };
  64
  65 enum {
  66         /*
  67          * Largest possible UD header: send with GRH and immediate
  68          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  69          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  70          * biggest case)
  71          */
  72         MLX4_IB_UD_HEADER_SIZE          = 82,
  73         MLX4_IB_LSO_HEADER_SPARE        = 128,
  74 };
  75
  76 enum {
  77         MLX4_IB_IBOE_ETHERTYPE          = 0x8915
  78 };
  79
  80 struct mlx4_ib_sqp {
  81         struct mlx4_ib_qp       qp;
  82         int                     pkey_index;
  83         u32                     qkey;
  84         u32                     send_psn;
  85         struct ib_ud_header     ud_header;
  86         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  87 };
  88
  89 enum {
  90         MLX4_IB_MIN_SQ_STRIDE   = 6,
  91         MLX4_IB_CACHE_LINE_SIZE = 64,
  92 };
  93
  94 enum {
  95         MLX4_RAW_QP_MTU         = 7,
  96         MLX4_RAW_QP_MSGMAX      = 31,
  97 };
  98
  99 #ifndef ETH_ALEN
 100 #define ETH_ALEN        6
 101 #endif
 102
 103 static const __be32 mlx4_ib_opcode[] = {
 104         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
 105         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
 106         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
 107         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
 108         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
 109         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 110         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 111         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 112         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 113         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 114         [IB_WR_FAST_REG_MR]                     = cpu_to_be32(MLX4_OPCODE_FMR),
 115         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 116         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 117         [IB_WR_BIND_MW]                         = cpu_to_be32(MLX4_OPCODE_BIND_MW),
 118 };
 119
 120 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 121 {
 122         return container_of(mqp, struct mlx4_ib_sqp, qp);
 123 }
 124
 125 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 126 {
 127         if (!mlx4_is_master(dev->dev))
 128                 return 0;
 129
 130         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 131                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 132                 8 * MLX4_MFUNC_MAX;
 133 }
 134
 135 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 136 {
 137         int proxy_sqp = 0;
 138         int real_sqp = 0;
 139         int i;
 140         /* PPF or Native -- real SQP */
 141         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 142                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 143                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 144         if (real_sqp)
 145                 return 1;
 146         /* VF or PF -- proxy SQP */
 147         if (mlx4_is_mfunc(dev->dev)) {
 148                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 149                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
 150                             qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
 151                                 proxy_sqp = 1;
 152                                 break;
 153                         }
 154                 }
 155         }
 156         return proxy_sqp;
 157 }
 158
 159 /* used for INIT/CLOSE port logic */
 160 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 161 {
 162         int proxy_qp0 = 0;
 163         int real_qp0 = 0;
 164         int i;
 165         /* PPF or Native -- real QP0 */
 166         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 167                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 168                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 169         if (real_qp0)
 170                 return 1;
 171         /* VF or PF -- proxy QP0 */
 172         if (mlx4_is_mfunc(dev->dev)) {
 173                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 174                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
 175                                 proxy_qp0 = 1;
 176                                 break;
 177                         }
 178                 }
 179         }
 180         return proxy_qp0;
 181 }
 182
 183 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 184 {
 185         return mlx4_buf_offset(&qp->buf, offset);
 186 }
 187
 188 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 189 {
 190         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 191 }
 192
 193 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 194 {
 195         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 196 }
 197
 198 /*
 199  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 200  * first four bytes of every 64 byte chunk with
 201  *     0x7FFFFFF | (invalid_ownership_value << 31).
 202  *
 203  * When the max work request size is less than or equal to the WQE
 204  * basic block size, as an optimization, we can stamp all WQEs with
 205  * 0xffffffff, and skip the very first chunk of each WQE.
 206  */
 207 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 208 {
 209         __be32 *wqe;
 210         int i;
 211         int s;
 212         int ind;
 213         void *buf;
 214         __be32 stamp;
 215         struct mlx4_wqe_ctrl_seg *ctrl;
 216
 217         if (qp->sq_max_wqes_per_wr > 1) {
 218                 s = roundup(size, 1U << qp->sq.wqe_shift);
 219                 for (i = 0; i < s; i += 64) {
 220                         ind = (i >> qp->sq.wqe_shift) + n;
 221                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 222                                                        cpu_to_be32(0xffffffff);
 223                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 224                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 225                         *wqe = stamp;
 226                 }
 227         } else {
 228                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 229                 s = (ctrl->fence_size & 0x3f) << 4;
 230                 for (i = 64; i < s; i += 64) {
 231                         wqe = buf + i;
 232                         *wqe = cpu_to_be32(0xffffffff);
 233                 }
 234         }
 235 }
 236
 237 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 238 {
 239         struct mlx4_wqe_ctrl_seg *ctrl;
 240         struct mlx4_wqe_inline_seg *inl;
 241         void *wqe;
 242         int s;
 243
 244         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 245         s = sizeof(struct mlx4_wqe_ctrl_seg);
 246
 247         if (qp->ibqp.qp_type == IB_QPT_UD) {
 248                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 249                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 250                 memset(dgram, 0, sizeof *dgram);
 251                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 252                 s += sizeof(struct mlx4_wqe_datagram_seg);
 253         }
 254
 255         /* Pad the remainder of the WQE with an inline data segment. */
 256         if (size > s) {
 257                 inl = wqe + s;
 258                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 259         }
 260         ctrl->srcrb_flags = 0;
 261         ctrl->fence_size = size / 16;
 262         /*
 263          * Make sure descriptor is fully written before setting ownership bit
 264          * (because HW can start executing as soon as we do).
 265          */
 266         wmb();
 267
 268         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 269                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 270
 271         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 272 }
 273
 274 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 275 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 276 {
 277         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 278         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 279                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 280                 ind += s;
 281         }
 282         return ind;
 283 }
 284
 285 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 286 {
 287         struct ib_event event;
 288         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 289
 290         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 291                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 292
 293         if (ibqp->event_handler) {
 294                 event.device     = ibqp->device;
 295                 event.element.qp = ibqp;
 296                 switch (type) {
 297                 case MLX4_EVENT_TYPE_PATH_MIG:
 298                         event.event = IB_EVENT_PATH_MIG;
 299                         break;
 300                 case MLX4_EVENT_TYPE_COMM_EST:
 301                         event.event = IB_EVENT_COMM_EST;
 302                         break;
 303                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 304                         event.event = IB_EVENT_SQ_DRAINED;
 305                         break;
 306                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 307                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 308                         break;
 309                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 310                         event.event = IB_EVENT_QP_FATAL;
 311                         break;
 312                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 313                         event.event = IB_EVENT_PATH_MIG_ERR;
 314                         break;
 315                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 316                         event.event = IB_EVENT_QP_REQ_ERR;
 317                         break;
 318                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 319                         event.event = IB_EVENT_QP_ACCESS_ERR;
 320                         break;
 321                 default:
 322                         pr_warn("Unexpected event type %d "
 323                                "on QP %06x\n", type, qp->qpn);
 324                         return;
 325                 }
 326
 327                 ibqp->event_handler(&event, ibqp->qp_context);
 328         }
 329 }
 330
 331 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 332 {
 333         /*
 334          * UD WQEs must have a datagram segment.
 335          * RC and UC WQEs might have a remote address segment.
 336          * MLX WQEs need two extra inline data segments (for the UD
 337          * header and space for the ICRC).
 338          */
 339         switch (type) {
 340         case MLX4_IB_QPT_UD:
 341                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 342                         sizeof (struct mlx4_wqe_datagram_seg) +
 343                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 344         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 345         case MLX4_IB_QPT_PROXY_SMI:
 346         case MLX4_IB_QPT_PROXY_GSI:
 347                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 348                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 349         case MLX4_IB_QPT_TUN_SMI_OWNER:
 350         case MLX4_IB_QPT_TUN_GSI:
 351                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 352                         sizeof (struct mlx4_wqe_datagram_seg);
 353
 354         case MLX4_IB_QPT_UC:
 355                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 356                         sizeof (struct mlx4_wqe_raddr_seg);
 357         case MLX4_IB_QPT_RC:
 358                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 359                         sizeof (struct mlx4_wqe_atomic_seg) +
 360                         sizeof (struct mlx4_wqe_raddr_seg);
 361         case MLX4_IB_QPT_SMI:
 362         case MLX4_IB_QPT_GSI:
 363                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 364                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 365                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 366                                            MLX4_INLINE_ALIGN) *
 367                               sizeof (struct mlx4_wqe_inline_seg),
 368                               sizeof (struct mlx4_wqe_data_seg)) +
 369                         ALIGN(4 +
 370                               sizeof (struct mlx4_wqe_inline_seg),
 371                               sizeof (struct mlx4_wqe_data_seg));
 372         default:
 373                 return sizeof (struct mlx4_wqe_ctrl_seg);
 374         }
 375 }
 376
 377 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 378                        int is_user, int has_rq, struct mlx4_ib_qp *qp)
 379 {
 380         /* Sanity check RQ size before proceeding */
 381         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 382             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 383                 return -EINVAL;
 384
 385         if (!has_rq) {
 386                 if (cap->max_recv_wr)
 387                         return -EINVAL;
 388
 389                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 390         } else {
 391                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 392                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 393                         return -EINVAL;
 394
 395                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 396                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 397                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 398         }
 399
 400         /* leave userspace return values as they were, so as not to break ABI */
 401         if (is_user) {
 402                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 403                 cap->max_recv_sge = qp->rq.max_gs;
 404         } else {
 405                 cap->max_recv_wr  = qp->rq.max_post =
 406                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 407                 cap->max_recv_sge = min(qp->rq.max_gs,
 408                                         min(dev->dev->caps.max_sq_sg,
 409                                             dev->dev->caps.max_rq_sg));
 410         }
 411
 412         return 0;
 413 }
 414
 415 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 416                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
 417 {
 418         int s;
 419
 420         /* Sanity check SQ size before proceeding */
 421         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 422             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 423             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 424             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 425                 return -EINVAL;
 426
 427         /*
 428          * For MLX transport we need 2 extra S/G entries:
 429          * one for the header and one for the checksum at the end
 430          */
 431         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 432              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 433             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 434                 return -EINVAL;
 435
 436         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 437                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 438                 send_wqe_overhead(type, qp->flags);
 439
 440         if (s > dev->dev->caps.max_sq_desc_sz)
 441                 return -EINVAL;
 442
 443         /*
 444          * Hermon supports shrinking WQEs, such that a single work
 445          * request can include multiple units of 1 << wqe_shift.  This
 446          * way, work requests can differ in size, and do not have to
 447          * be a power of 2 in size, saving memory and speeding up send
 448          * WR posting.  Unfortunately, if we do this then the
 449          * wqe_index field in CQEs can't be used to look up the WR ID
 450          * anymore, so we do this only if selective signaling is off.
 451          *
 452          * Further, on 32-bit platforms, we can't use vmap() to make
 453          * the QP buffer virtually contiguous.  Thus we have to use
 454          * constant-sized WRs to make sure a WR is always fully within
 455          * a single page-sized chunk.
 456          *
 457          * Finally, we use NOP work requests to pad the end of the
 458          * work queue, to avoid wrap-around in the middle of WR.  We
 459          * set NEC bit to avoid getting completions with error for
 460          * these NOP WRs, but since NEC is only supported starting
 461          * with firmware 2.2.232, we use constant-sized WRs for older
 462          * firmware.
 463          *
 464          * And, since MLX QPs only support SEND, we use constant-sized
 465          * WRs in this case.
 466          *
 467          * We look for the smallest value of wqe_shift such that the
 468          * resulting number of wqes does not exceed device
 469          * capabilities.
 470          *
 471          * We set WQE size to at least 64 bytes, this way stamping
 472          * invalidates each WQE.
 473          */
 474         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 475             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 476             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
 477             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
 478                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
 479                 qp->sq.wqe_shift = ilog2(64);
 480         else
 481                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 482
 483         for (;;) {
 484                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 485
 486                 /*
 487                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 488                  * allow HW to prefetch.
 489                  */
 490                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 491                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 492                                                     qp->sq_max_wqes_per_wr +
 493                                                     qp->sq_spare_wqes);
 494
 495                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 496                         break;
 497
 498                 if (qp->sq_max_wqes_per_wr <= 1)
 499                         return -EINVAL;
 500
 501                 ++qp->sq.wqe_shift;
 502         }
 503
 504         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 505                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 506                          send_wqe_overhead(type, qp->flags)) /
 507                 sizeof (struct mlx4_wqe_data_seg);
 508
 509         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 510                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 511         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 512                 qp->rq.offset = 0;
 513                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 514         } else {
 515                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 516                 qp->sq.offset = 0;
 517         }
 518
 519         cap->max_send_wr  = qp->sq.max_post =
 520                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 521         cap->max_send_sge = min(qp->sq.max_gs,
 522                                 min(dev->dev->caps.max_sq_sg,
 523                                     dev->dev->caps.max_rq_sg));
 524         /* We don't support inline sends for kernel QPs (yet) */
 525         cap->max_inline_data = 0;
 526
 527         return 0;
 528 }
 529
 530 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 531                             struct mlx4_ib_qp *qp,
 532                             struct mlx4_ib_create_qp *ucmd)
 533 {
 534         /* Sanity check SQ size before proceeding */
 535         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 536             ucmd->log_sq_stride >
 537                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 538             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 539                 return -EINVAL;
 540
 541         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 542         qp->sq.wqe_shift = ucmd->log_sq_stride;
 543
 544         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 545                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 546
 547         return 0;
 548 }
 549
 550 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 551 {
 552         int i;
 553
 554         qp->sqp_proxy_rcv =
 555                 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
 556                         GFP_KERNEL);
 557         if (!qp->sqp_proxy_rcv)
 558                 return -ENOMEM;
 559         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 560                 qp->sqp_proxy_rcv[i].addr =
 561                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 562                                 GFP_KERNEL);
 563                 if (!qp->sqp_proxy_rcv[i].addr)
 564                         goto err;
 565                 qp->sqp_proxy_rcv[i].map =
 566                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 567                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 568                                           DMA_FROM_DEVICE);
 569                 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
 570                         kfree(qp->sqp_proxy_rcv[i].addr);
 571                         goto err;
 572                 }
 573         }
 574         return 0;
 575
 576 err:
 577         while (i > 0) {
 578                 --i;
 579                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 580                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 581                                     DMA_FROM_DEVICE);
 582                 kfree(qp->sqp_proxy_rcv[i].addr);
 583         }
 584         kfree(qp->sqp_proxy_rcv);
 585         qp->sqp_proxy_rcv = NULL;
 586         return -ENOMEM;
 587 }
 588
 589 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 590 {
 591         int i;
 592
 593         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 594                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 595                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 596                                     DMA_FROM_DEVICE);
 597                 kfree(qp->sqp_proxy_rcv[i].addr);
 598         }
 599         kfree(qp->sqp_proxy_rcv);
 600 }
 601
 602 static int qp_has_rq(struct ib_qp_init_attr *attr)
 603 {
 604         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 605                 return 0;
 606
 607         return !attr->srq;
 608 }
 609
 610 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
 611 {
 612         int i;
 613         for (i = 0; i < dev->caps.num_ports; i++) {
 614                 if (qpn == dev->caps.qp0_proxy[i])
 615                         return !!dev->caps.qp0_qkey[i];
 616         }
 617         return 0;
 618 }
 619
 620 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
 621                                     struct mlx4_ib_qp *qp)
 622 {
 623         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
 624         mlx4_counter_free(dev->dev, qp->counter_index->index);
 625         list_del(&qp->counter_index->list);
 626         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
 627
 628         kfree(qp->counter_index);
 629         qp->counter_index = NULL;
 630 }
 631
 632 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 633                             struct ib_qp_init_attr *init_attr,
 634                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
 635                             gfp_t gfp)
 636 {
 637         int qpn;
 638         int err;
 639         struct mlx4_ib_sqp *sqp;
 640         struct mlx4_ib_qp *qp;
 641         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 642         struct mlx4_ib_cq *mcq;
 643         unsigned long flags;
 644
 645         /* When tunneling special qps, we use a plain UD qp */
 646         if (sqpn) {
 647                 if (mlx4_is_mfunc(dev->dev) &&
 648                     (!mlx4_is_master(dev->dev) ||
 649                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 650                         if (init_attr->qp_type == IB_QPT_GSI)
 651                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 652                         else {
 653                                 if (mlx4_is_master(dev->dev) ||
 654                                     qp0_enabled_vf(dev->dev, sqpn))
 655                                         qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 656                                 else
 657                                         qp_type = MLX4_IB_QPT_PROXY_SMI;
 658                         }
 659                 }
 660                 qpn = sqpn;
 661                 /* add extra sg entry for tunneling */
 662                 init_attr->cap.max_recv_sge++;
 663         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
 664                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
 665                         container_of(init_attr,
 666                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
 667                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
 668                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
 669                     !mlx4_is_master(dev->dev))
 670                         return -EINVAL;
 671                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
 672                         qp_type = MLX4_IB_QPT_TUN_GSI;
 673                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
 674                          mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
 675                                              tnl_init->port))
 676                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
 677                 else
 678                         qp_type = MLX4_IB_QPT_TUN_SMI;
 679                 /* we are definitely in the PPF here, since we are creating
 680                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
 681                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
 682                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
 683                 sqpn = qpn;
 684         }
 685
 686         if (!*caller_qp) {
 687                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
 688                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
 689                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
 690                         sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
 691                         if (!sqp)
 692                                 return -ENOMEM;
 693                         qp = &sqp->qp;
 694                         qp->pri.vid = 0xFFFF;
 695                         qp->alt.vid = 0xFFFF;
 696                 } else {
 697                         qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
 698                         if (!qp)
 699                                 return -ENOMEM;
 700                         qp->pri.vid = 0xFFFF;
 701                         qp->alt.vid = 0xFFFF;
 702                 }
 703         } else
 704                 qp = *caller_qp;
 705
 706         qp->mlx4_ib_qp_type = qp_type;
 707
 708         mutex_init(&qp->mutex);
 709         spin_lock_init(&qp->sq.lock);
 710         spin_lock_init(&qp->rq.lock);
 711         INIT_LIST_HEAD(&qp->gid_list);
 712         INIT_LIST_HEAD(&qp->steering_rules);
 713
 714         qp->state        = IB_QPS_RESET;
 715         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 716                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 717
 718         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
 719         if (err)
 720                 goto err;
 721
 722         if (pd->uobject) {
 723                 struct mlx4_ib_create_qp ucmd;
 724
 725                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 726                         err = -EFAULT;
 727                         goto err;
 728                 }
 729
 730                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 731
 732                 err = set_user_sq_size(dev, qp, &ucmd);
 733                 if (err)
 734                         goto err;
 735
 736                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 737                                        qp->buf_size, 0, 0);
 738                 if (IS_ERR(qp->umem)) {
 739                         err = PTR_ERR(qp->umem);
 740                         goto err;
 741                 }
 742
 743                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 744                                     ilog2(qp->umem->page_size), &qp->mtt);
 745                 if (err)
 746                         goto err_buf;
 747
 748                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 749                 if (err)
 750                         goto err_mtt;
 751
 752                 if (qp_has_rq(init_attr)) {
 753                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 754                                                   ucmd.db_addr, &qp->db);
 755                         if (err)
 756                                 goto err_mtt;
 757                 }
 758         } else {
 759                 qp->sq_no_prefetch = 0;
 760
 761                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 762                         qp->flags |= MLX4_IB_QP_LSO;
 763
 764                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
 765                         if (dev->steering_support ==
 766                             MLX4_STEERING_MODE_DEVICE_MANAGED)
 767                                 qp->flags |= MLX4_IB_QP_NETIF;
 768                         else
 769                                 goto err;
 770                 }
 771
 772                 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
 773                 if (err)
 774                         goto err;
 775
 776                 if (qp_has_rq(init_attr)) {
 777                         err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
 778                         if (err)
 779                                 goto err;
 780
 781                         *qp->db.db = 0;
 782                 }
 783
 784                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
 785                         err = -ENOMEM;
 786                         goto err_db;
 787                 }
 788
 789                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 790                                     &qp->mtt);
 791                 if (err)
 792                         goto err_buf;
 793
 794                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
 795                 if (err)
 796                         goto err_mtt;
 797
 798                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), gfp);
 799                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), gfp);
 800                 if (!qp->sq.wrid || !qp->rq.wrid) {
 801                         err = -ENOMEM;
 802                         goto err_wrid;
 803                 }
 804         }
 805
 806         if (sqpn) {
 807                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
 808                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
 809                         if (alloc_proxy_bufs(pd->device, qp)) {
 810                                 err = -ENOMEM;
 811                                 goto err_wrid;
 812                         }
 813                 }
 814         } else {
 815                 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
 816                  * otherwise, the WQE BlueFlame setup flow wrongly causes
 817                  * VLAN insertion. */
 818                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
 819                         err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
 820                                                     (init_attr->cap.max_send_wr ?
 821                                                      MLX4_RESERVE_ETH_BF_QP : 0) |
 822                                                     (init_attr->cap.max_recv_wr ?
 823                                                      MLX4_RESERVE_A0_QP : 0));
 824                 else
 825                         if (qp->flags & MLX4_IB_QP_NETIF)
 826                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
 827                         else
 828                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
 829                                                             &qpn, 0);
 830                 if (err)
 831                         goto err_proxy;
 832         }
 833
 834         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 835                 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 836
 837         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
 838         if (err)
 839                 goto err_qpn;
 840
 841         if (init_attr->qp_type == IB_QPT_XRC_TGT)
 842                 qp->mqp.qpn |= (1 << 23);
 843
 844         /*
 845          * Hardware wants QPN written in big-endian order (after
 846          * shifting) for send doorbell.  Precompute this value to save
 847          * a little bit when posting sends.
 848          */
 849         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 850
 851         qp->mqp.event = mlx4_ib_qp_event;
 852         if (!*caller_qp)
 853                 *caller_qp = qp;
 854
 855         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
 856         mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
 857                          to_mcq(init_attr->recv_cq));
 858         /* Maintain device to QPs access, needed for further handling
 859          * via reset flow
 860          */
 861         list_add_tail(&qp->qps_list, &dev->qp_list);
 862         /* Maintain CQ to QPs access, needed for further handling
 863          * via reset flow
 864          */
 865         mcq = to_mcq(init_attr->send_cq);
 866         list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
 867         mcq = to_mcq(init_attr->recv_cq);
 868         list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
 869         mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
 870                            to_mcq(init_attr->recv_cq));
 871         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
 872         return 0;
 873
 874 err_qpn:
 875         if (!sqpn) {
 876                 if (qp->flags & MLX4_IB_QP_NETIF)
 877                         mlx4_ib_steer_qp_free(dev, qpn, 1);
 878                 else
 879                         mlx4_qp_release_range(dev->dev, qpn, 1);
 880         }
 881 err_proxy:
 882         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
 883                 free_proxy_bufs(pd->device, qp);
 884 err_wrid:
 885         if (pd->uobject) {
 886                 if (qp_has_rq(init_attr))
 887                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 888         } else {
 889                 kfree(qp->sq.wrid);
 890                 kfree(qp->rq.wrid);
 891         }
 892
 893 err_mtt:
 894         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 895
 896 err_buf:
 897         if (pd->uobject)
 898                 ib_umem_release(qp->umem);
 899         else
 900                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 901
 902 err_db:
 903         if (!pd->uobject && qp_has_rq(init_attr))
 904                 mlx4_db_free(dev->dev, &qp->db);
 905
 906 err:
 907         if (!*caller_qp)
 908                 kfree(qp);
 909         return err;
 910 }
 911
 912 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 913 {
 914         switch (state) {
 915         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 916         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 917         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 918         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 919         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 920         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 921         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 922         default:                return -1;
 923         }
 924 }
 925
 926 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 927         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 928 {
 929         if (send_cq == recv_cq) {
 930                 spin_lock(&send_cq->lock);
 931                 __acquire(&recv_cq->lock);
 932         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 933                 spin_lock(&send_cq->lock);
 934                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 935         } else {
 936                 spin_lock(&recv_cq->lock);
 937                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 938         }
 939 }
 940
 941 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 942         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 943 {
 944         if (send_cq == recv_cq) {
 945                 __release(&recv_cq->lock);
 946                 spin_unlock(&send_cq->lock);
 947         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 948                 spin_unlock(&recv_cq->lock);
 949                 spin_unlock(&send_cq->lock);
 950         } else {
 951                 spin_unlock(&send_cq->lock);
 952                 spin_unlock(&recv_cq->lock);
 953         }
 954 }
 955
 956 static void del_gid_entries(struct mlx4_ib_qp *qp)
 957 {
 958         struct mlx4_ib_gid_entry *ge, *tmp;
 959
 960         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 961                 list_del(&ge->list);
 962                 kfree(ge);
 963         }
 964 }
 965
 966 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
 967 {
 968         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
 969                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
 970         else
 971                 return to_mpd(qp->ibqp.pd);
 972 }
 973
 974 static void get_cqs(struct mlx4_ib_qp *qp,
 975                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
 976 {
 977         switch (qp->ibqp.qp_type) {
 978         case IB_QPT_XRC_TGT:
 979                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
 980                 *recv_cq = *send_cq;
 981                 break;
 982         case IB_QPT_XRC_INI:
 983                 *send_cq = to_mcq(qp->ibqp.send_cq);
 984                 *recv_cq = *send_cq;
 985                 break;
 986         default:
 987                 *send_cq = to_mcq(qp->ibqp.send_cq);
 988                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
 989                 break;
 990         }
 991 }
 992
 993 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 994                               int is_user)
 995 {
 996         struct mlx4_ib_cq *send_cq, *recv_cq;
 997         unsigned long flags;
 998
 999         if (qp->state != IB_QPS_RESET) {
1000                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1001                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1002                         pr_warn("modify QP %06x to RESET failed.\n",
1003                                qp->mqp.qpn);
1004                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1005                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1006                         qp->pri.smac = 0;
1007                         qp->pri.smac_port = 0;
1008                 }
1009                 if (qp->alt.smac) {
1010                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1011                         qp->alt.smac = 0;
1012                 }
1013                 if (qp->pri.vid < 0x1000) {
1014                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1015                         qp->pri.vid = 0xFFFF;
1016                         qp->pri.candidate_vid = 0xFFFF;
1017                         qp->pri.update_vid = 0;
1018                 }
1019                 if (qp->alt.vid < 0x1000) {
1020                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1021                         qp->alt.vid = 0xFFFF;
1022                         qp->alt.candidate_vid = 0xFFFF;
1023                         qp->alt.update_vid = 0;
1024                 }
1025         }
1026
1027         get_cqs(qp, &send_cq, &recv_cq);
1028
1029         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1030         mlx4_ib_lock_cqs(send_cq, recv_cq);
1031
1032         /* del from lists under both locks above to protect reset flow paths */
1033         list_del(&qp->qps_list);
1034         list_del(&qp->cq_send_list);
1035         list_del(&qp->cq_recv_list);
1036         if (!is_user) {
1037                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1038                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1039                 if (send_cq != recv_cq)
1040                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1041         }
1042
1043         mlx4_qp_remove(dev->dev, &qp->mqp);
1044
1045         mlx4_ib_unlock_cqs(send_cq, recv_cq);
1046         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1047
1048         mlx4_qp_free(dev->dev, &qp->mqp);
1049
1050         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1051                 if (qp->flags & MLX4_IB_QP_NETIF)
1052                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1053                 else
1054                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1055         }
1056
1057         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1058
1059         if (is_user) {
1060                 if (qp->rq.wqe_cnt)
1061                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1062                                               &qp->db);
1063                 ib_umem_release(qp->umem);
1064         } else {
1065                 kfree(qp->sq.wrid);
1066                 kfree(qp->rq.wrid);
1067                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1068                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1069                         free_proxy_bufs(&dev->ib_dev, qp);
1070                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1071                 if (qp->rq.wqe_cnt)
1072                         mlx4_db_free(dev->dev, &qp->db);
1073         }
1074
1075         del_gid_entries(qp);
1076 }
1077
1078 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1079 {
1080         /* Native or PPF */
1081         if (!mlx4_is_mfunc(dev->dev) ||
1082             (mlx4_is_master(dev->dev) &&
1083              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1084                 return  dev->dev->phys_caps.base_sqpn +
1085                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1086                         attr->port_num - 1;
1087         }
1088         /* PF or VF -- creating proxies */
1089         if (attr->qp_type == IB_QPT_SMI)
1090                 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1091         else
1092                 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1093 }
1094
1095 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1096                                 struct ib_qp_init_attr *init_attr,
1097                                 struct ib_udata *udata)
1098 {
1099         struct mlx4_ib_qp *qp = NULL;
1100         int err;
1101         int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1102         u16 xrcdn = 0;
1103         gfp_t gfp;
1104
1105         gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1106                 GFP_NOIO : GFP_KERNEL;
1107         /*
1108          * We only support LSO, vendor flag1, and multicast loopback blocking,
1109          * and only for kernel UD QPs.
1110          */
1111         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1112                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1113                                         MLX4_IB_SRIOV_TUNNEL_QP |
1114                                         MLX4_IB_SRIOV_SQP |
1115                                         MLX4_IB_QP_NETIF |
1116                                         MLX4_IB_QP_CREATE_USE_GFP_NOIO))
1117                 return ERR_PTR(-EINVAL);
1118
1119         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1120                 if (init_attr->qp_type != IB_QPT_UD)
1121                         return ERR_PTR(-EINVAL);
1122         }
1123
1124         if (init_attr->create_flags &&
1125             ((udata && init_attr->create_flags & ~(sup_u_create_flags)) ||
1126              ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1127                                            MLX4_IB_QP_CREATE_USE_GFP_NOIO |
1128                                            MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)) &&
1129               init_attr->qp_type != IB_QPT_UD) ||
1130              ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1131               init_attr->qp_type > IB_QPT_GSI)))
1132                 return ERR_PTR(-EINVAL);
1133
1134         switch (init_attr->qp_type) {
1135         case IB_QPT_XRC_TGT:
1136                 pd = to_mxrcd(init_attr->xrcd)->pd;
1137                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1138                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1139                 /* fall through */
1140         case IB_QPT_XRC_INI:
1141                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1142                         return ERR_PTR(-ENOSYS);
1143                 init_attr->recv_cq = init_attr->send_cq;
1144                 /* fall through */
1145         case IB_QPT_RC:
1146         case IB_QPT_UC:
1147         case IB_QPT_RAW_PACKET:
1148                 qp = kzalloc(sizeof *qp, gfp);
1149                 if (!qp)
1150                         return ERR_PTR(-ENOMEM);
1151                 qp->pri.vid = 0xFFFF;
1152                 qp->alt.vid = 0xFFFF;
1153                 /* fall through */
1154         case IB_QPT_UD:
1155         {
1156                 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1157                                        udata, 0, &qp, gfp);
1158                 if (err)
1159                         return ERR_PTR(err);
1160
1161                 qp->ibqp.qp_num = qp->mqp.qpn;
1162                 qp->xrcdn = xrcdn;
1163
1164                 break;
1165         }
1166         case IB_QPT_SMI:
1167         case IB_QPT_GSI:
1168         {
1169                 /* Userspace is not allowed to create special QPs: */
1170                 if (udata)
1171                         return ERR_PTR(-EINVAL);
1172
1173                 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1174                                        get_sqp_num(to_mdev(pd->device), init_attr),
1175                                        &qp, gfp);
1176                 if (err)
1177                         return ERR_PTR(err);
1178
1179                 qp->port        = init_attr->port_num;
1180                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1181
1182                 break;
1183         }
1184         default:
1185                 /* Don't support raw QPs */
1186                 return ERR_PTR(-EINVAL);
1187         }
1188
1189         return &qp->ibqp;
1190 }
1191
1192 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1193 {
1194         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1195         struct mlx4_ib_qp *mqp = to_mqp(qp);
1196         struct mlx4_ib_pd *pd;
1197
1198         if (is_qp0(dev, mqp))
1199                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1200
1201         if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1202                 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1203                 dev->qp1_proxy[mqp->port - 1] = NULL;
1204                 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1205         }
1206
1207         if (mqp->counter_index)
1208                 mlx4_ib_free_qp_counter(dev, mqp);
1209
1210         pd = get_pd(mqp);
1211         destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1212
1213         if (is_sqp(dev, mqp))
1214                 kfree(to_msqp(mqp));
1215         else
1216                 kfree(mqp);
1217
1218         return 0;
1219 }
1220
1221 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1222 {
1223         switch (type) {
1224         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1225         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1226         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1227         case MLX4_IB_QPT_XRC_INI:
1228         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1229         case MLX4_IB_QPT_SMI:
1230         case MLX4_IB_QPT_GSI:
1231         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1232
1233         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1234         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1235                                                 MLX4_QP_ST_MLX : -1);
1236         case MLX4_IB_QPT_PROXY_SMI:
1237         case MLX4_IB_QPT_TUN_SMI:
1238         case MLX4_IB_QPT_PROXY_GSI:
1239         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1240                                                 MLX4_QP_ST_UD : -1);
1241         default:                        return -1;
1242         }
1243 }
1244
1245 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1246                                    int attr_mask)
1247 {
1248         u8 dest_rd_atomic;
1249         u32 access_flags;
1250         u32 hw_access_flags = 0;
1251
1252         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1253                 dest_rd_atomic = attr->max_dest_rd_atomic;
1254         else
1255                 dest_rd_atomic = qp->resp_depth;
1256
1257         if (attr_mask & IB_QP_ACCESS_FLAGS)
1258                 access_flags = attr->qp_access_flags;
1259         else
1260                 access_flags = qp->atomic_rd_en;
1261
1262         if (!dest_rd_atomic)
1263                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1264
1265         if (access_flags & IB_ACCESS_REMOTE_READ)
1266                 hw_access_flags |= MLX4_QP_BIT_RRE;
1267         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1268                 hw_access_flags |= MLX4_QP_BIT_RAE;
1269         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1270                 hw_access_flags |= MLX4_QP_BIT_RWE;
1271
1272         return cpu_to_be32(hw_access_flags);
1273 }
1274
1275 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1276                             int attr_mask)
1277 {
1278         if (attr_mask & IB_QP_PKEY_INDEX)
1279                 sqp->pkey_index = attr->pkey_index;
1280         if (attr_mask & IB_QP_QKEY)
1281                 sqp->qkey = attr->qkey;
1282         if (attr_mask & IB_QP_SQ_PSN)
1283                 sqp->send_psn = attr->sq_psn;
1284 }
1285
1286 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1287 {
1288         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1289 }
1290
1291 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1292                           u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1293                           struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1294 {
1295         int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1296                 IB_LINK_LAYER_ETHERNET;
1297         int vidx;
1298         int smac_index;
1299         int err;
1300
1301
1302         path->grh_mylmc     = ah->src_path_bits & 0x7f;
1303         path->rlid          = cpu_to_be16(ah->dlid);
1304         if (ah->static_rate) {
1305                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1306                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1307                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1308                         --path->static_rate;
1309         } else
1310                 path->static_rate = 0;
1311
1312         if (ah->ah_flags & IB_AH_GRH) {
1313                 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1314                                                                       port,
1315                                                                       ah->grh.sgid_index);
1316
1317                 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1318                         pr_err("sgid_index (%u) too large. max is %d\n",
1319                                real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1320                         return -1;
1321                 }
1322
1323                 path->grh_mylmc |= 1 << 7;
1324                 path->mgid_index = real_sgid_index;
1325                 path->hop_limit  = ah->grh.hop_limit;
1326                 path->tclass_flowlabel =
1327                         cpu_to_be32((ah->grh.traffic_class << 20) |
1328                                     (ah->grh.flow_label));
1329                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1330         }
1331
1332         if (is_eth) {
1333                 if (!(ah->ah_flags & IB_AH_GRH))
1334                         return -1;
1335
1336                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1337                         ((port - 1) << 6) | ((ah->sl & 7) << 3);
1338
1339                 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1340                 if (vlan_tag < 0x1000) {
1341                         if (smac_info->vid < 0x1000) {
1342                                 /* both valid vlan ids */
1343                                 if (smac_info->vid != vlan_tag) {
1344                                         /* different VIDs.  unreg old and reg new */
1345                                         err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1346                                         if (err)
1347                                                 return err;
1348                                         smac_info->candidate_vid = vlan_tag;
1349                                         smac_info->candidate_vlan_index = vidx;
1350                                         smac_info->candidate_vlan_port = port;
1351                                         smac_info->update_vid = 1;
1352                                         path->vlan_index = vidx;
1353                                 } else {
1354                                         path->vlan_index = smac_info->vlan_index;
1355                                 }
1356                         } else {
1357                                 /* no current vlan tag in qp */
1358                                 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1359                                 if (err)
1360                                         return err;
1361                                 smac_info->candidate_vid = vlan_tag;
1362                                 smac_info->candidate_vlan_index = vidx;
1363                                 smac_info->candidate_vlan_port = port;
1364                                 smac_info->update_vid = 1;
1365                                 path->vlan_index = vidx;
1366                         }
1367                         path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1368                         path->fl = 1 << 6;
1369                 } else {
1370                         /* have current vlan tag. unregister it at modify-qp success */
1371                         if (smac_info->vid < 0x1000) {
1372                                 smac_info->candidate_vid = 0xFFFF;
1373                                 smac_info->update_vid = 1;
1374                         }
1375                 }
1376
1377                 /* get smac_index for RoCE use.
1378                  * If no smac was yet assigned, register one.
1379                  * If one was already assigned, but the new mac differs,
1380                  * unregister the old one and register the new one.
1381                 */
1382                 if ((!smac_info->smac && !smac_info->smac_port) ||
1383                     smac_info->smac != smac) {
1384                         /* register candidate now, unreg if needed, after success */
1385                         smac_index = mlx4_register_mac(dev->dev, port, smac);
1386                         if (smac_index >= 0) {
1387                                 smac_info->candidate_smac_index = smac_index;
1388                                 smac_info->candidate_smac = smac;
1389                                 smac_info->candidate_smac_port = port;
1390                         } else {
1391                                 return -EINVAL;
1392                         }
1393                 } else {
1394                         smac_index = smac_info->smac_index;
1395                 }
1396
1397                 memcpy(path->dmac, ah->dmac, 6);
1398                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1399                 /* put MAC table smac index for IBoE */
1400                 path->grh_mylmc = (u8) (smac_index) | 0x80;
1401         } else {
1402                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1403                         ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1404         }
1405
1406         return 0;
1407 }
1408
1409 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1410                          enum ib_qp_attr_mask qp_attr_mask,
1411                          struct mlx4_ib_qp *mqp,
1412                          struct mlx4_qp_path *path, u8 port)
1413 {
1414         return _mlx4_set_path(dev, &qp->ah_attr,
1415                               mlx4_mac_to_u64((u8 *)qp->smac),
1416                               (qp_attr_mask & IB_QP_VID) ? qp->vlan_id : 0xffff,
1417                               path, &mqp->pri, port);
1418 }
1419
1420 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1421                              const struct ib_qp_attr *qp,
1422                              enum ib_qp_attr_mask qp_attr_mask,
1423                              struct mlx4_ib_qp *mqp,
1424                              struct mlx4_qp_path *path, u8 port)
1425 {
1426         return _mlx4_set_path(dev, &qp->alt_ah_attr,
1427                               mlx4_mac_to_u64((u8 *)qp->alt_smac),
1428                               (qp_attr_mask & IB_QP_ALT_VID) ?
1429                               qp->alt_vlan_id : 0xffff,
1430                               path, &mqp->alt, port);
1431 }
1432
1433 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1434 {
1435         struct mlx4_ib_gid_entry *ge, *tmp;
1436
1437         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1438                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1439                         ge->added = 1;
1440                         ge->port = qp->port;
1441                 }
1442         }
1443 }
1444
1445 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, u8 *smac,
1446                                     struct mlx4_qp_context *context)
1447 {
1448         u64 u64_mac;
1449         int smac_index;
1450
1451         u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1452
1453         context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1454         if (!qp->pri.smac && !qp->pri.smac_port) {
1455                 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1456                 if (smac_index >= 0) {
1457                         qp->pri.candidate_smac_index = smac_index;
1458                         qp->pri.candidate_smac = u64_mac;
1459                         qp->pri.candidate_smac_port = qp->port;
1460                         context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1461                 } else {
1462                         return -ENOENT;
1463                 }
1464         }
1465         return 0;
1466 }
1467
1468 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1469 {
1470         struct counter_index *new_counter_index;
1471         int err;
1472         u32 tmp_idx;
1473
1474         if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1475             IB_LINK_LAYER_ETHERNET ||
1476             !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1477             !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1478                 return 0;
1479
1480         err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1481         if (err)
1482                 return err;
1483
1484         new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1485         if (!new_counter_index) {
1486                 mlx4_counter_free(dev->dev, tmp_idx);
1487                 return -ENOMEM;
1488         }
1489
1490         new_counter_index->index = tmp_idx;
1491         new_counter_index->allocated = 1;
1492         qp->counter_index = new_counter_index;
1493
1494         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1495         list_add_tail(&new_counter_index->list,
1496                       &dev->counters_table[qp->port - 1].counters_list);
1497         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1498
1499         return 0;
1500 }
1501
1502 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1503                                const struct ib_qp_attr *attr, int attr_mask,
1504                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1505 {
1506         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1507         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1508         struct mlx4_ib_pd *pd;
1509         struct mlx4_ib_cq *send_cq, *recv_cq;
1510         struct mlx4_qp_context *context;
1511         enum mlx4_qp_optpar optpar = 0;
1512         int sqd_event;
1513         int steer_qp = 0;
1514         int err = -EINVAL;
1515         int counter_index;
1516
1517         /* APM is not supported under RoCE */
1518         if (attr_mask & IB_QP_ALT_PATH &&
1519             rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1520             IB_LINK_LAYER_ETHERNET)
1521                 return -ENOTSUPP;
1522
1523         context = kzalloc(sizeof *context, GFP_KERNEL);
1524         if (!context)
1525                 return -ENOMEM;
1526
1527         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1528                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1529
1530         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1531                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1532         else {
1533                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1534                 switch (attr->path_mig_state) {
1535                 case IB_MIG_MIGRATED:
1536                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1537                         break;
1538                 case IB_MIG_REARM:
1539                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1540                         break;
1541                 case IB_MIG_ARMED:
1542                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1543                         break;
1544                 }
1545         }
1546
1547         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1548                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1549         else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1550                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1551         else if (ibqp->qp_type == IB_QPT_UD) {
1552                 if (qp->flags & MLX4_IB_QP_LSO)
1553                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
1554                                               ilog2(dev->dev->caps.max_gso_sz);
1555                 else
1556                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1557         } else if (attr_mask & IB_QP_PATH_MTU) {
1558                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1559                         pr_err("path MTU (%u) is invalid\n",
1560                                attr->path_mtu);
1561                         goto out;
1562                 }
1563                 context->mtu_msgmax = (attr->path_mtu << 5) |
1564                         ilog2(dev->dev->caps.max_msg_sz);
1565         }
1566
1567         if (qp->rq.wqe_cnt)
1568                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1569         context->rq_size_stride |= qp->rq.wqe_shift - 4;
1570
1571         if (qp->sq.wqe_cnt)
1572                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1573         context->sq_size_stride |= qp->sq.wqe_shift - 4;
1574
1575         if (new_state == IB_QPS_RESET && qp->counter_index)
1576                 mlx4_ib_free_qp_counter(dev, qp);
1577
1578         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1579                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1580                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1581                 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1582                         context->param3 |= cpu_to_be32(1 << 30);
1583         }
1584
1585         if (qp->ibqp.uobject)
1586                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1587         else
1588                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1589
1590         if (attr_mask & IB_QP_DEST_QPN)
1591                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1592
1593         if (attr_mask & IB_QP_PORT) {
1594                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1595                     !(attr_mask & IB_QP_AV)) {
1596                         mlx4_set_sched(&context->pri_path, attr->port_num);
1597                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1598                 }
1599         }
1600
1601         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1602                 err = create_qp_lb_counter(dev, qp);
1603                 if (err)
1604                         goto out;
1605
1606                 counter_index =
1607                         dev->counters_table[qp->port - 1].default_counter;
1608                 if (qp->counter_index)
1609                         counter_index = qp->counter_index->index;
1610
1611                 if (counter_index != -1) {
1612                         context->pri_path.counter_index = counter_index;
1613                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1614                         if (qp->counter_index) {
1615                                 context->pri_path.fl |=
1616                                         MLX4_FL_ETH_SRC_CHECK_MC_LB;
1617                                 context->pri_path.vlan_control |=
1618                                         MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1619                         }
1620                 } else
1621                         context->pri_path.counter_index =
1622                                 MLX4_SINK_COUNTER_INDEX(dev->dev);
1623
1624                 if (qp->flags & MLX4_IB_QP_NETIF) {
1625                         mlx4_ib_steer_qp_reg(dev, qp, 1);
1626                         steer_qp = 1;
1627                 }
1628         }
1629
1630         if (attr_mask & IB_QP_PKEY_INDEX) {
1631                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1632                         context->pri_path.disable_pkey_check = 0x40;
1633                 context->pri_path.pkey_index = attr->pkey_index;
1634                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1635         }
1636
1637         if (attr_mask & IB_QP_AV) {
1638                 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1639                                   attr_mask & IB_QP_PORT ?
1640                                   attr->port_num : qp->port))
1641                         goto out;
1642
1643                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1644                            MLX4_QP_OPTPAR_SCHED_QUEUE);
1645         }
1646
1647         if (attr_mask & IB_QP_TIMEOUT) {
1648                 context->pri_path.ackto |= attr->timeout << 3;
1649                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1650         }
1651
1652         if (attr_mask & IB_QP_ALT_PATH) {
1653                 if (attr->alt_port_num == 0 ||
1654                     attr->alt_port_num > dev->dev->caps.num_ports)
1655                         goto out;
1656
1657                 if (attr->alt_pkey_index >=
1658                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
1659                         goto out;
1660
1661                 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1662                                       &context->alt_path,
1663                                       attr->alt_port_num))
1664                         goto out;
1665
1666                 context->alt_path.pkey_index = attr->alt_pkey_index;
1667                 context->alt_path.ackto = attr->alt_timeout << 3;
1668                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1669         }
1670
1671         pd = get_pd(qp);
1672         get_cqs(qp, &send_cq, &recv_cq);
1673         context->pd       = cpu_to_be32(pd->pdn);
1674         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1675         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1676         context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1677
1678         /* Set "fast registration enabled" for all kernel QPs */
1679         if (!qp->ibqp.uobject)
1680                 context->params1 |= cpu_to_be32(1 << 11);
1681
1682         if (attr_mask & IB_QP_RNR_RETRY) {
1683                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1684                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1685         }
1686
1687         if (attr_mask & IB_QP_RETRY_CNT) {
1688                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1689                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1690         }
1691
1692         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1693                 if (attr->max_rd_atomic)
1694                         context->params1 |=
1695                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1696                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1697         }
1698
1699         if (attr_mask & IB_QP_SQ_PSN)
1700                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1701
1702         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1703                 if (attr->max_dest_rd_atomic)
1704                         context->params2 |=
1705                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1706                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1707         }
1708
1709         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1710                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1711                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1712         }
1713
1714         if (ibqp->srq)
1715                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1716
1717         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1718                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1719                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1720         }
1721         if (attr_mask & IB_QP_RQ_PSN)
1722                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1723
1724         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1725         if (attr_mask & IB_QP_QKEY) {
1726                 if (qp->mlx4_ib_qp_type &
1727                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1728                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1729                 else {
1730                         if (mlx4_is_mfunc(dev->dev) &&
1731                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1732                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1733                             MLX4_RESERVED_QKEY_BASE) {
1734                                 pr_err("Cannot use reserved QKEY"
1735                                        " 0x%x (range 0xffff0000..0xffffffff"
1736                                        " is reserved)\n", attr->qkey);
1737                                 err = -EINVAL;
1738                                 goto out;
1739                         }
1740                         context->qkey = cpu_to_be32(attr->qkey);
1741                 }
1742                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1743         }
1744
1745         if (ibqp->srq)
1746                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1747
1748         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1749                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1750
1751         if (cur_state == IB_QPS_INIT &&
1752             new_state == IB_QPS_RTR  &&
1753             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1754              ibqp->qp_type == IB_QPT_UD ||
1755              ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1756                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1757                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1758                     qp->mlx4_ib_qp_type &
1759                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1760                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1761                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1762                                 context->pri_path.fl = 0x80;
1763                 } else {
1764                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1765                                 context->pri_path.fl = 0x80;
1766                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1767                 }
1768                 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1769                     IB_LINK_LAYER_ETHERNET) {
1770                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1771                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1772                                 context->pri_path.feup = 1 << 7; /* don't fsm */
1773                         /* handle smac_index */
1774                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1775                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1776                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1777                                 err = handle_eth_ud_smac_index(dev, qp, (u8 *)attr->smac, context);
1778                                 if (err) {
1779                                         err = -EINVAL;
1780                                         goto out;
1781                                 }
1782                                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1783                                         dev->qp1_proxy[qp->port - 1] = qp;
1784                         }
1785                 }
1786         }
1787
1788         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1789                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1790                                         MLX4_IB_LINK_TYPE_ETH;
1791                 if (dev->dev->caps.tunnel_offload_mode ==  MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1792                         /* set QP to receive both tunneled & non-tunneled packets */
1793                         if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
1794                                 context->srqn = cpu_to_be32(7 << 28);
1795                 }
1796         }
1797
1798         if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1799                 int is_eth = rdma_port_get_link_layer(
1800                                 &dev->ib_dev, qp->port) ==
1801                                 IB_LINK_LAYER_ETHERNET;
1802                 if (is_eth) {
1803                         context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1804                         optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1805                 }
1806         }
1807
1808
1809         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1810             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1811                 sqd_event = 1;
1812         else
1813                 sqd_event = 0;
1814
1815         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1816                 context->rlkey |= (1 << 4);
1817
1818         /*
1819          * Before passing a kernel QP to the HW, make sure that the
1820          * ownership bits of the send queue are set and the SQ
1821          * headroom is stamped so that the hardware doesn't start
1822          * processing stale work requests.
1823          */
1824         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1825                 struct mlx4_wqe_ctrl_seg *ctrl;
1826                 int i;
1827
1828                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1829                         ctrl = get_send_wqe(qp, i);
1830                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1831                         if (qp->sq_max_wqes_per_wr == 1)
1832                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1833
1834                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1835                 }
1836         }
1837
1838         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1839                              to_mlx4_state(new_state), context, optpar,
1840                              sqd_event, &qp->mqp);
1841         if (err)
1842                 goto out;
1843
1844         qp->state = new_state;
1845
1846         if (attr_mask & IB_QP_ACCESS_FLAGS)
1847                 qp->atomic_rd_en = attr->qp_access_flags;
1848         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1849                 qp->resp_depth = attr->max_dest_rd_atomic;
1850         if (attr_mask & IB_QP_PORT) {
1851                 qp->port = attr->port_num;
1852                 update_mcg_macs(dev, qp);
1853         }
1854         if (attr_mask & IB_QP_ALT_PATH)
1855                 qp->alt_port = attr->alt_port_num;
1856
1857         if (is_sqp(dev, qp))
1858                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1859
1860         /*
1861          * If we moved QP0 to RTR, bring the IB link up; if we moved
1862          * QP0 to RESET or ERROR, bring the link back down.
1863          */
1864         if (is_qp0(dev, qp)) {
1865                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1866                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1867                                 pr_warn("INIT_PORT failed for port %d\n",
1868                                        qp->port);
1869
1870                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1871                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1872                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1873         }
1874
1875         /*
1876          * If we moved a kernel QP to RESET, clean up all old CQ
1877          * entries and reinitialize the QP.
1878          */
1879         if (new_state == IB_QPS_RESET) {
1880                 if (!ibqp->uobject) {
1881                         mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1882                                          ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1883                         if (send_cq != recv_cq)
1884                                 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1885
1886                         qp->rq.head = 0;
1887                         qp->rq.tail = 0;
1888                         qp->sq.head = 0;
1889                         qp->sq.tail = 0;
1890                         qp->sq_next_wqe = 0;
1891                         if (qp->rq.wqe_cnt)
1892                                 *qp->db.db  = 0;
1893
1894                         if (qp->flags & MLX4_IB_QP_NETIF)
1895                                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1896                 }
1897                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1898                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1899                         qp->pri.smac = 0;
1900                         qp->pri.smac_port = 0;
1901                 }
1902                 if (qp->alt.smac) {
1903                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1904                         qp->alt.smac = 0;
1905                 }
1906                 if (qp->pri.vid < 0x1000) {
1907                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1908                         qp->pri.vid = 0xFFFF;
1909                         qp->pri.candidate_vid = 0xFFFF;
1910                         qp->pri.update_vid = 0;
1911                 }
1912
1913                 if (qp->alt.vid < 0x1000) {
1914                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1915                         qp->alt.vid = 0xFFFF;
1916                         qp->alt.candidate_vid = 0xFFFF;
1917                         qp->alt.update_vid = 0;
1918                 }
1919         }
1920 out:
1921         if (err && qp->counter_index)
1922                 mlx4_ib_free_qp_counter(dev, qp);
1923         if (err && steer_qp)
1924                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1925         kfree(context);
1926         if (qp->pri.candidate_smac ||
1927             (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
1928                 if (err) {
1929                         mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1930                 } else {
1931                         if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
1932                                 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1933                         qp->pri.smac = qp->pri.candidate_smac;
1934                         qp->pri.smac_index = qp->pri.candidate_smac_index;
1935                         qp->pri.smac_port = qp->pri.candidate_smac_port;
1936                 }
1937                 qp->pri.candidate_smac = 0;
1938                 qp->pri.candidate_smac_index = 0;
1939                 qp->pri.candidate_smac_port = 0;
1940         }
1941         if (qp->alt.candidate_smac) {
1942                 if (err) {
1943                         mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1944                 } else {
1945                         if (qp->alt.smac)
1946                                 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1947                         qp->alt.smac = qp->alt.candidate_smac;
1948                         qp->alt.smac_index = qp->alt.candidate_smac_index;
1949                         qp->alt.smac_port = qp->alt.candidate_smac_port;
1950                 }
1951                 qp->alt.candidate_smac = 0;
1952                 qp->alt.candidate_smac_index = 0;
1953                 qp->alt.candidate_smac_port = 0;
1954         }
1955
1956         if (qp->pri.update_vid) {
1957                 if (err) {
1958                         if (qp->pri.candidate_vid < 0x1000)
1959                                 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1960                                                      qp->pri.candidate_vid);
1961                 } else {
1962                         if (qp->pri.vid < 0x1000)
1963                                 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1964                                                      qp->pri.vid);
1965                         qp->pri.vid = qp->pri.candidate_vid;
1966                         qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1967                         qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
1968                 }
1969                 qp->pri.candidate_vid = 0xFFFF;
1970                 qp->pri.update_vid = 0;
1971         }
1972
1973         if (qp->alt.update_vid) {
1974                 if (err) {
1975                         if (qp->alt.candidate_vid < 0x1000)
1976                                 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
1977                                                      qp->alt.candidate_vid);
1978                 } else {
1979                         if (qp->alt.vid < 0x1000)
1980                                 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
1981                                                      qp->alt.vid);
1982                         qp->alt.vid = qp->alt.candidate_vid;
1983                         qp->alt.vlan_port = qp->alt.candidate_vlan_port;
1984                         qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
1985                 }
1986                 qp->alt.candidate_vid = 0xFFFF;
1987                 qp->alt.update_vid = 0;
1988         }
1989
1990         return err;
1991 }
1992
1993 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1994                       int attr_mask, struct ib_udata *udata)
1995 {
1996         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1997         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1998         enum ib_qp_state cur_state, new_state;
1999         int err = -EINVAL;
2000         int ll;
2001         mutex_lock(&qp->mutex);
2002
2003         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2004         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2005
2006         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2007                 ll = IB_LINK_LAYER_UNSPECIFIED;
2008         } else {
2009                 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2010                 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2011         }
2012
2013         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2014                                 attr_mask, ll)) {
2015                 pr_debug("qpn 0x%x: invalid attribute mask specified "
2016                          "for transition %d to %d. qp_type %d,"
2017                          " attr_mask 0x%x\n",
2018                          ibqp->qp_num, cur_state, new_state,
2019                          ibqp->qp_type, attr_mask);
2020                 goto out;
2021         }
2022
2023         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2024                 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2025                         if ((ibqp->qp_type == IB_QPT_RC) ||
2026                             (ibqp->qp_type == IB_QPT_UD) ||
2027                             (ibqp->qp_type == IB_QPT_UC) ||
2028                             (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2029                             (ibqp->qp_type == IB_QPT_XRC_INI)) {
2030                                 attr->port_num = mlx4_ib_bond_next_port(dev);
2031                         }
2032                 } else {
2033                         /* no sense in changing port_num
2034                          * when ports are bonded */
2035                         attr_mask &= ~IB_QP_PORT;
2036                 }
2037         }
2038
2039         if ((attr_mask & IB_QP_PORT) &&
2040             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2041                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2042                          "for transition %d to %d. qp_type %d\n",
2043                          ibqp->qp_num, attr->port_num, cur_state,
2044                          new_state, ibqp->qp_type);
2045                 goto out;
2046         }
2047
2048         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2049             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2050              IB_LINK_LAYER_ETHERNET))
2051                 goto out;
2052
2053         if (attr_mask & IB_QP_PKEY_INDEX) {
2054                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2055                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2056                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2057                                  "for transition %d to %d. qp_type %d\n",
2058                                  ibqp->qp_num, attr->pkey_index, cur_state,
2059                                  new_state, ibqp->qp_type);
2060                         goto out;
2061                 }
2062         }
2063
2064         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2065             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2066                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2067                          "Transition %d to %d. qp_type %d\n",
2068                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
2069                          new_state, ibqp->qp_type);
2070                 goto out;
2071         }
2072
2073         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2074             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2075                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2076                          "Transition %d to %d. qp_type %d\n",
2077                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2078                          new_state, ibqp->qp_type);
2079                 goto out;
2080         }
2081
2082         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2083                 err = 0;
2084                 goto out;
2085         }
2086
2087         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2088
2089         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2090                 attr->port_num = 1;
2091
2092 out:
2093         mutex_unlock(&qp->mutex);
2094         return err;
2095 }
2096
2097 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2098 {
2099         int i;
2100         for (i = 0; i < dev->caps.num_ports; i++) {
2101                 if (qpn == dev->caps.qp0_proxy[i] ||
2102                     qpn == dev->caps.qp0_tunnel[i]) {
2103                         *qkey = dev->caps.qp0_qkey[i];
2104                         return 0;
2105                 }
2106         }
2107         return -EINVAL;
2108 }
2109
2110 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2111                                   struct ib_send_wr *wr,
2112                                   void *wqe, unsigned *mlx_seg_len)
2113 {
2114         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2115         struct ib_device *ib_dev = &mdev->ib_dev;
2116         struct mlx4_wqe_mlx_seg *mlx = wqe;
2117         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2118         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2119         u16 pkey;
2120         u32 qkey;
2121         int send_size;
2122         int header_size;
2123         int spc;
2124         int i;
2125
2126         if (wr->opcode != IB_WR_SEND)
2127                 return -EINVAL;
2128
2129         send_size = 0;
2130
2131         for (i = 0; i < wr->num_sge; ++i)
2132                 send_size += wr->sg_list[i].length;
2133
2134         /* for proxy-qp0 sends, need to add in size of tunnel header */
2135         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2136         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2137                 send_size += sizeof (struct mlx4_ib_tunnel_header);
2138
2139         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
2140
2141         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2142                 sqp->ud_header.lrh.service_level =
2143                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2144                 sqp->ud_header.lrh.destination_lid =
2145                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2146                 sqp->ud_header.lrh.source_lid =
2147                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2148         }
2149
2150         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2151
2152         /* force loopback */
2153         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2154         mlx->rlid = sqp->ud_header.lrh.destination_lid;
2155
2156         sqp->ud_header.lrh.virtual_lane    = 0;
2157         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2158         ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2159         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2160         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2161                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2162         else
2163                 sqp->ud_header.bth.destination_qpn =
2164                         cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
2165
2166         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2167         if (mlx4_is_master(mdev->dev)) {
2168                 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2169                         return -EINVAL;
2170         } else {
2171                 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2172                         return -EINVAL;
2173         }
2174         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2175         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2176
2177         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2178         sqp->ud_header.immediate_present = 0;
2179
2180         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2181
2182         /*
2183          * Inline data segments may not cross a 64 byte boundary.  If
2184          * our UD header is bigger than the space available up to the
2185          * next 64 byte boundary in the WQE, use two inline data
2186          * segments to hold the UD header.
2187          */
2188         spc = MLX4_INLINE_ALIGN -
2189               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2190         if (header_size <= spc) {
2191                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2192                 memcpy(inl + 1, sqp->header_buf, header_size);
2193                 i = 1;
2194         } else {
2195                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2196                 memcpy(inl + 1, sqp->header_buf, spc);
2197
2198                 inl = (void *) (inl + 1) + spc;
2199                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2200                 /*
2201                  * Need a barrier here to make sure all the data is
2202                  * visible before the byte_count field is set.
2203                  * Otherwise the HCA prefetcher could grab the 64-byte
2204                  * chunk with this inline segment and get a valid (!=
2205                  * 0xffffffff) byte count but stale data, and end up
2206                  * generating a packet with bad headers.
2207                  *
2208                  * The first inline segment's byte_count field doesn't
2209                  * need a barrier, because it comes after a
2210                  * control/MLX segment and therefore is at an offset
2211                  * of 16 mod 64.
2212                  */
2213                 wmb();
2214                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2215                 i = 2;
2216         }
2217
2218         *mlx_seg_len =
2219         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2220         return 0;
2221 }
2222
2223 static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
2224 {
2225         int i;
2226
2227         for (i = ETH_ALEN; i; i--) {
2228                 dst_mac[i - 1] = src_mac & 0xff;
2229                 src_mac >>= 8;
2230         }
2231 }
2232
2233 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
2234                             void *wqe, unsigned *mlx_seg_len)
2235 {
2236         struct ib_device *ib_dev = sqp->qp.ibqp.device;
2237         struct mlx4_wqe_mlx_seg *mlx = wqe;
2238         struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2239         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2240         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2241         union ib_gid sgid;
2242         u16 pkey;
2243         int send_size;
2244         int header_size;
2245         int spc;
2246         int i;
2247         int err = 0;
2248         u16 vlan = 0xffff;
2249         bool is_eth;
2250         bool is_vlan = false;
2251         bool is_grh;
2252
2253         send_size = 0;
2254         for (i = 0; i < wr->num_sge; ++i)
2255                 send_size += wr->sg_list[i].length;
2256
2257         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2258         is_grh = mlx4_ib_ah_grh_present(ah);
2259         if (is_eth) {
2260                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2261                         /* When multi-function is enabled, the ib_core gid
2262                          * indexes don't necessarily match the hw ones, so
2263                          * we must use our own cache */
2264                         err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2265                                                            be32_to_cpu(ah->av.ib.port_pd) >> 24,
2266                                                            ah->av.ib.gid_index, &sgid.raw[0]);
2267                         if (err)
2268                                 return err;
2269                 } else  {
2270                         err = ib_get_cached_gid(ib_dev,
2271                                                 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2272                                                 ah->av.ib.gid_index, &sgid,
2273                                                 NULL);
2274                         if (err)
2275                                 return err;
2276                 }
2277
2278                 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
2279                         vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2280                         is_vlan = 1;
2281                 }
2282         }
2283         ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
2284
2285         if (!is_eth) {
2286                 sqp->ud_header.lrh.service_level =
2287                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2288                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2289                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2290         }
2291
2292         if (is_grh) {
2293                 sqp->ud_header.grh.traffic_class =
2294                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2295                 sqp->ud_header.grh.flow_label    =
2296                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2297                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
2298                 if (is_eth)
2299                         memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2300                 else {
2301                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2302                         /* When multi-function is enabled, the ib_core gid
2303                          * indexes don't necessarily match the hw ones, so
2304                          * we must use our own cache */
2305                         sqp->ud_header.grh.source_gid.global.subnet_prefix =
2306                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2307                                                        subnet_prefix;
2308                         sqp->ud_header.grh.source_gid.global.interface_id =
2309                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2310                                                guid_cache[ah->av.ib.gid_index];
2311                 } else
2312                         ib_get_cached_gid(ib_dev,
2313                                           be32_to_cpu(ah->av.ib.port_pd) >> 24,
2314                                           ah->av.ib.gid_index,
2315                                           &sqp->ud_header.grh.source_gid, NULL);
2316                 }
2317                 memcpy(sqp->ud_header.grh.destination_gid.raw,
2318                        ah->av.ib.dgid, 16);
2319         }
2320
2321         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2322
2323         if (!is_eth) {
2324                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2325                                           (sqp->ud_header.lrh.destination_lid ==
2326                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2327                                           (sqp->ud_header.lrh.service_level << 8));
2328                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2329                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
2330                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2331         }
2332
2333         switch (wr->opcode) {
2334         case IB_WR_SEND:
2335                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2336                 sqp->ud_header.immediate_present = 0;
2337                 break;
2338         case IB_WR_SEND_WITH_IMM:
2339                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2340                 sqp->ud_header.immediate_present = 1;
2341                 sqp->ud_header.immediate_data    = wr->ex.imm_data;
2342                 break;
2343         default:
2344                 return -EINVAL;
2345         }
2346
2347         if (is_eth) {
2348                 struct in6_addr in6;
2349
2350                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2351
2352                 mlx->sched_prio = cpu_to_be16(pcp);
2353
2354                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2355                 /* FIXME: cache smac value? */
2356                 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2357                 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2358                 memcpy(&in6, sgid.raw, sizeof(in6));
2359
2360                 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2361                         u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
2362                         u8 smac[ETH_ALEN];
2363
2364                         mlx4_u64_to_smac(smac, mac);
2365                         memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
2366                 } else {
2367                         /* use the src mac of the tunnel */
2368                         memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
2369                 }
2370
2371                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2372                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2373                 if (!is_vlan) {
2374                         sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2375                 } else {
2376                         sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2377                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2378                 }
2379         } else {
2380                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
2381                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2382                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2383         }
2384         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2385         if (!sqp->qp.ibqp.qp_num)
2386                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2387         else
2388                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
2389         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2390         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2391         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2392         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
2393                                                sqp->qkey : wr->wr.ud.remote_qkey);
2394         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2395
2396         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2397
2398         if (0) {
2399                 pr_err("built UD header of size %d:\n", header_size);
2400                 for (i = 0; i < header_size / 4; ++i) {
2401                         if (i % 8 == 0)
2402                                 pr_err("  [%02x] ", i * 4);
2403                         pr_cont(" %08x",
2404                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2405                         if ((i + 1) % 8 == 0)
2406                                 pr_cont("\n");
2407                 }
2408                 pr_err("\n");
2409         }
2410
2411         /*
2412          * Inline data segments may not cross a 64 byte boundary.  If
2413          * our UD header is bigger than the space available up to the
2414          * next 64 byte boundary in the WQE, use two inline data
2415          * segments to hold the UD header.
2416          */
2417         spc = MLX4_INLINE_ALIGN -
2418                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2419         if (header_size <= spc) {
2420                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2421                 memcpy(inl + 1, sqp->header_buf, header_size);
2422                 i = 1;
2423         } else {
2424                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2425                 memcpy(inl + 1, sqp->header_buf, spc);
2426
2427                 inl = (void *) (inl + 1) + spc;
2428                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2429                 /*
2430                  * Need a barrier here to make sure all the data is
2431                  * visible before the byte_count field is set.
2432                  * Otherwise the HCA prefetcher could grab the 64-byte
2433                  * chunk with this inline segment and get a valid (!=
2434                  * 0xffffffff) byte count but stale data, and end up
2435                  * generating a packet with bad headers.
2436                  *
2437                  * The first inline segment's byte_count field doesn't
2438                  * need a barrier, because it comes after a
2439                  * control/MLX segment and therefore is at an offset
2440                  * of 16 mod 64.
2441                  */
2442                 wmb();
2443                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2444                 i = 2;
2445         }
2446
2447         *mlx_seg_len =
2448                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2449         return 0;
2450 }
2451
2452 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2453 {
2454         unsigned cur;
2455         struct mlx4_ib_cq *cq;
2456
2457         cur = wq->head - wq->tail;
2458         if (likely(cur + nreq < wq->max_post))
2459                 return 0;
2460
2461         cq = to_mcq(ib_cq);
2462         spin_lock(&cq->lock);
2463         cur = wq->head - wq->tail;
2464         spin_unlock(&cq->lock);
2465
2466         return cur + nreq >= wq->max_post;
2467 }
2468
2469 static __be32 convert_access(int acc)
2470 {
2471         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2472                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
2473                (acc & IB_ACCESS_REMOTE_WRITE  ?
2474                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2475                (acc & IB_ACCESS_REMOTE_READ   ?
2476                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
2477                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
2478                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2479 }
2480
2481 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
2482 {
2483         struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
2484         int i;
2485
2486         for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2487                 mfrpl->mapped_page_list[i] =
2488                         cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
2489                                     MLX4_MTT_FLAG_PRESENT);
2490
2491         fseg->flags             = convert_access(wr->wr.fast_reg.access_flags);
2492         fseg->mem_key           = cpu_to_be32(wr->wr.fast_reg.rkey);
2493         fseg->buf_list          = cpu_to_be64(mfrpl->map);
2494         fseg->start_addr        = cpu_to_be64(wr->wr.fast_reg.iova_start);
2495         fseg->reg_len           = cpu_to_be64(wr->wr.fast_reg.length);
2496         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
2497         fseg->page_size         = cpu_to_be32(wr->wr.fast_reg.page_shift);
2498         fseg->reserved[0]       = 0;
2499         fseg->reserved[1]       = 0;
2500 }
2501
2502 static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr)
2503 {
2504         bseg->flags1 =
2505                 convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) &
2506                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  |
2507                             MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2508                             MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2509         bseg->flags2 = 0;
2510         if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2)
2511                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2512         if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED)
2513                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2514         bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey);
2515         bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey);
2516         bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr);
2517         bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length);
2518 }
2519
2520 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2521 {
2522         memset(iseg, 0, sizeof(*iseg));
2523         iseg->mem_key = cpu_to_be32(rkey);
2524 }
2525
2526 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2527                                           u64 remote_addr, u32 rkey)
2528 {
2529         rseg->raddr    = cpu_to_be64(remote_addr);
2530         rseg->rkey     = cpu_to_be32(rkey);
2531         rseg->reserved = 0;
2532 }
2533
2534 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
2535 {
2536         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2537                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2538                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
2539         } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2540                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2541                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2542         } else {
2543                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2544                 aseg->compare  = 0;
2545         }
2546
2547 }
2548
2549 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2550                                   struct ib_send_wr *wr)
2551 {
2552         aseg->swap_add          = cpu_to_be64(wr->wr.atomic.swap);
2553         aseg->swap_add_mask     = cpu_to_be64(wr->wr.atomic.swap_mask);
2554         aseg->compare           = cpu_to_be64(wr->wr.atomic.compare_add);
2555         aseg->compare_mask      = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2556 }
2557
2558 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2559                              struct ib_send_wr *wr)
2560 {
2561         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
2562         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2563         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2564         dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
2565         memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
2566 }
2567
2568 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2569                                     struct mlx4_wqe_datagram_seg *dseg,
2570                                     struct ib_send_wr *wr,
2571                                     enum mlx4_ib_qp_type qpt)
2572 {
2573         union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2574         struct mlx4_av sqp_av = {0};
2575         int port = *((u8 *) &av->ib.port_pd) & 0x3;
2576
2577         /* force loopback */
2578         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2579         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2580         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2581                         cpu_to_be32(0xf0000000);
2582
2583         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2584         if (qpt == MLX4_IB_QPT_PROXY_GSI)
2585                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2586         else
2587                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
2588         /* Use QKEY from the QP context, which is set by master */
2589         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2590 }
2591
2592 static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2593 {
2594         struct mlx4_wqe_inline_seg *inl = wqe;
2595         struct mlx4_ib_tunnel_header hdr;
2596         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2597         int spc;
2598         int i;
2599
2600         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2601         hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2602         hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2603         hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2604         memcpy(hdr.mac, ah->av.eth.mac, 6);
2605         hdr.vlan = ah->av.eth.vlan;
2606
2607         spc = MLX4_INLINE_ALIGN -
2608                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2609         if (sizeof (hdr) <= spc) {
2610                 memcpy(inl + 1, &hdr, sizeof (hdr));
2611                 wmb();
2612                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2613                 i = 1;
2614         } else {
2615                 memcpy(inl + 1, &hdr, spc);
2616                 wmb();
2617                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2618
2619                 inl = (void *) (inl + 1) + spc;
2620                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2621                 wmb();
2622                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2623                 i = 2;
2624         }
2625
2626         *mlx_seg_len =
2627                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2628 }
2629
2630 static void set_mlx_icrc_seg(void *dseg)
2631 {
2632         u32 *t = dseg;
2633         struct mlx4_wqe_inline_seg *iseg = dseg;
2634
2635         t[1] = 0;
2636
2637         /*
2638          * Need a barrier here before writing the byte_count field to
2639          * make sure that all the data is visible before the
2640          * byte_count field is set.  Otherwise, if the segment begins
2641          * a new cacheline, the HCA prefetcher could grab the 64-byte
2642          * chunk and get a valid (!= * 0xffffffff) byte count but
2643          * stale data, and end up sending the wrong data.
2644          */
2645         wmb();
2646
2647         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2648 }
2649
2650 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2651 {
2652         dseg->lkey       = cpu_to_be32(sg->lkey);
2653         dseg->addr       = cpu_to_be64(sg->addr);
2654
2655         /*
2656          * Need a barrier here before writing the byte_count field to
2657          * make sure that all the data is visible before the
2658          * byte_count field is set.  Otherwise, if the segment begins
2659          * a new cacheline, the HCA prefetcher could grab the 64-byte
2660          * chunk and get a valid (!= * 0xffffffff) byte count but
2661          * stale data, and end up sending the wrong data.
2662          */
2663         wmb();
2664
2665         dseg->byte_count = cpu_to_be32(sg->length);
2666 }
2667
2668 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2669 {
2670         dseg->byte_count = cpu_to_be32(sg->length);
2671         dseg->lkey       = cpu_to_be32(sg->lkey);
2672         dseg->addr       = cpu_to_be64(sg->addr);
2673 }
2674
2675 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
2676                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2677                          __be32 *lso_hdr_sz, __be32 *blh)
2678 {
2679         unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2680
2681         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2682                 *blh = cpu_to_be32(1 << 6);
2683
2684         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2685                      wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2686                 return -EINVAL;
2687
2688         memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2689
2690         *lso_hdr_sz  = cpu_to_be32(wr->wr.ud.mss << 16 | wr->wr.ud.hlen);
2691         *lso_seg_len = halign;
2692         return 0;
2693 }
2694
2695 static __be32 send_ieth(struct ib_send_wr *wr)
2696 {
2697         switch (wr->opcode) {
2698         case IB_WR_SEND_WITH_IMM:
2699         case IB_WR_RDMA_WRITE_WITH_IMM:
2700                 return wr->ex.imm_data;
2701
2702         case IB_WR_SEND_WITH_INV:
2703                 return cpu_to_be32(wr->ex.invalidate_rkey);
2704
2705         default:
2706                 return 0;
2707         }
2708 }
2709
2710 static void add_zero_len_inline(void *wqe)
2711 {
2712         struct mlx4_wqe_inline_seg *inl = wqe;
2713         memset(wqe, 0, 16);
2714         inl->byte_count = cpu_to_be32(1 << 31);
2715 }
2716
2717 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2718                       struct ib_send_wr **bad_wr)
2719 {
2720         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2721         void *wqe;
2722         struct mlx4_wqe_ctrl_seg *ctrl;
2723         struct mlx4_wqe_data_seg *dseg;
2724         unsigned long flags;
2725         int nreq;
2726         int err = 0;
2727         unsigned ind;
2728         int uninitialized_var(stamp);
2729         int uninitialized_var(size);
2730         unsigned uninitialized_var(seglen);
2731         __be32 dummy;
2732         __be32 *lso_wqe;
2733         __be32 uninitialized_var(lso_hdr_sz);
2734         __be32 blh;
2735         int i;
2736         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2737
2738         spin_lock_irqsave(&qp->sq.lock, flags);
2739         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2740                 err = -EIO;
2741                 *bad_wr = wr;
2742                 nreq = 0;
2743                 goto out;
2744         }
2745
2746         ind = qp->sq_next_wqe;
2747
2748         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2749                 lso_wqe = &dummy;
2750                 blh = 0;
2751
2752                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2753                         err = -ENOMEM;
2754                         *bad_wr = wr;
2755                         goto out;
2756                 }
2757
2758                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2759                         err = -EINVAL;
2760                         *bad_wr = wr;
2761                         goto out;
2762                 }
2763
2764                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
2765                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
2766
2767                 ctrl->srcrb_flags =
2768                         (wr->send_flags & IB_SEND_SIGNALED ?
2769                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2770                         (wr->send_flags & IB_SEND_SOLICITED ?
2771                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
2772                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
2773                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2774                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
2775                         qp->sq_signal_bits;
2776
2777                 ctrl->imm = send_ieth(wr);
2778
2779                 wqe += sizeof *ctrl;
2780                 size = sizeof *ctrl / 16;
2781
2782                 switch (qp->mlx4_ib_qp_type) {
2783                 case MLX4_IB_QPT_RC:
2784                 case MLX4_IB_QPT_UC:
2785                         switch (wr->opcode) {
2786                         case IB_WR_ATOMIC_CMP_AND_SWP:
2787                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2788                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
2789                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2790                                               wr->wr.atomic.rkey);
2791                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2792
2793                                 set_atomic_seg(wqe, wr);
2794                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
2795
2796                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2797                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
2798
2799                                 break;
2800
2801                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2802                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2803                                               wr->wr.atomic.rkey);
2804                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2805
2806                                 set_masked_atomic_seg(wqe, wr);
2807                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
2808
2809                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2810                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
2811
2812                                 break;
2813
2814                         case IB_WR_RDMA_READ:
2815                         case IB_WR_RDMA_WRITE:
2816                         case IB_WR_RDMA_WRITE_WITH_IMM:
2817                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2818                                               wr->wr.rdma.rkey);
2819                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2820                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
2821                                 break;
2822
2823                         case IB_WR_LOCAL_INV:
2824                                 ctrl->srcrb_flags |=
2825                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2826                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2827                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
2828                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2829                                 break;
2830
2831                         case IB_WR_FAST_REG_MR:
2832                                 ctrl->srcrb_flags |=
2833                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2834                                 set_fmr_seg(wqe, wr);
2835                                 wqe  += sizeof (struct mlx4_wqe_fmr_seg);
2836                                 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2837                                 break;
2838
2839                         case IB_WR_BIND_MW:
2840                                 ctrl->srcrb_flags |=
2841                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2842                                 set_bind_seg(wqe, wr);
2843                                 wqe  += sizeof(struct mlx4_wqe_bind_seg);
2844                                 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2845                                 break;
2846                         default:
2847                                 /* No extra segments required for sends */
2848                                 break;
2849                         }
2850                         break;
2851
2852                 case MLX4_IB_QPT_TUN_SMI_OWNER:
2853                         err =  build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2854                         if (unlikely(err)) {
2855                                 *bad_wr = wr;
2856                                 goto out;
2857                         }
2858                         wqe  += seglen;
2859                         size += seglen / 16;
2860                         break;
2861                 case MLX4_IB_QPT_TUN_SMI:
2862                 case MLX4_IB_QPT_TUN_GSI:
2863                         /* this is a UD qp used in MAD responses to slaves. */
2864                         set_datagram_seg(wqe, wr);
2865                         /* set the forced-loopback bit in the data seg av */
2866                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2867                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2868                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2869                         break;
2870                 case MLX4_IB_QPT_UD:
2871                         set_datagram_seg(wqe, wr);
2872                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2873                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2874
2875                         if (wr->opcode == IB_WR_LSO) {
2876                                 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
2877                                 if (unlikely(err)) {
2878                                         *bad_wr = wr;
2879                                         goto out;
2880                                 }
2881                                 lso_wqe = (__be32 *) wqe;
2882                                 wqe  += seglen;
2883                                 size += seglen / 16;
2884                         }
2885                         break;
2886
2887                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
2888                         err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2889                         if (unlikely(err)) {
2890                                 *bad_wr = wr;
2891                                 goto out;
2892                         }
2893                         wqe  += seglen;
2894                         size += seglen / 16;
2895                         /* to start tunnel header on a cache-line boundary */
2896                         add_zero_len_inline(wqe);
2897                         wqe += 16;
2898                         size++;
2899                         build_tunnel_header(wr, wqe, &seglen);
2900                         wqe  += seglen;
2901                         size += seglen / 16;
2902                         break;
2903                 case MLX4_IB_QPT_PROXY_SMI:
2904                 case MLX4_IB_QPT_PROXY_GSI:
2905                         /* If we are tunneling special qps, this is a UD qp.
2906                          * In this case we first add a UD segment targeting
2907                          * the tunnel qp, and then add a header with address
2908                          * information */
2909                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr,
2910                                                 qp->mlx4_ib_qp_type);
2911                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2912                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2913                         build_tunnel_header(wr, wqe, &seglen);
2914                         wqe  += seglen;
2915                         size += seglen / 16;
2916                         break;
2917
2918                 case MLX4_IB_QPT_SMI:
2919                 case MLX4_IB_QPT_GSI:
2920                         err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2921                         if (unlikely(err)) {
2922                                 *bad_wr = wr;
2923                                 goto out;
2924                         }
2925                         wqe  += seglen;
2926                         size += seglen / 16;
2927                         break;
2928
2929                 default:
2930                         break;
2931                 }
2932
2933                 /*
2934                  * Write data segments in reverse order, so as to
2935                  * overwrite cacheline stamp last within each
2936                  * cacheline.  This avoids issues with WQE
2937                  * prefetching.
2938                  */
2939
2940                 dseg = wqe;
2941                 dseg += wr->num_sge - 1;
2942                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
2943
2944                 /* Add one more inline data segment for ICRC for MLX sends */
2945                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2946                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2947                              qp->mlx4_ib_qp_type &
2948                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
2949                         set_mlx_icrc_seg(dseg + 1);
2950                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
2951                 }
2952
2953                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2954                         set_data_seg(dseg, wr->sg_list + i);
2955
2956                 /*
2957                  * Possibly overwrite stamping in cacheline with LSO
2958                  * segment only after making sure all data segments
2959                  * are written.
2960                  */
2961                 wmb();
2962                 *lso_wqe = lso_hdr_sz;
2963
2964                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2965                                     MLX4_WQE_CTRL_FENCE : 0) | size;
2966
2967                 /*
2968                  * Make sure descriptor is fully written before
2969                  * setting ownership bit (because HW can start
2970                  * executing as soon as we do).
2971                  */
2972                 wmb();
2973
2974                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
2975                         *bad_wr = wr;
2976                         err = -EINVAL;
2977                         goto out;
2978                 }
2979
2980                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
2981                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
2982
2983                 stamp = ind + qp->sq_spare_wqes;
2984                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2985
2986                 /*
2987                  * We can improve latency by not stamping the last
2988                  * send queue WQE until after ringing the doorbell, so
2989                  * only stamp here if there are still more WQEs to post.
2990                  *
2991                  * Same optimization applies to padding with NOP wqe
2992                  * in case of WQE shrinking (used to prevent wrap-around
2993                  * in the middle of WR).
2994                  */
2995                 if (wr->next) {
2996                         stamp_send_wqe(qp, stamp, size * 16);
2997                         ind = pad_wraparound(qp, ind);
2998                 }
2999         }
3000
3001 out:
3002         if (likely(nreq)) {
3003                 qp->sq.head += nreq;
3004
3005                 /*
3006                  * Make sure that descriptors are written before
3007                  * doorbell record.
3008                  */
3009                 wmb();
3010
3011                 writel(qp->doorbell_qpn,
3012                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3013
3014                 /*
3015                  * Make sure doorbells don't leak out of SQ spinlock
3016                  * and reach the HCA out of order.
3017                  */
3018                 mmiowb();
3019
3020                 stamp_send_wqe(qp, stamp, size * 16);
3021
3022                 ind = pad_wraparound(qp, ind);
3023                 qp->sq_next_wqe = ind;
3024         }
3025
3026         spin_unlock_irqrestore(&qp->sq.lock, flags);
3027
3028         return err;
3029 }
3030
3031 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3032                       struct ib_recv_wr **bad_wr)
3033 {
3034         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3035         struct mlx4_wqe_data_seg *scat;
3036         unsigned long flags;
3037         int err = 0;
3038         int nreq;
3039         int ind;
3040         int max_gs;
3041         int i;
3042         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3043
3044         max_gs = qp->rq.max_gs;
3045         spin_lock_irqsave(&qp->rq.lock, flags);
3046
3047         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3048                 err = -EIO;
3049                 *bad_wr = wr;
3050                 nreq = 0;
3051                 goto out;
3052         }
3053
3054         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3055
3056         for (nreq = 0; wr; ++nreq, wr = wr->next) {
3057                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3058                         err = -ENOMEM;
3059                         *bad_wr = wr;
3060                         goto out;
3061                 }
3062
3063                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3064                         err = -EINVAL;
3065                         *bad_wr = wr;
3066                         goto out;
3067                 }
3068
3069                 scat = get_recv_wqe(qp, ind);
3070
3071                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3072                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3073                         ib_dma_sync_single_for_device(ibqp->device,
3074                                                       qp->sqp_proxy_rcv[ind].map,
3075                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
3076                                                       DMA_FROM_DEVICE);
3077                         scat->byte_count =
3078                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3079                         /* use dma lkey from upper layer entry */
3080                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3081                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3082                         scat++;
3083                         max_gs--;
3084                 }
3085
3086                 for (i = 0; i < wr->num_sge; ++i)
3087                         __set_data_seg(scat + i, wr->sg_list + i);
3088
3089                 if (i < max_gs) {
3090                         scat[i].byte_count = 0;
3091                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
3092                         scat[i].addr       = 0;
3093                 }
3094
3095                 qp->rq.wrid[ind] = wr->wr_id;
3096
3097                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3098         }
3099
3100 out:
3101         if (likely(nreq)) {
3102                 qp->rq.head += nreq;
3103
3104                 /*
3105                  * Make sure that descriptors are written before
3106                  * doorbell record.
3107                  */
3108                 wmb();
3109
3110                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3111         }
3112
3113         spin_unlock_irqrestore(&qp->rq.lock, flags);
3114
3115         return err;
3116 }
3117
3118 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3119 {
3120         switch (mlx4_state) {
3121         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
3122         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
3123         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
3124         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
3125         case MLX4_QP_STATE_SQ_DRAINING:
3126         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
3127         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
3128         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
3129         default:                     return -1;
3130         }
3131 }
3132
3133 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3134 {
3135         switch (mlx4_mig_state) {
3136         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
3137         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
3138         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
3139         default: return -1;
3140         }
3141 }
3142
3143 static int to_ib_qp_access_flags(int mlx4_flags)
3144 {
3145         int ib_flags = 0;
3146
3147         if (mlx4_flags & MLX4_QP_BIT_RRE)
3148                 ib_flags |= IB_ACCESS_REMOTE_READ;
3149         if (mlx4_flags & MLX4_QP_BIT_RWE)
3150                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3151         if (mlx4_flags & MLX4_QP_BIT_RAE)
3152                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3153
3154         return ib_flags;
3155 }
3156
3157 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3158                                 struct mlx4_qp_path *path)
3159 {
3160         struct mlx4_dev *dev = ibdev->dev;
3161         int is_eth;
3162
3163         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
3164         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
3165
3166         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3167                 return;
3168
3169         is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3170                 IB_LINK_LAYER_ETHERNET;
3171         if (is_eth)
3172                 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3173                 ((path->sched_queue & 4) << 1);
3174         else
3175                 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3176
3177         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
3178         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3179         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
3180         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3181         if (ib_ah_attr->ah_flags) {
3182                 ib_ah_attr->grh.sgid_index = path->mgid_index;
3183                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
3184                 ib_ah_attr->grh.traffic_class =
3185                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3186                 ib_ah_attr->grh.flow_label =
3187                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3188                 memcpy(ib_ah_attr->grh.dgid.raw,
3189                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3190         }
3191 }
3192
3193 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3194                      struct ib_qp_init_attr *qp_init_attr)
3195 {
3196         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3197         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3198         struct mlx4_qp_context context;
3199         int mlx4_state;
3200         int err = 0;
3201
3202         mutex_lock(&qp->mutex);
3203
3204         if (qp->state == IB_QPS_RESET) {
3205                 qp_attr->qp_state = IB_QPS_RESET;
3206                 goto done;
3207         }
3208
3209         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3210         if (err) {
3211                 err = -EINVAL;
3212                 goto out;
3213         }
3214
3215         mlx4_state = be32_to_cpu(context.flags) >> 28;
3216
3217         qp->state                    = to_ib_qp_state(mlx4_state);
3218         qp_attr->qp_state            = qp->state;
3219         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
3220         qp_attr->path_mig_state      =
3221                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3222         qp_attr->qkey                = be32_to_cpu(context.qkey);
3223         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3224         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
3225         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
3226         qp_attr->qp_access_flags     =
3227                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3228
3229         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3230                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3231                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3232                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3233                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
3234         }
3235
3236         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3237         if (qp_attr->qp_state == IB_QPS_INIT)
3238                 qp_attr->port_num = qp->port;
3239         else
3240                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3241
3242         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3243         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3244
3245         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3246
3247         qp_attr->max_dest_rd_atomic =
3248                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3249         qp_attr->min_rnr_timer      =
3250                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3251         qp_attr->timeout            = context.pri_path.ackto >> 3;
3252         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
3253         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
3254         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
3255
3256 done:
3257         qp_attr->cur_qp_state        = qp_attr->qp_state;
3258         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
3259         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
3260
3261         if (!ibqp->uobject) {
3262                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
3263                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3264         } else {
3265                 qp_attr->cap.max_send_wr  = 0;
3266                 qp_attr->cap.max_send_sge = 0;
3267         }
3268
3269         /*
3270          * We don't support inline sends for kernel QPs (yet), and we
3271          * don't know what userspace's value should be.
3272          */
3273         qp_attr->cap.max_inline_data = 0;
3274
3275         qp_init_attr->cap            = qp_attr->cap;
3276
3277         qp_init_attr->create_flags = 0;
3278         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3279                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3280
3281         if (qp->flags & MLX4_IB_QP_LSO)
3282                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3283
3284         if (qp->flags & MLX4_IB_QP_NETIF)
3285                 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3286
3287         qp_init_attr->sq_sig_type =
3288                 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3289                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3290
3291 out:
3292         mutex_unlock(&qp->mutex);
3293         return err;
3294 }
3295