drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/slab.h>
  36 #include <linux/netdevice.h>
  37
  38 #include <rdma/ib_cache.h>
  39 #include <rdma/ib_pack.h>
  40 #include <rdma/ib_addr.h>
  41 #include <rdma/ib_mad.h>
  42
  43 #include <linux/mlx4/qp.h>
  44
  45 #include "mlx4_ib.h"
  46 #include "user.h"
  47
  48 enum {
  49         MLX4_IB_ACK_REQ_FREQ    = 8,
  50 };
  51
  52 enum {
  53         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  54         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  55         MLX4_IB_LINK_TYPE_IB            = 0,
  56         MLX4_IB_LINK_TYPE_ETH           = 1
  57 };
  58
  59 enum {
  60         /*
  61          * Largest possible UD header: send with GRH and immediate
  62          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  63          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  64          * biggest case)
  65          */
  66         MLX4_IB_UD_HEADER_SIZE          = 82,
  67         MLX4_IB_LSO_HEADER_SPARE        = 128,
  68 };
  69
  70 enum {
  71         MLX4_IB_IBOE_ETHERTYPE          = 0x8915
  72 };
  73
  74 struct mlx4_ib_sqp {
  75         struct mlx4_ib_qp       qp;
  76         int                     pkey_index;
  77         u32                     qkey;
  78         u32                     send_psn;
  79         struct ib_ud_header     ud_header;
  80         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  81 };
  82
  83 enum {
  84         MLX4_IB_MIN_SQ_STRIDE   = 6,
  85         MLX4_IB_CACHE_LINE_SIZE = 64,
  86 };
  87
  88 enum {
  89         MLX4_RAW_QP_MTU         = 7,
  90         MLX4_RAW_QP_MSGMAX      = 31,
  91 };
  92
  93 static const __be32 mlx4_ib_opcode[] = {
  94         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
  95         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
  96         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
  97         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
  98         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
  99         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 100         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 101         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 102         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 103         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 104         [IB_WR_FAST_REG_MR]                     = cpu_to_be32(MLX4_OPCODE_FMR),
 105         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 106         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 107 };
 108
 109 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 110 {
 111         return container_of(mqp, struct mlx4_ib_sqp, qp);
 112 }
 113
 114 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 115 {
 116         if (!mlx4_is_master(dev->dev))
 117                 return 0;
 118
 119         return qp->mqp.qpn >= dev->dev->caps.base_sqpn &&
 120                qp->mqp.qpn < dev->dev->caps.base_sqpn +
 121                8 + 16 * MLX4_MFUNC_MAX;
 122 }
 123
 124 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 125 {
 126         return ((mlx4_is_master(dev->dev) &&
 127                  qp->mqp.qpn >= dev->dev->caps.base_sqpn &&
 128                  qp->mqp.qpn <= dev->dev->caps.base_sqpn + 3) ||
 129                 (qp->mqp.qpn >= dev->dev->caps.sqp_start &&
 130                  qp->mqp.qpn <= dev->dev->caps.sqp_start + 3));
 131 }
 132
 133 /* used for INIT/CLOSE port logic */
 134 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 135 {
 136         int qp0;
 137
 138         /* qp0 is either the proxy qp0, or the real qp0 */
 139         qp0 = (qp->mqp.qpn >= dev->dev->caps.sqp_start &&
 140                 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1) ||
 141                 (mlx4_is_master(dev->dev) &&
 142                  qp->mqp.qpn >= dev->dev->caps.base_sqpn &&
 143                  qp->mqp.qpn <= dev->dev->caps.base_sqpn + 1);
 144
 145         return qp0;
 146 }
 147
 148 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 149 {
 150         return mlx4_buf_offset(&qp->buf, offset);
 151 }
 152
 153 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 154 {
 155         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 156 }
 157
 158 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 159 {
 160         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 161 }
 162
 163 /*
 164  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 165  * first four bytes of every 64 byte chunk with
 166  *     0x7FFFFFF | (invalid_ownership_value << 31).
 167  *
 168  * When the max work request size is less than or equal to the WQE
 169  * basic block size, as an optimization, we can stamp all WQEs with
 170  * 0xffffffff, and skip the very first chunk of each WQE.
 171  */
 172 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 173 {
 174         __be32 *wqe;
 175         int i;
 176         int s;
 177         int ind;
 178         void *buf;
 179         __be32 stamp;
 180         struct mlx4_wqe_ctrl_seg *ctrl;
 181
 182         if (qp->sq_max_wqes_per_wr > 1) {
 183                 s = roundup(size, 1U << qp->sq.wqe_shift);
 184                 for (i = 0; i < s; i += 64) {
 185                         ind = (i >> qp->sq.wqe_shift) + n;
 186                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 187                                                        cpu_to_be32(0xffffffff);
 188                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 189                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 190                         *wqe = stamp;
 191                 }
 192         } else {
 193                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 194                 s = (ctrl->fence_size & 0x3f) << 4;
 195                 for (i = 64; i < s; i += 64) {
 196                         wqe = buf + i;
 197                         *wqe = cpu_to_be32(0xffffffff);
 198                 }
 199         }
 200 }
 201
 202 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 203 {
 204         struct mlx4_wqe_ctrl_seg *ctrl;
 205         struct mlx4_wqe_inline_seg *inl;
 206         void *wqe;
 207         int s;
 208
 209         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 210         s = sizeof(struct mlx4_wqe_ctrl_seg);
 211
 212         if (qp->ibqp.qp_type == IB_QPT_UD) {
 213                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 214                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 215                 memset(dgram, 0, sizeof *dgram);
 216                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 217                 s += sizeof(struct mlx4_wqe_datagram_seg);
 218         }
 219
 220         /* Pad the remainder of the WQE with an inline data segment. */
 221         if (size > s) {
 222                 inl = wqe + s;
 223                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 224         }
 225         ctrl->srcrb_flags = 0;
 226         ctrl->fence_size = size / 16;
 227         /*
 228          * Make sure descriptor is fully written before setting ownership bit
 229          * (because HW can start executing as soon as we do).
 230          */
 231         wmb();
 232
 233         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 234                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 235
 236         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 237 }
 238
 239 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 240 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 241 {
 242         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 243         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 244                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 245                 ind += s;
 246         }
 247         return ind;
 248 }
 249
 250 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 251 {
 252         struct ib_event event;
 253         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 254
 255         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 256                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 257
 258         if (ibqp->event_handler) {
 259                 event.device     = ibqp->device;
 260                 event.element.qp = ibqp;
 261                 switch (type) {
 262                 case MLX4_EVENT_TYPE_PATH_MIG:
 263                         event.event = IB_EVENT_PATH_MIG;
 264                         break;
 265                 case MLX4_EVENT_TYPE_COMM_EST:
 266                         event.event = IB_EVENT_COMM_EST;
 267                         break;
 268                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 269                         event.event = IB_EVENT_SQ_DRAINED;
 270                         break;
 271                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 272                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 273                         break;
 274                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 275                         event.event = IB_EVENT_QP_FATAL;
 276                         break;
 277                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 278                         event.event = IB_EVENT_PATH_MIG_ERR;
 279                         break;
 280                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 281                         event.event = IB_EVENT_QP_REQ_ERR;
 282                         break;
 283                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 284                         event.event = IB_EVENT_QP_ACCESS_ERR;
 285                         break;
 286                 default:
 287                         pr_warn("Unexpected event type %d "
 288                                "on QP %06x\n", type, qp->qpn);
 289                         return;
 290                 }
 291
 292                 ibqp->event_handler(&event, ibqp->qp_context);
 293         }
 294 }
 295
 296 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 297 {
 298         /*
 299          * UD WQEs must have a datagram segment.
 300          * RC and UC WQEs might have a remote address segment.
 301          * MLX WQEs need two extra inline data segments (for the UD
 302          * header and space for the ICRC).
 303          */
 304         switch (type) {
 305         case MLX4_IB_QPT_UD:
 306                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 307                         sizeof (struct mlx4_wqe_datagram_seg) +
 308                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 309         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 310         case MLX4_IB_QPT_PROXY_SMI:
 311         case MLX4_IB_QPT_PROXY_GSI:
 312                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 313                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 314         case MLX4_IB_QPT_TUN_SMI_OWNER:
 315         case MLX4_IB_QPT_TUN_GSI:
 316                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 317                         sizeof (struct mlx4_wqe_datagram_seg);
 318
 319         case MLX4_IB_QPT_UC:
 320                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 321                         sizeof (struct mlx4_wqe_raddr_seg);
 322         case MLX4_IB_QPT_RC:
 323                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 324                         sizeof (struct mlx4_wqe_atomic_seg) +
 325                         sizeof (struct mlx4_wqe_raddr_seg);
 326         case MLX4_IB_QPT_SMI:
 327         case MLX4_IB_QPT_GSI:
 328                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 329                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 330                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 331                                            MLX4_INLINE_ALIGN) *
 332                               sizeof (struct mlx4_wqe_inline_seg),
 333                               sizeof (struct mlx4_wqe_data_seg)) +
 334                         ALIGN(4 +
 335                               sizeof (struct mlx4_wqe_inline_seg),
 336                               sizeof (struct mlx4_wqe_data_seg));
 337         default:
 338                 return sizeof (struct mlx4_wqe_ctrl_seg);
 339         }
 340 }
 341
 342 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 343                        int is_user, int has_rq, struct mlx4_ib_qp *qp)
 344 {
 345         /* Sanity check RQ size before proceeding */
 346         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 347             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 348                 return -EINVAL;
 349
 350         if (!has_rq) {
 351                 if (cap->max_recv_wr)
 352                         return -EINVAL;
 353
 354                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 355         } else {
 356                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 357                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 358                         return -EINVAL;
 359
 360                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 361                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 362                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 363         }
 364
 365         /* leave userspace return values as they were, so as not to break ABI */
 366         if (is_user) {
 367                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 368                 cap->max_recv_sge = qp->rq.max_gs;
 369         } else {
 370                 cap->max_recv_wr  = qp->rq.max_post =
 371                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 372                 cap->max_recv_sge = min(qp->rq.max_gs,
 373                                         min(dev->dev->caps.max_sq_sg,
 374                                             dev->dev->caps.max_rq_sg));
 375         }
 376
 377         return 0;
 378 }
 379
 380 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 381                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
 382 {
 383         int s;
 384
 385         /* Sanity check SQ size before proceeding */
 386         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 387             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 388             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 389             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 390                 return -EINVAL;
 391
 392         /*
 393          * For MLX transport we need 2 extra S/G entries:
 394          * one for the header and one for the checksum at the end
 395          */
 396         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 397              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 398             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 399                 return -EINVAL;
 400
 401         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 402                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 403                 send_wqe_overhead(type, qp->flags);
 404
 405         if (s > dev->dev->caps.max_sq_desc_sz)
 406                 return -EINVAL;
 407
 408         /*
 409          * Hermon supports shrinking WQEs, such that a single work
 410          * request can include multiple units of 1 << wqe_shift.  This
 411          * way, work requests can differ in size, and do not have to
 412          * be a power of 2 in size, saving memory and speeding up send
 413          * WR posting.  Unfortunately, if we do this then the
 414          * wqe_index field in CQEs can't be used to look up the WR ID
 415          * anymore, so we do this only if selective signaling is off.
 416          *
 417          * Further, on 32-bit platforms, we can't use vmap() to make
 418          * the QP buffer virtually contiguous.  Thus we have to use
 419          * constant-sized WRs to make sure a WR is always fully within
 420          * a single page-sized chunk.
 421          *
 422          * Finally, we use NOP work requests to pad the end of the
 423          * work queue, to avoid wrap-around in the middle of WR.  We
 424          * set NEC bit to avoid getting completions with error for
 425          * these NOP WRs, but since NEC is only supported starting
 426          * with firmware 2.2.232, we use constant-sized WRs for older
 427          * firmware.
 428          *
 429          * And, since MLX QPs only support SEND, we use constant-sized
 430          * WRs in this case.
 431          *
 432          * We look for the smallest value of wqe_shift such that the
 433          * resulting number of wqes does not exceed device
 434          * capabilities.
 435          *
 436          * We set WQE size to at least 64 bytes, this way stamping
 437          * invalidates each WQE.
 438          */
 439         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 440             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 441             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
 442             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
 443                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
 444                 qp->sq.wqe_shift = ilog2(64);
 445         else
 446                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 447
 448         for (;;) {
 449                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 450
 451                 /*
 452                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 453                  * allow HW to prefetch.
 454                  */
 455                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 456                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 457                                                     qp->sq_max_wqes_per_wr +
 458                                                     qp->sq_spare_wqes);
 459
 460                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 461                         break;
 462
 463                 if (qp->sq_max_wqes_per_wr <= 1)
 464                         return -EINVAL;
 465
 466                 ++qp->sq.wqe_shift;
 467         }
 468
 469         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 470                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 471                          send_wqe_overhead(type, qp->flags)) /
 472                 sizeof (struct mlx4_wqe_data_seg);
 473
 474         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 475                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 476         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 477                 qp->rq.offset = 0;
 478                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 479         } else {
 480                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 481                 qp->sq.offset = 0;
 482         }
 483
 484         cap->max_send_wr  = qp->sq.max_post =
 485                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 486         cap->max_send_sge = min(qp->sq.max_gs,
 487                                 min(dev->dev->caps.max_sq_sg,
 488                                     dev->dev->caps.max_rq_sg));
 489         /* We don't support inline sends for kernel QPs (yet) */
 490         cap->max_inline_data = 0;
 491
 492         return 0;
 493 }
 494
 495 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 496                             struct mlx4_ib_qp *qp,
 497                             struct mlx4_ib_create_qp *ucmd)
 498 {
 499         /* Sanity check SQ size before proceeding */
 500         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 501             ucmd->log_sq_stride >
 502                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 503             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 504                 return -EINVAL;
 505
 506         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 507         qp->sq.wqe_shift = ucmd->log_sq_stride;
 508
 509         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 510                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 511
 512         return 0;
 513 }
 514
 515 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 516 {
 517         int i;
 518
 519         qp->sqp_proxy_rcv =
 520                 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
 521                         GFP_KERNEL);
 522         if (!qp->sqp_proxy_rcv)
 523                 return -ENOMEM;
 524         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 525                 qp->sqp_proxy_rcv[i].addr =
 526                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 527                                 GFP_KERNEL);
 528                 if (!qp->sqp_proxy_rcv[i].addr)
 529                         goto err;
 530                 qp->sqp_proxy_rcv[i].map =
 531                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 532                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 533                                           DMA_FROM_DEVICE);
 534         }
 535         return 0;
 536
 537 err:
 538         while (i > 0) {
 539                 --i;
 540                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 541                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 542                                     DMA_FROM_DEVICE);
 543                 kfree(qp->sqp_proxy_rcv[i].addr);
 544         }
 545         kfree(qp->sqp_proxy_rcv);
 546         qp->sqp_proxy_rcv = NULL;
 547         return -ENOMEM;
 548 }
 549
 550 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 551 {
 552         int i;
 553
 554         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 555                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 556                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 557                                     DMA_FROM_DEVICE);
 558                 kfree(qp->sqp_proxy_rcv[i].addr);
 559         }
 560         kfree(qp->sqp_proxy_rcv);
 561 }
 562
 563 static int qp_has_rq(struct ib_qp_init_attr *attr)
 564 {
 565         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 566                 return 0;
 567
 568         return !attr->srq;
 569 }
 570
 571 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 572                             struct ib_qp_init_attr *init_attr,
 573                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp)
 574 {
 575         int qpn;
 576         int err;
 577         struct mlx4_ib_sqp *sqp;
 578         struct mlx4_ib_qp *qp;
 579         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 580
 581         /* When tunneling special qps, we use a plain UD qp */
 582         if (sqpn) {
 583                 if (mlx4_is_mfunc(dev->dev) &&
 584                     (!mlx4_is_master(dev->dev) ||
 585                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 586                         if (init_attr->qp_type == IB_QPT_GSI)
 587                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 588                         else if (mlx4_is_master(dev->dev))
 589                                 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 590                         else
 591                                 qp_type = MLX4_IB_QPT_PROXY_SMI;
 592                 }
 593                 qpn = sqpn;
 594                 /* add extra sg entry for tunneling */
 595                 init_attr->cap.max_recv_sge++;
 596         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
 597                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
 598                         container_of(init_attr,
 599                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
 600                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
 601                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
 602                     !mlx4_is_master(dev->dev))
 603                         return -EINVAL;
 604                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
 605                         qp_type = MLX4_IB_QPT_TUN_GSI;
 606                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev))
 607                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
 608                 else
 609                         qp_type = MLX4_IB_QPT_TUN_SMI;
 610                 qpn = dev->dev->caps.base_tunnel_sqpn + 8 * tnl_init->slave +
 611                       tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
 612                 sqpn = qpn;
 613         }
 614
 615         if (!*caller_qp) {
 616                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
 617                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
 618                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
 619                         sqp = kzalloc(sizeof (struct mlx4_ib_sqp), GFP_KERNEL);
 620                         if (!sqp)
 621                                 return -ENOMEM;
 622                         qp = &sqp->qp;
 623                 } else {
 624                         qp = kzalloc(sizeof (struct mlx4_ib_qp), GFP_KERNEL);
 625                         if (!qp)
 626                                 return -ENOMEM;
 627                 }
 628         } else
 629                 qp = *caller_qp;
 630
 631         qp->mlx4_ib_qp_type = qp_type;
 632
 633         if (mlx4_is_mfunc(dev->dev) &&
 634             (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI)) {
 635                 qpn -= 8;
 636                 sqpn -= 8;
 637         }
 638
 639         mutex_init(&qp->mutex);
 640         spin_lock_init(&qp->sq.lock);
 641         spin_lock_init(&qp->rq.lock);
 642         INIT_LIST_HEAD(&qp->gid_list);
 643         INIT_LIST_HEAD(&qp->steering_rules);
 644
 645         qp->state        = IB_QPS_RESET;
 646         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 647                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 648
 649         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
 650         if (err)
 651                 goto err;
 652
 653         if (pd->uobject) {
 654                 struct mlx4_ib_create_qp ucmd;
 655
 656                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 657                         err = -EFAULT;
 658                         goto err;
 659                 }
 660
 661                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 662
 663                 err = set_user_sq_size(dev, qp, &ucmd);
 664                 if (err)
 665                         goto err;
 666
 667                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 668                                        qp->buf_size, 0, 0);
 669                 if (IS_ERR(qp->umem)) {
 670                         err = PTR_ERR(qp->umem);
 671                         goto err;
 672                 }
 673
 674                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 675                                     ilog2(qp->umem->page_size), &qp->mtt);
 676                 if (err)
 677                         goto err_buf;
 678
 679                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 680                 if (err)
 681                         goto err_mtt;
 682
 683                 if (qp_has_rq(init_attr)) {
 684                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 685                                                   ucmd.db_addr, &qp->db);
 686                         if (err)
 687                                 goto err_mtt;
 688                 }
 689         } else {
 690                 qp->sq_no_prefetch = 0;
 691
 692                 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 693                         qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 694
 695                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 696                         qp->flags |= MLX4_IB_QP_LSO;
 697
 698                 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
 699                 if (err)
 700                         goto err;
 701
 702                 if (qp_has_rq(init_attr)) {
 703                         err = mlx4_db_alloc(dev->dev, &qp->db, 0);
 704                         if (err)
 705                                 goto err;
 706
 707                         *qp->db.db = 0;
 708                 }
 709
 710                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 711                         err = -ENOMEM;
 712                         goto err_db;
 713                 }
 714
 715                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 716                                     &qp->mtt);
 717                 if (err)
 718                         goto err_buf;
 719
 720                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 721                 if (err)
 722                         goto err_mtt;
 723
 724                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 725                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 726
 727                 if (!qp->sq.wrid || !qp->rq.wrid) {
 728                         err = -ENOMEM;
 729                         goto err_wrid;
 730                 }
 731         }
 732
 733         if (sqpn) {
 734                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
 735                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
 736                         if (alloc_proxy_bufs(pd->device, qp)) {
 737                                 err = -ENOMEM;
 738                                 goto err_wrid;
 739                         }
 740                 }
 741         } else {
 742                 /* Raw packet QPNs must be aligned to 8 bits. If not, the WQE
 743                  * BlueFlame setup flow wrongly causes VLAN insertion. */
 744                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
 745                         err = mlx4_qp_reserve_range(dev->dev, 1, 1 << 8, &qpn);
 746                 else
 747                         err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn);
 748                 if (err)
 749                         goto err_proxy;
 750         }
 751
 752         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
 753         if (err)
 754                 goto err_qpn;
 755
 756         if (init_attr->qp_type == IB_QPT_XRC_TGT)
 757                 qp->mqp.qpn |= (1 << 23);
 758
 759         /*
 760          * Hardware wants QPN written in big-endian order (after
 761          * shifting) for send doorbell.  Precompute this value to save
 762          * a little bit when posting sends.
 763          */
 764         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 765
 766         qp->mqp.event = mlx4_ib_qp_event;
 767         if (!*caller_qp)
 768                 *caller_qp = qp;
 769         return 0;
 770
 771 err_qpn:
 772         if (!sqpn)
 773                 mlx4_qp_release_range(dev->dev, qpn, 1);
 774 err_proxy:
 775         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
 776                 free_proxy_bufs(pd->device, qp);
 777 err_wrid:
 778         if (pd->uobject) {
 779                 if (qp_has_rq(init_attr))
 780                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 781         } else {
 782                 kfree(qp->sq.wrid);
 783                 kfree(qp->rq.wrid);
 784         }
 785
 786 err_mtt:
 787         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 788
 789 err_buf:
 790         if (pd->uobject)
 791                 ib_umem_release(qp->umem);
 792         else
 793                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 794
 795 err_db:
 796         if (!pd->uobject && qp_has_rq(init_attr))
 797                 mlx4_db_free(dev->dev, &qp->db);
 798
 799 err:
 800         if (!*caller_qp)
 801                 kfree(qp);
 802         return err;
 803 }
 804
 805 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 806 {
 807         switch (state) {
 808         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 809         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 810         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 811         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 812         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 813         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 814         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 815         default:                return -1;
 816         }
 817 }
 818
 819 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 820         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 821 {
 822         if (send_cq == recv_cq) {
 823                 spin_lock_irq(&send_cq->lock);
 824                 __acquire(&recv_cq->lock);
 825         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 826                 spin_lock_irq(&send_cq->lock);
 827                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 828         } else {
 829                 spin_lock_irq(&recv_cq->lock);
 830                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 831         }
 832 }
 833
 834 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 835         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 836 {
 837         if (send_cq == recv_cq) {
 838                 __release(&recv_cq->lock);
 839                 spin_unlock_irq(&send_cq->lock);
 840         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 841                 spin_unlock(&recv_cq->lock);
 842                 spin_unlock_irq(&send_cq->lock);
 843         } else {
 844                 spin_unlock(&send_cq->lock);
 845                 spin_unlock_irq(&recv_cq->lock);
 846         }
 847 }
 848
 849 static void del_gid_entries(struct mlx4_ib_qp *qp)
 850 {
 851         struct mlx4_ib_gid_entry *ge, *tmp;
 852
 853         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 854                 list_del(&ge->list);
 855                 kfree(ge);
 856         }
 857 }
 858
 859 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
 860 {
 861         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
 862                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
 863         else
 864                 return to_mpd(qp->ibqp.pd);
 865 }
 866
 867 static void get_cqs(struct mlx4_ib_qp *qp,
 868                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
 869 {
 870         switch (qp->ibqp.qp_type) {
 871         case IB_QPT_XRC_TGT:
 872                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
 873                 *recv_cq = *send_cq;
 874                 break;
 875         case IB_QPT_XRC_INI:
 876                 *send_cq = to_mcq(qp->ibqp.send_cq);
 877                 *recv_cq = *send_cq;
 878                 break;
 879         default:
 880                 *send_cq = to_mcq(qp->ibqp.send_cq);
 881                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
 882                 break;
 883         }
 884 }
 885
 886 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 887                               int is_user)
 888 {
 889         struct mlx4_ib_cq *send_cq, *recv_cq;
 890
 891         if (qp->state != IB_QPS_RESET)
 892                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 893                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 894                         pr_warn("modify QP %06x to RESET failed.\n",
 895                                qp->mqp.qpn);
 896
 897         get_cqs(qp, &send_cq, &recv_cq);
 898
 899         mlx4_ib_lock_cqs(send_cq, recv_cq);
 900
 901         if (!is_user) {
 902                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 903                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 904                 if (send_cq != recv_cq)
 905                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 906         }
 907
 908         mlx4_qp_remove(dev->dev, &qp->mqp);
 909
 910         mlx4_ib_unlock_cqs(send_cq, recv_cq);
 911
 912         mlx4_qp_free(dev->dev, &qp->mqp);
 913
 914         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp))
 915                 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
 916
 917         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 918
 919         if (is_user) {
 920                 if (qp->rq.wqe_cnt)
 921                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
 922                                               &qp->db);
 923                 ib_umem_release(qp->umem);
 924         } else {
 925                 kfree(qp->sq.wrid);
 926                 kfree(qp->rq.wrid);
 927                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
 928                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
 929                         free_proxy_bufs(&dev->ib_dev, qp);
 930                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 931                 if (qp->rq.wqe_cnt)
 932                         mlx4_db_free(dev->dev, &qp->db);
 933         }
 934
 935         del_gid_entries(qp);
 936 }
 937
 938 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
 939                                 struct ib_qp_init_attr *init_attr,
 940                                 struct ib_udata *udata)
 941 {
 942         struct mlx4_ib_qp *qp = NULL;
 943         int err;
 944         u16 xrcdn = 0;
 945
 946         /*
 947          * We only support LSO, vendor flag1, and multicast loopback blocking,
 948          * and only for kernel UD QPs.
 949          */
 950         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
 951                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
 952                                         MLX4_IB_SRIOV_TUNNEL_QP | MLX4_IB_SRIOV_SQP))
 953                 return ERR_PTR(-EINVAL);
 954
 955         if (init_attr->create_flags &&
 956             (udata ||
 957              ((init_attr->create_flags & ~MLX4_IB_SRIOV_SQP) &&
 958               init_attr->qp_type != IB_QPT_UD) ||
 959              ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
 960               init_attr->qp_type > IB_QPT_GSI)))
 961                 return ERR_PTR(-EINVAL);
 962
 963         switch (init_attr->qp_type) {
 964         case IB_QPT_XRC_TGT:
 965                 pd = to_mxrcd(init_attr->xrcd)->pd;
 966                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
 967                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
 968                 /* fall through */
 969         case IB_QPT_XRC_INI:
 970                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
 971                         return ERR_PTR(-ENOSYS);
 972                 init_attr->recv_cq = init_attr->send_cq;
 973                 /* fall through */
 974         case IB_QPT_RC:
 975         case IB_QPT_UC:
 976         case IB_QPT_RAW_PACKET:
 977                 qp = kzalloc(sizeof *qp, GFP_KERNEL);
 978                 if (!qp)
 979                         return ERR_PTR(-ENOMEM);
 980                 /* fall through */
 981         case IB_QPT_UD:
 982         {
 983                 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
 984                                        udata, 0, &qp);
 985                 if (err)
 986                         return ERR_PTR(err);
 987
 988                 qp->ibqp.qp_num = qp->mqp.qpn;
 989                 qp->xrcdn = xrcdn;
 990
 991                 break;
 992         }
 993         case IB_QPT_SMI:
 994         case IB_QPT_GSI:
 995         {
 996                 /* Userspace is not allowed to create special QPs: */
 997                 if (udata)
 998                         return ERR_PTR(-EINVAL);
 999
1000                 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1001                                        to_mdev(pd->device)->dev->caps.sqp_start +
1002                                        (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1003                                        init_attr->port_num - 1,
1004                                        &qp);
1005                 if (err)
1006                         return ERR_PTR(err);
1007
1008                 qp->port        = init_attr->port_num;
1009                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1010
1011                 break;
1012         }
1013         default:
1014                 /* Don't support raw QPs */
1015                 return ERR_PTR(-EINVAL);
1016         }
1017
1018         return &qp->ibqp;
1019 }
1020
1021 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1022 {
1023         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1024         struct mlx4_ib_qp *mqp = to_mqp(qp);
1025         struct mlx4_ib_pd *pd;
1026
1027         if (is_qp0(dev, mqp))
1028                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1029
1030         pd = get_pd(mqp);
1031         destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1032
1033         if (is_sqp(dev, mqp))
1034                 kfree(to_msqp(mqp));
1035         else
1036                 kfree(mqp);
1037
1038         return 0;
1039 }
1040
1041 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1042 {
1043         switch (type) {
1044         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1045         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1046         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1047         case MLX4_IB_QPT_XRC_INI:
1048         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1049         case MLX4_IB_QPT_SMI:
1050         case MLX4_IB_QPT_GSI:
1051         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1052
1053         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1054         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1055                                                 MLX4_QP_ST_MLX : -1);
1056         case MLX4_IB_QPT_PROXY_SMI:
1057         case MLX4_IB_QPT_TUN_SMI:
1058         case MLX4_IB_QPT_PROXY_GSI:
1059         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1060                                                 MLX4_QP_ST_UD : -1);
1061         default:                        return -1;
1062         }
1063 }
1064
1065 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1066                                    int attr_mask)
1067 {
1068         u8 dest_rd_atomic;
1069         u32 access_flags;
1070         u32 hw_access_flags = 0;
1071
1072         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1073                 dest_rd_atomic = attr->max_dest_rd_atomic;
1074         else
1075                 dest_rd_atomic = qp->resp_depth;
1076
1077         if (attr_mask & IB_QP_ACCESS_FLAGS)
1078                 access_flags = attr->qp_access_flags;
1079         else
1080                 access_flags = qp->atomic_rd_en;
1081
1082         if (!dest_rd_atomic)
1083                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1084
1085         if (access_flags & IB_ACCESS_REMOTE_READ)
1086                 hw_access_flags |= MLX4_QP_BIT_RRE;
1087         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1088                 hw_access_flags |= MLX4_QP_BIT_RAE;
1089         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1090                 hw_access_flags |= MLX4_QP_BIT_RWE;
1091
1092         return cpu_to_be32(hw_access_flags);
1093 }
1094
1095 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1096                             int attr_mask)
1097 {
1098         if (attr_mask & IB_QP_PKEY_INDEX)
1099                 sqp->pkey_index = attr->pkey_index;
1100         if (attr_mask & IB_QP_QKEY)
1101                 sqp->qkey = attr->qkey;
1102         if (attr_mask & IB_QP_SQ_PSN)
1103                 sqp->send_psn = attr->sq_psn;
1104 }
1105
1106 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1107 {
1108         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1109 }
1110
1111 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1112                          struct mlx4_qp_path *path, u8 port)
1113 {
1114         int err;
1115         int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1116                 IB_LINK_LAYER_ETHERNET;
1117         u8 mac[6];
1118         int is_mcast;
1119         u16 vlan_tag;
1120         int vidx;
1121
1122         path->grh_mylmc     = ah->src_path_bits & 0x7f;
1123         path->rlid          = cpu_to_be16(ah->dlid);
1124         if (ah->static_rate) {
1125                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1126                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1127                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1128                         --path->static_rate;
1129         } else
1130                 path->static_rate = 0;
1131
1132         if (ah->ah_flags & IB_AH_GRH) {
1133                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
1134                         pr_err("sgid_index (%u) too large. max is %d\n",
1135                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1136                         return -1;
1137                 }
1138
1139                 path->grh_mylmc |= 1 << 7;
1140                 path->mgid_index = ah->grh.sgid_index;
1141                 path->hop_limit  = ah->grh.hop_limit;
1142                 path->tclass_flowlabel =
1143                         cpu_to_be32((ah->grh.traffic_class << 20) |
1144                                     (ah->grh.flow_label));
1145                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1146         }
1147
1148         if (is_eth) {
1149                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1150                         ((port - 1) << 6) | ((ah->sl & 7) << 3);
1151
1152                 if (!(ah->ah_flags & IB_AH_GRH))
1153                         return -1;
1154
1155                 err = mlx4_ib_resolve_grh(dev, ah, mac, &is_mcast, port);
1156                 if (err)
1157                         return err;
1158
1159                 memcpy(path->dmac, mac, 6);
1160                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1161                 /* use index 0 into MAC table for IBoE */
1162                 path->grh_mylmc &= 0x80;
1163
1164                 vlan_tag = rdma_get_vlan_id(&dev->iboe.gid_table[port - 1][ah->grh.sgid_index]);
1165                 if (vlan_tag < 0x1000) {
1166                         if (mlx4_find_cached_vlan(dev->dev, port, vlan_tag, &vidx))
1167                                 return -ENOENT;
1168
1169                         path->vlan_index = vidx;
1170                         path->fl = 1 << 6;
1171                 }
1172         } else
1173                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1174                         ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1175
1176         return 0;
1177 }
1178
1179 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1180 {
1181         struct mlx4_ib_gid_entry *ge, *tmp;
1182
1183         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1184                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1185                         ge->added = 1;
1186                         ge->port = qp->port;
1187                 }
1188         }
1189 }
1190
1191 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1192                                const struct ib_qp_attr *attr, int attr_mask,
1193                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1194 {
1195         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1196         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1197         struct mlx4_ib_pd *pd;
1198         struct mlx4_ib_cq *send_cq, *recv_cq;
1199         struct mlx4_qp_context *context;
1200         enum mlx4_qp_optpar optpar = 0;
1201         int sqd_event;
1202         int err = -EINVAL;
1203
1204         context = kzalloc(sizeof *context, GFP_KERNEL);
1205         if (!context)
1206                 return -ENOMEM;
1207
1208         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1209                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1210
1211         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1212                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1213         else {
1214                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1215                 switch (attr->path_mig_state) {
1216                 case IB_MIG_MIGRATED:
1217                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1218                         break;
1219                 case IB_MIG_REARM:
1220                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1221                         break;
1222                 case IB_MIG_ARMED:
1223                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1224                         break;
1225                 }
1226         }
1227
1228         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1229                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1230         else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1231                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1232         else if (ibqp->qp_type == IB_QPT_UD) {
1233                 if (qp->flags & MLX4_IB_QP_LSO)
1234                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
1235                                               ilog2(dev->dev->caps.max_gso_sz);
1236                 else
1237                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1238         } else if (attr_mask & IB_QP_PATH_MTU) {
1239                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1240                         pr_err("path MTU (%u) is invalid\n",
1241                                attr->path_mtu);
1242                         goto out;
1243                 }
1244                 context->mtu_msgmax = (attr->path_mtu << 5) |
1245                         ilog2(dev->dev->caps.max_msg_sz);
1246         }
1247
1248         if (qp->rq.wqe_cnt)
1249                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1250         context->rq_size_stride |= qp->rq.wqe_shift - 4;
1251
1252         if (qp->sq.wqe_cnt)
1253                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1254         context->sq_size_stride |= qp->sq.wqe_shift - 4;
1255
1256         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1257                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1258                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1259         }
1260
1261         if (qp->ibqp.uobject)
1262                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1263         else
1264                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1265
1266         if (attr_mask & IB_QP_DEST_QPN)
1267                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1268
1269         if (attr_mask & IB_QP_PORT) {
1270                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1271                     !(attr_mask & IB_QP_AV)) {
1272                         mlx4_set_sched(&context->pri_path, attr->port_num);
1273                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1274                 }
1275         }
1276
1277         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1278                 if (dev->counters[qp->port - 1] != -1) {
1279                         context->pri_path.counter_index =
1280                                                 dev->counters[qp->port - 1];
1281                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1282                 } else
1283                         context->pri_path.counter_index = 0xff;
1284         }
1285
1286         if (attr_mask & IB_QP_PKEY_INDEX) {
1287                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1288                         context->pri_path.disable_pkey_check = 0x40;
1289                 context->pri_path.pkey_index = attr->pkey_index;
1290                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1291         }
1292
1293         if (attr_mask & IB_QP_AV) {
1294                 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
1295                                   attr_mask & IB_QP_PORT ?
1296                                   attr->port_num : qp->port))
1297                         goto out;
1298
1299                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1300                            MLX4_QP_OPTPAR_SCHED_QUEUE);
1301         }
1302
1303         if (attr_mask & IB_QP_TIMEOUT) {
1304                 context->pri_path.ackto |= attr->timeout << 3;
1305                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1306         }
1307
1308         if (attr_mask & IB_QP_ALT_PATH) {
1309                 if (attr->alt_port_num == 0 ||
1310                     attr->alt_port_num > dev->dev->caps.num_ports)
1311                         goto out;
1312
1313                 if (attr->alt_pkey_index >=
1314                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
1315                         goto out;
1316
1317                 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1318                                   attr->alt_port_num))
1319                         goto out;
1320
1321                 context->alt_path.pkey_index = attr->alt_pkey_index;
1322                 context->alt_path.ackto = attr->alt_timeout << 3;
1323                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1324         }
1325
1326         pd = get_pd(qp);
1327         get_cqs(qp, &send_cq, &recv_cq);
1328         context->pd       = cpu_to_be32(pd->pdn);
1329         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1330         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1331         context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1332
1333         /* Set "fast registration enabled" for all kernel QPs */
1334         if (!qp->ibqp.uobject)
1335                 context->params1 |= cpu_to_be32(1 << 11);
1336
1337         if (attr_mask & IB_QP_RNR_RETRY) {
1338                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1339                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1340         }
1341
1342         if (attr_mask & IB_QP_RETRY_CNT) {
1343                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1344                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1345         }
1346
1347         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1348                 if (attr->max_rd_atomic)
1349                         context->params1 |=
1350                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1351                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1352         }
1353
1354         if (attr_mask & IB_QP_SQ_PSN)
1355                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1356
1357         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1358                 if (attr->max_dest_rd_atomic)
1359                         context->params2 |=
1360                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1361                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1362         }
1363
1364         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1365                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1366                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1367         }
1368
1369         if (ibqp->srq)
1370                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1371
1372         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1373                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1374                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1375         }
1376         if (attr_mask & IB_QP_RQ_PSN)
1377                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1378
1379         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1380         if (attr_mask & IB_QP_QKEY) {
1381                 if (qp->mlx4_ib_qp_type &
1382                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1383                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1384                 else {
1385                         if (mlx4_is_mfunc(dev->dev) &&
1386                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1387                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1388                             MLX4_RESERVED_QKEY_BASE) {
1389                                 pr_err("Cannot use reserved QKEY"
1390                                        " 0x%x (range 0xffff0000..0xffffffff"
1391                                        " is reserved)\n", attr->qkey);
1392                                 err = -EINVAL;
1393                                 goto out;
1394                         }
1395                         context->qkey = cpu_to_be32(attr->qkey);
1396                 }
1397                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1398         }
1399
1400         if (ibqp->srq)
1401                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1402
1403         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1404                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1405
1406         if (cur_state == IB_QPS_INIT &&
1407             new_state == IB_QPS_RTR  &&
1408             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1409              ibqp->qp_type == IB_QPT_UD ||
1410              ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1411                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1412                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1413                     qp->mlx4_ib_qp_type &
1414                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1415                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1416                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1417                                 context->pri_path.fl = 0x80;
1418                 } else {
1419                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1420                                 context->pri_path.fl = 0x80;
1421                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1422                 }
1423         }
1424
1425         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1426             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1427                 sqd_event = 1;
1428         else
1429                 sqd_event = 0;
1430
1431         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1432                 context->rlkey |= (1 << 4);
1433
1434         /*
1435          * Before passing a kernel QP to the HW, make sure that the
1436          * ownership bits of the send queue are set and the SQ
1437          * headroom is stamped so that the hardware doesn't start
1438          * processing stale work requests.
1439          */
1440         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1441                 struct mlx4_wqe_ctrl_seg *ctrl;
1442                 int i;
1443
1444                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1445                         ctrl = get_send_wqe(qp, i);
1446                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1447                         if (qp->sq_max_wqes_per_wr == 1)
1448                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1449
1450                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1451                 }
1452         }
1453
1454         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1455                              to_mlx4_state(new_state), context, optpar,
1456                              sqd_event, &qp->mqp);
1457         if (err)
1458                 goto out;
1459
1460         qp->state = new_state;
1461
1462         if (attr_mask & IB_QP_ACCESS_FLAGS)
1463                 qp->atomic_rd_en = attr->qp_access_flags;
1464         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1465                 qp->resp_depth = attr->max_dest_rd_atomic;
1466         if (attr_mask & IB_QP_PORT) {
1467                 qp->port = attr->port_num;
1468                 update_mcg_macs(dev, qp);
1469         }
1470         if (attr_mask & IB_QP_ALT_PATH)
1471                 qp->alt_port = attr->alt_port_num;
1472
1473         if (is_sqp(dev, qp))
1474                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1475
1476         /*
1477          * If we moved QP0 to RTR, bring the IB link up; if we moved
1478          * QP0 to RESET or ERROR, bring the link back down.
1479          */
1480         if (is_qp0(dev, qp)) {
1481                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1482                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1483                                 pr_warn("INIT_PORT failed for port %d\n",
1484                                        qp->port);
1485
1486                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1487                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1488                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1489         }
1490
1491         /*
1492          * If we moved a kernel QP to RESET, clean up all old CQ
1493          * entries and reinitialize the QP.
1494          */
1495         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1496                 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1497                                  ibqp->srq ? to_msrq(ibqp->srq): NULL);
1498                 if (send_cq != recv_cq)
1499                         mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1500
1501                 qp->rq.head = 0;
1502                 qp->rq.tail = 0;
1503                 qp->sq.head = 0;
1504                 qp->sq.tail = 0;
1505                 qp->sq_next_wqe = 0;
1506                 if (qp->rq.wqe_cnt)
1507                         *qp->db.db  = 0;
1508         }
1509
1510 out:
1511         kfree(context);
1512         return err;
1513 }
1514
1515 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1516                       int attr_mask, struct ib_udata *udata)
1517 {
1518         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1519         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1520         enum ib_qp_state cur_state, new_state;
1521         int err = -EINVAL;
1522
1523         mutex_lock(&qp->mutex);
1524
1525         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1526         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1527
1528         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask)) {
1529                 pr_debug("qpn 0x%x: invalid attribute mask specified "
1530                          "for transition %d to %d. qp_type %d,"
1531                          " attr_mask 0x%x\n",
1532                          ibqp->qp_num, cur_state, new_state,
1533                          ibqp->qp_type, attr_mask);
1534                 goto out;
1535         }
1536
1537         if ((attr_mask & IB_QP_PORT) &&
1538             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
1539                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
1540                          "for transition %d to %d. qp_type %d\n",
1541                          ibqp->qp_num, attr->port_num, cur_state,
1542                          new_state, ibqp->qp_type);
1543                 goto out;
1544         }
1545
1546         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
1547             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
1548              IB_LINK_LAYER_ETHERNET))
1549                 goto out;
1550
1551         if (attr_mask & IB_QP_PKEY_INDEX) {
1552                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1553                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
1554                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
1555                                  "for transition %d to %d. qp_type %d\n",
1556                                  ibqp->qp_num, attr->pkey_index, cur_state,
1557                                  new_state, ibqp->qp_type);
1558                         goto out;
1559                 }
1560         }
1561
1562         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1563             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1564                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
1565                          "Transition %d to %d. qp_type %d\n",
1566                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
1567                          new_state, ibqp->qp_type);
1568                 goto out;
1569         }
1570
1571         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1572             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1573                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
1574                          "Transition %d to %d. qp_type %d\n",
1575                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
1576                          new_state, ibqp->qp_type);
1577                 goto out;
1578         }
1579
1580         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1581                 err = 0;
1582                 goto out;
1583         }
1584
1585         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1586
1587 out:
1588         mutex_unlock(&qp->mutex);
1589         return err;
1590 }
1591
1592 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
1593                                   struct ib_send_wr *wr,
1594                                   void *wqe, unsigned *mlx_seg_len)
1595 {
1596         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
1597         struct ib_device *ib_dev = &mdev->ib_dev;
1598         struct mlx4_wqe_mlx_seg *mlx = wqe;
1599         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1600         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1601         u16 pkey;
1602         u32 qkey;
1603         int send_size;
1604         int header_size;
1605         int spc;
1606         int i;
1607
1608         if (wr->opcode != IB_WR_SEND)
1609                 return -EINVAL;
1610
1611         send_size = 0;
1612
1613         for (i = 0; i < wr->num_sge; ++i)
1614                 send_size += wr->sg_list[i].length;
1615
1616         /* for proxy-qp0 sends, need to add in size of tunnel header */
1617         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
1618         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
1619                 send_size += sizeof (struct mlx4_ib_tunnel_header);
1620
1621         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
1622
1623         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
1624                 sqp->ud_header.lrh.service_level =
1625                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
1626                 sqp->ud_header.lrh.destination_lid =
1627                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1628                 sqp->ud_header.lrh.source_lid =
1629                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1630         }
1631
1632         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1633
1634         /* force loopback */
1635         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
1636         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1637
1638         sqp->ud_header.lrh.virtual_lane    = 0;
1639         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1640         ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
1641         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1642         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
1643                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1644         else
1645                 sqp->ud_header.bth.destination_qpn =
1646                         cpu_to_be32(mdev->dev->caps.base_tunnel_sqpn +
1647                                     sqp->qp.port - 1);
1648
1649         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1650         if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
1651                 return -EINVAL;
1652         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
1653         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
1654
1655         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1656         sqp->ud_header.immediate_present = 0;
1657
1658         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1659
1660         /*
1661          * Inline data segments may not cross a 64 byte boundary.  If
1662          * our UD header is bigger than the space available up to the
1663          * next 64 byte boundary in the WQE, use two inline data
1664          * segments to hold the UD header.
1665          */
1666         spc = MLX4_INLINE_ALIGN -
1667               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1668         if (header_size <= spc) {
1669                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1670                 memcpy(inl + 1, sqp->header_buf, header_size);
1671                 i = 1;
1672         } else {
1673                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1674                 memcpy(inl + 1, sqp->header_buf, spc);
1675
1676                 inl = (void *) (inl + 1) + spc;
1677                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1678                 /*
1679                  * Need a barrier here to make sure all the data is
1680                  * visible before the byte_count field is set.
1681                  * Otherwise the HCA prefetcher could grab the 64-byte
1682                  * chunk with this inline segment and get a valid (!=
1683                  * 0xffffffff) byte count but stale data, and end up
1684                  * generating a packet with bad headers.
1685                  *
1686                  * The first inline segment's byte_count field doesn't
1687                  * need a barrier, because it comes after a
1688                  * control/MLX segment and therefore is at an offset
1689                  * of 16 mod 64.
1690                  */
1691                 wmb();
1692                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1693                 i = 2;
1694         }
1695
1696         *mlx_seg_len =
1697         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1698         return 0;
1699 }
1700
1701 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1702                             void *wqe, unsigned *mlx_seg_len)
1703 {
1704         struct ib_device *ib_dev = sqp->qp.ibqp.device;
1705         struct mlx4_wqe_mlx_seg *mlx = wqe;
1706         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1707         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1708         struct net_device *ndev;
1709         union ib_gid sgid;
1710         u16 pkey;
1711         int send_size;
1712         int header_size;
1713         int spc;
1714         int i;
1715         int is_eth;
1716         int is_vlan = 0;
1717         int is_grh;
1718         u16 vlan;
1719         int err = 0;
1720
1721         send_size = 0;
1722         for (i = 0; i < wr->num_sge; ++i)
1723                 send_size += wr->sg_list[i].length;
1724
1725         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
1726         is_grh = mlx4_ib_ah_grh_present(ah);
1727         if (is_eth) {
1728                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
1729                         /* When multi-function is enabled, the ib_core gid
1730                          * indexes don't necessarily match the hw ones, so
1731                          * we must use our own cache */
1732                         sgid.global.subnet_prefix =
1733                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
1734                                 subnet_prefix;
1735                         sgid.global.interface_id =
1736                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
1737                                 guid_cache[ah->av.ib.gid_index];
1738                 } else  {
1739                         err = ib_get_cached_gid(ib_dev,
1740                                                 be32_to_cpu(ah->av.ib.port_pd) >> 24,
1741                                                 ah->av.ib.gid_index, &sgid);
1742                         if (err)
1743                                 return err;
1744                 }
1745
1746                 vlan = rdma_get_vlan_id(&sgid);
1747                 is_vlan = vlan < 0x1000;
1748         }
1749         ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
1750
1751         if (!is_eth) {
1752                 sqp->ud_header.lrh.service_level =
1753                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
1754                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
1755                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1756         }
1757
1758         if (is_grh) {
1759                 sqp->ud_header.grh.traffic_class =
1760                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
1761                 sqp->ud_header.grh.flow_label    =
1762                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1763                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
1764                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
1765                         /* When multi-function is enabled, the ib_core gid
1766                          * indexes don't necessarily match the hw ones, so
1767                          * we must use our own cache */
1768                         sqp->ud_header.grh.source_gid.global.subnet_prefix =
1769                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
1770                                                        subnet_prefix;
1771                         sqp->ud_header.grh.source_gid.global.interface_id =
1772                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
1773                                                guid_cache[ah->av.ib.gid_index];
1774                 } else
1775                         ib_get_cached_gid(ib_dev,
1776                                           be32_to_cpu(ah->av.ib.port_pd) >> 24,
1777                                           ah->av.ib.gid_index,
1778                                           &sqp->ud_header.grh.source_gid);
1779                 memcpy(sqp->ud_header.grh.destination_gid.raw,
1780                        ah->av.ib.dgid, 16);
1781         }
1782
1783         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1784
1785         if (!is_eth) {
1786                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1787                                           (sqp->ud_header.lrh.destination_lid ==
1788                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1789                                           (sqp->ud_header.lrh.service_level << 8));
1790                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
1791                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
1792                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1793         }
1794
1795         switch (wr->opcode) {
1796         case IB_WR_SEND:
1797                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
1798                 sqp->ud_header.immediate_present = 0;
1799                 break;
1800         case IB_WR_SEND_WITH_IMM:
1801                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1802                 sqp->ud_header.immediate_present = 1;
1803                 sqp->ud_header.immediate_data    = wr->ex.imm_data;
1804                 break;
1805         default:
1806                 return -EINVAL;
1807         }
1808
1809         if (is_eth) {
1810                 u8 *smac;
1811                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
1812
1813                 mlx->sched_prio = cpu_to_be16(pcp);
1814
1815                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
1816                 /* FIXME: cache smac value? */
1817                 ndev = to_mdev(sqp->qp.ibqp.device)->iboe.netdevs[sqp->qp.port - 1];
1818                 if (!ndev)
1819                         return -ENODEV;
1820                 smac = ndev->dev_addr;
1821                 memcpy(sqp->ud_header.eth.smac_h, smac, 6);
1822                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
1823                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
1824                 if (!is_vlan) {
1825                         sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
1826                 } else {
1827                         sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
1828                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
1829                 }
1830         } else {
1831                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1832                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1833                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1834         }
1835         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1836         if (!sqp->qp.ibqp.qp_num)
1837                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1838         else
1839                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1840         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1841         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1842         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1843         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1844                                                sqp->qkey : wr->wr.ud.remote_qkey);
1845         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1846
1847         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1848
1849         if (0) {
1850                 pr_err("built UD header of size %d:\n", header_size);
1851                 for (i = 0; i < header_size / 4; ++i) {
1852                         if (i % 8 == 0)
1853                                 pr_err("  [%02x] ", i * 4);
1854                         pr_cont(" %08x",
1855                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1856                         if ((i + 1) % 8 == 0)
1857                                 pr_cont("\n");
1858                 }
1859                 pr_err("\n");
1860         }
1861
1862         /*
1863          * Inline data segments may not cross a 64 byte boundary.  If
1864          * our UD header is bigger than the space available up to the
1865          * next 64 byte boundary in the WQE, use two inline data
1866          * segments to hold the UD header.
1867          */
1868         spc = MLX4_INLINE_ALIGN -
1869                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1870         if (header_size <= spc) {
1871                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1872                 memcpy(inl + 1, sqp->header_buf, header_size);
1873                 i = 1;
1874         } else {
1875                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1876                 memcpy(inl + 1, sqp->header_buf, spc);
1877
1878                 inl = (void *) (inl + 1) + spc;
1879                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1880                 /*
1881                  * Need a barrier here to make sure all the data is
1882                  * visible before the byte_count field is set.
1883                  * Otherwise the HCA prefetcher could grab the 64-byte
1884                  * chunk with this inline segment and get a valid (!=
1885                  * 0xffffffff) byte count but stale data, and end up
1886                  * generating a packet with bad headers.
1887                  *
1888                  * The first inline segment's byte_count field doesn't
1889                  * need a barrier, because it comes after a
1890                  * control/MLX segment and therefore is at an offset
1891                  * of 16 mod 64.
1892                  */
1893                 wmb();
1894                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1895                 i = 2;
1896         }
1897
1898         *mlx_seg_len =
1899                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1900         return 0;
1901 }
1902
1903 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1904 {
1905         unsigned cur;
1906         struct mlx4_ib_cq *cq;
1907
1908         cur = wq->head - wq->tail;
1909         if (likely(cur + nreq < wq->max_post))
1910                 return 0;
1911
1912         cq = to_mcq(ib_cq);
1913         spin_lock(&cq->lock);
1914         cur = wq->head - wq->tail;
1915         spin_unlock(&cq->lock);
1916
1917         return cur + nreq >= wq->max_post;
1918 }
1919
1920 static __be32 convert_access(int acc)
1921 {
1922         return (acc & IB_ACCESS_REMOTE_ATOMIC ? cpu_to_be32(MLX4_WQE_FMR_PERM_ATOMIC)       : 0) |
1923                (acc & IB_ACCESS_REMOTE_WRITE  ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_WRITE) : 0) |
1924                (acc & IB_ACCESS_REMOTE_READ   ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_READ)  : 0) |
1925                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
1926                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
1927 }
1928
1929 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
1930 {
1931         struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
1932         int i;
1933
1934         for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
1935                 mfrpl->mapped_page_list[i] =
1936                         cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
1937                                     MLX4_MTT_FLAG_PRESENT);
1938
1939         fseg->flags             = convert_access(wr->wr.fast_reg.access_flags);
1940         fseg->mem_key           = cpu_to_be32(wr->wr.fast_reg.rkey);
1941         fseg->buf_list          = cpu_to_be64(mfrpl->map);
1942         fseg->start_addr        = cpu_to_be64(wr->wr.fast_reg.iova_start);
1943         fseg->reg_len           = cpu_to_be64(wr->wr.fast_reg.length);
1944         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
1945         fseg->page_size         = cpu_to_be32(wr->wr.fast_reg.page_shift);
1946         fseg->reserved[0]       = 0;
1947         fseg->reserved[1]       = 0;
1948 }
1949
1950 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
1951 {
1952         iseg->flags     = 0;
1953         iseg->mem_key   = cpu_to_be32(rkey);
1954         iseg->guest_id  = 0;
1955         iseg->pa        = 0;
1956 }
1957
1958 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1959                                           u64 remote_addr, u32 rkey)
1960 {
1961         rseg->raddr    = cpu_to_be64(remote_addr);
1962         rseg->rkey     = cpu_to_be32(rkey);
1963         rseg->reserved = 0;
1964 }
1965
1966 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1967 {
1968         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1969                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1970                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
1971         } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
1972                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1973                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add_mask);
1974         } else {
1975                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1976                 aseg->compare  = 0;
1977         }
1978
1979 }
1980
1981 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
1982                                   struct ib_send_wr *wr)
1983 {
1984         aseg->swap_add          = cpu_to_be64(wr->wr.atomic.swap);
1985         aseg->swap_add_mask     = cpu_to_be64(wr->wr.atomic.swap_mask);
1986         aseg->compare           = cpu_to_be64(wr->wr.atomic.compare_add);
1987         aseg->compare_mask      = cpu_to_be64(wr->wr.atomic.compare_add_mask);
1988 }
1989
1990 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1991                              struct ib_send_wr *wr)
1992 {
1993         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1994         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1995         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1996         dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
1997         memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
1998 }
1999
2000 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2001                                     struct mlx4_wqe_datagram_seg *dseg,
2002                                     struct ib_send_wr *wr, enum ib_qp_type qpt)
2003 {
2004         union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2005         struct mlx4_av sqp_av = {0};
2006         int port = *((u8 *) &av->ib.port_pd) & 0x3;
2007
2008         /* force loopback */
2009         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2010         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2011         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2012                         cpu_to_be32(0xf0000000);
2013
2014         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2015         dseg->dqpn = cpu_to_be32(dev->dev->caps.base_tunnel_sqpn +
2016                                  qpt * 2 + port - 1);
2017         /* use well-known qkey from the QPC */
2018         dseg->qkey = cpu_to_be32(0x80000000);
2019 }
2020
2021 static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2022 {
2023         struct mlx4_wqe_inline_seg *inl = wqe;
2024         struct mlx4_ib_tunnel_header hdr;
2025         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2026         int spc;
2027         int i;
2028
2029         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2030         hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2031         hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2032         hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2033
2034         spc = MLX4_INLINE_ALIGN -
2035                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2036         if (sizeof (hdr) <= spc) {
2037                 memcpy(inl + 1, &hdr, sizeof (hdr));
2038                 wmb();
2039                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2040                 i = 1;
2041         } else {
2042                 memcpy(inl + 1, &hdr, spc);
2043                 wmb();
2044                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2045
2046                 inl = (void *) (inl + 1) + spc;
2047                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2048                 wmb();
2049                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2050                 i = 2;
2051         }
2052
2053         *mlx_seg_len =
2054                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2055 }
2056
2057 static void set_mlx_icrc_seg(void *dseg)
2058 {
2059         u32 *t = dseg;
2060         struct mlx4_wqe_inline_seg *iseg = dseg;
2061
2062         t[1] = 0;
2063
2064         /*
2065          * Need a barrier here before writing the byte_count field to
2066          * make sure that all the data is visible before the
2067          * byte_count field is set.  Otherwise, if the segment begins
2068          * a new cacheline, the HCA prefetcher could grab the 64-byte
2069          * chunk and get a valid (!= * 0xffffffff) byte count but
2070          * stale data, and end up sending the wrong data.
2071          */
2072         wmb();
2073
2074         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2075 }
2076
2077 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2078 {
2079         dseg->lkey       = cpu_to_be32(sg->lkey);
2080         dseg->addr       = cpu_to_be64(sg->addr);
2081
2082         /*
2083          * Need a barrier here before writing the byte_count field to
2084          * make sure that all the data is visible before the
2085          * byte_count field is set.  Otherwise, if the segment begins
2086          * a new cacheline, the HCA prefetcher could grab the 64-byte
2087          * chunk and get a valid (!= * 0xffffffff) byte count but
2088          * stale data, and end up sending the wrong data.
2089          */
2090         wmb();
2091
2092         dseg->byte_count = cpu_to_be32(sg->length);
2093 }
2094
2095 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2096 {
2097         dseg->byte_count = cpu_to_be32(sg->length);
2098         dseg->lkey       = cpu_to_be32(sg->lkey);
2099         dseg->addr       = cpu_to_be64(sg->addr);
2100 }
2101
2102 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
2103                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2104                          __be32 *lso_hdr_sz, __be32 *blh)
2105 {
2106         unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2107
2108         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2109                 *blh = cpu_to_be32(1 << 6);
2110
2111         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2112                      wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2113                 return -EINVAL;
2114
2115         memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2116
2117         *lso_hdr_sz  = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
2118                                    wr->wr.ud.hlen);
2119         *lso_seg_len = halign;
2120         return 0;
2121 }
2122
2123 static __be32 send_ieth(struct ib_send_wr *wr)
2124 {
2125         switch (wr->opcode) {
2126         case IB_WR_SEND_WITH_IMM:
2127         case IB_WR_RDMA_WRITE_WITH_IMM:
2128                 return wr->ex.imm_data;
2129
2130         case IB_WR_SEND_WITH_INV:
2131                 return cpu_to_be32(wr->ex.invalidate_rkey);
2132
2133         default:
2134                 return 0;
2135         }
2136 }
2137
2138 static void add_zero_len_inline(void *wqe)
2139 {
2140         struct mlx4_wqe_inline_seg *inl = wqe;
2141         memset(wqe, 0, 16);
2142         inl->byte_count = cpu_to_be32(1 << 31);
2143 }
2144
2145 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2146                       struct ib_send_wr **bad_wr)
2147 {
2148         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2149         void *wqe;
2150         struct mlx4_wqe_ctrl_seg *ctrl;
2151         struct mlx4_wqe_data_seg *dseg;
2152         unsigned long flags;
2153         int nreq;
2154         int err = 0;
2155         unsigned ind;
2156         int uninitialized_var(stamp);
2157         int uninitialized_var(size);
2158         unsigned uninitialized_var(seglen);
2159         __be32 dummy;
2160         __be32 *lso_wqe;
2161         __be32 uninitialized_var(lso_hdr_sz);
2162         __be32 blh;
2163         int i;
2164
2165         spin_lock_irqsave(&qp->sq.lock, flags);
2166
2167         ind = qp->sq_next_wqe;
2168
2169         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2170                 lso_wqe = &dummy;
2171                 blh = 0;
2172
2173                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2174                         err = -ENOMEM;
2175                         *bad_wr = wr;
2176                         goto out;
2177                 }
2178
2179                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2180                         err = -EINVAL;
2181                         *bad_wr = wr;
2182                         goto out;
2183                 }
2184
2185                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
2186                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
2187
2188                 ctrl->srcrb_flags =
2189                         (wr->send_flags & IB_SEND_SIGNALED ?
2190                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2191                         (wr->send_flags & IB_SEND_SOLICITED ?
2192                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
2193                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
2194                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2195                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
2196                         qp->sq_signal_bits;
2197
2198                 ctrl->imm = send_ieth(wr);
2199
2200                 wqe += sizeof *ctrl;
2201                 size = sizeof *ctrl / 16;
2202
2203                 switch (qp->mlx4_ib_qp_type) {
2204                 case MLX4_IB_QPT_RC:
2205                 case MLX4_IB_QPT_UC:
2206                         switch (wr->opcode) {
2207                         case IB_WR_ATOMIC_CMP_AND_SWP:
2208                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2209                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
2210                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2211                                               wr->wr.atomic.rkey);
2212                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2213
2214                                 set_atomic_seg(wqe, wr);
2215                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
2216
2217                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2218                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
2219
2220                                 break;
2221
2222                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2223                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2224                                               wr->wr.atomic.rkey);
2225                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2226
2227                                 set_masked_atomic_seg(wqe, wr);
2228                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
2229
2230                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2231                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
2232
2233                                 break;
2234
2235                         case IB_WR_RDMA_READ:
2236                         case IB_WR_RDMA_WRITE:
2237                         case IB_WR_RDMA_WRITE_WITH_IMM:
2238                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2239                                               wr->wr.rdma.rkey);
2240                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2241                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
2242                                 break;
2243
2244                         case IB_WR_LOCAL_INV:
2245                                 ctrl->srcrb_flags |=
2246                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2247                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2248                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
2249                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2250                                 break;
2251
2252                         case IB_WR_FAST_REG_MR:
2253                                 ctrl->srcrb_flags |=
2254                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2255                                 set_fmr_seg(wqe, wr);
2256                                 wqe  += sizeof (struct mlx4_wqe_fmr_seg);
2257                                 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2258                                 break;
2259
2260                         default:
2261                                 /* No extra segments required for sends */
2262                                 break;
2263                         }
2264                         break;
2265
2266                 case MLX4_IB_QPT_TUN_SMI_OWNER:
2267                         err =  build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2268                         if (unlikely(err)) {
2269                                 *bad_wr = wr;
2270                                 goto out;
2271                         }
2272                         wqe  += seglen;
2273                         size += seglen / 16;
2274                         break;
2275                 case MLX4_IB_QPT_TUN_SMI:
2276                 case MLX4_IB_QPT_TUN_GSI:
2277                         /* this is a UD qp used in MAD responses to slaves. */
2278                         set_datagram_seg(wqe, wr);
2279                         /* set the forced-loopback bit in the data seg av */
2280                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2281                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2282                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2283                         break;
2284                 case MLX4_IB_QPT_UD:
2285                         set_datagram_seg(wqe, wr);
2286                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2287                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2288
2289                         if (wr->opcode == IB_WR_LSO) {
2290                                 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
2291                                 if (unlikely(err)) {
2292                                         *bad_wr = wr;
2293                                         goto out;
2294                                 }
2295                                 lso_wqe = (__be32 *) wqe;
2296                                 wqe  += seglen;
2297                                 size += seglen / 16;
2298                         }
2299                         break;
2300
2301                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
2302                         if (unlikely(!mlx4_is_master(to_mdev(ibqp->device)->dev))) {
2303                                 err = -ENOSYS;
2304                                 *bad_wr = wr;
2305                                 goto out;
2306                         }
2307                         err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2308                         if (unlikely(err)) {
2309                                 *bad_wr = wr;
2310                                 goto out;
2311                         }
2312                         wqe  += seglen;
2313                         size += seglen / 16;
2314                         /* to start tunnel header on a cache-line boundary */
2315                         add_zero_len_inline(wqe);
2316                         wqe += 16;
2317                         size++;
2318                         build_tunnel_header(wr, wqe, &seglen);
2319                         wqe  += seglen;
2320                         size += seglen / 16;
2321                         break;
2322                 case MLX4_IB_QPT_PROXY_SMI:
2323                         /* don't allow QP0 sends on guests */
2324                         err = -ENOSYS;
2325                         *bad_wr = wr;
2326                         goto out;
2327                 case MLX4_IB_QPT_PROXY_GSI:
2328                         /* If we are tunneling special qps, this is a UD qp.
2329                          * In this case we first add a UD segment targeting
2330                          * the tunnel qp, and then add a header with address
2331                          * information */
2332                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr, ibqp->qp_type);
2333                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2334                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2335                         build_tunnel_header(wr, wqe, &seglen);
2336                         wqe  += seglen;
2337                         size += seglen / 16;
2338                         break;
2339
2340                 case MLX4_IB_QPT_SMI:
2341                 case MLX4_IB_QPT_GSI:
2342                         err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2343                         if (unlikely(err)) {
2344                                 *bad_wr = wr;
2345                                 goto out;
2346                         }
2347                         wqe  += seglen;
2348                         size += seglen / 16;
2349                         break;
2350
2351                 default:
2352                         break;
2353                 }
2354
2355                 /*
2356                  * Write data segments in reverse order, so as to
2357                  * overwrite cacheline stamp last within each
2358                  * cacheline.  This avoids issues with WQE
2359                  * prefetching.
2360                  */
2361
2362                 dseg = wqe;
2363                 dseg += wr->num_sge - 1;
2364                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
2365
2366                 /* Add one more inline data segment for ICRC for MLX sends */
2367                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2368                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2369                              qp->mlx4_ib_qp_type &
2370                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
2371                         set_mlx_icrc_seg(dseg + 1);
2372                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
2373                 }
2374
2375                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2376                         set_data_seg(dseg, wr->sg_list + i);
2377
2378                 /*
2379                  * Possibly overwrite stamping in cacheline with LSO
2380                  * segment only after making sure all data segments
2381                  * are written.
2382                  */
2383                 wmb();
2384                 *lso_wqe = lso_hdr_sz;
2385
2386                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2387                                     MLX4_WQE_CTRL_FENCE : 0) | size;
2388
2389                 /*
2390                  * Make sure descriptor is fully written before
2391                  * setting ownership bit (because HW can start
2392                  * executing as soon as we do).
2393                  */
2394                 wmb();
2395
2396                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
2397                         *bad_wr = wr;
2398                         err = -EINVAL;
2399                         goto out;
2400                 }
2401
2402                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
2403                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
2404
2405                 stamp = ind + qp->sq_spare_wqes;
2406                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2407
2408                 /*
2409                  * We can improve latency by not stamping the last
2410                  * send queue WQE until after ringing the doorbell, so
2411                  * only stamp here if there are still more WQEs to post.
2412                  *
2413                  * Same optimization applies to padding with NOP wqe
2414                  * in case of WQE shrinking (used to prevent wrap-around
2415                  * in the middle of WR).
2416                  */
2417                 if (wr->next) {
2418                         stamp_send_wqe(qp, stamp, size * 16);
2419                         ind = pad_wraparound(qp, ind);
2420                 }
2421         }
2422
2423 out:
2424         if (likely(nreq)) {
2425                 qp->sq.head += nreq;
2426
2427                 /*
2428                  * Make sure that descriptors are written before
2429                  * doorbell record.
2430                  */
2431                 wmb();
2432
2433                 writel(qp->doorbell_qpn,
2434                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
2435
2436                 /*
2437                  * Make sure doorbells don't leak out of SQ spinlock
2438                  * and reach the HCA out of order.
2439                  */
2440                 mmiowb();
2441
2442                 stamp_send_wqe(qp, stamp, size * 16);
2443
2444                 ind = pad_wraparound(qp, ind);
2445                 qp->sq_next_wqe = ind;
2446         }
2447
2448         spin_unlock_irqrestore(&qp->sq.lock, flags);
2449
2450         return err;
2451 }
2452
2453 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2454                       struct ib_recv_wr **bad_wr)
2455 {
2456         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2457         struct mlx4_wqe_data_seg *scat;
2458         unsigned long flags;
2459         int err = 0;
2460         int nreq;
2461         int ind;
2462         int max_gs;
2463         int i;
2464
2465         max_gs = qp->rq.max_gs;
2466         spin_lock_irqsave(&qp->rq.lock, flags);
2467
2468         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2469
2470         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2471                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2472                         err = -ENOMEM;
2473                         *bad_wr = wr;
2474                         goto out;
2475                 }
2476
2477                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2478                         err = -EINVAL;
2479                         *bad_wr = wr;
2480                         goto out;
2481                 }
2482
2483                 scat = get_recv_wqe(qp, ind);
2484
2485                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
2486                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
2487                         ib_dma_sync_single_for_device(ibqp->device,
2488                                                       qp->sqp_proxy_rcv[ind].map,
2489                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
2490                                                       DMA_FROM_DEVICE);
2491                         scat->byte_count =
2492                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
2493                         /* use dma lkey from upper layer entry */
2494                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
2495                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
2496                         scat++;
2497                         max_gs--;
2498                 }
2499
2500                 for (i = 0; i < wr->num_sge; ++i)
2501                         __set_data_seg(scat + i, wr->sg_list + i);
2502
2503                 if (i < max_gs) {
2504                         scat[i].byte_count = 0;
2505                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
2506                         scat[i].addr       = 0;
2507                 }
2508
2509                 qp->rq.wrid[ind] = wr->wr_id;
2510
2511                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2512         }
2513
2514 out:
2515         if (likely(nreq)) {
2516                 qp->rq.head += nreq;
2517
2518                 /*
2519                  * Make sure that descriptors are written before
2520                  * doorbell record.
2521                  */
2522                 wmb();
2523
2524                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2525         }
2526
2527         spin_unlock_irqrestore(&qp->rq.lock, flags);
2528
2529         return err;
2530 }
2531
2532 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
2533 {
2534         switch (mlx4_state) {
2535         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
2536         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
2537         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
2538         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
2539         case MLX4_QP_STATE_SQ_DRAINING:
2540         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
2541         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
2542         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
2543         default:                     return -1;
2544         }
2545 }
2546
2547 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
2548 {
2549         switch (mlx4_mig_state) {
2550         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
2551         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
2552         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
2553         default: return -1;
2554         }
2555 }
2556
2557 static int to_ib_qp_access_flags(int mlx4_flags)
2558 {
2559         int ib_flags = 0;
2560
2561         if (mlx4_flags & MLX4_QP_BIT_RRE)
2562                 ib_flags |= IB_ACCESS_REMOTE_READ;
2563         if (mlx4_flags & MLX4_QP_BIT_RWE)
2564                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2565         if (mlx4_flags & MLX4_QP_BIT_RAE)
2566                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2567
2568         return ib_flags;
2569 }
2570
2571 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2572                                 struct mlx4_qp_path *path)
2573 {
2574         struct mlx4_dev *dev = ibdev->dev;
2575         int is_eth;
2576
2577         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
2578         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
2579
2580         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
2581                 return;
2582
2583         is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
2584                 IB_LINK_LAYER_ETHERNET;
2585         if (is_eth)
2586                 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
2587                 ((path->sched_queue & 4) << 1);
2588         else
2589                 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
2590
2591         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
2592         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
2593         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
2594         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
2595         if (ib_ah_attr->ah_flags) {
2596                 ib_ah_attr->grh.sgid_index = path->mgid_index;
2597                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
2598                 ib_ah_attr->grh.traffic_class =
2599                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
2600                 ib_ah_attr->grh.flow_label =
2601                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
2602                 memcpy(ib_ah_attr->grh.dgid.raw,
2603                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
2604         }
2605 }
2606
2607 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
2608                      struct ib_qp_init_attr *qp_init_attr)
2609 {
2610         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2611         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2612         struct mlx4_qp_context context;
2613         int mlx4_state;
2614         int err = 0;
2615
2616         mutex_lock(&qp->mutex);
2617
2618         if (qp->state == IB_QPS_RESET) {
2619                 qp_attr->qp_state = IB_QPS_RESET;
2620                 goto done;
2621         }
2622
2623         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
2624         if (err) {
2625                 err = -EINVAL;
2626                 goto out;
2627         }
2628
2629         mlx4_state = be32_to_cpu(context.flags) >> 28;
2630
2631         qp->state                    = to_ib_qp_state(mlx4_state);
2632         qp_attr->qp_state            = qp->state;
2633         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
2634         qp_attr->path_mig_state      =
2635                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
2636         qp_attr->qkey                = be32_to_cpu(context.qkey);
2637         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
2638         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
2639         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
2640         qp_attr->qp_access_flags     =
2641                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
2642
2643         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
2644                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
2645                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
2646                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
2647                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
2648         }
2649
2650         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
2651         if (qp_attr->qp_state == IB_QPS_INIT)
2652                 qp_attr->port_num = qp->port;
2653         else
2654                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
2655
2656         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
2657         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
2658
2659         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
2660
2661         qp_attr->max_dest_rd_atomic =
2662                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
2663         qp_attr->min_rnr_timer      =
2664                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
2665         qp_attr->timeout            = context.pri_path.ackto >> 3;
2666         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
2667         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
2668         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
2669
2670 done:
2671         qp_attr->cur_qp_state        = qp_attr->qp_state;
2672         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
2673         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
2674
2675         if (!ibqp->uobject) {
2676                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
2677                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
2678         } else {
2679                 qp_attr->cap.max_send_wr  = 0;
2680                 qp_attr->cap.max_send_sge = 0;
2681         }
2682
2683         /*
2684          * We don't support inline sends for kernel QPs (yet), and we
2685          * don't know what userspace's value should be.
2686          */
2687         qp_attr->cap.max_inline_data = 0;
2688
2689         qp_init_attr->cap            = qp_attr->cap;
2690
2691         qp_init_attr->create_flags = 0;
2692         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2693                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
2694
2695         if (qp->flags & MLX4_IB_QP_LSO)
2696                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
2697
2698 out:
2699         mutex_unlock(&qp->mutex);
2700         return err;
2701 }
2702