drivers/i2c/busses/i2c-imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *      Copyright (C) 2002 Motorola GSG-China
   4  *
   5  * Author:
   6  *      Darius Augulis, Teltonika Inc.
   7  *
   8  * Desc.:
   9  *      Implementation of I2C Adapter/Algorithm Driver
  10  *      for I2C Bus integrated in Freescale i.MX/MXC processors
  11  *
  12  *      Derived from Motorola GSG China I2C example driver
  13  *
  14  *      Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
  15  *      Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
  16  *      Copyright (C) 2007 RightHand Technologies, Inc.
  17  *      Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  18  *
  19  *      Copyright 2013 Freescale Semiconductor, Inc.
  20  *
  21  */
  22
  23 #include <linux/acpi.h>
  24 #include <linux/clk.h>
  25 #include <linux/completion.h>
  26 #include <linux/delay.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/dmapool.h>
  30 #include <linux/err.h>
  31 #include <linux/errno.h>
  32 #include <linux/gpio/consumer.h>
  33 #include <linux/i2c.h>
  34 #include <linux/init.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/io.h>
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/of.h>
  40 #include <linux/of_device.h>
  41 #include <linux/of_dma.h>
  42 #include <linux/pinctrl/consumer.h>
  43 #include <linux/platform_data/i2c-imx.h>
  44 #include <linux/platform_device.h>
  45 #include <linux/pm_runtime.h>
  46 #include <linux/sched.h>
  47 #include <linux/slab.h>
  48
  49 /* This will be the driver name the kernel reports */
  50 #define DRIVER_NAME "imx-i2c"
  51
  52 /* Default value */
  53 #define IMX_I2C_BIT_RATE        100000  /* 100kHz */
  54
  55 /*
  56  * Enable DMA if transfer byte size is bigger than this threshold.
  57  * As the hardware request, it must bigger than 4 bytes.\
  58  * I have set '16' here, maybe it's not the best but I think it's
  59  * the appropriate.
  60  */
  61 #define DMA_THRESHOLD   16
  62 #define DMA_TIMEOUT     1000
  63
  64 /* IMX I2C registers:
  65  * the I2C register offset is different between SoCs,
  66  * to provid support for all these chips, split the
  67  * register offset into a fixed base address and a
  68  * variable shift value, then the full register offset
  69  * will be calculated by
  70  * reg_off = ( reg_base_addr << reg_shift)
  71  */
  72 #define IMX_I2C_IADR    0x00    /* i2c slave address */
  73 #define IMX_I2C_IFDR    0x01    /* i2c frequency divider */
  74 #define IMX_I2C_I2CR    0x02    /* i2c control */
  75 #define IMX_I2C_I2SR    0x03    /* i2c status */
  76 #define IMX_I2C_I2DR    0x04    /* i2c transfer data */
  77
  78 #define IMX_I2C_REGSHIFT        2
  79 #define VF610_I2C_REGSHIFT      0
  80
  81 /* Bits of IMX I2C registers */
  82 #define I2SR_RXAK       0x01
  83 #define I2SR_IIF        0x02
  84 #define I2SR_SRW        0x04
  85 #define I2SR_IAL        0x10
  86 #define I2SR_IBB        0x20
  87 #define I2SR_IAAS       0x40
  88 #define I2SR_ICF        0x80
  89 #define I2CR_DMAEN      0x02
  90 #define I2CR_RSTA       0x04
  91 #define I2CR_TXAK       0x08
  92 #define I2CR_MTX        0x10
  93 #define I2CR_MSTA       0x20
  94 #define I2CR_IIEN       0x40
  95 #define I2CR_IEN        0x80
  96
  97 /* register bits different operating codes definition:
  98  * 1) I2SR: Interrupt flags clear operation differ between SoCs:
  99  * - write zero to clear(w0c) INT flag on i.MX,
 100  * - but write one to clear(w1c) INT flag on Vybrid.
 101  * 2) I2CR: I2C module enable operation also differ between SoCs:
 102  * - set I2CR_IEN bit enable the module on i.MX,
 103  * - but clear I2CR_IEN bit enable the module on Vybrid.
 104  */
 105 #define I2SR_CLR_OPCODE_W0C     0x0
 106 #define I2SR_CLR_OPCODE_W1C     (I2SR_IAL | I2SR_IIF)
 107 #define I2CR_IEN_OPCODE_0       0x0
 108 #define I2CR_IEN_OPCODE_1       I2CR_IEN
 109
 110 #define I2C_PM_TIMEOUT          10 /* ms */
 111
 112 /*
 113  * sorted list of clock divider, register value pairs
 114  * taken from table 26-5, p.26-9, Freescale i.MX
 115  * Integrated Portable System Processor Reference Manual
 116  * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
 117  *
 118  * Duplicated divider values removed from list
 119  */
 120 struct imx_i2c_clk_pair {
 121         u16     div;
 122         u16     val;
 123 };
 124
 125 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
 126         { 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
 127         { 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
 128         { 42,   0x03 }, { 44,   0x27 }, { 48,   0x28 }, { 52,   0x05 },
 129         { 56,   0x29 }, { 60,   0x06 }, { 64,   0x2A }, { 72,   0x2B },
 130         { 80,   0x2C }, { 88,   0x09 }, { 96,   0x2D }, { 104,  0x0A },
 131         { 112,  0x2E }, { 128,  0x2F }, { 144,  0x0C }, { 160,  0x30 },
 132         { 192,  0x31 }, { 224,  0x32 }, { 240,  0x0F }, { 256,  0x33 },
 133         { 288,  0x10 }, { 320,  0x34 }, { 384,  0x35 }, { 448,  0x36 },
 134         { 480,  0x13 }, { 512,  0x37 }, { 576,  0x14 }, { 640,  0x38 },
 135         { 768,  0x39 }, { 896,  0x3A }, { 960,  0x17 }, { 1024, 0x3B },
 136         { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
 137         { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
 138         { 3072, 0x1E }, { 3840, 0x1F }
 139 };
 140
 141 /* Vybrid VF610 clock divider, register value pairs */
 142 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
 143         { 20,   0x00 }, { 22,   0x01 }, { 24,   0x02 }, { 26,   0x03 },
 144         { 28,   0x04 }, { 30,   0x05 }, { 32,   0x09 }, { 34,   0x06 },
 145         { 36,   0x0A }, { 40,   0x07 }, { 44,   0x0C }, { 48,   0x0D },
 146         { 52,   0x43 }, { 56,   0x0E }, { 60,   0x45 }, { 64,   0x12 },
 147         { 68,   0x0F }, { 72,   0x13 }, { 80,   0x14 }, { 88,   0x15 },
 148         { 96,   0x19 }, { 104,  0x16 }, { 112,  0x1A }, { 128,  0x17 },
 149         { 136,  0x4F }, { 144,  0x1C }, { 160,  0x1D }, { 176,  0x55 },
 150         { 192,  0x1E }, { 208,  0x56 }, { 224,  0x22 }, { 228,  0x24 },
 151         { 240,  0x1F }, { 256,  0x23 }, { 288,  0x5C }, { 320,  0x25 },
 152         { 384,  0x26 }, { 448,  0x2A }, { 480,  0x27 }, { 512,  0x2B },
 153         { 576,  0x2C }, { 640,  0x2D }, { 768,  0x31 }, { 896,  0x32 },
 154         { 960,  0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
 155         { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
 156         { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
 157         { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
 158 };
 159
 160 enum imx_i2c_type {
 161         IMX1_I2C,
 162         IMX21_I2C,
 163         VF610_I2C,
 164 };
 165
 166 struct imx_i2c_hwdata {
 167         enum imx_i2c_type       devtype;
 168         unsigned                regshift;
 169         struct imx_i2c_clk_pair *clk_div;
 170         unsigned                ndivs;
 171         unsigned                i2sr_clr_opcode;
 172         unsigned                i2cr_ien_opcode;
 173 };
 174
 175 struct imx_i2c_dma {
 176         struct dma_chan         *chan_tx;
 177         struct dma_chan         *chan_rx;
 178         struct dma_chan         *chan_using;
 179         struct completion       cmd_complete;
 180         dma_addr_t              dma_buf;
 181         unsigned int            dma_len;
 182         enum dma_transfer_direction dma_transfer_dir;
 183         enum dma_data_direction dma_data_dir;
 184 };
 185
 186 struct imx_i2c_struct {
 187         struct i2c_adapter      adapter;
 188         struct clk              *clk;
 189         struct notifier_block   clk_change_nb;
 190         void __iomem            *base;
 191         wait_queue_head_t       queue;
 192         unsigned long           i2csr;
 193         unsigned int            disable_delay;
 194         int                     stopped;
 195         unsigned int            ifdr; /* IMX_I2C_IFDR */
 196         unsigned int            cur_clk;
 197         unsigned int            bitrate;
 198         const struct imx_i2c_hwdata     *hwdata;
 199         struct i2c_bus_recovery_info rinfo;
 200
 201         struct pinctrl *pinctrl;
 202         struct pinctrl_state *pinctrl_pins_default;
 203         struct pinctrl_state *pinctrl_pins_gpio;
 204
 205         struct imx_i2c_dma      *dma;
 206 };
 207
 208 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
 209         .devtype                = IMX1_I2C,
 210         .regshift               = IMX_I2C_REGSHIFT,
 211         .clk_div                = imx_i2c_clk_div,
 212         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
 213         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
 214         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
 215
 216 };
 217
 218 static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
 219         .devtype                = IMX21_I2C,
 220         .regshift               = IMX_I2C_REGSHIFT,
 221         .clk_div                = imx_i2c_clk_div,
 222         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
 223         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
 224         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
 225
 226 };
 227
 228 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
 229         .devtype                = VF610_I2C,
 230         .regshift               = VF610_I2C_REGSHIFT,
 231         .clk_div                = vf610_i2c_clk_div,
 232         .ndivs                  = ARRAY_SIZE(vf610_i2c_clk_div),
 233         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W1C,
 234         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_0,
 235
 236 };
 237
 238 static const struct platform_device_id imx_i2c_devtype[] = {
 239         {
 240                 .name = "imx1-i2c",
 241                 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
 242         }, {
 243                 .name = "imx21-i2c",
 244                 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
 245         }, {
 246                 /* sentinel */
 247         }
 248 };
 249 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
 250
 251 static const struct of_device_id i2c_imx_dt_ids[] = {
 252         { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
 253         { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
 254         { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
 255         { /* sentinel */ }
 256 };
 257 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
 258
 259 static const struct acpi_device_id i2c_imx_acpi_ids[] = {
 260         {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata},
 261         { }
 262 };
 263 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids);
 264
 265 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
 266 {
 267         return i2c_imx->hwdata->devtype == IMX1_I2C;
 268 }
 269
 270 static inline void imx_i2c_write_reg(unsigned int val,
 271                 struct imx_i2c_struct *i2c_imx, unsigned int reg)
 272 {
 273         writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 274 }
 275
 276 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
 277                 unsigned int reg)
 278 {
 279         return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 280 }
 281
 282 /* Functions for DMA support */
 283 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
 284                                                 dma_addr_t phy_addr)
 285 {
 286         struct imx_i2c_dma *dma;
 287         struct dma_slave_config dma_sconfig;
 288         struct device *dev = &i2c_imx->adapter.dev;
 289         int ret;
 290
 291         dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
 292         if (!dma)
 293                 return;
 294
 295         dma->chan_tx = dma_request_chan(dev, "tx");
 296         if (IS_ERR(dma->chan_tx)) {
 297                 ret = PTR_ERR(dma->chan_tx);
 298                 if (ret != -ENODEV && ret != -EPROBE_DEFER)
 299                         dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
 300                 goto fail_al;
 301         }
 302
 303         dma_sconfig.dst_addr = phy_addr +
 304                                 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 305         dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 306         dma_sconfig.dst_maxburst = 1;
 307         dma_sconfig.direction = DMA_MEM_TO_DEV;
 308         ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
 309         if (ret < 0) {
 310                 dev_err(dev, "can't configure tx channel (%d)\n", ret);
 311                 goto fail_tx;
 312         }
 313
 314         dma->chan_rx = dma_request_chan(dev, "rx");
 315         if (IS_ERR(dma->chan_rx)) {
 316                 ret = PTR_ERR(dma->chan_rx);
 317                 if (ret != -ENODEV && ret != -EPROBE_DEFER)
 318                         dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
 319                 goto fail_tx;
 320         }
 321
 322         dma_sconfig.src_addr = phy_addr +
 323                                 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
 324         dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 325         dma_sconfig.src_maxburst = 1;
 326         dma_sconfig.direction = DMA_DEV_TO_MEM;
 327         ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
 328         if (ret < 0) {
 329                 dev_err(dev, "can't configure rx channel (%d)\n", ret);
 330                 goto fail_rx;
 331         }
 332
 333         i2c_imx->dma = dma;
 334         init_completion(&dma->cmd_complete);
 335         dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
 336                 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
 337
 338         return;
 339
 340 fail_rx:
 341         dma_release_channel(dma->chan_rx);
 342 fail_tx:
 343         dma_release_channel(dma->chan_tx);
 344 fail_al:
 345         devm_kfree(dev, dma);
 346 }
 347
 348 static void i2c_imx_dma_callback(void *arg)
 349 {
 350         struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
 351         struct imx_i2c_dma *dma = i2c_imx->dma;
 352
 353         dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
 354                         dma->dma_len, dma->dma_data_dir);
 355         complete(&dma->cmd_complete);
 356 }
 357
 358 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
 359                                         struct i2c_msg *msgs)
 360 {
 361         struct imx_i2c_dma *dma = i2c_imx->dma;
 362         struct dma_async_tx_descriptor *txdesc;
 363         struct device *dev = &i2c_imx->adapter.dev;
 364         struct device *chan_dev = dma->chan_using->device->dev;
 365
 366         dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
 367                                         dma->dma_len, dma->dma_data_dir);
 368         if (dma_mapping_error(chan_dev, dma->dma_buf)) {
 369                 dev_err(dev, "DMA mapping failed\n");
 370                 goto err_map;
 371         }
 372
 373         txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
 374                                         dma->dma_len, dma->dma_transfer_dir,
 375                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 376         if (!txdesc) {
 377                 dev_err(dev, "Not able to get desc for DMA xfer\n");
 378                 goto err_desc;
 379         }
 380
 381         reinit_completion(&dma->cmd_complete);
 382         txdesc->callback = i2c_imx_dma_callback;
 383         txdesc->callback_param = i2c_imx;
 384         if (dma_submit_error(dmaengine_submit(txdesc))) {
 385                 dev_err(dev, "DMA submit failed\n");
 386                 goto err_submit;
 387         }
 388
 389         dma_async_issue_pending(dma->chan_using);
 390         return 0;
 391
 392 err_submit:
 393         dmaengine_terminate_all(dma->chan_using);
 394 err_desc:
 395         dma_unmap_single(chan_dev, dma->dma_buf,
 396                         dma->dma_len, dma->dma_data_dir);
 397 err_map:
 398         return -EINVAL;
 399 }
 400
 401 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
 402 {
 403         struct imx_i2c_dma *dma = i2c_imx->dma;
 404
 405         dma->dma_buf = 0;
 406         dma->dma_len = 0;
 407
 408         dma_release_channel(dma->chan_tx);
 409         dma->chan_tx = NULL;
 410
 411         dma_release_channel(dma->chan_rx);
 412         dma->chan_rx = NULL;
 413
 414         dma->chan_using = NULL;
 415 }
 416
 417 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
 418 {
 419         unsigned long orig_jiffies = jiffies;
 420         unsigned int temp;
 421
 422         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 423
 424         while (1) {
 425                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 426
 427                 /* check for arbitration lost */
 428                 if (temp & I2SR_IAL) {
 429                         temp &= ~I2SR_IAL;
 430                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
 431                         return -EAGAIN;
 432                 }
 433
 434                 if (for_busy && (temp & I2SR_IBB)) {
 435                         i2c_imx->stopped = 0;
 436                         break;
 437                 }
 438                 if (!for_busy && !(temp & I2SR_IBB)) {
 439                         i2c_imx->stopped = 1;
 440                         break;
 441                 }
 442                 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
 443                         dev_dbg(&i2c_imx->adapter.dev,
 444                                 "<%s> I2C bus is busy\n", __func__);
 445                         return -ETIMEDOUT;
 446                 }
 447                 schedule();
 448         }
 449
 450         return 0;
 451 }
 452
 453 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
 454 {
 455         wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
 456
 457         if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
 458                 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
 459                 return -ETIMEDOUT;
 460         }
 461         dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
 462         i2c_imx->i2csr = 0;
 463         return 0;
 464 }
 465
 466 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
 467 {
 468         if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
 469                 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
 470                 return -ENXIO;  /* No ACK */
 471         }
 472
 473         dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
 474         return 0;
 475 }
 476
 477 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
 478                             unsigned int i2c_clk_rate)
 479 {
 480         struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
 481         unsigned int div;
 482         int i;
 483
 484         /* Divider value calculation */
 485         if (i2c_imx->cur_clk == i2c_clk_rate)
 486                 return;
 487
 488         i2c_imx->cur_clk = i2c_clk_rate;
 489
 490         div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
 491         if (div < i2c_clk_div[0].div)
 492                 i = 0;
 493         else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
 494                 i = i2c_imx->hwdata->ndivs - 1;
 495         else
 496                 for (i = 0; i2c_clk_div[i].div < div; i++)
 497                         ;
 498
 499         /* Store divider value */
 500         i2c_imx->ifdr = i2c_clk_div[i].val;
 501
 502         /*
 503          * There dummy delay is calculated.
 504          * It should be about one I2C clock period long.
 505          * This delay is used in I2C bus disable function
 506          * to fix chip hardware bug.
 507          */
 508         i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
 509                 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
 510
 511 #ifdef CONFIG_I2C_DEBUG_BUS
 512         dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
 513                 i2c_clk_rate, div);
 514         dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
 515                 i2c_clk_div[i].val, i2c_clk_div[i].div);
 516 #endif
 517 }
 518
 519 static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
 520                                      unsigned long action, void *data)
 521 {
 522         struct clk_notifier_data *ndata = data;
 523         struct imx_i2c_struct *i2c_imx = container_of(nb,
 524                                                       struct imx_i2c_struct,
 525                                                       clk_change_nb);
 526
 527         if (action & POST_RATE_CHANGE)
 528                 i2c_imx_set_clk(i2c_imx, ndata->new_rate);
 529
 530         return NOTIFY_OK;
 531 }
 532
 533 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
 534 {
 535         unsigned int temp = 0;
 536         int result;
 537
 538         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 539
 540         imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
 541         /* Enable I2C controller */
 542         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
 543         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
 544
 545         /* Wait controller to be stable */
 546         usleep_range(50, 150);
 547
 548         /* Start I2C transaction */
 549         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 550         temp |= I2CR_MSTA;
 551         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 552         result = i2c_imx_bus_busy(i2c_imx, 1);
 553         if (result)
 554                 return result;
 555
 556         temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
 557         temp &= ~I2CR_DMAEN;
 558         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 559         return result;
 560 }
 561
 562 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
 563 {
 564         unsigned int temp = 0;
 565
 566         if (!i2c_imx->stopped) {
 567                 /* Stop I2C transaction */
 568                 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 569                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 570                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 571                 if (i2c_imx->dma)
 572                         temp &= ~I2CR_DMAEN;
 573                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 574         }
 575         if (is_imx1_i2c(i2c_imx)) {
 576                 /*
 577                  * This delay caused by an i.MXL hardware bug.
 578                  * If no (or too short) delay, no "STOP" bit will be generated.
 579                  */
 580                 udelay(i2c_imx->disable_delay);
 581         }
 582
 583         if (!i2c_imx->stopped)
 584                 i2c_imx_bus_busy(i2c_imx, 0);
 585
 586         /* Disable I2C controller */
 587         temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
 588         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 589 }
 590
 591 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
 592 {
 593         struct imx_i2c_struct *i2c_imx = dev_id;
 594         unsigned int temp;
 595
 596         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 597         if (temp & I2SR_IIF) {
 598                 /* save status register */
 599                 i2c_imx->i2csr = temp;
 600                 temp &= ~I2SR_IIF;
 601                 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
 602                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
 603                 wake_up(&i2c_imx->queue);
 604                 return IRQ_HANDLED;
 605         }
 606
 607         return IRQ_NONE;
 608 }
 609
 610 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
 611                                         struct i2c_msg *msgs)
 612 {
 613         int result;
 614         unsigned long time_left;
 615         unsigned int temp = 0;
 616         unsigned long orig_jiffies = jiffies;
 617         struct imx_i2c_dma *dma = i2c_imx->dma;
 618         struct device *dev = &i2c_imx->adapter.dev;
 619
 620         dma->chan_using = dma->chan_tx;
 621         dma->dma_transfer_dir = DMA_MEM_TO_DEV;
 622         dma->dma_data_dir = DMA_TO_DEVICE;
 623         dma->dma_len = msgs->len - 1;
 624         result = i2c_imx_dma_xfer(i2c_imx, msgs);
 625         if (result)
 626                 return result;
 627
 628         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 629         temp |= I2CR_DMAEN;
 630         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 631
 632         /*
 633          * Write slave address.
 634          * The first byte must be transmitted by the CPU.
 635          */
 636         imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 637         time_left = wait_for_completion_timeout(
 638                                 &i2c_imx->dma->cmd_complete,
 639                                 msecs_to_jiffies(DMA_TIMEOUT));
 640         if (time_left == 0) {
 641                 dmaengine_terminate_all(dma->chan_using);
 642                 return -ETIMEDOUT;
 643         }
 644
 645         /* Waiting for transfer complete. */
 646         while (1) {
 647                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 648                 if (temp & I2SR_ICF)
 649                         break;
 650                 if (time_after(jiffies, orig_jiffies +
 651                                 msecs_to_jiffies(DMA_TIMEOUT))) {
 652                         dev_dbg(dev, "<%s> Timeout\n", __func__);
 653                         return -ETIMEDOUT;
 654                 }
 655                 schedule();
 656         }
 657
 658         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 659         temp &= ~I2CR_DMAEN;
 660         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 661
 662         /* The last data byte must be transferred by the CPU. */
 663         imx_i2c_write_reg(msgs->buf[msgs->len-1],
 664                                 i2c_imx, IMX_I2C_I2DR);
 665         result = i2c_imx_trx_complete(i2c_imx);
 666         if (result)
 667                 return result;
 668
 669         return i2c_imx_acked(i2c_imx);
 670 }
 671
 672 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
 673                         struct i2c_msg *msgs, bool is_lastmsg)
 674 {
 675         int result;
 676         unsigned long time_left;
 677         unsigned int temp;
 678         unsigned long orig_jiffies = jiffies;
 679         struct imx_i2c_dma *dma = i2c_imx->dma;
 680         struct device *dev = &i2c_imx->adapter.dev;
 681
 682
 683         dma->chan_using = dma->chan_rx;
 684         dma->dma_transfer_dir = DMA_DEV_TO_MEM;
 685         dma->dma_data_dir = DMA_FROM_DEVICE;
 686         /* The last two data bytes must be transferred by the CPU. */
 687         dma->dma_len = msgs->len - 2;
 688         result = i2c_imx_dma_xfer(i2c_imx, msgs);
 689         if (result)
 690                 return result;
 691
 692         time_left = wait_for_completion_timeout(
 693                                 &i2c_imx->dma->cmd_complete,
 694                                 msecs_to_jiffies(DMA_TIMEOUT));
 695         if (time_left == 0) {
 696                 dmaengine_terminate_all(dma->chan_using);
 697                 return -ETIMEDOUT;
 698         }
 699
 700         /* waiting for transfer complete. */
 701         while (1) {
 702                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 703                 if (temp & I2SR_ICF)
 704                         break;
 705                 if (time_after(jiffies, orig_jiffies +
 706                                 msecs_to_jiffies(DMA_TIMEOUT))) {
 707                         dev_dbg(dev, "<%s> Timeout\n", __func__);
 708                         return -ETIMEDOUT;
 709                 }
 710                 schedule();
 711         }
 712
 713         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 714         temp &= ~I2CR_DMAEN;
 715         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 716
 717         /* read n-1 byte data */
 718         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 719         temp |= I2CR_TXAK;
 720         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 721
 722         msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 723         /* read n byte data */
 724         result = i2c_imx_trx_complete(i2c_imx);
 725         if (result)
 726                 return result;
 727
 728         if (is_lastmsg) {
 729                 /*
 730                  * It must generate STOP before read I2DR to prevent
 731                  * controller from generating another clock cycle
 732                  */
 733                 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
 734                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 735                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 736                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 737                 i2c_imx_bus_busy(i2c_imx, 0);
 738         } else {
 739                 /*
 740                  * For i2c master receiver repeat restart operation like:
 741                  * read -> repeat MSTA -> read/write
 742                  * The controller must set MTX before read the last byte in
 743                  * the first read operation, otherwise the first read cost
 744                  * one extra clock cycle.
 745                  */
 746                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 747                 temp |= I2CR_MTX;
 748                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 749         }
 750         msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 751
 752         return 0;
 753 }
 754
 755 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
 756 {
 757         int i, result;
 758
 759         dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
 760                 __func__, i2c_8bit_addr_from_msg(msgs));
 761
 762         /* write slave address */
 763         imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 764         result = i2c_imx_trx_complete(i2c_imx);
 765         if (result)
 766                 return result;
 767         result = i2c_imx_acked(i2c_imx);
 768         if (result)
 769                 return result;
 770         dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
 771
 772         /* write data */
 773         for (i = 0; i < msgs->len; i++) {
 774                 dev_dbg(&i2c_imx->adapter.dev,
 775                         "<%s> write byte: B%d=0x%X\n",
 776                         __func__, i, msgs->buf[i]);
 777                 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
 778                 result = i2c_imx_trx_complete(i2c_imx);
 779                 if (result)
 780                         return result;
 781                 result = i2c_imx_acked(i2c_imx);
 782                 if (result)
 783                         return result;
 784         }
 785         return 0;
 786 }
 787
 788 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg)
 789 {
 790         int i, result;
 791         unsigned int temp;
 792         int block_data = msgs->flags & I2C_M_RECV_LEN;
 793         int use_dma = i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data;
 794
 795         dev_dbg(&i2c_imx->adapter.dev,
 796                 "<%s> write slave address: addr=0x%x\n",
 797                 __func__, i2c_8bit_addr_from_msg(msgs));
 798
 799         /* write slave address */
 800         imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
 801         result = i2c_imx_trx_complete(i2c_imx);
 802         if (result)
 803                 return result;
 804         result = i2c_imx_acked(i2c_imx);
 805         if (result)
 806                 return result;
 807
 808         dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
 809
 810         /* setup bus to read data */
 811         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 812         temp &= ~I2CR_MTX;
 813
 814         /*
 815          * Reset the I2CR_TXAK flag initially for SMBus block read since the
 816          * length is unknown
 817          */
 818         if ((msgs->len - 1) || block_data)
 819                 temp &= ~I2CR_TXAK;
 820         if (use_dma)
 821                 temp |= I2CR_DMAEN;
 822         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 823         imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
 824
 825         dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
 826
 827         if (use_dma)
 828                 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
 829
 830         /* read data */
 831         for (i = 0; i < msgs->len; i++) {
 832                 u8 len = 0;
 833
 834                 result = i2c_imx_trx_complete(i2c_imx);
 835                 if (result)
 836                         return result;
 837                 /*
 838                  * First byte is the length of remaining packet
 839                  * in the SMBus block data read. Add it to
 840                  * msgs->len.
 841                  */
 842                 if ((!i) && block_data) {
 843                         len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 844                         if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
 845                                 return -EPROTO;
 846                         dev_dbg(&i2c_imx->adapter.dev,
 847                                 "<%s> read length: 0x%X\n",
 848                                 __func__, len);
 849                         msgs->len += len;
 850                 }
 851                 if (i == (msgs->len - 1)) {
 852                         if (is_lastmsg) {
 853                                 /*
 854                                  * It must generate STOP before read I2DR to prevent
 855                                  * controller from generating another clock cycle
 856                                  */
 857                                 dev_dbg(&i2c_imx->adapter.dev,
 858                                         "<%s> clear MSTA\n", __func__);
 859                                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 860                                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 861                                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 862                                 i2c_imx_bus_busy(i2c_imx, 0);
 863                         } else {
 864                                 /*
 865                                  * For i2c master receiver repeat restart operation like:
 866                                  * read -> repeat MSTA -> read/write
 867                                  * The controller must set MTX before read the last byte in
 868                                  * the first read operation, otherwise the first read cost
 869                                  * one extra clock cycle.
 870                                  */
 871                                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 872                                 temp |= I2CR_MTX;
 873                                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 874                         }
 875                 } else if (i == (msgs->len - 2)) {
 876                         dev_dbg(&i2c_imx->adapter.dev,
 877                                 "<%s> set TXAK\n", __func__);
 878                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 879                         temp |= I2CR_TXAK;
 880                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 881                 }
 882                 if ((!i) && block_data)
 883                         msgs->buf[0] = len;
 884                 else
 885                         msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 886                 dev_dbg(&i2c_imx->adapter.dev,
 887                         "<%s> read byte: B%d=0x%X\n",
 888                         __func__, i, msgs->buf[i]);
 889         }
 890         return 0;
 891 }
 892
 893 static int i2c_imx_xfer(struct i2c_adapter *adapter,
 894                                                 struct i2c_msg *msgs, int num)
 895 {
 896         unsigned int i, temp;
 897         int result;
 898         bool is_lastmsg = false;
 899         struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
 900
 901         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 902
 903         result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
 904         if (result < 0)
 905                 goto out;
 906
 907         /* Start I2C transfer */
 908         result = i2c_imx_start(i2c_imx);
 909         if (result) {
 910                 if (i2c_imx->adapter.bus_recovery_info) {
 911                         i2c_recover_bus(&i2c_imx->adapter);
 912                         result = i2c_imx_start(i2c_imx);
 913                 }
 914         }
 915
 916         if (result)
 917                 goto fail0;
 918
 919         /* read/write data */
 920         for (i = 0; i < num; i++) {
 921                 if (i == num - 1)
 922                         is_lastmsg = true;
 923
 924                 if (i) {
 925                         dev_dbg(&i2c_imx->adapter.dev,
 926                                 "<%s> repeated start\n", __func__);
 927                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 928                         temp |= I2CR_RSTA;
 929                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 930                         result = i2c_imx_bus_busy(i2c_imx, 1);
 931                         if (result)
 932                                 goto fail0;
 933                 }
 934                 dev_dbg(&i2c_imx->adapter.dev,
 935                         "<%s> transfer message: %d\n", __func__, i);
 936                 /* write/read data */
 937 #ifdef CONFIG_I2C_DEBUG_BUS
 938                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 939                 dev_dbg(&i2c_imx->adapter.dev,
 940                         "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
 941                         __func__,
 942                         (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
 943                         (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
 944                         (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
 945                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 946                 dev_dbg(&i2c_imx->adapter.dev,
 947                         "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
 948                         __func__,
 949                         (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
 950                         (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
 951                         (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
 952                         (temp & I2SR_RXAK ? 1 : 0));
 953 #endif
 954                 if (msgs[i].flags & I2C_M_RD)
 955                         result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
 956                 else {
 957                         if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
 958                                 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
 959                         else
 960                                 result = i2c_imx_write(i2c_imx, &msgs[i]);
 961                 }
 962                 if (result)
 963                         goto fail0;
 964         }
 965
 966 fail0:
 967         /* Stop I2C transfer */
 968         i2c_imx_stop(i2c_imx);
 969
 970         pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
 971         pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
 972
 973 out:
 974         dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
 975                 (result < 0) ? "error" : "success msg",
 976                         (result < 0) ? result : num);
 977         return (result < 0) ? result : num;
 978 }
 979
 980 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
 981 {
 982         struct imx_i2c_struct *i2c_imx;
 983
 984         i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
 985
 986         pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
 987 }
 988
 989 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
 990 {
 991         struct imx_i2c_struct *i2c_imx;
 992
 993         i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
 994
 995         pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
 996 }
 997
 998 /*
 999  * We switch SCL and SDA to their GPIO function and do some bitbanging
1000  * for bus recovery. These alternative pinmux settings can be
1001  * described in the device tree by a separate pinctrl state "gpio". If
1002  * this is missing this is not a big problem, the only implication is
1003  * that we can't do bus recovery.
1004  */
1005 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
1006                 struct platform_device *pdev)
1007 {
1008         struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
1009
1010         i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1011         if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) {
1012                 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1013                 return PTR_ERR(i2c_imx->pinctrl);
1014         }
1015
1016         i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
1017                         PINCTRL_STATE_DEFAULT);
1018         i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
1019                         "gpio");
1020         rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
1021         rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
1022
1023         if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER ||
1024             PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) {
1025                 return -EPROBE_DEFER;
1026         } else if (IS_ERR(rinfo->sda_gpiod) ||
1027                    IS_ERR(rinfo->scl_gpiod) ||
1028                    IS_ERR(i2c_imx->pinctrl_pins_default) ||
1029                    IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1030                 dev_dbg(&pdev->dev, "recovery information incomplete\n");
1031                 return 0;
1032         }
1033
1034         dev_dbg(&pdev->dev, "using scl%s for recovery\n",
1035                 rinfo->sda_gpiod ? ",sda" : "");
1036
1037         rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1038         rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1039         rinfo->recover_bus = i2c_generic_scl_recovery;
1040         i2c_imx->adapter.bus_recovery_info = rinfo;
1041
1042         return 0;
1043 }
1044
1045 static u32 i2c_imx_func(struct i2c_adapter *adapter)
1046 {
1047         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1048                 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1049 }
1050
1051 static const struct i2c_algorithm i2c_imx_algo = {
1052         .master_xfer    = i2c_imx_xfer,
1053         .functionality  = i2c_imx_func,
1054 };
1055
1056 static int i2c_imx_probe(struct platform_device *pdev)
1057 {
1058         struct imx_i2c_struct *i2c_imx;
1059         struct resource *res;
1060         struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1061         void __iomem *base;
1062         int irq, ret;
1063         dma_addr_t phy_addr;
1064         const struct imx_i2c_hwdata *match;
1065
1066         dev_dbg(&pdev->dev, "<%s>\n", __func__);
1067
1068         irq = platform_get_irq(pdev, 0);
1069         if (irq < 0) {
1070                 dev_err(&pdev->dev, "can't get irq number\n");
1071                 return irq;
1072         }
1073
1074         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1075         base = devm_ioremap_resource(&pdev->dev, res);
1076         if (IS_ERR(base))
1077                 return PTR_ERR(base);
1078
1079         phy_addr = (dma_addr_t)res->start;
1080         i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1081         if (!i2c_imx)
1082                 return -ENOMEM;
1083
1084         match = device_get_match_data(&pdev->dev);
1085         if (match)
1086                 i2c_imx->hwdata = match;
1087         else
1088                 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1089                                 platform_get_device_id(pdev)->driver_data;
1090
1091         /* Setup i2c_imx driver structure */
1092         strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1093         i2c_imx->adapter.owner          = THIS_MODULE;
1094         i2c_imx->adapter.algo           = &i2c_imx_algo;
1095         i2c_imx->adapter.dev.parent     = &pdev->dev;
1096         i2c_imx->adapter.nr             = pdev->id;
1097         i2c_imx->adapter.dev.of_node    = pdev->dev.of_node;
1098         i2c_imx->base                   = base;
1099         ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev));
1100
1101         /* Get I2C clock */
1102         i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1103         if (IS_ERR(i2c_imx->clk)) {
1104                 if (PTR_ERR(i2c_imx->clk) != -EPROBE_DEFER)
1105                         dev_err(&pdev->dev, "can't get I2C clock\n");
1106                 return PTR_ERR(i2c_imx->clk);
1107         }
1108
1109         ret = clk_prepare_enable(i2c_imx->clk);
1110         if (ret) {
1111                 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret);
1112                 return ret;
1113         }
1114
1115         /* Request IRQ */
1116         ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, IRQF_SHARED,
1117                                 pdev->name, i2c_imx);
1118         if (ret) {
1119                 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1120                 goto clk_disable;
1121         }
1122
1123         /* Init queue */
1124         init_waitqueue_head(&i2c_imx->queue);
1125
1126         /* Set up adapter data */
1127         i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1128
1129         /* Set up platform driver data */
1130         platform_set_drvdata(pdev, i2c_imx);
1131
1132         pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1133         pm_runtime_use_autosuspend(&pdev->dev);
1134         pm_runtime_set_active(&pdev->dev);
1135         pm_runtime_enable(&pdev->dev);
1136
1137         ret = pm_runtime_get_sync(&pdev->dev);
1138         if (ret < 0)
1139                 goto rpm_disable;
1140
1141         /* Set up clock divider */
1142         i2c_imx->bitrate = IMX_I2C_BIT_RATE;
1143         ret = of_property_read_u32(pdev->dev.of_node,
1144                                    "clock-frequency", &i2c_imx->bitrate);
1145         if (ret < 0 && pdata && pdata->bitrate)
1146                 i2c_imx->bitrate = pdata->bitrate;
1147         i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1148         clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1149         i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
1150
1151         /* Set up chip registers to defaults */
1152         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
1153                         i2c_imx, IMX_I2C_I2CR);
1154         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
1155
1156         /* Init optional bus recovery function */
1157         ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
1158         /* Give it another chance if pinctrl used is not ready yet */
1159         if (ret == -EPROBE_DEFER)
1160                 goto clk_notifier_unregister;
1161
1162         /* Add I2C adapter */
1163         ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1164         if (ret < 0)
1165                 goto clk_notifier_unregister;
1166
1167         pm_runtime_mark_last_busy(&pdev->dev);
1168         pm_runtime_put_autosuspend(&pdev->dev);
1169
1170         dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1171         dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1172         dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1173                 i2c_imx->adapter.name);
1174         dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1175
1176         /* Init DMA config if supported */
1177         i2c_imx_dma_request(i2c_imx, phy_addr);
1178
1179         return 0;   /* Return OK */
1180
1181 clk_notifier_unregister:
1182         clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1183 rpm_disable:
1184         pm_runtime_put_noidle(&pdev->dev);
1185         pm_runtime_disable(&pdev->dev);
1186         pm_runtime_set_suspended(&pdev->dev);
1187         pm_runtime_dont_use_autosuspend(&pdev->dev);
1188
1189 clk_disable:
1190         clk_disable_unprepare(i2c_imx->clk);
1191         return ret;
1192 }
1193
1194 static int i2c_imx_remove(struct platform_device *pdev)
1195 {
1196         struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1197         int ret;
1198
1199         ret = pm_runtime_get_sync(&pdev->dev);
1200         if (ret < 0)
1201                 return ret;
1202
1203         /* remove adapter */
1204         dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1205         i2c_del_adapter(&i2c_imx->adapter);
1206
1207         if (i2c_imx->dma)
1208                 i2c_imx_dma_free(i2c_imx);
1209
1210         /* setup chip registers to defaults */
1211         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1212         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1213         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1214         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1215
1216         clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1217         clk_disable_unprepare(i2c_imx->clk);
1218
1219         pm_runtime_put_noidle(&pdev->dev);
1220         pm_runtime_disable(&pdev->dev);
1221
1222         return 0;
1223 }
1224
1225 static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev)
1226 {
1227         struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1228
1229         clk_disable(i2c_imx->clk);
1230
1231         return 0;
1232 }
1233
1234 static int __maybe_unused i2c_imx_runtime_resume(struct device *dev)
1235 {
1236         struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1237         int ret;
1238
1239         ret = clk_enable(i2c_imx->clk);
1240         if (ret)
1241                 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1242
1243         return ret;
1244 }
1245
1246 static const struct dev_pm_ops i2c_imx_pm_ops = {
1247         SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend,
1248                            i2c_imx_runtime_resume, NULL)
1249 };
1250
1251 static struct platform_driver i2c_imx_driver = {
1252         .probe = i2c_imx_probe,
1253         .remove = i2c_imx_remove,
1254         .driver = {
1255                 .name = DRIVER_NAME,
1256                 .pm = &i2c_imx_pm_ops,
1257                 .of_match_table = i2c_imx_dt_ids,
1258                 .acpi_match_table = i2c_imx_acpi_ids,
1259         },
1260         .id_table = imx_i2c_devtype,
1261 };
1262
1263 static int __init i2c_adap_imx_init(void)
1264 {
1265         return platform_driver_register(&i2c_imx_driver);
1266 }
1267 subsys_initcall(i2c_adap_imx_init);
1268
1269 static void __exit i2c_adap_imx_exit(void)
1270 {
1271         platform_driver_unregister(&i2c_imx_driver);
1272 }
1273 module_exit(i2c_adap_imx_exit);
1274
1275 MODULE_LICENSE("GPL");
1276 MODULE_AUTHOR("Darius Augulis");
1277 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1278 MODULE_ALIAS("platform:" DRIVER_NAME);