drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_crtc.h>
  18 #include <drm/drm_crtc_helper.h>
  19 #include <drm/drm_plane_helper.h>
  20
  21 #include <linux/kernel.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/clk.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/component.h>
  28
  29 #include <linux/reset.h>
  30 #include <linux/delay.h>
  31
  32 #include "rockchip_drm_drv.h"
  33 #include "rockchip_drm_gem.h"
  34 #include "rockchip_drm_fb.h"
  35 #include "rockchip_drm_vop.h"
  36
  37 #define VOP_REG(off, _mask, s) \
  38                 {.offset = off, \
  39                  .mask = _mask, \
  40                  .shift = s,}
  41
  42 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
  43                 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
  44 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
  45                 vop_mask_write(x, off, (mask) << shift, (v) << shift)
  46
  47 #define REG_SET(x, base, reg, v, mode) \
  48                 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
  49
  50 #define VOP_WIN_SET(x, win, name, v) \
  51                 REG_SET(x, win->base, win->phy->name, v, RELAXED)
  52 #define VOP_CTRL_SET(x, name, v) \
  53                 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
  54
  55 #define VOP_WIN_GET(x, win, name) \
  56                 vop_read_reg(x, win->base, &win->phy->name)
  57
  58 #define VOP_WIN_GET_YRGBADDR(vop, win) \
  59                 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
  60
  61 #define to_vop(x) container_of(x, struct vop, crtc)
  62 #define to_vop_win(x) container_of(x, struct vop_win, base)
  63
  64 struct vop_win_state {
  65         struct list_head head;
  66         struct drm_framebuffer *fb;
  67         dma_addr_t yrgb_mst;
  68         struct drm_pending_vblank_event *event;
  69 };
  70
  71 struct vop_win {
  72         struct drm_plane base;
  73         const struct vop_win_data *data;
  74         struct vop *vop;
  75
  76         struct list_head pending;
  77         struct vop_win_state *active;
  78 };
  79
  80 struct vop {
  81         struct drm_crtc crtc;
  82         struct device *dev;
  83         struct drm_device *drm_dev;
  84         unsigned int dpms;
  85
  86         int connector_type;
  87         int connector_out_mode;
  88
  89         /* mutex vsync_ work */
  90         struct mutex vsync_mutex;
  91         bool vsync_work_pending;
  92
  93         const struct vop_data *data;
  94
  95         uint32_t *regsbak;
  96         void __iomem *regs;
  97
  98         /* physical map length of vop register */
  99         uint32_t len;
 100
 101         /* one time only one process allowed to config the register */
 102         spinlock_t reg_lock;
 103         /* lock vop irq reg */
 104         spinlock_t irq_lock;
 105
 106         unsigned int irq;
 107
 108         /* vop AHP clk */
 109         struct clk *hclk;
 110         /* vop dclk */
 111         struct clk *dclk;
 112         /* vop share memory frequency */
 113         struct clk *aclk;
 114
 115         /* vop dclk reset */
 116         struct reset_control *dclk_rst;
 117
 118         int pipe;
 119
 120         struct vop_win win[];
 121 };
 122
 123 enum vop_data_format {
 124         VOP_FMT_ARGB8888 = 0,
 125         VOP_FMT_RGB888,
 126         VOP_FMT_RGB565,
 127         VOP_FMT_YUV420SP = 4,
 128         VOP_FMT_YUV422SP,
 129         VOP_FMT_YUV444SP,
 130 };
 131
 132 struct vop_reg_data {
 133         uint32_t offset;
 134         uint32_t value;
 135 };
 136
 137 struct vop_reg {
 138         uint32_t offset;
 139         uint32_t shift;
 140         uint32_t mask;
 141 };
 142
 143 struct vop_ctrl {
 144         struct vop_reg standby;
 145         struct vop_reg data_blank;
 146         struct vop_reg gate_en;
 147         struct vop_reg mmu_en;
 148         struct vop_reg rgb_en;
 149         struct vop_reg edp_en;
 150         struct vop_reg hdmi_en;
 151         struct vop_reg mipi_en;
 152         struct vop_reg out_mode;
 153         struct vop_reg dither_down;
 154         struct vop_reg dither_up;
 155         struct vop_reg pin_pol;
 156
 157         struct vop_reg htotal_pw;
 158         struct vop_reg hact_st_end;
 159         struct vop_reg vtotal_pw;
 160         struct vop_reg vact_st_end;
 161         struct vop_reg hpost_st_end;
 162         struct vop_reg vpost_st_end;
 163 };
 164
 165 struct vop_win_phy {
 166         const uint32_t *data_formats;
 167         uint32_t nformats;
 168
 169         struct vop_reg enable;
 170         struct vop_reg format;
 171         struct vop_reg act_info;
 172         struct vop_reg dsp_info;
 173         struct vop_reg dsp_st;
 174         struct vop_reg yrgb_mst;
 175         struct vop_reg uv_mst;
 176         struct vop_reg yrgb_vir;
 177         struct vop_reg uv_vir;
 178
 179         struct vop_reg dst_alpha_ctl;
 180         struct vop_reg src_alpha_ctl;
 181 };
 182
 183 struct vop_win_data {
 184         uint32_t base;
 185         const struct vop_win_phy *phy;
 186         enum drm_plane_type type;
 187 };
 188
 189 struct vop_data {
 190         const struct vop_reg_data *init_table;
 191         unsigned int table_size;
 192         const struct vop_ctrl *ctrl;
 193         const struct vop_win_data *win;
 194         unsigned int win_size;
 195 };
 196
 197 static const uint32_t formats_01[] = {
 198         DRM_FORMAT_XRGB8888,
 199         DRM_FORMAT_ARGB8888,
 200         DRM_FORMAT_RGB888,
 201         DRM_FORMAT_RGB565,
 202         DRM_FORMAT_NV12,
 203         DRM_FORMAT_NV16,
 204         DRM_FORMAT_NV24,
 205 };
 206
 207 static const uint32_t formats_234[] = {
 208         DRM_FORMAT_XRGB8888,
 209         DRM_FORMAT_ARGB8888,
 210         DRM_FORMAT_RGB888,
 211         DRM_FORMAT_RGB565,
 212 };
 213
 214 static const struct vop_win_phy win01_data = {
 215         .data_formats = formats_01,
 216         .nformats = ARRAY_SIZE(formats_01),
 217         .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
 218         .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
 219         .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
 220         .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
 221         .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
 222         .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
 223         .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
 224         .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
 225         .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
 226         .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
 227         .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
 228 };
 229
 230 static const struct vop_win_phy win23_data = {
 231         .data_formats = formats_234,
 232         .nformats = ARRAY_SIZE(formats_234),
 233         .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
 234         .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
 235         .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
 236         .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
 237         .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
 238         .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
 239         .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 240         .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
 241 };
 242
 243 static const struct vop_win_phy cursor_data = {
 244         .data_formats = formats_234,
 245         .nformats = ARRAY_SIZE(formats_234),
 246         .enable = VOP_REG(HWC_CTRL0, 0x1, 0),
 247         .format = VOP_REG(HWC_CTRL0, 0x7, 1),
 248         .dsp_st = VOP_REG(HWC_DSP_ST, 0x1fff1fff, 0),
 249         .yrgb_mst = VOP_REG(HWC_MST, 0xffffffff, 0),
 250 };
 251
 252 static const struct vop_ctrl ctrl_data = {
 253         .standby = VOP_REG(SYS_CTRL, 0x1, 22),
 254         .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
 255         .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
 256         .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
 257         .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
 258         .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
 259         .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
 260         .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
 261         .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
 262         .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
 263         .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
 264         .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
 265         .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 266         .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
 267         .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 268         .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
 269         .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 270         .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 271 };
 272
 273 static const struct vop_reg_data vop_init_reg_table[] = {
 274         {SYS_CTRL, 0x00c00000},
 275         {DSP_CTRL0, 0x00000000},
 276         {WIN0_CTRL0, 0x00000080},
 277         {WIN1_CTRL0, 0x00000080},
 278 };
 279
 280 /*
 281  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 282  * special support to get alpha blending working.  For now, just use overlay
 283  * window 1 for the drm cursor.
 284  */
 285 static const struct vop_win_data rk3288_vop_win_data[] = {
 286         { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY },
 287         { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_CURSOR },
 288         { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
 289         { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
 290         { .base = 0x00, .phy = &cursor_data, .type = DRM_PLANE_TYPE_OVERLAY },
 291 };
 292
 293 static const struct vop_data rk3288_vop = {
 294         .init_table = vop_init_reg_table,
 295         .table_size = ARRAY_SIZE(vop_init_reg_table),
 296         .ctrl = &ctrl_data,
 297         .win = rk3288_vop_win_data,
 298         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 299 };
 300
 301 static const struct of_device_id vop_driver_dt_match[] = {
 302         { .compatible = "rockchip,rk3288-vop",
 303           .data = &rk3288_vop },
 304         {},
 305 };
 306
 307 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 308 {
 309         writel(v, vop->regs + offset);
 310         vop->regsbak[offset >> 2] = v;
 311 }
 312
 313 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 314 {
 315         return readl(vop->regs + offset);
 316 }
 317
 318 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 319                                     const struct vop_reg *reg)
 320 {
 321         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 322 }
 323
 324 static inline void vop_cfg_done(struct vop *vop)
 325 {
 326         writel(0x01, vop->regs + REG_CFG_DONE);
 327 }
 328
 329 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 330                                   uint32_t mask, uint32_t v)
 331 {
 332         if (mask) {
 333                 uint32_t cached_val = vop->regsbak[offset >> 2];
 334
 335                 cached_val = (cached_val & ~mask) | v;
 336                 writel(cached_val, vop->regs + offset);
 337                 vop->regsbak[offset >> 2] = cached_val;
 338         }
 339 }
 340
 341 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
 342                                           uint32_t mask, uint32_t v)
 343 {
 344         if (mask) {
 345                 uint32_t cached_val = vop->regsbak[offset >> 2];
 346
 347                 cached_val = (cached_val & ~mask) | v;
 348                 writel_relaxed(cached_val, vop->regs + offset);
 349                 vop->regsbak[offset >> 2] = cached_val;
 350         }
 351 }
 352
 353 static enum vop_data_format vop_convert_format(uint32_t format)
 354 {
 355         switch (format) {
 356         case DRM_FORMAT_XRGB8888:
 357         case DRM_FORMAT_ARGB8888:
 358                 return VOP_FMT_ARGB8888;
 359         case DRM_FORMAT_RGB888:
 360                 return VOP_FMT_RGB888;
 361         case DRM_FORMAT_RGB565:
 362                 return VOP_FMT_RGB565;
 363         case DRM_FORMAT_NV12:
 364                 return VOP_FMT_YUV420SP;
 365         case DRM_FORMAT_NV16:
 366                 return VOP_FMT_YUV422SP;
 367         case DRM_FORMAT_NV24:
 368                 return VOP_FMT_YUV444SP;
 369         default:
 370                 DRM_ERROR("unsupport format[%08x]\n", format);
 371                 return -EINVAL;
 372         }
 373 }
 374
 375 static bool is_alpha_support(uint32_t format)
 376 {
 377         switch (format) {
 378         case DRM_FORMAT_ARGB8888:
 379                 return true;
 380         default:
 381                 return false;
 382         }
 383 }
 384
 385 static void vop_enable(struct drm_crtc *crtc)
 386 {
 387         struct vop *vop = to_vop(crtc);
 388         int ret;
 389
 390         ret = clk_enable(vop->hclk);
 391         if (ret < 0) {
 392                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 393                 return;
 394         }
 395
 396         ret = clk_enable(vop->dclk);
 397         if (ret < 0) {
 398                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 399                 goto err_disable_hclk;
 400         }
 401
 402         ret = clk_enable(vop->aclk);
 403         if (ret < 0) {
 404                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 405                 goto err_disable_dclk;
 406         }
 407
 408         /*
 409          * Slave iommu shares power, irq and clock with vop.  It was associated
 410          * automatically with this master device via common driver code.
 411          * Now that we have enabled the clock we attach it to the shared drm
 412          * mapping.
 413          */
 414         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 415         if (ret) {
 416                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 417                 goto err_disable_aclk;
 418         }
 419
 420         spin_lock(&vop->reg_lock);
 421
 422         VOP_CTRL_SET(vop, standby, 0);
 423
 424         spin_unlock(&vop->reg_lock);
 425
 426         enable_irq(vop->irq);
 427
 428         drm_vblank_on(vop->drm_dev, vop->pipe);
 429
 430         return;
 431
 432 err_disable_aclk:
 433         clk_disable(vop->aclk);
 434 err_disable_dclk:
 435         clk_disable(vop->dclk);
 436 err_disable_hclk:
 437         clk_disable(vop->hclk);
 438 }
 439
 440 static void vop_disable(struct drm_crtc *crtc)
 441 {
 442         struct vop *vop = to_vop(crtc);
 443
 444         drm_vblank_off(crtc->dev, vop->pipe);
 445
 446         disable_irq(vop->irq);
 447
 448         /*
 449          * TODO: Since standby doesn't take effect until the next vblank,
 450          * when we turn off dclk below, the vop is probably still active.
 451          */
 452         spin_lock(&vop->reg_lock);
 453
 454         VOP_CTRL_SET(vop, standby, 1);
 455
 456         spin_unlock(&vop->reg_lock);
 457         /*
 458          * disable dclk to stop frame scan, so we can safely detach iommu,
 459          */
 460         clk_disable(vop->dclk);
 461
 462         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 463
 464         clk_disable(vop->aclk);
 465         clk_disable(vop->hclk);
 466 }
 467
 468 /*
 469  * Caller must hold vsync_mutex.
 470  */
 471 static struct drm_framebuffer *vop_win_last_pending_fb(struct vop_win *vop_win)
 472 {
 473         struct vop_win_state *last;
 474         struct vop_win_state *active = vop_win->active;
 475
 476         if (list_empty(&vop_win->pending))
 477                 return active ? active->fb : NULL;
 478
 479         last = list_last_entry(&vop_win->pending, struct vop_win_state, head);
 480         return last ? last->fb : NULL;
 481 }
 482
 483 /*
 484  * Caller must hold vsync_mutex.
 485  */
 486 static int vop_win_queue_fb(struct vop_win *vop_win,
 487                             struct drm_framebuffer *fb, dma_addr_t yrgb_mst,
 488                             struct drm_pending_vblank_event *event)
 489 {
 490         struct vop_win_state *state;
 491
 492         state = kzalloc(sizeof(*state), GFP_KERNEL);
 493         if (!state)
 494                 return -ENOMEM;
 495
 496         state->fb = fb;
 497         state->yrgb_mst = yrgb_mst;
 498         state->event = event;
 499
 500         list_add_tail(&state->head, &vop_win->pending);
 501
 502         return 0;
 503 }
 504
 505 static int vop_update_plane_event(struct drm_plane *plane,
 506                                   struct drm_crtc *crtc,
 507                                   struct drm_framebuffer *fb, int crtc_x,
 508                                   int crtc_y, unsigned int crtc_w,
 509                                   unsigned int crtc_h, uint32_t src_x,
 510                                   uint32_t src_y, uint32_t src_w,
 511                                   uint32_t src_h,
 512                                   struct drm_pending_vblank_event *event)
 513 {
 514         struct vop_win *vop_win = to_vop_win(plane);
 515         const struct vop_win_data *win = vop_win->data;
 516         struct vop *vop = to_vop(crtc);
 517         struct drm_gem_object *obj;
 518         struct rockchip_gem_object *rk_obj;
 519         unsigned long offset;
 520         unsigned int actual_w;
 521         unsigned int actual_h;
 522         unsigned int dsp_stx;
 523         unsigned int dsp_sty;
 524         unsigned int y_vir_stride;
 525         dma_addr_t yrgb_mst;
 526         enum vop_data_format format;
 527         uint32_t val;
 528         bool is_alpha;
 529         bool visible;
 530         int ret;
 531         struct drm_rect dest = {
 532                 .x1 = crtc_x,
 533                 .y1 = crtc_y,
 534                 .x2 = crtc_x + crtc_w,
 535                 .y2 = crtc_y + crtc_h,
 536         };
 537         struct drm_rect src = {
 538                 /* 16.16 fixed point */
 539                 .x1 = src_x,
 540                 .y1 = src_y,
 541                 .x2 = src_x + src_w,
 542                 .y2 = src_y + src_h,
 543         };
 544         const struct drm_rect clip = {
 545                 .x2 = crtc->mode.hdisplay,
 546                 .y2 = crtc->mode.vdisplay,
 547         };
 548         bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY;
 549
 550         ret = drm_plane_helper_check_update(plane, crtc, fb,
 551                                             &src, &dest, &clip,
 552                                             DRM_PLANE_HELPER_NO_SCALING,
 553                                             DRM_PLANE_HELPER_NO_SCALING,
 554                                             can_position, false, &visible);
 555         if (ret)
 556                 return ret;
 557
 558         if (!visible)
 559                 return 0;
 560
 561         is_alpha = is_alpha_support(fb->pixel_format);
 562         format = vop_convert_format(fb->pixel_format);
 563         if (format < 0)
 564                 return format;
 565
 566         obj = rockchip_fb_get_gem_obj(fb, 0);
 567         if (!obj) {
 568                 DRM_ERROR("fail to get rockchip gem object from framebuffer\n");
 569                 return -EINVAL;
 570         }
 571
 572         rk_obj = to_rockchip_obj(obj);
 573
 574         actual_w = (src.x2 - src.x1) >> 16;
 575         actual_h = (src.y2 - src.y1) >> 16;
 576         crtc_x = max(0, crtc_x);
 577         crtc_y = max(0, crtc_y);
 578
 579         dsp_stx = crtc_x + crtc->mode.htotal - crtc->mode.hsync_start;
 580         dsp_sty = crtc_y + crtc->mode.vtotal - crtc->mode.vsync_start;
 581
 582         offset = (src.x1 >> 16) * (fb->bits_per_pixel >> 3);
 583         offset += (src.y1 >> 16) * fb->pitches[0];
 584         yrgb_mst = rk_obj->dma_addr + offset;
 585
 586         y_vir_stride = fb->pitches[0] / (fb->bits_per_pixel >> 3);
 587
 588         /*
 589          * If this plane update changes the plane's framebuffer, (or more
 590          * precisely, if this update has a different framebuffer than the last
 591          * update), enqueue it so we can track when it completes.
 592          *
 593          * Only when we discover that this update has completed, can we
 594          * unreference any previous framebuffers.
 595          */
 596         mutex_lock(&vop->vsync_mutex);
 597         if (fb != vop_win_last_pending_fb(vop_win)) {
 598                 ret = drm_vblank_get(plane->dev, vop->pipe);
 599                 if (ret) {
 600                         DRM_ERROR("failed to get vblank, %d\n", ret);
 601                         mutex_unlock(&vop->vsync_mutex);
 602                         return ret;
 603                 }
 604
 605                 drm_framebuffer_reference(fb);
 606
 607                 ret = vop_win_queue_fb(vop_win, fb, yrgb_mst, event);
 608                 if (ret) {
 609                         drm_vblank_put(plane->dev, vop->pipe);
 610                         mutex_unlock(&vop->vsync_mutex);
 611                         return ret;
 612                 }
 613
 614                 vop->vsync_work_pending = true;
 615         }
 616         mutex_unlock(&vop->vsync_mutex);
 617
 618         spin_lock(&vop->reg_lock);
 619
 620         VOP_WIN_SET(vop, win, format, format);
 621         VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride);
 622         VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst);
 623         val = (actual_h - 1) << 16;
 624         val |= (actual_w - 1) & 0xffff;
 625         VOP_WIN_SET(vop, win, act_info, val);
 626         VOP_WIN_SET(vop, win, dsp_info, val);
 627         val = (dsp_sty - 1) << 16;
 628         val |= (dsp_stx - 1) & 0xffff;
 629         VOP_WIN_SET(vop, win, dsp_st, val);
 630
 631         if (is_alpha) {
 632                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 633                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 634                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 635                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 636                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 637                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 638                         SRC_FACTOR_M0(ALPHA_ONE);
 639                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 640         } else {
 641                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 642         }
 643
 644         VOP_WIN_SET(vop, win, enable, 1);
 645
 646         vop_cfg_done(vop);
 647         spin_unlock(&vop->reg_lock);
 648
 649         return 0;
 650 }
 651
 652 static int vop_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 653                             struct drm_framebuffer *fb, int crtc_x, int crtc_y,
 654                             unsigned int crtc_w, unsigned int crtc_h,
 655                             uint32_t src_x, uint32_t src_y, uint32_t src_w,
 656                             uint32_t src_h)
 657 {
 658         return vop_update_plane_event(plane, crtc, fb, crtc_x, crtc_y, crtc_w,
 659                                       crtc_h, src_x, src_y, src_w, src_h,
 660                                       NULL);
 661 }
 662
 663 static int vop_update_primary_plane(struct drm_crtc *crtc,
 664                                     struct drm_pending_vblank_event *event)
 665 {
 666         unsigned int crtc_w, crtc_h;
 667
 668         crtc_w = crtc->primary->fb->width - crtc->x;
 669         crtc_h = crtc->primary->fb->height - crtc->y;
 670
 671         return vop_update_plane_event(crtc->primary, crtc, crtc->primary->fb,
 672                                       0, 0, crtc_w, crtc_h, crtc->x << 16,
 673                                       crtc->y << 16, crtc_w << 16,
 674                                       crtc_h << 16, event);
 675 }
 676
 677 static int vop_disable_plane(struct drm_plane *plane)
 678 {
 679         struct vop_win *vop_win = to_vop_win(plane);
 680         const struct vop_win_data *win = vop_win->data;
 681         struct vop *vop;
 682         int ret;
 683
 684         if (!plane->crtc)
 685                 return 0;
 686
 687         vop = to_vop(plane->crtc);
 688
 689         ret = drm_vblank_get(plane->dev, vop->pipe);
 690         if (ret) {
 691                 DRM_ERROR("failed to get vblank, %d\n", ret);
 692                 return ret;
 693         }
 694
 695         mutex_lock(&vop->vsync_mutex);
 696
 697         ret = vop_win_queue_fb(vop_win, NULL, 0, NULL);
 698         if (ret) {
 699                 drm_vblank_put(plane->dev, vop->pipe);
 700                 mutex_unlock(&vop->vsync_mutex);
 701                 return ret;
 702         }
 703
 704         vop->vsync_work_pending = true;
 705         mutex_unlock(&vop->vsync_mutex);
 706
 707         spin_lock(&vop->reg_lock);
 708         VOP_WIN_SET(vop, win, enable, 0);
 709         vop_cfg_done(vop);
 710         spin_unlock(&vop->reg_lock);
 711
 712         return 0;
 713 }
 714
 715 static void vop_plane_destroy(struct drm_plane *plane)
 716 {
 717         vop_disable_plane(plane);
 718         drm_plane_cleanup(plane);
 719 }
 720
 721 static const struct drm_plane_funcs vop_plane_funcs = {
 722         .update_plane = vop_update_plane,
 723         .disable_plane = vop_disable_plane,
 724         .destroy = vop_plane_destroy,
 725 };
 726
 727 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
 728                                   int connector_type,
 729                                   int out_mode)
 730 {
 731         struct vop *vop = to_vop(crtc);
 732
 733         vop->connector_type = connector_type;
 734         vop->connector_out_mode = out_mode;
 735
 736         return 0;
 737 }
 738 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
 739
 740 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 741 {
 742         struct vop *vop = to_vop(crtc);
 743         unsigned long flags;
 744
 745         if (vop->dpms != DRM_MODE_DPMS_ON)
 746                 return -EPERM;
 747
 748         spin_lock_irqsave(&vop->irq_lock, flags);
 749
 750         vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1));
 751
 752         spin_unlock_irqrestore(&vop->irq_lock, flags);
 753
 754         return 0;
 755 }
 756
 757 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 758 {
 759         struct vop *vop = to_vop(crtc);
 760         unsigned long flags;
 761
 762         if (vop->dpms != DRM_MODE_DPMS_ON)
 763                 return;
 764         spin_lock_irqsave(&vop->irq_lock, flags);
 765         vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0));
 766         spin_unlock_irqrestore(&vop->irq_lock, flags);
 767 }
 768
 769 static const struct rockchip_crtc_funcs private_crtc_funcs = {
 770         .enable_vblank = vop_crtc_enable_vblank,
 771         .disable_vblank = vop_crtc_disable_vblank,
 772 };
 773
 774 static void vop_crtc_dpms(struct drm_crtc *crtc, int mode)
 775 {
 776         struct vop *vop = to_vop(crtc);
 777
 778         DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc->base.id, mode);
 779
 780         if (vop->dpms == mode) {
 781                 DRM_DEBUG_KMS("desired dpms mode is same as previous one.\n");
 782                 return;
 783         }
 784
 785         switch (mode) {
 786         case DRM_MODE_DPMS_ON:
 787                 vop_enable(crtc);
 788                 break;
 789         case DRM_MODE_DPMS_STANDBY:
 790         case DRM_MODE_DPMS_SUSPEND:
 791         case DRM_MODE_DPMS_OFF:
 792                 vop_disable(crtc);
 793                 break;
 794         default:
 795                 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
 796                 break;
 797         }
 798
 799         vop->dpms = mode;
 800 }
 801
 802 static void vop_crtc_prepare(struct drm_crtc *crtc)
 803 {
 804         vop_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 805 }
 806
 807 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
 808                                 const struct drm_display_mode *mode,
 809                                 struct drm_display_mode *adjusted_mode)
 810 {
 811         if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
 812                 return false;
 813
 814         return true;
 815 }
 816
 817 static int vop_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 818                                   struct drm_framebuffer *old_fb)
 819 {
 820         int ret;
 821
 822         crtc->x = x;
 823         crtc->y = y;
 824
 825         ret = vop_update_primary_plane(crtc, NULL);
 826         if (ret < 0) {
 827                 DRM_ERROR("fail to update plane\n");
 828                 return ret;
 829         }
 830
 831         return 0;
 832 }
 833
 834 static int vop_crtc_mode_set(struct drm_crtc *crtc,
 835                              struct drm_display_mode *mode,
 836                              struct drm_display_mode *adjusted_mode,
 837                              int x, int y, struct drm_framebuffer *fb)
 838 {
 839         struct vop *vop = to_vop(crtc);
 840         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
 841         u16 hdisplay = adjusted_mode->hdisplay;
 842         u16 htotal = adjusted_mode->htotal;
 843         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
 844         u16 hact_end = hact_st + hdisplay;
 845         u16 vdisplay = adjusted_mode->vdisplay;
 846         u16 vtotal = adjusted_mode->vtotal;
 847         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
 848         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
 849         u16 vact_end = vact_st + vdisplay;
 850         int ret;
 851         uint32_t val;
 852
 853         /*
 854          * disable dclk to stop frame scan, so that we can safe config mode and
 855          * enable iommu.
 856          */
 857         clk_disable(vop->dclk);
 858
 859         switch (vop->connector_type) {
 860         case DRM_MODE_CONNECTOR_LVDS:
 861                 VOP_CTRL_SET(vop, rgb_en, 1);
 862                 break;
 863         case DRM_MODE_CONNECTOR_eDP:
 864                 VOP_CTRL_SET(vop, edp_en, 1);
 865                 break;
 866         case DRM_MODE_CONNECTOR_HDMIA:
 867                 VOP_CTRL_SET(vop, hdmi_en, 1);
 868                 break;
 869         default:
 870                 DRM_ERROR("unsupport connector_type[%d]\n",
 871                           vop->connector_type);
 872                 return -EINVAL;
 873         };
 874         VOP_CTRL_SET(vop, out_mode, vop->connector_out_mode);
 875
 876         val = 0x8;
 877         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0;
 878         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? (1 << 1) : 0;
 879         VOP_CTRL_SET(vop, pin_pol, val);
 880
 881         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
 882         val = hact_st << 16;
 883         val |= hact_end;
 884         VOP_CTRL_SET(vop, hact_st_end, val);
 885         VOP_CTRL_SET(vop, hpost_st_end, val);
 886
 887         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
 888         val = vact_st << 16;
 889         val |= vact_end;
 890         VOP_CTRL_SET(vop, vact_st_end, val);
 891         VOP_CTRL_SET(vop, vpost_st_end, val);
 892
 893         ret = vop_crtc_mode_set_base(crtc, x, y, fb);
 894         if (ret)
 895                 return ret;
 896
 897         /*
 898          * reset dclk, take all mode config affect, so the clk would run in
 899          * correct frame.
 900          */
 901         reset_control_assert(vop->dclk_rst);
 902         usleep_range(10, 20);
 903         reset_control_deassert(vop->dclk_rst);
 904
 905         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
 906         ret = clk_enable(vop->dclk);
 907         if (ret < 0) {
 908                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 909                 return ret;
 910         }
 911
 912         return 0;
 913 }
 914
 915 static void vop_crtc_commit(struct drm_crtc *crtc)
 916 {
 917 }
 918
 919 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
 920         .dpms = vop_crtc_dpms,
 921         .prepare = vop_crtc_prepare,
 922         .mode_fixup = vop_crtc_mode_fixup,
 923         .mode_set = vop_crtc_mode_set,
 924         .mode_set_base = vop_crtc_mode_set_base,
 925         .commit = vop_crtc_commit,
 926 };
 927
 928 static int vop_crtc_page_flip(struct drm_crtc *crtc,
 929                               struct drm_framebuffer *fb,
 930                               struct drm_pending_vblank_event *event,
 931                               uint32_t page_flip_flags)
 932 {
 933         struct vop *vop = to_vop(crtc);
 934         struct drm_framebuffer *old_fb = crtc->primary->fb;
 935         int ret;
 936
 937         /* when the page flip is requested, crtc's dpms should be on */
 938         if (vop->dpms > DRM_MODE_DPMS_ON) {
 939                 DRM_DEBUG("failed page flip request at dpms[%d].\n", vop->dpms);
 940                 return 0;
 941         }
 942
 943         crtc->primary->fb = fb;
 944
 945         ret = vop_update_primary_plane(crtc, event);
 946         if (ret)
 947                 crtc->primary->fb = old_fb;
 948
 949         return ret;
 950 }
 951
 952 static void vop_win_state_complete(struct vop_win *vop_win,
 953                                    struct vop_win_state *state)
 954 {
 955         struct vop *vop = vop_win->vop;
 956         struct drm_crtc *crtc = &vop->crtc;
 957         struct drm_device *drm = crtc->dev;
 958         unsigned long flags;
 959
 960         if (state->event) {
 961                 spin_lock_irqsave(&drm->event_lock, flags);
 962                 drm_send_vblank_event(drm, -1, state->event);
 963                 spin_unlock_irqrestore(&drm->event_lock, flags);
 964         }
 965
 966         list_del(&state->head);
 967         drm_vblank_put(crtc->dev, vop->pipe);
 968 }
 969
 970 static void vop_crtc_destroy(struct drm_crtc *crtc)
 971 {
 972         drm_crtc_cleanup(crtc);
 973 }
 974
 975 static const struct drm_crtc_funcs vop_crtc_funcs = {
 976         .set_config = drm_crtc_helper_set_config,
 977         .page_flip = vop_crtc_page_flip,
 978         .destroy = vop_crtc_destroy,
 979 };
 980
 981 static bool vop_win_state_is_active(struct vop_win *vop_win,
 982                                     struct vop_win_state *state)
 983 {
 984         bool active = false;
 985
 986         if (state->fb) {
 987                 dma_addr_t yrgb_mst;
 988
 989                 /* check yrgb_mst to tell if pending_fb is now front */
 990                 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
 991
 992                 active = (yrgb_mst == state->yrgb_mst);
 993         } else {
 994                 bool enabled;
 995
 996                 /* if enable bit is clear, plane is now disabled */
 997                 enabled = VOP_WIN_GET(vop_win->vop, vop_win->data, enable);
 998
 999                 active = (enabled == 0);
1000         }
1001
1002         return active;
1003 }
1004
1005 static void vop_win_state_destroy(struct vop_win_state *state)
1006 {
1007         struct drm_framebuffer *fb = state->fb;
1008
1009         if (fb)
1010                 drm_framebuffer_unreference(fb);
1011
1012         kfree(state);
1013 }
1014
1015 static void vop_win_update_state(struct vop_win *vop_win)
1016 {
1017         struct vop_win_state *state, *n, *new_active = NULL;
1018
1019         /* Check if any pending states are now active */
1020         list_for_each_entry(state, &vop_win->pending, head)
1021                 if (vop_win_state_is_active(vop_win, state)) {
1022                         new_active = state;
1023                         break;
1024                 }
1025
1026         if (!new_active)
1027                 return;
1028
1029         /*
1030          * Destroy any 'skipped' pending states - states that were queued
1031          * before the newly active state.
1032          */
1033         list_for_each_entry_safe(state, n, &vop_win->pending, head) {
1034                 if (state == new_active)
1035                         break;
1036                 vop_win_state_complete(vop_win, state);
1037                 vop_win_state_destroy(state);
1038         }
1039
1040         vop_win_state_complete(vop_win, new_active);
1041
1042         if (vop_win->active)
1043                 vop_win_state_destroy(vop_win->active);
1044         vop_win->active = new_active;
1045 }
1046
1047 static bool vop_win_has_pending_state(struct vop_win *vop_win)
1048 {
1049         return !list_empty(&vop_win->pending);
1050 }
1051
1052 static irqreturn_t vop_isr_thread(int irq, void *data)
1053 {
1054         struct vop *vop = data;
1055         const struct vop_data *vop_data = vop->data;
1056         unsigned int i;
1057
1058         mutex_lock(&vop->vsync_mutex);
1059
1060         if (!vop->vsync_work_pending)
1061                 goto done;
1062
1063         vop->vsync_work_pending = false;
1064
1065         for (i = 0; i < vop_data->win_size; i++) {
1066                 struct vop_win *vop_win = &vop->win[i];
1067
1068                 vop_win_update_state(vop_win);
1069                 if (vop_win_has_pending_state(vop_win))
1070                         vop->vsync_work_pending = true;
1071         }
1072
1073 done:
1074         mutex_unlock(&vop->vsync_mutex);
1075
1076         return IRQ_HANDLED;
1077 }
1078
1079 static irqreturn_t vop_isr(int irq, void *data)
1080 {
1081         struct vop *vop = data;
1082         uint32_t intr0_reg, active_irqs;
1083         unsigned long flags;
1084
1085         /*
1086          * INTR_CTRL0 register has interrupt status, enable and clear bits, we
1087          * must hold irq_lock to avoid a race with enable/disable_vblank().
1088         */
1089         spin_lock_irqsave(&vop->irq_lock, flags);
1090         intr0_reg = vop_readl(vop, INTR_CTRL0);
1091         active_irqs = intr0_reg & INTR_MASK;
1092         /* Clear all active interrupt sources */
1093         if (active_irqs)
1094                 vop_writel(vop, INTR_CTRL0,
1095                            intr0_reg | (active_irqs << INTR_CLR_SHIFT));
1096         spin_unlock_irqrestore(&vop->irq_lock, flags);
1097
1098         /* This is expected for vop iommu irqs, since the irq is shared */
1099         if (!active_irqs)
1100                 return IRQ_NONE;
1101
1102         /* Only Frame Start Interrupt is enabled; other irqs are spurious. */
1103         if (!(active_irqs & FS_INTR)) {
1104                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1105                 return IRQ_NONE;
1106         }
1107
1108         drm_handle_vblank(vop->drm_dev, vop->pipe);
1109
1110         return (vop->vsync_work_pending) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
1111 }
1112
1113 static int vop_create_crtc(struct vop *vop)
1114 {
1115         const struct vop_data *vop_data = vop->data;
1116         struct device *dev = vop->dev;
1117         struct drm_device *drm_dev = vop->drm_dev;
1118         struct drm_plane *primary = NULL, *cursor = NULL, *plane;
1119         struct drm_crtc *crtc = &vop->crtc;
1120         struct device_node *port;
1121         int ret;
1122         int i;
1123
1124         /*
1125          * Create drm_plane for primary and cursor planes first, since we need
1126          * to pass them to drm_crtc_init_with_planes, which sets the
1127          * "possible_crtcs" to the newly initialized crtc.
1128          */
1129         for (i = 0; i < vop_data->win_size; i++) {
1130                 struct vop_win *vop_win = &vop->win[i];
1131                 const struct vop_win_data *win_data = vop_win->data;
1132
1133                 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1134                     win_data->type != DRM_PLANE_TYPE_CURSOR)
1135                         continue;
1136
1137                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1138                                                0, &vop_plane_funcs,
1139                                                win_data->phy->data_formats,
1140                                                win_data->phy->nformats,
1141                                                win_data->type);
1142                 if (ret) {
1143                         DRM_ERROR("failed to initialize plane\n");
1144                         goto err_cleanup_planes;
1145                 }
1146
1147                 plane = &vop_win->base;
1148                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1149                         primary = plane;
1150                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1151                         cursor = plane;
1152         }
1153
1154         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1155                                         &vop_crtc_funcs);
1156         if (ret)
1157                 return ret;
1158
1159         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1160
1161         /*
1162          * Create drm_planes for overlay windows with possible_crtcs restricted
1163          * to the newly created crtc.
1164          */
1165         for (i = 0; i < vop_data->win_size; i++) {
1166                 struct vop_win *vop_win = &vop->win[i];
1167                 const struct vop_win_data *win_data = vop_win->data;
1168                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1169
1170                 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1171                         continue;
1172
1173                 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1174                                                possible_crtcs,
1175                                                &vop_plane_funcs,
1176                                                win_data->phy->data_formats,
1177                                                win_data->phy->nformats,
1178                                                win_data->type);
1179                 if (ret) {
1180                         DRM_ERROR("failed to initialize overlay plane\n");
1181                         goto err_cleanup_crtc;
1182                 }
1183         }
1184
1185         port = of_get_child_by_name(dev->of_node, "port");
1186         if (!port) {
1187                 DRM_ERROR("no port node found in %s\n",
1188                           dev->of_node->full_name);
1189                 goto err_cleanup_crtc;
1190         }
1191
1192         crtc->port = port;
1193         vop->pipe = drm_crtc_index(crtc);
1194         rockchip_register_crtc_funcs(drm_dev, &private_crtc_funcs, vop->pipe);
1195
1196         return 0;
1197
1198 err_cleanup_crtc:
1199         drm_crtc_cleanup(crtc);
1200 err_cleanup_planes:
1201         list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head)
1202                 drm_plane_cleanup(plane);
1203         return ret;
1204 }
1205
1206 static void vop_destroy_crtc(struct vop *vop)
1207 {
1208         struct drm_crtc *crtc = &vop->crtc;
1209
1210         rockchip_unregister_crtc_funcs(vop->drm_dev, vop->pipe);
1211         of_node_put(crtc->port);
1212         drm_crtc_cleanup(crtc);
1213 }
1214
1215 static int vop_initial(struct vop *vop)
1216 {
1217         const struct vop_data *vop_data = vop->data;
1218         const struct vop_reg_data *init_table = vop_data->init_table;
1219         struct reset_control *ahb_rst;
1220         int i, ret;
1221
1222         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1223         if (IS_ERR(vop->hclk)) {
1224                 dev_err(vop->dev, "failed to get hclk source\n");
1225                 return PTR_ERR(vop->hclk);
1226         }
1227         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1228         if (IS_ERR(vop->aclk)) {
1229                 dev_err(vop->dev, "failed to get aclk source\n");
1230                 return PTR_ERR(vop->aclk);
1231         }
1232         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1233         if (IS_ERR(vop->dclk)) {
1234                 dev_err(vop->dev, "failed to get dclk source\n");
1235                 return PTR_ERR(vop->dclk);
1236         }
1237
1238         ret = clk_prepare(vop->hclk);
1239         if (ret < 0) {
1240                 dev_err(vop->dev, "failed to prepare hclk\n");
1241                 return ret;
1242         }
1243
1244         ret = clk_prepare(vop->dclk);
1245         if (ret < 0) {
1246                 dev_err(vop->dev, "failed to prepare dclk\n");
1247                 goto err_unprepare_hclk;
1248         }
1249
1250         ret = clk_prepare(vop->aclk);
1251         if (ret < 0) {
1252                 dev_err(vop->dev, "failed to prepare aclk\n");
1253                 goto err_unprepare_dclk;
1254         }
1255
1256         /*
1257          * enable hclk, so that we can config vop register.
1258          */
1259         ret = clk_enable(vop->hclk);
1260         if (ret < 0) {
1261                 dev_err(vop->dev, "failed to prepare aclk\n");
1262                 goto err_unprepare_aclk;
1263         }
1264         /*
1265          * do hclk_reset, reset all vop registers.
1266          */
1267         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1268         if (IS_ERR(ahb_rst)) {
1269                 dev_err(vop->dev, "failed to get ahb reset\n");
1270                 ret = PTR_ERR(ahb_rst);
1271                 goto err_disable_hclk;
1272         }
1273         reset_control_assert(ahb_rst);
1274         usleep_range(10, 20);
1275         reset_control_deassert(ahb_rst);
1276
1277         memcpy(vop->regsbak, vop->regs, vop->len);
1278
1279         for (i = 0; i < vop_data->table_size; i++)
1280                 vop_writel(vop, init_table[i].offset, init_table[i].value);
1281
1282         for (i = 0; i < vop_data->win_size; i++) {
1283                 const struct vop_win_data *win = &vop_data->win[i];
1284
1285                 VOP_WIN_SET(vop, win, enable, 0);
1286         }
1287
1288         vop_cfg_done(vop);
1289
1290         /*
1291          * do dclk_reset, let all config take affect.
1292          */
1293         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1294         if (IS_ERR(vop->dclk_rst)) {
1295                 dev_err(vop->dev, "failed to get dclk reset\n");
1296                 ret = PTR_ERR(vop->dclk_rst);
1297                 goto err_unprepare_aclk;
1298         }
1299         reset_control_assert(vop->dclk_rst);
1300         usleep_range(10, 20);
1301         reset_control_deassert(vop->dclk_rst);
1302
1303         clk_disable(vop->hclk);
1304
1305         vop->dpms = DRM_MODE_DPMS_OFF;
1306
1307         return 0;
1308
1309 err_disable_hclk:
1310         clk_disable(vop->hclk);
1311 err_unprepare_aclk:
1312         clk_unprepare(vop->aclk);
1313 err_unprepare_dclk:
1314         clk_unprepare(vop->dclk);
1315 err_unprepare_hclk:
1316         clk_unprepare(vop->hclk);
1317         return ret;
1318 }
1319
1320 /*
1321  * Initialize the vop->win array elements.
1322  */
1323 static void vop_win_init(struct vop *vop)
1324 {
1325         const struct vop_data *vop_data = vop->data;
1326         unsigned int i;
1327
1328         for (i = 0; i < vop_data->win_size; i++) {
1329                 struct vop_win *vop_win = &vop->win[i];
1330                 const struct vop_win_data *win_data = &vop_data->win[i];
1331
1332                 vop_win->data = win_data;
1333                 vop_win->vop = vop;
1334                 INIT_LIST_HEAD(&vop_win->pending);
1335         }
1336 }
1337
1338 static int vop_bind(struct device *dev, struct device *master, void *data)
1339 {
1340         struct platform_device *pdev = to_platform_device(dev);
1341         const struct of_device_id *of_id;
1342         const struct vop_data *vop_data;
1343         struct drm_device *drm_dev = data;
1344         struct vop *vop;
1345         struct resource *res;
1346         size_t alloc_size;
1347         int ret;
1348
1349         of_id = of_match_device(vop_driver_dt_match, dev);
1350         vop_data = of_id->data;
1351         if (!vop_data)
1352                 return -ENODEV;
1353
1354         /* Allocate vop struct and its vop_win array */
1355         alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1356         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1357         if (!vop)
1358                 return -ENOMEM;
1359
1360         vop->dev = dev;
1361         vop->data = vop_data;
1362         vop->drm_dev = drm_dev;
1363         dev_set_drvdata(dev, vop);
1364
1365         vop_win_init(vop);
1366
1367         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1368         vop->len = resource_size(res);
1369         vop->regs = devm_ioremap_resource(dev, res);
1370         if (IS_ERR(vop->regs))
1371                 return PTR_ERR(vop->regs);
1372
1373         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1374         if (!vop->regsbak)
1375                 return -ENOMEM;
1376
1377         ret = vop_initial(vop);
1378         if (ret < 0) {
1379                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1380                 return ret;
1381         }
1382
1383         vop->irq = platform_get_irq(pdev, 0);
1384         if (vop->irq < 0) {
1385                 dev_err(dev, "cannot find irq for vop\n");
1386                 return vop->irq;
1387         }
1388
1389         spin_lock_init(&vop->reg_lock);
1390         spin_lock_init(&vop->irq_lock);
1391
1392         mutex_init(&vop->vsync_mutex);
1393
1394         ret = devm_request_threaded_irq(dev, vop->irq, vop_isr, vop_isr_thread,
1395                                         IRQF_SHARED, dev_name(dev), vop);
1396         if (ret)
1397                 return ret;
1398
1399         /* IRQ is initially disabled; it gets enabled in power_on */
1400         disable_irq(vop->irq);
1401
1402         ret = vop_create_crtc(vop);
1403         if (ret)
1404                 return ret;
1405
1406         pm_runtime_enable(&pdev->dev);
1407         return 0;
1408 }
1409
1410 static void vop_unbind(struct device *dev, struct device *master, void *data)
1411 {
1412         struct vop *vop = dev_get_drvdata(dev);
1413
1414         pm_runtime_disable(dev);
1415         vop_destroy_crtc(vop);
1416 }
1417
1418 static const struct component_ops vop_component_ops = {
1419         .bind = vop_bind,
1420         .unbind = vop_unbind,
1421 };
1422
1423 static int vop_probe(struct platform_device *pdev)
1424 {
1425         struct device *dev = &pdev->dev;
1426
1427         if (!dev->of_node) {
1428                 dev_err(dev, "can't find vop devices\n");
1429                 return -ENODEV;
1430         }
1431
1432         return component_add(dev, &vop_component_ops);
1433 }
1434
1435 static int vop_remove(struct platform_device *pdev)
1436 {
1437         component_del(&pdev->dev, &vop_component_ops);
1438
1439         return 0;
1440 }
1441
1442 struct platform_driver vop_platform_driver = {
1443         .probe = vop_probe,
1444         .remove = vop_remove,
1445         .driver = {
1446                 .name = "rockchip-vop",
1447                 .owner = THIS_MODULE,
1448                 .of_match_table = of_match_ptr(vop_driver_dt_match),
1449         },
1450 };
1451
1452 module_platform_driver(vop_platform_driver);
1453
1454 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
1455 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
1456 MODULE_LICENSE("GPL v2");