1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __NVIF_CLASS_H__
3 #define __NVIF_CLASS_H__
5 /* these class numbers are made up by us, and not nvidia-assigned */
6 #define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000
8 #define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001
10 #define NVIF_CLASS_PERFMON /* if0002.h */ -0x00000002
11 #define NVIF_CLASS_PERFDOM /* if0003.h */ -0x00000003
13 #define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004
14 #define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005
15 #define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006
16 #define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007
18 /* the below match nvidia-assigned (either in hw, or sw) class numbers */
19 #define NV_NULL_CLASS 0x00000030
21 #define NV_DEVICE /* cl0080.h */ 0x00000080
23 #define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002
24 #define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003
25 #define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d
27 #define NV50_TWOD 0x0000502d
28 #define FERMI_TWOD_A 0x0000902d
30 #define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
31 #define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039
33 #define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
34 #define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
36 #define NV04_DISP /* cl0046.h */ 0x00000046
38 #define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b
39 #define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e
40 #define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e
41 #define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e
42 #define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e
43 #define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e
45 #define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f
46 #define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f
47 #define FERMI_CHANNEL_GPFIFO /* cl906f.h */ 0x0000906f
48 #define KEPLER_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000a06f
49 #define KEPLER_CHANNEL_GPFIFO_B /* cla06f.h */ 0x0000a16f
50 #define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f
51 #define PASCAL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000c06f
53 #define NV50_DISP /* cl5070.h */ 0x00005070
54 #define G82_DISP /* cl5070.h */ 0x00008270
55 #define GT200_DISP /* cl5070.h */ 0x00008370
56 #define GT214_DISP /* cl5070.h */ 0x00008570
57 #define GT206_DISP /* cl5070.h */ 0x00008870
58 #define GF110_DISP /* cl5070.h */ 0x00009070
59 #define GK104_DISP /* cl5070.h */ 0x00009170
60 #define GK110_DISP /* cl5070.h */ 0x00009270
61 #define GM107_DISP /* cl5070.h */ 0x00009470
62 #define GM200_DISP /* cl5070.h */ 0x00009570
63 #define GP100_DISP /* cl5070.h */ 0x00009770
64 #define GP102_DISP /* cl5070.h */ 0x00009870
66 #define NV31_MPEG 0x00003174
67 #define G82_MPEG 0x00008274
69 #define NV74_VP2 0x00007476
71 #define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a
72 #define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a
73 #define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a
74 #define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a
75 #define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a
77 #define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b
78 #define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b
79 #define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b
80 #define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b
81 #define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b
83 #define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c
84 #define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c
85 #define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c
86 #define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c
87 #define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c
88 #define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c
89 #define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c
91 #define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d
92 #define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d
93 #define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d
94 #define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d
95 #define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d
96 #define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d
97 #define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d
98 #define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d
99 #define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d
100 #define GM200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d
101 #define GP100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000977d
102 #define GP102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000987d
104 #define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e
105 #define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e
106 #define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e
107 #define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e
108 #define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e
109 #define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e
111 #define NV50_TESLA 0x00005097
112 #define G82_TESLA 0x00008297
113 #define GT200_TESLA 0x00008397
114 #define GT214_TESLA 0x00008597
115 #define GT21A_TESLA 0x00008697
117 #define FERMI_A /* cl9097.h */ 0x00009097
118 #define FERMI_B /* cl9097.h */ 0x00009197
119 #define FERMI_C /* cl9097.h */ 0x00009297
121 #define KEPLER_A /* cl9097.h */ 0x0000a097
122 #define KEPLER_B /* cl9097.h */ 0x0000a197
123 #define KEPLER_C /* cl9097.h */ 0x0000a297
125 #define MAXWELL_A /* cl9097.h */ 0x0000b097
126 #define MAXWELL_B /* cl9097.h */ 0x0000b197
128 #define PASCAL_A /* cl9097.h */ 0x0000c097
129 #define PASCAL_B /* cl9097.h */ 0x0000c197
131 #define NV74_BSP 0x000074b0
133 #define GT212_MSVLD 0x000085b1
134 #define IGT21A_MSVLD 0x000086b1
135 #define G98_MSVLD 0x000088b1
136 #define GF100_MSVLD 0x000090b1
137 #define GK104_MSVLD 0x000095b1
139 #define GT212_MSPDEC 0x000085b2
140 #define G98_MSPDEC 0x000088b2
141 #define GF100_MSPDEC 0x000090b2
142 #define GK104_MSPDEC 0x000095b2
144 #define GT212_MSPPP 0x000085b3
145 #define G98_MSPPP 0x000088b3
146 #define GF100_MSPPP 0x000090b3
148 #define G98_SEC 0x000088b4
150 #define GT212_DMA 0x000085b5
151 #define FERMI_DMA 0x000090b5
152 #define KEPLER_DMA_COPY_A 0x0000a0b5
153 #define MAXWELL_DMA_COPY_A 0x0000b0b5
154 #define PASCAL_DMA_COPY_A 0x0000c0b5
155 #define PASCAL_DMA_COPY_B 0x0000c1b5
157 #define FERMI_DECOMPRESS 0x000090b8
159 #define NV50_COMPUTE 0x000050c0
160 #define GT214_COMPUTE 0x000085c0
161 #define FERMI_COMPUTE_A 0x000090c0
162 #define FERMI_COMPUTE_B 0x000091c0
163 #define KEPLER_COMPUTE_A 0x0000a0c0
164 #define KEPLER_COMPUTE_B 0x0000a1c0
165 #define MAXWELL_COMPUTE_A 0x0000b0c0
166 #define MAXWELL_COMPUTE_B 0x0000b1c0
167 #define PASCAL_COMPUTE_A 0x0000c0c0
168 #define PASCAL_COMPUTE_B 0x0000c1c0
170 #define NV74_CIPHER 0x000074c1