drivers/gpu/drm/meson/meson_vpp.c

   1 /*
   2  * Copyright (C) 2016 BayLibre, SAS
   3  * Author: Neil Armstrong <narmstrong@baylibre.com>
   4  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   5  * Copyright (C) 2014 Endless Mobile
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of the
  10  * License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <drm/drmP.h>
  24 #include "meson_drv.h"
  25 #include "meson_vpp.h"
  26 #include "meson_registers.h"
  27
  28 /**
  29  * DOC: Video Post Processing
  30  *
  31  * VPP Handles all the Post Processing after the Scanout from the VIU
  32  * We handle the following post processings :
  33  *
  34  * - Postblend, Blends the OSD1 only
  35  *      We exclude OSD2, VS1, VS1 and Preblend output
  36  * - Vertical OSD Scaler for OSD1 only, we disable vertical scaler and
  37  *      use it only for interlace scanout
  38  * - Intermediate FIFO with default Amlogic values
  39  *
  40  * What is missing :
  41  *
  42  * - Preblend for video overlay pre-scaling
  43  * - OSD2 support for cursor framebuffer
  44  * - Video pre-scaling before postblend
  45  * - Full Vertical/Horizontal OSD scaling to support TV overscan
  46  * - HDR conversion
  47  */
  48
  49 void meson_vpp_setup_mux(struct meson_drm *priv, unsigned int mux)
  50 {
  51         writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL));
  52 }
  53
  54 static unsigned int vpp_filter_coefs_4point_bspline[] = {
  55         0x15561500, 0x14561600, 0x13561700, 0x12561800,
  56         0x11551a00, 0x11541b00, 0x10541c00, 0x0f541d00,
  57         0x0f531e00, 0x0e531f00, 0x0d522100, 0x0c522200,
  58         0x0b522300, 0x0b512400, 0x0a502600, 0x0a4f2700,
  59         0x094e2900, 0x084e2a00, 0x084d2b00, 0x074c2c01,
  60         0x074b2d01, 0x064a2f01, 0x06493001, 0x05483201,
  61         0x05473301, 0x05463401, 0x04453601, 0x04433702,
  62         0x04423802, 0x03413a02, 0x03403b02, 0x033f3c02,
  63         0x033d3d03
  64 };
  65
  66 static void meson_vpp_write_scaling_filter_coefs(struct meson_drm *priv,
  67                                                  const unsigned int *coefs,
  68                                                  bool is_horizontal)
  69 {
  70         int i;
  71
  72         writel_relaxed(is_horizontal ? BIT(8) : 0,
  73                         priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX));
  74         for (i = 0; i < 33; i++)
  75                 writel_relaxed(coefs[i],
  76                                 priv->io_base + _REG(VPP_OSD_SCALE_COEF));
  77 }
  78
  79 static const uint32_t vpp_filter_coefs_bicubic[] = {
  80         0x00800000, 0x007f0100, 0xff7f0200, 0xfe7f0300,
  81         0xfd7e0500, 0xfc7e0600, 0xfb7d0800, 0xfb7c0900,
  82         0xfa7b0b00, 0xfa7a0dff, 0xf9790fff, 0xf97711ff,
  83         0xf87613ff, 0xf87416fe, 0xf87218fe, 0xf8701afe,
  84         0xf76f1dfd, 0xf76d1ffd, 0xf76b21fd, 0xf76824fd,
  85         0xf76627fc, 0xf76429fc, 0xf7612cfc, 0xf75f2ffb,
  86         0xf75d31fb, 0xf75a34fb, 0xf75837fa, 0xf7553afa,
  87         0xf8523cfa, 0xf8503ff9, 0xf84d42f9, 0xf84a45f9,
  88         0xf84848f8
  89 };
  90
  91 static void meson_vpp_write_vd_scaling_filter_coefs(struct meson_drm *priv,
  92                                                     const unsigned int *coefs,
  93                                                     bool is_horizontal)
  94 {
  95         int i;
  96
  97         writel_relaxed(is_horizontal ? BIT(8) : 0,
  98                         priv->io_base + _REG(VPP_SCALE_COEF_IDX));
  99         for (i = 0; i < 33; i++)
 100                 writel_relaxed(coefs[i],
 101                                 priv->io_base + _REG(VPP_SCALE_COEF));
 102 }
 103
 104 void meson_vpp_init(struct meson_drm *priv)
 105 {
 106         /* set dummy data default YUV black */
 107         if (meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
 108                 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1));
 109         else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu")) {
 110                 writel_bits_relaxed(0xff << 16, 0xff << 16,
 111                                     priv->io_base + _REG(VIU_MISC_CTRL1));
 112                 writel_relaxed(0x20000, priv->io_base + _REG(VPP_DOLBY_CTRL));
 113                 writel_relaxed(0x1020080,
 114                                 priv->io_base + _REG(VPP_DUMMY_DATA1));
 115         } else if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
 116                 writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL));
 117
 118         /* Initialize vpu fifo control registers */
 119         if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu"))
 120                 writel_relaxed(0xfff << 20 | 0x1000,
 121                                priv->io_base + _REG(VPP_OFIFO_SIZE));
 122         else
 123                 writel_relaxed(readl_relaxed(priv->io_base + _REG(VPP_OFIFO_SIZE)) |
 124                                 0x77f, priv->io_base + _REG(VPP_OFIFO_SIZE));
 125         writel_relaxed(0x08080808, priv->io_base + _REG(VPP_HOLD_LINES));
 126
 127         if (!meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) {
 128                 /* Turn off preblend */
 129                 writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0,
 130                                     priv->io_base + _REG(VPP_MISC));
 131
 132                 /* Turn off POSTBLEND */
 133                 writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
 134                                     priv->io_base + _REG(VPP_MISC));
 135
 136                 /* Force all planes off */
 137                 writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND |
 138                                     VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND |
 139                                     VPP_VD1_PREBLEND | VPP_VD2_PREBLEND, 0,
 140                                     priv->io_base + _REG(VPP_MISC));
 141
 142                 /* Setup default VD settings */
 143                 writel_relaxed(4096,
 144                                 priv->io_base + _REG(VPP_PREBLEND_VD1_H_START_END));
 145                 writel_relaxed(4096,
 146                                 priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
 147         }
 148
 149         /* Disable Scalers */
 150         writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
 151         writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
 152         writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
 153         writel_relaxed(4 | (4 << 8) | BIT(15),
 154                        priv->io_base + _REG(VPP_SC_MISC));
 155
 156         writel_relaxed(1, priv->io_base + _REG(VPP_VADJ_CTRL));
 157
 158         /* Write in the proper filter coefficients. */
 159         meson_vpp_write_scaling_filter_coefs(priv,
 160                                 vpp_filter_coefs_4point_bspline, false);
 161         meson_vpp_write_scaling_filter_coefs(priv,
 162                                 vpp_filter_coefs_4point_bspline, true);
 163
 164         /* Write the VD proper filter coefficients. */
 165         meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic,
 166                                                 false);
 167         meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic,
 168                                                 true);
 169 }