3ee4d4a4ecbae1e59c1fb5e0dfb873b24bf4497c
[linux-2.6-block.git] / drivers / gpu / drm / meson / meson_drv.c
1 /*
2  * Copyright (C) 2016 BayLibre, SAS
3  * Author: Neil Armstrong <narmstrong@baylibre.com>
4  * Copyright (C) 2014 Endless Mobile
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of the
9  * License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but
12  * WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, see <http://www.gnu.org/licenses/>.
18  *
19  * Written by:
20  *     Jasper St. Pierre <jstpierre@mecheye.net>
21  */
22
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/mutex.h>
26 #include <linux/platform_device.h>
27 #include <linux/component.h>
28 #include <linux/of_graph.h>
29
30 #include <drm/drmP.h>
31 #include <drm/drm_atomic.h>
32 #include <drm/drm_atomic_helper.h>
33 #include <drm/drm_flip_work.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_plane_helper.h>
36 #include <drm/drm_gem_cma_helper.h>
37 #include <drm/drm_gem_framebuffer_helper.h>
38 #include <drm/drm_fb_cma_helper.h>
39 #include <drm/drm_rect.h>
40 #include <drm/drm_fb_helper.h>
41
42 #include "meson_drv.h"
43 #include "meson_plane.h"
44 #include "meson_overlay.h"
45 #include "meson_crtc.h"
46 #include "meson_venc_cvbs.h"
47
48 #include "meson_vpp.h"
49 #include "meson_viu.h"
50 #include "meson_venc.h"
51 #include "meson_canvas.h"
52 #include "meson_registers.h"
53
54 #define DRIVER_NAME "meson"
55 #define DRIVER_DESC "Amlogic Meson DRM driver"
56
57 /**
58  * DOC: Video Processing Unit
59  *
60  * VPU Handles the Global Video Processing, it includes management of the
61  * clocks gates, blocks reset lines and power domains.
62  *
63  * What is missing :
64  *
65  * - Full reset of entire video processing HW blocks
66  * - Scaling and setup of the VPU clock
67  * - Bus clock gates
68  * - Powering up video processing HW blocks
69  * - Powering Up HDMI controller and PHY
70  */
71
72 static const struct drm_mode_config_funcs meson_mode_config_funcs = {
73         .atomic_check        = drm_atomic_helper_check,
74         .atomic_commit       = drm_atomic_helper_commit,
75         .fb_create           = drm_gem_fb_create,
76 };
77
78 static irqreturn_t meson_irq(int irq, void *arg)
79 {
80         struct drm_device *dev = arg;
81         struct meson_drm *priv = dev->dev_private;
82
83         (void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG));
84
85         meson_crtc_irq(priv);
86
87         return IRQ_HANDLED;
88 }
89
90 DEFINE_DRM_GEM_CMA_FOPS(fops);
91
92 static struct drm_driver meson_driver = {
93         .driver_features        = DRIVER_HAVE_IRQ | DRIVER_GEM |
94                                   DRIVER_MODESET | DRIVER_PRIME |
95                                   DRIVER_ATOMIC,
96
97         /* IRQ */
98         .irq_handler            = meson_irq,
99
100         /* PRIME Ops */
101         .prime_handle_to_fd     = drm_gem_prime_handle_to_fd,
102         .prime_fd_to_handle     = drm_gem_prime_fd_to_handle,
103         .gem_prime_import       = drm_gem_prime_import,
104         .gem_prime_export       = drm_gem_prime_export,
105         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
106         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
107         .gem_prime_vmap         = drm_gem_cma_prime_vmap,
108         .gem_prime_vunmap       = drm_gem_cma_prime_vunmap,
109         .gem_prime_mmap         = drm_gem_cma_prime_mmap,
110
111         /* GEM Ops */
112         .dumb_create            = drm_gem_cma_dumb_create,
113         .gem_free_object_unlocked = drm_gem_cma_free_object,
114         .gem_vm_ops             = &drm_gem_cma_vm_ops,
115
116         /* Misc */
117         .fops                   = &fops,
118         .name                   = DRIVER_NAME,
119         .desc                   = DRIVER_DESC,
120         .date                   = "20161109",
121         .major                  = 1,
122         .minor                  = 0,
123 };
124
125 static bool meson_vpu_has_available_connectors(struct device *dev)
126 {
127         struct device_node *ep, *remote;
128
129         /* Parses each endpoint and check if remote exists */
130         for_each_endpoint_of_node(dev->of_node, ep) {
131                 /* If the endpoint node exists, consider it enabled */
132                 remote = of_graph_get_remote_port(ep);
133                 if (remote)
134                         return true;
135         }
136
137         return false;
138 }
139
140 static struct regmap_config meson_regmap_config = {
141         .reg_bits       = 32,
142         .val_bits       = 32,
143         .reg_stride     = 4,
144         .max_register   = 0x1000,
145 };
146
147 static void meson_vpu_init(struct meson_drm *priv)
148 {
149         writel_relaxed(0x210000, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
150         writel_relaxed(0x10000, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
151         writel_relaxed(0x900000, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
152         writel_relaxed(0x20000, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
153 }
154
155 static int meson_drv_bind_master(struct device *dev, bool has_components)
156 {
157         struct platform_device *pdev = to_platform_device(dev);
158         struct meson_drm *priv;
159         struct drm_device *drm;
160         struct resource *res;
161         void __iomem *regs;
162         int ret;
163
164         /* Checks if an output connector is available */
165         if (!meson_vpu_has_available_connectors(dev)) {
166                 dev_err(dev, "No output connector available\n");
167                 return -ENODEV;
168         }
169
170         drm = drm_dev_alloc(&meson_driver, dev);
171         if (IS_ERR(drm))
172                 return PTR_ERR(drm);
173
174         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
175         if (!priv) {
176                 ret = -ENOMEM;
177                 goto free_drm;
178         }
179         drm->dev_private = priv;
180         priv->drm = drm;
181         priv->dev = dev;
182
183         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpu");
184         regs = devm_ioremap_resource(dev, res);
185         if (IS_ERR(regs)) {
186                 ret = PTR_ERR(regs);
187                 goto free_drm;
188         }
189
190         priv->io_base = regs;
191
192         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi");
193         if (!res) {
194                 ret = -EINVAL;
195                 goto free_drm;
196         }
197         /* Simply ioremap since it may be a shared register zone */
198         regs = devm_ioremap(dev, res->start, resource_size(res));
199         if (!regs) {
200                 ret = -EADDRNOTAVAIL;
201                 goto free_drm;
202         }
203
204         priv->hhi = devm_regmap_init_mmio(dev, regs,
205                                           &meson_regmap_config);
206         if (IS_ERR(priv->hhi)) {
207                 dev_err(&pdev->dev, "Couldn't create the HHI regmap\n");
208                 ret = PTR_ERR(priv->hhi);
209                 goto free_drm;
210         }
211
212         priv->canvas = meson_canvas_get(dev);
213         if (!IS_ERR(priv->canvas)) {
214                 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
215                 if (ret)
216                         goto free_drm;
217                 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
218                 if (ret) {
219                         meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
220                         goto free_drm;
221                 }
222                 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);
223                 if (ret) {
224                         meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
225                         meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
226                         goto free_drm;
227                 }
228                 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);
229                 if (ret) {
230                         meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
231                         meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
232                         meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
233                         goto free_drm;
234                 }
235         } else {
236                 priv->canvas = NULL;
237
238                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dmc");
239                 if (!res) {
240                         ret = -EINVAL;
241                         goto free_drm;
242                 }
243                 /* Simply ioremap since it may be a shared register zone */
244                 regs = devm_ioremap(dev, res->start, resource_size(res));
245                 if (!regs) {
246                         ret = -EADDRNOTAVAIL;
247                         goto free_drm;
248                 }
249
250                 priv->dmc = devm_regmap_init_mmio(dev, regs,
251                                                   &meson_regmap_config);
252                 if (IS_ERR(priv->dmc)) {
253                         dev_err(&pdev->dev, "Couldn't create the DMC regmap\n");
254                         ret = PTR_ERR(priv->dmc);
255                         goto free_drm;
256                 }
257         }
258
259         priv->vsync_irq = platform_get_irq(pdev, 0);
260
261         ret = drm_vblank_init(drm, 1);
262         if (ret)
263                 goto free_drm;
264
265         drm_mode_config_init(drm);
266         drm->mode_config.max_width = 3840;
267         drm->mode_config.max_height = 2160;
268         drm->mode_config.funcs = &meson_mode_config_funcs;
269
270         /* Hardware Initialization */
271
272         meson_vpu_init(priv);
273         meson_venc_init(priv);
274         meson_vpp_init(priv);
275         meson_viu_init(priv);
276
277         /* Encoder Initialization */
278
279         ret = meson_venc_cvbs_create(priv);
280         if (ret)
281                 goto free_drm;
282
283         if (has_components) {
284                 ret = component_bind_all(drm->dev, drm);
285                 if (ret) {
286                         dev_err(drm->dev, "Couldn't bind all components\n");
287                         goto free_drm;
288                 }
289         }
290
291         ret = meson_plane_create(priv);
292         if (ret)
293                 goto free_drm;
294
295         ret = meson_overlay_create(priv);
296         if (ret)
297                 goto free_drm;
298
299         ret = meson_crtc_create(priv);
300         if (ret)
301                 goto free_drm;
302
303         ret = drm_irq_install(drm, priv->vsync_irq);
304         if (ret)
305                 goto free_drm;
306
307         drm_mode_config_reset(drm);
308
309         drm_kms_helper_poll_init(drm);
310
311         platform_set_drvdata(pdev, priv);
312
313         ret = drm_dev_register(drm, 0);
314         if (ret)
315                 goto free_drm;
316
317         drm_fbdev_generic_setup(drm, 32);
318
319         return 0;
320
321 free_drm:
322         drm_dev_put(drm);
323
324         return ret;
325 }
326
327 static int meson_drv_bind(struct device *dev)
328 {
329         return meson_drv_bind_master(dev, true);
330 }
331
332 static void meson_drv_unbind(struct device *dev)
333 {
334         struct drm_device *drm = dev_get_drvdata(dev);
335         struct meson_drm *priv = drm->dev_private;
336
337         if (priv->canvas) {
338                 meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
339                 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
340                 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
341                 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);
342         }
343
344         drm_dev_unregister(drm);
345         drm_kms_helper_poll_fini(drm);
346         drm_mode_config_cleanup(drm);
347         drm_dev_put(drm);
348
349 }
350
351 static const struct component_master_ops meson_drv_master_ops = {
352         .bind   = meson_drv_bind,
353         .unbind = meson_drv_unbind,
354 };
355
356 static int compare_of(struct device *dev, void *data)
357 {
358         DRM_DEBUG_DRIVER("Comparing of node %pOF with %pOF\n",
359                          dev->of_node, data);
360
361         return dev->of_node == data;
362 }
363
364 /* Possible connectors nodes to ignore */
365 static const struct of_device_id connectors_match[] = {
366         { .compatible = "composite-video-connector" },
367         { .compatible = "svideo-connector" },
368         { .compatible = "hdmi-connector" },
369         { .compatible = "dvi-connector" },
370         {}
371 };
372
373 static int meson_probe_remote(struct platform_device *pdev,
374                               struct component_match **match,
375                               struct device_node *parent,
376                               struct device_node *remote)
377 {
378         struct device_node *ep, *remote_node;
379         int count = 1;
380
381         /* If node is a connector, return and do not add to match table */
382         if (of_match_node(connectors_match, remote))
383                 return 1;
384
385         component_match_add(&pdev->dev, match, compare_of, remote);
386
387         for_each_endpoint_of_node(remote, ep) {
388                 remote_node = of_graph_get_remote_port_parent(ep);
389                 if (!remote_node ||
390                     remote_node == parent || /* Ignore parent endpoint */
391                     !of_device_is_available(remote_node))
392                         continue;
393
394                 count += meson_probe_remote(pdev, match, remote, remote_node);
395
396                 of_node_put(remote_node);
397         }
398
399         return count;
400 }
401
402 static int meson_drv_probe(struct platform_device *pdev)
403 {
404         struct component_match *match = NULL;
405         struct device_node *np = pdev->dev.of_node;
406         struct device_node *ep, *remote;
407         int count = 0;
408
409         for_each_endpoint_of_node(np, ep) {
410                 remote = of_graph_get_remote_port_parent(ep);
411                 if (!remote || !of_device_is_available(remote))
412                         continue;
413
414                 count += meson_probe_remote(pdev, &match, np, remote);
415         }
416
417         if (count && !match)
418                 return meson_drv_bind_master(&pdev->dev, false);
419
420         /* If some endpoints were found, initialize the nodes */
421         if (count) {
422                 dev_info(&pdev->dev, "Queued %d outputs on vpu\n", count);
423
424                 return component_master_add_with_match(&pdev->dev,
425                                                        &meson_drv_master_ops,
426                                                        match);
427         }
428
429         /* If no output endpoints were available, simply bail out */
430         return 0;
431 };
432
433 static const struct of_device_id dt_match[] = {
434         { .compatible = "amlogic,meson-gxbb-vpu" },
435         { .compatible = "amlogic,meson-gxl-vpu" },
436         { .compatible = "amlogic,meson-gxm-vpu" },
437         {}
438 };
439 MODULE_DEVICE_TABLE(of, dt_match);
440
441 static struct platform_driver meson_drm_platform_driver = {
442         .probe      = meson_drv_probe,
443         .driver     = {
444                 .name   = "meson-drm",
445                 .of_match_table = dt_match,
446         },
447 };
448
449 module_platform_driver(meson_drm_platform_driver);
450
451 MODULE_AUTHOR("Jasper St. Pierre <jstpierre@mecheye.net>");
452 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
453 MODULE_DESCRIPTION(DRIVER_DESC);
454 MODULE_LICENSE("GPL");