drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 static bool
  43 format_is_yuv(uint32_t format)
  44 {
  45         switch (format) {
  46         case DRM_FORMAT_YUYV:
  47         case DRM_FORMAT_UYVY:
  48         case DRM_FORMAT_VYUY:
  49         case DRM_FORMAT_YVYU:
  50                 return true;
  51         default:
  52                 return false;
  53         }
  54 }
  55
  56 static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  57                               int usecs)
  58 {
  59         /* paranoia */
  60         if (!adjusted_mode->crtc_htotal)
  61                 return 1;
  62
  63         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  64                             1000 * adjusted_mode->crtc_htotal);
  65 }
  66
  67 /**
  68  * intel_pipe_update_start() - start update of a set of display registers
  69  * @crtc: the crtc of which the registers are going to be updated
  70  * @start_vbl_count: vblank counter return pointer used for error checking
  71  *
  72  * Mark the start of an update to pipe registers that should be updated
  73  * atomically regarding vblank. If the next vblank will happens within
  74  * the next 100 us, this function waits until the vblank passes.
  75  *
  76  * After a successful call to this function, interrupts will be disabled
  77  * until a subsequent call to intel_pipe_update_end(). That is done to
  78  * avoid random delays. The value written to @start_vbl_count should be
  79  * supplied to intel_pipe_update_end() for error checking.
  80  */
  81 void intel_pipe_update_start(struct intel_crtc *crtc)
  82 {
  83         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  84         long timeout = msecs_to_jiffies_timeout(1);
  85         int scanline, min, max, vblank_start;
  86         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  87         DEFINE_WAIT(wait);
  88
  89         vblank_start = adjusted_mode->crtc_vblank_start;
  90         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  91                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  92
  93         /* FIXME needs to be calibrated sensibly */
  94         min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
  95         max = vblank_start - 1;
  96
  97         local_irq_disable();
  98
  99         if (min <= 0 || max <= 0)
 100                 return;
 101
 102         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 103                 return;
 104
 105         crtc->debug.min_vbl = min;
 106         crtc->debug.max_vbl = max;
 107         trace_i915_pipe_update_start(crtc);
 108
 109         for (;;) {
 110                 /*
 111                  * prepare_to_wait() has a memory barrier, which guarantees
 112                  * other CPUs can see the task state update by the time we
 113                  * read the scanline.
 114                  */
 115                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 116
 117                 scanline = intel_get_crtc_scanline(crtc);
 118                 if (scanline < min || scanline > max)
 119                         break;
 120
 121                 if (timeout <= 0) {
 122                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 123                                   pipe_name(crtc->pipe));
 124                         break;
 125                 }
 126
 127                 local_irq_enable();
 128
 129                 timeout = schedule_timeout(timeout);
 130
 131                 local_irq_disable();
 132         }
 133
 134         finish_wait(wq, &wait);
 135
 136         drm_crtc_vblank_put(&crtc->base);
 137
 138         crtc->debug.scanline_start = scanline;
 139         crtc->debug.start_vbl_time = ktime_get();
 140         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 141
 142         trace_i915_pipe_update_vblank_evaded(crtc);
 143 }
 144
 145 /**
 146  * intel_pipe_update_end() - end update of a set of display registers
 147  * @crtc: the crtc of which the registers were updated
 148  * @start_vbl_count: start vblank counter (used for error checking)
 149  *
 150  * Mark the end of an update started with intel_pipe_update_start(). This
 151  * re-enables interrupts and verifies the update was actually completed
 152  * before a vblank using the value of @start_vbl_count.
 153  */
 154 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work)
 155 {
 156         enum pipe pipe = crtc->pipe;
 157         int scanline_end = intel_get_crtc_scanline(crtc);
 158         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 159         ktime_t end_vbl_time = ktime_get();
 160
 161         if (work) {
 162                 work->flip_queued_vblank = end_vbl_count;
 163                 smp_mb__before_atomic();
 164                 atomic_set(&work->pending, 1);
 165         }
 166
 167         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 168
 169         local_irq_enable();
 170
 171         if (crtc->debug.start_vbl_count &&
 172             crtc->debug.start_vbl_count != end_vbl_count) {
 173                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 174                           pipe_name(pipe), crtc->debug.start_vbl_count,
 175                           end_vbl_count,
 176                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 177                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 178                           crtc->debug.scanline_start, scanline_end);
 179         }
 180 }
 181
 182 static void
 183 skl_update_plane(struct drm_plane *drm_plane,
 184                  const struct intel_crtc_state *crtc_state,
 185                  const struct intel_plane_state *plane_state)
 186 {
 187         struct drm_device *dev = drm_plane->dev;
 188         struct drm_i915_private *dev_priv = dev->dev_private;
 189         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 190         struct drm_framebuffer *fb = plane_state->base.fb;
 191         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 192         const int pipe = intel_plane->pipe;
 193         const int plane = intel_plane->plane + 1;
 194         u32 plane_ctl, stride_div, stride;
 195         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 196         u32 surf_addr;
 197         u32 tile_height, plane_offset, plane_size;
 198         unsigned int rotation = plane_state->base.rotation;
 199         int x_offset, y_offset;
 200         int crtc_x = plane_state->dst.x1;
 201         int crtc_y = plane_state->dst.y1;
 202         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 203         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 204         uint32_t x = plane_state->src.x1 >> 16;
 205         uint32_t y = plane_state->src.y1 >> 16;
 206         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 207         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 208
 209         plane_ctl = PLANE_CTL_ENABLE |
 210                 PLANE_CTL_PIPE_GAMMA_ENABLE |
 211                 PLANE_CTL_PIPE_CSC_ENABLE;
 212
 213         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
 214         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
 215
 216         plane_ctl |= skl_plane_ctl_rotation(rotation);
 217
 218         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
 219                                                fb->pixel_format);
 220
 221         /* Sizes are 0 based */
 222         src_w--;
 223         src_h--;
 224         crtc_w--;
 225         crtc_h--;
 226
 227         if (key->flags) {
 228                 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
 229                 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
 230                 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
 231         }
 232
 233         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 234                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 235         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 236                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 237
 238         surf_addr = intel_plane_obj_offset(intel_plane, obj, 0);
 239
 240         if (intel_rotation_90_or_270(rotation)) {
 241                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 242
 243                 /* stride: Surface height in tiles */
 244                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
 245                 stride = DIV_ROUND_UP(fb->height, tile_height);
 246                 plane_size = (src_w << 16) | src_h;
 247                 x_offset = stride * tile_height - y - (src_h + 1);
 248                 y_offset = x;
 249         } else {
 250                 stride = fb->pitches[0] / stride_div;
 251                 plane_size = (src_h << 16) | src_w;
 252                 x_offset = x;
 253                 y_offset = y;
 254         }
 255         plane_offset = y_offset << 16 | x_offset;
 256
 257         I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
 258         I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
 259         I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
 260
 261         /* program plane scaler */
 262         if (plane_state->scaler_id >= 0) {
 263                 int scaler_id = plane_state->scaler_id;
 264                 const struct intel_scaler *scaler;
 265
 266                 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
 267                         PS_PLANE_SEL(plane));
 268
 269                 scaler = &crtc_state->scaler_state.scalers[scaler_id];
 270
 271                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id),
 272                            PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode);
 273                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 274                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 275                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
 276                         ((crtc_w + 1) << 16)|(crtc_h + 1));
 277
 278                 I915_WRITE(PLANE_POS(pipe, plane), 0);
 279         } else {
 280                 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
 281         }
 282
 283         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
 284         I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
 285         POSTING_READ(PLANE_SURF(pipe, plane));
 286 }
 287
 288 static void
 289 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 290 {
 291         struct drm_device *dev = dplane->dev;
 292         struct drm_i915_private *dev_priv = dev->dev_private;
 293         struct intel_plane *intel_plane = to_intel_plane(dplane);
 294         const int pipe = intel_plane->pipe;
 295         const int plane = intel_plane->plane + 1;
 296
 297         I915_WRITE(PLANE_CTL(pipe, plane), 0);
 298
 299         I915_WRITE(PLANE_SURF(pipe, plane), 0);
 300         POSTING_READ(PLANE_SURF(pipe, plane));
 301 }
 302
 303 static void
 304 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 305 {
 306         struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
 307         int plane = intel_plane->plane;
 308
 309         /* Seems RGB data bypasses the CSC always */
 310         if (!format_is_yuv(format))
 311                 return;
 312
 313         /*
 314          * BT.601 limited range YCbCr -> full range RGB
 315          *
 316          * |r|   | 6537 4769     0|   |cr  |
 317          * |g| = |-3330 4769 -1605| x |y-64|
 318          * |b|   |    0 4769  8263|   |cb  |
 319          *
 320          * Cb and Cr apparently come in as signed already, so no
 321          * need for any offset. For Y we need to remove the offset.
 322          */
 323         I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 324         I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 325         I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 326
 327         I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
 328         I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
 329         I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
 330         I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
 331         I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
 332
 333         I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 334         I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 335         I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 336
 337         I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 338         I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 339         I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 340 }
 341
 342 static void
 343 vlv_update_plane(struct drm_plane *dplane,
 344                  const struct intel_crtc_state *crtc_state,
 345                  const struct intel_plane_state *plane_state)
 346 {
 347         struct drm_device *dev = dplane->dev;
 348         struct drm_i915_private *dev_priv = dev->dev_private;
 349         struct intel_plane *intel_plane = to_intel_plane(dplane);
 350         struct drm_framebuffer *fb = plane_state->base.fb;
 351         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 352         int pipe = intel_plane->pipe;
 353         int plane = intel_plane->plane;
 354         u32 sprctl;
 355         u32 sprsurf_offset, linear_offset;
 356         unsigned int rotation = dplane->state->rotation;
 357         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 358         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 359         int crtc_x = plane_state->dst.x1;
 360         int crtc_y = plane_state->dst.y1;
 361         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 362         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 363         uint32_t x = plane_state->src.x1 >> 16;
 364         uint32_t y = plane_state->src.y1 >> 16;
 365         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 366         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 367
 368         sprctl = SP_ENABLE;
 369
 370         switch (fb->pixel_format) {
 371         case DRM_FORMAT_YUYV:
 372                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 373                 break;
 374         case DRM_FORMAT_YVYU:
 375                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 376                 break;
 377         case DRM_FORMAT_UYVY:
 378                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 379                 break;
 380         case DRM_FORMAT_VYUY:
 381                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 382                 break;
 383         case DRM_FORMAT_RGB565:
 384                 sprctl |= SP_FORMAT_BGR565;
 385                 break;
 386         case DRM_FORMAT_XRGB8888:
 387                 sprctl |= SP_FORMAT_BGRX8888;
 388                 break;
 389         case DRM_FORMAT_ARGB8888:
 390                 sprctl |= SP_FORMAT_BGRA8888;
 391                 break;
 392         case DRM_FORMAT_XBGR2101010:
 393                 sprctl |= SP_FORMAT_RGBX1010102;
 394                 break;
 395         case DRM_FORMAT_ABGR2101010:
 396                 sprctl |= SP_FORMAT_RGBA1010102;
 397                 break;
 398         case DRM_FORMAT_XBGR8888:
 399                 sprctl |= SP_FORMAT_RGBX8888;
 400                 break;
 401         case DRM_FORMAT_ABGR8888:
 402                 sprctl |= SP_FORMAT_RGBA8888;
 403                 break;
 404         default:
 405                 /*
 406                  * If we get here one of the upper layers failed to filter
 407                  * out the unsupported plane formats
 408                  */
 409                 BUG();
 410                 break;
 411         }
 412
 413         /*
 414          * Enable gamma to match primary/cursor plane behaviour.
 415          * FIXME should be user controllable via propertiesa.
 416          */
 417         sprctl |= SP_GAMMA_ENABLE;
 418
 419         if (obj->tiling_mode != I915_TILING_NONE)
 420                 sprctl |= SP_TILED;
 421
 422         /* Sizes are 0 based */
 423         src_w--;
 424         src_h--;
 425         crtc_w--;
 426         crtc_h--;
 427
 428         linear_offset = y * fb->pitches[0] + x * cpp;
 429         sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0,
 430                                                    fb->pitches[0], rotation);
 431         linear_offset -= sprsurf_offset;
 432
 433         if (rotation == BIT(DRM_ROTATE_180)) {
 434                 sprctl |= SP_ROTATE_180;
 435
 436                 x += src_w;
 437                 y += src_h;
 438                 linear_offset += src_h * fb->pitches[0] + src_w * cpp;
 439         }
 440
 441         if (key->flags) {
 442                 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
 443                 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
 444                 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
 445         }
 446
 447         if (key->flags & I915_SET_COLORKEY_SOURCE)
 448                 sprctl |= SP_SOURCE_KEY;
 449
 450         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
 451                 chv_update_csc(intel_plane, fb->pixel_format);
 452
 453         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 454         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 455
 456         if (obj->tiling_mode != I915_TILING_NONE)
 457                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 458         else
 459                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
 460
 461         I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
 462
 463         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
 464         I915_WRITE(SPCNTR(pipe, plane), sprctl);
 465         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
 466                    sprsurf_offset);
 467         POSTING_READ(SPSURF(pipe, plane));
 468 }
 469
 470 static void
 471 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 472 {
 473         struct drm_device *dev = dplane->dev;
 474         struct drm_i915_private *dev_priv = dev->dev_private;
 475         struct intel_plane *intel_plane = to_intel_plane(dplane);
 476         int pipe = intel_plane->pipe;
 477         int plane = intel_plane->plane;
 478
 479         I915_WRITE(SPCNTR(pipe, plane), 0);
 480
 481         I915_WRITE(SPSURF(pipe, plane), 0);
 482         POSTING_READ(SPSURF(pipe, plane));
 483 }
 484
 485 static void
 486 ivb_update_plane(struct drm_plane *plane,
 487                  const struct intel_crtc_state *crtc_state,
 488                  const struct intel_plane_state *plane_state)
 489 {
 490         struct drm_device *dev = plane->dev;
 491         struct drm_i915_private *dev_priv = dev->dev_private;
 492         struct intel_plane *intel_plane = to_intel_plane(plane);
 493         struct drm_framebuffer *fb = plane_state->base.fb;
 494         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 495         enum pipe pipe = intel_plane->pipe;
 496         u32 sprctl, sprscale = 0;
 497         u32 sprsurf_offset, linear_offset;
 498         unsigned int rotation = plane_state->base.rotation;
 499         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 500         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 501         int crtc_x = plane_state->dst.x1;
 502         int crtc_y = plane_state->dst.y1;
 503         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 504         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 505         uint32_t x = plane_state->src.x1 >> 16;
 506         uint32_t y = plane_state->src.y1 >> 16;
 507         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 508         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 509
 510         sprctl = SPRITE_ENABLE;
 511
 512         switch (fb->pixel_format) {
 513         case DRM_FORMAT_XBGR8888:
 514                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 515                 break;
 516         case DRM_FORMAT_XRGB8888:
 517                 sprctl |= SPRITE_FORMAT_RGBX888;
 518                 break;
 519         case DRM_FORMAT_YUYV:
 520                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 521                 break;
 522         case DRM_FORMAT_YVYU:
 523                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 524                 break;
 525         case DRM_FORMAT_UYVY:
 526                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 527                 break;
 528         case DRM_FORMAT_VYUY:
 529                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 530                 break;
 531         default:
 532                 BUG();
 533         }
 534
 535         /*
 536          * Enable gamma to match primary/cursor plane behaviour.
 537          * FIXME should be user controllable via propertiesa.
 538          */
 539         sprctl |= SPRITE_GAMMA_ENABLE;
 540
 541         if (obj->tiling_mode != I915_TILING_NONE)
 542                 sprctl |= SPRITE_TILED;
 543
 544         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 545                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 546         else
 547                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 548
 549         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 550                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 551
 552         /* Sizes are 0 based */
 553         src_w--;
 554         src_h--;
 555         crtc_w--;
 556         crtc_h--;
 557
 558         if (crtc_w != src_w || crtc_h != src_h)
 559                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 560
 561         linear_offset = y * fb->pitches[0] + x * cpp;
 562         sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0,
 563                                                    fb->pitches[0], rotation);
 564         linear_offset -= sprsurf_offset;
 565
 566         if (rotation == BIT(DRM_ROTATE_180)) {
 567                 sprctl |= SPRITE_ROTATE_180;
 568
 569                 /* HSW and BDW does this automagically in hardware */
 570                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
 571                         x += src_w;
 572                         y += src_h;
 573                         linear_offset += src_h * fb->pitches[0] + src_w * cpp;
 574                 }
 575         }
 576
 577         if (key->flags) {
 578                 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
 579                 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
 580                 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
 581         }
 582
 583         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 584                 sprctl |= SPRITE_DEST_KEY;
 585         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 586                 sprctl |= SPRITE_SOURCE_KEY;
 587
 588         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 589         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 590
 591         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 592          * register */
 593         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 594                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 595         else if (obj->tiling_mode != I915_TILING_NONE)
 596                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 597         else
 598                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 599
 600         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 601         if (intel_plane->can_scale)
 602                 I915_WRITE(SPRSCALE(pipe), sprscale);
 603         I915_WRITE(SPRCTL(pipe), sprctl);
 604         I915_WRITE(SPRSURF(pipe),
 605                    i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
 606         POSTING_READ(SPRSURF(pipe));
 607 }
 608
 609 static void
 610 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 611 {
 612         struct drm_device *dev = plane->dev;
 613         struct drm_i915_private *dev_priv = dev->dev_private;
 614         struct intel_plane *intel_plane = to_intel_plane(plane);
 615         int pipe = intel_plane->pipe;
 616
 617         I915_WRITE(SPRCTL(pipe), 0);
 618         /* Can't leave the scaler enabled... */
 619         if (intel_plane->can_scale)
 620                 I915_WRITE(SPRSCALE(pipe), 0);
 621
 622         I915_WRITE(SPRSURF(pipe), 0);
 623         POSTING_READ(SPRSURF(pipe));
 624 }
 625
 626 static void
 627 ilk_update_plane(struct drm_plane *plane,
 628                  const struct intel_crtc_state *crtc_state,
 629                  const struct intel_plane_state *plane_state)
 630 {
 631         struct drm_device *dev = plane->dev;
 632         struct drm_i915_private *dev_priv = dev->dev_private;
 633         struct intel_plane *intel_plane = to_intel_plane(plane);
 634         struct drm_framebuffer *fb = plane_state->base.fb;
 635         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 636         int pipe = intel_plane->pipe;
 637         u32 dvscntr, dvsscale;
 638         u32 dvssurf_offset, linear_offset;
 639         unsigned int rotation = plane_state->base.rotation;
 640         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 641         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 642         int crtc_x = plane_state->dst.x1;
 643         int crtc_y = plane_state->dst.y1;
 644         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
 645         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
 646         uint32_t x = plane_state->src.x1 >> 16;
 647         uint32_t y = plane_state->src.y1 >> 16;
 648         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
 649         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
 650
 651         dvscntr = DVS_ENABLE;
 652
 653         switch (fb->pixel_format) {
 654         case DRM_FORMAT_XBGR8888:
 655                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 656                 break;
 657         case DRM_FORMAT_XRGB8888:
 658                 dvscntr |= DVS_FORMAT_RGBX888;
 659                 break;
 660         case DRM_FORMAT_YUYV:
 661                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 662                 break;
 663         case DRM_FORMAT_YVYU:
 664                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 665                 break;
 666         case DRM_FORMAT_UYVY:
 667                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 668                 break;
 669         case DRM_FORMAT_VYUY:
 670                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 671                 break;
 672         default:
 673                 BUG();
 674         }
 675
 676         /*
 677          * Enable gamma to match primary/cursor plane behaviour.
 678          * FIXME should be user controllable via propertiesa.
 679          */
 680         dvscntr |= DVS_GAMMA_ENABLE;
 681
 682         if (obj->tiling_mode != I915_TILING_NONE)
 683                 dvscntr |= DVS_TILED;
 684
 685         if (IS_GEN6(dev))
 686                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 687
 688         /* Sizes are 0 based */
 689         src_w--;
 690         src_h--;
 691         crtc_w--;
 692         crtc_h--;
 693
 694         dvsscale = 0;
 695         if (crtc_w != src_w || crtc_h != src_h)
 696                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 697
 698         linear_offset = y * fb->pitches[0] + x * cpp;
 699         dvssurf_offset = intel_compute_tile_offset(&x, &y, fb, 0,
 700                                                    fb->pitches[0], rotation);
 701         linear_offset -= dvssurf_offset;
 702
 703         if (rotation == BIT(DRM_ROTATE_180)) {
 704                 dvscntr |= DVS_ROTATE_180;
 705
 706                 x += src_w;
 707                 y += src_h;
 708                 linear_offset += src_h * fb->pitches[0] + src_w * cpp;
 709         }
 710
 711         if (key->flags) {
 712                 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
 713                 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
 714                 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
 715         }
 716
 717         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 718                 dvscntr |= DVS_DEST_KEY;
 719         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 720                 dvscntr |= DVS_SOURCE_KEY;
 721
 722         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 723         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 724
 725         if (obj->tiling_mode != I915_TILING_NONE)
 726                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 727         else
 728                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 729
 730         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 731         I915_WRITE(DVSSCALE(pipe), dvsscale);
 732         I915_WRITE(DVSCNTR(pipe), dvscntr);
 733         I915_WRITE(DVSSURF(pipe),
 734                    i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
 735         POSTING_READ(DVSSURF(pipe));
 736 }
 737
 738 static void
 739 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 740 {
 741         struct drm_device *dev = plane->dev;
 742         struct drm_i915_private *dev_priv = dev->dev_private;
 743         struct intel_plane *intel_plane = to_intel_plane(plane);
 744         int pipe = intel_plane->pipe;
 745
 746         I915_WRITE(DVSCNTR(pipe), 0);
 747         /* Disable the scaler */
 748         I915_WRITE(DVSSCALE(pipe), 0);
 749
 750         I915_WRITE(DVSSURF(pipe), 0);
 751         POSTING_READ(DVSSURF(pipe));
 752 }
 753
 754 static int
 755 intel_check_sprite_plane(struct drm_plane *plane,
 756                          struct intel_crtc_state *crtc_state,
 757                          struct intel_plane_state *state)
 758 {
 759         struct drm_device *dev = plane->dev;
 760         struct drm_crtc *crtc = state->base.crtc;
 761         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 762         struct intel_plane *intel_plane = to_intel_plane(plane);
 763         struct drm_framebuffer *fb = state->base.fb;
 764         int crtc_x, crtc_y;
 765         unsigned int crtc_w, crtc_h;
 766         uint32_t src_x, src_y, src_w, src_h;
 767         struct drm_rect *src = &state->src;
 768         struct drm_rect *dst = &state->dst;
 769         const struct drm_rect *clip = &state->clip;
 770         int hscale, vscale;
 771         int max_scale, min_scale;
 772         bool can_scale;
 773
 774         if (!fb) {
 775                 state->visible = false;
 776                 return 0;
 777         }
 778
 779         /* Don't modify another pipe's plane */
 780         if (intel_plane->pipe != intel_crtc->pipe) {
 781                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 782                 return -EINVAL;
 783         }
 784
 785         /* FIXME check all gen limits */
 786         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 787                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 788                 return -EINVAL;
 789         }
 790
 791         /* setup can_scale, min_scale, max_scale */
 792         if (INTEL_INFO(dev)->gen >= 9) {
 793                 /* use scaler when colorkey is not required */
 794                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 795                         can_scale = 1;
 796                         min_scale = 1;
 797                         max_scale = skl_max_scale(intel_crtc, crtc_state);
 798                 } else {
 799                         can_scale = 0;
 800                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 801                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 802                 }
 803         } else {
 804                 can_scale = intel_plane->can_scale;
 805                 max_scale = intel_plane->max_downscale << 16;
 806                 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
 807         }
 808
 809         /*
 810          * FIXME the following code does a bunch of fuzzy adjustments to the
 811          * coordinates and sizes. We probably need some way to decide whether
 812          * more strict checking should be done instead.
 813          */
 814         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 815                         state->base.rotation);
 816
 817         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 818         BUG_ON(hscale < 0);
 819
 820         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 821         BUG_ON(vscale < 0);
 822
 823         state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 824
 825         crtc_x = dst->x1;
 826         crtc_y = dst->y1;
 827         crtc_w = drm_rect_width(dst);
 828         crtc_h = drm_rect_height(dst);
 829
 830         if (state->visible) {
 831                 /* check again in case clipping clamped the results */
 832                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 833                 if (hscale < 0) {
 834                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 835                         drm_rect_debug_print("src: ", src, true);
 836                         drm_rect_debug_print("dst: ", dst, false);
 837
 838                         return hscale;
 839                 }
 840
 841                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 842                 if (vscale < 0) {
 843                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 844                         drm_rect_debug_print("src: ", src, true);
 845                         drm_rect_debug_print("dst: ", dst, false);
 846
 847                         return vscale;
 848                 }
 849
 850                 /* Make the source viewport size an exact multiple of the scaling factors. */
 851                 drm_rect_adjust_size(src,
 852                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 853                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 854
 855                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 856                                     state->base.rotation);
 857
 858                 /* sanity check to make sure the src viewport wasn't enlarged */
 859                 WARN_ON(src->x1 < (int) state->base.src_x ||
 860                         src->y1 < (int) state->base.src_y ||
 861                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 862                         src->y2 > (int) state->base.src_y + state->base.src_h);
 863
 864                 /*
 865                  * Hardware doesn't handle subpixel coordinates.
 866                  * Adjust to (macro)pixel boundary, but be careful not to
 867                  * increase the source viewport size, because that could
 868                  * push the downscaling factor out of bounds.
 869                  */
 870                 src_x = src->x1 >> 16;
 871                 src_w = drm_rect_width(src) >> 16;
 872                 src_y = src->y1 >> 16;
 873                 src_h = drm_rect_height(src) >> 16;
 874
 875                 if (format_is_yuv(fb->pixel_format)) {
 876                         src_x &= ~1;
 877                         src_w &= ~1;
 878
 879                         /*
 880                          * Must keep src and dst the
 881                          * same if we can't scale.
 882                          */
 883                         if (!can_scale)
 884                                 crtc_w &= ~1;
 885
 886                         if (crtc_w == 0)
 887                                 state->visible = false;
 888                 }
 889         }
 890
 891         /* Check size restrictions when scaling */
 892         if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
 893                 unsigned int width_bytes;
 894                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
 895
 896                 WARN_ON(!can_scale);
 897
 898                 /* FIXME interlacing min height is 6 */
 899
 900                 if (crtc_w < 3 || crtc_h < 3)
 901                         state->visible = false;
 902
 903                 if (src_w < 3 || src_h < 3)
 904                         state->visible = false;
 905
 906                 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
 907
 908                 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
 909                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 910                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 911                         return -EINVAL;
 912                 }
 913         }
 914
 915         if (state->visible) {
 916                 src->x1 = src_x << 16;
 917                 src->x2 = (src_x + src_w) << 16;
 918                 src->y1 = src_y << 16;
 919                 src->y2 = (src_y + src_h) << 16;
 920         }
 921
 922         dst->x1 = crtc_x;
 923         dst->x2 = crtc_x + crtc_w;
 924         dst->y1 = crtc_y;
 925         dst->y2 = crtc_y + crtc_h;
 926
 927         return 0;
 928 }
 929
 930 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 931                               struct drm_file *file_priv)
 932 {
 933         struct drm_intel_sprite_colorkey *set = data;
 934         struct drm_plane *plane;
 935         struct drm_plane_state *plane_state;
 936         struct drm_atomic_state *state;
 937         struct drm_modeset_acquire_ctx ctx;
 938         int ret = 0;
 939
 940         /* Make sure we don't try to enable both src & dest simultaneously */
 941         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 942                 return -EINVAL;
 943
 944         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 945             set->flags & I915_SET_COLORKEY_DESTINATION)
 946                 return -EINVAL;
 947
 948         plane = drm_plane_find(dev, set->plane_id);
 949         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
 950                 return -ENOENT;
 951
 952         drm_modeset_acquire_init(&ctx, 0);
 953
 954         state = drm_atomic_state_alloc(plane->dev);
 955         if (!state) {
 956                 ret = -ENOMEM;
 957                 goto out;
 958         }
 959         state->acquire_ctx = &ctx;
 960
 961         while (1) {
 962                 plane_state = drm_atomic_get_plane_state(state, plane);
 963                 ret = PTR_ERR_OR_ZERO(plane_state);
 964                 if (!ret) {
 965                         to_intel_plane_state(plane_state)->ckey = *set;
 966                         ret = drm_atomic_commit(state);
 967                 }
 968
 969                 if (ret != -EDEADLK)
 970                         break;
 971
 972                 drm_atomic_state_clear(state);
 973                 drm_modeset_backoff(&ctx);
 974         }
 975
 976         if (ret)
 977                 drm_atomic_state_free(state);
 978
 979 out:
 980         drm_modeset_drop_locks(&ctx);
 981         drm_modeset_acquire_fini(&ctx);
 982         return ret;
 983 }
 984
 985 static const uint32_t ilk_plane_formats[] = {
 986         DRM_FORMAT_XRGB8888,
 987         DRM_FORMAT_YUYV,
 988         DRM_FORMAT_YVYU,
 989         DRM_FORMAT_UYVY,
 990         DRM_FORMAT_VYUY,
 991 };
 992
 993 static const uint32_t snb_plane_formats[] = {
 994         DRM_FORMAT_XBGR8888,
 995         DRM_FORMAT_XRGB8888,
 996         DRM_FORMAT_YUYV,
 997         DRM_FORMAT_YVYU,
 998         DRM_FORMAT_UYVY,
 999         DRM_FORMAT_VYUY,
1000 };
1001
1002 static const uint32_t vlv_plane_formats[] = {
1003         DRM_FORMAT_RGB565,
1004         DRM_FORMAT_ABGR8888,
1005         DRM_FORMAT_ARGB8888,
1006         DRM_FORMAT_XBGR8888,
1007         DRM_FORMAT_XRGB8888,
1008         DRM_FORMAT_XBGR2101010,
1009         DRM_FORMAT_ABGR2101010,
1010         DRM_FORMAT_YUYV,
1011         DRM_FORMAT_YVYU,
1012         DRM_FORMAT_UYVY,
1013         DRM_FORMAT_VYUY,
1014 };
1015
1016 static uint32_t skl_plane_formats[] = {
1017         DRM_FORMAT_RGB565,
1018         DRM_FORMAT_ABGR8888,
1019         DRM_FORMAT_ARGB8888,
1020         DRM_FORMAT_XBGR8888,
1021         DRM_FORMAT_XRGB8888,
1022         DRM_FORMAT_YUYV,
1023         DRM_FORMAT_YVYU,
1024         DRM_FORMAT_UYVY,
1025         DRM_FORMAT_VYUY,
1026 };
1027
1028 int
1029 intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1030 {
1031         struct intel_plane *intel_plane = NULL;
1032         struct intel_plane_state *state = NULL;
1033         unsigned long possible_crtcs;
1034         const uint32_t *plane_formats;
1035         int num_plane_formats;
1036         int ret;
1037
1038         if (INTEL_INFO(dev)->gen < 5)
1039                 return -ENODEV;
1040
1041         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1042         if (!intel_plane) {
1043                 ret = -ENOMEM;
1044                 goto fail;
1045         }
1046
1047         state = intel_create_plane_state(&intel_plane->base);
1048         if (!state) {
1049                 ret = -ENOMEM;
1050                 goto fail;
1051         }
1052         intel_plane->base.state = &state->base;
1053
1054         switch (INTEL_INFO(dev)->gen) {
1055         case 5:
1056         case 6:
1057                 intel_plane->can_scale = true;
1058                 intel_plane->max_downscale = 16;
1059                 intel_plane->update_plane = ilk_update_plane;
1060                 intel_plane->disable_plane = ilk_disable_plane;
1061
1062                 if (IS_GEN6(dev)) {
1063                         plane_formats = snb_plane_formats;
1064                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1065                 } else {
1066                         plane_formats = ilk_plane_formats;
1067                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1068                 }
1069                 break;
1070
1071         case 7:
1072         case 8:
1073                 if (IS_IVYBRIDGE(dev)) {
1074                         intel_plane->can_scale = true;
1075                         intel_plane->max_downscale = 2;
1076                 } else {
1077                         intel_plane->can_scale = false;
1078                         intel_plane->max_downscale = 1;
1079                 }
1080
1081                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1082                         intel_plane->update_plane = vlv_update_plane;
1083                         intel_plane->disable_plane = vlv_disable_plane;
1084
1085                         plane_formats = vlv_plane_formats;
1086                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1087                 } else {
1088                         intel_plane->update_plane = ivb_update_plane;
1089                         intel_plane->disable_plane = ivb_disable_plane;
1090
1091                         plane_formats = snb_plane_formats;
1092                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1093                 }
1094                 break;
1095         case 9:
1096                 intel_plane->can_scale = true;
1097                 intel_plane->update_plane = skl_update_plane;
1098                 intel_plane->disable_plane = skl_disable_plane;
1099                 state->scaler_id = -1;
1100
1101                 plane_formats = skl_plane_formats;
1102                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1103                 break;
1104         default:
1105                 MISSING_CASE(INTEL_INFO(dev)->gen);
1106                 ret = -ENODEV;
1107                 goto fail;
1108         }
1109
1110         intel_plane->pipe = pipe;
1111         intel_plane->plane = plane;
1112         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1113         intel_plane->check_plane = intel_check_sprite_plane;
1114
1115         possible_crtcs = (1 << pipe);
1116
1117         if (INTEL_INFO(dev)->gen >= 9)
1118                 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1119                                                &intel_plane_funcs,
1120                                                plane_formats, num_plane_formats,
1121                                                DRM_PLANE_TYPE_OVERLAY,
1122                                                "plane %d%c", plane + 2, pipe_name(pipe));
1123         else
1124                 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1125                                                &intel_plane_funcs,
1126                                                plane_formats, num_plane_formats,
1127                                                DRM_PLANE_TYPE_OVERLAY,
1128                                                "sprite %c", sprite_name(pipe, plane));
1129         if (ret)
1130                 goto fail;
1131
1132         intel_create_rotation_property(dev, intel_plane);
1133
1134         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1135
1136         return 0;
1137
1138 fail:
1139         kfree(state);
1140         kfree(intel_plane);
1141
1142         return ret;
1143 }