drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define GEN9_ENABLE_DC5(dev) 0
  53 #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
  54
  55 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  56         for (i = 0;                                                     \
  57              i < (power_domains)->power_well_count &&                   \
  58                  ((power_well) = &(power_domains)->power_wells[i]);     \
  59              i++)                                                       \
  60                 if ((power_well)->domains & (domain_mask))
  61
  62 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  63         for (i = (power_domains)->power_well_count - 1;                  \
  64              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  65              i--)                                                        \
  66                 if ((power_well)->domains & (domain_mask))
  67
  68 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  69                                     int power_well_id);
  70
  71 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
  72                                     struct i915_power_well *power_well)
  73 {
  74         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
  75         power_well->ops->enable(dev_priv, power_well);
  76         power_well->hw_enabled = true;
  77 }
  78
  79 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
  80                                      struct i915_power_well *power_well)
  81 {
  82         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
  83         power_well->hw_enabled = false;
  84         power_well->ops->disable(dev_priv, power_well);
  85 }
  86
  87 /*
  88  * We should only use the power well if we explicitly asked the hardware to
  89  * enable it, so check if it's enabled and also check if we've requested it to
  90  * be enabled.
  91  */
  92 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
  93                                    struct i915_power_well *power_well)
  94 {
  95         return I915_READ(HSW_PWR_WELL_DRIVER) ==
  96                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
  97 }
  98
  99 /**
 100  * __intel_display_power_is_enabled - unlocked check for a power domain
 101  * @dev_priv: i915 device instance
 102  * @domain: power domain to check
 103  *
 104  * This is the unlocked version of intel_display_power_is_enabled() and should
 105  * only be used from error capture and recovery code where deadlocks are
 106  * possible.
 107  *
 108  * Returns:
 109  * True when the power domain is enabled, false otherwise.
 110  */
 111 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 112                                       enum intel_display_power_domain domain)
 113 {
 114         struct i915_power_domains *power_domains;
 115         struct i915_power_well *power_well;
 116         bool is_enabled;
 117         int i;
 118
 119         if (dev_priv->pm.suspended)
 120                 return false;
 121
 122         power_domains = &dev_priv->power_domains;
 123
 124         is_enabled = true;
 125
 126         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 127                 if (power_well->always_on)
 128                         continue;
 129
 130                 if (!power_well->hw_enabled) {
 131                         is_enabled = false;
 132                         break;
 133                 }
 134         }
 135
 136         return is_enabled;
 137 }
 138
 139 /**
 140  * intel_display_power_is_enabled - check for a power domain
 141  * @dev_priv: i915 device instance
 142  * @domain: power domain to check
 143  *
 144  * This function can be used to check the hw power domain state. It is mostly
 145  * used in hardware state readout functions. Everywhere else code should rely
 146  * upon explicit power domain reference counting to ensure that the hardware
 147  * block is powered up before accessing it.
 148  *
 149  * Callers must hold the relevant modesetting locks to ensure that concurrent
 150  * threads can't disable the power well while the caller tries to read a few
 151  * registers.
 152  *
 153  * Returns:
 154  * True when the power domain is enabled, false otherwise.
 155  */
 156 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 157                                     enum intel_display_power_domain domain)
 158 {
 159         struct i915_power_domains *power_domains;
 160         bool ret;
 161
 162         power_domains = &dev_priv->power_domains;
 163
 164         mutex_lock(&power_domains->lock);
 165         ret = __intel_display_power_is_enabled(dev_priv, domain);
 166         mutex_unlock(&power_domains->lock);
 167
 168         return ret;
 169 }
 170
 171 /**
 172  * intel_display_set_init_power - set the initial power domain state
 173  * @dev_priv: i915 device instance
 174  * @enable: whether to enable or disable the initial power domain state
 175  *
 176  * For simplicity our driver load/unload and system suspend/resume code assumes
 177  * that all power domains are always enabled. This functions controls the state
 178  * of this little hack. While the initial power domain state is enabled runtime
 179  * pm is effectively disabled.
 180  */
 181 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 182                                   bool enable)
 183 {
 184         if (dev_priv->power_domains.init_power_on == enable)
 185                 return;
 186
 187         if (enable)
 188                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 189         else
 190                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 191
 192         dev_priv->power_domains.init_power_on = enable;
 193 }
 194
 195 /*
 196  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 197  * when not needed anymore. We have 4 registers that can request the power well
 198  * to be enabled, and it will only be disabled if none of the registers is
 199  * requesting it to be enabled.
 200  */
 201 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 202 {
 203         struct drm_device *dev = dev_priv->dev;
 204
 205         /*
 206          * After we re-enable the power well, if we touch VGA register 0x3d5
 207          * we'll get unclaimed register interrupts. This stops after we write
 208          * anything to the VGA MSR register. The vgacon module uses this
 209          * register all the time, so if we unbind our driver and, as a
 210          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 211          * console_unlock(). So make here we touch the VGA MSR register, making
 212          * sure vgacon can keep working normally without triggering interrupts
 213          * and error messages.
 214          */
 215         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 216         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 217         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 218
 219         if (IS_BROADWELL(dev))
 220                 gen8_irq_power_well_post_enable(dev_priv,
 221                                                 1 << PIPE_C | 1 << PIPE_B);
 222 }
 223
 224 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 225                                        struct i915_power_well *power_well)
 226 {
 227         struct drm_device *dev = dev_priv->dev;
 228
 229         /*
 230          * After we re-enable the power well, if we touch VGA register 0x3d5
 231          * we'll get unclaimed register interrupts. This stops after we write
 232          * anything to the VGA MSR register. The vgacon module uses this
 233          * register all the time, so if we unbind our driver and, as a
 234          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 235          * console_unlock(). So make here we touch the VGA MSR register, making
 236          * sure vgacon can keep working normally without triggering interrupts
 237          * and error messages.
 238          */
 239         if (power_well->data == SKL_DISP_PW_2) {
 240                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 241                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 242                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 243
 244                 gen8_irq_power_well_post_enable(dev_priv,
 245                                                 1 << PIPE_C | 1 << PIPE_B);
 246         }
 247
 248         if (power_well->data == SKL_DISP_PW_1) {
 249                 intel_prepare_ddi(dev);
 250                 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
 251         }
 252 }
 253
 254 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 255                                struct i915_power_well *power_well, bool enable)
 256 {
 257         bool is_enabled, enable_requested;
 258         uint32_t tmp;
 259
 260         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 261         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 262         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 263
 264         if (enable) {
 265                 if (!enable_requested)
 266                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 267                                    HSW_PWR_WELL_ENABLE_REQUEST);
 268
 269                 if (!is_enabled) {
 270                         DRM_DEBUG_KMS("Enabling power well\n");
 271                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 272                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 273                                 DRM_ERROR("Timeout enabling power well\n");
 274                         hsw_power_well_post_enable(dev_priv);
 275                 }
 276
 277         } else {
 278                 if (enable_requested) {
 279                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 280                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 281                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 282                 }
 283         }
 284 }
 285
 286 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 287         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 288         BIT(POWER_DOMAIN_PIPE_B) |                      \
 289         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 290         BIT(POWER_DOMAIN_PIPE_C) |                      \
 291         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 292         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 293         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 294         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 295         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 296         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 297         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 298         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
 299         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
 300         BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) |          \
 301         BIT(POWER_DOMAIN_AUX_B) |                       \
 302         BIT(POWER_DOMAIN_AUX_C) |                       \
 303         BIT(POWER_DOMAIN_AUX_D) |                       \
 304         BIT(POWER_DOMAIN_AUDIO) |                       \
 305         BIT(POWER_DOMAIN_VGA) |                         \
 306         BIT(POWER_DOMAIN_INIT))
 307 #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 308         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 309         BIT(POWER_DOMAIN_PLLS) |                        \
 310         BIT(POWER_DOMAIN_PIPE_A) |                      \
 311         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 312         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 313         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 314         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 315         BIT(POWER_DOMAIN_AUX_A) |                       \
 316         BIT(POWER_DOMAIN_INIT))
 317 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 318         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 319         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 320         BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) |          \
 321         BIT(POWER_DOMAIN_INIT))
 322 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 323         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 324         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 325         BIT(POWER_DOMAIN_INIT))
 326 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 327         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 328         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 329         BIT(POWER_DOMAIN_INIT))
 330 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 331         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
 332         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
 333         BIT(POWER_DOMAIN_INIT))
 334 #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS (             \
 335         SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |         \
 336         BIT(POWER_DOMAIN_PLLS) |                        \
 337         BIT(POWER_DOMAIN_INIT))
 338 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 339         (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 340         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 341         SKL_DISPLAY_DDI_A_E_POWER_DOMAINS |             \
 342         SKL_DISPLAY_DDI_B_POWER_DOMAINS |               \
 343         SKL_DISPLAY_DDI_C_POWER_DOMAINS |               \
 344         SKL_DISPLAY_DDI_D_POWER_DOMAINS |               \
 345         SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) |           \
 346         BIT(POWER_DOMAIN_INIT))
 347
 348 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 349         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 350         BIT(POWER_DOMAIN_PIPE_B) |                      \
 351         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 352         BIT(POWER_DOMAIN_PIPE_C) |                      \
 353         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 354         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 355         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 356         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
 357         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
 358         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
 359         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
 360         BIT(POWER_DOMAIN_AUX_B) |                       \
 361         BIT(POWER_DOMAIN_AUX_C) |                       \
 362         BIT(POWER_DOMAIN_AUDIO) |                       \
 363         BIT(POWER_DOMAIN_VGA) |                         \
 364         BIT(POWER_DOMAIN_INIT))
 365 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 366         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 367         BIT(POWER_DOMAIN_PIPE_A) |                      \
 368         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 369         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 370         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
 371         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
 372         BIT(POWER_DOMAIN_AUX_A) |                       \
 373         BIT(POWER_DOMAIN_PLLS) |                        \
 374         BIT(POWER_DOMAIN_INIT))
 375 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 376         (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 377         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |       \
 378         BIT(POWER_DOMAIN_INIT))
 379
 380 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 381 {
 382         struct drm_device *dev = dev_priv->dev;
 383
 384         WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
 385         WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 386                 "DC9 already programmed to be enabled.\n");
 387         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 388                 "DC5 still not disabled to enable DC9.\n");
 389         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 390         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 391
 392          /*
 393           * TODO: check for the following to verify the conditions to enter DC9
 394           * state are satisfied:
 395           * 1] Check relevant display engine registers to verify if mode set
 396           * disable sequence was followed.
 397           * 2] Check if display uninitialize sequence is initialized.
 398           */
 399 }
 400
 401 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 402 {
 403         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 404         WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 405                 "DC9 already programmed to be disabled.\n");
 406         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 407                 "DC5 still not disabled.\n");
 408
 409          /*
 410           * TODO: check for the following to verify DC9 state was indeed
 411           * entered before programming to disable it:
 412           * 1] Check relevant display engine registers to verify if mode
 413           *  set disable sequence was followed.
 414           * 2] Check if display uninitialize sequence is initialized.
 415           */
 416 }
 417
 418 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 419 {
 420         uint32_t val;
 421
 422         assert_can_enable_dc9(dev_priv);
 423
 424         DRM_DEBUG_KMS("Enabling DC9\n");
 425
 426         val = I915_READ(DC_STATE_EN);
 427         val |= DC_STATE_EN_DC9;
 428         I915_WRITE(DC_STATE_EN, val);
 429         POSTING_READ(DC_STATE_EN);
 430 }
 431
 432 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 433 {
 434         uint32_t val;
 435
 436         assert_can_disable_dc9(dev_priv);
 437
 438         DRM_DEBUG_KMS("Disabling DC9\n");
 439
 440         val = I915_READ(DC_STATE_EN);
 441         val &= ~DC_STATE_EN_DC9;
 442         I915_WRITE(DC_STATE_EN, val);
 443         POSTING_READ(DC_STATE_EN);
 444 }
 445
 446 static void gen9_set_dc_state_debugmask_memory_up(
 447                         struct drm_i915_private *dev_priv)
 448 {
 449         uint32_t val;
 450
 451         /* The below bit doesn't need to be cleared ever afterwards */
 452         val = I915_READ(DC_STATE_DEBUG);
 453         if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
 454                 val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
 455                 I915_WRITE(DC_STATE_DEBUG, val);
 456                 POSTING_READ(DC_STATE_DEBUG);
 457         }
 458 }
 459
 460 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 461 {
 462         struct drm_device *dev = dev_priv->dev;
 463         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 464                                         SKL_DISP_PW_2);
 465
 466         WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
 467         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 468         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 469
 470         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 471                   "DC5 already programmed to be enabled.\n");
 472         WARN_ONCE(dev_priv->pm.suspended,
 473                   "DC5 cannot be enabled, if platform is runtime-suspended.\n");
 474
 475         assert_csr_loaded(dev_priv);
 476 }
 477
 478 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
 479 {
 480         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 481                                         SKL_DISP_PW_2);
 482         /*
 483          * During initialization, the firmware may not be loaded yet.
 484          * We still want to make sure that the DC enabling flag is cleared.
 485          */
 486         if (dev_priv->power_domains.initializing)
 487                 return;
 488
 489         WARN_ONCE(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
 490         WARN_ONCE(dev_priv->pm.suspended,
 491                 "Disabling of DC5 while platform is runtime-suspended should never happen.\n");
 492 }
 493
 494 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 495 {
 496         uint32_t val;
 497
 498         assert_can_enable_dc5(dev_priv);
 499
 500         DRM_DEBUG_KMS("Enabling DC5\n");
 501
 502         gen9_set_dc_state_debugmask_memory_up(dev_priv);
 503
 504         val = I915_READ(DC_STATE_EN);
 505         val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
 506         val |= DC_STATE_EN_UPTO_DC5;
 507         I915_WRITE(DC_STATE_EN, val);
 508         POSTING_READ(DC_STATE_EN);
 509 }
 510
 511 static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
 512 {
 513         uint32_t val;
 514
 515         assert_can_disable_dc5(dev_priv);
 516
 517         DRM_DEBUG_KMS("Disabling DC5\n");
 518
 519         val = I915_READ(DC_STATE_EN);
 520         val &= ~DC_STATE_EN_UPTO_DC5;
 521         I915_WRITE(DC_STATE_EN, val);
 522         POSTING_READ(DC_STATE_EN);
 523 }
 524
 525 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 526 {
 527         struct drm_device *dev = dev_priv->dev;
 528
 529         WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n");
 530         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 531         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 532                   "Backlight is not disabled.\n");
 533         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 534                   "DC6 already programmed to be enabled.\n");
 535
 536         assert_csr_loaded(dev_priv);
 537 }
 538
 539 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
 540 {
 541         /*
 542          * During initialization, the firmware may not be loaded yet.
 543          * We still want to make sure that the DC enabling flag is cleared.
 544          */
 545         if (dev_priv->power_domains.initializing)
 546                 return;
 547
 548         assert_csr_loaded(dev_priv);
 549         WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 550                   "DC6 already programmed to be disabled.\n");
 551 }
 552
 553 static void skl_enable_dc6(struct drm_i915_private *dev_priv)
 554 {
 555         uint32_t val;
 556
 557         assert_can_enable_dc6(dev_priv);
 558
 559         DRM_DEBUG_KMS("Enabling DC6\n");
 560
 561         gen9_set_dc_state_debugmask_memory_up(dev_priv);
 562
 563         val = I915_READ(DC_STATE_EN);
 564         val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
 565         val |= DC_STATE_EN_UPTO_DC6;
 566         I915_WRITE(DC_STATE_EN, val);
 567         POSTING_READ(DC_STATE_EN);
 568 }
 569
 570 static void skl_disable_dc6(struct drm_i915_private *dev_priv)
 571 {
 572         uint32_t val;
 573
 574         assert_can_disable_dc6(dev_priv);
 575
 576         DRM_DEBUG_KMS("Disabling DC6\n");
 577
 578         val = I915_READ(DC_STATE_EN);
 579         val &= ~DC_STATE_EN_UPTO_DC6;
 580         I915_WRITE(DC_STATE_EN, val);
 581         POSTING_READ(DC_STATE_EN);
 582 }
 583
 584 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 585                         struct i915_power_well *power_well, bool enable)
 586 {
 587         struct drm_device *dev = dev_priv->dev;
 588         uint32_t tmp, fuse_status;
 589         uint32_t req_mask, state_mask;
 590         bool is_enabled, enable_requested, check_fuse_status = false;
 591
 592         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 593         fuse_status = I915_READ(SKL_FUSE_STATUS);
 594
 595         switch (power_well->data) {
 596         case SKL_DISP_PW_1:
 597                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 598                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 599                         DRM_ERROR("PG0 not enabled\n");
 600                         return;
 601                 }
 602                 break;
 603         case SKL_DISP_PW_2:
 604                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 605                         DRM_ERROR("PG1 in disabled state\n");
 606                         return;
 607                 }
 608                 break;
 609         case SKL_DISP_PW_DDI_A_E:
 610         case SKL_DISP_PW_DDI_B:
 611         case SKL_DISP_PW_DDI_C:
 612         case SKL_DISP_PW_DDI_D:
 613         case SKL_DISP_PW_MISC_IO:
 614                 break;
 615         default:
 616                 WARN(1, "Unknown power well %lu\n", power_well->data);
 617                 return;
 618         }
 619
 620         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 621         enable_requested = tmp & req_mask;
 622         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 623         is_enabled = tmp & state_mask;
 624
 625         if (enable) {
 626                 if (!enable_requested) {
 627                         WARN((tmp & state_mask) &&
 628                                 !I915_READ(HSW_PWR_WELL_BIOS),
 629                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 630                                 when request is to disable!\n");
 631                         if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
 632                                 power_well->data == SKL_DISP_PW_2) {
 633                                 if (SKL_ENABLE_DC6(dev)) {
 634                                         skl_disable_dc6(dev_priv);
 635                                         /*
 636                                          * DDI buffer programming unnecessary during driver-load/resume
 637                                          * as it's already done during modeset initialization then.
 638                                          * It's also invalid here as encoder list is still uninitialized.
 639                                          */
 640                                         if (!dev_priv->power_domains.initializing)
 641                                                 intel_prepare_ddi(dev);
 642                                 } else {
 643                                         gen9_disable_dc5(dev_priv);
 644                                 }
 645                         }
 646                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 647                 }
 648
 649                 if (!is_enabled) {
 650                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 651                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 652                                 state_mask), 1))
 653                                 DRM_ERROR("%s enable timeout\n",
 654                                         power_well->name);
 655                         check_fuse_status = true;
 656                 }
 657         } else {
 658                 if (enable_requested) {
 659                         if (IS_SKYLAKE(dev) &&
 660                                 (power_well->data == SKL_DISP_PW_1) &&
 661                                 (intel_csr_load_status_get(dev_priv) == FW_LOADED))
 662                                 DRM_DEBUG_KMS("Not Disabling PW1, dmc will handle\n");
 663                         else {
 664                                 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 665                                 POSTING_READ(HSW_PWR_WELL_DRIVER);
 666                                 DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 667                         }
 668
 669                         if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) &&
 670                                 power_well->data == SKL_DISP_PW_2) {
 671                                 enum csr_state state;
 672                                 /* TODO: wait for a completion event or
 673                                  * similar here instead of busy
 674                                  * waiting using wait_for function.
 675                                  */
 676                                 wait_for((state = intel_csr_load_status_get(dev_priv)) !=
 677                                                 FW_UNINITIALIZED, 1000);
 678                                 if (state != FW_LOADED)
 679                                         DRM_DEBUG("CSR firmware not ready (%d)\n",
 680                                                         state);
 681                                 else
 682                                         if (SKL_ENABLE_DC6(dev))
 683                                                 skl_enable_dc6(dev_priv);
 684                                         else
 685                                                 gen9_enable_dc5(dev_priv);
 686                         }
 687                 }
 688         }
 689
 690         if (check_fuse_status) {
 691                 if (power_well->data == SKL_DISP_PW_1) {
 692                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 693                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 694                                 DRM_ERROR("PG1 distributing status timeout\n");
 695                 } else if (power_well->data == SKL_DISP_PW_2) {
 696                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 697                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 698                                 DRM_ERROR("PG2 distributing status timeout\n");
 699                 }
 700         }
 701
 702         if (enable && !is_enabled)
 703                 skl_power_well_post_enable(dev_priv, power_well);
 704 }
 705
 706 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 707                                    struct i915_power_well *power_well)
 708 {
 709         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 710
 711         /*
 712          * We're taking over the BIOS, so clear any requests made by it since
 713          * the driver is in charge now.
 714          */
 715         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 716                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 717 }
 718
 719 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 720                                   struct i915_power_well *power_well)
 721 {
 722         hsw_set_power_well(dev_priv, power_well, true);
 723 }
 724
 725 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 726                                    struct i915_power_well *power_well)
 727 {
 728         hsw_set_power_well(dev_priv, power_well, false);
 729 }
 730
 731 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 732                                         struct i915_power_well *power_well)
 733 {
 734         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 735                 SKL_POWER_WELL_STATE(power_well->data);
 736
 737         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 738 }
 739
 740 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 741                                 struct i915_power_well *power_well)
 742 {
 743         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 744
 745         /* Clear any request made by BIOS as driver is taking over */
 746         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 747 }
 748
 749 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 750                                 struct i915_power_well *power_well)
 751 {
 752         skl_set_power_well(dev_priv, power_well, true);
 753 }
 754
 755 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 756                                 struct i915_power_well *power_well)
 757 {
 758         skl_set_power_well(dev_priv, power_well, false);
 759 }
 760
 761 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 762                                            struct i915_power_well *power_well)
 763 {
 764 }
 765
 766 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 767                                              struct i915_power_well *power_well)
 768 {
 769         return true;
 770 }
 771
 772 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 773                                struct i915_power_well *power_well, bool enable)
 774 {
 775         enum punit_power_well power_well_id = power_well->data;
 776         u32 mask;
 777         u32 state;
 778         u32 ctrl;
 779
 780         mask = PUNIT_PWRGT_MASK(power_well_id);
 781         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 782                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 783
 784         mutex_lock(&dev_priv->rps.hw_lock);
 785
 786 #define COND \
 787         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 788
 789         if (COND)
 790                 goto out;
 791
 792         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 793         ctrl &= ~mask;
 794         ctrl |= state;
 795         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 796
 797         if (wait_for(COND, 100))
 798                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 799                           state,
 800                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 801
 802 #undef COND
 803
 804 out:
 805         mutex_unlock(&dev_priv->rps.hw_lock);
 806 }
 807
 808 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 809                                    struct i915_power_well *power_well)
 810 {
 811         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 812 }
 813
 814 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 815                                   struct i915_power_well *power_well)
 816 {
 817         vlv_set_power_well(dev_priv, power_well, true);
 818 }
 819
 820 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 821                                    struct i915_power_well *power_well)
 822 {
 823         vlv_set_power_well(dev_priv, power_well, false);
 824 }
 825
 826 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 827                                    struct i915_power_well *power_well)
 828 {
 829         int power_well_id = power_well->data;
 830         bool enabled = false;
 831         u32 mask;
 832         u32 state;
 833         u32 ctrl;
 834
 835         mask = PUNIT_PWRGT_MASK(power_well_id);
 836         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 837
 838         mutex_lock(&dev_priv->rps.hw_lock);
 839
 840         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 841         /*
 842          * We only ever set the power-on and power-gate states, anything
 843          * else is unexpected.
 844          */
 845         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 846                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 847         if (state == ctrl)
 848                 enabled = true;
 849
 850         /*
 851          * A transient state at this point would mean some unexpected party
 852          * is poking at the power controls too.
 853          */
 854         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 855         WARN_ON(ctrl != state);
 856
 857         mutex_unlock(&dev_priv->rps.hw_lock);
 858
 859         return enabled;
 860 }
 861
 862 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 863 {
 864         enum pipe pipe;
 865
 866         /*
 867          * Enable the CRI clock source so we can get at the
 868          * display and the reference clock for VGA
 869          * hotplug / manual detection. Supposedly DSI also
 870          * needs the ref clock up and running.
 871          *
 872          * CHV DPLL B/C have some issues if VGA mode is enabled.
 873          */
 874         for_each_pipe(dev_priv->dev, pipe) {
 875                 u32 val = I915_READ(DPLL(pipe));
 876
 877                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 878                 if (pipe != PIPE_A)
 879                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 880
 881                 I915_WRITE(DPLL(pipe), val);
 882         }
 883
 884         spin_lock_irq(&dev_priv->irq_lock);
 885         valleyview_enable_display_irqs(dev_priv);
 886         spin_unlock_irq(&dev_priv->irq_lock);
 887
 888         /*
 889          * During driver initialization/resume we can avoid restoring the
 890          * part of the HW/SW state that will be inited anyway explicitly.
 891          */
 892         if (dev_priv->power_domains.initializing)
 893                 return;
 894
 895         intel_hpd_init(dev_priv);
 896
 897         i915_redisable_vga_power_on(dev_priv->dev);
 898 }
 899
 900 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 901 {
 902         spin_lock_irq(&dev_priv->irq_lock);
 903         valleyview_disable_display_irqs(dev_priv);
 904         spin_unlock_irq(&dev_priv->irq_lock);
 905
 906         vlv_power_sequencer_reset(dev_priv);
 907 }
 908
 909 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
 910                                           struct i915_power_well *power_well)
 911 {
 912         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 913
 914         vlv_set_power_well(dev_priv, power_well, true);
 915
 916         vlv_display_power_well_init(dev_priv);
 917 }
 918
 919 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
 920                                            struct i915_power_well *power_well)
 921 {
 922         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
 923
 924         vlv_display_power_well_deinit(dev_priv);
 925
 926         vlv_set_power_well(dev_priv, power_well, false);
 927 }
 928
 929 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 930                                            struct i915_power_well *power_well)
 931 {
 932         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 933
 934         /* since ref/cri clock was enabled */
 935         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
 936
 937         vlv_set_power_well(dev_priv, power_well, true);
 938
 939         /*
 940          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
 941          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
 942          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
 943          *   b. The other bits such as sfr settings / modesel may all
 944          *      be set to 0.
 945          *
 946          * This should only be done on init and resume from S3 with
 947          * both PLLs disabled, or we risk losing DPIO and PLL
 948          * synchronization.
 949          */
 950         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
 951 }
 952
 953 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 954                                             struct i915_power_well *power_well)
 955 {
 956         enum pipe pipe;
 957
 958         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
 959
 960         for_each_pipe(dev_priv, pipe)
 961                 assert_pll_disabled(dev_priv, pipe);
 962
 963         /* Assert common reset */
 964         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
 965
 966         vlv_set_power_well(dev_priv, power_well, false);
 967 }
 968
 969 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
 970
 971 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
 972                                                  int power_well_id)
 973 {
 974         struct i915_power_domains *power_domains = &dev_priv->power_domains;
 975         struct i915_power_well *power_well;
 976         int i;
 977
 978         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
 979                 if (power_well->data == power_well_id)
 980                         return power_well;
 981         }
 982
 983         return NULL;
 984 }
 985
 986 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
 987
 988 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
 989 {
 990         struct i915_power_well *cmn_bc =
 991                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
 992         struct i915_power_well *cmn_d =
 993                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
 994         u32 phy_control = dev_priv->chv_phy_control;
 995         u32 phy_status = 0;
 996         u32 tmp;
 997
 998         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
 999                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1000
1001                 /* this assumes override is only used to enable lanes */
1002                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1003                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1004
1005                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1006                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1007
1008                 /* CL1 is on whenever anything is on in either channel */
1009                 if (BITS_SET(phy_control,
1010                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1011                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1012                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1013
1014                 /*
1015                  * The DPLLB check accounts for the pipe B + port A usage
1016                  * with CL2 powered up but all the lanes in the second channel
1017                  * powered down.
1018                  */
1019                 if (BITS_SET(phy_control,
1020                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1021                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1022                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1023
1024                 if (BITS_SET(phy_control,
1025                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1026                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1027                 if (BITS_SET(phy_control,
1028                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1029                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1030
1031                 if (BITS_SET(phy_control,
1032                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1033                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1034                 if (BITS_SET(phy_control,
1035                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1036                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1037         }
1038
1039         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1040                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1041
1042                 /* this assumes override is only used to enable lanes */
1043                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1044                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1045
1046                 if (BITS_SET(phy_control,
1047                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1048                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1049
1050                 if (BITS_SET(phy_control,
1051                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1052                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1053                 if (BITS_SET(phy_control,
1054                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1055                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1056         }
1057
1058         /*
1059          * The PHY may be busy with some initial calibration and whatnot,
1060          * so the power state can take a while to actually change.
1061          */
1062         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS)) == phy_status, 10))
1063                 WARN(phy_status != tmp,
1064                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1065                      tmp, phy_status, dev_priv->chv_phy_control);
1066 }
1067
1068 #undef BITS_SET
1069
1070 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1071                                            struct i915_power_well *power_well)
1072 {
1073         enum dpio_phy phy;
1074         enum pipe pipe;
1075         uint32_t tmp;
1076
1077         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1078                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1079
1080         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1081                 pipe = PIPE_A;
1082                 phy = DPIO_PHY0;
1083         } else {
1084                 pipe = PIPE_C;
1085                 phy = DPIO_PHY1;
1086         }
1087
1088         /* since ref/cri clock was enabled */
1089         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1090         vlv_set_power_well(dev_priv, power_well, true);
1091
1092         /* Poll for phypwrgood signal */
1093         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1094                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1095
1096         mutex_lock(&dev_priv->sb_lock);
1097
1098         /* Enable dynamic power down */
1099         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1100         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1101                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1102         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1103
1104         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1105                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1106                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1107                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1108         } else {
1109                 /*
1110                  * Force the non-existing CL2 off. BXT does this
1111                  * too, so maybe it saves some power even though
1112                  * CL2 doesn't exist?
1113                  */
1114                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1115                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1116                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1117         }
1118
1119         mutex_unlock(&dev_priv->sb_lock);
1120
1121         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1122         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1123
1124         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1125                       phy, dev_priv->chv_phy_control);
1126
1127         assert_chv_phy_status(dev_priv);
1128 }
1129
1130 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1131                                             struct i915_power_well *power_well)
1132 {
1133         enum dpio_phy phy;
1134
1135         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1136                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1137
1138         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1139                 phy = DPIO_PHY0;
1140                 assert_pll_disabled(dev_priv, PIPE_A);
1141                 assert_pll_disabled(dev_priv, PIPE_B);
1142         } else {
1143                 phy = DPIO_PHY1;
1144                 assert_pll_disabled(dev_priv, PIPE_C);
1145         }
1146
1147         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1148         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1149
1150         vlv_set_power_well(dev_priv, power_well, false);
1151
1152         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1153                       phy, dev_priv->chv_phy_control);
1154
1155         assert_chv_phy_status(dev_priv);
1156 }
1157
1158 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1159                                      enum dpio_channel ch, bool override, unsigned int mask)
1160 {
1161         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1162         u32 reg, val, expected, actual;
1163
1164         if (ch == DPIO_CH0)
1165                 reg = _CHV_CMN_DW0_CH0;
1166         else
1167                 reg = _CHV_CMN_DW6_CH1;
1168
1169         mutex_lock(&dev_priv->sb_lock);
1170         val = vlv_dpio_read(dev_priv, pipe, reg);
1171         mutex_unlock(&dev_priv->sb_lock);
1172
1173         /*
1174          * This assumes !override is only used when the port is disabled.
1175          * All lanes should power down even without the override when
1176          * the port is disabled.
1177          */
1178         if (!override || mask == 0xf) {
1179                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1180                 /*
1181                  * If CH1 common lane is not active anymore
1182                  * (eg. for pipe B DPLL) the entire channel will
1183                  * shut down, which causes the common lane registers
1184                  * to read as 0. That means we can't actually check
1185                  * the lane power down status bits, but as the entire
1186                  * register reads as 0 it's a good indication that the
1187                  * channel is indeed entirely powered down.
1188                  */
1189                 if (ch == DPIO_CH1 && val == 0)
1190                         expected = 0;
1191         } else if (mask != 0x0) {
1192                 expected = DPIO_ANYDL_POWERDOWN;
1193         } else {
1194                 expected = 0;
1195         }
1196
1197         if (ch == DPIO_CH0)
1198                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1199         else
1200                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1201         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1202
1203         WARN(actual != expected,
1204              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1205              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1206              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1207              reg, val);
1208 }
1209
1210 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1211                           enum dpio_channel ch, bool override)
1212 {
1213         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1214         bool was_override;
1215
1216         mutex_lock(&power_domains->lock);
1217
1218         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1219
1220         if (override == was_override)
1221                 goto out;
1222
1223         if (override)
1224                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1225         else
1226                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1227
1228         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1229
1230         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1231                       phy, ch, dev_priv->chv_phy_control);
1232
1233         assert_chv_phy_status(dev_priv);
1234
1235 out:
1236         mutex_unlock(&power_domains->lock);
1237
1238         return was_override;
1239 }
1240
1241 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1242                              bool override, unsigned int mask)
1243 {
1244         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1245         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1246         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1247         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1248
1249         mutex_lock(&power_domains->lock);
1250
1251         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1252         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1253
1254         if (override)
1255                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1256         else
1257                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1258
1259         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1260
1261         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1262                       phy, ch, mask, dev_priv->chv_phy_control);
1263
1264         assert_chv_phy_status(dev_priv);
1265
1266         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1267
1268         mutex_unlock(&power_domains->lock);
1269 }
1270
1271 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1272                                         struct i915_power_well *power_well)
1273 {
1274         enum pipe pipe = power_well->data;
1275         bool enabled;
1276         u32 state, ctrl;
1277
1278         mutex_lock(&dev_priv->rps.hw_lock);
1279
1280         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1281         /*
1282          * We only ever set the power-on and power-gate states, anything
1283          * else is unexpected.
1284          */
1285         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1286         enabled = state == DP_SSS_PWR_ON(pipe);
1287
1288         /*
1289          * A transient state at this point would mean some unexpected party
1290          * is poking at the power controls too.
1291          */
1292         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1293         WARN_ON(ctrl << 16 != state);
1294
1295         mutex_unlock(&dev_priv->rps.hw_lock);
1296
1297         return enabled;
1298 }
1299
1300 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1301                                     struct i915_power_well *power_well,
1302                                     bool enable)
1303 {
1304         enum pipe pipe = power_well->data;
1305         u32 state;
1306         u32 ctrl;
1307
1308         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1309
1310         mutex_lock(&dev_priv->rps.hw_lock);
1311
1312 #define COND \
1313         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1314
1315         if (COND)
1316                 goto out;
1317
1318         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1319         ctrl &= ~DP_SSC_MASK(pipe);
1320         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1321         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1322
1323         if (wait_for(COND, 100))
1324                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1325                           state,
1326                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1327
1328 #undef COND
1329
1330 out:
1331         mutex_unlock(&dev_priv->rps.hw_lock);
1332 }
1333
1334 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1335                                         struct i915_power_well *power_well)
1336 {
1337         WARN_ON_ONCE(power_well->data != PIPE_A);
1338
1339         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1340 }
1341
1342 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1343                                        struct i915_power_well *power_well)
1344 {
1345         WARN_ON_ONCE(power_well->data != PIPE_A);
1346
1347         chv_set_pipe_power_well(dev_priv, power_well, true);
1348
1349         vlv_display_power_well_init(dev_priv);
1350 }
1351
1352 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1353                                         struct i915_power_well *power_well)
1354 {
1355         WARN_ON_ONCE(power_well->data != PIPE_A);
1356
1357         vlv_display_power_well_deinit(dev_priv);
1358
1359         chv_set_pipe_power_well(dev_priv, power_well, false);
1360 }
1361
1362 /**
1363  * intel_display_power_get - grab a power domain reference
1364  * @dev_priv: i915 device instance
1365  * @domain: power domain to reference
1366  *
1367  * This function grabs a power domain reference for @domain and ensures that the
1368  * power domain and all its parents are powered up. Therefore users should only
1369  * grab a reference to the innermost power domain they need.
1370  *
1371  * Any power domain reference obtained by this function must have a symmetric
1372  * call to intel_display_power_put() to release the reference again.
1373  */
1374 void intel_display_power_get(struct drm_i915_private *dev_priv,
1375                              enum intel_display_power_domain domain)
1376 {
1377         struct i915_power_domains *power_domains;
1378         struct i915_power_well *power_well;
1379         int i;
1380
1381         intel_runtime_pm_get(dev_priv);
1382
1383         power_domains = &dev_priv->power_domains;
1384
1385         mutex_lock(&power_domains->lock);
1386
1387         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1388                 if (!power_well->count++)
1389                         intel_power_well_enable(dev_priv, power_well);
1390         }
1391
1392         power_domains->domain_use_count[domain]++;
1393
1394         mutex_unlock(&power_domains->lock);
1395 }
1396
1397 /**
1398  * intel_display_power_put - release a power domain reference
1399  * @dev_priv: i915 device instance
1400  * @domain: power domain to reference
1401  *
1402  * This function drops the power domain reference obtained by
1403  * intel_display_power_get() and might power down the corresponding hardware
1404  * block right away if this is the last reference.
1405  */
1406 void intel_display_power_put(struct drm_i915_private *dev_priv,
1407                              enum intel_display_power_domain domain)
1408 {
1409         struct i915_power_domains *power_domains;
1410         struct i915_power_well *power_well;
1411         int i;
1412
1413         power_domains = &dev_priv->power_domains;
1414
1415         mutex_lock(&power_domains->lock);
1416
1417         WARN_ON(!power_domains->domain_use_count[domain]);
1418         power_domains->domain_use_count[domain]--;
1419
1420         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1421                 WARN_ON(!power_well->count);
1422
1423                 if (!--power_well->count && i915.disable_power_well)
1424                         intel_power_well_disable(dev_priv, power_well);
1425         }
1426
1427         mutex_unlock(&power_domains->lock);
1428
1429         intel_runtime_pm_put(dev_priv);
1430 }
1431
1432 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
1433         BIT(POWER_DOMAIN_PIPE_A) |                      \
1434         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
1435         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
1436         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
1437         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
1438         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
1439         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
1440         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
1441         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
1442         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
1443         BIT(POWER_DOMAIN_PORT_CRT) |                    \
1444         BIT(POWER_DOMAIN_PLLS) |                        \
1445         BIT(POWER_DOMAIN_AUX_A) |                       \
1446         BIT(POWER_DOMAIN_AUX_B) |                       \
1447         BIT(POWER_DOMAIN_AUX_C) |                       \
1448         BIT(POWER_DOMAIN_AUX_D) |                       \
1449         BIT(POWER_DOMAIN_INIT))
1450 #define HSW_DISPLAY_POWER_DOMAINS (                             \
1451         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
1452         BIT(POWER_DOMAIN_INIT))
1453
1454 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
1455         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
1456         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1457 #define BDW_DISPLAY_POWER_DOMAINS (                             \
1458         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
1459         BIT(POWER_DOMAIN_INIT))
1460
1461 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
1462 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
1463
1464 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1465         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1466         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1467         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1468         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1469         BIT(POWER_DOMAIN_PORT_CRT) |            \
1470         BIT(POWER_DOMAIN_AUX_B) |               \
1471         BIT(POWER_DOMAIN_AUX_C) |               \
1472         BIT(POWER_DOMAIN_INIT))
1473
1474 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1475         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1476         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1477         BIT(POWER_DOMAIN_AUX_B) |               \
1478         BIT(POWER_DOMAIN_INIT))
1479
1480 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1481         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1482         BIT(POWER_DOMAIN_AUX_B) |               \
1483         BIT(POWER_DOMAIN_INIT))
1484
1485 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1486         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1487         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1488         BIT(POWER_DOMAIN_AUX_C) |               \
1489         BIT(POWER_DOMAIN_INIT))
1490
1491 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1492         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1493         BIT(POWER_DOMAIN_AUX_C) |               \
1494         BIT(POWER_DOMAIN_INIT))
1495
1496 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1497         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
1498         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
1499         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
1500         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
1501         BIT(POWER_DOMAIN_AUX_B) |               \
1502         BIT(POWER_DOMAIN_AUX_C) |               \
1503         BIT(POWER_DOMAIN_INIT))
1504
1505 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1506         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |  \
1507         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |  \
1508         BIT(POWER_DOMAIN_AUX_D) |               \
1509         BIT(POWER_DOMAIN_INIT))
1510
1511 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1512         .sync_hw = i9xx_always_on_power_well_noop,
1513         .enable = i9xx_always_on_power_well_noop,
1514         .disable = i9xx_always_on_power_well_noop,
1515         .is_enabled = i9xx_always_on_power_well_enabled,
1516 };
1517
1518 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1519         .sync_hw = chv_pipe_power_well_sync_hw,
1520         .enable = chv_pipe_power_well_enable,
1521         .disable = chv_pipe_power_well_disable,
1522         .is_enabled = chv_pipe_power_well_enabled,
1523 };
1524
1525 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1526         .sync_hw = vlv_power_well_sync_hw,
1527         .enable = chv_dpio_cmn_power_well_enable,
1528         .disable = chv_dpio_cmn_power_well_disable,
1529         .is_enabled = vlv_power_well_enabled,
1530 };
1531
1532 static struct i915_power_well i9xx_always_on_power_well[] = {
1533         {
1534                 .name = "always-on",
1535                 .always_on = 1,
1536                 .domains = POWER_DOMAIN_MASK,
1537                 .ops = &i9xx_always_on_power_well_ops,
1538         },
1539 };
1540
1541 static const struct i915_power_well_ops hsw_power_well_ops = {
1542         .sync_hw = hsw_power_well_sync_hw,
1543         .enable = hsw_power_well_enable,
1544         .disable = hsw_power_well_disable,
1545         .is_enabled = hsw_power_well_enabled,
1546 };
1547
1548 static const struct i915_power_well_ops skl_power_well_ops = {
1549         .sync_hw = skl_power_well_sync_hw,
1550         .enable = skl_power_well_enable,
1551         .disable = skl_power_well_disable,
1552         .is_enabled = skl_power_well_enabled,
1553 };
1554
1555 static struct i915_power_well hsw_power_wells[] = {
1556         {
1557                 .name = "always-on",
1558                 .always_on = 1,
1559                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1560                 .ops = &i9xx_always_on_power_well_ops,
1561         },
1562         {
1563                 .name = "display",
1564                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1565                 .ops = &hsw_power_well_ops,
1566         },
1567 };
1568
1569 static struct i915_power_well bdw_power_wells[] = {
1570         {
1571                 .name = "always-on",
1572                 .always_on = 1,
1573                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1574                 .ops = &i9xx_always_on_power_well_ops,
1575         },
1576         {
1577                 .name = "display",
1578                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1579                 .ops = &hsw_power_well_ops,
1580         },
1581 };
1582
1583 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1584         .sync_hw = vlv_power_well_sync_hw,
1585         .enable = vlv_display_power_well_enable,
1586         .disable = vlv_display_power_well_disable,
1587         .is_enabled = vlv_power_well_enabled,
1588 };
1589
1590 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1591         .sync_hw = vlv_power_well_sync_hw,
1592         .enable = vlv_dpio_cmn_power_well_enable,
1593         .disable = vlv_dpio_cmn_power_well_disable,
1594         .is_enabled = vlv_power_well_enabled,
1595 };
1596
1597 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1598         .sync_hw = vlv_power_well_sync_hw,
1599         .enable = vlv_power_well_enable,
1600         .disable = vlv_power_well_disable,
1601         .is_enabled = vlv_power_well_enabled,
1602 };
1603
1604 static struct i915_power_well vlv_power_wells[] = {
1605         {
1606                 .name = "always-on",
1607                 .always_on = 1,
1608                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1609                 .ops = &i9xx_always_on_power_well_ops,
1610         },
1611         {
1612                 .name = "display",
1613                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1614                 .data = PUNIT_POWER_WELL_DISP2D,
1615                 .ops = &vlv_display_power_well_ops,
1616         },
1617         {
1618                 .name = "dpio-tx-b-01",
1619                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1620                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1621                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1622                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1623                 .ops = &vlv_dpio_power_well_ops,
1624                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1625         },
1626         {
1627                 .name = "dpio-tx-b-23",
1628                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1629                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1630                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1631                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1632                 .ops = &vlv_dpio_power_well_ops,
1633                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1634         },
1635         {
1636                 .name = "dpio-tx-c-01",
1637                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1638                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1639                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1640                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1641                 .ops = &vlv_dpio_power_well_ops,
1642                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1643         },
1644         {
1645                 .name = "dpio-tx-c-23",
1646                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1647                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1648                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1649                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1650                 .ops = &vlv_dpio_power_well_ops,
1651                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1652         },
1653         {
1654                 .name = "dpio-common",
1655                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1656                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1657                 .ops = &vlv_dpio_cmn_power_well_ops,
1658         },
1659 };
1660
1661 static struct i915_power_well chv_power_wells[] = {
1662         {
1663                 .name = "always-on",
1664                 .always_on = 1,
1665                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1666                 .ops = &i9xx_always_on_power_well_ops,
1667         },
1668         {
1669                 .name = "display",
1670                 /*
1671                  * Pipe A power well is the new disp2d well. Pipe B and C
1672                  * power wells don't actually exist. Pipe A power well is
1673                  * required for any pipe to work.
1674                  */
1675                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1676                 .data = PIPE_A,
1677                 .ops = &chv_pipe_power_well_ops,
1678         },
1679         {
1680                 .name = "dpio-common-bc",
1681                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1682                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1683                 .ops = &chv_dpio_cmn_power_well_ops,
1684         },
1685         {
1686                 .name = "dpio-common-d",
1687                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1688                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1689                 .ops = &chv_dpio_cmn_power_well_ops,
1690         },
1691 };
1692
1693 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1694                                     int power_well_id)
1695 {
1696         struct i915_power_well *power_well;
1697         bool ret;
1698
1699         power_well = lookup_power_well(dev_priv, power_well_id);
1700         ret = power_well->ops->is_enabled(dev_priv, power_well);
1701
1702         return ret;
1703 }
1704
1705 static struct i915_power_well skl_power_wells[] = {
1706         {
1707                 .name = "always-on",
1708                 .always_on = 1,
1709                 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1710                 .ops = &i9xx_always_on_power_well_ops,
1711         },
1712         {
1713                 .name = "power well 1",
1714                 .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1715                 .ops = &skl_power_well_ops,
1716                 .data = SKL_DISP_PW_1,
1717         },
1718         {
1719                 .name = "MISC IO power well",
1720                 .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS,
1721                 .ops = &skl_power_well_ops,
1722                 .data = SKL_DISP_PW_MISC_IO,
1723         },
1724         {
1725                 .name = "power well 2",
1726                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1727                 .ops = &skl_power_well_ops,
1728                 .data = SKL_DISP_PW_2,
1729         },
1730         {
1731                 .name = "DDI A/E power well",
1732                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1733                 .ops = &skl_power_well_ops,
1734                 .data = SKL_DISP_PW_DDI_A_E,
1735         },
1736         {
1737                 .name = "DDI B power well",
1738                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1739                 .ops = &skl_power_well_ops,
1740                 .data = SKL_DISP_PW_DDI_B,
1741         },
1742         {
1743                 .name = "DDI C power well",
1744                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1745                 .ops = &skl_power_well_ops,
1746                 .data = SKL_DISP_PW_DDI_C,
1747         },
1748         {
1749                 .name = "DDI D power well",
1750                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1751                 .ops = &skl_power_well_ops,
1752                 .data = SKL_DISP_PW_DDI_D,
1753         },
1754 };
1755
1756 static struct i915_power_well bxt_power_wells[] = {
1757         {
1758                 .name = "always-on",
1759                 .always_on = 1,
1760                 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1761                 .ops = &i9xx_always_on_power_well_ops,
1762         },
1763         {
1764                 .name = "power well 1",
1765                 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1766                 .ops = &skl_power_well_ops,
1767                 .data = SKL_DISP_PW_1,
1768         },
1769         {
1770                 .name = "power well 2",
1771                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1772                 .ops = &skl_power_well_ops,
1773                 .data = SKL_DISP_PW_2,
1774         }
1775 };
1776
1777 #define set_power_wells(power_domains, __power_wells) ({                \
1778         (power_domains)->power_wells = (__power_wells);                 \
1779         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
1780 })
1781
1782 /**
1783  * intel_power_domains_init - initializes the power domain structures
1784  * @dev_priv: i915 device instance
1785  *
1786  * Initializes the power domain structures for @dev_priv depending upon the
1787  * supported platform.
1788  */
1789 int intel_power_domains_init(struct drm_i915_private *dev_priv)
1790 {
1791         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1792
1793         mutex_init(&power_domains->lock);
1794
1795         /*
1796          * The enabling order will be from lower to higher indexed wells,
1797          * the disabling order is reversed.
1798          */
1799         if (IS_HASWELL(dev_priv->dev)) {
1800                 set_power_wells(power_domains, hsw_power_wells);
1801         } else if (IS_BROADWELL(dev_priv->dev)) {
1802                 set_power_wells(power_domains, bdw_power_wells);
1803         } else if (IS_SKYLAKE(dev_priv->dev)) {
1804                 set_power_wells(power_domains, skl_power_wells);
1805         } else if (IS_BROXTON(dev_priv->dev)) {
1806                 set_power_wells(power_domains, bxt_power_wells);
1807         } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1808                 set_power_wells(power_domains, chv_power_wells);
1809         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
1810                 set_power_wells(power_domains, vlv_power_wells);
1811         } else {
1812                 set_power_wells(power_domains, i9xx_always_on_power_well);
1813         }
1814
1815         return 0;
1816 }
1817
1818 static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)
1819 {
1820         struct drm_device *dev = dev_priv->dev;
1821         struct device *device = &dev->pdev->dev;
1822
1823         if (!HAS_RUNTIME_PM(dev))
1824                 return;
1825
1826         if (!intel_enable_rc6(dev))
1827                 return;
1828
1829         /* Make sure we're not suspended first. */
1830         pm_runtime_get_sync(device);
1831 }
1832
1833 /**
1834  * intel_power_domains_fini - finalizes the power domain structures
1835  * @dev_priv: i915 device instance
1836  *
1837  * Finalizes the power domain structures for @dev_priv depending upon the
1838  * supported platform. This function also disables runtime pm and ensures that
1839  * the device stays powered up so that the driver can be reloaded.
1840  */
1841 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
1842 {
1843         intel_runtime_pm_disable(dev_priv);
1844
1845         /* The i915.ko module is still not prepared to be loaded when
1846          * the power well is not enabled, so just enable it in case
1847          * we're going to unload/reload. */
1848         intel_display_set_init_power(dev_priv, true);
1849 }
1850
1851 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
1852 {
1853         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1854         struct i915_power_well *power_well;
1855         int i;
1856
1857         mutex_lock(&power_domains->lock);
1858         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1859                 power_well->ops->sync_hw(dev_priv, power_well);
1860                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
1861                                                                      power_well);
1862         }
1863         mutex_unlock(&power_domains->lock);
1864 }
1865
1866 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
1867 {
1868         struct i915_power_well *cmn_bc =
1869                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1870         struct i915_power_well *cmn_d =
1871                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1872
1873         /*
1874          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
1875          * workaround never ever read DISPLAY_PHY_CONTROL, and
1876          * instead maintain a shadow copy ourselves. Use the actual
1877          * power well state and lane status to reconstruct the
1878          * expected initial value.
1879          */
1880         dev_priv->chv_phy_control =
1881                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
1882                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
1883                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
1884                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
1885                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
1886
1887         /*
1888          * If all lanes are disabled we leave the override disabled
1889          * with all power down bits cleared to match the state we
1890          * would use after disabling the port. Otherwise enable the
1891          * override and set the lane powerdown bits accding to the
1892          * current lane status.
1893          */
1894         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1895                 uint32_t status = I915_READ(DPLL(PIPE_A));
1896                 unsigned int mask;
1897
1898                 mask = status & DPLL_PORTB_READY_MASK;
1899                 if (mask == 0xf)
1900                         mask = 0x0;
1901                 else
1902                         dev_priv->chv_phy_control |=
1903                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
1904
1905                 dev_priv->chv_phy_control |=
1906                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
1907
1908                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
1909                 if (mask == 0xf)
1910                         mask = 0x0;
1911                 else
1912                         dev_priv->chv_phy_control |=
1913                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
1914
1915                 dev_priv->chv_phy_control |=
1916                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
1917
1918                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
1919         }
1920
1921         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1922                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
1923                 unsigned int mask;
1924
1925                 mask = status & DPLL_PORTD_READY_MASK;
1926
1927                 if (mask == 0xf)
1928                         mask = 0x0;
1929                 else
1930                         dev_priv->chv_phy_control |=
1931                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
1932
1933                 dev_priv->chv_phy_control |=
1934                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
1935
1936                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
1937         }
1938
1939         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1940
1941         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
1942                       dev_priv->chv_phy_control);
1943 }
1944
1945 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
1946 {
1947         struct i915_power_well *cmn =
1948                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1949         struct i915_power_well *disp2d =
1950                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
1951
1952         /* If the display might be already active skip this */
1953         if (cmn->ops->is_enabled(dev_priv, cmn) &&
1954             disp2d->ops->is_enabled(dev_priv, disp2d) &&
1955             I915_READ(DPIO_CTL) & DPIO_CMNRST)
1956                 return;
1957
1958         DRM_DEBUG_KMS("toggling display PHY side reset\n");
1959
1960         /* cmnlane needs DPLL registers */
1961         disp2d->ops->enable(dev_priv, disp2d);
1962
1963         /*
1964          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1965          * Need to assert and de-assert PHY SB reset by gating the
1966          * common lane power, then un-gating it.
1967          * Simply ungating isn't enough to reset the PHY enough to get
1968          * ports and lanes running.
1969          */
1970         cmn->ops->disable(dev_priv, cmn);
1971 }
1972
1973 /**
1974  * intel_power_domains_init_hw - initialize hardware power domain state
1975  * @dev_priv: i915 device instance
1976  *
1977  * This function initializes the hardware power domain state and enables all
1978  * power domains using intel_display_set_init_power().
1979  */
1980 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
1981 {
1982         struct drm_device *dev = dev_priv->dev;
1983         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1984
1985         power_domains->initializing = true;
1986
1987         if (IS_CHERRYVIEW(dev)) {
1988                 mutex_lock(&power_domains->lock);
1989                 chv_phy_control_init(dev_priv);
1990                 mutex_unlock(&power_domains->lock);
1991         } else if (IS_VALLEYVIEW(dev)) {
1992                 mutex_lock(&power_domains->lock);
1993                 vlv_cmnlane_wa(dev_priv);
1994                 mutex_unlock(&power_domains->lock);
1995         }
1996
1997         /* For now, we need the power well to be always enabled. */
1998         intel_display_set_init_power(dev_priv, true);
1999         intel_power_domains_resume(dev_priv);
2000         power_domains->initializing = false;
2001 }
2002
2003 /**
2004  * intel_aux_display_runtime_get - grab an auxiliary power domain reference
2005  * @dev_priv: i915 device instance
2006  *
2007  * This function grabs a power domain reference for the auxiliary power domain
2008  * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its
2009  * parents are powered up. Therefore users should only grab a reference to the
2010  * innermost power domain they need.
2011  *
2012  * Any power domain reference obtained by this function must have a symmetric
2013  * call to intel_aux_display_runtime_put() to release the reference again.
2014  */
2015 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
2016 {
2017         intel_runtime_pm_get(dev_priv);
2018 }
2019
2020 /**
2021  * intel_aux_display_runtime_put - release an auxiliary power domain reference
2022  * @dev_priv: i915 device instance
2023  *
2024  * This function drops the auxiliary power domain reference obtained by
2025  * intel_aux_display_runtime_get() and might power down the corresponding
2026  * hardware block right away if this is the last reference.
2027  */
2028 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
2029 {
2030         intel_runtime_pm_put(dev_priv);
2031 }
2032
2033 /**
2034  * intel_runtime_pm_get - grab a runtime pm reference
2035  * @dev_priv: i915 device instance
2036  *
2037  * This function grabs a device-level runtime pm reference (mostly used for GEM
2038  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2039  *
2040  * Any runtime pm reference obtained by this function must have a symmetric
2041  * call to intel_runtime_pm_put() to release the reference again.
2042  */
2043 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2044 {
2045         struct drm_device *dev = dev_priv->dev;
2046         struct device *device = &dev->pdev->dev;
2047
2048         if (!HAS_RUNTIME_PM(dev))
2049                 return;
2050
2051         pm_runtime_get_sync(device);
2052         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
2053 }
2054
2055 /**
2056  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2057  * @dev_priv: i915 device instance
2058  *
2059  * This function grabs a device-level runtime pm reference (mostly used for GEM
2060  * code to ensure the GTT or GT is on).
2061  *
2062  * It will _not_ power up the device but instead only check that it's powered
2063  * on.  Therefore it is only valid to call this functions from contexts where
2064  * the device is known to be powered up and where trying to power it up would
2065  * result in hilarity and deadlocks. That pretty much means only the system
2066  * suspend/resume code where this is used to grab runtime pm references for
2067  * delayed setup down in work items.
2068  *
2069  * Any runtime pm reference obtained by this function must have a symmetric
2070  * call to intel_runtime_pm_put() to release the reference again.
2071  */
2072 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2073 {
2074         struct drm_device *dev = dev_priv->dev;
2075         struct device *device = &dev->pdev->dev;
2076
2077         if (!HAS_RUNTIME_PM(dev))
2078                 return;
2079
2080         WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
2081         pm_runtime_get_noresume(device);
2082 }
2083
2084 /**
2085  * intel_runtime_pm_put - release a runtime pm reference
2086  * @dev_priv: i915 device instance
2087  *
2088  * This function drops the device-level runtime pm reference obtained by
2089  * intel_runtime_pm_get() and might power down the corresponding
2090  * hardware block right away if this is the last reference.
2091  */
2092 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2093 {
2094         struct drm_device *dev = dev_priv->dev;
2095         struct device *device = &dev->pdev->dev;
2096
2097         if (!HAS_RUNTIME_PM(dev))
2098                 return;
2099
2100         pm_runtime_mark_last_busy(device);
2101         pm_runtime_put_autosuspend(device);
2102 }
2103
2104 /**
2105  * intel_runtime_pm_enable - enable runtime pm
2106  * @dev_priv: i915 device instance
2107  *
2108  * This function enables runtime pm at the end of the driver load sequence.
2109  *
2110  * Note that this function does currently not enable runtime pm for the
2111  * subordinate display power domains. That is only done on the first modeset
2112  * using intel_display_set_init_power().
2113  */
2114 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2115 {
2116         struct drm_device *dev = dev_priv->dev;
2117         struct device *device = &dev->pdev->dev;
2118
2119         if (!HAS_RUNTIME_PM(dev))
2120                 return;
2121
2122         /*
2123          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
2124          * requirement.
2125          */
2126         if (!intel_enable_rc6(dev)) {
2127                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
2128                 return;
2129         }
2130
2131         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2132         pm_runtime_mark_last_busy(device);
2133         pm_runtime_use_autosuspend(device);
2134
2135         pm_runtime_put_autosuspend(device);
2136 }
2137