drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include "i915_drv.h"
  31 #include "intel_drv.h"
  32 #include "../../../platform/x86/intel_ips.h"
  33 #include <linux/module.h>
  34
  35 /**
  36  * DOC: RC6
  37  *
  38  * RC6 is a special power stage which allows the GPU to enter an very
  39  * low-voltage mode when idle, using down to 0V while at this stage.  This
  40  * stage is entered automatically when the GPU is idle when RC6 support is
  41  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  42  *
  43  * There are different RC6 modes available in Intel GPU, which differentiate
  44  * among each other with the latency required to enter and leave RC6 and
  45  * voltage consumed by the GPU in different states.
  46  *
  47  * The combination of the following flags define which states GPU is allowed
  48  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  49  * RC6pp is deepest RC6. Their support by hardware varies according to the
  50  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  51  * which brings the most power savings; deeper states save more power, but
  52  * require higher latency to switch to and wake up.
  53  */
  54 #define INTEL_RC6_ENABLE                        (1<<0)
  55 #define INTEL_RC6p_ENABLE                       (1<<1)
  56 #define INTEL_RC6pp_ENABLE                      (1<<2)
  57
  58 static void gen9_init_clock_gating(struct drm_device *dev)
  59 {
  60         struct drm_i915_private *dev_priv = dev->dev_private;
  61
  62         /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
  63         I915_WRITE(CHICKEN_PAR1_1,
  64                    I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
  65
  66         I915_WRITE(GEN8_CONFIG0,
  67                    I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
  68
  69         /* WaEnableChickenDCPR:skl,bxt,kbl */
  70         I915_WRITE(GEN8_CHICKEN_DCPR_1,
  71                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
  72
  73         /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
  74         /* WaFbcWakeMemOn:skl,bxt,kbl */
  75         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
  76                    DISP_FBC_WM_DIS |
  77                    DISP_FBC_MEMORY_WAKE);
  78
  79         /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
  80         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  81                    ILK_DPFC_DISABLE_DUMMY0);
  82 }
  83
  84 static void bxt_init_clock_gating(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = to_i915(dev);
  87
  88         gen9_init_clock_gating(dev);
  89
  90         /* WaDisableSDEUnitClockGating:bxt */
  91         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  92                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  93
  94         /*
  95          * FIXME:
  96          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  97          */
  98         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  99                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 100
 101         /*
 102          * Wa: Backlight PWM may stop in the asserted state, causing backlight
 103          * to stay fully on.
 104          */
 105         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
 106                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
 107                            PWM1_GATING_DIS | PWM2_GATING_DIS);
 108 }
 109
 110 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 111 {
 112         struct drm_i915_private *dev_priv = to_i915(dev);
 113         u32 tmp;
 114
 115         tmp = I915_READ(CLKCFG);
 116
 117         switch (tmp & CLKCFG_FSB_MASK) {
 118         case CLKCFG_FSB_533:
 119                 dev_priv->fsb_freq = 533; /* 133*4 */
 120                 break;
 121         case CLKCFG_FSB_800:
 122                 dev_priv->fsb_freq = 800; /* 200*4 */
 123                 break;
 124         case CLKCFG_FSB_667:
 125                 dev_priv->fsb_freq =  667; /* 167*4 */
 126                 break;
 127         case CLKCFG_FSB_400:
 128                 dev_priv->fsb_freq = 400; /* 100*4 */
 129                 break;
 130         }
 131
 132         switch (tmp & CLKCFG_MEM_MASK) {
 133         case CLKCFG_MEM_533:
 134                 dev_priv->mem_freq = 533;
 135                 break;
 136         case CLKCFG_MEM_667:
 137                 dev_priv->mem_freq = 667;
 138                 break;
 139         case CLKCFG_MEM_800:
 140                 dev_priv->mem_freq = 800;
 141                 break;
 142         }
 143
 144         /* detect pineview DDR3 setting */
 145         tmp = I915_READ(CSHRDDR3CTL);
 146         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 147 }
 148
 149 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 150 {
 151         struct drm_i915_private *dev_priv = to_i915(dev);
 152         u16 ddrpll, csipll;
 153
 154         ddrpll = I915_READ16(DDRMPLL1);
 155         csipll = I915_READ16(CSIPLL0);
 156
 157         switch (ddrpll & 0xff) {
 158         case 0xc:
 159                 dev_priv->mem_freq = 800;
 160                 break;
 161         case 0x10:
 162                 dev_priv->mem_freq = 1066;
 163                 break;
 164         case 0x14:
 165                 dev_priv->mem_freq = 1333;
 166                 break;
 167         case 0x18:
 168                 dev_priv->mem_freq = 1600;
 169                 break;
 170         default:
 171                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 172                                  ddrpll & 0xff);
 173                 dev_priv->mem_freq = 0;
 174                 break;
 175         }
 176
 177         dev_priv->ips.r_t = dev_priv->mem_freq;
 178
 179         switch (csipll & 0x3ff) {
 180         case 0x00c:
 181                 dev_priv->fsb_freq = 3200;
 182                 break;
 183         case 0x00e:
 184                 dev_priv->fsb_freq = 3733;
 185                 break;
 186         case 0x010:
 187                 dev_priv->fsb_freq = 4266;
 188                 break;
 189         case 0x012:
 190                 dev_priv->fsb_freq = 4800;
 191                 break;
 192         case 0x014:
 193                 dev_priv->fsb_freq = 5333;
 194                 break;
 195         case 0x016:
 196                 dev_priv->fsb_freq = 5866;
 197                 break;
 198         case 0x018:
 199                 dev_priv->fsb_freq = 6400;
 200                 break;
 201         default:
 202                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 203                                  csipll & 0x3ff);
 204                 dev_priv->fsb_freq = 0;
 205                 break;
 206         }
 207
 208         if (dev_priv->fsb_freq == 3200) {
 209                 dev_priv->ips.c_m = 0;
 210         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 211                 dev_priv->ips.c_m = 1;
 212         } else {
 213                 dev_priv->ips.c_m = 2;
 214         }
 215 }
 216
 217 static const struct cxsr_latency cxsr_latency_table[] = {
 218         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 219         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 220         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 221         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 222         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 223
 224         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 225         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 226         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 227         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 228         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 229
 230         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 231         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 232         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 233         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 234         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 235
 236         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 237         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 238         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 239         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 240         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 241
 242         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 243         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 244         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 245         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 246         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 247
 248         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 249         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 250         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 251         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 252         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 253 };
 254
 255 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 256                                                          int is_ddr3,
 257                                                          int fsb,
 258                                                          int mem)
 259 {
 260         const struct cxsr_latency *latency;
 261         int i;
 262
 263         if (fsb == 0 || mem == 0)
 264                 return NULL;
 265
 266         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 267                 latency = &cxsr_latency_table[i];
 268                 if (is_desktop == latency->is_desktop &&
 269                     is_ddr3 == latency->is_ddr3 &&
 270                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 271                         return latency;
 272         }
 273
 274         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 275
 276         return NULL;
 277 }
 278
 279 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 280 {
 281         u32 val;
 282
 283         mutex_lock(&dev_priv->rps.hw_lock);
 284
 285         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 286         if (enable)
 287                 val &= ~FORCE_DDR_HIGH_FREQ;
 288         else
 289                 val |= FORCE_DDR_HIGH_FREQ;
 290         val &= ~FORCE_DDR_LOW_FREQ;
 291         val |= FORCE_DDR_FREQ_REQ_ACK;
 292         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 293
 294         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 295                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 296                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 297
 298         mutex_unlock(&dev_priv->rps.hw_lock);
 299 }
 300
 301 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 302 {
 303         u32 val;
 304
 305         mutex_lock(&dev_priv->rps.hw_lock);
 306
 307         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 308         if (enable)
 309                 val |= DSP_MAXFIFO_PM5_ENABLE;
 310         else
 311                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 312         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 313
 314         mutex_unlock(&dev_priv->rps.hw_lock);
 315 }
 316
 317 #define FW_WM(value, plane) \
 318         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 319
 320 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 321 {
 322         struct drm_device *dev = &dev_priv->drm;
 323         u32 val;
 324
 325         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 326                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 327                 POSTING_READ(FW_BLC_SELF_VLV);
 328                 dev_priv->wm.vlv.cxsr = enable;
 329         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 330                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 331                 POSTING_READ(FW_BLC_SELF);
 332         } else if (IS_PINEVIEW(dev)) {
 333                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 334                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 335                 I915_WRITE(DSPFW3, val);
 336                 POSTING_READ(DSPFW3);
 337         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 338                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 339                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 340                 I915_WRITE(FW_BLC_SELF, val);
 341                 POSTING_READ(FW_BLC_SELF);
 342         } else if (IS_I915GM(dev)) {
 343                 /*
 344                  * FIXME can't find a bit like this for 915G, and
 345                  * and yet it does have the related watermark in
 346                  * FW_BLC_SELF. What's going on?
 347                  */
 348                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 349                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 350                 I915_WRITE(INSTPM, val);
 351                 POSTING_READ(INSTPM);
 352         } else {
 353                 return;
 354         }
 355
 356         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 357                       enable ? "enabled" : "disabled");
 358 }
 359
 360
 361 /*
 362  * Latency for FIFO fetches is dependent on several factors:
 363  *   - memory configuration (speed, channels)
 364  *   - chipset
 365  *   - current MCH state
 366  * It can be fairly high in some situations, so here we assume a fairly
 367  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 368  * set this value too high, the FIFO will fetch frequently to stay full)
 369  * and power consumption (set it too low to save power and we might see
 370  * FIFO underruns and display "flicker").
 371  *
 372  * A value of 5us seems to be a good balance; safe for very low end
 373  * platforms but not overly aggressive on lower latency configs.
 374  */
 375 static const int pessimal_latency_ns = 5000;
 376
 377 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 378         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 379
 380 static int vlv_get_fifo_size(struct drm_device *dev,
 381                               enum pipe pipe, int plane)
 382 {
 383         struct drm_i915_private *dev_priv = to_i915(dev);
 384         int sprite0_start, sprite1_start, size;
 385
 386         switch (pipe) {
 387                 uint32_t dsparb, dsparb2, dsparb3;
 388         case PIPE_A:
 389                 dsparb = I915_READ(DSPARB);
 390                 dsparb2 = I915_READ(DSPARB2);
 391                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 392                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 393                 break;
 394         case PIPE_B:
 395                 dsparb = I915_READ(DSPARB);
 396                 dsparb2 = I915_READ(DSPARB2);
 397                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 398                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 399                 break;
 400         case PIPE_C:
 401                 dsparb2 = I915_READ(DSPARB2);
 402                 dsparb3 = I915_READ(DSPARB3);
 403                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 404                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 405                 break;
 406         default:
 407                 return 0;
 408         }
 409
 410         switch (plane) {
 411         case 0:
 412                 size = sprite0_start;
 413                 break;
 414         case 1:
 415                 size = sprite1_start - sprite0_start;
 416                 break;
 417         case 2:
 418                 size = 512 - 1 - sprite1_start;
 419                 break;
 420         default:
 421                 return 0;
 422         }
 423
 424         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 425                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 426                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 427                       size);
 428
 429         return size;
 430 }
 431
 432 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 433 {
 434         struct drm_i915_private *dev_priv = to_i915(dev);
 435         uint32_t dsparb = I915_READ(DSPARB);
 436         int size;
 437
 438         size = dsparb & 0x7f;
 439         if (plane)
 440                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 441
 442         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 443                       plane ? "B" : "A", size);
 444
 445         return size;
 446 }
 447
 448 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 449 {
 450         struct drm_i915_private *dev_priv = to_i915(dev);
 451         uint32_t dsparb = I915_READ(DSPARB);
 452         int size;
 453
 454         size = dsparb & 0x1ff;
 455         if (plane)
 456                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 457         size >>= 1; /* Convert to cachelines */
 458
 459         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 460                       plane ? "B" : "A", size);
 461
 462         return size;
 463 }
 464
 465 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 466 {
 467         struct drm_i915_private *dev_priv = to_i915(dev);
 468         uint32_t dsparb = I915_READ(DSPARB);
 469         int size;
 470
 471         size = dsparb & 0x7f;
 472         size >>= 2; /* Convert to cachelines */
 473
 474         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 475                       plane ? "B" : "A",
 476                       size);
 477
 478         return size;
 479 }
 480
 481 /* Pineview has different values for various configs */
 482 static const struct intel_watermark_params pineview_display_wm = {
 483         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 484         .max_wm = PINEVIEW_MAX_WM,
 485         .default_wm = PINEVIEW_DFT_WM,
 486         .guard_size = PINEVIEW_GUARD_WM,
 487         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 488 };
 489 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 490         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 491         .max_wm = PINEVIEW_MAX_WM,
 492         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 493         .guard_size = PINEVIEW_GUARD_WM,
 494         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 495 };
 496 static const struct intel_watermark_params pineview_cursor_wm = {
 497         .fifo_size = PINEVIEW_CURSOR_FIFO,
 498         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 499         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 500         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 501         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 502 };
 503 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 504         .fifo_size = PINEVIEW_CURSOR_FIFO,
 505         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 506         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 507         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 508         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 509 };
 510 static const struct intel_watermark_params g4x_wm_info = {
 511         .fifo_size = G4X_FIFO_SIZE,
 512         .max_wm = G4X_MAX_WM,
 513         .default_wm = G4X_MAX_WM,
 514         .guard_size = 2,
 515         .cacheline_size = G4X_FIFO_LINE_SIZE,
 516 };
 517 static const struct intel_watermark_params g4x_cursor_wm_info = {
 518         .fifo_size = I965_CURSOR_FIFO,
 519         .max_wm = I965_CURSOR_MAX_WM,
 520         .default_wm = I965_CURSOR_DFT_WM,
 521         .guard_size = 2,
 522         .cacheline_size = G4X_FIFO_LINE_SIZE,
 523 };
 524 static const struct intel_watermark_params i965_cursor_wm_info = {
 525         .fifo_size = I965_CURSOR_FIFO,
 526         .max_wm = I965_CURSOR_MAX_WM,
 527         .default_wm = I965_CURSOR_DFT_WM,
 528         .guard_size = 2,
 529         .cacheline_size = I915_FIFO_LINE_SIZE,
 530 };
 531 static const struct intel_watermark_params i945_wm_info = {
 532         .fifo_size = I945_FIFO_SIZE,
 533         .max_wm = I915_MAX_WM,
 534         .default_wm = 1,
 535         .guard_size = 2,
 536         .cacheline_size = I915_FIFO_LINE_SIZE,
 537 };
 538 static const struct intel_watermark_params i915_wm_info = {
 539         .fifo_size = I915_FIFO_SIZE,
 540         .max_wm = I915_MAX_WM,
 541         .default_wm = 1,
 542         .guard_size = 2,
 543         .cacheline_size = I915_FIFO_LINE_SIZE,
 544 };
 545 static const struct intel_watermark_params i830_a_wm_info = {
 546         .fifo_size = I855GM_FIFO_SIZE,
 547         .max_wm = I915_MAX_WM,
 548         .default_wm = 1,
 549         .guard_size = 2,
 550         .cacheline_size = I830_FIFO_LINE_SIZE,
 551 };
 552 static const struct intel_watermark_params i830_bc_wm_info = {
 553         .fifo_size = I855GM_FIFO_SIZE,
 554         .max_wm = I915_MAX_WM/2,
 555         .default_wm = 1,
 556         .guard_size = 2,
 557         .cacheline_size = I830_FIFO_LINE_SIZE,
 558 };
 559 static const struct intel_watermark_params i845_wm_info = {
 560         .fifo_size = I830_FIFO_SIZE,
 561         .max_wm = I915_MAX_WM,
 562         .default_wm = 1,
 563         .guard_size = 2,
 564         .cacheline_size = I830_FIFO_LINE_SIZE,
 565 };
 566
 567 /**
 568  * intel_calculate_wm - calculate watermark level
 569  * @clock_in_khz: pixel clock
 570  * @wm: chip FIFO params
 571  * @cpp: bytes per pixel
 572  * @latency_ns: memory latency for the platform
 573  *
 574  * Calculate the watermark level (the level at which the display plane will
 575  * start fetching from memory again).  Each chip has a different display
 576  * FIFO size and allocation, so the caller needs to figure that out and pass
 577  * in the correct intel_watermark_params structure.
 578  *
 579  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 580  * on the pixel size.  When it reaches the watermark level, it'll start
 581  * fetching FIFO line sized based chunks from memory until the FIFO fills
 582  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 583  * will occur, and a display engine hang could result.
 584  */
 585 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 586                                         const struct intel_watermark_params *wm,
 587                                         int fifo_size, int cpp,
 588                                         unsigned long latency_ns)
 589 {
 590         long entries_required, wm_size;
 591
 592         /*
 593          * Note: we need to make sure we don't overflow for various clock &
 594          * latency values.
 595          * clocks go from a few thousand to several hundred thousand.
 596          * latency is usually a few thousand
 597          */
 598         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 599                 1000;
 600         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 601
 602         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 603
 604         wm_size = fifo_size - (entries_required + wm->guard_size);
 605
 606         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 607
 608         /* Don't promote wm_size to unsigned... */
 609         if (wm_size > (long)wm->max_wm)
 610                 wm_size = wm->max_wm;
 611         if (wm_size <= 0)
 612                 wm_size = wm->default_wm;
 613
 614         /*
 615          * Bspec seems to indicate that the value shouldn't be lower than
 616          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 617          * Lets go for 8 which is the burst size since certain platforms
 618          * already use a hardcoded 8 (which is what the spec says should be
 619          * done).
 620          */
 621         if (wm_size <= 8)
 622                 wm_size = 8;
 623
 624         return wm_size;
 625 }
 626
 627 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 628 {
 629         struct drm_crtc *crtc, *enabled = NULL;
 630
 631         for_each_crtc(dev, crtc) {
 632                 if (intel_crtc_active(crtc)) {
 633                         if (enabled)
 634                                 return NULL;
 635                         enabled = crtc;
 636                 }
 637         }
 638
 639         return enabled;
 640 }
 641
 642 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 643 {
 644         struct drm_device *dev = unused_crtc->dev;
 645         struct drm_i915_private *dev_priv = to_i915(dev);
 646         struct drm_crtc *crtc;
 647         const struct cxsr_latency *latency;
 648         u32 reg;
 649         unsigned long wm;
 650
 651         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 652                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 653         if (!latency) {
 654                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 655                 intel_set_memory_cxsr(dev_priv, false);
 656                 return;
 657         }
 658
 659         crtc = single_enabled_crtc(dev);
 660         if (crtc) {
 661                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 662                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 663                 int clock = adjusted_mode->crtc_clock;
 664
 665                 /* Display SR */
 666                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 667                                         pineview_display_wm.fifo_size,
 668                                         cpp, latency->display_sr);
 669                 reg = I915_READ(DSPFW1);
 670                 reg &= ~DSPFW_SR_MASK;
 671                 reg |= FW_WM(wm, SR);
 672                 I915_WRITE(DSPFW1, reg);
 673                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 674
 675                 /* cursor SR */
 676                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 677                                         pineview_display_wm.fifo_size,
 678                                         cpp, latency->cursor_sr);
 679                 reg = I915_READ(DSPFW3);
 680                 reg &= ~DSPFW_CURSOR_SR_MASK;
 681                 reg |= FW_WM(wm, CURSOR_SR);
 682                 I915_WRITE(DSPFW3, reg);
 683
 684                 /* Display HPLL off SR */
 685                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 686                                         pineview_display_hplloff_wm.fifo_size,
 687                                         cpp, latency->display_hpll_disable);
 688                 reg = I915_READ(DSPFW3);
 689                 reg &= ~DSPFW_HPLL_SR_MASK;
 690                 reg |= FW_WM(wm, HPLL_SR);
 691                 I915_WRITE(DSPFW3, reg);
 692
 693                 /* cursor HPLL off SR */
 694                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 695                                         pineview_display_hplloff_wm.fifo_size,
 696                                         cpp, latency->cursor_hpll_disable);
 697                 reg = I915_READ(DSPFW3);
 698                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 699                 reg |= FW_WM(wm, HPLL_CURSOR);
 700                 I915_WRITE(DSPFW3, reg);
 701                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 702
 703                 intel_set_memory_cxsr(dev_priv, true);
 704         } else {
 705                 intel_set_memory_cxsr(dev_priv, false);
 706         }
 707 }
 708
 709 static bool g4x_compute_wm0(struct drm_device *dev,
 710                             int plane,
 711                             const struct intel_watermark_params *display,
 712                             int display_latency_ns,
 713                             const struct intel_watermark_params *cursor,
 714                             int cursor_latency_ns,
 715                             int *plane_wm,
 716                             int *cursor_wm)
 717 {
 718         struct drm_crtc *crtc;
 719         const struct drm_display_mode *adjusted_mode;
 720         int htotal, hdisplay, clock, cpp;
 721         int line_time_us, line_count;
 722         int entries, tlb_miss;
 723
 724         crtc = intel_get_crtc_for_plane(dev, plane);
 725         if (!intel_crtc_active(crtc)) {
 726                 *cursor_wm = cursor->guard_size;
 727                 *plane_wm = display->guard_size;
 728                 return false;
 729         }
 730
 731         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 732         clock = adjusted_mode->crtc_clock;
 733         htotal = adjusted_mode->crtc_htotal;
 734         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 735         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 736
 737         /* Use the small buffer method to calculate plane watermark */
 738         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 739         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 740         if (tlb_miss > 0)
 741                 entries += tlb_miss;
 742         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 743         *plane_wm = entries + display->guard_size;
 744         if (*plane_wm > (int)display->max_wm)
 745                 *plane_wm = display->max_wm;
 746
 747         /* Use the large buffer method to calculate cursor watermark */
 748         line_time_us = max(htotal * 1000 / clock, 1);
 749         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 750         entries = line_count * crtc->cursor->state->crtc_w * cpp;
 751         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 752         if (tlb_miss > 0)
 753                 entries += tlb_miss;
 754         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 755         *cursor_wm = entries + cursor->guard_size;
 756         if (*cursor_wm > (int)cursor->max_wm)
 757                 *cursor_wm = (int)cursor->max_wm;
 758
 759         return true;
 760 }
 761
 762 /*
 763  * Check the wm result.
 764  *
 765  * If any calculated watermark values is larger than the maximum value that
 766  * can be programmed into the associated watermark register, that watermark
 767  * must be disabled.
 768  */
 769 static bool g4x_check_srwm(struct drm_device *dev,
 770                            int display_wm, int cursor_wm,
 771                            const struct intel_watermark_params *display,
 772                            const struct intel_watermark_params *cursor)
 773 {
 774         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 775                       display_wm, cursor_wm);
 776
 777         if (display_wm > display->max_wm) {
 778                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 779                               display_wm, display->max_wm);
 780                 return false;
 781         }
 782
 783         if (cursor_wm > cursor->max_wm) {
 784                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 785                               cursor_wm, cursor->max_wm);
 786                 return false;
 787         }
 788
 789         if (!(display_wm || cursor_wm)) {
 790                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 791                 return false;
 792         }
 793
 794         return true;
 795 }
 796
 797 static bool g4x_compute_srwm(struct drm_device *dev,
 798                              int plane,
 799                              int latency_ns,
 800                              const struct intel_watermark_params *display,
 801                              const struct intel_watermark_params *cursor,
 802                              int *display_wm, int *cursor_wm)
 803 {
 804         struct drm_crtc *crtc;
 805         const struct drm_display_mode *adjusted_mode;
 806         int hdisplay, htotal, cpp, clock;
 807         unsigned long line_time_us;
 808         int line_count, line_size;
 809         int small, large;
 810         int entries;
 811
 812         if (!latency_ns) {
 813                 *display_wm = *cursor_wm = 0;
 814                 return false;
 815         }
 816
 817         crtc = intel_get_crtc_for_plane(dev, plane);
 818         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 819         clock = adjusted_mode->crtc_clock;
 820         htotal = adjusted_mode->crtc_htotal;
 821         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 822         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 823
 824         line_time_us = max(htotal * 1000 / clock, 1);
 825         line_count = (latency_ns / line_time_us + 1000) / 1000;
 826         line_size = hdisplay * cpp;
 827
 828         /* Use the minimum of the small and large buffer method for primary */
 829         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 830         large = line_count * line_size;
 831
 832         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 833         *display_wm = entries + display->guard_size;
 834
 835         /* calculate the self-refresh watermark for display cursor */
 836         entries = line_count * cpp * crtc->cursor->state->crtc_w;
 837         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 838         *cursor_wm = entries + cursor->guard_size;
 839
 840         return g4x_check_srwm(dev,
 841                               *display_wm, *cursor_wm,
 842                               display, cursor);
 843 }
 844
 845 #define FW_WM_VLV(value, plane) \
 846         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 847
 848 static void vlv_write_wm_values(struct intel_crtc *crtc,
 849                                 const struct vlv_wm_values *wm)
 850 {
 851         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 852         enum pipe pipe = crtc->pipe;
 853
 854         I915_WRITE(VLV_DDL(pipe),
 855                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 856                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 857                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 858                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 859
 860         I915_WRITE(DSPFW1,
 861                    FW_WM(wm->sr.plane, SR) |
 862                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 863                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 864                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 865         I915_WRITE(DSPFW2,
 866                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 867                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 868                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 869         I915_WRITE(DSPFW3,
 870                    FW_WM(wm->sr.cursor, CURSOR_SR));
 871
 872         if (IS_CHERRYVIEW(dev_priv)) {
 873                 I915_WRITE(DSPFW7_CHV,
 874                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 875                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 876                 I915_WRITE(DSPFW8_CHV,
 877                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 878                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 879                 I915_WRITE(DSPFW9_CHV,
 880                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 881                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 882                 I915_WRITE(DSPHOWM,
 883                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 884                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 885                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 886                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 887                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 888                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 889                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 890                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 891                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 892                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 893         } else {
 894                 I915_WRITE(DSPFW7,
 895                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 896                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 897                 I915_WRITE(DSPHOWM,
 898                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 899                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 900                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 901                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 902                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 903                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 904                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 905         }
 906
 907         /* zero (unused) WM1 watermarks */
 908         I915_WRITE(DSPFW4, 0);
 909         I915_WRITE(DSPFW5, 0);
 910         I915_WRITE(DSPFW6, 0);
 911         I915_WRITE(DSPHOWM1, 0);
 912
 913         POSTING_READ(DSPFW1);
 914 }
 915
 916 #undef FW_WM_VLV
 917
 918 enum vlv_wm_level {
 919         VLV_WM_LEVEL_PM2,
 920         VLV_WM_LEVEL_PM5,
 921         VLV_WM_LEVEL_DDR_DVFS,
 922 };
 923
 924 /* latency must be in 0.1us units. */
 925 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 926                                    unsigned int pipe_htotal,
 927                                    unsigned int horiz_pixels,
 928                                    unsigned int cpp,
 929                                    unsigned int latency)
 930 {
 931         unsigned int ret;
 932
 933         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 934         ret = (ret + 1) * horiz_pixels * cpp;
 935         ret = DIV_ROUND_UP(ret, 64);
 936
 937         return ret;
 938 }
 939
 940 static void vlv_setup_wm_latency(struct drm_device *dev)
 941 {
 942         struct drm_i915_private *dev_priv = to_i915(dev);
 943
 944         /* all latencies in usec */
 945         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 946
 947         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 948
 949         if (IS_CHERRYVIEW(dev_priv)) {
 950                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 951                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 952
 953                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 954         }
 955 }
 956
 957 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 958                                      struct intel_crtc *crtc,
 959                                      const struct intel_plane_state *state,
 960                                      int level)
 961 {
 962         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 963         int clock, htotal, cpp, width, wm;
 964
 965         if (dev_priv->wm.pri_latency[level] == 0)
 966                 return USHRT_MAX;
 967
 968         if (!state->base.visible)
 969                 return 0;
 970
 971         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 972         clock = crtc->config->base.adjusted_mode.crtc_clock;
 973         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 974         width = crtc->config->pipe_src_w;
 975         if (WARN_ON(htotal == 0))
 976                 htotal = 1;
 977
 978         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 979                 /*
 980                  * FIXME the formula gives values that are
 981                  * too big for the cursor FIFO, and hence we
 982                  * would never be able to use cursors. For
 983                  * now just hardcode the watermark.
 984                  */
 985                 wm = 63;
 986         } else {
 987                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 988                                     dev_priv->wm.pri_latency[level] * 10);
 989         }
 990
 991         return min_t(int, wm, USHRT_MAX);
 992 }
 993
 994 static void vlv_compute_fifo(struct intel_crtc *crtc)
 995 {
 996         struct drm_device *dev = crtc->base.dev;
 997         struct vlv_wm_state *wm_state = &crtc->wm_state;
 998         struct intel_plane *plane;
 999         unsigned int total_rate = 0;
1000         const int fifo_size = 512 - 1;
1001         int fifo_extra, fifo_left = fifo_size;
1002
1003         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1004                 struct intel_plane_state *state =
1005                         to_intel_plane_state(plane->base.state);
1006
1007                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1008                         continue;
1009
1010                 if (state->base.visible) {
1011                         wm_state->num_active_planes++;
1012                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013                 }
1014         }
1015
1016         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1017                 struct intel_plane_state *state =
1018                         to_intel_plane_state(plane->base.state);
1019                 unsigned int rate;
1020
1021                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1022                         plane->wm.fifo_size = 63;
1023                         continue;
1024                 }
1025
1026                 if (!state->base.visible) {
1027                         plane->wm.fifo_size = 0;
1028                         continue;
1029                 }
1030
1031                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1032                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1033                 fifo_left -= plane->wm.fifo_size;
1034         }
1035
1036         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1037
1038         /* spread the remainder evenly */
1039         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1040                 int plane_extra;
1041
1042                 if (fifo_left == 0)
1043                         break;
1044
1045                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1046                         continue;
1047
1048                 /* give it all to the first plane if none are active */
1049                 if (plane->wm.fifo_size == 0 &&
1050                     wm_state->num_active_planes)
1051                         continue;
1052
1053                 plane_extra = min(fifo_extra, fifo_left);
1054                 plane->wm.fifo_size += plane_extra;
1055                 fifo_left -= plane_extra;
1056         }
1057
1058         WARN_ON(fifo_left != 0);
1059 }
1060
1061 static void vlv_invert_wms(struct intel_crtc *crtc)
1062 {
1063         struct vlv_wm_state *wm_state = &crtc->wm_state;
1064         int level;
1065
1066         for (level = 0; level < wm_state->num_levels; level++) {
1067                 struct drm_device *dev = crtc->base.dev;
1068                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1069                 struct intel_plane *plane;
1070
1071                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1072                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1073
1074                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1075                         switch (plane->base.type) {
1076                                 int sprite;
1077                         case DRM_PLANE_TYPE_CURSOR:
1078                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1079                                         wm_state->wm[level].cursor;
1080                                 break;
1081                         case DRM_PLANE_TYPE_PRIMARY:
1082                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1083                                         wm_state->wm[level].primary;
1084                                 break;
1085                         case DRM_PLANE_TYPE_OVERLAY:
1086                                 sprite = plane->plane;
1087                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1088                                         wm_state->wm[level].sprite[sprite];
1089                                 break;
1090                         }
1091                 }
1092         }
1093 }
1094
1095 static void vlv_compute_wm(struct intel_crtc *crtc)
1096 {
1097         struct drm_device *dev = crtc->base.dev;
1098         struct vlv_wm_state *wm_state = &crtc->wm_state;
1099         struct intel_plane *plane;
1100         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1101         int level;
1102
1103         memset(wm_state, 0, sizeof(*wm_state));
1104
1105         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1106         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1107
1108         wm_state->num_active_planes = 0;
1109
1110         vlv_compute_fifo(crtc);
1111
1112         if (wm_state->num_active_planes != 1)
1113                 wm_state->cxsr = false;
1114
1115         if (wm_state->cxsr) {
1116                 for (level = 0; level < wm_state->num_levels; level++) {
1117                         wm_state->sr[level].plane = sr_fifo_size;
1118                         wm_state->sr[level].cursor = 63;
1119                 }
1120         }
1121
1122         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1123                 struct intel_plane_state *state =
1124                         to_intel_plane_state(plane->base.state);
1125
1126                 if (!state->base.visible)
1127                         continue;
1128
1129                 /* normal watermarks */
1130                 for (level = 0; level < wm_state->num_levels; level++) {
1131                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1132                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1133
1134                         /* hack */
1135                         if (WARN_ON(level == 0 && wm > max_wm))
1136                                 wm = max_wm;
1137
1138                         if (wm > plane->wm.fifo_size)
1139                                 break;
1140
1141                         switch (plane->base.type) {
1142                                 int sprite;
1143                         case DRM_PLANE_TYPE_CURSOR:
1144                                 wm_state->wm[level].cursor = wm;
1145                                 break;
1146                         case DRM_PLANE_TYPE_PRIMARY:
1147                                 wm_state->wm[level].primary = wm;
1148                                 break;
1149                         case DRM_PLANE_TYPE_OVERLAY:
1150                                 sprite = plane->plane;
1151                                 wm_state->wm[level].sprite[sprite] = wm;
1152                                 break;
1153                         }
1154                 }
1155
1156                 wm_state->num_levels = level;
1157
1158                 if (!wm_state->cxsr)
1159                         continue;
1160
1161                 /* maxfifo watermarks */
1162                 switch (plane->base.type) {
1163                         int sprite, level;
1164                 case DRM_PLANE_TYPE_CURSOR:
1165                         for (level = 0; level < wm_state->num_levels; level++)
1166                                 wm_state->sr[level].cursor =
1167                                         wm_state->wm[level].cursor;
1168                         break;
1169                 case DRM_PLANE_TYPE_PRIMARY:
1170                         for (level = 0; level < wm_state->num_levels; level++)
1171                                 wm_state->sr[level].plane =
1172                                         min(wm_state->sr[level].plane,
1173                                             wm_state->wm[level].primary);
1174                         break;
1175                 case DRM_PLANE_TYPE_OVERLAY:
1176                         sprite = plane->plane;
1177                         for (level = 0; level < wm_state->num_levels; level++)
1178                                 wm_state->sr[level].plane =
1179                                         min(wm_state->sr[level].plane,
1180                                             wm_state->wm[level].sprite[sprite]);
1181                         break;
1182                 }
1183         }
1184
1185         /* clear any (partially) filled invalid levels */
1186         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1187                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1188                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1189         }
1190
1191         vlv_invert_wms(crtc);
1192 }
1193
1194 #define VLV_FIFO(plane, value) \
1195         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1196
1197 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1198 {
1199         struct drm_device *dev = crtc->base.dev;
1200         struct drm_i915_private *dev_priv = to_i915(dev);
1201         struct intel_plane *plane;
1202         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1203
1204         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1205                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1206                         WARN_ON(plane->wm.fifo_size != 63);
1207                         continue;
1208                 }
1209
1210                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1211                         sprite0_start = plane->wm.fifo_size;
1212                 else if (plane->plane == 0)
1213                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1214                 else
1215                         fifo_size = sprite1_start + plane->wm.fifo_size;
1216         }
1217
1218         WARN_ON(fifo_size != 512 - 1);
1219
1220         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1221                       pipe_name(crtc->pipe), sprite0_start,
1222                       sprite1_start, fifo_size);
1223
1224         switch (crtc->pipe) {
1225                 uint32_t dsparb, dsparb2, dsparb3;
1226         case PIPE_A:
1227                 dsparb = I915_READ(DSPARB);
1228                 dsparb2 = I915_READ(DSPARB2);
1229
1230                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1231                             VLV_FIFO(SPRITEB, 0xff));
1232                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1233                            VLV_FIFO(SPRITEB, sprite1_start));
1234
1235                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1236                              VLV_FIFO(SPRITEB_HI, 0x1));
1237                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1238                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1239
1240                 I915_WRITE(DSPARB, dsparb);
1241                 I915_WRITE(DSPARB2, dsparb2);
1242                 break;
1243         case PIPE_B:
1244                 dsparb = I915_READ(DSPARB);
1245                 dsparb2 = I915_READ(DSPARB2);
1246
1247                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1248                             VLV_FIFO(SPRITED, 0xff));
1249                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1250                            VLV_FIFO(SPRITED, sprite1_start));
1251
1252                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1253                              VLV_FIFO(SPRITED_HI, 0xff));
1254                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1255                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1256
1257                 I915_WRITE(DSPARB, dsparb);
1258                 I915_WRITE(DSPARB2, dsparb2);
1259                 break;
1260         case PIPE_C:
1261                 dsparb3 = I915_READ(DSPARB3);
1262                 dsparb2 = I915_READ(DSPARB2);
1263
1264                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1265                              VLV_FIFO(SPRITEF, 0xff));
1266                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1267                             VLV_FIFO(SPRITEF, sprite1_start));
1268
1269                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1270                              VLV_FIFO(SPRITEF_HI, 0xff));
1271                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1272                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1273
1274                 I915_WRITE(DSPARB3, dsparb3);
1275                 I915_WRITE(DSPARB2, dsparb2);
1276                 break;
1277         default:
1278                 break;
1279         }
1280 }
1281
1282 #undef VLV_FIFO
1283
1284 static void vlv_merge_wm(struct drm_device *dev,
1285                          struct vlv_wm_values *wm)
1286 {
1287         struct intel_crtc *crtc;
1288         int num_active_crtcs = 0;
1289
1290         wm->level = to_i915(dev)->wm.max_level;
1291         wm->cxsr = true;
1292
1293         for_each_intel_crtc(dev, crtc) {
1294                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1295
1296                 if (!crtc->active)
1297                         continue;
1298
1299                 if (!wm_state->cxsr)
1300                         wm->cxsr = false;
1301
1302                 num_active_crtcs++;
1303                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1304         }
1305
1306         if (num_active_crtcs != 1)
1307                 wm->cxsr = false;
1308
1309         if (num_active_crtcs > 1)
1310                 wm->level = VLV_WM_LEVEL_PM2;
1311
1312         for_each_intel_crtc(dev, crtc) {
1313                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1314                 enum pipe pipe = crtc->pipe;
1315
1316                 if (!crtc->active)
1317                         continue;
1318
1319                 wm->pipe[pipe] = wm_state->wm[wm->level];
1320                 if (wm->cxsr)
1321                         wm->sr = wm_state->sr[wm->level];
1322
1323                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1324                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1325                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1326                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1327         }
1328 }
1329
1330 static void vlv_update_wm(struct drm_crtc *crtc)
1331 {
1332         struct drm_device *dev = crtc->dev;
1333         struct drm_i915_private *dev_priv = to_i915(dev);
1334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1335         enum pipe pipe = intel_crtc->pipe;
1336         struct vlv_wm_values wm = {};
1337
1338         vlv_compute_wm(intel_crtc);
1339         vlv_merge_wm(dev, &wm);
1340
1341         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1342                 /* FIXME should be part of crtc atomic commit */
1343                 vlv_pipe_set_fifo_size(intel_crtc);
1344                 return;
1345         }
1346
1347         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1348             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1349                 chv_set_memory_dvfs(dev_priv, false);
1350
1351         if (wm.level < VLV_WM_LEVEL_PM5 &&
1352             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1353                 chv_set_memory_pm5(dev_priv, false);
1354
1355         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1356                 intel_set_memory_cxsr(dev_priv, false);
1357
1358         /* FIXME should be part of crtc atomic commit */
1359         vlv_pipe_set_fifo_size(intel_crtc);
1360
1361         vlv_write_wm_values(intel_crtc, &wm);
1362
1363         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1364                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1365                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1366                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1367                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1368
1369         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1370                 intel_set_memory_cxsr(dev_priv, true);
1371
1372         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1373             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1374                 chv_set_memory_pm5(dev_priv, true);
1375
1376         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1377             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1378                 chv_set_memory_dvfs(dev_priv, true);
1379
1380         dev_priv->wm.vlv = wm;
1381 }
1382
1383 #define single_plane_enabled(mask) is_power_of_2(mask)
1384
1385 static void g4x_update_wm(struct drm_crtc *crtc)
1386 {
1387         struct drm_device *dev = crtc->dev;
1388         static const int sr_latency_ns = 12000;
1389         struct drm_i915_private *dev_priv = to_i915(dev);
1390         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1391         int plane_sr, cursor_sr;
1392         unsigned int enabled = 0;
1393         bool cxsr_enabled;
1394
1395         if (g4x_compute_wm0(dev, PIPE_A,
1396                             &g4x_wm_info, pessimal_latency_ns,
1397                             &g4x_cursor_wm_info, pessimal_latency_ns,
1398                             &planea_wm, &cursora_wm))
1399                 enabled |= 1 << PIPE_A;
1400
1401         if (g4x_compute_wm0(dev, PIPE_B,
1402                             &g4x_wm_info, pessimal_latency_ns,
1403                             &g4x_cursor_wm_info, pessimal_latency_ns,
1404                             &planeb_wm, &cursorb_wm))
1405                 enabled |= 1 << PIPE_B;
1406
1407         if (single_plane_enabled(enabled) &&
1408             g4x_compute_srwm(dev, ffs(enabled) - 1,
1409                              sr_latency_ns,
1410                              &g4x_wm_info,
1411                              &g4x_cursor_wm_info,
1412                              &plane_sr, &cursor_sr)) {
1413                 cxsr_enabled = true;
1414         } else {
1415                 cxsr_enabled = false;
1416                 intel_set_memory_cxsr(dev_priv, false);
1417                 plane_sr = cursor_sr = 0;
1418         }
1419
1420         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1421                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1422                       planea_wm, cursora_wm,
1423                       planeb_wm, cursorb_wm,
1424                       plane_sr, cursor_sr);
1425
1426         I915_WRITE(DSPFW1,
1427                    FW_WM(plane_sr, SR) |
1428                    FW_WM(cursorb_wm, CURSORB) |
1429                    FW_WM(planeb_wm, PLANEB) |
1430                    FW_WM(planea_wm, PLANEA));
1431         I915_WRITE(DSPFW2,
1432                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1433                    FW_WM(cursora_wm, CURSORA));
1434         /* HPLL off in SR has some issues on G4x... disable it */
1435         I915_WRITE(DSPFW3,
1436                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1437                    FW_WM(cursor_sr, CURSOR_SR));
1438
1439         if (cxsr_enabled)
1440                 intel_set_memory_cxsr(dev_priv, true);
1441 }
1442
1443 static void i965_update_wm(struct drm_crtc *unused_crtc)
1444 {
1445         struct drm_device *dev = unused_crtc->dev;
1446         struct drm_i915_private *dev_priv = to_i915(dev);
1447         struct drm_crtc *crtc;
1448         int srwm = 1;
1449         int cursor_sr = 16;
1450         bool cxsr_enabled;
1451
1452         /* Calc sr entries for one plane configs */
1453         crtc = single_enabled_crtc(dev);
1454         if (crtc) {
1455                 /* self-refresh has much higher latency */
1456                 static const int sr_latency_ns = 12000;
1457                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1458                 int clock = adjusted_mode->crtc_clock;
1459                 int htotal = adjusted_mode->crtc_htotal;
1460                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1461                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1462                 unsigned long line_time_us;
1463                 int entries;
1464
1465                 line_time_us = max(htotal * 1000 / clock, 1);
1466
1467                 /* Use ns/us then divide to preserve precision */
1468                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1469                         cpp * hdisplay;
1470                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1471                 srwm = I965_FIFO_SIZE - entries;
1472                 if (srwm < 0)
1473                         srwm = 1;
1474                 srwm &= 0x1ff;
1475                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1476                               entries, srwm);
1477
1478                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1479                         cpp * crtc->cursor->state->crtc_w;
1480                 entries = DIV_ROUND_UP(entries,
1481                                           i965_cursor_wm_info.cacheline_size);
1482                 cursor_sr = i965_cursor_wm_info.fifo_size -
1483                         (entries + i965_cursor_wm_info.guard_size);
1484
1485                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1486                         cursor_sr = i965_cursor_wm_info.max_wm;
1487
1488                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1489                               "cursor %d\n", srwm, cursor_sr);
1490
1491                 cxsr_enabled = true;
1492         } else {
1493                 cxsr_enabled = false;
1494                 /* Turn off self refresh if both pipes are enabled */
1495                 intel_set_memory_cxsr(dev_priv, false);
1496         }
1497
1498         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1499                       srwm);
1500
1501         /* 965 has limitations... */
1502         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1503                    FW_WM(8, CURSORB) |
1504                    FW_WM(8, PLANEB) |
1505                    FW_WM(8, PLANEA));
1506         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1507                    FW_WM(8, PLANEC_OLD));
1508         /* update cursor SR watermark */
1509         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1510
1511         if (cxsr_enabled)
1512                 intel_set_memory_cxsr(dev_priv, true);
1513 }
1514
1515 #undef FW_WM
1516
1517 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1518 {
1519         struct drm_device *dev = unused_crtc->dev;
1520         struct drm_i915_private *dev_priv = to_i915(dev);
1521         const struct intel_watermark_params *wm_info;
1522         uint32_t fwater_lo;
1523         uint32_t fwater_hi;
1524         int cwm, srwm = 1;
1525         int fifo_size;
1526         int planea_wm, planeb_wm;
1527         struct drm_crtc *crtc, *enabled = NULL;
1528
1529         if (IS_I945GM(dev))
1530                 wm_info = &i945_wm_info;
1531         else if (!IS_GEN2(dev))
1532                 wm_info = &i915_wm_info;
1533         else
1534                 wm_info = &i830_a_wm_info;
1535
1536         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1537         crtc = intel_get_crtc_for_plane(dev, 0);
1538         if (intel_crtc_active(crtc)) {
1539                 const struct drm_display_mode *adjusted_mode;
1540                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1541                 if (IS_GEN2(dev))
1542                         cpp = 4;
1543
1544                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1545                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1546                                                wm_info, fifo_size, cpp,
1547                                                pessimal_latency_ns);
1548                 enabled = crtc;
1549         } else {
1550                 planea_wm = fifo_size - wm_info->guard_size;
1551                 if (planea_wm > (long)wm_info->max_wm)
1552                         planea_wm = wm_info->max_wm;
1553         }
1554
1555         if (IS_GEN2(dev))
1556                 wm_info = &i830_bc_wm_info;
1557
1558         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1559         crtc = intel_get_crtc_for_plane(dev, 1);
1560         if (intel_crtc_active(crtc)) {
1561                 const struct drm_display_mode *adjusted_mode;
1562                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1563                 if (IS_GEN2(dev))
1564                         cpp = 4;
1565
1566                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1567                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1568                                                wm_info, fifo_size, cpp,
1569                                                pessimal_latency_ns);
1570                 if (enabled == NULL)
1571                         enabled = crtc;
1572                 else
1573                         enabled = NULL;
1574         } else {
1575                 planeb_wm = fifo_size - wm_info->guard_size;
1576                 if (planeb_wm > (long)wm_info->max_wm)
1577                         planeb_wm = wm_info->max_wm;
1578         }
1579
1580         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1581
1582         if (IS_I915GM(dev) && enabled) {
1583                 struct drm_i915_gem_object *obj;
1584
1585                 obj = intel_fb_obj(enabled->primary->state->fb);
1586
1587                 /* self-refresh seems busted with untiled */
1588                 if (!i915_gem_object_is_tiled(obj))
1589                         enabled = NULL;
1590         }
1591
1592         /*
1593          * Overlay gets an aggressive default since video jitter is bad.
1594          */
1595         cwm = 2;
1596
1597         /* Play safe and disable self-refresh before adjusting watermarks. */
1598         intel_set_memory_cxsr(dev_priv, false);
1599
1600         /* Calc sr entries for one plane configs */
1601         if (HAS_FW_BLC(dev) && enabled) {
1602                 /* self-refresh has much higher latency */
1603                 static const int sr_latency_ns = 6000;
1604                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1605                 int clock = adjusted_mode->crtc_clock;
1606                 int htotal = adjusted_mode->crtc_htotal;
1607                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1608                 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1609                 unsigned long line_time_us;
1610                 int entries;
1611
1612                 if (IS_I915GM(dev) || IS_I945GM(dev))
1613                         cpp = 4;
1614
1615                 line_time_us = max(htotal * 1000 / clock, 1);
1616
1617                 /* Use ns/us then divide to preserve precision */
1618                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1619                         cpp * hdisplay;
1620                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1621                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1622                 srwm = wm_info->fifo_size - entries;
1623                 if (srwm < 0)
1624                         srwm = 1;
1625
1626                 if (IS_I945G(dev) || IS_I945GM(dev))
1627                         I915_WRITE(FW_BLC_SELF,
1628                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1629                 else
1630                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1631         }
1632
1633         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1634                       planea_wm, planeb_wm, cwm, srwm);
1635
1636         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1637         fwater_hi = (cwm & 0x1f);
1638
1639         /* Set request length to 8 cachelines per fetch */
1640         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1641         fwater_hi = fwater_hi | (1 << 8);
1642
1643         I915_WRITE(FW_BLC, fwater_lo);
1644         I915_WRITE(FW_BLC2, fwater_hi);
1645
1646         if (enabled)
1647                 intel_set_memory_cxsr(dev_priv, true);
1648 }
1649
1650 static void i845_update_wm(struct drm_crtc *unused_crtc)
1651 {
1652         struct drm_device *dev = unused_crtc->dev;
1653         struct drm_i915_private *dev_priv = to_i915(dev);
1654         struct drm_crtc *crtc;
1655         const struct drm_display_mode *adjusted_mode;
1656         uint32_t fwater_lo;
1657         int planea_wm;
1658
1659         crtc = single_enabled_crtc(dev);
1660         if (crtc == NULL)
1661                 return;
1662
1663         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1664         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1665                                        &i845_wm_info,
1666                                        dev_priv->display.get_fifo_size(dev, 0),
1667                                        4, pessimal_latency_ns);
1668         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1669         fwater_lo |= (3<<8) | planea_wm;
1670
1671         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1672
1673         I915_WRITE(FW_BLC, fwater_lo);
1674 }
1675
1676 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1677 {
1678         uint32_t pixel_rate;
1679
1680         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1681
1682         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1683          * adjust the pixel_rate here. */
1684
1685         if (pipe_config->pch_pfit.enabled) {
1686                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1687                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1688
1689                 pipe_w = pipe_config->pipe_src_w;
1690                 pipe_h = pipe_config->pipe_src_h;
1691
1692                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1693                 pfit_h = pfit_size & 0xFFFF;
1694                 if (pipe_w < pfit_w)
1695                         pipe_w = pfit_w;
1696                 if (pipe_h < pfit_h)
1697                         pipe_h = pfit_h;
1698
1699                 if (WARN_ON(!pfit_w || !pfit_h))
1700                         return pixel_rate;
1701
1702                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1703                                      pfit_w * pfit_h);
1704         }
1705
1706         return pixel_rate;
1707 }
1708
1709 /* latency must be in 0.1us units. */
1710 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1711 {
1712         uint64_t ret;
1713
1714         if (WARN(latency == 0, "Latency value missing\n"))
1715                 return UINT_MAX;
1716
1717         ret = (uint64_t) pixel_rate * cpp * latency;
1718         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1719
1720         return ret;
1721 }
1722
1723 /* latency must be in 0.1us units. */
1724 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1725                                uint32_t horiz_pixels, uint8_t cpp,
1726                                uint32_t latency)
1727 {
1728         uint32_t ret;
1729
1730         if (WARN(latency == 0, "Latency value missing\n"))
1731                 return UINT_MAX;
1732         if (WARN_ON(!pipe_htotal))
1733                 return UINT_MAX;
1734
1735         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1736         ret = (ret + 1) * horiz_pixels * cpp;
1737         ret = DIV_ROUND_UP(ret, 64) + 2;
1738         return ret;
1739 }
1740
1741 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1742                            uint8_t cpp)
1743 {
1744         /*
1745          * Neither of these should be possible since this function shouldn't be
1746          * called if the CRTC is off or the plane is invisible.  But let's be
1747          * extra paranoid to avoid a potential divide-by-zero if we screw up
1748          * elsewhere in the driver.
1749          */
1750         if (WARN_ON(!cpp))
1751                 return 0;
1752         if (WARN_ON(!horiz_pixels))
1753                 return 0;
1754
1755         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1756 }
1757
1758 struct ilk_wm_maximums {
1759         uint16_t pri;
1760         uint16_t spr;
1761         uint16_t cur;
1762         uint16_t fbc;
1763 };
1764
1765 /*
1766  * For both WM_PIPE and WM_LP.
1767  * mem_value must be in 0.1us units.
1768  */
1769 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1770                                    const struct intel_plane_state *pstate,
1771                                    uint32_t mem_value,
1772                                    bool is_lp)
1773 {
1774         int cpp = pstate->base.fb ?
1775                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1776         uint32_t method1, method2;
1777
1778         if (!cstate->base.active || !pstate->base.visible)
1779                 return 0;
1780
1781         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1782
1783         if (!is_lp)
1784                 return method1;
1785
1786         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1787                                  cstate->base.adjusted_mode.crtc_htotal,
1788                                  drm_rect_width(&pstate->base.dst),
1789                                  cpp, mem_value);
1790
1791         return min(method1, method2);
1792 }
1793
1794 /*
1795  * For both WM_PIPE and WM_LP.
1796  * mem_value must be in 0.1us units.
1797  */
1798 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1799                                    const struct intel_plane_state *pstate,
1800                                    uint32_t mem_value)
1801 {
1802         int cpp = pstate->base.fb ?
1803                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1804         uint32_t method1, method2;
1805
1806         if (!cstate->base.active || !pstate->base.visible)
1807                 return 0;
1808
1809         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1810         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1811                                  cstate->base.adjusted_mode.crtc_htotal,
1812                                  drm_rect_width(&pstate->base.dst),
1813                                  cpp, mem_value);
1814         return min(method1, method2);
1815 }
1816
1817 /*
1818  * For both WM_PIPE and WM_LP.
1819  * mem_value must be in 0.1us units.
1820  */
1821 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1822                                    const struct intel_plane_state *pstate,
1823                                    uint32_t mem_value)
1824 {
1825         /*
1826          * We treat the cursor plane as always-on for the purposes of watermark
1827          * calculation.  Until we have two-stage watermark programming merged,
1828          * this is necessary to avoid flickering.
1829          */
1830         int cpp = 4;
1831         int width = pstate->base.visible ? pstate->base.crtc_w : 64;
1832
1833         if (!cstate->base.active)
1834                 return 0;
1835
1836         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1837                               cstate->base.adjusted_mode.crtc_htotal,
1838                               width, cpp, mem_value);
1839 }
1840
1841 /* Only for WM_LP. */
1842 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1843                                    const struct intel_plane_state *pstate,
1844                                    uint32_t pri_val)
1845 {
1846         int cpp = pstate->base.fb ?
1847                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1848
1849         if (!cstate->base.active || !pstate->base.visible)
1850                 return 0;
1851
1852         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
1853 }
1854
1855 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1856 {
1857         if (INTEL_INFO(dev)->gen >= 8)
1858                 return 3072;
1859         else if (INTEL_INFO(dev)->gen >= 7)
1860                 return 768;
1861         else
1862                 return 512;
1863 }
1864
1865 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1866                                          int level, bool is_sprite)
1867 {
1868         if (INTEL_INFO(dev)->gen >= 8)
1869                 /* BDW primary/sprite plane watermarks */
1870                 return level == 0 ? 255 : 2047;
1871         else if (INTEL_INFO(dev)->gen >= 7)
1872                 /* IVB/HSW primary/sprite plane watermarks */
1873                 return level == 0 ? 127 : 1023;
1874         else if (!is_sprite)
1875                 /* ILK/SNB primary plane watermarks */
1876                 return level == 0 ? 127 : 511;
1877         else
1878                 /* ILK/SNB sprite plane watermarks */
1879                 return level == 0 ? 63 : 255;
1880 }
1881
1882 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1883                                           int level)
1884 {
1885         if (INTEL_INFO(dev)->gen >= 7)
1886                 return level == 0 ? 63 : 255;
1887         else
1888                 return level == 0 ? 31 : 63;
1889 }
1890
1891 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1892 {
1893         if (INTEL_INFO(dev)->gen >= 8)
1894                 return 31;
1895         else
1896                 return 15;
1897 }
1898
1899 /* Calculate the maximum primary/sprite plane watermark */
1900 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1901                                      int level,
1902                                      const struct intel_wm_config *config,
1903                                      enum intel_ddb_partitioning ddb_partitioning,
1904                                      bool is_sprite)
1905 {
1906         unsigned int fifo_size = ilk_display_fifo_size(dev);
1907
1908         /* if sprites aren't enabled, sprites get nothing */
1909         if (is_sprite && !config->sprites_enabled)
1910                 return 0;
1911
1912         /* HSW allows LP1+ watermarks even with multiple pipes */
1913         if (level == 0 || config->num_pipes_active > 1) {
1914                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1915
1916                 /*
1917                  * For some reason the non self refresh
1918                  * FIFO size is only half of the self
1919                  * refresh FIFO size on ILK/SNB.
1920                  */
1921                 if (INTEL_INFO(dev)->gen <= 6)
1922                         fifo_size /= 2;
1923         }
1924
1925         if (config->sprites_enabled) {
1926                 /* level 0 is always calculated with 1:1 split */
1927                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1928                         if (is_sprite)
1929                                 fifo_size *= 5;
1930                         fifo_size /= 6;
1931                 } else {
1932                         fifo_size /= 2;
1933                 }
1934         }
1935
1936         /* clamp to max that the registers can hold */
1937         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1938 }
1939
1940 /* Calculate the maximum cursor plane watermark */
1941 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1942                                       int level,
1943                                       const struct intel_wm_config *config)
1944 {
1945         /* HSW LP1+ watermarks w/ multiple pipes */
1946         if (level > 0 && config->num_pipes_active > 1)
1947                 return 64;
1948
1949         /* otherwise just report max that registers can hold */
1950         return ilk_cursor_wm_reg_max(dev, level);
1951 }
1952
1953 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1954                                     int level,
1955                                     const struct intel_wm_config *config,
1956                                     enum intel_ddb_partitioning ddb_partitioning,
1957                                     struct ilk_wm_maximums *max)
1958 {
1959         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1960         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1961         max->cur = ilk_cursor_wm_max(dev, level, config);
1962         max->fbc = ilk_fbc_wm_reg_max(dev);
1963 }
1964
1965 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1966                                         int level,
1967                                         struct ilk_wm_maximums *max)
1968 {
1969         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1970         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1971         max->cur = ilk_cursor_wm_reg_max(dev, level);
1972         max->fbc = ilk_fbc_wm_reg_max(dev);
1973 }
1974
1975 static bool ilk_validate_wm_level(int level,
1976                                   const struct ilk_wm_maximums *max,
1977                                   struct intel_wm_level *result)
1978 {
1979         bool ret;
1980
1981         /* already determined to be invalid? */
1982         if (!result->enable)
1983                 return false;
1984
1985         result->enable = result->pri_val <= max->pri &&
1986                          result->spr_val <= max->spr &&
1987                          result->cur_val <= max->cur;
1988
1989         ret = result->enable;
1990
1991         /*
1992          * HACK until we can pre-compute everything,
1993          * and thus fail gracefully if LP0 watermarks
1994          * are exceeded...
1995          */
1996         if (level == 0 && !result->enable) {
1997                 if (result->pri_val > max->pri)
1998                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1999                                       level, result->pri_val, max->pri);
2000                 if (result->spr_val > max->spr)
2001                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2002                                       level, result->spr_val, max->spr);
2003                 if (result->cur_val > max->cur)
2004                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2005                                       level, result->cur_val, max->cur);
2006
2007                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2008                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2009                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2010                 result->enable = true;
2011         }
2012
2013         return ret;
2014 }
2015
2016 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
2017                                  const struct intel_crtc *intel_crtc,
2018                                  int level,
2019                                  struct intel_crtc_state *cstate,
2020                                  struct intel_plane_state *pristate,
2021                                  struct intel_plane_state *sprstate,
2022                                  struct intel_plane_state *curstate,
2023                                  struct intel_wm_level *result)
2024 {
2025         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2026         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2027         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2028
2029         /* WM1+ latency values stored in 0.5us units */
2030         if (level > 0) {
2031                 pri_latency *= 5;
2032                 spr_latency *= 5;
2033                 cur_latency *= 5;
2034         }
2035
2036         if (pristate) {
2037                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2038                                                      pri_latency, level);
2039                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2040         }
2041
2042         if (sprstate)
2043                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2044
2045         if (curstate)
2046                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2047
2048         result->enable = true;
2049 }
2050
2051 static uint32_t
2052 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
2053 {
2054         const struct intel_atomic_state *intel_state =
2055                 to_intel_atomic_state(cstate->base.state);
2056         const struct drm_display_mode *adjusted_mode =
2057                 &cstate->base.adjusted_mode;
2058         u32 linetime, ips_linetime;
2059
2060         if (!cstate->base.active)
2061                 return 0;
2062         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2063                 return 0;
2064         if (WARN_ON(intel_state->cdclk == 0))
2065                 return 0;
2066
2067         /* The WM are computed with base on how long it takes to fill a single
2068          * row at the given clock rate, multiplied by 8.
2069          * */
2070         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2071                                      adjusted_mode->crtc_clock);
2072         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2073                                          intel_state->cdclk);
2074
2075         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2076                PIPE_WM_LINETIME_TIME(linetime);
2077 }
2078
2079 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2080 {
2081         struct drm_i915_private *dev_priv = to_i915(dev);
2082
2083         if (IS_GEN9(dev)) {
2084                 uint32_t val;
2085                 int ret, i;
2086                 int level, max_level = ilk_wm_max_level(dev);
2087
2088                 /* read the first set of memory latencies[0:3] */
2089                 val = 0; /* data0 to be programmed to 0 for first set */
2090                 mutex_lock(&dev_priv->rps.hw_lock);
2091                 ret = sandybridge_pcode_read(dev_priv,
2092                                              GEN9_PCODE_READ_MEM_LATENCY,
2093                                              &val);
2094                 mutex_unlock(&dev_priv->rps.hw_lock);
2095
2096                 if (ret) {
2097                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2098                         return;
2099                 }
2100
2101                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2102                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2103                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2104                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2105                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2106                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2107                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2108
2109                 /* read the second set of memory latencies[4:7] */
2110                 val = 1; /* data0 to be programmed to 1 for second set */
2111                 mutex_lock(&dev_priv->rps.hw_lock);
2112                 ret = sandybridge_pcode_read(dev_priv,
2113                                              GEN9_PCODE_READ_MEM_LATENCY,
2114                                              &val);
2115                 mutex_unlock(&dev_priv->rps.hw_lock);
2116                 if (ret) {
2117                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2118                         return;
2119                 }
2120
2121                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2122                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2123                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2124                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2125                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2126                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2127                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2128
2129                 /*
2130                  * WaWmMemoryReadLatency:skl
2131                  *
2132                  * punit doesn't take into account the read latency so we need
2133                  * to add 2us to the various latency levels we retrieve from
2134                  * the punit.
2135                  *   - W0 is a bit special in that it's the only level that
2136                  *   can't be disabled if we want to have display working, so
2137                  *   we always add 2us there.
2138                  *   - For levels >=1, punit returns 0us latency when they are
2139                  *   disabled, so we respect that and don't add 2us then
2140                  *
2141                  * Additionally, if a level n (n > 1) has a 0us latency, all
2142                  * levels m (m >= n) need to be disabled. We make sure to
2143                  * sanitize the values out of the punit to satisfy this
2144                  * requirement.
2145                  */
2146                 wm[0] += 2;
2147                 for (level = 1; level <= max_level; level++)
2148                         if (wm[level] != 0)
2149                                 wm[level] += 2;
2150                         else {
2151                                 for (i = level + 1; i <= max_level; i++)
2152                                         wm[i] = 0;
2153
2154                                 break;
2155                         }
2156         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2157                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2158
2159                 wm[0] = (sskpd >> 56) & 0xFF;
2160                 if (wm[0] == 0)
2161                         wm[0] = sskpd & 0xF;
2162                 wm[1] = (sskpd >> 4) & 0xFF;
2163                 wm[2] = (sskpd >> 12) & 0xFF;
2164                 wm[3] = (sskpd >> 20) & 0x1FF;
2165                 wm[4] = (sskpd >> 32) & 0x1FF;
2166         } else if (INTEL_INFO(dev)->gen >= 6) {
2167                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2168
2169                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2170                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2171                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2172                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2173         } else if (INTEL_INFO(dev)->gen >= 5) {
2174                 uint32_t mltr = I915_READ(MLTR_ILK);
2175
2176                 /* ILK primary LP0 latency is 700 ns */
2177                 wm[0] = 7;
2178                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2179                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2180         }
2181 }
2182
2183 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2184 {
2185         /* ILK sprite LP0 latency is 1300 ns */
2186         if (IS_GEN5(dev))
2187                 wm[0] = 13;
2188 }
2189
2190 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2191 {
2192         /* ILK cursor LP0 latency is 1300 ns */
2193         if (IS_GEN5(dev))
2194                 wm[0] = 13;
2195
2196         /* WaDoubleCursorLP3Latency:ivb */
2197         if (IS_IVYBRIDGE(dev))
2198                 wm[3] *= 2;
2199 }
2200
2201 int ilk_wm_max_level(const struct drm_device *dev)
2202 {
2203         /* how many WM levels are we expecting */
2204         if (INTEL_INFO(dev)->gen >= 9)
2205                 return 7;
2206         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2207                 return 4;
2208         else if (INTEL_INFO(dev)->gen >= 6)
2209                 return 3;
2210         else
2211                 return 2;
2212 }
2213
2214 static void intel_print_wm_latency(struct drm_device *dev,
2215                                    const char *name,
2216                                    const uint16_t wm[8])
2217 {
2218         int level, max_level = ilk_wm_max_level(dev);
2219
2220         for (level = 0; level <= max_level; level++) {
2221                 unsigned int latency = wm[level];
2222
2223                 if (latency == 0) {
2224                         DRM_ERROR("%s WM%d latency not provided\n",
2225                                   name, level);
2226                         continue;
2227                 }
2228
2229                 /*
2230                  * - latencies are in us on gen9.
2231                  * - before then, WM1+ latency values are in 0.5us units
2232                  */
2233                 if (IS_GEN9(dev))
2234                         latency *= 10;
2235                 else if (level > 0)
2236                         latency *= 5;
2237
2238                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2239                               name, level, wm[level],
2240                               latency / 10, latency % 10);
2241         }
2242 }
2243
2244 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2245                                     uint16_t wm[5], uint16_t min)
2246 {
2247         int level, max_level = ilk_wm_max_level(&dev_priv->drm);
2248
2249         if (wm[0] >= min)
2250                 return false;
2251
2252         wm[0] = max(wm[0], min);
2253         for (level = 1; level <= max_level; level++)
2254                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2255
2256         return true;
2257 }
2258
2259 static void snb_wm_latency_quirk(struct drm_device *dev)
2260 {
2261         struct drm_i915_private *dev_priv = to_i915(dev);
2262         bool changed;
2263
2264         /*
2265          * The BIOS provided WM memory latency values are often
2266          * inadequate for high resolution displays. Adjust them.
2267          */
2268         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2269                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2270                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2271
2272         if (!changed)
2273                 return;
2274
2275         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2276         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2277         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2278         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2279 }
2280
2281 static void ilk_setup_wm_latency(struct drm_device *dev)
2282 {
2283         struct drm_i915_private *dev_priv = to_i915(dev);
2284
2285         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2286
2287         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2288                sizeof(dev_priv->wm.pri_latency));
2289         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2290                sizeof(dev_priv->wm.pri_latency));
2291
2292         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2293         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2294
2295         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2296         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2297         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2298
2299         if (IS_GEN6(dev))
2300                 snb_wm_latency_quirk(dev);
2301 }
2302
2303 static void skl_setup_wm_latency(struct drm_device *dev)
2304 {
2305         struct drm_i915_private *dev_priv = to_i915(dev);
2306
2307         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2308         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2309 }
2310
2311 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2312                                  struct intel_pipe_wm *pipe_wm)
2313 {
2314         /* LP0 watermark maximums depend on this pipe alone */
2315         const struct intel_wm_config config = {
2316                 .num_pipes_active = 1,
2317                 .sprites_enabled = pipe_wm->sprites_enabled,
2318                 .sprites_scaled = pipe_wm->sprites_scaled,
2319         };
2320         struct ilk_wm_maximums max;
2321
2322         /* LP0 watermarks always use 1/2 DDB partitioning */
2323         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2324
2325         /* At least LP0 must be valid */
2326         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2327                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2328                 return false;
2329         }
2330
2331         return true;
2332 }
2333
2334 /* Compute new watermarks for the pipe */
2335 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2336 {
2337         struct drm_atomic_state *state = cstate->base.state;
2338         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2339         struct intel_pipe_wm *pipe_wm;
2340         struct drm_device *dev = state->dev;
2341         const struct drm_i915_private *dev_priv = to_i915(dev);
2342         struct intel_plane *intel_plane;
2343         struct intel_plane_state *pristate = NULL;
2344         struct intel_plane_state *sprstate = NULL;
2345         struct intel_plane_state *curstate = NULL;
2346         int level, max_level = ilk_wm_max_level(dev), usable_level;
2347         struct ilk_wm_maximums max;
2348
2349         pipe_wm = &cstate->wm.ilk.optimal;
2350
2351         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2352                 struct intel_plane_state *ps;
2353
2354                 ps = intel_atomic_get_existing_plane_state(state,
2355                                                            intel_plane);
2356                 if (!ps)
2357                         continue;
2358
2359                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2360                         pristate = ps;
2361                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2362                         sprstate = ps;
2363                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2364                         curstate = ps;
2365         }
2366
2367         pipe_wm->pipe_enabled = cstate->base.active;
2368         if (sprstate) {
2369                 pipe_wm->sprites_enabled = sprstate->base.visible;
2370                 pipe_wm->sprites_scaled = sprstate->base.visible &&
2371                         (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2372                          drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
2373         }
2374
2375         usable_level = max_level;
2376
2377         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2378         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2379                 usable_level = 1;
2380
2381         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2382         if (pipe_wm->sprites_scaled)
2383                 usable_level = 0;
2384
2385         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2386                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2387
2388         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2389         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2390
2391         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2392                 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
2393
2394         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2395                 return -EINVAL;
2396
2397         ilk_compute_wm_reg_maximums(dev, 1, &max);
2398
2399         for (level = 1; level <= max_level; level++) {
2400                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2401
2402                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2403                                      pristate, sprstate, curstate, wm);
2404
2405                 /*
2406                  * Disable any watermark level that exceeds the
2407                  * register maximums since such watermarks are
2408                  * always invalid.
2409                  */
2410                 if (level > usable_level)
2411                         continue;
2412
2413                 if (ilk_validate_wm_level(level, &max, wm))
2414                         pipe_wm->wm[level] = *wm;
2415                 else
2416                         usable_level = level;
2417         }
2418
2419         return 0;
2420 }
2421
2422 /*
2423  * Build a set of 'intermediate' watermark values that satisfy both the old
2424  * state and the new state.  These can be programmed to the hardware
2425  * immediately.
2426  */
2427 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2428                                        struct intel_crtc *intel_crtc,
2429                                        struct intel_crtc_state *newstate)
2430 {
2431         struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
2432         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2433         int level, max_level = ilk_wm_max_level(dev);
2434
2435         /*
2436          * Start with the final, target watermarks, then combine with the
2437          * currently active watermarks to get values that are safe both before
2438          * and after the vblank.
2439          */
2440         *a = newstate->wm.ilk.optimal;
2441         a->pipe_enabled |= b->pipe_enabled;
2442         a->sprites_enabled |= b->sprites_enabled;
2443         a->sprites_scaled |= b->sprites_scaled;
2444
2445         for (level = 0; level <= max_level; level++) {
2446                 struct intel_wm_level *a_wm = &a->wm[level];
2447                 const struct intel_wm_level *b_wm = &b->wm[level];
2448
2449                 a_wm->enable &= b_wm->enable;
2450                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2451                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2452                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2453                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2454         }
2455
2456         /*
2457          * We need to make sure that these merged watermark values are
2458          * actually a valid configuration themselves.  If they're not,
2459          * there's no safe way to transition from the old state to
2460          * the new state, so we need to fail the atomic transaction.
2461          */
2462         if (!ilk_validate_pipe_wm(dev, a))
2463                 return -EINVAL;
2464
2465         /*
2466          * If our intermediate WM are identical to the final WM, then we can
2467          * omit the post-vblank programming; only update if it's different.
2468          */
2469         if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
2470                 newstate->wm.need_postvbl_update = false;
2471
2472         return 0;
2473 }
2474
2475 /*
2476  * Merge the watermarks from all active pipes for a specific level.
2477  */
2478 static void ilk_merge_wm_level(struct drm_device *dev,
2479                                int level,
2480                                struct intel_wm_level *ret_wm)
2481 {
2482         const struct intel_crtc *intel_crtc;
2483
2484         ret_wm->enable = true;
2485
2486         for_each_intel_crtc(dev, intel_crtc) {
2487                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2488                 const struct intel_wm_level *wm = &active->wm[level];
2489
2490                 if (!active->pipe_enabled)
2491                         continue;
2492
2493                 /*
2494                  * The watermark values may have been used in the past,
2495                  * so we must maintain them in the registers for some
2496                  * time even if the level is now disabled.
2497                  */
2498                 if (!wm->enable)
2499                         ret_wm->enable = false;
2500
2501                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2502                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2503                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2504                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2505         }
2506 }
2507
2508 /*
2509  * Merge all low power watermarks for all active pipes.
2510  */
2511 static void ilk_wm_merge(struct drm_device *dev,
2512                          const struct intel_wm_config *config,
2513                          const struct ilk_wm_maximums *max,
2514                          struct intel_pipe_wm *merged)
2515 {
2516         struct drm_i915_private *dev_priv = to_i915(dev);
2517         int level, max_level = ilk_wm_max_level(dev);
2518         int last_enabled_level = max_level;
2519
2520         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2521         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2522             config->num_pipes_active > 1)
2523                 last_enabled_level = 0;
2524
2525         /* ILK: FBC WM must be disabled always */
2526         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2527
2528         /* merge each WM1+ level */
2529         for (level = 1; level <= max_level; level++) {
2530                 struct intel_wm_level *wm = &merged->wm[level];
2531
2532                 ilk_merge_wm_level(dev, level, wm);
2533
2534                 if (level > last_enabled_level)
2535                         wm->enable = false;
2536                 else if (!ilk_validate_wm_level(level, max, wm))
2537                         /* make sure all following levels get disabled */
2538                         last_enabled_level = level - 1;
2539
2540                 /*
2541                  * The spec says it is preferred to disable
2542                  * FBC WMs instead of disabling a WM level.
2543                  */
2544                 if (wm->fbc_val > max->fbc) {
2545                         if (wm->enable)
2546                                 merged->fbc_wm_enabled = false;
2547                         wm->fbc_val = 0;
2548                 }
2549         }
2550
2551         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2552         /*
2553          * FIXME this is racy. FBC might get enabled later.
2554          * What we should check here is whether FBC can be
2555          * enabled sometime later.
2556          */
2557         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2558             intel_fbc_is_active(dev_priv)) {
2559                 for (level = 2; level <= max_level; level++) {
2560                         struct intel_wm_level *wm = &merged->wm[level];
2561
2562                         wm->enable = false;
2563                 }
2564         }
2565 }
2566
2567 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2568 {
2569         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2570         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2571 }
2572
2573 /* The value we need to program into the WM_LPx latency field */
2574 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2575 {
2576         struct drm_i915_private *dev_priv = to_i915(dev);
2577
2578         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2579                 return 2 * level;
2580         else
2581                 return dev_priv->wm.pri_latency[level];
2582 }
2583
2584 static void ilk_compute_wm_results(struct drm_device *dev,
2585                                    const struct intel_pipe_wm *merged,
2586                                    enum intel_ddb_partitioning partitioning,
2587                                    struct ilk_wm_values *results)
2588 {
2589         struct intel_crtc *intel_crtc;
2590         int level, wm_lp;
2591
2592         results->enable_fbc_wm = merged->fbc_wm_enabled;
2593         results->partitioning = partitioning;
2594
2595         /* LP1+ register values */
2596         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2597                 const struct intel_wm_level *r;
2598
2599                 level = ilk_wm_lp_to_level(wm_lp, merged);
2600
2601                 r = &merged->wm[level];
2602
2603                 /*
2604                  * Maintain the watermark values even if the level is
2605                  * disabled. Doing otherwise could cause underruns.
2606                  */
2607                 results->wm_lp[wm_lp - 1] =
2608                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2609                         (r->pri_val << WM1_LP_SR_SHIFT) |
2610                         r->cur_val;
2611
2612                 if (r->enable)
2613                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2614
2615                 if (INTEL_INFO(dev)->gen >= 8)
2616                         results->wm_lp[wm_lp - 1] |=
2617                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2618                 else
2619                         results->wm_lp[wm_lp - 1] |=
2620                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2621
2622                 /*
2623                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2624                  * level is disabled. Doing otherwise could cause underruns.
2625                  */
2626                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2627                         WARN_ON(wm_lp != 1);
2628                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2629                 } else
2630                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2631         }
2632
2633         /* LP0 register values */
2634         for_each_intel_crtc(dev, intel_crtc) {
2635                 enum pipe pipe = intel_crtc->pipe;
2636                 const struct intel_wm_level *r =
2637                         &intel_crtc->wm.active.ilk.wm[0];
2638
2639                 if (WARN_ON(!r->enable))
2640                         continue;
2641
2642                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2643
2644                 results->wm_pipe[pipe] =
2645                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2646                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2647                         r->cur_val;
2648         }
2649 }
2650
2651 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2652  * case both are at the same level. Prefer r1 in case they're the same. */
2653 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2654                                                   struct intel_pipe_wm *r1,
2655                                                   struct intel_pipe_wm *r2)
2656 {
2657         int level, max_level = ilk_wm_max_level(dev);
2658         int level1 = 0, level2 = 0;
2659
2660         for (level = 1; level <= max_level; level++) {
2661                 if (r1->wm[level].enable)
2662                         level1 = level;
2663                 if (r2->wm[level].enable)
2664                         level2 = level;
2665         }
2666
2667         if (level1 == level2) {
2668                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2669                         return r2;
2670                 else
2671                         return r1;
2672         } else if (level1 > level2) {
2673                 return r1;
2674         } else {
2675                 return r2;
2676         }
2677 }
2678
2679 /* dirty bits used to track which watermarks need changes */
2680 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2681 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2682 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2683 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2684 #define WM_DIRTY_FBC (1 << 24)
2685 #define WM_DIRTY_DDB (1 << 25)
2686
2687 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2688                                          const struct ilk_wm_values *old,
2689                                          const struct ilk_wm_values *new)
2690 {
2691         unsigned int dirty = 0;
2692         enum pipe pipe;
2693         int wm_lp;
2694
2695         for_each_pipe(dev_priv, pipe) {
2696                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2697                         dirty |= WM_DIRTY_LINETIME(pipe);
2698                         /* Must disable LP1+ watermarks too */
2699                         dirty |= WM_DIRTY_LP_ALL;
2700                 }
2701
2702                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2703                         dirty |= WM_DIRTY_PIPE(pipe);
2704                         /* Must disable LP1+ watermarks too */
2705                         dirty |= WM_DIRTY_LP_ALL;
2706                 }
2707         }
2708
2709         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2710                 dirty |= WM_DIRTY_FBC;
2711                 /* Must disable LP1+ watermarks too */
2712                 dirty |= WM_DIRTY_LP_ALL;
2713         }
2714
2715         if (old->partitioning != new->partitioning) {
2716                 dirty |= WM_DIRTY_DDB;
2717                 /* Must disable LP1+ watermarks too */
2718                 dirty |= WM_DIRTY_LP_ALL;
2719         }
2720
2721         /* LP1+ watermarks already deemed dirty, no need to continue */
2722         if (dirty & WM_DIRTY_LP_ALL)
2723                 return dirty;
2724
2725         /* Find the lowest numbered LP1+ watermark in need of an update... */
2726         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2727                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2728                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2729                         break;
2730         }
2731
2732         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2733         for (; wm_lp <= 3; wm_lp++)
2734                 dirty |= WM_DIRTY_LP(wm_lp);
2735
2736         return dirty;
2737 }
2738
2739 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2740                                unsigned int dirty)
2741 {
2742         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2743         bool changed = false;
2744
2745         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2746                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2747                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2748                 changed = true;
2749         }
2750         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2751                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2752                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2753                 changed = true;
2754         }
2755         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2756                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2757                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2758                 changed = true;
2759         }
2760
2761         /*
2762          * Don't touch WM1S_LP_EN here.
2763          * Doing so could cause underruns.
2764          */
2765
2766         return changed;
2767 }
2768
2769 /*
2770  * The spec says we shouldn't write when we don't need, because every write
2771  * causes WMs to be re-evaluated, expending some power.
2772  */
2773 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2774                                 struct ilk_wm_values *results)
2775 {
2776         struct drm_device *dev = &dev_priv->drm;
2777         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2778         unsigned int dirty;
2779         uint32_t val;
2780
2781         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2782         if (!dirty)
2783                 return;
2784
2785         _ilk_disable_lp_wm(dev_priv, dirty);
2786
2787         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2788                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2789         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2790                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2791         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2792                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2793
2794         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2795                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2796         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2797                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2798         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2799                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2800
2801         if (dirty & WM_DIRTY_DDB) {
2802                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2803                         val = I915_READ(WM_MISC);
2804                         if (results->partitioning == INTEL_DDB_PART_1_2)
2805                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2806                         else
2807                                 val |= WM_MISC_DATA_PARTITION_5_6;
2808                         I915_WRITE(WM_MISC, val);
2809                 } else {
2810                         val = I915_READ(DISP_ARB_CTL2);
2811                         if (results->partitioning == INTEL_DDB_PART_1_2)
2812                                 val &= ~DISP_DATA_PARTITION_5_6;
2813                         else
2814                                 val |= DISP_DATA_PARTITION_5_6;
2815                         I915_WRITE(DISP_ARB_CTL2, val);
2816                 }
2817         }
2818
2819         if (dirty & WM_DIRTY_FBC) {
2820                 val = I915_READ(DISP_ARB_CTL);
2821                 if (results->enable_fbc_wm)
2822                         val &= ~DISP_FBC_WM_DIS;
2823                 else
2824                         val |= DISP_FBC_WM_DIS;
2825                 I915_WRITE(DISP_ARB_CTL, val);
2826         }
2827
2828         if (dirty & WM_DIRTY_LP(1) &&
2829             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2830                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2831
2832         if (INTEL_INFO(dev)->gen >= 7) {
2833                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2834                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2835                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2836                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2837         }
2838
2839         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2840                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2841         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2842                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2843         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2844                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2845
2846         dev_priv->wm.hw = *results;
2847 }
2848
2849 bool ilk_disable_lp_wm(struct drm_device *dev)
2850 {
2851         struct drm_i915_private *dev_priv = to_i915(dev);
2852
2853         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2854 }
2855
2856 #define SKL_SAGV_BLOCK_TIME     30 /* µs */
2857
2858 /*
2859  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2860  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2861  * other universal planes are in indices 1..n.  Note that this may leave unused
2862  * indices between the top "sprite" plane and the cursor.
2863  */
2864 static int
2865 skl_wm_plane_id(const struct intel_plane *plane)
2866 {
2867         switch (plane->base.type) {
2868         case DRM_PLANE_TYPE_PRIMARY:
2869                 return 0;
2870         case DRM_PLANE_TYPE_CURSOR:
2871                 return PLANE_CURSOR;
2872         case DRM_PLANE_TYPE_OVERLAY:
2873                 return plane->plane + 1;
2874         default:
2875                 MISSING_CASE(plane->base.type);
2876                 return plane->plane;
2877         }
2878 }
2879
2880 /*
2881  * SAGV dynamically adjusts the system agent voltage and clock frequencies
2882  * depending on power and performance requirements. The display engine access
2883  * to system memory is blocked during the adjustment time. Because of the
2884  * blocking time, having this enabled can cause full system hangs and/or pipe
2885  * underruns if we don't meet all of the following requirements:
2886  *
2887  *  - <= 1 pipe enabled
2888  *  - All planes can enable watermarks for latencies >= SAGV engine block time
2889  *  - We're not using an interlaced display configuration
2890  */
2891 int
2892 skl_enable_sagv(struct drm_i915_private *dev_priv)
2893 {
2894         int ret;
2895
2896         if (dev_priv->skl_sagv_status == I915_SKL_SAGV_NOT_CONTROLLED ||
2897             dev_priv->skl_sagv_status == I915_SKL_SAGV_ENABLED)
2898                 return 0;
2899
2900         DRM_DEBUG_KMS("Enabling the SAGV\n");
2901         mutex_lock(&dev_priv->rps.hw_lock);
2902
2903         ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2904                                       GEN9_SAGV_ENABLE);
2905
2906         /* We don't need to wait for the SAGV when enabling */
2907         mutex_unlock(&dev_priv->rps.hw_lock);
2908
2909         /*
2910          * Some skl systems, pre-release machines in particular,
2911          * don't actually have an SAGV.
2912          */
2913         if (ret == -ENXIO) {
2914                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2915                 dev_priv->skl_sagv_status = I915_SKL_SAGV_NOT_CONTROLLED;
2916                 return 0;
2917         } else if (ret < 0) {
2918                 DRM_ERROR("Failed to enable the SAGV\n");
2919                 return ret;
2920         }
2921
2922         dev_priv->skl_sagv_status = I915_SKL_SAGV_ENABLED;
2923         return 0;
2924 }
2925
2926 static int
2927 skl_do_sagv_disable(struct drm_i915_private *dev_priv)
2928 {
2929         int ret;
2930         uint32_t temp = GEN9_SAGV_DISABLE;
2931
2932         ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2933                                      &temp);
2934         if (ret)
2935                 return ret;
2936         else
2937                 return temp & GEN9_SAGV_IS_DISABLED;
2938 }
2939
2940 int
2941 skl_disable_sagv(struct drm_i915_private *dev_priv)
2942 {
2943         int ret, result;
2944
2945         if (dev_priv->skl_sagv_status == I915_SKL_SAGV_NOT_CONTROLLED ||
2946             dev_priv->skl_sagv_status == I915_SKL_SAGV_DISABLED)
2947                 return 0;
2948
2949         DRM_DEBUG_KMS("Disabling the SAGV\n");
2950         mutex_lock(&dev_priv->rps.hw_lock);
2951
2952         /* bspec says to keep retrying for at least 1 ms */
2953         ret = wait_for(result = skl_do_sagv_disable(dev_priv), 1);
2954         mutex_unlock(&dev_priv->rps.hw_lock);
2955
2956         if (ret == -ETIMEDOUT) {
2957                 DRM_ERROR("Request to disable SAGV timed out\n");
2958                 return -ETIMEDOUT;
2959         }
2960
2961         /*
2962          * Some skl systems, pre-release machines in particular,
2963          * don't actually have an SAGV.
2964          */
2965         if (result == -ENXIO) {
2966                 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
2967                 dev_priv->skl_sagv_status = I915_SKL_SAGV_NOT_CONTROLLED;
2968                 return 0;
2969         } else if (result < 0) {
2970                 DRM_ERROR("Failed to disable the SAGV\n");
2971                 return result;
2972         }
2973
2974         dev_priv->skl_sagv_status = I915_SKL_SAGV_DISABLED;
2975         return 0;
2976 }
2977
2978 bool skl_can_enable_sagv(struct drm_atomic_state *state)
2979 {
2980         struct drm_device *dev = state->dev;
2981         struct drm_i915_private *dev_priv = to_i915(dev);
2982         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
2983         struct drm_crtc *crtc;
2984         enum pipe pipe;
2985         int level, plane;
2986
2987         /*
2988          * SKL workaround: bspec recommends we disable the SAGV when we have
2989          * more then one pipe enabled
2990          *
2991          * If there are no active CRTCs, no additional checks need be performed
2992          */
2993         if (hweight32(intel_state->active_crtcs) == 0)
2994                 return true;
2995         else if (hweight32(intel_state->active_crtcs) > 1)
2996                 return false;
2997
2998         /* Since we're now guaranteed to only have one active CRTC... */
2999         pipe = ffs(intel_state->active_crtcs) - 1;
3000         crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3001
3002         if (crtc->state->mode.flags & DRM_MODE_FLAG_INTERLACE)
3003                 return false;
3004
3005         for_each_plane(dev_priv, pipe, plane) {
3006                 /* Skip this plane if it's not enabled */
3007                 if (intel_state->wm_results.plane[pipe][plane][0] == 0)
3008                         continue;
3009
3010                 /* Find the highest enabled wm level for this plane */
3011                 for (level = ilk_wm_max_level(dev);
3012                      intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
3013                      { }
3014
3015                 /*
3016                  * If any of the planes on this pipe don't enable wm levels
3017                  * that incur memory latencies higher then 30µs we can't enable
3018                  * the SAGV
3019                  */
3020                 if (dev_priv->wm.skl_latency[level] < SKL_SAGV_BLOCK_TIME)
3021                         return false;
3022         }
3023
3024         return true;
3025 }
3026
3027 static void
3028 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
3029                                    const struct intel_crtc_state *cstate,
3030                                    struct skl_ddb_entry *alloc, /* out */
3031                                    int *num_active /* out */)
3032 {
3033         struct drm_atomic_state *state = cstate->base.state;
3034         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3035         struct drm_i915_private *dev_priv = to_i915(dev);
3036         struct drm_crtc *for_crtc = cstate->base.crtc;
3037         unsigned int pipe_size, ddb_size;
3038         int nth_active_pipe;
3039         int pipe = to_intel_crtc(for_crtc)->pipe;
3040
3041         if (WARN_ON(!state) || !cstate->base.active) {
3042                 alloc->start = 0;
3043                 alloc->end = 0;
3044                 *num_active = hweight32(dev_priv->active_crtcs);
3045                 return;
3046         }
3047
3048         if (intel_state->active_pipe_changes)
3049                 *num_active = hweight32(intel_state->active_crtcs);
3050         else
3051                 *num_active = hweight32(dev_priv->active_crtcs);
3052
3053         ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3054         WARN_ON(ddb_size == 0);
3055
3056         ddb_size -= 4; /* 4 blocks for bypass path allocation */
3057
3058         /*
3059          * If the state doesn't change the active CRTC's, then there's
3060          * no need to recalculate; the existing pipe allocation limits
3061          * should remain unchanged.  Note that we're safe from racing
3062          * commits since any racing commit that changes the active CRTC
3063          * list would need to grab _all_ crtc locks, including the one
3064          * we currently hold.
3065          */
3066         if (!intel_state->active_pipe_changes) {
3067                 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
3068                 return;
3069         }
3070
3071         nth_active_pipe = hweight32(intel_state->active_crtcs &
3072                                     (drm_crtc_mask(for_crtc) - 1));
3073         pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3074         alloc->start = nth_active_pipe * ddb_size / *num_active;
3075         alloc->end = alloc->start + pipe_size;
3076 }
3077
3078 static unsigned int skl_cursor_allocation(int num_active)
3079 {
3080         if (num_active == 1)
3081                 return 32;
3082
3083         return 8;
3084 }
3085
3086 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3087 {
3088         entry->start = reg & 0x3ff;
3089         entry->end = (reg >> 16) & 0x3ff;
3090         if (entry->end)
3091                 entry->end += 1;
3092 }
3093
3094 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3095                           struct skl_ddb_allocation *ddb /* out */)
3096 {
3097         enum pipe pipe;
3098         int plane;
3099         u32 val;
3100
3101         memset(ddb, 0, sizeof(*ddb));
3102
3103         for_each_pipe(dev_priv, pipe) {
3104                 enum intel_display_power_domain power_domain;
3105
3106                 power_domain = POWER_DOMAIN_PIPE(pipe);
3107                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
3108                         continue;
3109
3110                 for_each_plane(dev_priv, pipe, plane) {
3111                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3112                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3113                                                    val);
3114                 }
3115
3116                 val = I915_READ(CUR_BUF_CFG(pipe));
3117                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3118                                            val);
3119
3120                 intel_display_power_put(dev_priv, power_domain);
3121         }
3122 }
3123
3124 /*
3125  * Determines the downscale amount of a plane for the purposes of watermark calculations.
3126  * The bspec defines downscale amount as:
3127  *
3128  * """
3129  * Horizontal down scale amount = maximum[1, Horizontal source size /
3130  *                                           Horizontal destination size]
3131  * Vertical down scale amount = maximum[1, Vertical source size /
3132  *                                         Vertical destination size]
3133  * Total down scale amount = Horizontal down scale amount *
3134  *                           Vertical down scale amount
3135  * """
3136  *
3137  * Return value is provided in 16.16 fixed point form to retain fractional part.
3138  * Caller should take care of dividing & rounding off the value.
3139  */
3140 static uint32_t
3141 skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3142 {
3143         uint32_t downscale_h, downscale_w;
3144         uint32_t src_w, src_h, dst_w, dst_h;
3145
3146         if (WARN_ON(!pstate->base.visible))
3147                 return DRM_PLANE_HELPER_NO_SCALING;
3148
3149         /* n.b., src is 16.16 fixed point, dst is whole integer */
3150         src_w = drm_rect_width(&pstate->base.src);
3151         src_h = drm_rect_height(&pstate->base.src);
3152         dst_w = drm_rect_width(&pstate->base.dst);
3153         dst_h = drm_rect_height(&pstate->base.dst);
3154         if (drm_rotation_90_or_270(pstate->base.rotation))
3155                 swap(dst_w, dst_h);
3156
3157         downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3158         downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3159
3160         /* Provide result in 16.16 fixed point */
3161         return (uint64_t)downscale_w * downscale_h >> 16;
3162 }
3163
3164 static unsigned int
3165 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3166                              const struct drm_plane_state *pstate,
3167                              int y)
3168 {
3169         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3170         struct drm_framebuffer *fb = pstate->fb;
3171         uint32_t down_scale_amount, data_rate;
3172         uint32_t width = 0, height = 0;
3173         unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3174
3175         if (!intel_pstate->base.visible)
3176                 return 0;
3177         if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3178                 return 0;
3179         if (y && format != DRM_FORMAT_NV12)
3180                 return 0;
3181
3182         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3183         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3184
3185         if (drm_rotation_90_or_270(pstate->rotation))
3186                 swap(width, height);
3187
3188         /* for planar format */
3189         if (format == DRM_FORMAT_NV12) {
3190                 if (y)  /* y-plane data rate */
3191                         data_rate = width * height *
3192                                 drm_format_plane_cpp(format, 0);
3193                 else    /* uv-plane data rate */
3194                         data_rate = (width / 2) * (height / 2) *
3195                                 drm_format_plane_cpp(format, 1);
3196         } else {
3197                 /* for packed formats */
3198                 data_rate = width * height * drm_format_plane_cpp(format, 0);
3199         }
3200
3201         down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3202
3203         return (uint64_t)data_rate * down_scale_amount >> 16;
3204 }
3205
3206 /*
3207  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3208  * a 8192x4096@32bpp framebuffer:
3209  *   3 * 4096 * 8192  * 4 < 2^32
3210  */
3211 static unsigned int
3212 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
3213 {
3214         struct drm_crtc_state *cstate = &intel_cstate->base;
3215         struct drm_atomic_state *state = cstate->state;
3216         struct drm_crtc *crtc = cstate->crtc;
3217         struct drm_device *dev = crtc->dev;
3218         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3219         const struct drm_plane *plane;
3220         const struct intel_plane *intel_plane;
3221         struct drm_plane_state *pstate;
3222         unsigned int rate, total_data_rate = 0;
3223         int id;
3224         int i;
3225
3226         if (WARN_ON(!state))
3227                 return 0;
3228
3229         /* Calculate and cache data rate for each plane */
3230         for_each_plane_in_state(state, plane, pstate, i) {
3231                 id = skl_wm_plane_id(to_intel_plane(plane));
3232                 intel_plane = to_intel_plane(plane);
3233
3234                 if (intel_plane->pipe != intel_crtc->pipe)
3235                         continue;
3236
3237                 /* packed/uv */
3238                 rate = skl_plane_relative_data_rate(intel_cstate,
3239                                                     pstate, 0);
3240                 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3241
3242                 /* y-plane */
3243                 rate = skl_plane_relative_data_rate(intel_cstate,
3244                                                     pstate, 1);
3245                 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
3246         }
3247
3248         /* Calculate CRTC's total data rate from cached values */
3249         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3250                 int id = skl_wm_plane_id(intel_plane);
3251
3252                 /* packed/uv */
3253                 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3254                 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
3255         }
3256
3257         return total_data_rate;
3258 }
3259
3260 static uint16_t
3261 skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3262                   const int y)
3263 {
3264         struct drm_framebuffer *fb = pstate->fb;
3265         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3266         uint32_t src_w, src_h;
3267         uint32_t min_scanlines = 8;
3268         uint8_t plane_bpp;
3269
3270         if (WARN_ON(!fb))
3271                 return 0;
3272
3273         /* For packed formats, no y-plane, return 0 */
3274         if (y && fb->pixel_format != DRM_FORMAT_NV12)
3275                 return 0;
3276
3277         /* For Non Y-tile return 8-blocks */
3278         if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3279             fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3280                 return 8;
3281
3282         src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3283         src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
3284
3285         if (drm_rotation_90_or_270(pstate->rotation))
3286                 swap(src_w, src_h);
3287
3288         /* Halve UV plane width and height for NV12 */
3289         if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3290                 src_w /= 2;
3291                 src_h /= 2;
3292         }
3293
3294         if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3295                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3296         else
3297                 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3298
3299         if (drm_rotation_90_or_270(pstate->rotation)) {
3300                 switch (plane_bpp) {
3301                 case 1:
3302                         min_scanlines = 32;
3303                         break;
3304                 case 2:
3305                         min_scanlines = 16;
3306                         break;
3307                 case 4:
3308                         min_scanlines = 8;
3309                         break;
3310                 case 8:
3311                         min_scanlines = 4;
3312                         break;
3313                 default:
3314                         WARN(1, "Unsupported pixel depth %u for rotation",
3315                              plane_bpp);
3316                         min_scanlines = 32;
3317                 }
3318         }
3319
3320         return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3321 }
3322
3323 static int
3324 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3325                       struct skl_ddb_allocation *ddb /* out */)
3326 {
3327         struct drm_atomic_state *state = cstate->base.state;
3328         struct drm_crtc *crtc = cstate->base.crtc;
3329         struct drm_device *dev = crtc->dev;
3330         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3331         struct intel_plane *intel_plane;
3332         struct drm_plane *plane;
3333         struct drm_plane_state *pstate;
3334         enum pipe pipe = intel_crtc->pipe;
3335         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3336         uint16_t alloc_size, start, cursor_blocks;
3337         uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3338         uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
3339         unsigned int total_data_rate;
3340         int num_active;
3341         int id, i;
3342
3343         if (WARN_ON(!state))
3344                 return 0;
3345
3346         if (!cstate->base.active) {
3347                 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
3348                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3349                 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3350                 return 0;
3351         }
3352
3353         skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
3354         alloc_size = skl_ddb_entry_size(alloc);
3355         if (alloc_size == 0) {
3356                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3357                 return 0;
3358         }
3359
3360         cursor_blocks = skl_cursor_allocation(num_active);
3361         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3362         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3363
3364         alloc_size -= cursor_blocks;
3365
3366         /* 1. Allocate the mininum required blocks for each active plane */
3367         for_each_plane_in_state(state, plane, pstate, i) {
3368                 intel_plane = to_intel_plane(plane);
3369                 id = skl_wm_plane_id(intel_plane);
3370
3371                 if (intel_plane->pipe != pipe)
3372                         continue;
3373
3374                 if (!to_intel_plane_state(pstate)->base.visible) {
3375                         minimum[id] = 0;
3376                         y_minimum[id] = 0;
3377                         continue;
3378                 }
3379                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3380                         minimum[id] = 0;
3381                         y_minimum[id] = 0;
3382                         continue;
3383                 }
3384
3385                 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3386                 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3387         }
3388
3389         for (i = 0; i < PLANE_CURSOR; i++) {
3390                 alloc_size -= minimum[i];
3391                 alloc_size -= y_minimum[i];
3392         }
3393
3394         /*
3395          * 2. Distribute the remaining space in proportion to the amount of
3396          * data each plane needs to fetch from memory.
3397          *
3398          * FIXME: we may not allocate every single block here.
3399          */
3400         total_data_rate = skl_get_total_relative_data_rate(cstate);
3401         if (total_data_rate == 0)
3402                 return 0;
3403
3404         start = alloc->start;
3405         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3406                 unsigned int data_rate, y_data_rate;
3407                 uint16_t plane_blocks, y_plane_blocks = 0;
3408                 int id = skl_wm_plane_id(intel_plane);
3409
3410                 data_rate = cstate->wm.skl.plane_data_rate[id];
3411
3412                 /*
3413                  * allocation for (packed formats) or (uv-plane part of planar format):
3414                  * promote the expression to 64 bits to avoid overflowing, the
3415                  * result is < available as data_rate / total_data_rate < 1
3416                  */
3417                 plane_blocks = minimum[id];
3418                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3419                                         total_data_rate);
3420
3421                 /* Leave disabled planes at (0,0) */
3422                 if (data_rate) {
3423                         ddb->plane[pipe][id].start = start;
3424                         ddb->plane[pipe][id].end = start + plane_blocks;
3425                 }
3426
3427                 start += plane_blocks;
3428
3429                 /*
3430                  * allocation for y_plane part of planar format:
3431                  */
3432                 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3433
3434                 y_plane_blocks = y_minimum[id];
3435                 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3436                                         total_data_rate);
3437
3438                 if (y_data_rate) {
3439                         ddb->y_plane[pipe][id].start = start;
3440                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3441                 }
3442
3443                 start += y_plane_blocks;
3444         }
3445
3446         return 0;
3447 }
3448
3449 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3450 {
3451         /* TODO: Take into account the scalers once we support them */
3452         return config->base.adjusted_mode.crtc_clock;
3453 }
3454
3455 /*
3456  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3457  * for the read latency) and cpp should always be <= 8, so that
3458  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3459  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3460 */
3461 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3462 {
3463         uint32_t wm_intermediate_val, ret;
3464
3465         if (latency == 0)
3466                 return UINT_MAX;
3467
3468         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3469         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3470
3471         return ret;
3472 }
3473
3474 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3475                                uint32_t horiz_pixels, uint8_t cpp,
3476                                uint64_t tiling, uint32_t latency)
3477 {
3478         uint32_t ret;
3479         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3480         uint32_t wm_intermediate_val;
3481
3482         if (latency == 0)
3483                 return UINT_MAX;
3484
3485         plane_bytes_per_line = horiz_pixels * cpp;
3486
3487         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3488             tiling == I915_FORMAT_MOD_Yf_TILED) {
3489                 plane_bytes_per_line *= 4;
3490                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3491                 plane_blocks_per_line /= 4;
3492         } else if (tiling == DRM_FORMAT_MOD_NONE) {
3493                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
3494         } else {
3495                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3496         }
3497
3498         wm_intermediate_val = latency * pixel_rate;
3499         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3500                                 plane_blocks_per_line;
3501
3502         return ret;
3503 }
3504
3505 static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3506                                               struct intel_plane_state *pstate)
3507 {
3508         uint64_t adjusted_pixel_rate;
3509         uint64_t downscale_amount;
3510         uint64_t pixel_rate;
3511
3512         /* Shouldn't reach here on disabled planes... */
3513         if (WARN_ON(!pstate->base.visible))
3514                 return 0;
3515
3516         /*
3517          * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3518          * with additional adjustments for plane-specific scaling.
3519          */
3520         adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3521         downscale_amount = skl_plane_downscale_amount(pstate);
3522
3523         pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3524         WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3525
3526         return pixel_rate;
3527 }
3528
3529 static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3530                                 struct intel_crtc_state *cstate,
3531                                 struct intel_plane_state *intel_pstate,
3532                                 uint16_t ddb_allocation,
3533                                 int level,
3534                                 uint16_t *out_blocks, /* out */
3535                                 uint8_t *out_lines, /* out */
3536                                 bool *enabled /* out */)
3537 {
3538         struct drm_plane_state *pstate = &intel_pstate->base;
3539         struct drm_framebuffer *fb = pstate->fb;
3540         uint32_t latency = dev_priv->wm.skl_latency[level];
3541         uint32_t method1, method2;
3542         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3543         uint32_t res_blocks, res_lines;
3544         uint32_t selected_result;
3545         uint8_t cpp;
3546         uint32_t width = 0, height = 0;
3547         uint32_t plane_pixel_rate;
3548
3549         if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
3550                 *enabled = false;
3551                 return 0;
3552         }
3553
3554         width = drm_rect_width(&intel_pstate->base.src) >> 16;
3555         height = drm_rect_height(&intel_pstate->base.src) >> 16;
3556
3557         if (drm_rotation_90_or_270(pstate->rotation))
3558                 swap(width, height);
3559
3560         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3561         plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3562
3563         method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3564         method2 = skl_wm_method2(plane_pixel_rate,
3565                                  cstate->base.adjusted_mode.crtc_htotal,
3566                                  width,
3567                                  cpp,
3568                                  fb->modifier[0],
3569                                  latency);
3570
3571         plane_bytes_per_line = width * cpp;
3572         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3573
3574         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3575             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3576                 uint32_t min_scanlines = 4;
3577                 uint32_t y_tile_minimum;
3578                 if (drm_rotation_90_or_270(pstate->rotation)) {
3579                         int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3580                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3581                                 drm_format_plane_cpp(fb->pixel_format, 0);
3582
3583                         switch (cpp) {
3584                         case 1:
3585                                 min_scanlines = 16;
3586                                 break;
3587                         case 2:
3588                                 min_scanlines = 8;
3589                                 break;
3590                         case 8:
3591                                 WARN(1, "Unsupported pixel depth for rotation");
3592                         }
3593                 }
3594                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3595                 selected_result = max(method2, y_tile_minimum);
3596         } else {
3597                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3598                         selected_result = min(method1, method2);
3599                 else
3600                         selected_result = method1;
3601         }
3602
3603         res_blocks = selected_result + 1;
3604         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3605
3606         if (level >= 1 && level <= 7) {
3607                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3608                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3609                         res_lines += 4;
3610                 else
3611                         res_blocks++;
3612         }
3613
3614         if (res_blocks >= ddb_allocation || res_lines > 31) {
3615                 *enabled = false;
3616
3617                 /*
3618                  * If there are no valid level 0 watermarks, then we can't
3619                  * support this display configuration.
3620                  */
3621                 if (level) {
3622                         return 0;
3623                 } else {
3624                         DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3625                         DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3626                                       to_intel_crtc(cstate->base.crtc)->pipe,
3627                                       skl_wm_plane_id(to_intel_plane(pstate->plane)),
3628                                       res_blocks, ddb_allocation, res_lines);
3629
3630                         return -EINVAL;
3631                 }
3632         }
3633
3634         *out_blocks = res_blocks;
3635         *out_lines = res_lines;
3636         *enabled = true;
3637
3638         return 0;
3639 }
3640
3641 static int
3642 skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3643                      struct skl_ddb_allocation *ddb,
3644                      struct intel_crtc_state *cstate,
3645                      int level,
3646                      struct skl_wm_level *result)
3647 {
3648         struct drm_atomic_state *state = cstate->base.state;
3649         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3650         struct drm_plane *plane;
3651         struct intel_plane *intel_plane;
3652         struct intel_plane_state *intel_pstate;
3653         uint16_t ddb_blocks;
3654         enum pipe pipe = intel_crtc->pipe;
3655         int ret;
3656
3657         /*
3658          * We'll only calculate watermarks for planes that are actually
3659          * enabled, so make sure all other planes are set as disabled.
3660          */
3661         memset(result, 0, sizeof(*result));
3662
3663         for_each_intel_plane_mask(&dev_priv->drm,
3664                                   intel_plane,
3665                                   cstate->base.plane_mask) {
3666                 int i = skl_wm_plane_id(intel_plane);
3667
3668                 plane = &intel_plane->base;
3669                 intel_pstate = NULL;
3670                 if (state)
3671                         intel_pstate =
3672                                 intel_atomic_get_existing_plane_state(state,
3673                                                                       intel_plane);
3674
3675                 /*
3676                  * Note: If we start supporting multiple pending atomic commits
3677                  * against the same planes/CRTC's in the future, plane->state
3678                  * will no longer be the correct pre-state to use for the
3679                  * calculations here and we'll need to change where we get the
3680                  * 'unchanged' plane data from.
3681                  *
3682                  * For now this is fine because we only allow one queued commit
3683                  * against a CRTC.  Even if the plane isn't modified by this
3684                  * transaction and we don't have a plane lock, we still have
3685                  * the CRTC's lock, so we know that no other transactions are
3686                  * racing with us to update it.
3687                  */
3688                 if (!intel_pstate)
3689                         intel_pstate = to_intel_plane_state(plane->state);
3690
3691                 WARN_ON(!intel_pstate->base.fb);
3692
3693                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3694
3695                 ret = skl_compute_plane_wm(dev_priv,
3696                                            cstate,
3697                                            intel_pstate,
3698                                            ddb_blocks,
3699                                            level,
3700                                            &result->plane_res_b[i],
3701                                            &result->plane_res_l[i],
3702                                            &result->plane_en[i]);
3703                 if (ret)
3704                         return ret;
3705         }
3706
3707         return 0;
3708 }
3709
3710 static uint32_t
3711 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3712 {
3713         if (!cstate->base.active)
3714                 return 0;
3715
3716         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3717                 return 0;
3718
3719         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3720                             skl_pipe_pixel_rate(cstate));
3721 }
3722
3723 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3724                                       struct skl_wm_level *trans_wm /* out */)
3725 {
3726         struct drm_crtc *crtc = cstate->base.crtc;
3727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3728         struct intel_plane *intel_plane;
3729
3730         if (!cstate->base.active)
3731                 return;
3732
3733         /* Until we know more, just disable transition WMs */
3734         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3735                 int i = skl_wm_plane_id(intel_plane);
3736
3737                 trans_wm->plane_en[i] = false;
3738         }
3739 }
3740
3741 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3742                              struct skl_ddb_allocation *ddb,
3743                              struct skl_pipe_wm *pipe_wm)
3744 {
3745         struct drm_device *dev = cstate->base.crtc->dev;
3746         const struct drm_i915_private *dev_priv = to_i915(dev);
3747         int level, max_level = ilk_wm_max_level(dev);
3748         int ret;
3749
3750         for (level = 0; level <= max_level; level++) {
3751                 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3752                                            level, &pipe_wm->wm[level]);
3753                 if (ret)
3754                         return ret;
3755         }
3756         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3757
3758         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3759
3760         return 0;
3761 }
3762
3763 static void skl_compute_wm_results(struct drm_device *dev,
3764                                    struct skl_pipe_wm *p_wm,
3765                                    struct skl_wm_values *r,
3766                                    struct intel_crtc *intel_crtc)
3767 {
3768         int level, max_level = ilk_wm_max_level(dev);
3769         enum pipe pipe = intel_crtc->pipe;
3770         uint32_t temp;
3771         int i;
3772
3773         for (level = 0; level <= max_level; level++) {
3774                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3775                         temp = 0;
3776
3777                         temp |= p_wm->wm[level].plane_res_l[i] <<
3778                                         PLANE_WM_LINES_SHIFT;
3779                         temp |= p_wm->wm[level].plane_res_b[i];
3780                         if (p_wm->wm[level].plane_en[i])
3781                                 temp |= PLANE_WM_EN;
3782
3783                         r->plane[pipe][i][level] = temp;
3784                 }
3785
3786                 temp = 0;
3787
3788                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3789                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3790
3791                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3792                         temp |= PLANE_WM_EN;
3793
3794                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3795
3796         }
3797
3798         /* transition WMs */
3799         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3800                 temp = 0;
3801                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3802                 temp |= p_wm->trans_wm.plane_res_b[i];
3803                 if (p_wm->trans_wm.plane_en[i])
3804                         temp |= PLANE_WM_EN;
3805
3806                 r->plane_trans[pipe][i] = temp;
3807         }
3808
3809         temp = 0;
3810         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3811         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3812         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3813                 temp |= PLANE_WM_EN;
3814
3815         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3816
3817         r->wm_linetime[pipe] = p_wm->linetime;
3818 }
3819
3820 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3821                                 i915_reg_t reg,
3822                                 const struct skl_ddb_entry *entry)
3823 {
3824         if (entry->end)
3825                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3826         else
3827                 I915_WRITE(reg, 0);
3828 }
3829
3830 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3831                         const struct skl_wm_values *wm,
3832                         int plane)
3833 {
3834         struct drm_crtc *crtc = &intel_crtc->base;
3835         struct drm_device *dev = crtc->dev;
3836         struct drm_i915_private *dev_priv = to_i915(dev);
3837         int level, max_level = ilk_wm_max_level(dev);
3838         enum pipe pipe = intel_crtc->pipe;
3839
3840         for (level = 0; level <= max_level; level++) {
3841                 I915_WRITE(PLANE_WM(pipe, plane, level),
3842                            wm->plane[pipe][plane][level]);
3843         }
3844         I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]);
3845
3846         skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3847                             &wm->ddb.plane[pipe][plane]);
3848         skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3849                             &wm->ddb.y_plane[pipe][plane]);
3850 }
3851
3852 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3853                          const struct skl_wm_values *wm)
3854 {
3855         struct drm_crtc *crtc = &intel_crtc->base;
3856         struct drm_device *dev = crtc->dev;
3857         struct drm_i915_private *dev_priv = to_i915(dev);
3858         int level, max_level = ilk_wm_max_level(dev);
3859         enum pipe pipe = intel_crtc->pipe;
3860
3861         for (level = 0; level <= max_level; level++) {
3862                 I915_WRITE(CUR_WM(pipe, level),
3863                            wm->plane[pipe][PLANE_CURSOR][level]);
3864         }
3865         I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]);
3866
3867         skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3868                             &wm->ddb.plane[pipe][PLANE_CURSOR]);
3869 }
3870
3871 bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
3872                                const struct skl_ddb_allocation *new,
3873                                enum pipe pipe)
3874 {
3875         return new->pipe[pipe].start == old->pipe[pipe].start &&
3876                new->pipe[pipe].end == old->pipe[pipe].end;
3877 }
3878
3879 static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3880                                            const struct skl_ddb_entry *b)
3881 {
3882         return a->start < b->end && b->start < a->end;
3883 }
3884
3885 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3886                                  const struct skl_ddb_allocation *old,
3887                                  const struct skl_ddb_allocation *new,
3888                                  enum pipe pipe)
3889 {
3890         struct drm_device *dev = state->dev;
3891         struct intel_crtc *intel_crtc;
3892         enum pipe otherp;
3893
3894         for_each_intel_crtc(dev, intel_crtc) {
3895                 otherp = intel_crtc->pipe;
3896
3897                 if (otherp == pipe)
3898                         continue;
3899
3900                 if (skl_ddb_entries_overlap(&new->pipe[pipe],
3901                                             &old->pipe[otherp]))
3902                         return true;
3903         }
3904
3905         return false;
3906 }
3907
3908 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3909                               struct skl_ddb_allocation *ddb, /* out */
3910                               struct skl_pipe_wm *pipe_wm, /* out */
3911                               bool *changed /* out */)
3912 {
3913         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3914         struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
3915         int ret;
3916
3917         ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3918         if (ret)
3919                 return ret;
3920
3921         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3922                 *changed = false;
3923         else
3924                 *changed = true;
3925
3926         return 0;
3927 }
3928
3929 static uint32_t
3930 pipes_modified(struct drm_atomic_state *state)
3931 {
3932         struct drm_crtc *crtc;
3933         struct drm_crtc_state *cstate;
3934         uint32_t i, ret = 0;
3935
3936         for_each_crtc_in_state(state, crtc, cstate, i)
3937                 ret |= drm_crtc_mask(crtc);
3938
3939         return ret;
3940 }
3941
3942 static int
3943 skl_compute_ddb(struct drm_atomic_state *state)
3944 {
3945         struct drm_device *dev = state->dev;
3946         struct drm_i915_private *dev_priv = to_i915(dev);
3947         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3948         struct intel_crtc *intel_crtc;
3949         struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
3950         uint32_t realloc_pipes = pipes_modified(state);
3951         int ret;
3952
3953         /*
3954          * If this is our first atomic update following hardware readout,
3955          * we can't trust the DDB that the BIOS programmed for us.  Let's
3956          * pretend that all pipes switched active status so that we'll
3957          * ensure a full DDB recompute.
3958          */
3959         if (dev_priv->wm.distrust_bios_wm) {
3960                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
3961                                        state->acquire_ctx);
3962                 if (ret)
3963                         return ret;
3964
3965                 intel_state->active_pipe_changes = ~0;
3966
3967                 /*
3968                  * We usually only initialize intel_state->active_crtcs if we
3969                  * we're doing a modeset; make sure this field is always
3970                  * initialized during the sanitization process that happens
3971                  * on the first commit too.
3972                  */
3973                 if (!intel_state->modeset)
3974                         intel_state->active_crtcs = dev_priv->active_crtcs;
3975         }
3976
3977         /*
3978          * If the modeset changes which CRTC's are active, we need to
3979          * recompute the DDB allocation for *all* active pipes, even
3980          * those that weren't otherwise being modified in any way by this
3981          * atomic commit.  Due to the shrinking of the per-pipe allocations
3982          * when new active CRTC's are added, it's possible for a pipe that
3983          * we were already using and aren't changing at all here to suddenly
3984          * become invalid if its DDB needs exceeds its new allocation.
3985          *
3986          * Note that if we wind up doing a full DDB recompute, we can't let
3987          * any other display updates race with this transaction, so we need
3988          * to grab the lock on *all* CRTC's.
3989          */
3990         if (intel_state->active_pipe_changes) {
3991                 realloc_pipes = ~0;
3992                 intel_state->wm_results.dirty_pipes = ~0;
3993         }
3994
3995         for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
3996                 struct intel_crtc_state *cstate;
3997
3998                 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
3999                 if (IS_ERR(cstate))
4000                         return PTR_ERR(cstate);
4001
4002                 ret = skl_allocate_pipe_ddb(cstate, ddb);
4003                 if (ret)
4004                         return ret;
4005
4006                 ret = drm_atomic_add_affected_planes(state, &intel_crtc->base);
4007                 if (ret)
4008                         return ret;
4009         }
4010
4011         return 0;
4012 }
4013
4014 static void
4015 skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4016                      struct skl_wm_values *src,
4017                      enum pipe pipe)
4018 {
4019         dst->wm_linetime[pipe] = src->wm_linetime[pipe];
4020         memcpy(dst->plane[pipe], src->plane[pipe],
4021                sizeof(dst->plane[pipe]));
4022         memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
4023                sizeof(dst->plane_trans[pipe]));
4024
4025         dst->ddb.pipe[pipe] = src->ddb.pipe[pipe];
4026         memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4027                sizeof(dst->ddb.y_plane[pipe]));
4028         memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4029                sizeof(dst->ddb.plane[pipe]));
4030 }
4031
4032 static int
4033 skl_compute_wm(struct drm_atomic_state *state)
4034 {
4035         struct drm_crtc *crtc;
4036         struct drm_crtc_state *cstate;
4037         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4038         struct skl_wm_values *results = &intel_state->wm_results;
4039         struct skl_pipe_wm *pipe_wm;
4040         bool changed = false;
4041         int ret, i;
4042
4043         /*
4044          * If this transaction isn't actually touching any CRTC's, don't
4045          * bother with watermark calculation.  Note that if we pass this
4046          * test, we're guaranteed to hold at least one CRTC state mutex,
4047          * which means we can safely use values like dev_priv->active_crtcs
4048          * since any racing commits that want to update them would need to
4049          * hold _all_ CRTC state mutexes.
4050          */
4051         for_each_crtc_in_state(state, crtc, cstate, i)
4052                 changed = true;
4053         if (!changed)
4054                 return 0;
4055
4056         /* Clear all dirty flags */
4057         results->dirty_pipes = 0;
4058
4059         ret = skl_compute_ddb(state);
4060         if (ret)
4061                 return ret;
4062
4063         /*
4064          * Calculate WM's for all pipes that are part of this transaction.
4065          * Note that the DDB allocation above may have added more CRTC's that
4066          * weren't otherwise being modified (and set bits in dirty_pipes) if
4067          * pipe allocations had to change.
4068          *
4069          * FIXME:  Now that we're doing this in the atomic check phase, we
4070          * should allow skl_update_pipe_wm() to return failure in cases where
4071          * no suitable watermark values can be found.
4072          */
4073         for_each_crtc_in_state(state, crtc, cstate, i) {
4074                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4075                 struct intel_crtc_state *intel_cstate =
4076                         to_intel_crtc_state(cstate);
4077
4078                 pipe_wm = &intel_cstate->wm.skl.optimal;
4079                 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4080                                          &changed);
4081                 if (ret)
4082                         return ret;
4083
4084                 if (changed)
4085                         results->dirty_pipes |= drm_crtc_mask(crtc);
4086
4087                 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4088                         /* This pipe's WM's did not change */
4089                         continue;
4090
4091                 intel_cstate->update_wm_pre = true;
4092                 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4093         }
4094
4095         return 0;
4096 }
4097
4098 static void skl_update_wm(struct drm_crtc *crtc)
4099 {
4100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4101         struct drm_device *dev = crtc->dev;
4102         struct drm_i915_private *dev_priv = to_i915(dev);
4103         struct skl_wm_values *results = &dev_priv->wm.skl_results;
4104         struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4105         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4106         struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
4107         enum pipe pipe = intel_crtc->pipe;
4108
4109         if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4110                 return;
4111
4112         intel_crtc->wm.active.skl = *pipe_wm;
4113
4114         mutex_lock(&dev_priv->wm.wm_mutex);
4115
4116         /*
4117          * If this pipe isn't active already, we're going to be enabling it
4118          * very soon. Since it's safe to update a pipe's ddb allocation while
4119          * the pipe's shut off, just do so here. Already active pipes will have
4120          * their watermarks updated once we update their planes.
4121          */
4122         if (crtc->state->active_changed) {
4123                 int plane;
4124
4125                 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++)
4126                         skl_write_plane_wm(intel_crtc, results, plane);
4127
4128                 skl_write_cursor_wm(intel_crtc, results);
4129         }
4130
4131         skl_copy_wm_for_pipe(hw_vals, results, pipe);
4132
4133         mutex_unlock(&dev_priv->wm.wm_mutex);
4134 }
4135
4136 static void ilk_compute_wm_config(struct drm_device *dev,
4137                                   struct intel_wm_config *config)
4138 {
4139         struct intel_crtc *crtc;
4140
4141         /* Compute the currently _active_ config */
4142         for_each_intel_crtc(dev, crtc) {
4143                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4144
4145                 if (!wm->pipe_enabled)
4146                         continue;
4147
4148                 config->sprites_enabled |= wm->sprites_enabled;
4149                 config->sprites_scaled |= wm->sprites_scaled;
4150                 config->num_pipes_active++;
4151         }
4152 }
4153
4154 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
4155 {
4156         struct drm_device *dev = &dev_priv->drm;
4157         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
4158         struct ilk_wm_maximums max;
4159         struct intel_wm_config config = {};
4160         struct ilk_wm_values results = {};
4161         enum intel_ddb_partitioning partitioning;
4162
4163         ilk_compute_wm_config(dev, &config);
4164
4165         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4166         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
4167
4168         /* 5/6 split only in single pipe config on IVB+ */
4169         if (INTEL_INFO(dev)->gen >= 7 &&
4170             config.num_pipes_active == 1 && config.sprites_enabled) {
4171                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4172                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
4173
4174                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
4175         } else {
4176                 best_lp_wm = &lp_wm_1_2;
4177         }
4178
4179         partitioning = (best_lp_wm == &lp_wm_1_2) ?
4180                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
4181
4182         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
4183
4184         ilk_write_wm_values(dev_priv, &results);
4185 }
4186
4187 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
4188 {
4189         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4190         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4191
4192         mutex_lock(&dev_priv->wm.wm_mutex);
4193         intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
4194         ilk_program_watermarks(dev_priv);
4195         mutex_unlock(&dev_priv->wm.wm_mutex);
4196 }
4197
4198 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4199 {
4200         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4201         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
4202
4203         mutex_lock(&dev_priv->wm.wm_mutex);
4204         if (cstate->wm.need_postvbl_update) {
4205                 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
4206                 ilk_program_watermarks(dev_priv);
4207         }
4208         mutex_unlock(&dev_priv->wm.wm_mutex);
4209 }
4210
4211 static void skl_pipe_wm_active_state(uint32_t val,
4212                                      struct skl_pipe_wm *active,
4213                                      bool is_transwm,
4214                                      bool is_cursor,
4215                                      int i,
4216                                      int level)
4217 {
4218         bool is_enabled = (val & PLANE_WM_EN) != 0;
4219
4220         if (!is_transwm) {
4221                 if (!is_cursor) {
4222                         active->wm[level].plane_en[i] = is_enabled;
4223                         active->wm[level].plane_res_b[i] =
4224                                         val & PLANE_WM_BLOCKS_MASK;
4225                         active->wm[level].plane_res_l[i] =
4226                                         (val >> PLANE_WM_LINES_SHIFT) &
4227                                                 PLANE_WM_LINES_MASK;
4228                 } else {
4229                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4230                         active->wm[level].plane_res_b[PLANE_CURSOR] =
4231                                         val & PLANE_WM_BLOCKS_MASK;
4232                         active->wm[level].plane_res_l[PLANE_CURSOR] =
4233                                         (val >> PLANE_WM_LINES_SHIFT) &
4234                                                 PLANE_WM_LINES_MASK;
4235                 }
4236         } else {
4237                 if (!is_cursor) {
4238                         active->trans_wm.plane_en[i] = is_enabled;
4239                         active->trans_wm.plane_res_b[i] =
4240                                         val & PLANE_WM_BLOCKS_MASK;
4241                         active->trans_wm.plane_res_l[i] =
4242                                         (val >> PLANE_WM_LINES_SHIFT) &
4243                                                 PLANE_WM_LINES_MASK;
4244                 } else {
4245                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4246                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
4247                                         val & PLANE_WM_BLOCKS_MASK;
4248                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
4249                                         (val >> PLANE_WM_LINES_SHIFT) &
4250                                                 PLANE_WM_LINES_MASK;
4251                 }
4252         }
4253 }
4254
4255 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4256 {
4257         struct drm_device *dev = crtc->dev;
4258         struct drm_i915_private *dev_priv = to_i915(dev);
4259         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4260         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4261         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4262         struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
4263         enum pipe pipe = intel_crtc->pipe;
4264         int level, i, max_level;
4265         uint32_t temp;
4266
4267         max_level = ilk_wm_max_level(dev);
4268
4269         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4270
4271         for (level = 0; level <= max_level; level++) {
4272                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4273                         hw->plane[pipe][i][level] =
4274                                         I915_READ(PLANE_WM(pipe, i, level));
4275                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
4276         }
4277
4278         for (i = 0; i < intel_num_planes(intel_crtc); i++)
4279                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4280         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
4281
4282         if (!intel_crtc->active)
4283                 return;
4284
4285         hw->dirty_pipes |= drm_crtc_mask(crtc);
4286
4287         active->linetime = hw->wm_linetime[pipe];
4288
4289         for (level = 0; level <= max_level; level++) {
4290                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4291                         temp = hw->plane[pipe][i][level];
4292                         skl_pipe_wm_active_state(temp, active, false,
4293                                                 false, i, level);
4294                 }
4295                 temp = hw->plane[pipe][PLANE_CURSOR][level];
4296                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4297         }
4298
4299         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4300                 temp = hw->plane_trans[pipe][i];
4301                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4302         }
4303
4304         temp = hw->plane_trans[pipe][PLANE_CURSOR];
4305         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4306
4307         intel_crtc->wm.active.skl = *active;
4308 }
4309
4310 void skl_wm_get_hw_state(struct drm_device *dev)
4311 {
4312         struct drm_i915_private *dev_priv = to_i915(dev);
4313         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
4314         struct drm_crtc *crtc;
4315
4316         skl_ddb_get_hw_state(dev_priv, ddb);
4317         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4318                 skl_pipe_wm_get_hw_state(crtc);
4319
4320         if (dev_priv->active_crtcs) {
4321                 /* Fully recompute DDB on first atomic commit */
4322                 dev_priv->wm.distrust_bios_wm = true;
4323         } else {
4324                 /* Easy/common case; just sanitize DDB now if everything off */
4325                 memset(ddb, 0, sizeof(*ddb));
4326         }
4327 }
4328
4329 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4330 {
4331         struct drm_device *dev = crtc->dev;
4332         struct drm_i915_private *dev_priv = to_i915(dev);
4333         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4335         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
4336         struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
4337         enum pipe pipe = intel_crtc->pipe;
4338         static const i915_reg_t wm0_pipe_reg[] = {
4339                 [PIPE_A] = WM0_PIPEA_ILK,
4340                 [PIPE_B] = WM0_PIPEB_ILK,
4341                 [PIPE_C] = WM0_PIPEC_IVB,
4342         };
4343
4344         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
4345         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4346                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4347
4348         memset(active, 0, sizeof(*active));
4349
4350         active->pipe_enabled = intel_crtc->active;
4351
4352         if (active->pipe_enabled) {
4353                 u32 tmp = hw->wm_pipe[pipe];
4354
4355                 /*
4356                  * For active pipes LP0 watermark is marked as
4357                  * enabled, and LP1+ watermaks as disabled since
4358                  * we can't really reverse compute them in case
4359                  * multiple pipes are active.
4360                  */
4361                 active->wm[0].enable = true;
4362                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4363                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4364                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4365                 active->linetime = hw->wm_linetime[pipe];
4366         } else {
4367                 int level, max_level = ilk_wm_max_level(dev);
4368
4369                 /*
4370                  * For inactive pipes, all watermark levels
4371                  * should be marked as enabled but zeroed,
4372                  * which is what we'd compute them to.
4373                  */
4374                 for (level = 0; level <= max_level; level++)
4375                         active->wm[level].enable = true;
4376         }
4377
4378         intel_crtc->wm.active.ilk = *active;
4379 }
4380
4381 #define _FW_WM(value, plane) \
4382         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4383 #define _FW_WM_VLV(value, plane) \
4384         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4385
4386 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4387                                struct vlv_wm_values *wm)
4388 {
4389         enum pipe pipe;
4390         uint32_t tmp;
4391
4392         for_each_pipe(dev_priv, pipe) {
4393                 tmp = I915_READ(VLV_DDL(pipe));
4394
4395                 wm->ddl[pipe].primary =
4396                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4397                 wm->ddl[pipe].cursor =
4398                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4399                 wm->ddl[pipe].sprite[0] =
4400                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4401                 wm->ddl[pipe].sprite[1] =
4402                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4403         }
4404
4405         tmp = I915_READ(DSPFW1);
4406         wm->sr.plane = _FW_WM(tmp, SR);
4407         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4408         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4409         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4410
4411         tmp = I915_READ(DSPFW2);
4412         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4413         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4414         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4415
4416         tmp = I915_READ(DSPFW3);
4417         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4418
4419         if (IS_CHERRYVIEW(dev_priv)) {
4420                 tmp = I915_READ(DSPFW7_CHV);
4421                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4422                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4423
4424                 tmp = I915_READ(DSPFW8_CHV);
4425                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4426                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4427
4428                 tmp = I915_READ(DSPFW9_CHV);
4429                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4430                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4431
4432                 tmp = I915_READ(DSPHOWM);
4433                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4434                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4435                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4436                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4437                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4438                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4439                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4440                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4441                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4442                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4443         } else {
4444                 tmp = I915_READ(DSPFW7);
4445                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4446                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4447
4448                 tmp = I915_READ(DSPHOWM);
4449                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4450                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4451                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4452                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4453                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4454                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4455                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4456         }
4457 }
4458
4459 #undef _FW_WM
4460 #undef _FW_WM_VLV
4461
4462 void vlv_wm_get_hw_state(struct drm_device *dev)
4463 {
4464         struct drm_i915_private *dev_priv = to_i915(dev);
4465         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4466         struct intel_plane *plane;
4467         enum pipe pipe;
4468         u32 val;
4469
4470         vlv_read_wm_values(dev_priv, wm);
4471
4472         for_each_intel_plane(dev, plane) {
4473                 switch (plane->base.type) {
4474                         int sprite;
4475                 case DRM_PLANE_TYPE_CURSOR:
4476                         plane->wm.fifo_size = 63;
4477                         break;
4478                 case DRM_PLANE_TYPE_PRIMARY:
4479                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4480                         break;
4481                 case DRM_PLANE_TYPE_OVERLAY:
4482                         sprite = plane->plane;
4483                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4484                         break;
4485                 }
4486         }
4487
4488         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4489         wm->level = VLV_WM_LEVEL_PM2;
4490
4491         if (IS_CHERRYVIEW(dev_priv)) {
4492                 mutex_lock(&dev_priv->rps.hw_lock);
4493
4494                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4495                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4496                         wm->level = VLV_WM_LEVEL_PM5;
4497
4498                 /*
4499                  * If DDR DVFS is disabled in the BIOS, Punit
4500                  * will never ack the request. So if that happens
4501                  * assume we don't have to enable/disable DDR DVFS
4502                  * dynamically. To test that just set the REQ_ACK
4503                  * bit to poke the Punit, but don't change the
4504                  * HIGH/LOW bits so that we don't actually change
4505                  * the current state.
4506                  */
4507                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4508                 val |= FORCE_DDR_FREQ_REQ_ACK;
4509                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4510
4511                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4512                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4513                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4514                                       "assuming DDR DVFS is disabled\n");
4515                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4516                 } else {
4517                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4518                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4519                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4520                 }
4521
4522                 mutex_unlock(&dev_priv->rps.hw_lock);
4523         }
4524
4525         for_each_pipe(dev_priv, pipe)
4526                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4527                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4528                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4529
4530         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4531                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4532 }
4533
4534 void ilk_wm_get_hw_state(struct drm_device *dev)
4535 {
4536         struct drm_i915_private *dev_priv = to_i915(dev);
4537         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4538         struct drm_crtc *crtc;
4539
4540         for_each_crtc(dev, crtc)
4541                 ilk_pipe_wm_get_hw_state(crtc);
4542
4543         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4544         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4545         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4546
4547         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4548         if (INTEL_INFO(dev)->gen >= 7) {
4549                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4550                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4551         }
4552
4553         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4554                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4555                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4556         else if (IS_IVYBRIDGE(dev))
4557                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4558                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4559
4560         hw->enable_fbc_wm =
4561                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4562 }
4563
4564 /**
4565  * intel_update_watermarks - update FIFO watermark values based on current modes
4566  *
4567  * Calculate watermark values for the various WM regs based on current mode
4568  * and plane configuration.
4569  *
4570  * There are several cases to deal with here:
4571  *   - normal (i.e. non-self-refresh)
4572  *   - self-refresh (SR) mode
4573  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4574  *   - lines are small relative to FIFO size (buffer can hold more than 2
4575  *     lines), so need to account for TLB latency
4576  *
4577  *   The normal calculation is:
4578  *     watermark = dotclock * bytes per pixel * latency
4579  *   where latency is platform & configuration dependent (we assume pessimal
4580  *   values here).
4581  *
4582  *   The SR calculation is:
4583  *     watermark = (trunc(latency/line time)+1) * surface width *
4584  *       bytes per pixel
4585  *   where
4586  *     line time = htotal / dotclock
4587  *     surface width = hdisplay for normal plane and 64 for cursor
4588  *   and latency is assumed to be high, as above.
4589  *
4590  * The final value programmed to the register should always be rounded up,
4591  * and include an extra 2 entries to account for clock crossings.
4592  *
4593  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4594  * to set the non-SR watermarks to 8.
4595  */
4596 void intel_update_watermarks(struct drm_crtc *crtc)
4597 {
4598         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4599
4600         if (dev_priv->display.update_wm)
4601                 dev_priv->display.update_wm(crtc);
4602 }
4603
4604 /*
4605  * Lock protecting IPS related data structures
4606  */
4607 DEFINE_SPINLOCK(mchdev_lock);
4608
4609 /* Global for IPS driver to get at the current i915 device. Protected by
4610  * mchdev_lock. */
4611 static struct drm_i915_private *i915_mch_dev;
4612
4613 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
4614 {
4615         u16 rgvswctl;
4616
4617         assert_spin_locked(&mchdev_lock);
4618
4619         rgvswctl = I915_READ16(MEMSWCTL);
4620         if (rgvswctl & MEMCTL_CMD_STS) {
4621                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4622                 return false; /* still busy with another command */
4623         }
4624
4625         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4626                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4627         I915_WRITE16(MEMSWCTL, rgvswctl);
4628         POSTING_READ16(MEMSWCTL);
4629
4630         rgvswctl |= MEMCTL_CMD_STS;
4631         I915_WRITE16(MEMSWCTL, rgvswctl);
4632
4633         return true;
4634 }
4635
4636 static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
4637 {
4638         u32 rgvmodectl;
4639         u8 fmax, fmin, fstart, vstart;
4640
4641         spin_lock_irq(&mchdev_lock);
4642
4643         rgvmodectl = I915_READ(MEMMODECTL);
4644
4645         /* Enable temp reporting */
4646         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4647         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4648
4649         /* 100ms RC evaluation intervals */
4650         I915_WRITE(RCUPEI, 100000);
4651         I915_WRITE(RCDNEI, 100000);
4652
4653         /* Set max/min thresholds to 90ms and 80ms respectively */
4654         I915_WRITE(RCBMAXAVG, 90000);
4655         I915_WRITE(RCBMINAVG, 80000);
4656
4657         I915_WRITE(MEMIHYST, 1);
4658
4659         /* Set up min, max, and cur for interrupt handling */
4660         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4661         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4662         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4663                 MEMMODE_FSTART_SHIFT;
4664
4665         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4666                 PXVFREQ_PX_SHIFT;
4667
4668         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4669         dev_priv->ips.fstart = fstart;
4670
4671         dev_priv->ips.max_delay = fstart;
4672         dev_priv->ips.min_delay = fmin;
4673         dev_priv->ips.cur_delay = fstart;
4674
4675         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4676                          fmax, fmin, fstart);
4677
4678         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4679
4680         /*
4681          * Interrupts will be enabled in ironlake_irq_postinstall
4682          */
4683
4684         I915_WRITE(VIDSTART, vstart);
4685         POSTING_READ(VIDSTART);
4686
4687         rgvmodectl |= MEMMODE_SWMODE_EN;
4688         I915_WRITE(MEMMODECTL, rgvmodectl);
4689
4690         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4691                 DRM_ERROR("stuck trying to change perf mode\n");
4692         mdelay(1);
4693
4694         ironlake_set_drps(dev_priv, fstart);
4695
4696         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4697                 I915_READ(DDREC) + I915_READ(CSIEC);
4698         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4699         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4700         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4701
4702         spin_unlock_irq(&mchdev_lock);
4703 }
4704
4705 static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
4706 {
4707         u16 rgvswctl;
4708
4709         spin_lock_irq(&mchdev_lock);
4710
4711         rgvswctl = I915_READ16(MEMSWCTL);
4712
4713         /* Ack interrupts, disable EFC interrupt */
4714         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4715         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4716         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4717         I915_WRITE(DEIIR, DE_PCU_EVENT);
4718         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4719
4720         /* Go back to the starting frequency */
4721         ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
4722         mdelay(1);
4723         rgvswctl |= MEMCTL_CMD_STS;
4724         I915_WRITE(MEMSWCTL, rgvswctl);
4725         mdelay(1);
4726
4727         spin_unlock_irq(&mchdev_lock);
4728 }
4729
4730 /* There's a funny hw issue where the hw returns all 0 when reading from
4731  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4732  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4733  * all limits and the gpu stuck at whatever frequency it is at atm).
4734  */
4735 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4736 {
4737         u32 limits;
4738
4739         /* Only set the down limit when we've reached the lowest level to avoid
4740          * getting more interrupts, otherwise leave this clear. This prevents a
4741          * race in the hw when coming out of rc6: There's a tiny window where
4742          * the hw runs at the minimal clock before selecting the desired
4743          * frequency, if the down threshold expires in that window we will not
4744          * receive a down interrupt. */
4745         if (IS_GEN9(dev_priv)) {
4746                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4747                 if (val <= dev_priv->rps.min_freq_softlimit)
4748                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4749         } else {
4750                 limits = dev_priv->rps.max_freq_softlimit << 24;
4751                 if (val <= dev_priv->rps.min_freq_softlimit)
4752                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4753         }
4754
4755         return limits;
4756 }
4757
4758 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4759 {
4760         int new_power;
4761         u32 threshold_up = 0, threshold_down = 0; /* in % */
4762         u32 ei_up = 0, ei_down = 0;
4763
4764         new_power = dev_priv->rps.power;
4765         switch (dev_priv->rps.power) {
4766         case LOW_POWER:
4767                 if (val > dev_priv->rps.efficient_freq + 1 &&
4768                     val > dev_priv->rps.cur_freq)
4769                         new_power = BETWEEN;
4770                 break;
4771
4772         case BETWEEN:
4773                 if (val <= dev_priv->rps.efficient_freq &&
4774                     val < dev_priv->rps.cur_freq)
4775                         new_power = LOW_POWER;
4776                 else if (val >= dev_priv->rps.rp0_freq &&
4777                          val > dev_priv->rps.cur_freq)
4778                         new_power = HIGH_POWER;
4779                 break;
4780
4781         case HIGH_POWER:
4782                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4783                     val < dev_priv->rps.cur_freq)
4784                         new_power = BETWEEN;
4785                 break;
4786         }
4787         /* Max/min bins are special */
4788         if (val <= dev_priv->rps.min_freq_softlimit)
4789                 new_power = LOW_POWER;
4790         if (val >= dev_priv->rps.max_freq_softlimit)
4791                 new_power = HIGH_POWER;
4792         if (new_power == dev_priv->rps.power)
4793                 return;
4794
4795         /* Note the units here are not exactly 1us, but 1280ns. */
4796         switch (new_power) {
4797         case LOW_POWER:
4798                 /* Upclock if more than 95% busy over 16ms */
4799                 ei_up = 16000;
4800                 threshold_up = 95;
4801
4802                 /* Downclock if less than 85% busy over 32ms */
4803                 ei_down = 32000;
4804                 threshold_down = 85;
4805                 break;
4806
4807         case BETWEEN:
4808                 /* Upclock if more than 90% busy over 13ms */
4809                 ei_up = 13000;
4810                 threshold_up = 90;
4811
4812                 /* Downclock if less than 75% busy over 32ms */
4813                 ei_down = 32000;
4814                 threshold_down = 75;
4815                 break;
4816
4817         case HIGH_POWER:
4818                 /* Upclock if more than 85% busy over 10ms */
4819                 ei_up = 10000;
4820                 threshold_up = 85;
4821
4822                 /* Downclock if less than 60% busy over 32ms */
4823                 ei_down = 32000;
4824                 threshold_down = 60;
4825                 break;
4826         }
4827
4828         I915_WRITE(GEN6_RP_UP_EI,
4829                    GT_INTERVAL_FROM_US(dev_priv, ei_up));
4830         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4831                    GT_INTERVAL_FROM_US(dev_priv,
4832                                        ei_up * threshold_up / 100));
4833
4834         I915_WRITE(GEN6_RP_DOWN_EI,
4835                    GT_INTERVAL_FROM_US(dev_priv, ei_down));
4836         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4837                    GT_INTERVAL_FROM_US(dev_priv,
4838                                        ei_down * threshold_down / 100));
4839
4840         I915_WRITE(GEN6_RP_CONTROL,
4841                    GEN6_RP_MEDIA_TURBO |
4842                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4843                    GEN6_RP_MEDIA_IS_GFX |
4844                    GEN6_RP_ENABLE |
4845                    GEN6_RP_UP_BUSY_AVG |
4846                    GEN6_RP_DOWN_IDLE_AVG);
4847
4848         dev_priv->rps.power = new_power;
4849         dev_priv->rps.up_threshold = threshold_up;
4850         dev_priv->rps.down_threshold = threshold_down;
4851         dev_priv->rps.last_adj = 0;
4852 }
4853
4854 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4855 {
4856         u32 mask = 0;
4857
4858         if (val > dev_priv->rps.min_freq_softlimit)
4859                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4860         if (val < dev_priv->rps.max_freq_softlimit)
4861                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4862
4863         mask &= dev_priv->pm_rps_events;
4864
4865         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4866 }
4867
4868 /* gen6_set_rps is called to update the frequency request, but should also be
4869  * called when the range (min_delay and max_delay) is modified so that we can
4870  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4871 static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
4872 {
4873         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4874         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
4875                 return;
4876
4877         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4878         WARN_ON(val > dev_priv->rps.max_freq);
4879         WARN_ON(val < dev_priv->rps.min_freq);
4880
4881         /* min/max delay may still have been modified so be sure to
4882          * write the limits value.
4883          */
4884         if (val != dev_priv->rps.cur_freq) {
4885                 gen6_set_rps_thresholds(dev_priv, val);
4886
4887                 if (IS_GEN9(dev_priv))
4888                         I915_WRITE(GEN6_RPNSWREQ,
4889                                    GEN9_FREQUENCY(val));
4890                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
4891                         I915_WRITE(GEN6_RPNSWREQ,
4892                                    HSW_FREQUENCY(val));
4893                 else
4894                         I915_WRITE(GEN6_RPNSWREQ,
4895                                    GEN6_FREQUENCY(val) |
4896                                    GEN6_OFFSET(0) |
4897                                    GEN6_AGGRESSIVE_TURBO);
4898         }
4899
4900         /* Make sure we continue to get interrupts
4901          * until we hit the minimum or maximum frequencies.
4902          */
4903         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4904         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4905
4906         POSTING_READ(GEN6_RPNSWREQ);
4907
4908         dev_priv->rps.cur_freq = val;
4909         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4910 }
4911
4912 static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
4913 {
4914         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4915         WARN_ON(val > dev_priv->rps.max_freq);
4916         WARN_ON(val < dev_priv->rps.min_freq);
4917
4918         if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
4919                       "Odd GPU freq value\n"))
4920                 val &= ~1;
4921
4922         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4923
4924         if (val != dev_priv->rps.cur_freq) {
4925                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4926                 if (!IS_CHERRYVIEW(dev_priv))
4927                         gen6_set_rps_thresholds(dev_priv, val);
4928         }
4929
4930         dev_priv->rps.cur_freq = val;
4931         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4932 }
4933
4934 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4935  *
4936  * * If Gfx is Idle, then
4937  * 1. Forcewake Media well.
4938  * 2. Request idle freq.
4939  * 3. Release Forcewake of Media well.
4940 */
4941 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4942 {
4943         u32 val = dev_priv->rps.idle_freq;
4944
4945         if (dev_priv->rps.cur_freq <= val)
4946                 return;
4947
4948         /* Wake up the media well, as that takes a lot less
4949          * power than the Render well. */
4950         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4951         valleyview_set_rps(dev_priv, val);
4952         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4953 }
4954
4955 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4956 {
4957         mutex_lock(&dev_priv->rps.hw_lock);
4958         if (dev_priv->rps.enabled) {
4959                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4960                         gen6_rps_reset_ei(dev_priv);
4961                 I915_WRITE(GEN6_PMINTRMSK,
4962                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4963
4964                 gen6_enable_rps_interrupts(dev_priv);
4965
4966                 /* Ensure we start at the user's desired frequency */
4967                 intel_set_rps(dev_priv,
4968                               clamp(dev_priv->rps.cur_freq,
4969                                     dev_priv->rps.min_freq_softlimit,
4970                                     dev_priv->rps.max_freq_softlimit));
4971         }
4972         mutex_unlock(&dev_priv->rps.hw_lock);
4973 }
4974
4975 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4976 {
4977         /* Flush our bottom-half so that it does not race with us
4978          * setting the idle frequency and so that it is bounded by
4979          * our rpm wakeref. And then disable the interrupts to stop any
4980          * futher RPS reclocking whilst we are asleep.
4981          */
4982         gen6_disable_rps_interrupts(dev_priv);
4983
4984         mutex_lock(&dev_priv->rps.hw_lock);
4985         if (dev_priv->rps.enabled) {
4986                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4987                         vlv_set_rps_idle(dev_priv);
4988                 else
4989                         gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
4990                 dev_priv->rps.last_adj = 0;
4991                 I915_WRITE(GEN6_PMINTRMSK,
4992                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
4993         }
4994         mutex_unlock(&dev_priv->rps.hw_lock);
4995
4996         spin_lock(&dev_priv->rps.client_lock);
4997         while (!list_empty(&dev_priv->rps.clients))
4998                 list_del_init(dev_priv->rps.clients.next);
4999         spin_unlock(&dev_priv->rps.client_lock);
5000 }
5001
5002 void gen6_rps_boost(struct drm_i915_private *dev_priv,
5003                     struct intel_rps_client *rps,
5004                     unsigned long submitted)
5005 {
5006         /* This is intentionally racy! We peek at the state here, then
5007          * validate inside the RPS worker.
5008          */
5009         if (!(dev_priv->gt.awake &&
5010               dev_priv->rps.enabled &&
5011               dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
5012                 return;
5013
5014         /* Force a RPS boost (and don't count it against the client) if
5015          * the GPU is severely congested.
5016          */
5017         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
5018                 rps = NULL;
5019
5020         spin_lock(&dev_priv->rps.client_lock);
5021         if (rps == NULL || list_empty(&rps->link)) {
5022                 spin_lock_irq(&dev_priv->irq_lock);
5023                 if (dev_priv->rps.interrupts_enabled) {
5024                         dev_priv->rps.client_boost = true;
5025                         schedule_work(&dev_priv->rps.work);
5026                 }
5027                 spin_unlock_irq(&dev_priv->irq_lock);
5028
5029                 if (rps != NULL) {
5030                         list_add(&rps->link, &dev_priv->rps.clients);
5031                         rps->boosts++;
5032                 } else
5033                         dev_priv->rps.boosts++;
5034         }
5035         spin_unlock(&dev_priv->rps.client_lock);
5036 }
5037
5038 void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
5039 {
5040         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5041                 valleyview_set_rps(dev_priv, val);
5042         else
5043                 gen6_set_rps(dev_priv, val);
5044 }
5045
5046 static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
5047 {
5048         I915_WRITE(GEN6_RC_CONTROL, 0);
5049         I915_WRITE(GEN9_PG_ENABLE, 0);
5050 }
5051
5052 static void gen9_disable_rps(struct drm_i915_private *dev_priv)
5053 {
5054         I915_WRITE(GEN6_RP_CONTROL, 0);
5055 }
5056
5057 static void gen6_disable_rps(struct drm_i915_private *dev_priv)
5058 {
5059         I915_WRITE(GEN6_RC_CONTROL, 0);
5060         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
5061         I915_WRITE(GEN6_RP_CONTROL, 0);
5062 }
5063
5064 static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
5065 {
5066         I915_WRITE(GEN6_RC_CONTROL, 0);
5067 }
5068
5069 static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
5070 {
5071         /* we're doing forcewake before Disabling RC6,
5072          * This what the BIOS expects when going into suspend */
5073         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5074
5075         I915_WRITE(GEN6_RC_CONTROL, 0);
5076
5077         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5078 }
5079
5080 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
5081 {
5082         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5083                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5084                         mode = GEN6_RC_CTL_RC6_ENABLE;
5085                 else
5086                         mode = 0;
5087         }
5088         if (HAS_RC6p(dev_priv))
5089                 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5090                                  "RC6 %s RC6p %s RC6pp %s\n",
5091                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5092                                  onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5093                                  onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
5094
5095         else
5096                 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5097                                  onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
5098 }
5099
5100 static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
5101 {
5102         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5103         bool enable_rc6 = true;
5104         unsigned long rc6_ctx_base;
5105         u32 rc_ctl;
5106         int rc_sw_target;
5107
5108         rc_ctl = I915_READ(GEN6_RC_CONTROL);
5109         rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5110                        RC_SW_TARGET_STATE_SHIFT;
5111         DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5112                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5113                          onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5114                          onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5115                          rc_sw_target);
5116
5117         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
5118                 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
5119                 enable_rc6 = false;
5120         }
5121
5122         /*
5123          * The exact context size is not known for BXT, so assume a page size
5124          * for this check.
5125          */
5126         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
5127         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5128               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5129                                         ggtt->stolen_reserved_size))) {
5130                 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
5131                 enable_rc6 = false;
5132         }
5133
5134         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5135               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5136               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5137               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
5138                 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
5139                 enable_rc6 = false;
5140         }
5141
5142         if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5143             !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5144             !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5145                 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5146                 enable_rc6 = false;
5147         }
5148
5149         if (!I915_READ(GEN6_GFXPAUSE)) {
5150                 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5151                 enable_rc6 = false;
5152         }
5153
5154         if (!I915_READ(GEN8_MISC_CTRL0)) {
5155                 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
5156                 enable_rc6 = false;
5157         }
5158
5159         return enable_rc6;
5160 }
5161
5162 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
5163 {
5164         /* No RC6 before Ironlake and code is gone for ilk. */
5165         if (INTEL_INFO(dev_priv)->gen < 6)
5166                 return 0;
5167
5168         if (!enable_rc6)
5169                 return 0;
5170
5171         if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
5172                 DRM_INFO("RC6 disabled by BIOS\n");
5173                 return 0;
5174         }
5175
5176         /* Respect the kernel parameter if it is set */
5177         if (enable_rc6 >= 0) {
5178                 int mask;
5179
5180                 if (HAS_RC6p(dev_priv))
5181                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5182                                INTEL_RC6pp_ENABLE;
5183                 else
5184                         mask = INTEL_RC6_ENABLE;
5185
5186                 if ((enable_rc6 & mask) != enable_rc6)
5187                         DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5188                                          "(requested %d, valid %d)\n",
5189                                          enable_rc6 & mask, enable_rc6, mask);
5190
5191                 return enable_rc6 & mask;
5192         }
5193
5194         if (IS_IVYBRIDGE(dev_priv))
5195                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
5196
5197         return INTEL_RC6_ENABLE;
5198 }
5199
5200 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
5201 {
5202         /* All of these values are in units of 50MHz */
5203
5204         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
5205         if (IS_BROXTON(dev_priv)) {
5206                 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
5207                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5208                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5209                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
5210         } else {
5211                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
5212                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
5213                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
5214                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5215         }
5216         /* hw_max = RP0 until we check for overclocking */
5217         dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
5218
5219         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
5220         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5221             IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5222                 u32 ddcc_status = 0;
5223
5224                 if (sandybridge_pcode_read(dev_priv,
5225                                            HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5226                                            &ddcc_status) == 0)
5227                         dev_priv->rps.efficient_freq =
5228                                 clamp_t(u8,
5229                                         ((ddcc_status >> 8) & 0xff),
5230                                         dev_priv->rps.min_freq,
5231                                         dev_priv->rps.max_freq);
5232         }
5233
5234         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5235                 /* Store the frequency values in 16.66 MHZ units, which is
5236                  * the natural hardware unit for SKL
5237                  */
5238                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5239                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5240                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5241                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5242                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5243         }
5244 }
5245
5246 static void reset_rps(struct drm_i915_private *dev_priv,
5247                       void (*set)(struct drm_i915_private *, u8))
5248 {
5249         u8 freq = dev_priv->rps.cur_freq;
5250
5251         /* force a reset */
5252         dev_priv->rps.power = -1;
5253         dev_priv->rps.cur_freq = -1;
5254
5255         set(dev_priv, freq);
5256 }
5257
5258 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
5259 static void gen9_enable_rps(struct drm_i915_private *dev_priv)
5260 {
5261         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5262
5263         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
5264         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5265                 /*
5266                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
5267                  * clear out the Control register just to avoid inconsitency
5268                  * with debugfs interface, which will show  Turbo as enabled
5269                  * only and that is not expected by the User after adding the
5270                  * WaGsvDisableTurbo. Apart from this there is no problem even
5271                  * if the Turbo is left enabled in the Control register, as the
5272                  * Up/Down interrupts would remain masked.
5273                  */
5274                 gen9_disable_rps(dev_priv);
5275                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5276                 return;
5277         }
5278
5279         /* Program defaults and thresholds for RPS*/
5280         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5281                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5282
5283         /* 1 second timeout*/
5284         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5285                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5286
5287         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
5288
5289         /* Leaning on the below call to gen6_set_rps to program/setup the
5290          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5291          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
5292         reset_rps(dev_priv, gen6_set_rps);
5293
5294         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5295 }
5296
5297 static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
5298 {
5299         struct intel_engine_cs *engine;
5300         uint32_t rc6_mask = 0;
5301
5302         /* 1a: Software RC state - RC0 */
5303         I915_WRITE(GEN6_RC_STATE, 0);
5304
5305         /* 1b: Get forcewake during program sequence. Although the driver
5306          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5307         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5308
5309         /* 2a: Disable RC states. */
5310         I915_WRITE(GEN6_RC_CONTROL, 0);
5311
5312         /* 2b: Program RC6 thresholds.*/
5313
5314         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
5315         if (IS_SKYLAKE(dev_priv))
5316                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5317         else
5318                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
5319         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5320         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5321         for_each_engine(engine, dev_priv)
5322                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5323
5324         if (HAS_GUC(dev_priv))
5325                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5326
5327         I915_WRITE(GEN6_RC_SLEEP, 0);
5328
5329         /* 2c: Program Coarse Power Gating Policies. */
5330         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5331         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5332
5333         /* 3a: Enable RC6 */
5334         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5335                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5336         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
5337         /* WaRsUseTimeoutMode */
5338         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
5339             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
5340                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
5341                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5342                            GEN7_RC_CTL_TO_MODE |
5343                            rc6_mask);
5344         } else {
5345                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
5346                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5347                            GEN6_RC_CTL_EI_MODE(1) |
5348                            rc6_mask);
5349         }
5350
5351         /*
5352          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
5353          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
5354          */
5355         if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
5356                 I915_WRITE(GEN9_PG_ENABLE, 0);
5357         else
5358                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5359                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
5360
5361         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5362 }
5363
5364 static void gen8_enable_rps(struct drm_i915_private *dev_priv)
5365 {
5366         struct intel_engine_cs *engine;
5367         uint32_t rc6_mask = 0;
5368
5369         /* 1a: Software RC state - RC0 */
5370         I915_WRITE(GEN6_RC_STATE, 0);
5371
5372         /* 1c & 1d: Get forcewake during program sequence. Although the driver
5373          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5374         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5375
5376         /* 2a: Disable RC states. */
5377         I915_WRITE(GEN6_RC_CONTROL, 0);
5378
5379         /* 2b: Program RC6 thresholds.*/
5380         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5381         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5382         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5383         for_each_engine(engine, dev_priv)
5384                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5385         I915_WRITE(GEN6_RC_SLEEP, 0);
5386         if (IS_BROADWELL(dev_priv))
5387                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5388         else
5389                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
5390
5391         /* 3: Enable RC6 */
5392         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
5393                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
5394         intel_print_rc6_info(dev_priv, rc6_mask);
5395         if (IS_BROADWELL(dev_priv))
5396                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5397                                 GEN7_RC_CTL_TO_MODE |
5398                                 rc6_mask);
5399         else
5400                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5401                                 GEN6_RC_CTL_EI_MODE(1) |
5402                                 rc6_mask);
5403
5404         /* 4 Program defaults and thresholds for RPS*/
5405         I915_WRITE(GEN6_RPNSWREQ,
5406                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5407         I915_WRITE(GEN6_RC_VIDEO_FREQ,
5408                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5409         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5410         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5411
5412         /* Docs recommend 900MHz, and 300 MHz respectively */
5413         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5414                    dev_priv->rps.max_freq_softlimit << 24 |
5415                    dev_priv->rps.min_freq_softlimit << 16);
5416
5417         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5418         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5419         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5420         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5421
5422         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5423
5424         /* 5: Enable RPS */
5425         I915_WRITE(GEN6_RP_CONTROL,
5426                    GEN6_RP_MEDIA_TURBO |
5427                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5428                    GEN6_RP_MEDIA_IS_GFX |
5429                    GEN6_RP_ENABLE |
5430                    GEN6_RP_UP_BUSY_AVG |
5431                    GEN6_RP_DOWN_IDLE_AVG);
5432
5433         /* 6: Ring frequency + overclocking (our driver does this later */
5434
5435         reset_rps(dev_priv, gen6_set_rps);
5436
5437         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5438 }
5439
5440 static void gen6_enable_rps(struct drm_i915_private *dev_priv)
5441 {
5442         struct intel_engine_cs *engine;
5443         u32 rc6vids, rc6_mask = 0;
5444         u32 gtfifodbg;
5445         int rc6_mode;
5446         int ret;
5447
5448         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5449
5450         /* Here begins a magic sequence of register writes to enable
5451          * auto-downclocking.
5452          *
5453          * Perhaps there might be some value in exposing these to
5454          * userspace...
5455          */
5456         I915_WRITE(GEN6_RC_STATE, 0);
5457
5458         /* Clear the DBG now so we don't confuse earlier errors */
5459         gtfifodbg = I915_READ(GTFIFODBG);
5460         if (gtfifodbg) {
5461                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5462                 I915_WRITE(GTFIFODBG, gtfifodbg);
5463         }
5464
5465         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5466
5467         /* disable the counters and set deterministic thresholds */
5468         I915_WRITE(GEN6_RC_CONTROL, 0);
5469
5470         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5471         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5472         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5473         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5474         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5475
5476         for_each_engine(engine, dev_priv)
5477                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5478
5479         I915_WRITE(GEN6_RC_SLEEP, 0);
5480         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5481         if (IS_IVYBRIDGE(dev_priv))
5482                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5483         else
5484                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5485         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5486         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5487
5488         /* Check if we are enabling RC6 */
5489         rc6_mode = intel_enable_rc6();
5490         if (rc6_mode & INTEL_RC6_ENABLE)
5491                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5492
5493         /* We don't use those on Haswell */
5494         if (!IS_HASWELL(dev_priv)) {
5495                 if (rc6_mode & INTEL_RC6p_ENABLE)
5496                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5497
5498                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5499                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5500         }
5501
5502         intel_print_rc6_info(dev_priv, rc6_mask);
5503
5504         I915_WRITE(GEN6_RC_CONTROL,
5505                    rc6_mask |
5506                    GEN6_RC_CTL_EI_MODE(1) |
5507                    GEN6_RC_CTL_HW_ENABLE);
5508
5509         /* Power down if completely idle for over 50ms */
5510         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5511         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5512
5513         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5514         if (ret)
5515                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5516
5517         reset_rps(dev_priv, gen6_set_rps);
5518
5519         rc6vids = 0;
5520         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5521         if (IS_GEN6(dev_priv) && ret) {
5522                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5523         } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5524                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5525                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5526                 rc6vids &= 0xffff00;
5527                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5528                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5529                 if (ret)
5530                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5531         }
5532
5533         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5534 }
5535
5536 static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
5537 {
5538         int min_freq = 15;
5539         unsigned int gpu_freq;
5540         unsigned int max_ia_freq, min_ring_freq;
5541         unsigned int max_gpu_freq, min_gpu_freq;
5542         int scaling_factor = 180;
5543         struct cpufreq_policy *policy;
5544
5545         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5546
5547         policy = cpufreq_cpu_get(0);
5548         if (policy) {
5549                 max_ia_freq = policy->cpuinfo.max_freq;
5550                 cpufreq_cpu_put(policy);
5551         } else {
5552                 /*
5553                  * Default to measured freq if none found, PCU will ensure we
5554                  * don't go over
5555                  */
5556                 max_ia_freq = tsc_khz;
5557         }
5558
5559         /* Convert from kHz to MHz */
5560         max_ia_freq /= 1000;
5561
5562         min_ring_freq = I915_READ(DCLK) & 0xf;
5563         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5564         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5565
5566         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5567                 /* Convert GT frequency to 50 HZ units */
5568                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5569                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5570         } else {
5571                 min_gpu_freq = dev_priv->rps.min_freq;
5572                 max_gpu_freq = dev_priv->rps.max_freq;
5573         }
5574
5575         /*
5576          * For each potential GPU frequency, load a ring frequency we'd like
5577          * to use for memory access.  We do this by specifying the IA frequency
5578          * the PCU should use as a reference to determine the ring frequency.
5579          */
5580         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5581                 int diff = max_gpu_freq - gpu_freq;
5582                 unsigned int ia_freq = 0, ring_freq = 0;
5583
5584                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
5585                         /*
5586                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5587                          * No floor required for ring frequency on SKL.
5588                          */
5589                         ring_freq = gpu_freq;
5590                 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
5591                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5592                         ring_freq = max(min_ring_freq, gpu_freq);
5593                 } else if (IS_HASWELL(dev_priv)) {
5594                         ring_freq = mult_frac(gpu_freq, 5, 4);
5595                         ring_freq = max(min_ring_freq, ring_freq);
5596                         /* leave ia_freq as the default, chosen by cpufreq */
5597                 } else {
5598                         /* On older processors, there is no separate ring
5599                          * clock domain, so in order to boost the bandwidth
5600                          * of the ring, we need to upclock the CPU (ia_freq).
5601                          *
5602                          * For GPU frequencies less than 750MHz,
5603                          * just use the lowest ring freq.
5604                          */
5605                         if (gpu_freq < min_freq)
5606                                 ia_freq = 800;
5607                         else
5608                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5609                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5610                 }
5611
5612                 sandybridge_pcode_write(dev_priv,
5613                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5614                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5615                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5616                                         gpu_freq);
5617         }
5618 }
5619
5620 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5621 {
5622         u32 val, rp0;
5623
5624         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5625
5626         switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5627         case 8:
5628                 /* (2 * 4) config */
5629                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5630                 break;
5631         case 12:
5632                 /* (2 * 6) config */
5633                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5634                 break;
5635         case 16:
5636                 /* (2 * 8) config */
5637         default:
5638                 /* Setting (2 * 8) Min RP0 for any other combination */
5639                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5640                 break;
5641         }
5642
5643         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5644
5645         return rp0;
5646 }
5647
5648 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5649 {
5650         u32 val, rpe;
5651
5652         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5653         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5654
5655         return rpe;
5656 }
5657
5658 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5659 {
5660         u32 val, rp1;
5661
5662         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5663         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5664
5665         return rp1;
5666 }
5667
5668 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5669 {
5670         u32 val, rp1;
5671
5672         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5673
5674         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5675
5676         return rp1;
5677 }
5678
5679 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5680 {
5681         u32 val, rp0;
5682
5683         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5684
5685         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5686         /* Clamp to max */
5687         rp0 = min_t(u32, rp0, 0xea);
5688
5689         return rp0;
5690 }
5691
5692 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5693 {
5694         u32 val, rpe;
5695
5696         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5697         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5698         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5699         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5700
5701         return rpe;
5702 }
5703
5704 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5705 {
5706         u32 val;
5707
5708         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5709         /*
5710          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5711          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5712          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5713          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5714          * to make sure it matches what Punit accepts.
5715          */
5716         return max_t(u32, val, 0xc0);
5717 }
5718
5719 /* Check that the pctx buffer wasn't move under us. */
5720 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5721 {
5722         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5723
5724         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5725                              dev_priv->vlv_pctx->stolen->start);
5726 }
5727
5728
5729 /* Check that the pcbr address is not empty. */
5730 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5731 {
5732         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5733
5734         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5735 }
5736
5737 static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
5738 {
5739         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5740         unsigned long pctx_paddr, paddr;
5741         u32 pcbr;
5742         int pctx_size = 32*1024;
5743
5744         pcbr = I915_READ(VLV_PCBR);
5745         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5746                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5747                 paddr = (dev_priv->mm.stolen_base +
5748                          (ggtt->stolen_size - pctx_size));
5749
5750                 pctx_paddr = (paddr & (~4095));
5751                 I915_WRITE(VLV_PCBR, pctx_paddr);
5752         }
5753
5754         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5755 }
5756
5757 static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
5758 {
5759         struct drm_i915_gem_object *pctx;
5760         unsigned long pctx_paddr;
5761         u32 pcbr;
5762         int pctx_size = 24*1024;
5763
5764         pcbr = I915_READ(VLV_PCBR);
5765         if (pcbr) {
5766                 /* BIOS set it up already, grab the pre-alloc'd space */
5767                 int pcbr_offset;
5768
5769                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5770                 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
5771                                                                       pcbr_offset,
5772                                                                       I915_GTT_OFFSET_NONE,
5773                                                                       pctx_size);
5774                 goto out;
5775         }
5776
5777         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5778
5779         /*
5780          * From the Gunit register HAS:
5781          * The Gfx driver is expected to program this register and ensure
5782          * proper allocation within Gfx stolen memory.  For example, this
5783          * register should be programmed such than the PCBR range does not
5784          * overlap with other ranges, such as the frame buffer, protected
5785          * memory, or any other relevant ranges.
5786          */
5787         pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
5788         if (!pctx) {
5789                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5790                 goto out;
5791         }
5792
5793         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5794         I915_WRITE(VLV_PCBR, pctx_paddr);
5795
5796 out:
5797         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5798         dev_priv->vlv_pctx = pctx;
5799 }
5800
5801 static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
5802 {
5803         if (WARN_ON(!dev_priv->vlv_pctx))
5804                 return;
5805
5806         i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
5807         dev_priv->vlv_pctx = NULL;
5808 }
5809
5810 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5811 {
5812         dev_priv->rps.gpll_ref_freq =
5813                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5814                                   CCK_GPLL_CLOCK_CONTROL,
5815                                   dev_priv->czclk_freq);
5816
5817         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5818                          dev_priv->rps.gpll_ref_freq);
5819 }
5820
5821 static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
5822 {
5823         u32 val;
5824
5825         valleyview_setup_pctx(dev_priv);
5826
5827         vlv_init_gpll_ref_freq(dev_priv);
5828
5829         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5830         switch ((val >> 6) & 3) {
5831         case 0:
5832         case 1:
5833                 dev_priv->mem_freq = 800;
5834                 break;
5835         case 2:
5836                 dev_priv->mem_freq = 1066;
5837                 break;
5838         case 3:
5839                 dev_priv->mem_freq = 1333;
5840                 break;
5841         }
5842         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5843
5844         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5845         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5846         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5847                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5848                          dev_priv->rps.max_freq);
5849
5850         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5851         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5852                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5853                          dev_priv->rps.efficient_freq);
5854
5855         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5856         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5857                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5858                          dev_priv->rps.rp1_freq);
5859
5860         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5861         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5862                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5863                          dev_priv->rps.min_freq);
5864 }
5865
5866 static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
5867 {
5868         u32 val;
5869
5870         cherryview_setup_pctx(dev_priv);
5871
5872         vlv_init_gpll_ref_freq(dev_priv);
5873
5874         mutex_lock(&dev_priv->sb_lock);
5875         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5876         mutex_unlock(&dev_priv->sb_lock);
5877
5878         switch ((val >> 2) & 0x7) {
5879         case 3:
5880                 dev_priv->mem_freq = 2000;
5881                 break;
5882         default:
5883                 dev_priv->mem_freq = 1600;
5884                 break;
5885         }
5886         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5887
5888         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5889         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5890         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5891                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5892                          dev_priv->rps.max_freq);
5893
5894         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5895         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5896                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5897                          dev_priv->rps.efficient_freq);
5898
5899         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5900         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5901                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5902                          dev_priv->rps.rp1_freq);
5903
5904         /* PUnit validated range is only [RPe, RP0] */
5905         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5906         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5907                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5908                          dev_priv->rps.min_freq);
5909
5910         WARN_ONCE((dev_priv->rps.max_freq |
5911                    dev_priv->rps.efficient_freq |
5912                    dev_priv->rps.rp1_freq |
5913                    dev_priv->rps.min_freq) & 1,
5914                   "Odd GPU freq values\n");
5915 }
5916
5917 static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
5918 {
5919         valleyview_cleanup_pctx(dev_priv);
5920 }
5921
5922 static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
5923 {
5924         struct intel_engine_cs *engine;
5925         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5926
5927         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5928
5929         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5930                                              GT_FIFO_FREE_ENTRIES_CHV);
5931         if (gtfifodbg) {
5932                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5933                                  gtfifodbg);
5934                 I915_WRITE(GTFIFODBG, gtfifodbg);
5935         }
5936
5937         cherryview_check_pctx(dev_priv);
5938
5939         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5940          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5941         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5942
5943         /*  Disable RC states. */
5944         I915_WRITE(GEN6_RC_CONTROL, 0);
5945
5946         /* 2a: Program RC6 thresholds.*/
5947         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5948         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5949         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5950
5951         for_each_engine(engine, dev_priv)
5952                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5953         I915_WRITE(GEN6_RC_SLEEP, 0);
5954
5955         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5956         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5957
5958         /* allows RC6 residency counter to work */
5959         I915_WRITE(VLV_COUNTER_CONTROL,
5960                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5961                                       VLV_MEDIA_RC6_COUNT_EN |
5962                                       VLV_RENDER_RC6_COUNT_EN));
5963
5964         /* For now we assume BIOS is allocating and populating the PCBR  */
5965         pcbr = I915_READ(VLV_PCBR);
5966
5967         /* 3: Enable RC6 */
5968         if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
5969             (pcbr >> VLV_PCBR_ADDR_SHIFT))
5970                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5971
5972         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5973
5974         /* 4 Program defaults and thresholds for RPS*/
5975         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5976         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5977         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5978         I915_WRITE(GEN6_RP_UP_EI, 66000);
5979         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5980
5981         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5982
5983         /* 5: Enable RPS */
5984         I915_WRITE(GEN6_RP_CONTROL,
5985                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5986                    GEN6_RP_MEDIA_IS_GFX |
5987                    GEN6_RP_ENABLE |
5988                    GEN6_RP_UP_BUSY_AVG |
5989                    GEN6_RP_DOWN_IDLE_AVG);
5990
5991         /* Setting Fixed Bias */
5992         val = VLV_OVERRIDE_EN |
5993                   VLV_SOC_TDP_EN |
5994                   CHV_BIAS_CPU_50_SOC_50;
5995         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5996
5997         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5998
5999         /* RPS code assumes GPLL is used */
6000         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6001
6002         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6003         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6004
6005         reset_rps(dev_priv, valleyview_set_rps);
6006
6007         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6008 }
6009
6010 static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
6011 {
6012         struct intel_engine_cs *engine;
6013         u32 gtfifodbg, val, rc6_mode = 0;
6014
6015         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6016
6017         valleyview_check_pctx(dev_priv);
6018
6019         gtfifodbg = I915_READ(GTFIFODBG);
6020         if (gtfifodbg) {
6021                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6022                                  gtfifodbg);
6023                 I915_WRITE(GTFIFODBG, gtfifodbg);
6024         }
6025
6026         /* If VLV, Forcewake all wells, else re-direct to regular path */
6027         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6028
6029         /*  Disable RC states. */
6030         I915_WRITE(GEN6_RC_CONTROL, 0);
6031
6032         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6033         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6034         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6035         I915_WRITE(GEN6_RP_UP_EI, 66000);
6036         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6037
6038         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6039
6040         I915_WRITE(GEN6_RP_CONTROL,
6041                    GEN6_RP_MEDIA_TURBO |
6042                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
6043                    GEN6_RP_MEDIA_IS_GFX |
6044                    GEN6_RP_ENABLE |
6045                    GEN6_RP_UP_BUSY_AVG |
6046                    GEN6_RP_DOWN_IDLE_CONT);
6047
6048         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6049         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6050         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6051
6052         for_each_engine(engine, dev_priv)
6053                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6054
6055         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
6056
6057         /* allows RC6 residency counter to work */
6058         I915_WRITE(VLV_COUNTER_CONTROL,
6059                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6060                                       VLV_RENDER_RC0_COUNT_EN |
6061                                       VLV_MEDIA_RC6_COUNT_EN |
6062                                       VLV_RENDER_RC6_COUNT_EN));
6063
6064         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6065                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
6066
6067         intel_print_rc6_info(dev_priv, rc6_mode);
6068
6069         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6070
6071         /* Setting Fixed Bias */
6072         val = VLV_OVERRIDE_EN |
6073                   VLV_SOC_TDP_EN |
6074                   VLV_BIAS_CPU_125_SOC_875;
6075         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6076
6077         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6078
6079         /* RPS code assumes GPLL is used */
6080         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6081
6082         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
6083         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6084
6085         reset_rps(dev_priv, valleyview_set_rps);
6086
6087         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6088 }
6089
6090 static unsigned long intel_pxfreq(u32 vidfreq)
6091 {
6092         unsigned long freq;
6093         int div = (vidfreq & 0x3f0000) >> 16;
6094         int post = (vidfreq & 0x3000) >> 12;
6095         int pre = (vidfreq & 0x7);
6096
6097         if (!pre)
6098                 return 0;
6099
6100         freq = ((div * 133333) / ((1<<post) * pre));
6101
6102         return freq;
6103 }
6104
6105 static const struct cparams {
6106         u16 i;
6107         u16 t;
6108         u16 m;
6109         u16 c;
6110 } cparams[] = {
6111         { 1, 1333, 301, 28664 },
6112         { 1, 1066, 294, 24460 },
6113         { 1, 800, 294, 25192 },
6114         { 0, 1333, 276, 27605 },
6115         { 0, 1066, 276, 27605 },
6116         { 0, 800, 231, 23784 },
6117 };
6118
6119 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
6120 {
6121         u64 total_count, diff, ret;
6122         u32 count1, count2, count3, m = 0, c = 0;
6123         unsigned long now = jiffies_to_msecs(jiffies), diff1;
6124         int i;
6125
6126         assert_spin_locked(&mchdev_lock);
6127
6128         diff1 = now - dev_priv->ips.last_time1;
6129
6130         /* Prevent division-by-zero if we are asking too fast.
6131          * Also, we don't get interesting results if we are polling
6132          * faster than once in 10ms, so just return the saved value
6133          * in such cases.
6134          */
6135         if (diff1 <= 10)
6136                 return dev_priv->ips.chipset_power;
6137
6138         count1 = I915_READ(DMIEC);
6139         count2 = I915_READ(DDREC);
6140         count3 = I915_READ(CSIEC);
6141
6142         total_count = count1 + count2 + count3;
6143
6144         /* FIXME: handle per-counter overflow */
6145         if (total_count < dev_priv->ips.last_count1) {
6146                 diff = ~0UL - dev_priv->ips.last_count1;
6147                 diff += total_count;
6148         } else {
6149                 diff = total_count - dev_priv->ips.last_count1;
6150         }
6151
6152         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
6153                 if (cparams[i].i == dev_priv->ips.c_m &&
6154                     cparams[i].t == dev_priv->ips.r_t) {
6155                         m = cparams[i].m;
6156                         c = cparams[i].c;
6157                         break;
6158                 }
6159         }
6160
6161         diff = div_u64(diff, diff1);
6162         ret = ((m * diff) + c);
6163         ret = div_u64(ret, 10);
6164
6165         dev_priv->ips.last_count1 = total_count;
6166         dev_priv->ips.last_time1 = now;
6167
6168         dev_priv->ips.chipset_power = ret;
6169
6170         return ret;
6171 }
6172
6173 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6174 {
6175         unsigned long val;
6176
6177         if (INTEL_INFO(dev_priv)->gen != 5)
6178                 return 0;
6179
6180         spin_lock_irq(&mchdev_lock);
6181
6182         val = __i915_chipset_val(dev_priv);
6183
6184         spin_unlock_irq(&mchdev_lock);
6185
6186         return val;
6187 }
6188
6189 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6190 {
6191         unsigned long m, x, b;
6192         u32 tsfs;
6193
6194         tsfs = I915_READ(TSFS);
6195
6196         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6197         x = I915_READ8(TR1);
6198
6199         b = tsfs & TSFS_INTR_MASK;
6200
6201         return ((m * x) / 127) - b;
6202 }
6203
6204 static int _pxvid_to_vd(u8 pxvid)
6205 {
6206         if (pxvid == 0)
6207                 return 0;
6208
6209         if (pxvid >= 8 && pxvid < 31)
6210                 pxvid = 31;
6211
6212         return (pxvid + 2) * 125;
6213 }
6214
6215 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
6216 {
6217         const int vd = _pxvid_to_vd(pxvid);
6218         const int vm = vd - 1125;
6219
6220         if (INTEL_INFO(dev_priv)->is_mobile)
6221                 return vm > 0 ? vm : 0;
6222
6223         return vd;
6224 }
6225
6226 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
6227 {
6228         u64 now, diff, diffms;
6229         u32 count;
6230
6231         assert_spin_locked(&mchdev_lock);
6232
6233         now = ktime_get_raw_ns();
6234         diffms = now - dev_priv->ips.last_time2;
6235         do_div(diffms, NSEC_PER_MSEC);
6236
6237         /* Don't divide by 0 */
6238         if (!diffms)
6239                 return;
6240
6241         count = I915_READ(GFXEC);
6242
6243         if (count < dev_priv->ips.last_count2) {
6244                 diff = ~0UL - dev_priv->ips.last_count2;
6245                 diff += count;
6246         } else {
6247                 diff = count - dev_priv->ips.last_count2;
6248         }
6249
6250         dev_priv->ips.last_count2 = count;
6251         dev_priv->ips.last_time2 = now;
6252
6253         /* More magic constants... */
6254         diff = diff * 1181;
6255         diff = div_u64(diff, diffms * 10);
6256         dev_priv->ips.gfx_power = diff;
6257 }
6258
6259 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6260 {
6261         if (INTEL_INFO(dev_priv)->gen != 5)
6262                 return;
6263
6264         spin_lock_irq(&mchdev_lock);
6265
6266         __i915_update_gfx_val(dev_priv);
6267
6268         spin_unlock_irq(&mchdev_lock);
6269 }
6270
6271 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
6272 {
6273         unsigned long t, corr, state1, corr2, state2;
6274         u32 pxvid, ext_v;
6275
6276         assert_spin_locked(&mchdev_lock);
6277
6278         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
6279         pxvid = (pxvid >> 24) & 0x7f;
6280         ext_v = pvid_to_extvid(dev_priv, pxvid);
6281
6282         state1 = ext_v;
6283
6284         t = i915_mch_val(dev_priv);
6285
6286         /* Revel in the empirically derived constants */
6287
6288         /* Correction factor in 1/100000 units */
6289         if (t > 80)
6290                 corr = ((t * 2349) + 135940);
6291         else if (t >= 50)
6292                 corr = ((t * 964) + 29317);
6293         else /* < 50 */
6294                 corr = ((t * 301) + 1004);
6295
6296         corr = corr * ((150142 * state1) / 10000 - 78642);
6297         corr /= 100000;
6298         corr2 = (corr * dev_priv->ips.corr);
6299
6300         state2 = (corr2 * state1) / 10000;
6301         state2 /= 100; /* convert to mW */
6302
6303         __i915_update_gfx_val(dev_priv);
6304
6305         return dev_priv->ips.gfx_power + state2;
6306 }
6307
6308 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6309 {
6310         unsigned long val;
6311
6312         if (INTEL_INFO(dev_priv)->gen != 5)
6313                 return 0;
6314
6315         spin_lock_irq(&mchdev_lock);
6316
6317         val = __i915_gfx_val(dev_priv);
6318
6319         spin_unlock_irq(&mchdev_lock);
6320
6321         return val;
6322 }
6323
6324 /**
6325  * i915_read_mch_val - return value for IPS use
6326  *
6327  * Calculate and return a value for the IPS driver to use when deciding whether
6328  * we have thermal and power headroom to increase CPU or GPU power budget.
6329  */
6330 unsigned long i915_read_mch_val(void)
6331 {
6332         struct drm_i915_private *dev_priv;
6333         unsigned long chipset_val, graphics_val, ret = 0;
6334
6335         spin_lock_irq(&mchdev_lock);
6336         if (!i915_mch_dev)
6337                 goto out_unlock;
6338         dev_priv = i915_mch_dev;
6339
6340         chipset_val = __i915_chipset_val(dev_priv);
6341         graphics_val = __i915_gfx_val(dev_priv);
6342
6343         ret = chipset_val + graphics_val;
6344
6345 out_unlock:
6346         spin_unlock_irq(&mchdev_lock);
6347
6348         return ret;
6349 }
6350 EXPORT_SYMBOL_GPL(i915_read_mch_val);
6351
6352 /**
6353  * i915_gpu_raise - raise GPU frequency limit
6354  *
6355  * Raise the limit; IPS indicates we have thermal headroom.
6356  */
6357 bool i915_gpu_raise(void)
6358 {
6359         struct drm_i915_private *dev_priv;
6360         bool ret = true;
6361
6362         spin_lock_irq(&mchdev_lock);
6363         if (!i915_mch_dev) {
6364                 ret = false;
6365                 goto out_unlock;
6366         }
6367         dev_priv = i915_mch_dev;
6368
6369         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6370                 dev_priv->ips.max_delay--;
6371
6372 out_unlock:
6373         spin_unlock_irq(&mchdev_lock);
6374
6375         return ret;
6376 }
6377 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6378
6379 /**
6380  * i915_gpu_lower - lower GPU frequency limit
6381  *
6382  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6383  * frequency maximum.
6384  */
6385 bool i915_gpu_lower(void)
6386 {
6387         struct drm_i915_private *dev_priv;
6388         bool ret = true;
6389
6390         spin_lock_irq(&mchdev_lock);
6391         if (!i915_mch_dev) {
6392                 ret = false;
6393                 goto out_unlock;
6394         }
6395         dev_priv = i915_mch_dev;
6396
6397         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6398                 dev_priv->ips.max_delay++;
6399
6400 out_unlock:
6401         spin_unlock_irq(&mchdev_lock);
6402
6403         return ret;
6404 }
6405 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6406
6407 /**
6408  * i915_gpu_busy - indicate GPU business to IPS
6409  *
6410  * Tell the IPS driver whether or not the GPU is busy.
6411  */
6412 bool i915_gpu_busy(void)
6413 {
6414         bool ret = false;
6415
6416         spin_lock_irq(&mchdev_lock);
6417         if (i915_mch_dev)
6418                 ret = i915_mch_dev->gt.awake;
6419         spin_unlock_irq(&mchdev_lock);
6420
6421         return ret;
6422 }
6423 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6424
6425 /**
6426  * i915_gpu_turbo_disable - disable graphics turbo
6427  *
6428  * Disable graphics turbo by resetting the max frequency and setting the
6429  * current frequency to the default.
6430  */
6431 bool i915_gpu_turbo_disable(void)
6432 {
6433         struct drm_i915_private *dev_priv;
6434         bool ret = true;
6435
6436         spin_lock_irq(&mchdev_lock);
6437         if (!i915_mch_dev) {
6438                 ret = false;
6439                 goto out_unlock;
6440         }
6441         dev_priv = i915_mch_dev;
6442
6443         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6444
6445         if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
6446                 ret = false;
6447
6448 out_unlock:
6449         spin_unlock_irq(&mchdev_lock);
6450
6451         return ret;
6452 }
6453 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6454
6455 /**
6456  * Tells the intel_ips driver that the i915 driver is now loaded, if
6457  * IPS got loaded first.
6458  *
6459  * This awkward dance is so that neither module has to depend on the
6460  * other in order for IPS to do the appropriate communication of
6461  * GPU turbo limits to i915.
6462  */
6463 static void
6464 ips_ping_for_i915_load(void)
6465 {
6466         void (*link)(void);
6467
6468         link = symbol_get(ips_link_to_i915_driver);
6469         if (link) {
6470                 link();
6471                 symbol_put(ips_link_to_i915_driver);
6472         }
6473 }
6474
6475 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6476 {
6477         /* We only register the i915 ips part with intel-ips once everything is
6478          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6479         spin_lock_irq(&mchdev_lock);
6480         i915_mch_dev = dev_priv;
6481         spin_unlock_irq(&mchdev_lock);
6482
6483         ips_ping_for_i915_load();
6484 }
6485
6486 void intel_gpu_ips_teardown(void)
6487 {
6488         spin_lock_irq(&mchdev_lock);
6489         i915_mch_dev = NULL;
6490         spin_unlock_irq(&mchdev_lock);
6491 }
6492
6493 static void intel_init_emon(struct drm_i915_private *dev_priv)
6494 {
6495         u32 lcfuse;
6496         u8 pxw[16];
6497         int i;
6498
6499         /* Disable to program */
6500         I915_WRITE(ECR, 0);
6501         POSTING_READ(ECR);
6502
6503         /* Program energy weights for various events */
6504         I915_WRITE(SDEW, 0x15040d00);
6505         I915_WRITE(CSIEW0, 0x007f0000);
6506         I915_WRITE(CSIEW1, 0x1e220004);
6507         I915_WRITE(CSIEW2, 0x04000004);
6508
6509         for (i = 0; i < 5; i++)
6510                 I915_WRITE(PEW(i), 0);
6511         for (i = 0; i < 3; i++)
6512                 I915_WRITE(DEW(i), 0);
6513
6514         /* Program P-state weights to account for frequency power adjustment */
6515         for (i = 0; i < 16; i++) {
6516                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6517                 unsigned long freq = intel_pxfreq(pxvidfreq);
6518                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6519                         PXVFREQ_PX_SHIFT;
6520                 unsigned long val;
6521
6522                 val = vid * vid;
6523                 val *= (freq / 1000);
6524                 val *= 255;
6525                 val /= (127*127*900);
6526                 if (val > 0xff)
6527                         DRM_ERROR("bad pxval: %ld\n", val);
6528                 pxw[i] = val;
6529         }
6530         /* Render standby states get 0 weight */
6531         pxw[14] = 0;
6532         pxw[15] = 0;
6533
6534         for (i = 0; i < 4; i++) {
6535                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6536                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6537                 I915_WRITE(PXW(i), val);
6538         }
6539
6540         /* Adjust magic regs to magic values (more experimental results) */
6541         I915_WRITE(OGW0, 0);
6542         I915_WRITE(OGW1, 0);
6543         I915_WRITE(EG0, 0x00007f00);
6544         I915_WRITE(EG1, 0x0000000e);
6545         I915_WRITE(EG2, 0x000e0000);
6546         I915_WRITE(EG3, 0x68000300);
6547         I915_WRITE(EG4, 0x42000000);
6548         I915_WRITE(EG5, 0x00140031);
6549         I915_WRITE(EG6, 0);
6550         I915_WRITE(EG7, 0);
6551
6552         for (i = 0; i < 8; i++)
6553                 I915_WRITE(PXWL(i), 0);
6554
6555         /* Enable PMON + select events */
6556         I915_WRITE(ECR, 0x80000019);
6557
6558         lcfuse = I915_READ(LCFUSE02);
6559
6560         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6561 }
6562
6563 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
6564 {
6565         /*
6566          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6567          * requirement.
6568          */
6569         if (!i915.enable_rc6) {
6570                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6571                 intel_runtime_pm_get(dev_priv);
6572         }
6573
6574         mutex_lock(&dev_priv->drm.struct_mutex);
6575         mutex_lock(&dev_priv->rps.hw_lock);
6576
6577         /* Initialize RPS limits (for userspace) */
6578         if (IS_CHERRYVIEW(dev_priv))
6579                 cherryview_init_gt_powersave(dev_priv);
6580         else if (IS_VALLEYVIEW(dev_priv))
6581                 valleyview_init_gt_powersave(dev_priv);
6582         else if (INTEL_GEN(dev_priv) >= 6)
6583                 gen6_init_rps_frequencies(dev_priv);
6584
6585         /* Derive initial user preferences/limits from the hardware limits */
6586         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6587         dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6588
6589         dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6590         dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6591
6592         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6593                 dev_priv->rps.min_freq_softlimit =
6594                         max_t(int,
6595                               dev_priv->rps.efficient_freq,
6596                               intel_freq_opcode(dev_priv, 450));
6597
6598         /* After setting max-softlimit, find the overclock max freq */
6599         if (IS_GEN6(dev_priv) ||
6600             IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6601                 u32 params = 0;
6602
6603                 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6604                 if (params & BIT(31)) { /* OC supported */
6605                         DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6606                                          (dev_priv->rps.max_freq & 0xff) * 50,
6607                                          (params & 0xff) * 50);
6608                         dev_priv->rps.max_freq = params & 0xff;
6609                 }
6610         }
6611
6612         /* Finally allow us to boost to max by default */
6613         dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6614
6615         mutex_unlock(&dev_priv->rps.hw_lock);
6616         mutex_unlock(&dev_priv->drm.struct_mutex);
6617
6618         intel_autoenable_gt_powersave(dev_priv);
6619 }
6620
6621 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
6622 {
6623         if (IS_VALLEYVIEW(dev_priv))
6624                 valleyview_cleanup_gt_powersave(dev_priv);
6625
6626         if (!i915.enable_rc6)
6627                 intel_runtime_pm_put(dev_priv);
6628 }
6629
6630 /**
6631  * intel_suspend_gt_powersave - suspend PM work and helper threads
6632  * @dev_priv: i915 device
6633  *
6634  * We don't want to disable RC6 or other features here, we just want
6635  * to make sure any work we've queued has finished and won't bother
6636  * us while we're suspended.
6637  */
6638 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6639 {
6640         if (INTEL_GEN(dev_priv) < 6)
6641                 return;
6642
6643         if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6644                 intel_runtime_pm_put(dev_priv);
6645
6646         /* gen6_rps_idle() will be called later to disable interrupts */
6647 }
6648
6649 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6650 {
6651         dev_priv->rps.enabled = true; /* force disabling */
6652         intel_disable_gt_powersave(dev_priv);
6653
6654         gen6_reset_rps_interrupts(dev_priv);
6655 }
6656
6657 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
6658 {
6659         if (!READ_ONCE(dev_priv->rps.enabled))
6660                 return;
6661
6662         mutex_lock(&dev_priv->rps.hw_lock);
6663
6664         if (INTEL_GEN(dev_priv) >= 9) {
6665                 gen9_disable_rc6(dev_priv);
6666                 gen9_disable_rps(dev_priv);
6667         } else if (IS_CHERRYVIEW(dev_priv)) {
6668                 cherryview_disable_rps(dev_priv);
6669         } else if (IS_VALLEYVIEW(dev_priv)) {
6670                 valleyview_disable_rps(dev_priv);
6671         } else if (INTEL_GEN(dev_priv) >= 6) {
6672                 gen6_disable_rps(dev_priv);
6673         }  else if (IS_IRONLAKE_M(dev_priv)) {
6674                 ironlake_disable_drps(dev_priv);
6675         }
6676
6677         dev_priv->rps.enabled = false;
6678         mutex_unlock(&dev_priv->rps.hw_lock);
6679 }
6680
6681 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
6682 {
6683         /* We shouldn't be disabling as we submit, so this should be less
6684          * racy than it appears!
6685          */
6686         if (READ_ONCE(dev_priv->rps.enabled))
6687                 return;
6688
6689         /* Powersaving is controlled by the host when inside a VM */
6690         if (intel_vgpu_active(dev_priv))
6691                 return;
6692
6693         mutex_lock(&dev_priv->rps.hw_lock);
6694
6695         if (IS_CHERRYVIEW(dev_priv)) {
6696                 cherryview_enable_rps(dev_priv);
6697         } else if (IS_VALLEYVIEW(dev_priv)) {
6698                 valleyview_enable_rps(dev_priv);
6699         } else if (INTEL_GEN(dev_priv) >= 9) {
6700                 gen9_enable_rc6(dev_priv);
6701                 gen9_enable_rps(dev_priv);
6702                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
6703                         gen6_update_ring_freq(dev_priv);
6704         } else if (IS_BROADWELL(dev_priv)) {
6705                 gen8_enable_rps(dev_priv);
6706                 gen6_update_ring_freq(dev_priv);
6707         } else if (INTEL_GEN(dev_priv) >= 6) {
6708                 gen6_enable_rps(dev_priv);
6709                 gen6_update_ring_freq(dev_priv);
6710         } else if (IS_IRONLAKE_M(dev_priv)) {
6711                 ironlake_enable_drps(dev_priv);
6712                 intel_init_emon(dev_priv);
6713         }
6714
6715         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6716         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6717
6718         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6719         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6720
6721         dev_priv->rps.enabled = true;
6722         mutex_unlock(&dev_priv->rps.hw_lock);
6723 }
6724
6725 static void __intel_autoenable_gt_powersave(struct work_struct *work)
6726 {
6727         struct drm_i915_private *dev_priv =
6728                 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6729         struct intel_engine_cs *rcs;
6730         struct drm_i915_gem_request *req;
6731
6732         if (READ_ONCE(dev_priv->rps.enabled))
6733                 goto out;
6734
6735         rcs = &dev_priv->engine[RCS];
6736         if (rcs->last_context)
6737                 goto out;
6738
6739         if (!rcs->init_context)
6740                 goto out;
6741
6742         mutex_lock(&dev_priv->drm.struct_mutex);
6743
6744         req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6745         if (IS_ERR(req))
6746                 goto unlock;
6747
6748         if (!i915.enable_execlists && i915_switch_context(req) == 0)
6749                 rcs->init_context(req);
6750
6751         /* Mark the device busy, calling intel_enable_gt_powersave() */
6752         i915_add_request_no_flush(req);
6753
6754 unlock:
6755         mutex_unlock(&dev_priv->drm.struct_mutex);
6756 out:
6757         intel_runtime_pm_put(dev_priv);
6758 }
6759
6760 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6761 {
6762         if (READ_ONCE(dev_priv->rps.enabled))
6763                 return;
6764
6765         if (IS_IRONLAKE_M(dev_priv)) {
6766                 ironlake_enable_drps(dev_priv);
6767                 intel_init_emon(dev_priv);
6768         } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6769                 /*
6770                  * PCU communication is slow and this doesn't need to be
6771                  * done at any specific time, so do this out of our fast path
6772                  * to make resume and init faster.
6773                  *
6774                  * We depend on the HW RC6 power context save/restore
6775                  * mechanism when entering D3 through runtime PM suspend. So
6776                  * disable RPM until RPS/RC6 is properly setup. We can only
6777                  * get here via the driver load/system resume/runtime resume
6778                  * paths, so the _noresume version is enough (and in case of
6779                  * runtime resume it's necessary).
6780                  */
6781                 if (queue_delayed_work(dev_priv->wq,
6782                                        &dev_priv->rps.autoenable_work,
6783                                        round_jiffies_up_relative(HZ)))
6784                         intel_runtime_pm_get_noresume(dev_priv);
6785         }
6786 }
6787
6788 static void ibx_init_clock_gating(struct drm_device *dev)
6789 {
6790         struct drm_i915_private *dev_priv = to_i915(dev);
6791
6792         /*
6793          * On Ibex Peak and Cougar Point, we need to disable clock
6794          * gating for the panel power sequencer or it will fail to
6795          * start up when no ports are active.
6796          */
6797         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6798 }
6799
6800 static void g4x_disable_trickle_feed(struct drm_device *dev)
6801 {
6802         struct drm_i915_private *dev_priv = to_i915(dev);
6803         enum pipe pipe;
6804
6805         for_each_pipe(dev_priv, pipe) {
6806                 I915_WRITE(DSPCNTR(pipe),
6807                            I915_READ(DSPCNTR(pipe)) |
6808                            DISPPLANE_TRICKLE_FEED_DISABLE);
6809
6810                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6811                 POSTING_READ(DSPSURF(pipe));
6812         }
6813 }
6814
6815 static void ilk_init_lp_watermarks(struct drm_device *dev)
6816 {
6817         struct drm_i915_private *dev_priv = to_i915(dev);
6818
6819         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6820         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6821         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6822
6823         /*
6824          * Don't touch WM1S_LP_EN here.
6825          * Doing so could cause underruns.
6826          */
6827 }
6828
6829 static void ironlake_init_clock_gating(struct drm_device *dev)
6830 {
6831         struct drm_i915_private *dev_priv = to_i915(dev);
6832         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6833
6834         /*
6835          * Required for FBC
6836          * WaFbcDisableDpfcClockGating:ilk
6837          */
6838         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6839                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6840                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6841
6842         I915_WRITE(PCH_3DCGDIS0,
6843                    MARIUNIT_CLOCK_GATE_DISABLE |
6844                    SVSMUNIT_CLOCK_GATE_DISABLE);
6845         I915_WRITE(PCH_3DCGDIS1,
6846                    VFMUNIT_CLOCK_GATE_DISABLE);
6847
6848         /*
6849          * According to the spec the following bits should be set in
6850          * order to enable memory self-refresh
6851          * The bit 22/21 of 0x42004
6852          * The bit 5 of 0x42020
6853          * The bit 15 of 0x45000
6854          */
6855         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6856                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6857                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6858         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6859         I915_WRITE(DISP_ARB_CTL,
6860                    (I915_READ(DISP_ARB_CTL) |
6861                     DISP_FBC_WM_DIS));
6862
6863         ilk_init_lp_watermarks(dev);
6864
6865         /*
6866          * Based on the document from hardware guys the following bits
6867          * should be set unconditionally in order to enable FBC.
6868          * The bit 22 of 0x42000
6869          * The bit 22 of 0x42004
6870          * The bit 7,8,9 of 0x42020.
6871          */
6872         if (IS_IRONLAKE_M(dev)) {
6873                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6874                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6875                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6876                            ILK_FBCQ_DIS);
6877                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6878                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6879                            ILK_DPARB_GATE);
6880         }
6881
6882         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6883
6884         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6885                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6886                    ILK_ELPIN_409_SELECT);
6887         I915_WRITE(_3D_CHICKEN2,
6888                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6889                    _3D_CHICKEN2_WM_READ_PIPELINED);
6890
6891         /* WaDisableRenderCachePipelinedFlush:ilk */
6892         I915_WRITE(CACHE_MODE_0,
6893                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6894
6895         /* WaDisable_RenderCache_OperationalFlush:ilk */
6896         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6897
6898         g4x_disable_trickle_feed(dev);
6899
6900         ibx_init_clock_gating(dev);
6901 }
6902
6903 static void cpt_init_clock_gating(struct drm_device *dev)
6904 {
6905         struct drm_i915_private *dev_priv = to_i915(dev);
6906         int pipe;
6907         uint32_t val;
6908
6909         /*
6910          * On Ibex Peak and Cougar Point, we need to disable clock
6911          * gating for the panel power sequencer or it will fail to
6912          * start up when no ports are active.
6913          */
6914         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6915                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6916                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6917         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6918                    DPLS_EDP_PPS_FIX_DIS);
6919         /* The below fixes the weird display corruption, a few pixels shifted
6920          * downward, on (only) LVDS of some HP laptops with IVY.
6921          */
6922         for_each_pipe(dev_priv, pipe) {
6923                 val = I915_READ(TRANS_CHICKEN2(pipe));
6924                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6925                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6926                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6927                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6928                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6929                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6930                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6931                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6932         }
6933         /* WADP0ClockGatingDisable */
6934         for_each_pipe(dev_priv, pipe) {
6935                 I915_WRITE(TRANS_CHICKEN1(pipe),
6936                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6937         }
6938 }
6939
6940 static void gen6_check_mch_setup(struct drm_device *dev)
6941 {
6942         struct drm_i915_private *dev_priv = to_i915(dev);
6943         uint32_t tmp;
6944
6945         tmp = I915_READ(MCH_SSKPD);
6946         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6947                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6948                               tmp);
6949 }
6950
6951 static void gen6_init_clock_gating(struct drm_device *dev)
6952 {
6953         struct drm_i915_private *dev_priv = to_i915(dev);
6954         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6955
6956         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6957
6958         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6959                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6960                    ILK_ELPIN_409_SELECT);
6961
6962         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6963         I915_WRITE(_3D_CHICKEN,
6964                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6965
6966         /* WaDisable_RenderCache_OperationalFlush:snb */
6967         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6968
6969         /*
6970          * BSpec recoomends 8x4 when MSAA is used,
6971          * however in practice 16x4 seems fastest.
6972          *
6973          * Note that PS/WM thread counts depend on the WIZ hashing
6974          * disable bit, which we don't touch here, but it's good
6975          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6976          */
6977         I915_WRITE(GEN6_GT_MODE,
6978                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6979
6980         ilk_init_lp_watermarks(dev);
6981
6982         I915_WRITE(CACHE_MODE_0,
6983                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6984
6985         I915_WRITE(GEN6_UCGCTL1,
6986                    I915_READ(GEN6_UCGCTL1) |
6987                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6988                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6989
6990         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6991          * gating disable must be set.  Failure to set it results in
6992          * flickering pixels due to Z write ordering failures after
6993          * some amount of runtime in the Mesa "fire" demo, and Unigine
6994          * Sanctuary and Tropics, and apparently anything else with
6995          * alpha test or pixel discard.
6996          *
6997          * According to the spec, bit 11 (RCCUNIT) must also be set,
6998          * but we didn't debug actual testcases to find it out.
6999          *
7000          * WaDisableRCCUnitClockGating:snb
7001          * WaDisableRCPBUnitClockGating:snb
7002          */
7003         I915_WRITE(GEN6_UCGCTL2,
7004                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7005                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7006
7007         /* WaStripsFansDisableFastClipPerformanceFix:snb */
7008         I915_WRITE(_3D_CHICKEN3,
7009                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
7010
7011         /*
7012          * Bspec says:
7013          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7014          * 3DSTATE_SF number of SF output attributes is more than 16."
7015          */
7016         I915_WRITE(_3D_CHICKEN3,
7017                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7018
7019         /*
7020          * According to the spec the following bits should be
7021          * set in order to enable memory self-refresh and fbc:
7022          * The bit21 and bit22 of 0x42000
7023          * The bit21 and bit22 of 0x42004
7024          * The bit5 and bit7 of 0x42020
7025          * The bit14 of 0x70180
7026          * The bit14 of 0x71180
7027          *
7028          * WaFbcAsynchFlipDisableFbcQueue:snb
7029          */
7030         I915_WRITE(ILK_DISPLAY_CHICKEN1,
7031                    I915_READ(ILK_DISPLAY_CHICKEN1) |
7032                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7033         I915_WRITE(ILK_DISPLAY_CHICKEN2,
7034                    I915_READ(ILK_DISPLAY_CHICKEN2) |
7035                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7036         I915_WRITE(ILK_DSPCLK_GATE_D,
7037                    I915_READ(ILK_DSPCLK_GATE_D) |
7038                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
7039                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
7040
7041         g4x_disable_trickle_feed(dev);
7042
7043         cpt_init_clock_gating(dev);
7044
7045         gen6_check_mch_setup(dev);
7046 }
7047
7048 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7049 {
7050         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7051
7052         /*
7053          * WaVSThreadDispatchOverride:ivb,vlv
7054          *
7055          * This actually overrides the dispatch
7056          * mode for all thread types.
7057          */
7058         reg &= ~GEN7_FF_SCHED_MASK;
7059         reg |= GEN7_FF_TS_SCHED_HW;
7060         reg |= GEN7_FF_VS_SCHED_HW;
7061         reg |= GEN7_FF_DS_SCHED_HW;
7062
7063         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7064 }
7065
7066 static void lpt_init_clock_gating(struct drm_device *dev)
7067 {
7068         struct drm_i915_private *dev_priv = to_i915(dev);
7069
7070         /*
7071          * TODO: this bit should only be enabled when really needed, then
7072          * disabled when not needed anymore in order to save power.
7073          */
7074         if (HAS_PCH_LPT_LP(dev))
7075                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7076                            I915_READ(SOUTH_DSPCLK_GATE_D) |
7077                            PCH_LP_PARTITION_LEVEL_DISABLE);
7078
7079         /* WADPOClockGatingDisable:hsw */
7080         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7081                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
7082                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7083 }
7084
7085 static void lpt_suspend_hw(struct drm_device *dev)
7086 {
7087         struct drm_i915_private *dev_priv = to_i915(dev);
7088
7089         if (HAS_PCH_LPT_LP(dev)) {
7090                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7091
7092                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7093                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7094         }
7095 }
7096
7097 static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7098                                    int general_prio_credits,
7099                                    int high_prio_credits)
7100 {
7101         u32 misccpctl;
7102
7103         /* WaTempDisableDOPClkGating:bdw */
7104         misccpctl = I915_READ(GEN7_MISCCPCTL);
7105         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7106
7107         I915_WRITE(GEN8_L3SQCREG1,
7108                    L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7109                    L3_HIGH_PRIO_CREDITS(high_prio_credits));
7110
7111         /*
7112          * Wait at least 100 clocks before re-enabling clock gating.
7113          * See the definition of L3SQCREG1 in BSpec.
7114          */
7115         POSTING_READ(GEN8_L3SQCREG1);
7116         udelay(1);
7117         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7118 }
7119
7120 static void kabylake_init_clock_gating(struct drm_device *dev)
7121 {
7122         struct drm_i915_private *dev_priv = dev->dev_private;
7123
7124         gen9_init_clock_gating(dev);
7125
7126         /* WaDisableSDEUnitClockGating:kbl */
7127         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7128                 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7129                            GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7130
7131         /* WaDisableGamClockGating:kbl */
7132         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7133                 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7134                            GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
7135
7136         /* WaFbcNukeOnHostModify:kbl */
7137         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7138                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7139 }
7140
7141 static void skylake_init_clock_gating(struct drm_device *dev)
7142 {
7143         struct drm_i915_private *dev_priv = dev->dev_private;
7144
7145         gen9_init_clock_gating(dev);
7146
7147         /* WAC6entrylatency:skl */
7148         I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7149                    FBC_LLC_FULLY_OPEN);
7150
7151         /* WaFbcNukeOnHostModify:skl */
7152         I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7153                    ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
7154 }
7155
7156 static void broadwell_init_clock_gating(struct drm_device *dev)
7157 {
7158         struct drm_i915_private *dev_priv = to_i915(dev);
7159         enum pipe pipe;
7160
7161         ilk_init_lp_watermarks(dev);
7162
7163         /* WaSwitchSolVfFArbitrationPriority:bdw */
7164         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7165
7166         /* WaPsrDPAMaskVBlankInSRD:bdw */
7167         I915_WRITE(CHICKEN_PAR1_1,
7168                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7169
7170         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
7171         for_each_pipe(dev_priv, pipe) {
7172                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7173                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
7174                            BDW_DPRS_MASK_VBLANK_SRD);
7175         }
7176
7177         /* WaVSRefCountFullforceMissDisable:bdw */
7178         /* WaDSRefCountFullforceMissDisable:bdw */
7179         I915_WRITE(GEN7_FF_THREAD_MODE,
7180                    I915_READ(GEN7_FF_THREAD_MODE) &
7181                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7182
7183         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7184                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7185
7186         /* WaDisableSDEUnitClockGating:bdw */
7187         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7188                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7189
7190         /* WaProgramL3SqcReg1Default:bdw */
7191         gen8_set_l3sqc_credits(dev_priv, 30, 2);
7192
7193         /*
7194          * WaGttCachingOffByDefault:bdw
7195          * GTT cache may not work with big pages, so if those
7196          * are ever enabled GTT cache may need to be disabled.
7197          */
7198         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7199
7200         /* WaKVMNotificationOnConfigChange:bdw */
7201         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7202                    | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7203
7204         lpt_init_clock_gating(dev);
7205 }
7206
7207 static void haswell_init_clock_gating(struct drm_device *dev)
7208 {
7209         struct drm_i915_private *dev_priv = to_i915(dev);
7210
7211         ilk_init_lp_watermarks(dev);
7212
7213         /* L3 caching of data atomics doesn't work -- disable it. */
7214         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7215         I915_WRITE(HSW_ROW_CHICKEN3,
7216                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7217
7218         /* This is required by WaCatErrorRejectionIssue:hsw */
7219         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7220                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7221                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7222
7223         /* WaVSRefCountFullforceMissDisable:hsw */
7224         I915_WRITE(GEN7_FF_THREAD_MODE,
7225                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
7226
7227         /* WaDisable_RenderCache_OperationalFlush:hsw */
7228         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7229
7230         /* enable HiZ Raw Stall Optimization */
7231         I915_WRITE(CACHE_MODE_0_GEN7,
7232                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7233
7234         /* WaDisable4x2SubspanOptimization:hsw */
7235         I915_WRITE(CACHE_MODE_1,
7236                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7237
7238         /*
7239          * BSpec recommends 8x4 when MSAA is used,
7240          * however in practice 16x4 seems fastest.
7241          *
7242          * Note that PS/WM thread counts depend on the WIZ hashing
7243          * disable bit, which we don't touch here, but it's good
7244          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7245          */
7246         I915_WRITE(GEN7_GT_MODE,
7247                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7248
7249         /* WaSampleCChickenBitEnable:hsw */
7250         I915_WRITE(HALF_SLICE_CHICKEN3,
7251                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7252
7253         /* WaSwitchSolVfFArbitrationPriority:hsw */
7254         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7255
7256         /* WaRsPkgCStateDisplayPMReq:hsw */
7257         I915_WRITE(CHICKEN_PAR1_1,
7258                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
7259
7260         lpt_init_clock_gating(dev);
7261 }
7262
7263 static void ivybridge_init_clock_gating(struct drm_device *dev)
7264 {
7265         struct drm_i915_private *dev_priv = to_i915(dev);
7266         uint32_t snpcr;
7267
7268         ilk_init_lp_watermarks(dev);
7269
7270         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
7271
7272         /* WaDisableEarlyCull:ivb */
7273         I915_WRITE(_3D_CHICKEN3,
7274                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7275
7276         /* WaDisableBackToBackFlipFix:ivb */
7277         I915_WRITE(IVB_CHICKEN3,
7278                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7279                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7280
7281         /* WaDisablePSDDualDispatchEnable:ivb */
7282         if (IS_IVB_GT1(dev))
7283                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7284                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7285
7286         /* WaDisable_RenderCache_OperationalFlush:ivb */
7287         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7288
7289         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
7290         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7291                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7292
7293         /* WaApplyL3ControlAndL3ChickenMode:ivb */
7294         I915_WRITE(GEN7_L3CNTLREG1,
7295                         GEN7_WA_FOR_GEN7_L3_CONTROL);
7296         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
7297                    GEN7_WA_L3_CHICKEN_MODE);
7298         if (IS_IVB_GT1(dev))
7299                 I915_WRITE(GEN7_ROW_CHICKEN2,
7300                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7301         else {
7302                 /* must write both registers */
7303                 I915_WRITE(GEN7_ROW_CHICKEN2,
7304                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7305                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7306                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7307         }
7308
7309         /* WaForceL3Serialization:ivb */
7310         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7311                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7312
7313         /*
7314          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7315          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
7316          */
7317         I915_WRITE(GEN6_UCGCTL2,
7318                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7319
7320         /* This is required by WaCatErrorRejectionIssue:ivb */
7321         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7322                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7323                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7324
7325         g4x_disable_trickle_feed(dev);
7326
7327         gen7_setup_fixed_func_scheduler(dev_priv);
7328
7329         if (0) { /* causes HiZ corruption on ivb:gt1 */
7330                 /* enable HiZ Raw Stall Optimization */
7331                 I915_WRITE(CACHE_MODE_0_GEN7,
7332                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7333         }
7334
7335         /* WaDisable4x2SubspanOptimization:ivb */
7336         I915_WRITE(CACHE_MODE_1,
7337                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7338
7339         /*
7340          * BSpec recommends 8x4 when MSAA is used,
7341          * however in practice 16x4 seems fastest.
7342          *
7343          * Note that PS/WM thread counts depend on the WIZ hashing
7344          * disable bit, which we don't touch here, but it's good
7345          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7346          */
7347         I915_WRITE(GEN7_GT_MODE,
7348                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7349
7350         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7351         snpcr &= ~GEN6_MBC_SNPCR_MASK;
7352         snpcr |= GEN6_MBC_SNPCR_MED;
7353         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
7354
7355         if (!HAS_PCH_NOP(dev))
7356                 cpt_init_clock_gating(dev);
7357
7358         gen6_check_mch_setup(dev);
7359 }
7360
7361 static void valleyview_init_clock_gating(struct drm_device *dev)
7362 {
7363         struct drm_i915_private *dev_priv = to_i915(dev);
7364
7365         /* WaDisableEarlyCull:vlv */
7366         I915_WRITE(_3D_CHICKEN3,
7367                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7368
7369         /* WaDisableBackToBackFlipFix:vlv */
7370         I915_WRITE(IVB_CHICKEN3,
7371                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7372                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
7373
7374         /* WaPsdDispatchEnable:vlv */
7375         /* WaDisablePSDDualDispatchEnable:vlv */
7376         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7377                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7378                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
7379
7380         /* WaDisable_RenderCache_OperationalFlush:vlv */
7381         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7382
7383         /* WaForceL3Serialization:vlv */
7384         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7385                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7386
7387         /* WaDisableDopClockGating:vlv */
7388         I915_WRITE(GEN7_ROW_CHICKEN2,
7389                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7390
7391         /* This is required by WaCatErrorRejectionIssue:vlv */
7392         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7393                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7394                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7395
7396         gen7_setup_fixed_func_scheduler(dev_priv);
7397
7398         /*
7399          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
7400          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
7401          */
7402         I915_WRITE(GEN6_UCGCTL2,
7403                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
7404
7405         /* WaDisableL3Bank2xClockGate:vlv
7406          * Disabling L3 clock gating- MMIO 940c[25] = 1
7407          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7408         I915_WRITE(GEN7_UCGCTL4,
7409                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
7410
7411         /*
7412          * BSpec says this must be set, even though
7413          * WaDisable4x2SubspanOptimization isn't listed for VLV.
7414          */
7415         I915_WRITE(CACHE_MODE_1,
7416                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7417
7418         /*
7419          * BSpec recommends 8x4 when MSAA is used,
7420          * however in practice 16x4 seems fastest.
7421          *
7422          * Note that PS/WM thread counts depend on the WIZ hashing
7423          * disable bit, which we don't touch here, but it's good
7424          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7425          */
7426         I915_WRITE(GEN7_GT_MODE,
7427                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7428
7429         /*
7430          * WaIncreaseL3CreditsForVLVB0:vlv
7431          * This is the hardware default actually.
7432          */
7433         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7434
7435         /*
7436          * WaDisableVLVClockGating_VBIIssue:vlv
7437          * Disable clock gating on th GCFG unit to prevent a delay
7438          * in the reporting of vblank events.
7439          */
7440         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
7441 }
7442
7443 static void cherryview_init_clock_gating(struct drm_device *dev)
7444 {
7445         struct drm_i915_private *dev_priv = to_i915(dev);
7446
7447         /* WaVSRefCountFullforceMissDisable:chv */
7448         /* WaDSRefCountFullforceMissDisable:chv */
7449         I915_WRITE(GEN7_FF_THREAD_MODE,
7450                    I915_READ(GEN7_FF_THREAD_MODE) &
7451                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7452
7453         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7454         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7455                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7456
7457         /* WaDisableCSUnitClockGating:chv */
7458         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7459                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7460
7461         /* WaDisableSDEUnitClockGating:chv */
7462         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7463                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7464
7465         /*
7466          * WaProgramL3SqcReg1Default:chv
7467          * See gfxspecs/Related Documents/Performance Guide/
7468          * LSQC Setting Recommendations.
7469          */
7470         gen8_set_l3sqc_credits(dev_priv, 38, 2);
7471
7472         /*
7473          * GTT cache may not work with big pages, so if those
7474          * are ever enabled GTT cache may need to be disabled.
7475          */
7476         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7477 }
7478
7479 static void g4x_init_clock_gating(struct drm_device *dev)
7480 {
7481         struct drm_i915_private *dev_priv = to_i915(dev);
7482         uint32_t dspclk_gate;
7483
7484         I915_WRITE(RENCLK_GATE_D1, 0);
7485         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7486                    GS_UNIT_CLOCK_GATE_DISABLE |
7487                    CL_UNIT_CLOCK_GATE_DISABLE);
7488         I915_WRITE(RAMCLK_GATE_D, 0);
7489         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7490                 OVRUNIT_CLOCK_GATE_DISABLE |
7491                 OVCUNIT_CLOCK_GATE_DISABLE;
7492         if (IS_GM45(dev))
7493                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7494         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7495
7496         /* WaDisableRenderCachePipelinedFlush */
7497         I915_WRITE(CACHE_MODE_0,
7498                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7499
7500         /* WaDisable_RenderCache_OperationalFlush:g4x */
7501         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7502
7503         g4x_disable_trickle_feed(dev);
7504 }
7505
7506 static void crestline_init_clock_gating(struct drm_device *dev)
7507 {
7508         struct drm_i915_private *dev_priv = to_i915(dev);
7509
7510         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7511         I915_WRITE(RENCLK_GATE_D2, 0);
7512         I915_WRITE(DSPCLK_GATE_D, 0);
7513         I915_WRITE(RAMCLK_GATE_D, 0);
7514         I915_WRITE16(DEUC, 0);
7515         I915_WRITE(MI_ARB_STATE,
7516                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7517
7518         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7519         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7520 }
7521
7522 static void broadwater_init_clock_gating(struct drm_device *dev)
7523 {
7524         struct drm_i915_private *dev_priv = to_i915(dev);
7525
7526         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7527                    I965_RCC_CLOCK_GATE_DISABLE |
7528                    I965_RCPB_CLOCK_GATE_DISABLE |
7529                    I965_ISC_CLOCK_GATE_DISABLE |
7530                    I965_FBC_CLOCK_GATE_DISABLE);
7531         I915_WRITE(RENCLK_GATE_D2, 0);
7532         I915_WRITE(MI_ARB_STATE,
7533                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7534
7535         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7536         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7537 }
7538
7539 static void gen3_init_clock_gating(struct drm_device *dev)
7540 {
7541         struct drm_i915_private *dev_priv = to_i915(dev);
7542         u32 dstate = I915_READ(D_STATE);
7543
7544         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7545                 DSTATE_DOT_CLOCK_GATING;
7546         I915_WRITE(D_STATE, dstate);
7547
7548         if (IS_PINEVIEW(dev))
7549                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7550
7551         /* IIR "flip pending" means done if this bit is set */
7552         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7553
7554         /* interrupts should cause a wake up from C3 */
7555         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7556
7557         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7558         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7559
7560         I915_WRITE(MI_ARB_STATE,
7561                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7562 }
7563
7564 static void i85x_init_clock_gating(struct drm_device *dev)
7565 {
7566         struct drm_i915_private *dev_priv = to_i915(dev);
7567
7568         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7569
7570         /* interrupts should cause a wake up from C3 */
7571         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7572                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7573
7574         I915_WRITE(MEM_MODE,
7575                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7576 }
7577
7578 static void i830_init_clock_gating(struct drm_device *dev)
7579 {
7580         struct drm_i915_private *dev_priv = to_i915(dev);
7581
7582         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7583
7584         I915_WRITE(MEM_MODE,
7585                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7586                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7587 }
7588
7589 void intel_init_clock_gating(struct drm_device *dev)
7590 {
7591         struct drm_i915_private *dev_priv = to_i915(dev);
7592
7593         dev_priv->display.init_clock_gating(dev);
7594 }
7595
7596 void intel_suspend_hw(struct drm_device *dev)
7597 {
7598         if (HAS_PCH_LPT(dev))
7599                 lpt_suspend_hw(dev);
7600 }
7601
7602 static void nop_init_clock_gating(struct drm_device *dev)
7603 {
7604         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7605 }
7606
7607 /**
7608  * intel_init_clock_gating_hooks - setup the clock gating hooks
7609  * @dev_priv: device private
7610  *
7611  * Setup the hooks that configure which clocks of a given platform can be
7612  * gated and also apply various GT and display specific workarounds for these
7613  * platforms. Note that some GT specific workarounds are applied separately
7614  * when GPU contexts or batchbuffers start their execution.
7615  */
7616 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7617 {
7618         if (IS_SKYLAKE(dev_priv))
7619                 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
7620         else if (IS_KABYLAKE(dev_priv))
7621                 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
7622         else if (IS_BROXTON(dev_priv))
7623                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7624         else if (IS_BROADWELL(dev_priv))
7625                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7626         else if (IS_CHERRYVIEW(dev_priv))
7627                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7628         else if (IS_HASWELL(dev_priv))
7629                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7630         else if (IS_IVYBRIDGE(dev_priv))
7631                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7632         else if (IS_VALLEYVIEW(dev_priv))
7633                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7634         else if (IS_GEN6(dev_priv))
7635                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7636         else if (IS_GEN5(dev_priv))
7637                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7638         else if (IS_G4X(dev_priv))
7639                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7640         else if (IS_CRESTLINE(dev_priv))
7641                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7642         else if (IS_BROADWATER(dev_priv))
7643                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7644         else if (IS_GEN3(dev_priv))
7645                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7646         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7647                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7648         else if (IS_GEN2(dev_priv))
7649                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7650         else {
7651                 MISSING_CASE(INTEL_DEVID(dev_priv));
7652                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7653         }
7654 }
7655
7656 /* Set up chip specific power management-related functions */
7657 void intel_init_pm(struct drm_device *dev)
7658 {
7659         struct drm_i915_private *dev_priv = to_i915(dev);
7660
7661         intel_fbc_init(dev_priv);
7662
7663         /* For cxsr */
7664         if (IS_PINEVIEW(dev))
7665                 i915_pineview_get_mem_freq(dev);
7666         else if (IS_GEN5(dev))
7667                 i915_ironlake_get_mem_freq(dev);
7668
7669         /* For FIFO watermark updates */
7670         if (INTEL_INFO(dev)->gen >= 9) {
7671                 skl_setup_wm_latency(dev);
7672                 dev_priv->display.update_wm = skl_update_wm;
7673                 dev_priv->display.compute_global_watermarks = skl_compute_wm;
7674         } else if (HAS_PCH_SPLIT(dev)) {
7675                 ilk_setup_wm_latency(dev);
7676
7677                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7678                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7679                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7680                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7681                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7682                         dev_priv->display.compute_intermediate_wm =
7683                                 ilk_compute_intermediate_wm;
7684                         dev_priv->display.initial_watermarks =
7685                                 ilk_initial_watermarks;
7686                         dev_priv->display.optimize_watermarks =
7687                                 ilk_optimize_watermarks;
7688                 } else {
7689                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7690                                       "Disable CxSR\n");
7691                 }
7692         } else if (IS_CHERRYVIEW(dev)) {
7693                 vlv_setup_wm_latency(dev);
7694                 dev_priv->display.update_wm = vlv_update_wm;
7695         } else if (IS_VALLEYVIEW(dev)) {
7696                 vlv_setup_wm_latency(dev);
7697                 dev_priv->display.update_wm = vlv_update_wm;
7698         } else if (IS_PINEVIEW(dev)) {
7699                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7700                                             dev_priv->is_ddr3,
7701                                             dev_priv->fsb_freq,
7702                                             dev_priv->mem_freq)) {
7703                         DRM_INFO("failed to find known CxSR latency "
7704                                  "(found ddr%s fsb freq %d, mem freq %d), "
7705                                  "disabling CxSR\n",
7706                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7707                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7708                         /* Disable CxSR and never update its watermark again */
7709                         intel_set_memory_cxsr(dev_priv, false);
7710                         dev_priv->display.update_wm = NULL;
7711                 } else
7712                         dev_priv->display.update_wm = pineview_update_wm;
7713         } else if (IS_G4X(dev)) {
7714                 dev_priv->display.update_wm = g4x_update_wm;
7715         } else if (IS_GEN4(dev)) {
7716                 dev_priv->display.update_wm = i965_update_wm;
7717         } else if (IS_GEN3(dev)) {
7718                 dev_priv->display.update_wm = i9xx_update_wm;
7719                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7720         } else if (IS_GEN2(dev)) {
7721                 if (INTEL_INFO(dev)->num_pipes == 1) {
7722                         dev_priv->display.update_wm = i845_update_wm;
7723                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7724                 } else {
7725                         dev_priv->display.update_wm = i9xx_update_wm;
7726                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7727                 }
7728         } else {
7729                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7730         }
7731 }
7732
7733 static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7734 {
7735         uint32_t flags =
7736                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7737
7738         switch (flags) {
7739         case GEN6_PCODE_SUCCESS:
7740                 return 0;
7741         case GEN6_PCODE_UNIMPLEMENTED_CMD:
7742         case GEN6_PCODE_ILLEGAL_CMD:
7743                 return -ENXIO;
7744         case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7745         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7746                 return -EOVERFLOW;
7747         case GEN6_PCODE_TIMEOUT:
7748                 return -ETIMEDOUT;
7749         default:
7750                 MISSING_CASE(flags)
7751                 return 0;
7752         }
7753 }
7754
7755 static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7756 {
7757         uint32_t flags =
7758                 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7759
7760         switch (flags) {
7761         case GEN6_PCODE_SUCCESS:
7762                 return 0;
7763         case GEN6_PCODE_ILLEGAL_CMD:
7764                 return -ENXIO;
7765         case GEN7_PCODE_TIMEOUT:
7766                 return -ETIMEDOUT;
7767         case GEN7_PCODE_ILLEGAL_DATA:
7768                 return -EINVAL;
7769         case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7770                 return -EOVERFLOW;
7771         default:
7772                 MISSING_CASE(flags);
7773                 return 0;
7774         }
7775 }
7776
7777 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7778 {
7779         int status;
7780
7781         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7782
7783         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7784          * use te fw I915_READ variants to reduce the amount of work
7785          * required when reading/writing.
7786          */
7787
7788         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7789                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7790                 return -EAGAIN;
7791         }
7792
7793         I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7794         I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7795         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7796
7797         if (intel_wait_for_register_fw(dev_priv,
7798                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7799                                        500)) {
7800                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7801                 return -ETIMEDOUT;
7802         }
7803
7804         *val = I915_READ_FW(GEN6_PCODE_DATA);
7805         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7806
7807         if (INTEL_GEN(dev_priv) > 6)
7808                 status = gen7_check_mailbox_status(dev_priv);
7809         else
7810                 status = gen6_check_mailbox_status(dev_priv);
7811
7812         if (status) {
7813                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7814                                  status);
7815                 return status;
7816         }
7817
7818         return 0;
7819 }
7820
7821 int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
7822                             u32 mbox, u32 val)
7823 {
7824         int status;
7825
7826         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7827
7828         /* GEN6_PCODE_* are outside of the forcewake domain, we can
7829          * use te fw I915_READ variants to reduce the amount of work
7830          * required when reading/writing.
7831          */
7832
7833         if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7834                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7835                 return -EAGAIN;
7836         }
7837
7838         I915_WRITE_FW(GEN6_PCODE_DATA, val);
7839         I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7840
7841         if (intel_wait_for_register_fw(dev_priv,
7842                                        GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7843                                        500)) {
7844                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7845                 return -ETIMEDOUT;
7846         }
7847
7848         I915_WRITE_FW(GEN6_PCODE_DATA, 0);
7849
7850         if (INTEL_GEN(dev_priv) > 6)
7851                 status = gen7_check_mailbox_status(dev_priv);
7852         else
7853                 status = gen6_check_mailbox_status(dev_priv);
7854
7855         if (status) {
7856                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7857                                  status);
7858                 return status;
7859         }
7860
7861         return 0;
7862 }
7863
7864 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7865 {
7866         /*
7867          * N = val - 0xb7
7868          * Slow = Fast = GPLL ref * N
7869          */
7870         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7871 }
7872
7873 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7874 {
7875         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7876 }
7877
7878 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7879 {
7880         /*
7881          * N = val / 2
7882          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7883          */
7884         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7885 }
7886
7887 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7888 {
7889         /* CHV needs even values */
7890         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7891 }
7892
7893 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7894 {
7895         if (IS_GEN9(dev_priv))
7896                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7897                                          GEN9_FREQ_SCALER);
7898         else if (IS_CHERRYVIEW(dev_priv))
7899                 return chv_gpu_freq(dev_priv, val);
7900         else if (IS_VALLEYVIEW(dev_priv))
7901                 return byt_gpu_freq(dev_priv, val);
7902         else
7903                 return val * GT_FREQUENCY_MULTIPLIER;
7904 }
7905
7906 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7907 {
7908         if (IS_GEN9(dev_priv))
7909                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7910                                          GT_FREQUENCY_MULTIPLIER);
7911         else if (IS_CHERRYVIEW(dev_priv))
7912                 return chv_freq_opcode(dev_priv, val);
7913         else if (IS_VALLEYVIEW(dev_priv))
7914                 return byt_freq_opcode(dev_priv, val);
7915         else
7916                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7917 }
7918
7919 struct request_boost {
7920         struct work_struct work;
7921         struct drm_i915_gem_request *req;
7922 };
7923
7924 static void __intel_rps_boost_work(struct work_struct *work)
7925 {
7926         struct request_boost *boost = container_of(work, struct request_boost, work);
7927         struct drm_i915_gem_request *req = boost->req;
7928
7929         if (!i915_gem_request_completed(req))
7930                 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
7931
7932         i915_gem_request_put(req);
7933         kfree(boost);
7934 }
7935
7936 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
7937 {
7938         struct request_boost *boost;
7939
7940         if (req == NULL || INTEL_GEN(req->i915) < 6)
7941                 return;
7942
7943         if (i915_gem_request_completed(req))
7944                 return;
7945
7946         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7947         if (boost == NULL)
7948                 return;
7949
7950         boost->req = i915_gem_request_get(req);
7951
7952         INIT_WORK(&boost->work, __intel_rps_boost_work);
7953         queue_work(req->i915->wq, &boost->work);
7954 }
7955
7956 void intel_pm_setup(struct drm_device *dev)
7957 {
7958         struct drm_i915_private *dev_priv = to_i915(dev);
7959
7960         mutex_init(&dev_priv->rps.hw_lock);
7961         spin_lock_init(&dev_priv->rps.client_lock);
7962
7963         INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
7964                           __intel_autoenable_gt_powersave);
7965         INIT_LIST_HEAD(&dev_priv->rps.clients);
7966
7967         dev_priv->pm.suspended = false;
7968         atomic_set(&dev_priv->pm.wakeref_count, 0);
7969         atomic_set(&dev_priv->pm.atomic_seq, 0);
7970 }