drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  42 {
  43         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  44 }
  45
  46 static void
  47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  48 {
  49         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  50         struct drm_i915_private *dev_priv = dev->dev_private;
  51         uint32_t enabled_bits;
  52
  53         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  54
  55         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  56              "HDMI port enabled, expecting disabled\n");
  57 }
  58
  59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  60 {
  61         struct intel_digital_port *intel_dig_port =
  62                 container_of(encoder, struct intel_digital_port, base.base);
  63         return &intel_dig_port->hdmi;
  64 }
  65
  66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  67 {
  68         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  69 }
  70
  71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  72 {
  73         switch (type) {
  74         case HDMI_INFOFRAME_TYPE_AVI:
  75                 return VIDEO_DIP_SELECT_AVI;
  76         case HDMI_INFOFRAME_TYPE_SPD:
  77                 return VIDEO_DIP_SELECT_SPD;
  78         case HDMI_INFOFRAME_TYPE_VENDOR:
  79                 return VIDEO_DIP_SELECT_VENDOR;
  80         default:
  81                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  82                 return 0;
  83         }
  84 }
  85
  86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  87 {
  88         switch (type) {
  89         case HDMI_INFOFRAME_TYPE_AVI:
  90                 return VIDEO_DIP_ENABLE_AVI;
  91         case HDMI_INFOFRAME_TYPE_SPD:
  92                 return VIDEO_DIP_ENABLE_SPD;
  93         case HDMI_INFOFRAME_TYPE_VENDOR:
  94                 return VIDEO_DIP_ENABLE_VENDOR;
  95         default:
  96                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  97                 return 0;
  98         }
  99 }
 100
 101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 102 {
 103         switch (type) {
 104         case HDMI_INFOFRAME_TYPE_AVI:
 105                 return VIDEO_DIP_ENABLE_AVI_HSW;
 106         case HDMI_INFOFRAME_TYPE_SPD:
 107                 return VIDEO_DIP_ENABLE_SPD_HSW;
 108         case HDMI_INFOFRAME_TYPE_VENDOR:
 109                 return VIDEO_DIP_ENABLE_VS_HSW;
 110         default:
 111                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 112                 return 0;
 113         }
 114 }
 115
 116 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
 117                                   enum transcoder cpu_transcoder,
 118                                   struct drm_i915_private *dev_priv)
 119 {
 120         switch (type) {
 121         case HDMI_INFOFRAME_TYPE_AVI:
 122                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 123         case HDMI_INFOFRAME_TYPE_SPD:
 124                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 125         case HDMI_INFOFRAME_TYPE_VENDOR:
 126                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
 127         default:
 128                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 129                 return 0;
 130         }
 131 }
 132
 133 static void g4x_write_infoframe(struct drm_encoder *encoder,
 134                                 enum hdmi_infoframe_type type,
 135                                 const void *frame, ssize_t len)
 136 {
 137         const uint32_t *data = frame;
 138         struct drm_device *dev = encoder->dev;
 139         struct drm_i915_private *dev_priv = dev->dev_private;
 140         u32 val = I915_READ(VIDEO_DIP_CTL);
 141         int i;
 142
 143         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 144
 145         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 146         val |= g4x_infoframe_index(type);
 147
 148         val &= ~g4x_infoframe_enable(type);
 149
 150         I915_WRITE(VIDEO_DIP_CTL, val);
 151
 152         mmiowb();
 153         for (i = 0; i < len; i += 4) {
 154                 I915_WRITE(VIDEO_DIP_DATA, *data);
 155                 data++;
 156         }
 157         /* Write every possible data byte to force correct ECC calculation. */
 158         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 159                 I915_WRITE(VIDEO_DIP_DATA, 0);
 160         mmiowb();
 161
 162         val |= g4x_infoframe_enable(type);
 163         val &= ~VIDEO_DIP_FREQ_MASK;
 164         val |= VIDEO_DIP_FREQ_VSYNC;
 165
 166         I915_WRITE(VIDEO_DIP_CTL, val);
 167         POSTING_READ(VIDEO_DIP_CTL);
 168 }
 169
 170 static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
 171 {
 172         struct drm_device *dev = encoder->dev;
 173         struct drm_i915_private *dev_priv = dev->dev_private;
 174         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 175         u32 val = I915_READ(VIDEO_DIP_CTL);
 176
 177         if ((val & VIDEO_DIP_ENABLE) == 0)
 178                 return false;
 179
 180         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 181                 return false;
 182
 183         return val & (VIDEO_DIP_ENABLE_AVI |
 184                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 185 }
 186
 187 static void ibx_write_infoframe(struct drm_encoder *encoder,
 188                                 enum hdmi_infoframe_type type,
 189                                 const void *frame, ssize_t len)
 190 {
 191         const uint32_t *data = frame;
 192         struct drm_device *dev = encoder->dev;
 193         struct drm_i915_private *dev_priv = dev->dev_private;
 194         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 195         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 196         u32 val = I915_READ(reg);
 197
 198         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 199
 200         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 201         val |= g4x_infoframe_index(type);
 202
 203         val &= ~g4x_infoframe_enable(type);
 204
 205         I915_WRITE(reg, val);
 206
 207         mmiowb();
 208         for (i = 0; i < len; i += 4) {
 209                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 210                 data++;
 211         }
 212         /* Write every possible data byte to force correct ECC calculation. */
 213         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 214                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 215         mmiowb();
 216
 217         val |= g4x_infoframe_enable(type);
 218         val &= ~VIDEO_DIP_FREQ_MASK;
 219         val |= VIDEO_DIP_FREQ_VSYNC;
 220
 221         I915_WRITE(reg, val);
 222         POSTING_READ(reg);
 223 }
 224
 225 static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
 226 {
 227         struct drm_device *dev = encoder->dev;
 228         struct drm_i915_private *dev_priv = dev->dev_private;
 229         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 230         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 231         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 232         u32 val = I915_READ(reg);
 233
 234         if ((val & VIDEO_DIP_ENABLE) == 0)
 235                 return false;
 236
 237         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 238                 return false;
 239
 240         return val & (VIDEO_DIP_ENABLE_AVI |
 241                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 242                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 243 }
 244
 245 static void cpt_write_infoframe(struct drm_encoder *encoder,
 246                                 enum hdmi_infoframe_type type,
 247                                 const void *frame, ssize_t len)
 248 {
 249         const uint32_t *data = frame;
 250         struct drm_device *dev = encoder->dev;
 251         struct drm_i915_private *dev_priv = dev->dev_private;
 252         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 253         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 254         u32 val = I915_READ(reg);
 255
 256         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 257
 258         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 259         val |= g4x_infoframe_index(type);
 260
 261         /* The DIP control register spec says that we need to update the AVI
 262          * infoframe without clearing its enable bit */
 263         if (type != HDMI_INFOFRAME_TYPE_AVI)
 264                 val &= ~g4x_infoframe_enable(type);
 265
 266         I915_WRITE(reg, val);
 267
 268         mmiowb();
 269         for (i = 0; i < len; i += 4) {
 270                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 271                 data++;
 272         }
 273         /* Write every possible data byte to force correct ECC calculation. */
 274         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 275                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 276         mmiowb();
 277
 278         val |= g4x_infoframe_enable(type);
 279         val &= ~VIDEO_DIP_FREQ_MASK;
 280         val |= VIDEO_DIP_FREQ_VSYNC;
 281
 282         I915_WRITE(reg, val);
 283         POSTING_READ(reg);
 284 }
 285
 286 static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
 287 {
 288         struct drm_device *dev = encoder->dev;
 289         struct drm_i915_private *dev_priv = dev->dev_private;
 290         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 291         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 292         u32 val = I915_READ(reg);
 293
 294         if ((val & VIDEO_DIP_ENABLE) == 0)
 295                 return false;
 296
 297         return val & (VIDEO_DIP_ENABLE_AVI |
 298                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 299                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 300 }
 301
 302 static void vlv_write_infoframe(struct drm_encoder *encoder,
 303                                 enum hdmi_infoframe_type type,
 304                                 const void *frame, ssize_t len)
 305 {
 306         const uint32_t *data = frame;
 307         struct drm_device *dev = encoder->dev;
 308         struct drm_i915_private *dev_priv = dev->dev_private;
 309         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 310         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 311         u32 val = I915_READ(reg);
 312
 313         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 314
 315         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 316         val |= g4x_infoframe_index(type);
 317
 318         val &= ~g4x_infoframe_enable(type);
 319
 320         I915_WRITE(reg, val);
 321
 322         mmiowb();
 323         for (i = 0; i < len; i += 4) {
 324                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 325                 data++;
 326         }
 327         /* Write every possible data byte to force correct ECC calculation. */
 328         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 329                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 330         mmiowb();
 331
 332         val |= g4x_infoframe_enable(type);
 333         val &= ~VIDEO_DIP_FREQ_MASK;
 334         val |= VIDEO_DIP_FREQ_VSYNC;
 335
 336         I915_WRITE(reg, val);
 337         POSTING_READ(reg);
 338 }
 339
 340 static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
 341 {
 342         struct drm_device *dev = encoder->dev;
 343         struct drm_i915_private *dev_priv = dev->dev_private;
 344         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 345         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 346         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 347         u32 val = I915_READ(reg);
 348
 349         if ((val & VIDEO_DIP_ENABLE) == 0)
 350                 return false;
 351
 352         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
 353                 return false;
 354
 355         return val & (VIDEO_DIP_ENABLE_AVI |
 356                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 357                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 358 }
 359
 360 static void hsw_write_infoframe(struct drm_encoder *encoder,
 361                                 enum hdmi_infoframe_type type,
 362                                 const void *frame, ssize_t len)
 363 {
 364         const uint32_t *data = frame;
 365         struct drm_device *dev = encoder->dev;
 366         struct drm_i915_private *dev_priv = dev->dev_private;
 367         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 368         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 369         u32 data_reg;
 370         int i;
 371         u32 val = I915_READ(ctl_reg);
 372
 373         data_reg = hsw_infoframe_data_reg(type,
 374                                           intel_crtc->config->cpu_transcoder,
 375                                           dev_priv);
 376         if (data_reg == 0)
 377                 return;
 378
 379         val &= ~hsw_infoframe_enable(type);
 380         I915_WRITE(ctl_reg, val);
 381
 382         mmiowb();
 383         for (i = 0; i < len; i += 4) {
 384                 I915_WRITE(data_reg + i, *data);
 385                 data++;
 386         }
 387         /* Write every possible data byte to force correct ECC calculation. */
 388         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 389                 I915_WRITE(data_reg + i, 0);
 390         mmiowb();
 391
 392         val |= hsw_infoframe_enable(type);
 393         I915_WRITE(ctl_reg, val);
 394         POSTING_READ(ctl_reg);
 395 }
 396
 397 static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
 398 {
 399         struct drm_device *dev = encoder->dev;
 400         struct drm_i915_private *dev_priv = dev->dev_private;
 401         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 402         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 403         u32 val = I915_READ(ctl_reg);
 404
 405         return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 406                       VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 407                       VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 408 }
 409
 410 /*
 411  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 412  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 413  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 414  * used for both technologies.
 415  *
 416  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 417  * DW1:       DB3       | DB2 | DB1 | DB0
 418  * DW2:       DB7       | DB6 | DB5 | DB4
 419  * DW3: ...
 420  *
 421  * (HB is Header Byte, DB is Data Byte)
 422  *
 423  * The hdmi pack() functions don't know about that hardware specific hole so we
 424  * trick them by giving an offset into the buffer and moving back the header
 425  * bytes by one.
 426  */
 427 static void intel_write_infoframe(struct drm_encoder *encoder,
 428                                   union hdmi_infoframe *frame)
 429 {
 430         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 431         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 432         ssize_t len;
 433
 434         /* see comment above for the reason for this offset */
 435         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 436         if (len < 0)
 437                 return;
 438
 439         /* Insert the 'hole' (see big comment above) at position 3 */
 440         buffer[0] = buffer[1];
 441         buffer[1] = buffer[2];
 442         buffer[2] = buffer[3];
 443         buffer[3] = 0;
 444         len++;
 445
 446         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 447 }
 448
 449 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 450                                          struct drm_display_mode *adjusted_mode)
 451 {
 452         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 453         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 454         union hdmi_infoframe frame;
 455         int ret;
 456
 457         /* Set user selected PAR to incoming mode's member */
 458         adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
 459
 460         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 461                                                        adjusted_mode);
 462         if (ret < 0) {
 463                 DRM_ERROR("couldn't fill AVI infoframe\n");
 464                 return;
 465         }
 466
 467         if (intel_hdmi->rgb_quant_range_selectable) {
 468                 if (intel_crtc->config->limited_color_range)
 469                         frame.avi.quantization_range =
 470                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 471                 else
 472                         frame.avi.quantization_range =
 473                                 HDMI_QUANTIZATION_RANGE_FULL;
 474         }
 475
 476         intel_write_infoframe(encoder, &frame);
 477 }
 478
 479 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 480 {
 481         union hdmi_infoframe frame;
 482         int ret;
 483
 484         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 485         if (ret < 0) {
 486                 DRM_ERROR("couldn't fill SPD infoframe\n");
 487                 return;
 488         }
 489
 490         frame.spd.sdi = HDMI_SPD_SDI_PC;
 491
 492         intel_write_infoframe(encoder, &frame);
 493 }
 494
 495 static void
 496 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 497                               struct drm_display_mode *adjusted_mode)
 498 {
 499         union hdmi_infoframe frame;
 500         int ret;
 501
 502         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 503                                                           adjusted_mode);
 504         if (ret < 0)
 505                 return;
 506
 507         intel_write_infoframe(encoder, &frame);
 508 }
 509
 510 static void g4x_set_infoframes(struct drm_encoder *encoder,
 511                                bool enable,
 512                                struct drm_display_mode *adjusted_mode)
 513 {
 514         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 515         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 516         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 517         u32 reg = VIDEO_DIP_CTL;
 518         u32 val = I915_READ(reg);
 519         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 520
 521         assert_hdmi_port_disabled(intel_hdmi);
 522
 523         /* If the registers were not initialized yet, they might be zeroes,
 524          * which means we're selecting the AVI DIP and we're setting its
 525          * frequency to once. This seems to really confuse the HW and make
 526          * things stop working (the register spec says the AVI always needs to
 527          * be sent every VSync). So here we avoid writing to the register more
 528          * than we need and also explicitly select the AVI DIP and explicitly
 529          * set its frequency to every VSync. Avoiding to write it twice seems to
 530          * be enough to solve the problem, but being defensive shouldn't hurt us
 531          * either. */
 532         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 533
 534         if (!enable) {
 535                 if (!(val & VIDEO_DIP_ENABLE))
 536                         return;
 537                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 538                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 539                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 540                         return;
 541                 }
 542                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 543                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 544                 I915_WRITE(reg, val);
 545                 POSTING_READ(reg);
 546                 return;
 547         }
 548
 549         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 550                 if (val & VIDEO_DIP_ENABLE) {
 551                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 552                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 553                         return;
 554                 }
 555                 val &= ~VIDEO_DIP_PORT_MASK;
 556                 val |= port;
 557         }
 558
 559         val |= VIDEO_DIP_ENABLE;
 560         val &= ~(VIDEO_DIP_ENABLE_AVI |
 561                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 562
 563         I915_WRITE(reg, val);
 564         POSTING_READ(reg);
 565
 566         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 567         intel_hdmi_set_spd_infoframe(encoder);
 568         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 569 }
 570
 571 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
 572 {
 573         struct drm_device *dev = encoder->dev;
 574         struct drm_connector *connector;
 575
 576         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 577
 578         /*
 579          * HDMI cloning is only supported on g4x which doesn't
 580          * support deep color or GCP infoframes anyway so no
 581          * need to worry about multiple HDMI sinks here.
 582          */
 583         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
 584                 if (connector->encoder == encoder)
 585                         return connector->display_info.bpc > 8;
 586
 587         return false;
 588 }
 589
 590 /*
 591  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 592  *
 593  * From HDMI specification 1.4a:
 594  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 595  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 596  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 597  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 598  *   phase of 0
 599  */
 600 static bool gcp_default_phase_possible(int pipe_bpp,
 601                                        const struct drm_display_mode *mode)
 602 {
 603         unsigned int pixels_per_group;
 604
 605         switch (pipe_bpp) {
 606         case 30:
 607                 /* 4 pixels in 5 clocks */
 608                 pixels_per_group = 4;
 609                 break;
 610         case 36:
 611                 /* 2 pixels in 3 clocks */
 612                 pixels_per_group = 2;
 613                 break;
 614         case 48:
 615                 /* 1 pixel in 2 clocks */
 616                 pixels_per_group = 1;
 617                 break;
 618         default:
 619                 /* phase information not relevant for 8bpc */
 620                 return false;
 621         }
 622
 623         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 624                 mode->crtc_htotal % pixels_per_group == 0 &&
 625                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 626                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 627                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 628                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 629                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 630                  mode->crtc_htotal/2 % pixels_per_group == 0);
 631 }
 632
 633 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
 634 {
 635         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 636         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
 637         u32 reg, val = 0;
 638
 639         if (HAS_DDI(dev_priv))
 640                 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
 641         else if (IS_VALLEYVIEW(dev_priv))
 642                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 643         else if (HAS_PCH_SPLIT(dev_priv->dev))
 644                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 645         else
 646                 return false;
 647
 648         /* Indicate color depth whenever the sink supports deep color */
 649         if (hdmi_sink_is_deep_color(encoder))
 650                 val |= GCP_COLOR_INDICATION;
 651
 652         /* Enable default_phase whenever the display mode is suitably aligned */
 653         if (gcp_default_phase_possible(crtc->config->pipe_bpp,
 654                                        &crtc->config->base.adjusted_mode))
 655                 val |= GCP_DEFAULT_PHASE_ENABLE;
 656
 657         I915_WRITE(reg, val);
 658
 659         return val != 0;
 660 }
 661
 662 static void ibx_set_infoframes(struct drm_encoder *encoder,
 663                                bool enable,
 664                                struct drm_display_mode *adjusted_mode)
 665 {
 666         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 667         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 668         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 669         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 670         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 671         u32 val = I915_READ(reg);
 672         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 673
 674         assert_hdmi_port_disabled(intel_hdmi);
 675
 676         /* See the big comment in g4x_set_infoframes() */
 677         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 678
 679         if (!enable) {
 680                 if (!(val & VIDEO_DIP_ENABLE))
 681                         return;
 682                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 683                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 684                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 685                 I915_WRITE(reg, val);
 686                 POSTING_READ(reg);
 687                 return;
 688         }
 689
 690         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 691                 WARN(val & VIDEO_DIP_ENABLE,
 692                      "DIP already enabled on port %c\n",
 693                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 694                 val &= ~VIDEO_DIP_PORT_MASK;
 695                 val |= port;
 696         }
 697
 698         val |= VIDEO_DIP_ENABLE;
 699         val &= ~(VIDEO_DIP_ENABLE_AVI |
 700                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 701                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 702
 703         if (intel_hdmi_set_gcp_infoframe(encoder))
 704                 val |= VIDEO_DIP_ENABLE_GCP;
 705
 706         I915_WRITE(reg, val);
 707         POSTING_READ(reg);
 708
 709         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 710         intel_hdmi_set_spd_infoframe(encoder);
 711         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 712 }
 713
 714 static void cpt_set_infoframes(struct drm_encoder *encoder,
 715                                bool enable,
 716                                struct drm_display_mode *adjusted_mode)
 717 {
 718         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 719         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 720         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 721         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 722         u32 val = I915_READ(reg);
 723
 724         assert_hdmi_port_disabled(intel_hdmi);
 725
 726         /* See the big comment in g4x_set_infoframes() */
 727         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 728
 729         if (!enable) {
 730                 if (!(val & VIDEO_DIP_ENABLE))
 731                         return;
 732                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 733                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 734                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 735                 I915_WRITE(reg, val);
 736                 POSTING_READ(reg);
 737                 return;
 738         }
 739
 740         /* Set both together, unset both together: see the spec. */
 741         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 742         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 743                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 744
 745         if (intel_hdmi_set_gcp_infoframe(encoder))
 746                 val |= VIDEO_DIP_ENABLE_GCP;
 747
 748         I915_WRITE(reg, val);
 749         POSTING_READ(reg);
 750
 751         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 752         intel_hdmi_set_spd_infoframe(encoder);
 753         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 754 }
 755
 756 static void vlv_set_infoframes(struct drm_encoder *encoder,
 757                                bool enable,
 758                                struct drm_display_mode *adjusted_mode)
 759 {
 760         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 761         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 762         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 763         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 764         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 765         u32 val = I915_READ(reg);
 766         u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
 767
 768         assert_hdmi_port_disabled(intel_hdmi);
 769
 770         /* See the big comment in g4x_set_infoframes() */
 771         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 772
 773         if (!enable) {
 774                 if (!(val & VIDEO_DIP_ENABLE))
 775                         return;
 776                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 777                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 778                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 779                 I915_WRITE(reg, val);
 780                 POSTING_READ(reg);
 781                 return;
 782         }
 783
 784         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 785                 WARN(val & VIDEO_DIP_ENABLE,
 786                      "DIP already enabled on port %c\n",
 787                      (val & VIDEO_DIP_PORT_MASK) >> 29);
 788                 val &= ~VIDEO_DIP_PORT_MASK;
 789                 val |= port;
 790         }
 791
 792         val |= VIDEO_DIP_ENABLE;
 793         val &= ~(VIDEO_DIP_ENABLE_AVI |
 794                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 795                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 796
 797         if (intel_hdmi_set_gcp_infoframe(encoder))
 798                 val |= VIDEO_DIP_ENABLE_GCP;
 799
 800         I915_WRITE(reg, val);
 801         POSTING_READ(reg);
 802
 803         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 804         intel_hdmi_set_spd_infoframe(encoder);
 805         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 806 }
 807
 808 static void hsw_set_infoframes(struct drm_encoder *encoder,
 809                                bool enable,
 810                                struct drm_display_mode *adjusted_mode)
 811 {
 812         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 813         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 814         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 815         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
 816         u32 val = I915_READ(reg);
 817
 818         assert_hdmi_port_disabled(intel_hdmi);
 819
 820         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 821                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 822                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 823
 824         if (!enable) {
 825                 I915_WRITE(reg, val);
 826                 POSTING_READ(reg);
 827                 return;
 828         }
 829
 830         if (intel_hdmi_set_gcp_infoframe(encoder))
 831                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
 832
 833         I915_WRITE(reg, val);
 834         POSTING_READ(reg);
 835
 836         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 837         intel_hdmi_set_spd_infoframe(encoder);
 838         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 839 }
 840
 841 static void intel_hdmi_prepare(struct intel_encoder *encoder)
 842 {
 843         struct drm_device *dev = encoder->base.dev;
 844         struct drm_i915_private *dev_priv = dev->dev_private;
 845         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 846         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 847         struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
 848         u32 hdmi_val;
 849
 850         hdmi_val = SDVO_ENCODING_HDMI;
 851         if (!HAS_PCH_SPLIT(dev))
 852                 hdmi_val |= intel_hdmi->color_range;
 853         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 854                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 855         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 856                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 857
 858         if (crtc->config->pipe_bpp > 24)
 859                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 860         else
 861                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 862
 863         if (crtc->config->has_hdmi_sink)
 864                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 865
 866         if (HAS_PCH_CPT(dev))
 867                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 868         else if (IS_CHERRYVIEW(dev))
 869                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
 870         else
 871                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 872
 873         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 874         POSTING_READ(intel_hdmi->hdmi_reg);
 875 }
 876
 877 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 878                                     enum pipe *pipe)
 879 {
 880         struct drm_device *dev = encoder->base.dev;
 881         struct drm_i915_private *dev_priv = dev->dev_private;
 882         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 883         enum intel_display_power_domain power_domain;
 884         u32 tmp;
 885
 886         power_domain = intel_display_port_power_domain(encoder);
 887         if (!intel_display_power_is_enabled(dev_priv, power_domain))
 888                 return false;
 889
 890         tmp = I915_READ(intel_hdmi->hdmi_reg);
 891
 892         if (!(tmp & SDVO_ENABLE))
 893                 return false;
 894
 895         if (HAS_PCH_CPT(dev))
 896                 *pipe = PORT_TO_PIPE_CPT(tmp);
 897         else if (IS_CHERRYVIEW(dev))
 898                 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
 899         else
 900                 *pipe = PORT_TO_PIPE(tmp);
 901
 902         return true;
 903 }
 904
 905 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 906                                   struct intel_crtc_state *pipe_config)
 907 {
 908         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 909         struct drm_device *dev = encoder->base.dev;
 910         struct drm_i915_private *dev_priv = dev->dev_private;
 911         u32 tmp, flags = 0;
 912         int dotclock;
 913
 914         tmp = I915_READ(intel_hdmi->hdmi_reg);
 915
 916         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 917                 flags |= DRM_MODE_FLAG_PHSYNC;
 918         else
 919                 flags |= DRM_MODE_FLAG_NHSYNC;
 920
 921         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 922                 flags |= DRM_MODE_FLAG_PVSYNC;
 923         else
 924                 flags |= DRM_MODE_FLAG_NVSYNC;
 925
 926         if (tmp & HDMI_MODE_SELECT_HDMI)
 927                 pipe_config->has_hdmi_sink = true;
 928
 929         if (intel_hdmi->infoframe_enabled(&encoder->base))
 930                 pipe_config->has_infoframe = true;
 931
 932         if (tmp & SDVO_AUDIO_ENABLE)
 933                 pipe_config->has_audio = true;
 934
 935         if (!HAS_PCH_SPLIT(dev) &&
 936             tmp & HDMI_COLOR_RANGE_16_235)
 937                 pipe_config->limited_color_range = true;
 938
 939         pipe_config->base.adjusted_mode.flags |= flags;
 940
 941         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 942                 dotclock = pipe_config->port_clock * 2 / 3;
 943         else
 944                 dotclock = pipe_config->port_clock;
 945
 946         if (pipe_config->pixel_multiplier)
 947                 dotclock /= pipe_config->pixel_multiplier;
 948
 949         if (HAS_PCH_SPLIT(dev_priv->dev))
 950                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 951
 952         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
 953 }
 954
 955 static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
 956 {
 957         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 958
 959         WARN_ON(!crtc->config->has_hdmi_sink);
 960         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 961                          pipe_name(crtc->pipe));
 962         intel_audio_codec_enable(encoder);
 963 }
 964
 965 static void g4x_enable_hdmi(struct intel_encoder *encoder)
 966 {
 967         struct drm_device *dev = encoder->base.dev;
 968         struct drm_i915_private *dev_priv = dev->dev_private;
 969         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 970         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 971         u32 temp;
 972
 973         temp = I915_READ(intel_hdmi->hdmi_reg);
 974
 975         temp |= SDVO_ENABLE;
 976         if (crtc->config->has_audio)
 977                 temp |= SDVO_AUDIO_ENABLE;
 978
 979         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 980         POSTING_READ(intel_hdmi->hdmi_reg);
 981
 982         if (crtc->config->has_audio)
 983                 intel_enable_hdmi_audio(encoder);
 984 }
 985
 986 static void ibx_enable_hdmi(struct intel_encoder *encoder)
 987 {
 988         struct drm_device *dev = encoder->base.dev;
 989         struct drm_i915_private *dev_priv = dev->dev_private;
 990         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 991         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 992         u32 temp;
 993
 994         temp = I915_READ(intel_hdmi->hdmi_reg);
 995
 996         temp |= SDVO_ENABLE;
 997         if (crtc->config->has_audio)
 998                 temp |= SDVO_AUDIO_ENABLE;
 999
1000         /*
1001          * HW workaround, need to write this twice for issue
1002          * that may result in first write getting masked.
1003          */
1004         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1005         POSTING_READ(intel_hdmi->hdmi_reg);
1006         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1007         POSTING_READ(intel_hdmi->hdmi_reg);
1008
1009         /*
1010          * HW workaround, need to toggle enable bit off and on
1011          * for 12bpc with pixel repeat.
1012          *
1013          * FIXME: BSpec says this should be done at the end of
1014          * of the modeset sequence, so not sure if this isn't too soon.
1015          */
1016         if (crtc->config->pipe_bpp > 24 &&
1017             crtc->config->pixel_multiplier > 1) {
1018                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1019                 POSTING_READ(intel_hdmi->hdmi_reg);
1020
1021                 /*
1022                  * HW workaround, need to write this twice for issue
1023                  * that may result in first write getting masked.
1024                  */
1025                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1026                 POSTING_READ(intel_hdmi->hdmi_reg);
1027                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1028                 POSTING_READ(intel_hdmi->hdmi_reg);
1029         }
1030
1031         if (crtc->config->has_audio)
1032                 intel_enable_hdmi_audio(encoder);
1033 }
1034
1035 static void cpt_enable_hdmi(struct intel_encoder *encoder)
1036 {
1037         struct drm_device *dev = encoder->base.dev;
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1040         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1041         enum pipe pipe = crtc->pipe;
1042         u32 temp;
1043
1044         temp = I915_READ(intel_hdmi->hdmi_reg);
1045
1046         temp |= SDVO_ENABLE;
1047         if (crtc->config->has_audio)
1048                 temp |= SDVO_AUDIO_ENABLE;
1049
1050         /*
1051          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1052          *
1053          * The procedure for 12bpc is as follows:
1054          * 1. disable HDMI clock gating
1055          * 2. enable HDMI with 8bpc
1056          * 3. enable HDMI with 12bpc
1057          * 4. enable HDMI clock gating
1058          */
1059
1060         if (crtc->config->pipe_bpp > 24) {
1061                 I915_WRITE(TRANS_CHICKEN1(pipe),
1062                            I915_READ(TRANS_CHICKEN1(pipe)) |
1063                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1064
1065                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1066                 temp |= SDVO_COLOR_FORMAT_8bpc;
1067         }
1068
1069         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1070         POSTING_READ(intel_hdmi->hdmi_reg);
1071
1072         if (crtc->config->pipe_bpp > 24) {
1073                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1074                 temp |= HDMI_COLOR_FORMAT_12bpc;
1075
1076                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1077                 POSTING_READ(intel_hdmi->hdmi_reg);
1078
1079                 I915_WRITE(TRANS_CHICKEN1(pipe),
1080                            I915_READ(TRANS_CHICKEN1(pipe)) &
1081                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1082         }
1083
1084         if (crtc->config->has_audio)
1085                 intel_enable_hdmi_audio(encoder);
1086 }
1087
1088 static void vlv_enable_hdmi(struct intel_encoder *encoder)
1089 {
1090 }
1091
1092 static void intel_disable_hdmi(struct intel_encoder *encoder)
1093 {
1094         struct drm_device *dev = encoder->base.dev;
1095         struct drm_i915_private *dev_priv = dev->dev_private;
1096         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1097         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1098         u32 temp;
1099
1100         temp = I915_READ(intel_hdmi->hdmi_reg);
1101
1102         temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1103         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1104         POSTING_READ(intel_hdmi->hdmi_reg);
1105
1106         /*
1107          * HW workaround for IBX, we need to move the port
1108          * to transcoder A after disabling it to allow the
1109          * matching DP port to be enabled on transcoder A.
1110          */
1111         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
1112                 temp &= ~SDVO_PIPE_B_SELECT;
1113                 temp |= SDVO_ENABLE;
1114                 /*
1115                  * HW workaround, need to write this twice for issue
1116                  * that may result in first write getting masked.
1117                  */
1118                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1119                 POSTING_READ(intel_hdmi->hdmi_reg);
1120                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1121                 POSTING_READ(intel_hdmi->hdmi_reg);
1122
1123                 temp &= ~SDVO_ENABLE;
1124                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1125                 POSTING_READ(intel_hdmi->hdmi_reg);
1126         }
1127
1128         intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1129 }
1130
1131 static void g4x_disable_hdmi(struct intel_encoder *encoder)
1132 {
1133         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1134
1135         if (crtc->config->has_audio)
1136                 intel_audio_codec_disable(encoder);
1137
1138         intel_disable_hdmi(encoder);
1139 }
1140
1141 static void pch_disable_hdmi(struct intel_encoder *encoder)
1142 {
1143         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1144
1145         if (crtc->config->has_audio)
1146                 intel_audio_codec_disable(encoder);
1147 }
1148
1149 static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1150 {
1151         intel_disable_hdmi(encoder);
1152 }
1153
1154 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
1155 {
1156         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1157
1158         if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
1159                 return 165000;
1160         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
1161                 return 300000;
1162         else
1163                 return 225000;
1164 }
1165
1166 static enum drm_mode_status
1167 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1168                       int clock, bool respect_dvi_limit)
1169 {
1170         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1171
1172         if (clock < 25000)
1173                 return MODE_CLOCK_LOW;
1174         if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
1175                 return MODE_CLOCK_HIGH;
1176
1177         /* BXT DPLL can't generate 223-240 MHz */
1178         if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1179                 return MODE_CLOCK_RANGE;
1180
1181         /* CHV DPLL can't generate 216-240 MHz */
1182         if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
1183                 return MODE_CLOCK_RANGE;
1184
1185         return MODE_OK;
1186 }
1187
1188 static enum drm_mode_status
1189 intel_hdmi_mode_valid(struct drm_connector *connector,
1190                       struct drm_display_mode *mode)
1191 {
1192         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1193         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1194         enum drm_mode_status status;
1195         int clock;
1196
1197         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1198                 return MODE_NO_DBLESCAN;
1199
1200         clock = mode->clock;
1201         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1202                 clock *= 2;
1203
1204         /* check if we can do 8bpc */
1205         status = hdmi_port_clock_valid(hdmi, clock, true);
1206
1207         /* if we can't do 8bpc we may still be able to do 12bpc */
1208         if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1209                 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1210
1211         return status;
1212 }
1213
1214 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1215 {
1216         struct drm_device *dev = crtc_state->base.crtc->dev;
1217         struct drm_atomic_state *state;
1218         struct intel_encoder *encoder;
1219         struct drm_connector *connector;
1220         struct drm_connector_state *connector_state;
1221         int count = 0, count_hdmi = 0;
1222         int i;
1223
1224         if (HAS_GMCH_DISPLAY(dev))
1225                 return false;
1226
1227         state = crtc_state->base.state;
1228
1229         for_each_connector_in_state(state, connector, connector_state, i) {
1230                 if (connector_state->crtc != crtc_state->base.crtc)
1231                         continue;
1232
1233                 encoder = to_intel_encoder(connector_state->best_encoder);
1234
1235                 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1236                 count++;
1237         }
1238
1239         /*
1240          * HDMI 12bpc affects the clocks, so it's only possible
1241          * when not cloning with other encoder types.
1242          */
1243         return count_hdmi > 0 && count_hdmi == count;
1244 }
1245
1246 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1247                                struct intel_crtc_state *pipe_config)
1248 {
1249         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1250         struct drm_device *dev = encoder->base.dev;
1251         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1252         int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1253         int clock_12bpc = clock_8bpc * 3 / 2;
1254         int desired_bpp;
1255
1256         pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1257
1258         if (pipe_config->has_hdmi_sink)
1259                 pipe_config->has_infoframe = true;
1260
1261         if (intel_hdmi->color_range_auto) {
1262                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1263                 if (pipe_config->has_hdmi_sink &&
1264                     drm_match_cea_mode(adjusted_mode) > 1)
1265                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1266                 else
1267                         intel_hdmi->color_range = 0;
1268         }
1269
1270         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1271                 pipe_config->pixel_multiplier = 2;
1272                 clock_8bpc *= 2;
1273                 clock_12bpc *= 2;
1274         }
1275
1276         if (intel_hdmi->color_range)
1277                 pipe_config->limited_color_range = true;
1278
1279         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1280                 pipe_config->has_pch_encoder = true;
1281
1282         if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1283                 pipe_config->has_audio = true;
1284
1285         /*
1286          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1287          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1288          * outputs. We also need to check that the higher clock still fits
1289          * within limits.
1290          */
1291         if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1292             hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
1293             hdmi_12bpc_possible(pipe_config)) {
1294                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1295                 desired_bpp = 12*3;
1296
1297                 /* Need to adjust the port link by 1.5x for 12bpc. */
1298                 pipe_config->port_clock = clock_12bpc;
1299         } else {
1300                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1301                 desired_bpp = 8*3;
1302
1303                 pipe_config->port_clock = clock_8bpc;
1304         }
1305
1306         if (!pipe_config->bw_constrained) {
1307                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1308                 pipe_config->pipe_bpp = desired_bpp;
1309         }
1310
1311         if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1312                                   false) != MODE_OK) {
1313                 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1314                 return false;
1315         }
1316
1317         return true;
1318 }
1319
1320 static void
1321 intel_hdmi_unset_edid(struct drm_connector *connector)
1322 {
1323         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1324
1325         intel_hdmi->has_hdmi_sink = false;
1326         intel_hdmi->has_audio = false;
1327         intel_hdmi->rgb_quant_range_selectable = false;
1328
1329         kfree(to_intel_connector(connector)->detect_edid);
1330         to_intel_connector(connector)->detect_edid = NULL;
1331 }
1332
1333 static bool
1334 intel_hdmi_set_edid(struct drm_connector *connector)
1335 {
1336         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1337         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1338         struct intel_encoder *intel_encoder =
1339                 &hdmi_to_dig_port(intel_hdmi)->base;
1340         enum intel_display_power_domain power_domain;
1341         struct edid *edid;
1342         bool connected = false;
1343
1344         power_domain = intel_display_port_power_domain(intel_encoder);
1345         intel_display_power_get(dev_priv, power_domain);
1346
1347         edid = drm_get_edid(connector,
1348                             intel_gmbus_get_adapter(dev_priv,
1349                                                     intel_hdmi->ddc_bus));
1350
1351         intel_display_power_put(dev_priv, power_domain);
1352
1353         to_intel_connector(connector)->detect_edid = edid;
1354         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1355                 intel_hdmi->rgb_quant_range_selectable =
1356                         drm_rgb_quant_range_selectable(edid);
1357
1358                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1359                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1360                         intel_hdmi->has_audio =
1361                                 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1362
1363                 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1364                         intel_hdmi->has_hdmi_sink =
1365                                 drm_detect_hdmi_monitor(edid);
1366
1367                 connected = true;
1368         }
1369
1370         return connected;
1371 }
1372
1373 static enum drm_connector_status
1374 intel_hdmi_detect(struct drm_connector *connector, bool force)
1375 {
1376         enum drm_connector_status status;
1377
1378         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1379                       connector->base.id, connector->name);
1380
1381         intel_hdmi_unset_edid(connector);
1382
1383         if (intel_hdmi_set_edid(connector)) {
1384                 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1385
1386                 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1387                 status = connector_status_connected;
1388         } else
1389                 status = connector_status_disconnected;
1390
1391         return status;
1392 }
1393
1394 static void
1395 intel_hdmi_force(struct drm_connector *connector)
1396 {
1397         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1398
1399         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1400                       connector->base.id, connector->name);
1401
1402         intel_hdmi_unset_edid(connector);
1403
1404         if (connector->status != connector_status_connected)
1405                 return;
1406
1407         intel_hdmi_set_edid(connector);
1408         hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1409 }
1410
1411 static int intel_hdmi_get_modes(struct drm_connector *connector)
1412 {
1413         struct edid *edid;
1414
1415         edid = to_intel_connector(connector)->detect_edid;
1416         if (edid == NULL)
1417                 return 0;
1418
1419         return intel_connector_update_modes(connector, edid);
1420 }
1421
1422 static bool
1423 intel_hdmi_detect_audio(struct drm_connector *connector)
1424 {
1425         bool has_audio = false;
1426         struct edid *edid;
1427
1428         edid = to_intel_connector(connector)->detect_edid;
1429         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1430                 has_audio = drm_detect_monitor_audio(edid);
1431
1432         return has_audio;
1433 }
1434
1435 static int
1436 intel_hdmi_set_property(struct drm_connector *connector,
1437                         struct drm_property *property,
1438                         uint64_t val)
1439 {
1440         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1441         struct intel_digital_port *intel_dig_port =
1442                 hdmi_to_dig_port(intel_hdmi);
1443         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1444         int ret;
1445
1446         ret = drm_object_property_set_value(&connector->base, property, val);
1447         if (ret)
1448                 return ret;
1449
1450         if (property == dev_priv->force_audio_property) {
1451                 enum hdmi_force_audio i = val;
1452                 bool has_audio;
1453
1454                 if (i == intel_hdmi->force_audio)
1455                         return 0;
1456
1457                 intel_hdmi->force_audio = i;
1458
1459                 if (i == HDMI_AUDIO_AUTO)
1460                         has_audio = intel_hdmi_detect_audio(connector);
1461                 else
1462                         has_audio = (i == HDMI_AUDIO_ON);
1463
1464                 if (i == HDMI_AUDIO_OFF_DVI)
1465                         intel_hdmi->has_hdmi_sink = 0;
1466
1467                 intel_hdmi->has_audio = has_audio;
1468                 goto done;
1469         }
1470
1471         if (property == dev_priv->broadcast_rgb_property) {
1472                 bool old_auto = intel_hdmi->color_range_auto;
1473                 uint32_t old_range = intel_hdmi->color_range;
1474
1475                 switch (val) {
1476                 case INTEL_BROADCAST_RGB_AUTO:
1477                         intel_hdmi->color_range_auto = true;
1478                         break;
1479                 case INTEL_BROADCAST_RGB_FULL:
1480                         intel_hdmi->color_range_auto = false;
1481                         intel_hdmi->color_range = 0;
1482                         break;
1483                 case INTEL_BROADCAST_RGB_LIMITED:
1484                         intel_hdmi->color_range_auto = false;
1485                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1486                         break;
1487                 default:
1488                         return -EINVAL;
1489                 }
1490
1491                 if (old_auto == intel_hdmi->color_range_auto &&
1492                     old_range == intel_hdmi->color_range)
1493                         return 0;
1494
1495                 goto done;
1496         }
1497
1498         if (property == connector->dev->mode_config.aspect_ratio_property) {
1499                 switch (val) {
1500                 case DRM_MODE_PICTURE_ASPECT_NONE:
1501                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1502                         break;
1503                 case DRM_MODE_PICTURE_ASPECT_4_3:
1504                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1505                         break;
1506                 case DRM_MODE_PICTURE_ASPECT_16_9:
1507                         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1508                         break;
1509                 default:
1510                         return -EINVAL;
1511                 }
1512                 goto done;
1513         }
1514
1515         return -EINVAL;
1516
1517 done:
1518         if (intel_dig_port->base.base.crtc)
1519                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1520
1521         return 0;
1522 }
1523
1524 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1525 {
1526         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1527         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1528         struct drm_display_mode *adjusted_mode =
1529                 &intel_crtc->config->base.adjusted_mode;
1530
1531         intel_hdmi_prepare(encoder);
1532
1533         intel_hdmi->set_infoframes(&encoder->base,
1534                                    intel_crtc->config->has_hdmi_sink,
1535                                    adjusted_mode);
1536 }
1537
1538 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1539 {
1540         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1541         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1542         struct drm_device *dev = encoder->base.dev;
1543         struct drm_i915_private *dev_priv = dev->dev_private;
1544         struct intel_crtc *intel_crtc =
1545                 to_intel_crtc(encoder->base.crtc);
1546         struct drm_display_mode *adjusted_mode =
1547                 &intel_crtc->config->base.adjusted_mode;
1548         enum dpio_channel port = vlv_dport_to_channel(dport);
1549         int pipe = intel_crtc->pipe;
1550         u32 val;
1551
1552         /* Enable clock channels for this port */
1553         mutex_lock(&dev_priv->sb_lock);
1554         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1555         val = 0;
1556         if (pipe)
1557                 val |= (1<<21);
1558         else
1559                 val &= ~(1<<21);
1560         val |= 0x001000c4;
1561         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1562
1563         /* HDMI 1.0V-2dB */
1564         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1565         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1566         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1567         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1568         vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1569         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1570         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1571         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1572
1573         /* Program lane clock */
1574         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1575         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1576         mutex_unlock(&dev_priv->sb_lock);
1577
1578         intel_hdmi->set_infoframes(&encoder->base,
1579                                    intel_crtc->config->has_hdmi_sink,
1580                                    adjusted_mode);
1581
1582         g4x_enable_hdmi(encoder);
1583
1584         vlv_wait_port_ready(dev_priv, dport, 0x0);
1585 }
1586
1587 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1588 {
1589         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1590         struct drm_device *dev = encoder->base.dev;
1591         struct drm_i915_private *dev_priv = dev->dev_private;
1592         struct intel_crtc *intel_crtc =
1593                 to_intel_crtc(encoder->base.crtc);
1594         enum dpio_channel port = vlv_dport_to_channel(dport);
1595         int pipe = intel_crtc->pipe;
1596
1597         intel_hdmi_prepare(encoder);
1598
1599         /* Program Tx lane resets to default */
1600         mutex_lock(&dev_priv->sb_lock);
1601         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1602                          DPIO_PCS_TX_LANE2_RESET |
1603                          DPIO_PCS_TX_LANE1_RESET);
1604         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1605                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1606                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1607                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1608                          DPIO_PCS_CLK_SOFT_RESET);
1609
1610         /* Fix up inter-pair skew failure */
1611         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1612         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1613         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1614
1615         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1616         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1617         mutex_unlock(&dev_priv->sb_lock);
1618 }
1619
1620 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1621 {
1622         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1623         struct drm_device *dev = encoder->base.dev;
1624         struct drm_i915_private *dev_priv = dev->dev_private;
1625         struct intel_crtc *intel_crtc =
1626                 to_intel_crtc(encoder->base.crtc);
1627         enum dpio_channel ch = vlv_dport_to_channel(dport);
1628         enum pipe pipe = intel_crtc->pipe;
1629         u32 val;
1630
1631         intel_hdmi_prepare(encoder);
1632
1633         mutex_lock(&dev_priv->sb_lock);
1634
1635         /* program left/right clock distribution */
1636         if (pipe != PIPE_B) {
1637                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1638                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1639                 if (ch == DPIO_CH0)
1640                         val |= CHV_BUFLEFTENA1_FORCE;
1641                 if (ch == DPIO_CH1)
1642                         val |= CHV_BUFRIGHTENA1_FORCE;
1643                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1644         } else {
1645                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1646                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1647                 if (ch == DPIO_CH0)
1648                         val |= CHV_BUFLEFTENA2_FORCE;
1649                 if (ch == DPIO_CH1)
1650                         val |= CHV_BUFRIGHTENA2_FORCE;
1651                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1652         }
1653
1654         /* program clock channel usage */
1655         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1656         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1657         if (pipe != PIPE_B)
1658                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1659         else
1660                 val |= CHV_PCS_USEDCLKCHANNEL;
1661         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1662
1663         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1664         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1665         if (pipe != PIPE_B)
1666                 val &= ~CHV_PCS_USEDCLKCHANNEL;
1667         else
1668                 val |= CHV_PCS_USEDCLKCHANNEL;
1669         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1670
1671         /*
1672          * This a a bit weird since generally CL
1673          * matches the pipe, but here we need to
1674          * pick the CL based on the port.
1675          */
1676         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1677         if (pipe != PIPE_B)
1678                 val &= ~CHV_CMN_USEDCLKCHANNEL;
1679         else
1680                 val |= CHV_CMN_USEDCLKCHANNEL;
1681         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1682
1683         mutex_unlock(&dev_priv->sb_lock);
1684 }
1685
1686 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1687 {
1688         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1689         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1690         struct intel_crtc *intel_crtc =
1691                 to_intel_crtc(encoder->base.crtc);
1692         enum dpio_channel port = vlv_dport_to_channel(dport);
1693         int pipe = intel_crtc->pipe;
1694
1695         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1696         mutex_lock(&dev_priv->sb_lock);
1697         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1698         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1699         mutex_unlock(&dev_priv->sb_lock);
1700 }
1701
1702 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1703 {
1704         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1705         struct drm_device *dev = encoder->base.dev;
1706         struct drm_i915_private *dev_priv = dev->dev_private;
1707         struct intel_crtc *intel_crtc =
1708                 to_intel_crtc(encoder->base.crtc);
1709         enum dpio_channel ch = vlv_dport_to_channel(dport);
1710         enum pipe pipe = intel_crtc->pipe;
1711         u32 val;
1712
1713         mutex_lock(&dev_priv->sb_lock);
1714
1715         /* Propagate soft reset to data lane reset */
1716         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1717         val |= CHV_PCS_REQ_SOFTRESET_EN;
1718         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1719
1720         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1721         val |= CHV_PCS_REQ_SOFTRESET_EN;
1722         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1723
1724         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1725         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1726         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1727
1728         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1729         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1730         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1731
1732         mutex_unlock(&dev_priv->sb_lock);
1733 }
1734
1735 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1736 {
1737         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1738         struct intel_hdmi *intel_hdmi = &dport->hdmi;
1739         struct drm_device *dev = encoder->base.dev;
1740         struct drm_i915_private *dev_priv = dev->dev_private;
1741         struct intel_crtc *intel_crtc =
1742                 to_intel_crtc(encoder->base.crtc);
1743         struct drm_display_mode *adjusted_mode =
1744                 &intel_crtc->config->base.adjusted_mode;
1745         enum dpio_channel ch = vlv_dport_to_channel(dport);
1746         int pipe = intel_crtc->pipe;
1747         int data, i, stagger;
1748         u32 val;
1749
1750         mutex_lock(&dev_priv->sb_lock);
1751
1752         /* allow hardware to manage TX FIFO reset source */
1753         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1754         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1755         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1756
1757         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1758         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1759         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1760
1761         /* Deassert soft data lane reset*/
1762         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1763         val |= CHV_PCS_REQ_SOFTRESET_EN;
1764         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1765
1766         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1767         val |= CHV_PCS_REQ_SOFTRESET_EN;
1768         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1769
1770         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1771         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1772         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1773
1774         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1775         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1776         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1777
1778         /* Program Tx latency optimal setting */
1779         for (i = 0; i < 4; i++) {
1780                 /* Set the upar bit */
1781                 data = (i == 1) ? 0x0 : 0x1;
1782                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1783                                 data << DPIO_UPAR_SHIFT);
1784         }
1785
1786         /* Data lane stagger programming */
1787         if (intel_crtc->config->port_clock > 270000)
1788                 stagger = 0x18;
1789         else if (intel_crtc->config->port_clock > 135000)
1790                 stagger = 0xd;
1791         else if (intel_crtc->config->port_clock > 67500)
1792                 stagger = 0x7;
1793         else if (intel_crtc->config->port_clock > 33750)
1794                 stagger = 0x4;
1795         else
1796                 stagger = 0x2;
1797
1798         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1799         val |= DPIO_TX2_STAGGER_MASK(0x1f);
1800         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1801
1802         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1803         val |= DPIO_TX2_STAGGER_MASK(0x1f);
1804         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1805
1806         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1807                        DPIO_LANESTAGGER_STRAP(stagger) |
1808                        DPIO_LANESTAGGER_STRAP_OVRD |
1809                        DPIO_TX1_STAGGER_MASK(0x1f) |
1810                        DPIO_TX1_STAGGER_MULT(6) |
1811                        DPIO_TX2_STAGGER_MULT(0));
1812
1813         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1814                        DPIO_LANESTAGGER_STRAP(stagger) |
1815                        DPIO_LANESTAGGER_STRAP_OVRD |
1816                        DPIO_TX1_STAGGER_MASK(0x1f) |
1817                        DPIO_TX1_STAGGER_MULT(7) |
1818                        DPIO_TX2_STAGGER_MULT(5));
1819
1820         /* Clear calc init */
1821         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1822         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1823         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1824         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1825         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1826
1827         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1828         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1829         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1830         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1831         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1832
1833         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1834         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1835         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1836         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1837
1838         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1839         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1840         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1841         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1842
1843         /* FIXME: Program the support xxx V-dB */
1844         /* Use 800mV-0dB */
1845         for (i = 0; i < 4; i++) {
1846                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1847                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1848                 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1849                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1850         }
1851
1852         for (i = 0; i < 4; i++) {
1853                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1854                 val &= ~DPIO_SWING_MARGIN000_MASK;
1855                 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1856                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1857         }
1858
1859         /* Disable unique transition scale */
1860         for (i = 0; i < 4; i++) {
1861                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1862                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1863                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1864         }
1865
1866         /* Additional steps for 1200mV-0dB */
1867 #if 0
1868         val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
1869         if (ch)
1870                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
1871         else
1872                 val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
1873         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
1874
1875         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
1876                         vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
1877                                 (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
1878 #endif
1879         /* Start swing calculation */
1880         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1881         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1882         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1883
1884         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1885         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1886         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1887
1888         /* LRC Bypass */
1889         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1890         val |= DPIO_LRC_BYPASS;
1891         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
1892
1893         mutex_unlock(&dev_priv->sb_lock);
1894
1895         intel_hdmi->set_infoframes(&encoder->base,
1896                                    intel_crtc->config->has_hdmi_sink,
1897                                    adjusted_mode);
1898
1899         g4x_enable_hdmi(encoder);
1900
1901         vlv_wait_port_ready(dev_priv, dport, 0x0);
1902 }
1903
1904 static void intel_hdmi_destroy(struct drm_connector *connector)
1905 {
1906         kfree(to_intel_connector(connector)->detect_edid);
1907         drm_connector_cleanup(connector);
1908         kfree(connector);
1909 }
1910
1911 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1912         .dpms = drm_atomic_helper_connector_dpms,
1913         .detect = intel_hdmi_detect,
1914         .force = intel_hdmi_force,
1915         .fill_modes = drm_helper_probe_single_connector_modes,
1916         .set_property = intel_hdmi_set_property,
1917         .atomic_get_property = intel_connector_atomic_get_property,
1918         .destroy = intel_hdmi_destroy,
1919         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1920         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1921 };
1922
1923 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1924         .get_modes = intel_hdmi_get_modes,
1925         .mode_valid = intel_hdmi_mode_valid,
1926         .best_encoder = intel_best_encoder,
1927 };
1928
1929 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1930         .destroy = intel_encoder_destroy,
1931 };
1932
1933 static void
1934 intel_attach_aspect_ratio_property(struct drm_connector *connector)
1935 {
1936         if (!drm_mode_create_aspect_ratio_property(connector->dev))
1937                 drm_object_attach_property(&connector->base,
1938                         connector->dev->mode_config.aspect_ratio_property,
1939                         DRM_MODE_PICTURE_ASPECT_NONE);
1940 }
1941
1942 static void
1943 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1944 {
1945         intel_attach_force_audio_property(connector);
1946         intel_attach_broadcast_rgb_property(connector);
1947         intel_hdmi->color_range_auto = true;
1948         intel_attach_aspect_ratio_property(connector);
1949         intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1950 }
1951
1952 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1953                                struct intel_connector *intel_connector)
1954 {
1955         struct drm_connector *connector = &intel_connector->base;
1956         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1957         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1958         struct drm_device *dev = intel_encoder->base.dev;
1959         struct drm_i915_private *dev_priv = dev->dev_private;
1960         enum port port = intel_dig_port->port;
1961
1962         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1963                            DRM_MODE_CONNECTOR_HDMIA);
1964         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1965
1966         connector->interlace_allowed = 1;
1967         connector->doublescan_allowed = 0;
1968         connector->stereo_allowed = 1;
1969
1970         switch (port) {
1971         case PORT_B:
1972                 if (IS_BROXTON(dev_priv))
1973                         intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
1974                 else
1975                         intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
1976                 /*
1977                  * On BXT A0/A1, sw needs to activate DDIA HPD logic and
1978                  * interrupts to check the external panel connection.
1979                  */
1980                 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0))
1981                         intel_encoder->hpd_pin = HPD_PORT_A;
1982                 else
1983                         intel_encoder->hpd_pin = HPD_PORT_B;
1984                 break;
1985         case PORT_C:
1986                 if (IS_BROXTON(dev_priv))
1987                         intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
1988                 else
1989                         intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
1990                 intel_encoder->hpd_pin = HPD_PORT_C;
1991                 break;
1992         case PORT_D:
1993                 if (WARN_ON(IS_BROXTON(dev_priv)))
1994                         intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
1995                 else if (IS_CHERRYVIEW(dev_priv))
1996                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
1997                 else
1998                         intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
1999                 intel_encoder->hpd_pin = HPD_PORT_D;
2000                 break;
2001         case PORT_A:
2002                 intel_encoder->hpd_pin = HPD_PORT_A;
2003                 /* Internal port only for eDP. */
2004         default:
2005                 BUG();
2006         }
2007
2008         if (IS_VALLEYVIEW(dev)) {
2009                 intel_hdmi->write_infoframe = vlv_write_infoframe;
2010                 intel_hdmi->set_infoframes = vlv_set_infoframes;
2011                 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
2012         } else if (IS_G4X(dev)) {
2013                 intel_hdmi->write_infoframe = g4x_write_infoframe;
2014                 intel_hdmi->set_infoframes = g4x_set_infoframes;
2015                 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
2016         } else if (HAS_DDI(dev)) {
2017                 intel_hdmi->write_infoframe = hsw_write_infoframe;
2018                 intel_hdmi->set_infoframes = hsw_set_infoframes;
2019                 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
2020         } else if (HAS_PCH_IBX(dev)) {
2021                 intel_hdmi->write_infoframe = ibx_write_infoframe;
2022                 intel_hdmi->set_infoframes = ibx_set_infoframes;
2023                 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2024         } else {
2025                 intel_hdmi->write_infoframe = cpt_write_infoframe;
2026                 intel_hdmi->set_infoframes = cpt_set_infoframes;
2027                 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2028         }
2029
2030         if (HAS_DDI(dev))
2031                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2032         else
2033                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2034         intel_connector->unregister = intel_connector_unregister;
2035
2036         intel_hdmi_add_properties(intel_hdmi, connector);
2037
2038         intel_connector_attach_encoder(intel_connector, intel_encoder);
2039         drm_connector_register(connector);
2040
2041         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2042          * 0xd.  Failure to do so will result in spurious interrupts being
2043          * generated on the port when a cable is not attached.
2044          */
2045         if (IS_G4X(dev) && !IS_GM45(dev)) {
2046                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2047                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2048         }
2049 }
2050
2051 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
2052 {
2053         struct intel_digital_port *intel_dig_port;
2054         struct intel_encoder *intel_encoder;
2055         struct intel_connector *intel_connector;
2056
2057         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2058         if (!intel_dig_port)
2059                 return;
2060
2061         intel_connector = intel_connector_alloc();
2062         if (!intel_connector) {
2063                 kfree(intel_dig_port);
2064                 return;
2065         }
2066
2067         intel_encoder = &intel_dig_port->base;
2068
2069         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
2070                          DRM_MODE_ENCODER_TMDS);
2071
2072         intel_encoder->compute_config = intel_hdmi_compute_config;
2073         if (HAS_PCH_SPLIT(dev)) {
2074                 intel_encoder->disable = pch_disable_hdmi;
2075                 intel_encoder->post_disable = pch_post_disable_hdmi;
2076         } else {
2077                 intel_encoder->disable = g4x_disable_hdmi;
2078         }
2079         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2080         intel_encoder->get_config = intel_hdmi_get_config;
2081         if (IS_CHERRYVIEW(dev)) {
2082                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2083                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2084                 intel_encoder->enable = vlv_enable_hdmi;
2085                 intel_encoder->post_disable = chv_hdmi_post_disable;
2086         } else if (IS_VALLEYVIEW(dev)) {
2087                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2088                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2089                 intel_encoder->enable = vlv_enable_hdmi;
2090                 intel_encoder->post_disable = vlv_hdmi_post_disable;
2091         } else {
2092                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2093                 if (HAS_PCH_CPT(dev))
2094                         intel_encoder->enable = cpt_enable_hdmi;
2095                 else if (HAS_PCH_IBX(dev))
2096                         intel_encoder->enable = ibx_enable_hdmi;
2097                 else
2098                         intel_encoder->enable = g4x_enable_hdmi;
2099         }
2100
2101         intel_encoder->type = INTEL_OUTPUT_HDMI;
2102         if (IS_CHERRYVIEW(dev)) {
2103                 if (port == PORT_D)
2104                         intel_encoder->crtc_mask = 1 << 2;
2105                 else
2106                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2107         } else {
2108                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2109         }
2110         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2111         /*
2112          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2113          * to work on real hardware. And since g4x can send infoframes to
2114          * only one port anyway, nothing is lost by allowing it.
2115          */
2116         if (IS_G4X(dev))
2117                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2118
2119         intel_dig_port->port = port;
2120         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2121         intel_dig_port->dp.output_reg = 0;
2122
2123         intel_hdmi_init_connector(intel_dig_port, intel_connector);
2124 }