drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_fb_helper.h>
  36 #include <drm/drm_dp_mst_helper.h>
  37 #include <drm/drm_rect.h>
  38 #include <drm/drm_atomic.h>
  39
  40 #define DIV_ROUND_CLOSEST_ULL(ll, d)    \
  41 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
  42
  43 /**
  44  * _wait_for - magic (register) wait macro
  45  *
  46  * Does the right thing for modeset paths when run under kdgb or similar atomic
  47  * contexts. Note that it's important that we check the condition again after
  48  * having timed out, since the timeout could be due to preemption or similar and
  49  * we've never had a chance to check the condition before the timeout.
  50  */
  51 #define _wait_for(COND, MS, W) ({ \
  52         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1;   \
  53         int ret__ = 0;                                                  \
  54         while (!(COND)) {                                               \
  55                 if (time_after(jiffies, timeout__)) {                   \
  56                         if (!(COND))                                    \
  57                                 ret__ = -ETIMEDOUT;                     \
  58                         break;                                          \
  59                 }                                                       \
  60                 if ((W) && drm_can_sleep()) {                           \
  61                         usleep_range((W)*1000, (W)*2000);               \
  62                 } else {                                                \
  63                         cpu_relax();                                    \
  64                 }                                                       \
  65         }                                                               \
  66         ret__;                                                          \
  67 })
  68
  69 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
  70 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
  71 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
  72                                                DIV_ROUND_UP((US), 1000), 0)
  73
  74 #define KHz(x) (1000 * (x))
  75 #define MHz(x) KHz(1000 * (x))
  76
  77 /*
  78  * Display related stuff
  79  */
  80
  81 /* store information about an Ixxx DVO */
  82 /* The i830->i865 use multiple DVOs with multiple i2cs */
  83 /* the i915, i945 have a single sDVO i2c bus - which is different */
  84 #define MAX_OUTPUTS 6
  85 /* maximum connectors per crtcs in the mode set */
  86
  87 /* Maximum cursor sizes */
  88 #define GEN2_CURSOR_WIDTH 64
  89 #define GEN2_CURSOR_HEIGHT 64
  90 #define MAX_CURSOR_WIDTH 256
  91 #define MAX_CURSOR_HEIGHT 256
  92
  93 #define INTEL_I2C_BUS_DVO 1
  94 #define INTEL_I2C_BUS_SDVO 2
  95
  96 /* these are outputs from the chip - integrated only
  97    external chips are via DVO or SDVO output */
  98 enum intel_output_type {
  99         INTEL_OUTPUT_UNUSED = 0,
 100         INTEL_OUTPUT_ANALOG = 1,
 101         INTEL_OUTPUT_DVO = 2,
 102         INTEL_OUTPUT_SDVO = 3,
 103         INTEL_OUTPUT_LVDS = 4,
 104         INTEL_OUTPUT_TVOUT = 5,
 105         INTEL_OUTPUT_HDMI = 6,
 106         INTEL_OUTPUT_DISPLAYPORT = 7,
 107         INTEL_OUTPUT_EDP = 8,
 108         INTEL_OUTPUT_DSI = 9,
 109         INTEL_OUTPUT_UNKNOWN = 10,
 110         INTEL_OUTPUT_DP_MST = 11,
 111 };
 112
 113 #define INTEL_DVO_CHIP_NONE 0
 114 #define INTEL_DVO_CHIP_LVDS 1
 115 #define INTEL_DVO_CHIP_TMDS 2
 116 #define INTEL_DVO_CHIP_TVOUT 4
 117
 118 #define INTEL_DSI_VIDEO_MODE    0
 119 #define INTEL_DSI_COMMAND_MODE  1
 120
 121 struct intel_framebuffer {
 122         struct drm_framebuffer base;
 123         struct drm_i915_gem_object *obj;
 124 };
 125
 126 struct intel_fbdev {
 127         struct drm_fb_helper helper;
 128         struct intel_framebuffer *fb;
 129         struct list_head fbdev_list;
 130         struct drm_display_mode *our_mode;
 131         int preferred_bpp;
 132 };
 133
 134 struct intel_encoder {
 135         struct drm_encoder base;
 136         /*
 137          * The new crtc this encoder will be driven from. Only differs from
 138          * base->crtc while a modeset is in progress.
 139          */
 140         struct intel_crtc *new_crtc;
 141
 142         enum intel_output_type type;
 143         unsigned int cloneable;
 144         bool connectors_active;
 145         void (*hot_plug)(struct intel_encoder *);
 146         bool (*compute_config)(struct intel_encoder *,
 147                                struct intel_crtc_state *);
 148         void (*pre_pll_enable)(struct intel_encoder *);
 149         void (*pre_enable)(struct intel_encoder *);
 150         void (*enable)(struct intel_encoder *);
 151         void (*mode_set)(struct intel_encoder *intel_encoder);
 152         void (*disable)(struct intel_encoder *);
 153         void (*post_disable)(struct intel_encoder *);
 154         /* Read out the current hw state of this connector, returning true if
 155          * the encoder is active. If the encoder is enabled it also set the pipe
 156          * it is connected to in the pipe parameter. */
 157         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 158         /* Reconstructs the equivalent mode flags for the current hardware
 159          * state. This must be called _after_ display->get_pipe_config has
 160          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 161          * be set correctly before calling this function. */
 162         void (*get_config)(struct intel_encoder *,
 163                            struct intel_crtc_state *pipe_config);
 164         /*
 165          * Called during system suspend after all pending requests for the
 166          * encoder are flushed (for example for DP AUX transactions) and
 167          * device interrupts are disabled.
 168          */
 169         void (*suspend)(struct intel_encoder *);
 170         int crtc_mask;
 171         enum hpd_pin hpd_pin;
 172 };
 173
 174 struct intel_panel {
 175         struct drm_display_mode *fixed_mode;
 176         struct drm_display_mode *downclock_mode;
 177         int fitting_mode;
 178
 179         /* backlight */
 180         struct {
 181                 bool present;
 182                 u32 level;
 183                 u32 min;
 184                 u32 max;
 185                 bool enabled;
 186                 bool combination_mode;  /* gen 2/4 only */
 187                 bool active_low_pwm;
 188                 struct backlight_device *device;
 189         } backlight;
 190
 191         void (*backlight_power)(struct intel_connector *, bool enable);
 192 };
 193
 194 struct intel_connector {
 195         struct drm_connector base;
 196         /*
 197          * The fixed encoder this connector is connected to.
 198          */
 199         struct intel_encoder *encoder;
 200
 201         /*
 202          * The new encoder this connector will be driven. Only differs from
 203          * encoder while a modeset is in progress.
 204          */
 205         struct intel_encoder *new_encoder;
 206
 207         /* Reads out the current hw, returning true if the connector is enabled
 208          * and active (i.e. dpms ON state). */
 209         bool (*get_hw_state)(struct intel_connector *);
 210
 211         /*
 212          * Removes all interfaces through which the connector is accessible
 213          * - like sysfs, debugfs entries -, so that no new operations can be
 214          * started on the connector. Also makes sure all currently pending
 215          * operations finish before returing.
 216          */
 217         void (*unregister)(struct intel_connector *);
 218
 219         /* Panel info for eDP and LVDS */
 220         struct intel_panel panel;
 221
 222         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 223         struct edid *edid;
 224         struct edid *detect_edid;
 225
 226         /* since POLL and HPD connectors may use the same HPD line keep the native
 227            state of connector->polled in case hotplug storm detection changes it */
 228         u8 polled;
 229
 230         void *port; /* store this opaque as its illegal to dereference it */
 231
 232         struct intel_dp *mst_port;
 233 };
 234
 235 typedef struct dpll {
 236         /* given values */
 237         int n;
 238         int m1, m2;
 239         int p1, p2;
 240         /* derived values */
 241         int     dot;
 242         int     vco;
 243         int     m;
 244         int     p;
 245 } intel_clock_t;
 246
 247 struct intel_plane_state {
 248         struct drm_plane_state base;
 249         struct drm_rect src;
 250         struct drm_rect dst;
 251         struct drm_rect clip;
 252         bool visible;
 253
 254         /*
 255          * used only for sprite planes to determine when to implicitly
 256          * enable/disable the primary plane
 257          */
 258         bool hides_primary;
 259 };
 260
 261 struct intel_initial_plane_config {
 262         struct intel_framebuffer *fb;
 263         unsigned int tiling;
 264         int size;
 265         u32 base;
 266 };
 267
 268 struct intel_crtc_state {
 269         struct drm_crtc_state base;
 270
 271         /**
 272          * quirks - bitfield with hw state readout quirks
 273          *
 274          * For various reasons the hw state readout code might not be able to
 275          * completely faithfully read out the current state. These cases are
 276          * tracked with quirk flags so that fastboot and state checker can act
 277          * accordingly.
 278          */
 279 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 280 #define PIPE_CONFIG_QUIRK_INHERITED_MODE        (1<<1) /* mode inherited from firmware */
 281         unsigned long quirks;
 282
 283         /* Pipe source size (ie. panel fitter input size)
 284          * All planes will be positioned inside this space,
 285          * and get clipped at the edges. */
 286         int pipe_src_w, pipe_src_h;
 287
 288         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 289          * between pch encoders and cpu encoders. */
 290         bool has_pch_encoder;
 291
 292         /* Are we sending infoframes on the attached port */
 293         bool has_infoframe;
 294
 295         /* CPU Transcoder for the pipe. Currently this can only differ from the
 296          * pipe on Haswell (where we have a special eDP transcoder). */
 297         enum transcoder cpu_transcoder;
 298
 299         /*
 300          * Use reduced/limited/broadcast rbg range, compressing from the full
 301          * range fed into the crtcs.
 302          */
 303         bool limited_color_range;
 304
 305         /* DP has a bunch of special case unfortunately, so mark the pipe
 306          * accordingly. */
 307         bool has_dp_encoder;
 308
 309         /* Whether we should send NULL infoframes. Required for audio. */
 310         bool has_hdmi_sink;
 311
 312         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 313          * has_dp_encoder is set. */
 314         bool has_audio;
 315
 316         /*
 317          * Enable dithering, used when the selected pipe bpp doesn't match the
 318          * plane bpp.
 319          */
 320         bool dither;
 321
 322         /* Controls for the clock computation, to override various stages. */
 323         bool clock_set;
 324
 325         /* SDVO TV has a bunch of special case. To make multifunction encoders
 326          * work correctly, we need to track this at runtime.*/
 327         bool sdvo_tv_clock;
 328
 329         /*
 330          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 331          * required. This is set in the 2nd loop of calling encoder's
 332          * ->compute_config if the first pick doesn't work out.
 333          */
 334         bool bw_constrained;
 335
 336         /* Settings for the intel dpll used on pretty much everything but
 337          * haswell. */
 338         struct dpll dpll;
 339
 340         /* Selected dpll when shared or DPLL_ID_PRIVATE. */
 341         enum intel_dpll_id shared_dpll;
 342
 343         /*
 344          * - PORT_CLK_SEL for DDI ports on HSW/BDW.
 345          * - enum skl_dpll on SKL
 346          */
 347         uint32_t ddi_pll_sel;
 348
 349         /* Actual register state of the dpll, for shared dpll cross-checking. */
 350         struct intel_dpll_hw_state dpll_hw_state;
 351
 352         int pipe_bpp;
 353         struct intel_link_m_n dp_m_n;
 354
 355         /* m2_n2 for eDP downclock */
 356         struct intel_link_m_n dp_m2_n2;
 357         bool has_drrs;
 358
 359         /*
 360          * Frequence the dpll for the port should run at. Differs from the
 361          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 362          * already multiplied by pixel_multiplier.
 363          */
 364         int port_clock;
 365
 366         /* Used by SDVO (and if we ever fix it, HDMI). */
 367         unsigned pixel_multiplier;
 368
 369         /* Panel fitter controls for gen2-gen4 + VLV */
 370         struct {
 371                 u32 control;
 372                 u32 pgm_ratios;
 373                 u32 lvds_border_bits;
 374         } gmch_pfit;
 375
 376         /* Panel fitter placement and size for Ironlake+ */
 377         struct {
 378                 u32 pos;
 379                 u32 size;
 380                 bool enabled;
 381                 bool force_thru;
 382         } pch_pfit;
 383
 384         /* FDI configuration, only valid if has_pch_encoder is set. */
 385         int fdi_lanes;
 386         struct intel_link_m_n fdi_m_n;
 387
 388         bool ips_enabled;
 389
 390         bool double_wide;
 391
 392         bool dp_encoder_is_mst;
 393         int pbn;
 394 };
 395
 396 struct intel_pipe_wm {
 397         struct intel_wm_level wm[5];
 398         uint32_t linetime;
 399         bool fbc_wm_enabled;
 400         bool pipe_enabled;
 401         bool sprites_enabled;
 402         bool sprites_scaled;
 403 };
 404
 405 struct intel_mmio_flip {
 406         struct drm_i915_gem_request *req;
 407         struct work_struct work;
 408 };
 409
 410 struct skl_pipe_wm {
 411         struct skl_wm_level wm[8];
 412         struct skl_wm_level trans_wm;
 413         uint32_t linetime;
 414 };
 415
 416 /*
 417  * Tracking of operations that need to be performed at the beginning/end of an
 418  * atomic commit, outside the atomic section where interrupts are disabled.
 419  * These are generally operations that grab mutexes or might otherwise sleep
 420  * and thus can't be run with interrupts disabled.
 421  */
 422 struct intel_crtc_atomic_commit {
 423         /* vblank evasion */
 424         bool evade;
 425         unsigned start_vbl_count;
 426
 427         /* Sleepable operations to perform before commit */
 428         bool wait_for_flips;
 429         bool disable_fbc;
 430         bool pre_disable_primary;
 431         bool update_wm;
 432         unsigned disabled_planes;
 433
 434         /* Sleepable operations to perform after commit */
 435         unsigned fb_bits;
 436         bool wait_vblank;
 437         bool update_fbc;
 438         bool post_enable_primary;
 439         unsigned update_sprite_watermarks;
 440 };
 441
 442 struct intel_crtc {
 443         struct drm_crtc base;
 444         enum pipe pipe;
 445         enum plane plane;
 446         u8 lut_r[256], lut_g[256], lut_b[256];
 447         /*
 448          * Whether the crtc and the connected output pipeline is active. Implies
 449          * that crtc->enabled is set, i.e. the current mode configuration has
 450          * some outputs connected to this crtc.
 451          */
 452         bool active;
 453         unsigned long enabled_power_domains;
 454         bool primary_enabled; /* is the primary plane (partially) visible? */
 455         bool lowfreq_avail;
 456         struct intel_overlay *overlay;
 457         struct intel_unpin_work *unpin_work;
 458
 459         atomic_t unpin_work_count;
 460
 461         /* Display surface base address adjustement for pageflips. Note that on
 462          * gen4+ this only adjusts up to a tile, offsets within a tile are
 463          * handled in the hw itself (with the TILEOFF register). */
 464         unsigned long dspaddr_offset;
 465
 466         struct drm_i915_gem_object *cursor_bo;
 467         uint32_t cursor_addr;
 468         uint32_t cursor_cntl;
 469         uint32_t cursor_size;
 470         uint32_t cursor_base;
 471
 472         struct intel_initial_plane_config plane_config;
 473         struct intel_crtc_state *config;
 474         bool new_enabled;
 475
 476         /* reset counter value when the last flip was submitted */
 477         unsigned int reset_counter;
 478
 479         /* Access to these should be protected by dev_priv->irq_lock. */
 480         bool cpu_fifo_underrun_disabled;
 481         bool pch_fifo_underrun_disabled;
 482
 483         /* per-pipe watermark state */
 484         struct {
 485                 /* watermarks currently being used  */
 486                 struct intel_pipe_wm active;
 487                 /* SKL wm values currently in use */
 488                 struct skl_pipe_wm skl_active;
 489         } wm;
 490
 491         int scanline_offset;
 492         struct intel_mmio_flip mmio_flip;
 493
 494         struct intel_crtc_atomic_commit atomic;
 495 };
 496
 497 struct intel_plane_wm_parameters {
 498         uint32_t horiz_pixels;
 499         uint32_t vert_pixels;
 500         uint8_t bytes_per_pixel;
 501         bool enabled;
 502         bool scaled;
 503         u64 tiling;
 504         unsigned int rotation;
 505 };
 506
 507 struct intel_plane {
 508         struct drm_plane base;
 509         int plane;
 510         enum pipe pipe;
 511         bool can_scale;
 512         int max_downscale;
 513
 514         /* FIXME convert to properties */
 515         struct drm_intel_sprite_colorkey ckey;
 516
 517         /* Since we need to change the watermarks before/after
 518          * enabling/disabling the planes, we need to store the parameters here
 519          * as the other pieces of the struct may not reflect the values we want
 520          * for the watermark calculations. Currently only Haswell uses this.
 521          */
 522         struct intel_plane_wm_parameters wm;
 523
 524         /*
 525          * NOTE: Do not place new plane state fields here (e.g., when adding
 526          * new plane properties).  New runtime state should now be placed in
 527          * the intel_plane_state structure and accessed via drm_plane->state.
 528          */
 529
 530         void (*update_plane)(struct drm_plane *plane,
 531                              struct drm_crtc *crtc,
 532                              struct drm_framebuffer *fb,
 533                              int crtc_x, int crtc_y,
 534                              unsigned int crtc_w, unsigned int crtc_h,
 535                              uint32_t x, uint32_t y,
 536                              uint32_t src_w, uint32_t src_h);
 537         void (*disable_plane)(struct drm_plane *plane,
 538                               struct drm_crtc *crtc);
 539         int (*check_plane)(struct drm_plane *plane,
 540                            struct intel_plane_state *state);
 541         void (*commit_plane)(struct drm_plane *plane,
 542                              struct intel_plane_state *state);
 543 };
 544
 545 struct intel_watermark_params {
 546         unsigned long fifo_size;
 547         unsigned long max_wm;
 548         unsigned long default_wm;
 549         unsigned long guard_size;
 550         unsigned long cacheline_size;
 551 };
 552
 553 struct cxsr_latency {
 554         int is_desktop;
 555         int is_ddr3;
 556         unsigned long fsb_freq;
 557         unsigned long mem_freq;
 558         unsigned long display_sr;
 559         unsigned long display_hpll_disable;
 560         unsigned long cursor_sr;
 561         unsigned long cursor_hpll_disable;
 562 };
 563
 564 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 565 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 566 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 567 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 568 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 569 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 570 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 571 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 572
 573 struct intel_hdmi {
 574         u32 hdmi_reg;
 575         int ddc_bus;
 576         uint32_t color_range;
 577         bool color_range_auto;
 578         bool has_hdmi_sink;
 579         bool has_audio;
 580         enum hdmi_force_audio force_audio;
 581         bool rgb_quant_range_selectable;
 582         enum hdmi_picture_aspect aspect_ratio;
 583         void (*write_infoframe)(struct drm_encoder *encoder,
 584                                 enum hdmi_infoframe_type type,
 585                                 const void *frame, ssize_t len);
 586         void (*set_infoframes)(struct drm_encoder *encoder,
 587                                bool enable,
 588                                struct drm_display_mode *adjusted_mode);
 589         bool (*infoframe_enabled)(struct drm_encoder *encoder);
 590 };
 591
 592 struct intel_dp_mst_encoder;
 593 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 594
 595 /*
 596  * enum link_m_n_set:
 597  *      When platform provides two set of M_N registers for dp, we can
 598  *      program them and switch between them incase of DRRS.
 599  *      But When only one such register is provided, we have to program the
 600  *      required divider value on that registers itself based on the DRRS state.
 601  *
 602  * M1_N1        : Program dp_m_n on M1_N1 registers
 603  *                        dp_m2_n2 on M2_N2 registers (If supported)
 604  *
 605  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 606  *                        M2_N2 registers are not supported
 607  */
 608
 609 enum link_m_n_set {
 610         /* Sets the m1_n1 and m2_n2 */
 611         M1_N1 = 0,
 612         M2_N2
 613 };
 614
 615 struct intel_dp {
 616         uint32_t output_reg;
 617         uint32_t aux_ch_ctl_reg;
 618         uint32_t DP;
 619         bool has_audio;
 620         enum hdmi_force_audio force_audio;
 621         uint32_t color_range;
 622         bool color_range_auto;
 623         uint8_t link_bw;
 624         uint8_t rate_select;
 625         uint8_t lane_count;
 626         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 627         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 628         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 629         /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
 630         uint8_t num_sink_rates;
 631         int sink_rates[DP_MAX_SUPPORTED_RATES];
 632         struct drm_dp_aux aux;
 633         uint8_t train_set[4];
 634         int panel_power_up_delay;
 635         int panel_power_down_delay;
 636         int panel_power_cycle_delay;
 637         int backlight_on_delay;
 638         int backlight_off_delay;
 639         struct delayed_work panel_vdd_work;
 640         bool want_panel_vdd;
 641         unsigned long last_power_cycle;
 642         unsigned long last_power_on;
 643         unsigned long last_backlight_off;
 644
 645         struct notifier_block edp_notifier;
 646
 647         /*
 648          * Pipe whose power sequencer is currently locked into
 649          * this port. Only relevant on VLV/CHV.
 650          */
 651         enum pipe pps_pipe;
 652         struct edp_power_seq pps_delays;
 653
 654         bool use_tps3;
 655         bool can_mst; /* this port supports mst */
 656         bool is_mst;
 657         int active_mst_links;
 658         /* connector directly attached - won't be use for modeset in mst world */
 659         struct intel_connector *attached_connector;
 660
 661         /* mst connector list */
 662         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
 663         struct drm_dp_mst_topology_mgr mst_mgr;
 664
 665         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
 666         /*
 667          * This function returns the value we have to program the AUX_CTL
 668          * register with to kick off an AUX transaction.
 669          */
 670         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
 671                                      bool has_aux_irq,
 672                                      int send_bytes,
 673                                      uint32_t aux_clock_divider);
 674 };
 675
 676 struct intel_digital_port {
 677         struct intel_encoder base;
 678         enum port port;
 679         u32 saved_port_bits;
 680         struct intel_dp dp;
 681         struct intel_hdmi hdmi;
 682         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
 683 };
 684
 685 struct intel_dp_mst_encoder {
 686         struct intel_encoder base;
 687         enum pipe pipe;
 688         struct intel_digital_port *primary;
 689         void *port; /* store this opaque as its illegal to dereference it */
 690 };
 691
 692 static inline int
 693 vlv_dport_to_channel(struct intel_digital_port *dport)
 694 {
 695         switch (dport->port) {
 696         case PORT_B:
 697         case PORT_D:
 698                 return DPIO_CH0;
 699         case PORT_C:
 700                 return DPIO_CH1;
 701         default:
 702                 BUG();
 703         }
 704 }
 705
 706 static inline int
 707 vlv_pipe_to_channel(enum pipe pipe)
 708 {
 709         switch (pipe) {
 710         case PIPE_A:
 711         case PIPE_C:
 712                 return DPIO_CH0;
 713         case PIPE_B:
 714                 return DPIO_CH1;
 715         default:
 716                 BUG();
 717         }
 718 }
 719
 720 static inline struct drm_crtc *
 721 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
 722 {
 723         struct drm_i915_private *dev_priv = dev->dev_private;
 724         return dev_priv->pipe_to_crtc_mapping[pipe];
 725 }
 726
 727 static inline struct drm_crtc *
 728 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
 729 {
 730         struct drm_i915_private *dev_priv = dev->dev_private;
 731         return dev_priv->plane_to_crtc_mapping[plane];
 732 }
 733
 734 struct intel_unpin_work {
 735         struct work_struct work;
 736         struct drm_crtc *crtc;
 737         struct drm_framebuffer *old_fb;
 738         struct drm_i915_gem_object *pending_flip_obj;
 739         struct drm_pending_vblank_event *event;
 740         atomic_t pending;
 741 #define INTEL_FLIP_INACTIVE     0
 742 #define INTEL_FLIP_PENDING      1
 743 #define INTEL_FLIP_COMPLETE     2
 744         u32 flip_count;
 745         u32 gtt_offset;
 746         struct drm_i915_gem_request *flip_queued_req;
 747         int flip_queued_vblank;
 748         int flip_ready_vblank;
 749         bool enable_stall_check;
 750 };
 751
 752 struct intel_set_config {
 753         struct drm_encoder **save_connector_encoders;
 754         struct drm_crtc **save_encoder_crtcs;
 755         bool *save_crtc_enabled;
 756
 757         bool fb_changed;
 758         bool mode_changed;
 759 };
 760
 761 struct intel_load_detect_pipe {
 762         struct drm_framebuffer *release_fb;
 763         bool load_detect_temp;
 764         int dpms_mode;
 765 };
 766
 767 static inline struct intel_encoder *
 768 intel_attached_encoder(struct drm_connector *connector)
 769 {
 770         return to_intel_connector(connector)->encoder;
 771 }
 772
 773 static inline struct intel_digital_port *
 774 enc_to_dig_port(struct drm_encoder *encoder)
 775 {
 776         return container_of(encoder, struct intel_digital_port, base.base);
 777 }
 778
 779 static inline struct intel_dp_mst_encoder *
 780 enc_to_mst(struct drm_encoder *encoder)
 781 {
 782         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
 783 }
 784
 785 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 786 {
 787         return &enc_to_dig_port(encoder)->dp;
 788 }
 789
 790 static inline struct intel_digital_port *
 791 dp_to_dig_port(struct intel_dp *intel_dp)
 792 {
 793         return container_of(intel_dp, struct intel_digital_port, dp);
 794 }
 795
 796 static inline struct intel_digital_port *
 797 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
 798 {
 799         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
 800 }
 801
 802 /*
 803  * Returns the number of planes for this pipe, ie the number of sprites + 1
 804  * (primary plane). This doesn't count the cursor plane then.
 805  */
 806 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
 807 {
 808         return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
 809 }
 810
 811 /* intel_fifo_underrun.c */
 812 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 813                                            enum pipe pipe, bool enable);
 814 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
 815                                            enum transcoder pch_transcoder,
 816                                            bool enable);
 817 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 818                                          enum pipe pipe);
 819 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 820                                          enum transcoder pch_transcoder);
 821 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
 822
 823 /* i915_irq.c */
 824 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 825 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 826 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 827 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 828 void gen6_reset_rps_interrupts(struct drm_device *dev);
 829 void gen6_enable_rps_interrupts(struct drm_device *dev);
 830 void gen6_disable_rps_interrupts(struct drm_device *dev);
 831 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
 832 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 833 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 834 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 835 {
 836         /*
 837          * We only use drm_irq_uninstall() at unload and VT switch, so
 838          * this is the only thing we need to check.
 839          */
 840         return dev_priv->pm.irqs_enabled;
 841 }
 842
 843 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 844 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 845                                      unsigned int pipe_mask);
 846
 847 /* intel_crt.c */
 848 void intel_crt_init(struct drm_device *dev);
 849
 850
 851 /* intel_ddi.c */
 852 void intel_prepare_ddi(struct drm_device *dev);
 853 void hsw_fdi_link_train(struct drm_crtc *crtc);
 854 void intel_ddi_init(struct drm_device *dev, enum port port);
 855 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
 856 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
 857 void intel_ddi_pll_init(struct drm_device *dev);
 858 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
 859 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 860                                        enum transcoder cpu_transcoder);
 861 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
 862 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
 863 bool intel_ddi_pll_select(struct intel_crtc *crtc,
 864                           struct intel_crtc_state *crtc_state);
 865 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
 866 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
 867 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
 868 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
 869 void intel_ddi_get_config(struct intel_encoder *encoder,
 870                           struct intel_crtc_state *pipe_config);
 871
 872 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
 873 void intel_ddi_clock_get(struct intel_encoder *encoder,
 874                          struct intel_crtc_state *pipe_config);
 875 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 876
 877 /* intel_frontbuffer.c */
 878 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 879                              struct intel_engine_cs *ring,
 880                              enum fb_op_origin origin);
 881 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
 882                                     unsigned frontbuffer_bits);
 883 void intel_frontbuffer_flip_complete(struct drm_device *dev,
 884                                      unsigned frontbuffer_bits);
 885 void intel_frontbuffer_flush(struct drm_device *dev,
 886                              unsigned frontbuffer_bits);
 887 /**
 888  * intel_frontbuffer_flip - synchronous frontbuffer flip
 889  * @dev: DRM device
 890  * @frontbuffer_bits: frontbuffer plane tracking bits
 891  *
 892  * This function gets called after scheduling a flip on @obj. This is for
 893  * synchronous plane updates which will happen on the next vblank and which will
 894  * not get delayed by pending gpu rendering.
 895  *
 896  * Can be called without any locks held.
 897  */
 898 static inline
 899 void intel_frontbuffer_flip(struct drm_device *dev,
 900                             unsigned frontbuffer_bits)
 901 {
 902         intel_frontbuffer_flush(dev, frontbuffer_bits);
 903 }
 904
 905 unsigned int intel_fb_align_height(struct drm_device *dev,
 906                                    unsigned int height,
 907                                    uint32_t pixel_format,
 908                                    uint64_t fb_format_modifier);
 909 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 910
 911 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
 912                               uint32_t pixel_format);
 913
 914 /* intel_audio.c */
 915 void intel_init_audio(struct drm_device *dev);
 916 void intel_audio_codec_enable(struct intel_encoder *encoder);
 917 void intel_audio_codec_disable(struct intel_encoder *encoder);
 918 void i915_audio_component_init(struct drm_i915_private *dev_priv);
 919 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
 920
 921 /* intel_display.c */
 922 extern const struct drm_plane_funcs intel_plane_funcs;
 923 bool intel_has_pending_fb_unpin(struct drm_device *dev);
 924 int intel_pch_rawclk(struct drm_device *dev);
 925 void intel_mark_busy(struct drm_device *dev);
 926 void intel_mark_idle(struct drm_device *dev);
 927 void intel_crtc_restore_mode(struct drm_crtc *crtc);
 928 void intel_crtc_control(struct drm_crtc *crtc, bool enable);
 929 void intel_crtc_update_dpms(struct drm_crtc *crtc);
 930 void intel_encoder_destroy(struct drm_encoder *encoder);
 931 void intel_connector_dpms(struct drm_connector *, int mode);
 932 bool intel_connector_get_hw_state(struct intel_connector *connector);
 933 void intel_modeset_check_state(struct drm_device *dev);
 934 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 935                                 struct intel_digital_port *port);
 936 void intel_connector_attach_encoder(struct intel_connector *connector,
 937                                     struct intel_encoder *encoder);
 938 struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
 939 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
 940                                              struct drm_crtc *crtc);
 941 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
 942 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 943                                 struct drm_file *file_priv);
 944 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 945                                              enum pipe pipe);
 946 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
 947 static inline void
 948 intel_wait_for_vblank(struct drm_device *dev, int pipe)
 949 {
 950         drm_wait_one_vblank(dev, pipe);
 951 }
 952 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
 953 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 954                          struct intel_digital_port *dport);
 955 bool intel_get_load_detect_pipe(struct drm_connector *connector,
 956                                 struct drm_display_mode *mode,
 957                                 struct intel_load_detect_pipe *old,
 958                                 struct drm_modeset_acquire_ctx *ctx);
 959 void intel_release_load_detect_pipe(struct drm_connector *connector,
 960                                     struct intel_load_detect_pipe *old,
 961                                     struct drm_modeset_acquire_ctx *ctx);
 962 int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 963                                struct drm_framebuffer *fb,
 964                                const struct drm_plane_state *plane_state,
 965                                struct intel_engine_cs *pipelined);
 966 struct drm_framebuffer *
 967 __intel_framebuffer_create(struct drm_device *dev,
 968                            struct drm_mode_fb_cmd2 *mode_cmd,
 969                            struct drm_i915_gem_object *obj);
 970 void intel_prepare_page_flip(struct drm_device *dev, int plane);
 971 void intel_finish_page_flip(struct drm_device *dev, int pipe);
 972 void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 973 void intel_check_page_flip(struct drm_device *dev, int pipe);
 974 int intel_prepare_plane_fb(struct drm_plane *plane,
 975                            struct drm_framebuffer *fb,
 976                            const struct drm_plane_state *new_state);
 977 void intel_cleanup_plane_fb(struct drm_plane *plane,
 978                             struct drm_framebuffer *fb,
 979                             const struct drm_plane_state *old_state);
 980 int intel_plane_atomic_get_property(struct drm_plane *plane,
 981                                     const struct drm_plane_state *state,
 982                                     struct drm_property *property,
 983                                     uint64_t *val);
 984 int intel_plane_atomic_set_property(struct drm_plane *plane,
 985                                     struct drm_plane_state *state,
 986                                     struct drm_property *property,
 987                                     uint64_t val);
 988
 989 unsigned int
 990 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
 991                   uint64_t fb_format_modifier);
 992
 993 static inline bool
 994 intel_rotation_90_or_270(unsigned int rotation)
 995 {
 996         return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
 997 }
 998
 999 unsigned int
1000 intel_tile_height(struct drm_device *dev, uint32_t bits_per_pixel,
1001                   uint64_t fb_modifier);
1002 void intel_create_rotation_property(struct drm_device *dev,
1003                                         struct intel_plane *plane);
1004
1005 bool intel_wm_need_update(struct drm_plane *plane,
1006                           struct drm_plane_state *state);
1007
1008 /* shared dpll functions */
1009 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1010 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1011                         struct intel_shared_dpll *pll,
1012                         bool state);
1013 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1014 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
1015 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1016                                                 struct intel_crtc_state *state);
1017 void intel_put_shared_dpll(struct intel_crtc *crtc);
1018
1019 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1020                       const struct dpll *dpll);
1021 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1022
1023 /* modesetting asserts */
1024 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1025                            enum pipe pipe);
1026 void assert_pll(struct drm_i915_private *dev_priv,
1027                 enum pipe pipe, bool state);
1028 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1029 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1030 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1031                        enum pipe pipe, bool state);
1032 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1033 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1034 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1035 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1036 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1037 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1038                                              unsigned int tiling_mode,
1039                                              unsigned int bpp,
1040                                              unsigned int pitch);
1041 void intel_prepare_reset(struct drm_device *dev);
1042 void intel_finish_reset(struct drm_device *dev);
1043 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1044 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1045 void intel_dp_get_m_n(struct intel_crtc *crtc,
1046                       struct intel_crtc_state *pipe_config);
1047 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1048 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1049 void
1050 ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1051                                 int dotclock);
1052 bool intel_crtc_active(struct drm_crtc *crtc);
1053 void hsw_enable_ips(struct intel_crtc *crtc);
1054 void hsw_disable_ips(struct intel_crtc *crtc);
1055 enum intel_display_power_domain
1056 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1057 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1058                                  struct intel_crtc_state *pipe_config);
1059 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1060 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1061
1062 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1063                                      struct drm_i915_gem_object *obj);
1064
1065 /* intel_dp.c */
1066 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1067 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1068                              struct intel_connector *intel_connector);
1069 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1070 void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1071 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1072 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1073 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1074 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1075 bool intel_dp_compute_config(struct intel_encoder *encoder,
1076                              struct intel_crtc_state *pipe_config);
1077 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1078 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1079                                   bool long_hpd);
1080 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1081 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1082 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1083 void intel_edp_panel_on(struct intel_dp *intel_dp);
1084 void intel_edp_panel_off(struct intel_dp *intel_dp);
1085 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1086 void intel_dp_mst_suspend(struct drm_device *dev);
1087 void intel_dp_mst_resume(struct drm_device *dev);
1088 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1089 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1090 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1091 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
1092 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1093 void intel_plane_destroy(struct drm_plane *plane);
1094 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1095 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1096 void intel_edp_drrs_invalidate(struct drm_device *dev,
1097                 unsigned frontbuffer_bits);
1098 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1099
1100 /* intel_dp_mst.c */
1101 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1102 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1103 /* intel_dsi.c */
1104 void intel_dsi_init(struct drm_device *dev);
1105
1106
1107 /* intel_dvo.c */
1108 void intel_dvo_init(struct drm_device *dev);
1109
1110
1111 /* legacy fbdev emulation in intel_fbdev.c */
1112 #ifdef CONFIG_DRM_I915_FBDEV
1113 extern int intel_fbdev_init(struct drm_device *dev);
1114 extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
1115 extern void intel_fbdev_fini(struct drm_device *dev);
1116 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1117 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1118 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1119 #else
1120 static inline int intel_fbdev_init(struct drm_device *dev)
1121 {
1122         return 0;
1123 }
1124
1125 static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
1126 {
1127 }
1128
1129 static inline void intel_fbdev_fini(struct drm_device *dev)
1130 {
1131 }
1132
1133 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1134 {
1135 }
1136
1137 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1138 {
1139 }
1140 #endif
1141
1142 /* intel_fbc.c */
1143 bool intel_fbc_enabled(struct drm_device *dev);
1144 void intel_fbc_update(struct drm_device *dev);
1145 void intel_fbc_init(struct drm_i915_private *dev_priv);
1146 void intel_fbc_disable(struct drm_device *dev);
1147 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1148                           unsigned int frontbuffer_bits,
1149                           enum fb_op_origin origin);
1150 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1151                      unsigned int frontbuffer_bits);
1152
1153 /* intel_hdmi.c */
1154 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1155 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1156                                struct intel_connector *intel_connector);
1157 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1158 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1159                                struct intel_crtc_state *pipe_config);
1160
1161
1162 /* intel_lvds.c */
1163 void intel_lvds_init(struct drm_device *dev);
1164 bool intel_is_dual_link_lvds(struct drm_device *dev);
1165
1166
1167 /* intel_modes.c */
1168 int intel_connector_update_modes(struct drm_connector *connector,
1169                                  struct edid *edid);
1170 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1171 void intel_attach_force_audio_property(struct drm_connector *connector);
1172 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1173
1174
1175 /* intel_overlay.c */
1176 void intel_setup_overlay(struct drm_device *dev);
1177 void intel_cleanup_overlay(struct drm_device *dev);
1178 int intel_overlay_switch_off(struct intel_overlay *overlay);
1179 int intel_overlay_put_image(struct drm_device *dev, void *data,
1180                             struct drm_file *file_priv);
1181 int intel_overlay_attrs(struct drm_device *dev, void *data,
1182                         struct drm_file *file_priv);
1183 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1184
1185
1186 /* intel_panel.c */
1187 int intel_panel_init(struct intel_panel *panel,
1188                      struct drm_display_mode *fixed_mode,
1189                      struct drm_display_mode *downclock_mode);
1190 void intel_panel_fini(struct intel_panel *panel);
1191 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1192                             struct drm_display_mode *adjusted_mode);
1193 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1194                              struct intel_crtc_state *pipe_config,
1195                              int fitting_mode);
1196 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1197                               struct intel_crtc_state *pipe_config,
1198                               int fitting_mode);
1199 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1200                                     u32 level, u32 max);
1201 int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
1202 void intel_panel_enable_backlight(struct intel_connector *connector);
1203 void intel_panel_disable_backlight(struct intel_connector *connector);
1204 void intel_panel_destroy_backlight(struct drm_connector *connector);
1205 void intel_panel_init_backlight_funcs(struct drm_device *dev);
1206 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1207 extern struct drm_display_mode *intel_find_panel_downclock(
1208                                 struct drm_device *dev,
1209                                 struct drm_display_mode *fixed_mode,
1210                                 struct drm_connector *connector);
1211 void intel_backlight_register(struct drm_device *dev);
1212 void intel_backlight_unregister(struct drm_device *dev);
1213
1214
1215 /* intel_psr.c */
1216 void intel_psr_enable(struct intel_dp *intel_dp);
1217 void intel_psr_disable(struct intel_dp *intel_dp);
1218 void intel_psr_invalidate(struct drm_device *dev,
1219                               unsigned frontbuffer_bits);
1220 void intel_psr_flush(struct drm_device *dev,
1221                          unsigned frontbuffer_bits);
1222 void intel_psr_init(struct drm_device *dev);
1223
1224 /* intel_runtime_pm.c */
1225 int intel_power_domains_init(struct drm_i915_private *);
1226 void intel_power_domains_fini(struct drm_i915_private *);
1227 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
1228 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1229
1230 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1231                                     enum intel_display_power_domain domain);
1232 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1233                                       enum intel_display_power_domain domain);
1234 void intel_display_power_get(struct drm_i915_private *dev_priv,
1235                              enum intel_display_power_domain domain);
1236 void intel_display_power_put(struct drm_i915_private *dev_priv,
1237                              enum intel_display_power_domain domain);
1238 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1239 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1240 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1241 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1242 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1243
1244 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1245
1246 /* intel_pm.c */
1247 void intel_init_clock_gating(struct drm_device *dev);
1248 void intel_suspend_hw(struct drm_device *dev);
1249 int ilk_wm_max_level(const struct drm_device *dev);
1250 void intel_update_watermarks(struct drm_crtc *crtc);
1251 void intel_update_sprite_watermarks(struct drm_plane *plane,
1252                                     struct drm_crtc *crtc,
1253                                     uint32_t sprite_width,
1254                                     uint32_t sprite_height,
1255                                     int pixel_size,
1256                                     bool enabled, bool scaled);
1257 void intel_init_pm(struct drm_device *dev);
1258 void intel_pm_setup(struct drm_device *dev);
1259 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1260 void intel_gpu_ips_teardown(void);
1261 void intel_init_gt_powersave(struct drm_device *dev);
1262 void intel_cleanup_gt_powersave(struct drm_device *dev);
1263 void intel_enable_gt_powersave(struct drm_device *dev);
1264 void intel_disable_gt_powersave(struct drm_device *dev);
1265 void intel_suspend_gt_powersave(struct drm_device *dev);
1266 void intel_reset_gt_powersave(struct drm_device *dev);
1267 void gen6_update_ring_freq(struct drm_device *dev);
1268 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1269 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1270 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1271 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1272                     struct drm_i915_file_private *file_priv);
1273 void intel_queue_rps_boost_for_request(struct drm_device *dev,
1274                                        struct drm_i915_gem_request *rq);
1275 void ilk_wm_get_hw_state(struct drm_device *dev);
1276 void skl_wm_get_hw_state(struct drm_device *dev);
1277 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1278                           struct skl_ddb_allocation *ddb /* out */);
1279
1280
1281 /* intel_sdvo.c */
1282 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
1283
1284
1285 /* intel_sprite.c */
1286 int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
1287 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1288                                enum plane plane);
1289 int intel_plane_restore(struct drm_plane *plane);
1290 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1291                               struct drm_file *file_priv);
1292 bool intel_pipe_update_start(struct intel_crtc *crtc,
1293                              uint32_t *start_vbl_count);
1294 void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
1295 void intel_post_enable_primary(struct drm_crtc *crtc);
1296 void intel_pre_disable_primary(struct drm_crtc *crtc);
1297
1298 /* intel_tv.c */
1299 void intel_tv_init(struct drm_device *dev);
1300
1301 /* intel_atomic.c */
1302 int intel_atomic_check(struct drm_device *dev,
1303                        struct drm_atomic_state *state);
1304 int intel_atomic_commit(struct drm_device *dev,
1305                         struct drm_atomic_state *state,
1306                         bool async);
1307 int intel_connector_atomic_get_property(struct drm_connector *connector,
1308                                         const struct drm_connector_state *state,
1309                                         struct drm_property *property,
1310                                         uint64_t *val);
1311 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1312 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1313                                struct drm_crtc_state *state);
1314 static inline struct intel_crtc_state *
1315 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1316                             struct intel_crtc *crtc)
1317 {
1318         struct drm_crtc_state *crtc_state;
1319         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1320         if (IS_ERR(crtc_state))
1321                 return ERR_PTR(PTR_ERR(crtc_state));
1322
1323         return to_intel_crtc_state(crtc_state);
1324 }
1325
1326 /* intel_atomic_plane.c */
1327 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1328 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1329 void intel_plane_destroy_state(struct drm_plane *plane,
1330                                struct drm_plane_state *state);
1331 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1332
1333 #endif /* __INTEL_DRV_H__ */