drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_crtc_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 /* Compliance test status bits  */
  45 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  46 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  47 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  48 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49
  50 struct dp_link_dpll {
  51         int clock;
  52         struct dpll dpll;
  53 };
  54
  55 static const struct dp_link_dpll gen4_dpll[] = {
  56         { 162000,
  57                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  58         { 270000,
  59                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  60 };
  61
  62 static const struct dp_link_dpll pch_dpll[] = {
  63         { 162000,
  64                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  65         { 270000,
  66                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  67 };
  68
  69 static const struct dp_link_dpll vlv_dpll[] = {
  70         { 162000,
  71                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  72         { 270000,
  73                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  74 };
  75
  76 /*
  77  * CHV supports eDP 1.4 that have  more link rates.
  78  * Below only provides the fixed rate but exclude variable rate.
  79  */
  80 static const struct dp_link_dpll chv_dpll[] = {
  81         /*
  82          * CHV requires to program fractional division for m2.
  83          * m2 is stored in fixed point format using formula below
  84          * (m2_int << 22) | m2_fraction
  85          */
  86         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  87                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  88         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  89                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  90         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  92 };
  93
  94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  95                                   324000, 432000, 540000 };
  96 static const int skl_rates[] = { 162000, 216000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int default_rates[] = { 162000, 270000, 540000 };
  99
 100 /**
 101  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 102  * @intel_dp: DP struct
 103  *
 104  * If a CPU or PCH DP output is attached to an eDP panel, this function
 105  * will return true, and false otherwise.
 106  */
 107 static bool is_edp(struct intel_dp *intel_dp)
 108 {
 109         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 110
 111         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 112 }
 113
 114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 115 {
 116         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 117
 118         return intel_dig_port->base.base.dev;
 119 }
 120
 121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 122 {
 123         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 124 }
 125
 126 static void intel_dp_link_down(struct intel_dp *intel_dp);
 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 130 static void vlv_steal_power_sequencer(struct drm_device *dev,
 131                                       enum pipe pipe);
 132 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 133
 134 static unsigned int intel_dp_unused_lane_mask(int lane_count)
 135 {
 136         return ~((1 << lane_count) - 1) & 0xf;
 137 }
 138
 139 static int
 140 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 141 {
 142         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 143
 144         switch (max_link_bw) {
 145         case DP_LINK_BW_1_62:
 146         case DP_LINK_BW_2_7:
 147         case DP_LINK_BW_5_4:
 148                 break;
 149         default:
 150                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 151                      max_link_bw);
 152                 max_link_bw = DP_LINK_BW_1_62;
 153                 break;
 154         }
 155         return max_link_bw;
 156 }
 157
 158 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 159 {
 160         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 161         u8 source_max, sink_max;
 162
 163         source_max = intel_dig_port->max_lanes;
 164         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 165
 166         return min(source_max, sink_max);
 167 }
 168
 169 /*
 170  * The units on the numbers in the next two are... bizarre.  Examples will
 171  * make it clearer; this one parallels an example in the eDP spec.
 172  *
 173  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 174  *
 175  *     270000 * 1 * 8 / 10 == 216000
 176  *
 177  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 178  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 179  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 180  * 119000.  At 18bpp that's 2142000 kilobits per second.
 181  *
 182  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 183  * get the result in decakilobits instead of kilobits.
 184  */
 185
 186 static int
 187 intel_dp_link_required(int pixel_clock, int bpp)
 188 {
 189         return (pixel_clock * bpp + 9) / 10;
 190 }
 191
 192 static int
 193 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 194 {
 195         return (max_link_clock * max_lanes * 8) / 10;
 196 }
 197
 198 static enum drm_mode_status
 199 intel_dp_mode_valid(struct drm_connector *connector,
 200                     struct drm_display_mode *mode)
 201 {
 202         struct intel_dp *intel_dp = intel_attached_dp(connector);
 203         struct intel_connector *intel_connector = to_intel_connector(connector);
 204         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 205         int target_clock = mode->clock;
 206         int max_rate, mode_rate, max_lanes, max_link_clock;
 207         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 208
 209         if (is_edp(intel_dp) && fixed_mode) {
 210                 if (mode->hdisplay > fixed_mode->hdisplay)
 211                         return MODE_PANEL;
 212
 213                 if (mode->vdisplay > fixed_mode->vdisplay)
 214                         return MODE_PANEL;
 215
 216                 target_clock = fixed_mode->clock;
 217         }
 218
 219         max_link_clock = intel_dp_max_link_rate(intel_dp);
 220         max_lanes = intel_dp_max_lane_count(intel_dp);
 221
 222         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 223         mode_rate = intel_dp_link_required(target_clock, 18);
 224
 225         if (mode_rate > max_rate || target_clock > max_dotclk)
 226                 return MODE_CLOCK_HIGH;
 227
 228         if (mode->clock < 10000)
 229                 return MODE_CLOCK_LOW;
 230
 231         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 232                 return MODE_H_ILLEGAL;
 233
 234         return MODE_OK;
 235 }
 236
 237 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 238 {
 239         int     i;
 240         uint32_t v = 0;
 241
 242         if (src_bytes > 4)
 243                 src_bytes = 4;
 244         for (i = 0; i < src_bytes; i++)
 245                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 246         return v;
 247 }
 248
 249 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 250 {
 251         int i;
 252         if (dst_bytes > 4)
 253                 dst_bytes = 4;
 254         for (i = 0; i < dst_bytes; i++)
 255                 dst[i] = src >> ((3-i) * 8);
 256 }
 257
 258 static void
 259 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 260                                     struct intel_dp *intel_dp);
 261 static void
 262 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 263                                               struct intel_dp *intel_dp);
 264
 265 static void pps_lock(struct intel_dp *intel_dp)
 266 {
 267         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 268         struct intel_encoder *encoder = &intel_dig_port->base;
 269         struct drm_device *dev = encoder->base.dev;
 270         struct drm_i915_private *dev_priv = dev->dev_private;
 271         enum intel_display_power_domain power_domain;
 272
 273         /*
 274          * See vlv_power_sequencer_reset() why we need
 275          * a power domain reference here.
 276          */
 277         power_domain = intel_display_port_aux_power_domain(encoder);
 278         intel_display_power_get(dev_priv, power_domain);
 279
 280         mutex_lock(&dev_priv->pps_mutex);
 281 }
 282
 283 static void pps_unlock(struct intel_dp *intel_dp)
 284 {
 285         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 286         struct intel_encoder *encoder = &intel_dig_port->base;
 287         struct drm_device *dev = encoder->base.dev;
 288         struct drm_i915_private *dev_priv = dev->dev_private;
 289         enum intel_display_power_domain power_domain;
 290
 291         mutex_unlock(&dev_priv->pps_mutex);
 292
 293         power_domain = intel_display_port_aux_power_domain(encoder);
 294         intel_display_power_put(dev_priv, power_domain);
 295 }
 296
 297 static void
 298 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 299 {
 300         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 301         struct drm_device *dev = intel_dig_port->base.base.dev;
 302         struct drm_i915_private *dev_priv = dev->dev_private;
 303         enum pipe pipe = intel_dp->pps_pipe;
 304         bool pll_enabled, release_cl_override = false;
 305         enum dpio_phy phy = DPIO_PHY(pipe);
 306         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 307         uint32_t DP;
 308
 309         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 310                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 311                  pipe_name(pipe), port_name(intel_dig_port->port)))
 312                 return;
 313
 314         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 315                       pipe_name(pipe), port_name(intel_dig_port->port));
 316
 317         /* Preserve the BIOS-computed detected bit. This is
 318          * supposed to be read-only.
 319          */
 320         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 321         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 322         DP |= DP_PORT_WIDTH(1);
 323         DP |= DP_LINK_TRAIN_PAT_1;
 324
 325         if (IS_CHERRYVIEW(dev))
 326                 DP |= DP_PIPE_SELECT_CHV(pipe);
 327         else if (pipe == PIPE_B)
 328                 DP |= DP_PIPEB_SELECT;
 329
 330         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 331
 332         /*
 333          * The DPLL for the pipe must be enabled for this to work.
 334          * So enable temporarily it if it's not already enabled.
 335          */
 336         if (!pll_enabled) {
 337                 release_cl_override = IS_CHERRYVIEW(dev) &&
 338                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 339
 340                 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 341                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 342                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 343                                   pipe_name(pipe));
 344                         return;
 345                 }
 346         }
 347
 348         /*
 349          * Similar magic as in intel_dp_enable_port().
 350          * We _must_ do this port enable + disable trick
 351          * to make this power seqeuencer lock onto the port.
 352          * Otherwise even VDD force bit won't work.
 353          */
 354         I915_WRITE(intel_dp->output_reg, DP);
 355         POSTING_READ(intel_dp->output_reg);
 356
 357         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 358         POSTING_READ(intel_dp->output_reg);
 359
 360         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 361         POSTING_READ(intel_dp->output_reg);
 362
 363         if (!pll_enabled) {
 364                 vlv_force_pll_off(dev, pipe);
 365
 366                 if (release_cl_override)
 367                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 368         }
 369 }
 370
 371 static enum pipe
 372 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 373 {
 374         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 375         struct drm_device *dev = intel_dig_port->base.base.dev;
 376         struct drm_i915_private *dev_priv = dev->dev_private;
 377         struct intel_encoder *encoder;
 378         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 379         enum pipe pipe;
 380
 381         lockdep_assert_held(&dev_priv->pps_mutex);
 382
 383         /* We should never land here with regular DP ports */
 384         WARN_ON(!is_edp(intel_dp));
 385
 386         if (intel_dp->pps_pipe != INVALID_PIPE)
 387                 return intel_dp->pps_pipe;
 388
 389         /*
 390          * We don't have power sequencer currently.
 391          * Pick one that's not used by other ports.
 392          */
 393         for_each_intel_encoder(dev, encoder) {
 394                 struct intel_dp *tmp;
 395
 396                 if (encoder->type != INTEL_OUTPUT_EDP)
 397                         continue;
 398
 399                 tmp = enc_to_intel_dp(&encoder->base);
 400
 401                 if (tmp->pps_pipe != INVALID_PIPE)
 402                         pipes &= ~(1 << tmp->pps_pipe);
 403         }
 404
 405         /*
 406          * Didn't find one. This should not happen since there
 407          * are two power sequencers and up to two eDP ports.
 408          */
 409         if (WARN_ON(pipes == 0))
 410                 pipe = PIPE_A;
 411         else
 412                 pipe = ffs(pipes) - 1;
 413
 414         vlv_steal_power_sequencer(dev, pipe);
 415         intel_dp->pps_pipe = pipe;
 416
 417         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 418                       pipe_name(intel_dp->pps_pipe),
 419                       port_name(intel_dig_port->port));
 420
 421         /* init power sequencer on this pipe and port */
 422         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 423         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 424
 425         /*
 426          * Even vdd force doesn't work until we've made
 427          * the power sequencer lock in on the port.
 428          */
 429         vlv_power_sequencer_kick(intel_dp);
 430
 431         return intel_dp->pps_pipe;
 432 }
 433
 434 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 435                                enum pipe pipe);
 436
 437 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 438                                enum pipe pipe)
 439 {
 440         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 441 }
 442
 443 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 444                                 enum pipe pipe)
 445 {
 446         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 447 }
 448
 449 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 450                          enum pipe pipe)
 451 {
 452         return true;
 453 }
 454
 455 static enum pipe
 456 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 457                      enum port port,
 458                      vlv_pipe_check pipe_check)
 459 {
 460         enum pipe pipe;
 461
 462         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 463                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 464                         PANEL_PORT_SELECT_MASK;
 465
 466                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 467                         continue;
 468
 469                 if (!pipe_check(dev_priv, pipe))
 470                         continue;
 471
 472                 return pipe;
 473         }
 474
 475         return INVALID_PIPE;
 476 }
 477
 478 static void
 479 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 480 {
 481         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 482         struct drm_device *dev = intel_dig_port->base.base.dev;
 483         struct drm_i915_private *dev_priv = dev->dev_private;
 484         enum port port = intel_dig_port->port;
 485
 486         lockdep_assert_held(&dev_priv->pps_mutex);
 487
 488         /* try to find a pipe with this port selected */
 489         /* first pick one where the panel is on */
 490         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 491                                                   vlv_pipe_has_pp_on);
 492         /* didn't find one? pick one where vdd is on */
 493         if (intel_dp->pps_pipe == INVALID_PIPE)
 494                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 495                                                           vlv_pipe_has_vdd_on);
 496         /* didn't find one? pick one with just the correct port */
 497         if (intel_dp->pps_pipe == INVALID_PIPE)
 498                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 499                                                           vlv_pipe_any);
 500
 501         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 502         if (intel_dp->pps_pipe == INVALID_PIPE) {
 503                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 504                               port_name(port));
 505                 return;
 506         }
 507
 508         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 509                       port_name(port), pipe_name(intel_dp->pps_pipe));
 510
 511         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 512         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 513 }
 514
 515 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 516 {
 517         struct drm_device *dev = dev_priv->dev;
 518         struct intel_encoder *encoder;
 519
 520         if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)))
 521                 return;
 522
 523         /*
 524          * We can't grab pps_mutex here due to deadlock with power_domain
 525          * mutex when power_domain functions are called while holding pps_mutex.
 526          * That also means that in order to use pps_pipe the code needs to
 527          * hold both a power domain reference and pps_mutex, and the power domain
 528          * reference get/put must be done while _not_ holding pps_mutex.
 529          * pps_{lock,unlock}() do these steps in the correct order, so one
 530          * should use them always.
 531          */
 532
 533         for_each_intel_encoder(dev, encoder) {
 534                 struct intel_dp *intel_dp;
 535
 536                 if (encoder->type != INTEL_OUTPUT_EDP)
 537                         continue;
 538
 539                 intel_dp = enc_to_intel_dp(&encoder->base);
 540                 intel_dp->pps_pipe = INVALID_PIPE;
 541         }
 542 }
 543
 544 static i915_reg_t
 545 _pp_ctrl_reg(struct intel_dp *intel_dp)
 546 {
 547         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 548
 549         if (IS_BROXTON(dev))
 550                 return BXT_PP_CONTROL(0);
 551         else if (HAS_PCH_SPLIT(dev))
 552                 return PCH_PP_CONTROL;
 553         else
 554                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 555 }
 556
 557 static i915_reg_t
 558 _pp_stat_reg(struct intel_dp *intel_dp)
 559 {
 560         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 561
 562         if (IS_BROXTON(dev))
 563                 return BXT_PP_STATUS(0);
 564         else if (HAS_PCH_SPLIT(dev))
 565                 return PCH_PP_STATUS;
 566         else
 567                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 568 }
 569
 570 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 571    This function only applicable when panel PM state is not to be tracked */
 572 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 573                               void *unused)
 574 {
 575         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 576                                                  edp_notifier);
 577         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 578         struct drm_i915_private *dev_priv = dev->dev_private;
 579
 580         if (!is_edp(intel_dp) || code != SYS_RESTART)
 581                 return 0;
 582
 583         pps_lock(intel_dp);
 584
 585         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 586                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 587                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 588                 u32 pp_div;
 589
 590                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 591                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 592                 pp_div = I915_READ(pp_div_reg);
 593                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 594
 595                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 596                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 597                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 598                 msleep(intel_dp->panel_power_cycle_delay);
 599         }
 600
 601         pps_unlock(intel_dp);
 602
 603         return 0;
 604 }
 605
 606 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 607 {
 608         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 609         struct drm_i915_private *dev_priv = dev->dev_private;
 610
 611         lockdep_assert_held(&dev_priv->pps_mutex);
 612
 613         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 614             intel_dp->pps_pipe == INVALID_PIPE)
 615                 return false;
 616
 617         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 618 }
 619
 620 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 621 {
 622         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 623         struct drm_i915_private *dev_priv = dev->dev_private;
 624
 625         lockdep_assert_held(&dev_priv->pps_mutex);
 626
 627         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 628             intel_dp->pps_pipe == INVALID_PIPE)
 629                 return false;
 630
 631         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 632 }
 633
 634 static void
 635 intel_dp_check_edp(struct intel_dp *intel_dp)
 636 {
 637         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 638         struct drm_i915_private *dev_priv = dev->dev_private;
 639
 640         if (!is_edp(intel_dp))
 641                 return;
 642
 643         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 644                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 645                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 646                               I915_READ(_pp_stat_reg(intel_dp)),
 647                               I915_READ(_pp_ctrl_reg(intel_dp)));
 648         }
 649 }
 650
 651 static uint32_t
 652 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 653 {
 654         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 655         struct drm_device *dev = intel_dig_port->base.base.dev;
 656         struct drm_i915_private *dev_priv = dev->dev_private;
 657         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 658         uint32_t status;
 659         bool done;
 660
 661 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 662         if (has_aux_irq)
 663                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 664                                           msecs_to_jiffies_timeout(10));
 665         else
 666                 done = wait_for_atomic(C, 10) == 0;
 667         if (!done)
 668                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 669                           has_aux_irq);
 670 #undef C
 671
 672         return status;
 673 }
 674
 675 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 676 {
 677         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 678         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 679
 680         if (index)
 681                 return 0;
 682
 683         /*
 684          * The clock divider is based off the hrawclk, and would like to run at
 685          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 686          */
 687         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 688 }
 689
 690 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 691 {
 692         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 693         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 694
 695         if (index)
 696                 return 0;
 697
 698         /*
 699          * The clock divider is based off the cdclk or PCH rawclk, and would
 700          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 701          * divide by 2000 and use that
 702          */
 703         if (intel_dig_port->port == PORT_A)
 704                 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 705         else
 706                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 707 }
 708
 709 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 710 {
 711         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 712         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 713
 714         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 715                 /* Workaround for non-ULT HSW */
 716                 switch (index) {
 717                 case 0: return 63;
 718                 case 1: return 72;
 719                 default: return 0;
 720                 }
 721         }
 722
 723         return ilk_get_aux_clock_divider(intel_dp, index);
 724 }
 725
 726 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 727 {
 728         /*
 729          * SKL doesn't need us to program the AUX clock divider (Hardware will
 730          * derive the clock from CDCLK automatically). We still implement the
 731          * get_aux_clock_divider vfunc to plug-in into the existing code.
 732          */
 733         return index ? 0 : 1;
 734 }
 735
 736 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
 737                                      bool has_aux_irq,
 738                                      int send_bytes,
 739                                      uint32_t aux_clock_divider)
 740 {
 741         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 742         struct drm_device *dev = intel_dig_port->base.base.dev;
 743         uint32_t precharge, timeout;
 744
 745         if (IS_GEN6(dev))
 746                 precharge = 3;
 747         else
 748                 precharge = 5;
 749
 750         if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
 751                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 752         else
 753                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 754
 755         return DP_AUX_CH_CTL_SEND_BUSY |
 756                DP_AUX_CH_CTL_DONE |
 757                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 758                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 759                timeout |
 760                DP_AUX_CH_CTL_RECEIVE_ERROR |
 761                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 762                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 763                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 764 }
 765
 766 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 767                                       bool has_aux_irq,
 768                                       int send_bytes,
 769                                       uint32_t unused)
 770 {
 771         return DP_AUX_CH_CTL_SEND_BUSY |
 772                DP_AUX_CH_CTL_DONE |
 773                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 774                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 775                DP_AUX_CH_CTL_TIME_OUT_1600us |
 776                DP_AUX_CH_CTL_RECEIVE_ERROR |
 777                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 778                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 779 }
 780
 781 static int
 782 intel_dp_aux_ch(struct intel_dp *intel_dp,
 783                 const uint8_t *send, int send_bytes,
 784                 uint8_t *recv, int recv_size)
 785 {
 786         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 787         struct drm_device *dev = intel_dig_port->base.base.dev;
 788         struct drm_i915_private *dev_priv = dev->dev_private;
 789         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 790         uint32_t aux_clock_divider;
 791         int i, ret, recv_bytes;
 792         uint32_t status;
 793         int try, clock = 0;
 794         bool has_aux_irq = HAS_AUX_IRQ(dev);
 795         bool vdd;
 796
 797         pps_lock(intel_dp);
 798
 799         /*
 800          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 801          * In such cases we want to leave VDD enabled and it's up to upper layers
 802          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 803          * ourselves.
 804          */
 805         vdd = edp_panel_vdd_on(intel_dp);
 806
 807         /* dp aux is extremely sensitive to irq latency, hence request the
 808          * lowest possible wakeup latency and so prevent the cpu from going into
 809          * deep sleep states.
 810          */
 811         pm_qos_update_request(&dev_priv->pm_qos, 0);
 812
 813         intel_dp_check_edp(intel_dp);
 814
 815         /* Try to wait for any previous AUX channel activity */
 816         for (try = 0; try < 3; try++) {
 817                 status = I915_READ_NOTRACE(ch_ctl);
 818                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 819                         break;
 820                 msleep(1);
 821         }
 822
 823         if (try == 3) {
 824                 static u32 last_status = -1;
 825                 const u32 status = I915_READ(ch_ctl);
 826
 827                 if (status != last_status) {
 828                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
 829                              status);
 830                         last_status = status;
 831                 }
 832
 833                 ret = -EBUSY;
 834                 goto out;
 835         }
 836
 837         /* Only 5 data registers! */
 838         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 839                 ret = -E2BIG;
 840                 goto out;
 841         }
 842
 843         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 844                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 845                                                           has_aux_irq,
 846                                                           send_bytes,
 847                                                           aux_clock_divider);
 848
 849                 /* Must try at least 3 times according to DP spec */
 850                 for (try = 0; try < 5; try++) {
 851                         /* Load the send data into the aux channel data registers */
 852                         for (i = 0; i < send_bytes; i += 4)
 853                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
 854                                            intel_dp_pack_aux(send + i,
 855                                                              send_bytes - i));
 856
 857                         /* Send the command and wait for it to complete */
 858                         I915_WRITE(ch_ctl, send_ctl);
 859
 860                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 861
 862                         /* Clear done status and any errors */
 863                         I915_WRITE(ch_ctl,
 864                                    status |
 865                                    DP_AUX_CH_CTL_DONE |
 866                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 867                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 868
 869                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
 870                                 continue;
 871
 872                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
 873                          *   400us delay required for errors and timeouts
 874                          *   Timeout errors from the HW already meet this
 875                          *   requirement so skip to next iteration
 876                          */
 877                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 878                                 usleep_range(400, 500);
 879                                 continue;
 880                         }
 881                         if (status & DP_AUX_CH_CTL_DONE)
 882                                 goto done;
 883                 }
 884         }
 885
 886         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 887                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 888                 ret = -EBUSY;
 889                 goto out;
 890         }
 891
 892 done:
 893         /* Check for timeout or receive error.
 894          * Timeouts occur when the sink is not connected
 895          */
 896         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 897                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 898                 ret = -EIO;
 899                 goto out;
 900         }
 901
 902         /* Timeouts occur when the device isn't connected, so they're
 903          * "normal" -- don't fill the kernel log with these */
 904         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 905                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 906                 ret = -ETIMEDOUT;
 907                 goto out;
 908         }
 909
 910         /* Unload any bytes sent back from the other side */
 911         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 912                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 913
 914         /*
 915          * By BSpec: "Message sizes of 0 or >20 are not allowed."
 916          * We have no idea of what happened so we return -EBUSY so
 917          * drm layer takes care for the necessary retries.
 918          */
 919         if (recv_bytes == 0 || recv_bytes > 20) {
 920                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
 921                               recv_bytes);
 922                 /*
 923                  * FIXME: This patch was created on top of a series that
 924                  * organize the retries at drm level. There EBUSY should
 925                  * also take care for 1ms wait before retrying.
 926                  * That aux retries re-org is still needed and after that is
 927                  * merged we remove this sleep from here.
 928                  */
 929                 usleep_range(1000, 1500);
 930                 ret = -EBUSY;
 931                 goto out;
 932         }
 933
 934         if (recv_bytes > recv_size)
 935                 recv_bytes = recv_size;
 936
 937         for (i = 0; i < recv_bytes; i += 4)
 938                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
 939                                     recv + i, recv_bytes - i);
 940
 941         ret = recv_bytes;
 942 out:
 943         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 944
 945         if (vdd)
 946                 edp_panel_vdd_off(intel_dp, false);
 947
 948         pps_unlock(intel_dp);
 949
 950         return ret;
 951 }
 952
 953 #define BARE_ADDRESS_SIZE       3
 954 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 955 static ssize_t
 956 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 957 {
 958         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 959         uint8_t txbuf[20], rxbuf[20];
 960         size_t txsize, rxsize;
 961         int ret;
 962
 963         txbuf[0] = (msg->request << 4) |
 964                 ((msg->address >> 16) & 0xf);
 965         txbuf[1] = (msg->address >> 8) & 0xff;
 966         txbuf[2] = msg->address & 0xff;
 967         txbuf[3] = msg->size - 1;
 968
 969         switch (msg->request & ~DP_AUX_I2C_MOT) {
 970         case DP_AUX_NATIVE_WRITE:
 971         case DP_AUX_I2C_WRITE:
 972         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
 973                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 974                 rxsize = 2; /* 0 or 1 data bytes */
 975
 976                 if (WARN_ON(txsize > 20))
 977                         return -E2BIG;
 978
 979                 if (msg->buffer)
 980                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 981                 else
 982                         WARN_ON(msg->size);
 983
 984                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 985                 if (ret > 0) {
 986                         msg->reply = rxbuf[0] >> 4;
 987
 988                         if (ret > 1) {
 989                                 /* Number of bytes written in a short write. */
 990                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
 991                         } else {
 992                                 /* Return payload size. */
 993                                 ret = msg->size;
 994                         }
 995                 }
 996                 break;
 997
 998         case DP_AUX_NATIVE_READ:
 999         case DP_AUX_I2C_READ:
1000                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1001                 rxsize = msg->size + 1;
1002
1003                 if (WARN_ON(rxsize > 20))
1004                         return -E2BIG;
1005
1006                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1007                 if (ret > 0) {
1008                         msg->reply = rxbuf[0] >> 4;
1009                         /*
1010                          * Assume happy day, and copy the data. The caller is
1011                          * expected to check msg->reply before touching it.
1012                          *
1013                          * Return payload size.
1014                          */
1015                         ret--;
1016                         memcpy(msg->buffer, rxbuf + 1, ret);
1017                 }
1018                 break;
1019
1020         default:
1021                 ret = -EINVAL;
1022                 break;
1023         }
1024
1025         return ret;
1026 }
1027
1028 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1029                                        enum port port)
1030 {
1031         switch (port) {
1032         case PORT_B:
1033         case PORT_C:
1034         case PORT_D:
1035                 return DP_AUX_CH_CTL(port);
1036         default:
1037                 MISSING_CASE(port);
1038                 return DP_AUX_CH_CTL(PORT_B);
1039         }
1040 }
1041
1042 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1043                                         enum port port, int index)
1044 {
1045         switch (port) {
1046         case PORT_B:
1047         case PORT_C:
1048         case PORT_D:
1049                 return DP_AUX_CH_DATA(port, index);
1050         default:
1051                 MISSING_CASE(port);
1052                 return DP_AUX_CH_DATA(PORT_B, index);
1053         }
1054 }
1055
1056 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1057                                        enum port port)
1058 {
1059         switch (port) {
1060         case PORT_A:
1061                 return DP_AUX_CH_CTL(port);
1062         case PORT_B:
1063         case PORT_C:
1064         case PORT_D:
1065                 return PCH_DP_AUX_CH_CTL(port);
1066         default:
1067                 MISSING_CASE(port);
1068                 return DP_AUX_CH_CTL(PORT_A);
1069         }
1070 }
1071
1072 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1073                                         enum port port, int index)
1074 {
1075         switch (port) {
1076         case PORT_A:
1077                 return DP_AUX_CH_DATA(port, index);
1078         case PORT_B:
1079         case PORT_C:
1080         case PORT_D:
1081                 return PCH_DP_AUX_CH_DATA(port, index);
1082         default:
1083                 MISSING_CASE(port);
1084                 return DP_AUX_CH_DATA(PORT_A, index);
1085         }
1086 }
1087
1088 /*
1089  * On SKL we don't have Aux for port E so we rely
1090  * on VBT to set a proper alternate aux channel.
1091  */
1092 static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1093 {
1094         const struct ddi_vbt_port_info *info =
1095                 &dev_priv->vbt.ddi_port_info[PORT_E];
1096
1097         switch (info->alternate_aux_channel) {
1098         case DP_AUX_A:
1099                 return PORT_A;
1100         case DP_AUX_B:
1101                 return PORT_B;
1102         case DP_AUX_C:
1103                 return PORT_C;
1104         case DP_AUX_D:
1105                 return PORT_D;
1106         default:
1107                 MISSING_CASE(info->alternate_aux_channel);
1108                 return PORT_A;
1109         }
1110 }
1111
1112 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1113                                        enum port port)
1114 {
1115         if (port == PORT_E)
1116                 port = skl_porte_aux_port(dev_priv);
1117
1118         switch (port) {
1119         case PORT_A:
1120         case PORT_B:
1121         case PORT_C:
1122         case PORT_D:
1123                 return DP_AUX_CH_CTL(port);
1124         default:
1125                 MISSING_CASE(port);
1126                 return DP_AUX_CH_CTL(PORT_A);
1127         }
1128 }
1129
1130 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1131                                         enum port port, int index)
1132 {
1133         if (port == PORT_E)
1134                 port = skl_porte_aux_port(dev_priv);
1135
1136         switch (port) {
1137         case PORT_A:
1138         case PORT_B:
1139         case PORT_C:
1140         case PORT_D:
1141                 return DP_AUX_CH_DATA(port, index);
1142         default:
1143                 MISSING_CASE(port);
1144                 return DP_AUX_CH_DATA(PORT_A, index);
1145         }
1146 }
1147
1148 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1149                                          enum port port)
1150 {
1151         if (INTEL_INFO(dev_priv)->gen >= 9)
1152                 return skl_aux_ctl_reg(dev_priv, port);
1153         else if (HAS_PCH_SPLIT(dev_priv))
1154                 return ilk_aux_ctl_reg(dev_priv, port);
1155         else
1156                 return g4x_aux_ctl_reg(dev_priv, port);
1157 }
1158
1159 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1160                                           enum port port, int index)
1161 {
1162         if (INTEL_INFO(dev_priv)->gen >= 9)
1163                 return skl_aux_data_reg(dev_priv, port, index);
1164         else if (HAS_PCH_SPLIT(dev_priv))
1165                 return ilk_aux_data_reg(dev_priv, port, index);
1166         else
1167                 return g4x_aux_data_reg(dev_priv, port, index);
1168 }
1169
1170 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1171 {
1172         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1173         enum port port = dp_to_dig_port(intel_dp)->port;
1174         int i;
1175
1176         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1177         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1178                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1179 }
1180
1181 static void
1182 intel_dp_aux_fini(struct intel_dp *intel_dp)
1183 {
1184         drm_dp_aux_unregister(&intel_dp->aux);
1185         kfree(intel_dp->aux.name);
1186 }
1187
1188 static int
1189 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1190 {
1191         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1192         enum port port = intel_dig_port->port;
1193         int ret;
1194
1195         intel_aux_reg_init(intel_dp);
1196
1197         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1198         if (!intel_dp->aux.name)
1199                 return -ENOMEM;
1200
1201         intel_dp->aux.dev = connector->base.kdev;
1202         intel_dp->aux.transfer = intel_dp_aux_transfer;
1203
1204         DRM_DEBUG_KMS("registering %s bus for %s\n",
1205                       intel_dp->aux.name,
1206                       connector->base.kdev->kobj.name);
1207
1208         ret = drm_dp_aux_register(&intel_dp->aux);
1209         if (ret < 0) {
1210                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1211                           intel_dp->aux.name, ret);
1212                 kfree(intel_dp->aux.name);
1213                 return ret;
1214         }
1215
1216         return 0;
1217 }
1218
1219 static void
1220 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1221 {
1222         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1223
1224         intel_dp_aux_fini(intel_dp);
1225         intel_connector_unregister(intel_connector);
1226 }
1227
1228 static int
1229 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1230 {
1231         if (intel_dp->num_sink_rates) {
1232                 *sink_rates = intel_dp->sink_rates;
1233                 return intel_dp->num_sink_rates;
1234         }
1235
1236         *sink_rates = default_rates;
1237
1238         return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1239 }
1240
1241 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1242 {
1243         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1244         struct drm_device *dev = dig_port->base.base.dev;
1245
1246         /* WaDisableHBR2:skl */
1247         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
1248                 return false;
1249
1250         if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1251             (INTEL_INFO(dev)->gen >= 9))
1252                 return true;
1253         else
1254                 return false;
1255 }
1256
1257 static int
1258 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
1259 {
1260         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1261         struct drm_device *dev = dig_port->base.base.dev;
1262         int size;
1263
1264         if (IS_BROXTON(dev)) {
1265                 *source_rates = bxt_rates;
1266                 size = ARRAY_SIZE(bxt_rates);
1267         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1268                 *source_rates = skl_rates;
1269                 size = ARRAY_SIZE(skl_rates);
1270         } else {
1271                 *source_rates = default_rates;
1272                 size = ARRAY_SIZE(default_rates);
1273         }
1274
1275         /* This depends on the fact that 5.4 is last value in the array */
1276         if (!intel_dp_source_supports_hbr2(intel_dp))
1277                 size--;
1278
1279         return size;
1280 }
1281
1282 static void
1283 intel_dp_set_clock(struct intel_encoder *encoder,
1284                    struct intel_crtc_state *pipe_config)
1285 {
1286         struct drm_device *dev = encoder->base.dev;
1287         const struct dp_link_dpll *divisor = NULL;
1288         int i, count = 0;
1289
1290         if (IS_G4X(dev)) {
1291                 divisor = gen4_dpll;
1292                 count = ARRAY_SIZE(gen4_dpll);
1293         } else if (HAS_PCH_SPLIT(dev)) {
1294                 divisor = pch_dpll;
1295                 count = ARRAY_SIZE(pch_dpll);
1296         } else if (IS_CHERRYVIEW(dev)) {
1297                 divisor = chv_dpll;
1298                 count = ARRAY_SIZE(chv_dpll);
1299         } else if (IS_VALLEYVIEW(dev)) {
1300                 divisor = vlv_dpll;
1301                 count = ARRAY_SIZE(vlv_dpll);
1302         }
1303
1304         if (divisor && count) {
1305                 for (i = 0; i < count; i++) {
1306                         if (pipe_config->port_clock == divisor[i].clock) {
1307                                 pipe_config->dpll = divisor[i].dpll;
1308                                 pipe_config->clock_set = true;
1309                                 break;
1310                         }
1311                 }
1312         }
1313 }
1314
1315 static int intersect_rates(const int *source_rates, int source_len,
1316                            const int *sink_rates, int sink_len,
1317                            int *common_rates)
1318 {
1319         int i = 0, j = 0, k = 0;
1320
1321         while (i < source_len && j < sink_len) {
1322                 if (source_rates[i] == sink_rates[j]) {
1323                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1324                                 return k;
1325                         common_rates[k] = source_rates[i];
1326                         ++k;
1327                         ++i;
1328                         ++j;
1329                 } else if (source_rates[i] < sink_rates[j]) {
1330                         ++i;
1331                 } else {
1332                         ++j;
1333                 }
1334         }
1335         return k;
1336 }
1337
1338 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1339                                  int *common_rates)
1340 {
1341         const int *source_rates, *sink_rates;
1342         int source_len, sink_len;
1343
1344         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1345         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1346
1347         return intersect_rates(source_rates, source_len,
1348                                sink_rates, sink_len,
1349                                common_rates);
1350 }
1351
1352 static void snprintf_int_array(char *str, size_t len,
1353                                const int *array, int nelem)
1354 {
1355         int i;
1356
1357         str[0] = '\0';
1358
1359         for (i = 0; i < nelem; i++) {
1360                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1361                 if (r >= len)
1362                         return;
1363                 str += r;
1364                 len -= r;
1365         }
1366 }
1367
1368 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1369 {
1370         const int *source_rates, *sink_rates;
1371         int source_len, sink_len, common_len;
1372         int common_rates[DP_MAX_SUPPORTED_RATES];
1373         char str[128]; /* FIXME: too big for stack? */
1374
1375         if ((drm_debug & DRM_UT_KMS) == 0)
1376                 return;
1377
1378         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1379         snprintf_int_array(str, sizeof(str), source_rates, source_len);
1380         DRM_DEBUG_KMS("source rates: %s\n", str);
1381
1382         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1383         snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1384         DRM_DEBUG_KMS("sink rates: %s\n", str);
1385
1386         common_len = intel_dp_common_rates(intel_dp, common_rates);
1387         snprintf_int_array(str, sizeof(str), common_rates, common_len);
1388         DRM_DEBUG_KMS("common rates: %s\n", str);
1389 }
1390
1391 static int rate_to_index(int find, const int *rates)
1392 {
1393         int i = 0;
1394
1395         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1396                 if (find == rates[i])
1397                         break;
1398
1399         return i;
1400 }
1401
1402 int
1403 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1404 {
1405         int rates[DP_MAX_SUPPORTED_RATES] = {};
1406         int len;
1407
1408         len = intel_dp_common_rates(intel_dp, rates);
1409         if (WARN_ON(len <= 0))
1410                 return 162000;
1411
1412         return rates[rate_to_index(0, rates) - 1];
1413 }
1414
1415 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1416 {
1417         return rate_to_index(rate, intel_dp->sink_rates);
1418 }
1419
1420 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1421                            uint8_t *link_bw, uint8_t *rate_select)
1422 {
1423         if (intel_dp->num_sink_rates) {
1424                 *link_bw = 0;
1425                 *rate_select =
1426                         intel_dp_rate_select(intel_dp, port_clock);
1427         } else {
1428                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1429                 *rate_select = 0;
1430         }
1431 }
1432
1433 bool
1434 intel_dp_compute_config(struct intel_encoder *encoder,
1435                         struct intel_crtc_state *pipe_config)
1436 {
1437         struct drm_device *dev = encoder->base.dev;
1438         struct drm_i915_private *dev_priv = dev->dev_private;
1439         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1440         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1441         enum port port = dp_to_dig_port(intel_dp)->port;
1442         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1443         struct intel_connector *intel_connector = intel_dp->attached_connector;
1444         int lane_count, clock;
1445         int min_lane_count = 1;
1446         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1447         /* Conveniently, the link BW constants become indices with a shift...*/
1448         int min_clock = 0;
1449         int max_clock;
1450         int bpp, mode_rate;
1451         int link_avail, link_clock;
1452         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1453         int common_len;
1454         uint8_t link_bw, rate_select;
1455
1456         common_len = intel_dp_common_rates(intel_dp, common_rates);
1457
1458         /* No common link rates between source and sink */
1459         WARN_ON(common_len <= 0);
1460
1461         max_clock = common_len - 1;
1462
1463         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1464                 pipe_config->has_pch_encoder = true;
1465
1466         pipe_config->has_dp_encoder = true;
1467         pipe_config->has_drrs = false;
1468         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1469
1470         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1471                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1472                                        adjusted_mode);
1473
1474                 if (INTEL_INFO(dev)->gen >= 9) {
1475                         int ret;
1476                         ret = skl_update_scaler_crtc(pipe_config);
1477                         if (ret)
1478                                 return ret;
1479                 }
1480
1481                 if (HAS_GMCH_DISPLAY(dev))
1482                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1483                                                  intel_connector->panel.fitting_mode);
1484                 else
1485                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1486                                                 intel_connector->panel.fitting_mode);
1487         }
1488
1489         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1490                 return false;
1491
1492         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1493                       "max bw %d pixel clock %iKHz\n",
1494                       max_lane_count, common_rates[max_clock],
1495                       adjusted_mode->crtc_clock);
1496
1497         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1498          * bpc in between. */
1499         bpp = pipe_config->pipe_bpp;
1500         if (is_edp(intel_dp)) {
1501
1502                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1503                 if (intel_connector->base.display_info.bpc == 0 &&
1504                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1505                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1506                                       dev_priv->vbt.edp.bpp);
1507                         bpp = dev_priv->vbt.edp.bpp;
1508                 }
1509
1510                 /*
1511                  * Use the maximum clock and number of lanes the eDP panel
1512                  * advertizes being capable of. The panels are generally
1513                  * designed to support only a single clock and lane
1514                  * configuration, and typically these values correspond to the
1515                  * native resolution of the panel.
1516                  */
1517                 min_lane_count = max_lane_count;
1518                 min_clock = max_clock;
1519         }
1520
1521         for (; bpp >= 6*3; bpp -= 2*3) {
1522                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1523                                                    bpp);
1524
1525                 for (clock = min_clock; clock <= max_clock; clock++) {
1526                         for (lane_count = min_lane_count;
1527                                 lane_count <= max_lane_count;
1528                                 lane_count <<= 1) {
1529
1530                                 link_clock = common_rates[clock];
1531                                 link_avail = intel_dp_max_data_rate(link_clock,
1532                                                                     lane_count);
1533
1534                                 if (mode_rate <= link_avail) {
1535                                         goto found;
1536                                 }
1537                         }
1538                 }
1539         }
1540
1541         return false;
1542
1543 found:
1544         if (intel_dp->color_range_auto) {
1545                 /*
1546                  * See:
1547                  * CEA-861-E - 5.1 Default Encoding Parameters
1548                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1549                  */
1550                 pipe_config->limited_color_range =
1551                         bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1552         } else {
1553                 pipe_config->limited_color_range =
1554                         intel_dp->limited_color_range;
1555         }
1556
1557         pipe_config->lane_count = lane_count;
1558
1559         pipe_config->pipe_bpp = bpp;
1560         pipe_config->port_clock = common_rates[clock];
1561
1562         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1563                               &link_bw, &rate_select);
1564
1565         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1566                       link_bw, rate_select, pipe_config->lane_count,
1567                       pipe_config->port_clock, bpp);
1568         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1569                       mode_rate, link_avail);
1570
1571         intel_link_compute_m_n(bpp, lane_count,
1572                                adjusted_mode->crtc_clock,
1573                                pipe_config->port_clock,
1574                                &pipe_config->dp_m_n);
1575
1576         if (intel_connector->panel.downclock_mode != NULL &&
1577                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1578                         pipe_config->has_drrs = true;
1579                         intel_link_compute_m_n(bpp, lane_count,
1580                                 intel_connector->panel.downclock_mode->clock,
1581                                 pipe_config->port_clock,
1582                                 &pipe_config->dp_m2_n2);
1583         }
1584
1585         if (!HAS_DDI(dev))
1586                 intel_dp_set_clock(encoder, pipe_config);
1587
1588         return true;
1589 }
1590
1591 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1592                               const struct intel_crtc_state *pipe_config)
1593 {
1594         intel_dp->link_rate = pipe_config->port_clock;
1595         intel_dp->lane_count = pipe_config->lane_count;
1596 }
1597
1598 static void intel_dp_prepare(struct intel_encoder *encoder)
1599 {
1600         struct drm_device *dev = encoder->base.dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1603         enum port port = dp_to_dig_port(intel_dp)->port;
1604         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1605         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1606
1607         intel_dp_set_link_params(intel_dp, crtc->config);
1608
1609         /*
1610          * There are four kinds of DP registers:
1611          *
1612          *      IBX PCH
1613          *      SNB CPU
1614          *      IVB CPU
1615          *      CPT PCH
1616          *
1617          * IBX PCH and CPU are the same for almost everything,
1618          * except that the CPU DP PLL is configured in this
1619          * register
1620          *
1621          * CPT PCH is quite different, having many bits moved
1622          * to the TRANS_DP_CTL register instead. That
1623          * configuration happens (oddly) in ironlake_pch_enable
1624          */
1625
1626         /* Preserve the BIOS-computed detected bit. This is
1627          * supposed to be read-only.
1628          */
1629         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1630
1631         /* Handle DP bits in common between all three register formats */
1632         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1633         intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
1634
1635         /* Split out the IBX/CPU vs CPT settings */
1636
1637         if (IS_GEN7(dev) && port == PORT_A) {
1638                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1639                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1640                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1641                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1642                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1643
1644                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1645                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1646
1647                 intel_dp->DP |= crtc->pipe << 29;
1648         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1649                 u32 trans_dp;
1650
1651                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1652
1653                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1654                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1655                         trans_dp |= TRANS_DP_ENH_FRAMING;
1656                 else
1657                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1658                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1659         } else {
1660                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1661                     !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
1662                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1663
1664                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1665                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1666                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1667                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1668                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1669
1670                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1671                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1672
1673                 if (IS_CHERRYVIEW(dev))
1674                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1675                 else if (crtc->pipe == PIPE_B)
1676                         intel_dp->DP |= DP_PIPEB_SELECT;
1677         }
1678 }
1679
1680 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1681 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1682
1683 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1684 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1685
1686 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1687 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1688
1689 static void wait_panel_status(struct intel_dp *intel_dp,
1690                                        u32 mask,
1691                                        u32 value)
1692 {
1693         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1694         struct drm_i915_private *dev_priv = dev->dev_private;
1695         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1696
1697         lockdep_assert_held(&dev_priv->pps_mutex);
1698
1699         pp_stat_reg = _pp_stat_reg(intel_dp);
1700         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1701
1702         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1703                         mask, value,
1704                         I915_READ(pp_stat_reg),
1705                         I915_READ(pp_ctrl_reg));
1706
1707         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value,
1708                       5 * USEC_PER_SEC, 10 * USEC_PER_MSEC))
1709                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1710                                 I915_READ(pp_stat_reg),
1711                                 I915_READ(pp_ctrl_reg));
1712
1713         DRM_DEBUG_KMS("Wait complete\n");
1714 }
1715
1716 static void wait_panel_on(struct intel_dp *intel_dp)
1717 {
1718         DRM_DEBUG_KMS("Wait for panel power on\n");
1719         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1720 }
1721
1722 static void wait_panel_off(struct intel_dp *intel_dp)
1723 {
1724         DRM_DEBUG_KMS("Wait for panel power off time\n");
1725         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1726 }
1727
1728 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1729 {
1730         ktime_t panel_power_on_time;
1731         s64 panel_power_off_duration;
1732
1733         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1734
1735         /* take the difference of currrent time and panel power off time
1736          * and then make panel wait for t11_t12 if needed. */
1737         panel_power_on_time = ktime_get_boottime();
1738         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1739
1740         /* When we disable the VDD override bit last we have to do the manual
1741          * wait. */
1742         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1743                 wait_remaining_ms_from_jiffies(jiffies,
1744                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1745
1746         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1747 }
1748
1749 static void wait_backlight_on(struct intel_dp *intel_dp)
1750 {
1751         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1752                                        intel_dp->backlight_on_delay);
1753 }
1754
1755 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1756 {
1757         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1758                                        intel_dp->backlight_off_delay);
1759 }
1760
1761 /* Read the current pp_control value, unlocking the register if it
1762  * is locked
1763  */
1764
1765 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1766 {
1767         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1768         struct drm_i915_private *dev_priv = dev->dev_private;
1769         u32 control;
1770
1771         lockdep_assert_held(&dev_priv->pps_mutex);
1772
1773         control = I915_READ(_pp_ctrl_reg(intel_dp));
1774         if (!IS_BROXTON(dev)) {
1775                 control &= ~PANEL_UNLOCK_MASK;
1776                 control |= PANEL_UNLOCK_REGS;
1777         }
1778         return control;
1779 }
1780
1781 /*
1782  * Must be paired with edp_panel_vdd_off().
1783  * Must hold pps_mutex around the whole on/off sequence.
1784  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1785  */
1786 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1787 {
1788         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1789         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1790         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1791         struct drm_i915_private *dev_priv = dev->dev_private;
1792         enum intel_display_power_domain power_domain;
1793         u32 pp;
1794         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1795         bool need_to_disable = !intel_dp->want_panel_vdd;
1796
1797         lockdep_assert_held(&dev_priv->pps_mutex);
1798
1799         if (!is_edp(intel_dp))
1800                 return false;
1801
1802         cancel_delayed_work(&intel_dp->panel_vdd_work);
1803         intel_dp->want_panel_vdd = true;
1804
1805         if (edp_have_panel_vdd(intel_dp))
1806                 return need_to_disable;
1807
1808         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1809         intel_display_power_get(dev_priv, power_domain);
1810
1811         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1812                       port_name(intel_dig_port->port));
1813
1814         if (!edp_have_panel_power(intel_dp))
1815                 wait_panel_power_cycle(intel_dp);
1816
1817         pp = ironlake_get_pp_control(intel_dp);
1818         pp |= EDP_FORCE_VDD;
1819
1820         pp_stat_reg = _pp_stat_reg(intel_dp);
1821         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1822
1823         I915_WRITE(pp_ctrl_reg, pp);
1824         POSTING_READ(pp_ctrl_reg);
1825         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1826                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1827         /*
1828          * If the panel wasn't on, delay before accessing aux channel
1829          */
1830         if (!edp_have_panel_power(intel_dp)) {
1831                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1832                               port_name(intel_dig_port->port));
1833                 msleep(intel_dp->panel_power_up_delay);
1834         }
1835
1836         return need_to_disable;
1837 }
1838
1839 /*
1840  * Must be paired with intel_edp_panel_vdd_off() or
1841  * intel_edp_panel_off().
1842  * Nested calls to these functions are not allowed since
1843  * we drop the lock. Caller must use some higher level
1844  * locking to prevent nested calls from other threads.
1845  */
1846 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1847 {
1848         bool vdd;
1849
1850         if (!is_edp(intel_dp))
1851                 return;
1852
1853         pps_lock(intel_dp);
1854         vdd = edp_panel_vdd_on(intel_dp);
1855         pps_unlock(intel_dp);
1856
1857         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1858              port_name(dp_to_dig_port(intel_dp)->port));
1859 }
1860
1861 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1862 {
1863         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1864         struct drm_i915_private *dev_priv = dev->dev_private;
1865         struct intel_digital_port *intel_dig_port =
1866                 dp_to_dig_port(intel_dp);
1867         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1868         enum intel_display_power_domain power_domain;
1869         u32 pp;
1870         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1871
1872         lockdep_assert_held(&dev_priv->pps_mutex);
1873
1874         WARN_ON(intel_dp->want_panel_vdd);
1875
1876         if (!edp_have_panel_vdd(intel_dp))
1877                 return;
1878
1879         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1880                       port_name(intel_dig_port->port));
1881
1882         pp = ironlake_get_pp_control(intel_dp);
1883         pp &= ~EDP_FORCE_VDD;
1884
1885         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1886         pp_stat_reg = _pp_stat_reg(intel_dp);
1887
1888         I915_WRITE(pp_ctrl_reg, pp);
1889         POSTING_READ(pp_ctrl_reg);
1890
1891         /* Make sure sequencer is idle before allowing subsequent activity */
1892         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1893         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1894
1895         if ((pp & POWER_TARGET_ON) == 0)
1896                 intel_dp->panel_power_off_time = ktime_get_boottime();
1897
1898         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1899         intel_display_power_put(dev_priv, power_domain);
1900 }
1901
1902 static void edp_panel_vdd_work(struct work_struct *__work)
1903 {
1904         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1905                                                  struct intel_dp, panel_vdd_work);
1906
1907         pps_lock(intel_dp);
1908         if (!intel_dp->want_panel_vdd)
1909                 edp_panel_vdd_off_sync(intel_dp);
1910         pps_unlock(intel_dp);
1911 }
1912
1913 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1914 {
1915         unsigned long delay;
1916
1917         /*
1918          * Queue the timer to fire a long time from now (relative to the power
1919          * down delay) to keep the panel power up across a sequence of
1920          * operations.
1921          */
1922         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1923         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1924 }
1925
1926 /*
1927  * Must be paired with edp_panel_vdd_on().
1928  * Must hold pps_mutex around the whole on/off sequence.
1929  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1930  */
1931 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1932 {
1933         struct drm_i915_private *dev_priv =
1934                 intel_dp_to_dev(intel_dp)->dev_private;
1935
1936         lockdep_assert_held(&dev_priv->pps_mutex);
1937
1938         if (!is_edp(intel_dp))
1939                 return;
1940
1941         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1942              port_name(dp_to_dig_port(intel_dp)->port));
1943
1944         intel_dp->want_panel_vdd = false;
1945
1946         if (sync)
1947                 edp_panel_vdd_off_sync(intel_dp);
1948         else
1949                 edp_panel_vdd_schedule_off(intel_dp);
1950 }
1951
1952 static void edp_panel_on(struct intel_dp *intel_dp)
1953 {
1954         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1955         struct drm_i915_private *dev_priv = dev->dev_private;
1956         u32 pp;
1957         i915_reg_t pp_ctrl_reg;
1958
1959         lockdep_assert_held(&dev_priv->pps_mutex);
1960
1961         if (!is_edp(intel_dp))
1962                 return;
1963
1964         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1965                       port_name(dp_to_dig_port(intel_dp)->port));
1966
1967         if (WARN(edp_have_panel_power(intel_dp),
1968                  "eDP port %c panel power already on\n",
1969                  port_name(dp_to_dig_port(intel_dp)->port)))
1970                 return;
1971
1972         wait_panel_power_cycle(intel_dp);
1973
1974         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1975         pp = ironlake_get_pp_control(intel_dp);
1976         if (IS_GEN5(dev)) {
1977                 /* ILK workaround: disable reset around power sequence */
1978                 pp &= ~PANEL_POWER_RESET;
1979                 I915_WRITE(pp_ctrl_reg, pp);
1980                 POSTING_READ(pp_ctrl_reg);
1981         }
1982
1983         pp |= POWER_TARGET_ON;
1984         if (!IS_GEN5(dev))
1985                 pp |= PANEL_POWER_RESET;
1986
1987         I915_WRITE(pp_ctrl_reg, pp);
1988         POSTING_READ(pp_ctrl_reg);
1989
1990         wait_panel_on(intel_dp);
1991         intel_dp->last_power_on = jiffies;
1992
1993         if (IS_GEN5(dev)) {
1994                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1995                 I915_WRITE(pp_ctrl_reg, pp);
1996                 POSTING_READ(pp_ctrl_reg);
1997         }
1998 }
1999
2000 void intel_edp_panel_on(struct intel_dp *intel_dp)
2001 {
2002         if (!is_edp(intel_dp))
2003                 return;
2004
2005         pps_lock(intel_dp);
2006         edp_panel_on(intel_dp);
2007         pps_unlock(intel_dp);
2008 }
2009
2010
2011 static void edp_panel_off(struct intel_dp *intel_dp)
2012 {
2013         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2014         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2015         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2016         struct drm_i915_private *dev_priv = dev->dev_private;
2017         enum intel_display_power_domain power_domain;
2018         u32 pp;
2019         i915_reg_t pp_ctrl_reg;
2020
2021         lockdep_assert_held(&dev_priv->pps_mutex);
2022
2023         if (!is_edp(intel_dp))
2024                 return;
2025
2026         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2027                       port_name(dp_to_dig_port(intel_dp)->port));
2028
2029         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2030              port_name(dp_to_dig_port(intel_dp)->port));
2031
2032         pp = ironlake_get_pp_control(intel_dp);
2033         /* We need to switch off panel power _and_ force vdd, for otherwise some
2034          * panels get very unhappy and cease to work. */
2035         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2036                 EDP_BLC_ENABLE);
2037
2038         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2039
2040         intel_dp->want_panel_vdd = false;
2041
2042         I915_WRITE(pp_ctrl_reg, pp);
2043         POSTING_READ(pp_ctrl_reg);
2044
2045         intel_dp->panel_power_off_time = ktime_get_boottime();
2046         wait_panel_off(intel_dp);
2047
2048         /* We got a reference when we enabled the VDD. */
2049         power_domain = intel_display_port_aux_power_domain(intel_encoder);
2050         intel_display_power_put(dev_priv, power_domain);
2051 }
2052
2053 void intel_edp_panel_off(struct intel_dp *intel_dp)
2054 {
2055         if (!is_edp(intel_dp))
2056                 return;
2057
2058         pps_lock(intel_dp);
2059         edp_panel_off(intel_dp);
2060         pps_unlock(intel_dp);
2061 }
2062
2063 /* Enable backlight in the panel power control. */
2064 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2065 {
2066         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2067         struct drm_device *dev = intel_dig_port->base.base.dev;
2068         struct drm_i915_private *dev_priv = dev->dev_private;
2069         u32 pp;
2070         i915_reg_t pp_ctrl_reg;
2071
2072         /*
2073          * If we enable the backlight right away following a panel power
2074          * on, we may see slight flicker as the panel syncs with the eDP
2075          * link.  So delay a bit to make sure the image is solid before
2076          * allowing it to appear.
2077          */
2078         wait_backlight_on(intel_dp);
2079
2080         pps_lock(intel_dp);
2081
2082         pp = ironlake_get_pp_control(intel_dp);
2083         pp |= EDP_BLC_ENABLE;
2084
2085         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2086
2087         I915_WRITE(pp_ctrl_reg, pp);
2088         POSTING_READ(pp_ctrl_reg);
2089
2090         pps_unlock(intel_dp);
2091 }
2092
2093 /* Enable backlight PWM and backlight PP control. */
2094 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2095 {
2096         if (!is_edp(intel_dp))
2097                 return;
2098
2099         DRM_DEBUG_KMS("\n");
2100
2101         intel_panel_enable_backlight(intel_dp->attached_connector);
2102         _intel_edp_backlight_on(intel_dp);
2103 }
2104
2105 /* Disable backlight in the panel power control. */
2106 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2107 {
2108         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2109         struct drm_i915_private *dev_priv = dev->dev_private;
2110         u32 pp;
2111         i915_reg_t pp_ctrl_reg;
2112
2113         if (!is_edp(intel_dp))
2114                 return;
2115
2116         pps_lock(intel_dp);
2117
2118         pp = ironlake_get_pp_control(intel_dp);
2119         pp &= ~EDP_BLC_ENABLE;
2120
2121         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2122
2123         I915_WRITE(pp_ctrl_reg, pp);
2124         POSTING_READ(pp_ctrl_reg);
2125
2126         pps_unlock(intel_dp);
2127
2128         intel_dp->last_backlight_off = jiffies;
2129         edp_wait_backlight_off(intel_dp);
2130 }
2131
2132 /* Disable backlight PP control and backlight PWM. */
2133 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2134 {
2135         if (!is_edp(intel_dp))
2136                 return;
2137
2138         DRM_DEBUG_KMS("\n");
2139
2140         _intel_edp_backlight_off(intel_dp);
2141         intel_panel_disable_backlight(intel_dp->attached_connector);
2142 }
2143
2144 /*
2145  * Hook for controlling the panel power control backlight through the bl_power
2146  * sysfs attribute. Take care to handle multiple calls.
2147  */
2148 static void intel_edp_backlight_power(struct intel_connector *connector,
2149                                       bool enable)
2150 {
2151         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2152         bool is_enabled;
2153
2154         pps_lock(intel_dp);
2155         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2156         pps_unlock(intel_dp);
2157
2158         if (is_enabled == enable)
2159                 return;
2160
2161         DRM_DEBUG_KMS("panel power control backlight %s\n",
2162                       enable ? "enable" : "disable");
2163
2164         if (enable)
2165                 _intel_edp_backlight_on(intel_dp);
2166         else
2167                 _intel_edp_backlight_off(intel_dp);
2168 }
2169
2170 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2171 {
2172         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2173         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2174         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2175
2176         I915_STATE_WARN(cur_state != state,
2177                         "DP port %c state assertion failure (expected %s, current %s)\n",
2178                         port_name(dig_port->port),
2179                         onoff(state), onoff(cur_state));
2180 }
2181 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2182
2183 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2184 {
2185         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2186
2187         I915_STATE_WARN(cur_state != state,
2188                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2189                         onoff(state), onoff(cur_state));
2190 }
2191 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2192 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2193
2194 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2195 {
2196         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2197         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2198         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2199
2200         assert_pipe_disabled(dev_priv, crtc->pipe);
2201         assert_dp_port_disabled(intel_dp);
2202         assert_edp_pll_disabled(dev_priv);
2203
2204         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2205                       crtc->config->port_clock);
2206
2207         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2208
2209         if (crtc->config->port_clock == 162000)
2210                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2211         else
2212                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2213
2214         I915_WRITE(DP_A, intel_dp->DP);
2215         POSTING_READ(DP_A);
2216         udelay(500);
2217
2218         intel_dp->DP |= DP_PLL_ENABLE;
2219
2220         I915_WRITE(DP_A, intel_dp->DP);
2221         POSTING_READ(DP_A);
2222         udelay(200);
2223 }
2224
2225 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2226 {
2227         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2228         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2229         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2230
2231         assert_pipe_disabled(dev_priv, crtc->pipe);
2232         assert_dp_port_disabled(intel_dp);
2233         assert_edp_pll_enabled(dev_priv);
2234
2235         DRM_DEBUG_KMS("disabling eDP PLL\n");
2236
2237         intel_dp->DP &= ~DP_PLL_ENABLE;
2238
2239         I915_WRITE(DP_A, intel_dp->DP);
2240         POSTING_READ(DP_A);
2241         udelay(200);
2242 }
2243
2244 /* If the sink supports it, try to set the power state appropriately */
2245 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2246 {
2247         int ret, i;
2248
2249         /* Should have a valid DPCD by this point */
2250         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2251                 return;
2252
2253         if (mode != DRM_MODE_DPMS_ON) {
2254                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2255                                          DP_SET_POWER_D3);
2256         } else {
2257                 /*
2258                  * When turning on, we need to retry for 1ms to give the sink
2259                  * time to wake up.
2260                  */
2261                 for (i = 0; i < 3; i++) {
2262                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2263                                                  DP_SET_POWER_D0);
2264                         if (ret == 1)
2265                                 break;
2266                         msleep(1);
2267                 }
2268         }
2269
2270         if (ret != 1)
2271                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2272                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2273 }
2274
2275 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2276                                   enum pipe *pipe)
2277 {
2278         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2279         enum port port = dp_to_dig_port(intel_dp)->port;
2280         struct drm_device *dev = encoder->base.dev;
2281         struct drm_i915_private *dev_priv = dev->dev_private;
2282         enum intel_display_power_domain power_domain;
2283         u32 tmp;
2284         bool ret;
2285
2286         power_domain = intel_display_port_power_domain(encoder);
2287         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2288                 return false;
2289
2290         ret = false;
2291
2292         tmp = I915_READ(intel_dp->output_reg);
2293
2294         if (!(tmp & DP_PORT_EN))
2295                 goto out;
2296
2297         if (IS_GEN7(dev) && port == PORT_A) {
2298                 *pipe = PORT_TO_PIPE_CPT(tmp);
2299         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2300                 enum pipe p;
2301
2302                 for_each_pipe(dev_priv, p) {
2303                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2304                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2305                                 *pipe = p;
2306                                 ret = true;
2307
2308                                 goto out;
2309                         }
2310                 }
2311
2312                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2313                               i915_mmio_reg_offset(intel_dp->output_reg));
2314         } else if (IS_CHERRYVIEW(dev)) {
2315                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2316         } else {
2317                 *pipe = PORT_TO_PIPE(tmp);
2318         }
2319
2320         ret = true;
2321
2322 out:
2323         intel_display_power_put(dev_priv, power_domain);
2324
2325         return ret;
2326 }
2327
2328 static void intel_dp_get_config(struct intel_encoder *encoder,
2329                                 struct intel_crtc_state *pipe_config)
2330 {
2331         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2332         u32 tmp, flags = 0;
2333         struct drm_device *dev = encoder->base.dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         enum port port = dp_to_dig_port(intel_dp)->port;
2336         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2337
2338         tmp = I915_READ(intel_dp->output_reg);
2339
2340         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2341
2342         if (HAS_PCH_CPT(dev) && port != PORT_A) {
2343                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2344
2345                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2346                         flags |= DRM_MODE_FLAG_PHSYNC;
2347                 else
2348                         flags |= DRM_MODE_FLAG_NHSYNC;
2349
2350                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2351                         flags |= DRM_MODE_FLAG_PVSYNC;
2352                 else
2353                         flags |= DRM_MODE_FLAG_NVSYNC;
2354         } else {
2355                 if (tmp & DP_SYNC_HS_HIGH)
2356                         flags |= DRM_MODE_FLAG_PHSYNC;
2357                 else
2358                         flags |= DRM_MODE_FLAG_NHSYNC;
2359
2360                 if (tmp & DP_SYNC_VS_HIGH)
2361                         flags |= DRM_MODE_FLAG_PVSYNC;
2362                 else
2363                         flags |= DRM_MODE_FLAG_NVSYNC;
2364         }
2365
2366         pipe_config->base.adjusted_mode.flags |= flags;
2367
2368         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2369             !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
2370                 pipe_config->limited_color_range = true;
2371
2372         pipe_config->has_dp_encoder = true;
2373
2374         pipe_config->lane_count =
2375                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2376
2377         intel_dp_get_m_n(crtc, pipe_config);
2378
2379         if (port == PORT_A) {
2380                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2381                         pipe_config->port_clock = 162000;
2382                 else
2383                         pipe_config->port_clock = 270000;
2384         }
2385
2386         pipe_config->base.adjusted_mode.crtc_clock =
2387                 intel_dotclock_calculate(pipe_config->port_clock,
2388                                          &pipe_config->dp_m_n);
2389
2390         if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2391             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2392                 /*
2393                  * This is a big fat ugly hack.
2394                  *
2395                  * Some machines in UEFI boot mode provide us a VBT that has 18
2396                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2397                  * unknown we fail to light up. Yet the same BIOS boots up with
2398                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2399                  * max, not what it tells us to use.
2400                  *
2401                  * Note: This will still be broken if the eDP panel is not lit
2402                  * up by the BIOS, and thus we can't get the mode at module
2403                  * load.
2404                  */
2405                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2406                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2407                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2408         }
2409 }
2410
2411 static void intel_disable_dp(struct intel_encoder *encoder)
2412 {
2413         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2414         struct drm_device *dev = encoder->base.dev;
2415         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2416
2417         if (crtc->config->has_audio)
2418                 intel_audio_codec_disable(encoder);
2419
2420         if (HAS_PSR(dev) && !HAS_DDI(dev))
2421                 intel_psr_disable(intel_dp);
2422
2423         /* Make sure the panel is off before trying to change the mode. But also
2424          * ensure that we have vdd while we switch off the panel. */
2425         intel_edp_panel_vdd_on(intel_dp);
2426         intel_edp_backlight_off(intel_dp);
2427         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2428         intel_edp_panel_off(intel_dp);
2429
2430         /* disable the port before the pipe on g4x */
2431         if (INTEL_INFO(dev)->gen < 5)
2432                 intel_dp_link_down(intel_dp);
2433 }
2434
2435 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2436 {
2437         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2438         enum port port = dp_to_dig_port(intel_dp)->port;
2439
2440         intel_dp_link_down(intel_dp);
2441
2442         /* Only ilk+ has port A */
2443         if (port == PORT_A)
2444                 ironlake_edp_pll_off(intel_dp);
2445 }
2446
2447 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2448 {
2449         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2450
2451         intel_dp_link_down(intel_dp);
2452 }
2453
2454 static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
2455                                      bool reset)
2456 {
2457         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2458         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
2459         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2460         enum pipe pipe = crtc->pipe;
2461         uint32_t val;
2462
2463         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2464         if (reset)
2465                 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2466         else
2467                 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2468         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2469
2470         if (crtc->config->lane_count > 2) {
2471                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2472                 if (reset)
2473                         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2474                 else
2475                         val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2476                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2477         }
2478
2479         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2480         val |= CHV_PCS_REQ_SOFTRESET_EN;
2481         if (reset)
2482                 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2483         else
2484                 val |= DPIO_PCS_CLK_SOFT_RESET;
2485         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2486
2487         if (crtc->config->lane_count > 2) {
2488                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2489                 val |= CHV_PCS_REQ_SOFTRESET_EN;
2490                 if (reset)
2491                         val &= ~DPIO_PCS_CLK_SOFT_RESET;
2492                 else
2493                         val |= DPIO_PCS_CLK_SOFT_RESET;
2494                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2495         }
2496 }
2497
2498 static void chv_post_disable_dp(struct intel_encoder *encoder)
2499 {
2500         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2501         struct drm_device *dev = encoder->base.dev;
2502         struct drm_i915_private *dev_priv = dev->dev_private;
2503
2504         intel_dp_link_down(intel_dp);
2505
2506         mutex_lock(&dev_priv->sb_lock);
2507
2508         /* Assert data lane reset */
2509         chv_data_lane_soft_reset(encoder, true);
2510
2511         mutex_unlock(&dev_priv->sb_lock);
2512 }
2513
2514 static void
2515 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2516                          uint32_t *DP,
2517                          uint8_t dp_train_pat)
2518 {
2519         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2520         struct drm_device *dev = intel_dig_port->base.base.dev;
2521         struct drm_i915_private *dev_priv = dev->dev_private;
2522         enum port port = intel_dig_port->port;
2523
2524         if (HAS_DDI(dev)) {
2525                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2526
2527                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2528                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2529                 else
2530                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2531
2532                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2533                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2534                 case DP_TRAINING_PATTERN_DISABLE:
2535                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2536
2537                         break;
2538                 case DP_TRAINING_PATTERN_1:
2539                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2540                         break;
2541                 case DP_TRAINING_PATTERN_2:
2542                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2543                         break;
2544                 case DP_TRAINING_PATTERN_3:
2545                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2546                         break;
2547                 }
2548                 I915_WRITE(DP_TP_CTL(port), temp);
2549
2550         } else if ((IS_GEN7(dev) && port == PORT_A) ||
2551                    (HAS_PCH_CPT(dev) && port != PORT_A)) {
2552                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2553
2554                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2555                 case DP_TRAINING_PATTERN_DISABLE:
2556                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2557                         break;
2558                 case DP_TRAINING_PATTERN_1:
2559                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2560                         break;
2561                 case DP_TRAINING_PATTERN_2:
2562                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2563                         break;
2564                 case DP_TRAINING_PATTERN_3:
2565                         DRM_ERROR("DP training pattern 3 not supported\n");
2566                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2567                         break;
2568                 }
2569
2570         } else {
2571                 if (IS_CHERRYVIEW(dev))
2572                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2573                 else
2574                         *DP &= ~DP_LINK_TRAIN_MASK;
2575
2576                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2577                 case DP_TRAINING_PATTERN_DISABLE:
2578                         *DP |= DP_LINK_TRAIN_OFF;
2579                         break;
2580                 case DP_TRAINING_PATTERN_1:
2581                         *DP |= DP_LINK_TRAIN_PAT_1;
2582                         break;
2583                 case DP_TRAINING_PATTERN_2:
2584                         *DP |= DP_LINK_TRAIN_PAT_2;
2585                         break;
2586                 case DP_TRAINING_PATTERN_3:
2587                         if (IS_CHERRYVIEW(dev)) {
2588                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2589                         } else {
2590                                 DRM_ERROR("DP training pattern 3 not supported\n");
2591                                 *DP |= DP_LINK_TRAIN_PAT_2;
2592                         }
2593                         break;
2594                 }
2595         }
2596 }
2597
2598 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2599 {
2600         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2601         struct drm_i915_private *dev_priv = dev->dev_private;
2602         struct intel_crtc *crtc =
2603                 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
2604
2605         /* enable with pattern 1 (as per spec) */
2606         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2607                                  DP_TRAINING_PATTERN_1);
2608
2609         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2610         POSTING_READ(intel_dp->output_reg);
2611
2612         /*
2613          * Magic for VLV/CHV. We _must_ first set up the register
2614          * without actually enabling the port, and then do another
2615          * write to enable the port. Otherwise link training will
2616          * fail when the power sequencer is freshly used for this port.
2617          */
2618         intel_dp->DP |= DP_PORT_EN;
2619         if (crtc->config->has_audio)
2620                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2621
2622         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2623         POSTING_READ(intel_dp->output_reg);
2624 }
2625
2626 static void intel_enable_dp(struct intel_encoder *encoder)
2627 {
2628         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2629         struct drm_device *dev = encoder->base.dev;
2630         struct drm_i915_private *dev_priv = dev->dev_private;
2631         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2632         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2633         enum port port = dp_to_dig_port(intel_dp)->port;
2634         enum pipe pipe = crtc->pipe;
2635
2636         if (WARN_ON(dp_reg & DP_PORT_EN))
2637                 return;
2638
2639         pps_lock(intel_dp);
2640
2641         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2642                 vlv_init_panel_power_sequencer(intel_dp);
2643
2644         /*
2645          * We get an occasional spurious underrun between the port
2646          * enable and vdd enable, when enabling port A eDP.
2647          *
2648          * FIXME: Not sure if this applies to (PCH) port D eDP as well
2649          */
2650         if (port == PORT_A)
2651                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2652
2653         intel_dp_enable_port(intel_dp);
2654
2655         if (port == PORT_A && IS_GEN5(dev_priv)) {
2656                 /*
2657                  * Underrun reporting for the other pipe was disabled in
2658                  * g4x_pre_enable_dp(). The eDP PLL and port have now been
2659                  * enabled, so it's now safe to re-enable underrun reporting.
2660                  */
2661                 intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
2662                 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
2663                 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
2664         }
2665
2666         edp_panel_vdd_on(intel_dp);
2667         edp_panel_on(intel_dp);
2668         edp_panel_vdd_off(intel_dp, true);
2669
2670         if (port == PORT_A)
2671                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2672
2673         pps_unlock(intel_dp);
2674
2675         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2676                 unsigned int lane_mask = 0x0;
2677
2678                 if (IS_CHERRYVIEW(dev))
2679                         lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2680
2681                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2682                                     lane_mask);
2683         }
2684
2685         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2686         intel_dp_start_link_train(intel_dp);
2687         intel_dp_stop_link_train(intel_dp);
2688
2689         if (crtc->config->has_audio) {
2690                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2691                                  pipe_name(pipe));
2692                 intel_audio_codec_enable(encoder);
2693         }
2694 }
2695
2696 static void g4x_enable_dp(struct intel_encoder *encoder)
2697 {
2698         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2699
2700         intel_enable_dp(encoder);
2701         intel_edp_backlight_on(intel_dp);
2702 }
2703
2704 static void vlv_enable_dp(struct intel_encoder *encoder)
2705 {
2706         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2707
2708         intel_edp_backlight_on(intel_dp);
2709         intel_psr_enable(intel_dp);
2710 }
2711
2712 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2713 {
2714         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2715         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2716         enum port port = dp_to_dig_port(intel_dp)->port;
2717         enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
2718
2719         intel_dp_prepare(encoder);
2720
2721         if (port == PORT_A && IS_GEN5(dev_priv)) {
2722                 /*
2723                  * We get FIFO underruns on the other pipe when
2724                  * enabling the CPU eDP PLL, and when enabling CPU
2725                  * eDP port. We could potentially avoid the PLL
2726                  * underrun with a vblank wait just prior to enabling
2727                  * the PLL, but that doesn't appear to help the port
2728                  * enable case. Just sweep it all under the rug.
2729                  */
2730                 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
2731                 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
2732         }
2733
2734         /* Only ilk+ has port A */
2735         if (port == PORT_A)
2736                 ironlake_edp_pll_on(intel_dp);
2737 }
2738
2739 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2740 {
2741         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2742         struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2743         enum pipe pipe = intel_dp->pps_pipe;
2744         i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2745
2746         edp_panel_vdd_off_sync(intel_dp);
2747
2748         /*
2749          * VLV seems to get confused when multiple power seqeuencers
2750          * have the same port selected (even if only one has power/vdd
2751          * enabled). The failure manifests as vlv_wait_port_ready() failing
2752          * CHV on the other hand doesn't seem to mind having the same port
2753          * selected in multiple power seqeuencers, but let's clear the
2754          * port select always when logically disconnecting a power sequencer
2755          * from a port.
2756          */
2757         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2758                       pipe_name(pipe), port_name(intel_dig_port->port));
2759         I915_WRITE(pp_on_reg, 0);
2760         POSTING_READ(pp_on_reg);
2761
2762         intel_dp->pps_pipe = INVALID_PIPE;
2763 }
2764
2765 static void vlv_steal_power_sequencer(struct drm_device *dev,
2766                                       enum pipe pipe)
2767 {
2768         struct drm_i915_private *dev_priv = dev->dev_private;
2769         struct intel_encoder *encoder;
2770
2771         lockdep_assert_held(&dev_priv->pps_mutex);
2772
2773         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2774                 return;
2775
2776         for_each_intel_encoder(dev, encoder) {
2777                 struct intel_dp *intel_dp;
2778                 enum port port;
2779
2780                 if (encoder->type != INTEL_OUTPUT_EDP)
2781                         continue;
2782
2783                 intel_dp = enc_to_intel_dp(&encoder->base);
2784                 port = dp_to_dig_port(intel_dp)->port;
2785
2786                 if (intel_dp->pps_pipe != pipe)
2787                         continue;
2788
2789                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2790                               pipe_name(pipe), port_name(port));
2791
2792                 WARN(encoder->base.crtc,
2793                      "stealing pipe %c power sequencer from active eDP port %c\n",
2794                      pipe_name(pipe), port_name(port));
2795
2796                 /* make sure vdd is off before we steal it */
2797                 vlv_detach_power_sequencer(intel_dp);
2798         }
2799 }
2800
2801 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2802 {
2803         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2804         struct intel_encoder *encoder = &intel_dig_port->base;
2805         struct drm_device *dev = encoder->base.dev;
2806         struct drm_i915_private *dev_priv = dev->dev_private;
2807         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2808
2809         lockdep_assert_held(&dev_priv->pps_mutex);
2810
2811         if (!is_edp(intel_dp))
2812                 return;
2813
2814         if (intel_dp->pps_pipe == crtc->pipe)
2815                 return;
2816
2817         /*
2818          * If another power sequencer was being used on this
2819          * port previously make sure to turn off vdd there while
2820          * we still have control of it.
2821          */
2822         if (intel_dp->pps_pipe != INVALID_PIPE)
2823                 vlv_detach_power_sequencer(intel_dp);
2824
2825         /*
2826          * We may be stealing the power
2827          * sequencer from another port.
2828          */
2829         vlv_steal_power_sequencer(dev, crtc->pipe);
2830
2831         /* now it's all ours */
2832         intel_dp->pps_pipe = crtc->pipe;
2833
2834         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2835                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2836
2837         /* init power sequencer on this pipe and port */
2838         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2839         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2840 }
2841
2842 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2843 {
2844         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2845         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2846         struct drm_device *dev = encoder->base.dev;
2847         struct drm_i915_private *dev_priv = dev->dev_private;
2848         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2849         enum dpio_channel port = vlv_dport_to_channel(dport);
2850         int pipe = intel_crtc->pipe;
2851         u32 val;
2852
2853         mutex_lock(&dev_priv->sb_lock);
2854
2855         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2856         val = 0;
2857         if (pipe)
2858                 val |= (1<<21);
2859         else
2860                 val &= ~(1<<21);
2861         val |= 0x001000c4;
2862         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2863         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2864         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2865
2866         mutex_unlock(&dev_priv->sb_lock);
2867
2868         intel_enable_dp(encoder);
2869 }
2870
2871 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2872 {
2873         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2874         struct drm_device *dev = encoder->base.dev;
2875         struct drm_i915_private *dev_priv = dev->dev_private;
2876         struct intel_crtc *intel_crtc =
2877                 to_intel_crtc(encoder->base.crtc);
2878         enum dpio_channel port = vlv_dport_to_channel(dport);
2879         int pipe = intel_crtc->pipe;
2880
2881         intel_dp_prepare(encoder);
2882
2883         /* Program Tx lane resets to default */
2884         mutex_lock(&dev_priv->sb_lock);
2885         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2886                          DPIO_PCS_TX_LANE2_RESET |
2887                          DPIO_PCS_TX_LANE1_RESET);
2888         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2889                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2890                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2891                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2892                                  DPIO_PCS_CLK_SOFT_RESET);
2893
2894         /* Fix up inter-pair skew failure */
2895         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2896         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2897         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2898         mutex_unlock(&dev_priv->sb_lock);
2899 }
2900
2901 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2902 {
2903         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2904         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2905         struct drm_device *dev = encoder->base.dev;
2906         struct drm_i915_private *dev_priv = dev->dev_private;
2907         struct intel_crtc *intel_crtc =
2908                 to_intel_crtc(encoder->base.crtc);
2909         enum dpio_channel ch = vlv_dport_to_channel(dport);
2910         int pipe = intel_crtc->pipe;
2911         int data, i, stagger;
2912         u32 val;
2913
2914         mutex_lock(&dev_priv->sb_lock);
2915
2916         /* allow hardware to manage TX FIFO reset source */
2917         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2918         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2919         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2920
2921         if (intel_crtc->config->lane_count > 2) {
2922                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2923                 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2924                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2925         }
2926
2927         /* Program Tx lane latency optimal setting*/
2928         for (i = 0; i < intel_crtc->config->lane_count; i++) {
2929                 /* Set the upar bit */
2930                 if (intel_crtc->config->lane_count == 1)
2931                         data = 0x0;
2932                 else
2933                         data = (i == 1) ? 0x0 : 0x1;
2934                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2935                                 data << DPIO_UPAR_SHIFT);
2936         }
2937
2938         /* Data lane stagger programming */
2939         if (intel_crtc->config->port_clock > 270000)
2940                 stagger = 0x18;
2941         else if (intel_crtc->config->port_clock > 135000)
2942                 stagger = 0xd;
2943         else if (intel_crtc->config->port_clock > 67500)
2944                 stagger = 0x7;
2945         else if (intel_crtc->config->port_clock > 33750)
2946                 stagger = 0x4;
2947         else
2948                 stagger = 0x2;
2949
2950         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2951         val |= DPIO_TX2_STAGGER_MASK(0x1f);
2952         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2953
2954         if (intel_crtc->config->lane_count > 2) {
2955                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2956                 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2957                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2958         }
2959
2960         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
2961                        DPIO_LANESTAGGER_STRAP(stagger) |
2962                        DPIO_LANESTAGGER_STRAP_OVRD |
2963                        DPIO_TX1_STAGGER_MASK(0x1f) |
2964                        DPIO_TX1_STAGGER_MULT(6) |
2965                        DPIO_TX2_STAGGER_MULT(0));
2966
2967         if (intel_crtc->config->lane_count > 2) {
2968                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
2969                                DPIO_LANESTAGGER_STRAP(stagger) |
2970                                DPIO_LANESTAGGER_STRAP_OVRD |
2971                                DPIO_TX1_STAGGER_MASK(0x1f) |
2972                                DPIO_TX1_STAGGER_MULT(7) |
2973                                DPIO_TX2_STAGGER_MULT(5));
2974         }
2975
2976         /* Deassert data lane reset */
2977         chv_data_lane_soft_reset(encoder, false);
2978
2979         mutex_unlock(&dev_priv->sb_lock);
2980
2981         intel_enable_dp(encoder);
2982
2983         /* Second common lane will stay alive on its own now */
2984         if (dport->release_cl2_override) {
2985                 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
2986                 dport->release_cl2_override = false;
2987         }
2988 }
2989
2990 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2991 {
2992         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2993         struct drm_device *dev = encoder->base.dev;
2994         struct drm_i915_private *dev_priv = dev->dev_private;
2995         struct intel_crtc *intel_crtc =
2996                 to_intel_crtc(encoder->base.crtc);
2997         enum dpio_channel ch = vlv_dport_to_channel(dport);
2998         enum pipe pipe = intel_crtc->pipe;
2999         unsigned int lane_mask =
3000                 intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
3001         u32 val;
3002
3003         intel_dp_prepare(encoder);
3004
3005         /*
3006          * Must trick the second common lane into life.
3007          * Otherwise we can't even access the PLL.
3008          */
3009         if (ch == DPIO_CH0 && pipe == PIPE_B)
3010                 dport->release_cl2_override =
3011                         !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
3012
3013         chv_phy_powergate_lanes(encoder, true, lane_mask);
3014
3015         mutex_lock(&dev_priv->sb_lock);
3016
3017         /* Assert data lane reset */
3018         chv_data_lane_soft_reset(encoder, true);
3019
3020         /* program left/right clock distribution */
3021         if (pipe != PIPE_B) {
3022                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3023                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3024                 if (ch == DPIO_CH0)
3025                         val |= CHV_BUFLEFTENA1_FORCE;
3026                 if (ch == DPIO_CH1)
3027                         val |= CHV_BUFRIGHTENA1_FORCE;
3028                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3029         } else {
3030                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3031                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3032                 if (ch == DPIO_CH0)
3033                         val |= CHV_BUFLEFTENA2_FORCE;
3034                 if (ch == DPIO_CH1)
3035                         val |= CHV_BUFRIGHTENA2_FORCE;
3036                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3037         }
3038
3039         /* program clock channel usage */
3040         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
3041         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3042         if (pipe != PIPE_B)
3043                 val &= ~CHV_PCS_USEDCLKCHANNEL;
3044         else
3045                 val |= CHV_PCS_USEDCLKCHANNEL;
3046         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
3047
3048         if (intel_crtc->config->lane_count > 2) {
3049                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
3050                 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3051                 if (pipe != PIPE_B)
3052                         val &= ~CHV_PCS_USEDCLKCHANNEL;
3053                 else
3054                         val |= CHV_PCS_USEDCLKCHANNEL;
3055                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
3056         }
3057
3058         /*
3059          * This a a bit weird since generally CL
3060          * matches the pipe, but here we need to
3061          * pick the CL based on the port.
3062          */
3063         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
3064         if (pipe != PIPE_B)
3065                 val &= ~CHV_CMN_USEDCLKCHANNEL;
3066         else
3067                 val |= CHV_CMN_USEDCLKCHANNEL;
3068         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
3069
3070         mutex_unlock(&dev_priv->sb_lock);
3071 }
3072
3073 static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
3074 {
3075         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3076         enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
3077         u32 val;
3078
3079         mutex_lock(&dev_priv->sb_lock);
3080
3081         /* disable left/right clock distribution */
3082         if (pipe != PIPE_B) {
3083                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3084                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3085                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3086         } else {
3087                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3088                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3089                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3090         }
3091
3092         mutex_unlock(&dev_priv->sb_lock);
3093
3094         /*
3095          * Leave the power down bit cleared for at least one
3096          * lane so that chv_powergate_phy_ch() will power
3097          * on something when the channel is otherwise unused.
3098          * When the port is off and the override is removed
3099          * the lanes power down anyway, so otherwise it doesn't
3100          * really matter what the state of power down bits is
3101          * after this.
3102          */
3103         chv_phy_powergate_lanes(encoder, false, 0x0);
3104 }
3105
3106 /*
3107  * Native read with retry for link status and receiver capability reads for
3108  * cases where the sink may still be asleep.
3109  *
3110  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
3111  * supposed to retry 3 times per the spec.
3112  */
3113 static ssize_t
3114 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
3115                         void *buffer, size_t size)
3116 {
3117         ssize_t ret;
3118         int i;
3119
3120         /*
3121          * Sometime we just get the same incorrect byte repeated
3122          * over the entire buffer. Doing just one throw away read
3123          * initially seems to "solve" it.
3124          */
3125         drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
3126
3127         for (i = 0; i < 3; i++) {
3128                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
3129                 if (ret == size)
3130                         return ret;
3131                 msleep(1);
3132         }
3133
3134         return ret;
3135 }
3136
3137 /*
3138  * Fetch AUX CH registers 0x202 - 0x207 which contain
3139  * link status information
3140  */
3141 bool
3142 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3143 {
3144         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3145                                        DP_LANE0_1_STATUS,
3146                                        link_status,
3147                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3148 }
3149
3150 /* These are source-specific values. */
3151 uint8_t
3152 intel_dp_voltage_max(struct intel_dp *intel_dp)
3153 {
3154         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3155         struct drm_i915_private *dev_priv = dev->dev_private;
3156         enum port port = dp_to_dig_port(intel_dp)->port;
3157
3158         if (IS_BROXTON(dev))
3159                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3160         else if (INTEL_INFO(dev)->gen >= 9) {
3161                 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
3162                         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3163                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3164         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3165                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3166         else if (IS_GEN7(dev) && port == PORT_A)
3167                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3168         else if (HAS_PCH_CPT(dev) && port != PORT_A)
3169                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3170         else
3171                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3172 }
3173
3174 uint8_t
3175 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3176 {
3177         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3178         enum port port = dp_to_dig_port(intel_dp)->port;
3179
3180         if (INTEL_INFO(dev)->gen >= 9) {
3181                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3182                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3183                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3184                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3185                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3186                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3187                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3188                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3189                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3190                 default:
3191                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3192                 }
3193         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3194                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3195                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3196                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3197                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3198                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3199                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3200                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3201                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3202                 default:
3203                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3204                 }
3205         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
3206                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3207                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3208                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3209                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3210                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3211                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3212                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3213                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3214                 default:
3215                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3216                 }
3217         } else if (IS_GEN7(dev) && port == PORT_A) {
3218                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3219                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3220                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3221                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3222                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3223                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3224                 default:
3225                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3226                 }
3227         } else {
3228                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3229                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3230                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3231                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3232                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3233                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3234                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3235                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3236                 default:
3237                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3238                 }
3239         }
3240 }
3241
3242 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3243 {
3244         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3245         struct drm_i915_private *dev_priv = dev->dev_private;
3246         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3247         struct intel_crtc *intel_crtc =
3248                 to_intel_crtc(dport->base.base.crtc);
3249         unsigned long demph_reg_value, preemph_reg_value,
3250                 uniqtranscale_reg_value;
3251         uint8_t train_set = intel_dp->train_set[0];
3252         enum dpio_channel port = vlv_dport_to_channel(dport);
3253         int pipe = intel_crtc->pipe;
3254
3255         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3256         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3257                 preemph_reg_value = 0x0004000;
3258                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3259                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3260                         demph_reg_value = 0x2B405555;
3261                         uniqtranscale_reg_value = 0x552AB83A;
3262                         break;
3263                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3264                         demph_reg_value = 0x2B404040;
3265                         uniqtranscale_reg_value = 0x5548B83A;
3266                         break;
3267                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3268                         demph_reg_value = 0x2B245555;
3269                         uniqtranscale_reg_value = 0x5560B83A;
3270                         break;
3271                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3272                         demph_reg_value = 0x2B405555;
3273                         uniqtranscale_reg_value = 0x5598DA3A;
3274                         break;
3275                 default:
3276                         return 0;
3277                 }
3278                 break;
3279         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3280                 preemph_reg_value = 0x0002000;
3281                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3282                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3283                         demph_reg_value = 0x2B404040;
3284                         uniqtranscale_reg_value = 0x5552B83A;
3285                         break;
3286                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3287                         demph_reg_value = 0x2B404848;
3288                         uniqtranscale_reg_value = 0x5580B83A;
3289                         break;
3290                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3291                         demph_reg_value = 0x2B404040;
3292                         uniqtranscale_reg_value = 0x55ADDA3A;
3293                         break;
3294                 default:
3295                         return 0;
3296                 }
3297                 break;
3298         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3299                 preemph_reg_value = 0x0000000;
3300                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3301                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3302                         demph_reg_value = 0x2B305555;
3303                         uniqtranscale_reg_value = 0x5570B83A;
3304                         break;
3305                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3306                         demph_reg_value = 0x2B2B4040;
3307                         uniqtranscale_reg_value = 0x55ADDA3A;
3308                         break;
3309                 default:
3310                         return 0;
3311                 }
3312                 break;
3313         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3314                 preemph_reg_value = 0x0006000;
3315                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3316                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3317                         demph_reg_value = 0x1B405555;
3318                         uniqtranscale_reg_value = 0x55ADDA3A;
3319                         break;
3320                 default:
3321                         return 0;
3322                 }
3323                 break;
3324         default:
3325                 return 0;
3326         }
3327
3328         mutex_lock(&dev_priv->sb_lock);
3329         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3330         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3331         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3332                          uniqtranscale_reg_value);
3333         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3334         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3335         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3336         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3337         mutex_unlock(&dev_priv->sb_lock);
3338
3339         return 0;
3340 }
3341
3342 static bool chv_need_uniq_trans_scale(uint8_t train_set)
3343 {
3344         return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
3345                 (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3346 }
3347
3348 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3349 {
3350         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3351         struct drm_i915_private *dev_priv = dev->dev_private;
3352         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3353         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3354         u32 deemph_reg_value, margin_reg_value, val;
3355         uint8_t train_set = intel_dp->train_set[0];
3356         enum dpio_channel ch = vlv_dport_to_channel(dport);
3357         enum pipe pipe = intel_crtc->pipe;
3358         int i;
3359
3360         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3361         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3362                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3363                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3364                         deemph_reg_value = 128;
3365                         margin_reg_value = 52;
3366                         break;
3367                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3368                         deemph_reg_value = 128;
3369                         margin_reg_value = 77;
3370                         break;
3371                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3372                         deemph_reg_value = 128;
3373                         margin_reg_value = 102;
3374                         break;
3375                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3376                         deemph_reg_value = 128;
3377                         margin_reg_value = 154;
3378                         /* FIXME extra to set for 1200 */
3379                         break;
3380                 default:
3381                         return 0;
3382                 }
3383                 break;
3384         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3385                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3386                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3387                         deemph_reg_value = 85;
3388                         margin_reg_value = 78;
3389                         break;
3390                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3391                         deemph_reg_value = 85;
3392                         margin_reg_value = 116;
3393                         break;
3394                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3395                         deemph_reg_value = 85;
3396                         margin_reg_value = 154;
3397                         break;
3398                 default:
3399                         return 0;
3400                 }
3401                 break;
3402         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3403                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3404                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3405                         deemph_reg_value = 64;
3406                         margin_reg_value = 104;
3407                         break;
3408                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3409                         deemph_reg_value = 64;
3410                         margin_reg_value = 154;
3411                         break;
3412                 default:
3413                         return 0;
3414                 }
3415                 break;
3416         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3417                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3418                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3419                         deemph_reg_value = 43;
3420                         margin_reg_value = 154;
3421                         break;
3422                 default:
3423                         return 0;
3424                 }
3425                 break;
3426         default:
3427                 return 0;
3428         }
3429
3430         mutex_lock(&dev_priv->sb_lock);
3431
3432         /* Clear calc init */
3433         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3434         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3435         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3436         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3437         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3438
3439         if (intel_crtc->config->lane_count > 2) {
3440                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3441                 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3442                 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3443                 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3444                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3445         }
3446
3447         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3448         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3449         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3450         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3451
3452         if (intel_crtc->config->lane_count > 2) {
3453                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3454                 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3455                 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3456                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3457         }
3458
3459         /* Program swing deemph */
3460         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3461                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3462                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3463                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3464                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3465         }
3466
3467         /* Program swing margin */
3468         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3469                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3470
3471                 val &= ~DPIO_SWING_MARGIN000_MASK;
3472                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3473
3474                 /*
3475                  * Supposedly this value shouldn't matter when unique transition
3476                  * scale is disabled, but in fact it does matter. Let's just
3477                  * always program the same value and hope it's OK.
3478                  */
3479                 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3480                 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
3481
3482                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3483         }
3484
3485         /*
3486          * The document said it needs to set bit 27 for ch0 and bit 26
3487          * for ch1. Might be a typo in the doc.
3488          * For now, for this unique transition scale selection, set bit
3489          * 27 for ch0 and ch1.
3490          */
3491         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3492                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3493                 if (chv_need_uniq_trans_scale(train_set))
3494                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3495                 else
3496                         val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3497                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3498         }
3499
3500         /* Start swing calculation */
3501         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3502         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3503         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3504
3505         if (intel_crtc->config->lane_count > 2) {
3506                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3507                 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3508                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3509         }
3510
3511         mutex_unlock(&dev_priv->sb_lock);
3512
3513         return 0;
3514 }
3515
3516 static uint32_t
3517 gen4_signal_levels(uint8_t train_set)
3518 {
3519         uint32_t        signal_levels = 0;
3520
3521         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3522         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3523         default:
3524                 signal_levels |= DP_VOLTAGE_0_4;
3525                 break;
3526         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3527                 signal_levels |= DP_VOLTAGE_0_6;
3528                 break;
3529         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3530                 signal_levels |= DP_VOLTAGE_0_8;
3531                 break;
3532         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3533                 signal_levels |= DP_VOLTAGE_1_2;
3534                 break;
3535         }
3536         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3537         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3538         default:
3539                 signal_levels |= DP_PRE_EMPHASIS_0;
3540                 break;
3541         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3542                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3543                 break;
3544         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3545                 signal_levels |= DP_PRE_EMPHASIS_6;
3546                 break;
3547         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3548                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3549                 break;
3550         }
3551         return signal_levels;
3552 }
3553
3554 /* Gen6's DP voltage swing and pre-emphasis control */
3555 static uint32_t
3556 gen6_edp_signal_levels(uint8_t train_set)
3557 {
3558         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3559                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3560         switch (signal_levels) {
3561         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3562         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3563                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3564         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3565                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3566         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3567         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3568                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3569         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3570         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3571                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3572         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3573         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3574                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3575         default:
3576                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3577                               "0x%x\n", signal_levels);
3578                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3579         }
3580 }
3581
3582 /* Gen7's DP voltage swing and pre-emphasis control */
3583 static uint32_t
3584 gen7_edp_signal_levels(uint8_t train_set)
3585 {
3586         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3587                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3588         switch (signal_levels) {
3589         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3590                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3591         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3592                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3593         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3594                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3595
3596         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3597                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3598         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3599                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3600
3601         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3602                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3603         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3604                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3605
3606         default:
3607                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3608                               "0x%x\n", signal_levels);
3609                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3610         }
3611 }
3612
3613 void
3614 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3615 {
3616         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3617         enum port port = intel_dig_port->port;
3618         struct drm_device *dev = intel_dig_port->base.base.dev;
3619         struct drm_i915_private *dev_priv = to_i915(dev);
3620         uint32_t signal_levels, mask = 0;
3621         uint8_t train_set = intel_dp->train_set[0];
3622
3623         if (HAS_DDI(dev)) {
3624                 signal_levels = ddi_signal_levels(intel_dp);
3625
3626                 if (IS_BROXTON(dev))
3627                         signal_levels = 0;
3628                 else
3629                         mask = DDI_BUF_EMP_MASK;
3630         } else if (IS_CHERRYVIEW(dev)) {
3631                 signal_levels = chv_signal_levels(intel_dp);
3632         } else if (IS_VALLEYVIEW(dev)) {
3633                 signal_levels = vlv_signal_levels(intel_dp);
3634         } else if (IS_GEN7(dev) && port == PORT_A) {
3635                 signal_levels = gen7_edp_signal_levels(train_set);
3636                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3637         } else if (IS_GEN6(dev) && port == PORT_A) {
3638                 signal_levels = gen6_edp_signal_levels(train_set);
3639                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3640         } else {
3641                 signal_levels = gen4_signal_levels(train_set);
3642                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3643         }
3644
3645         if (mask)
3646                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3647
3648         DRM_DEBUG_KMS("Using vswing level %d\n",
3649                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3650         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3651                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3652                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3653
3654         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3655
3656         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3657         POSTING_READ(intel_dp->output_reg);
3658 }
3659
3660 void
3661 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3662                                        uint8_t dp_train_pat)
3663 {
3664         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3665         struct drm_i915_private *dev_priv =
3666                 to_i915(intel_dig_port->base.base.dev);
3667
3668         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3669
3670         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3671         POSTING_READ(intel_dp->output_reg);
3672 }
3673
3674 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3675 {
3676         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3677         struct drm_device *dev = intel_dig_port->base.base.dev;
3678         struct drm_i915_private *dev_priv = dev->dev_private;
3679         enum port port = intel_dig_port->port;
3680         uint32_t val;
3681
3682         if (!HAS_DDI(dev))
3683                 return;
3684
3685         val = I915_READ(DP_TP_CTL(port));
3686         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3687         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3688         I915_WRITE(DP_TP_CTL(port), val);
3689
3690         /*
3691          * On PORT_A we can have only eDP in SST mode. There the only reason
3692          * we need to set idle transmission mode is to work around a HW issue
3693          * where we enable the pipe while not in idle link-training mode.
3694          * In this case there is requirement to wait for a minimum number of
3695          * idle patterns to be sent.
3696          */
3697         if (port == PORT_A)
3698                 return;
3699
3700         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3701                      1))
3702                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3703 }
3704
3705 static void
3706 intel_dp_link_down(struct intel_dp *intel_dp)
3707 {
3708         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3709         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3710         enum port port = intel_dig_port->port;
3711         struct drm_device *dev = intel_dig_port->base.base.dev;
3712         struct drm_i915_private *dev_priv = dev->dev_private;
3713         uint32_t DP = intel_dp->DP;
3714
3715         if (WARN_ON(HAS_DDI(dev)))
3716                 return;
3717
3718         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3719                 return;
3720
3721         DRM_DEBUG_KMS("\n");
3722
3723         if ((IS_GEN7(dev) && port == PORT_A) ||
3724             (HAS_PCH_CPT(dev) && port != PORT_A)) {
3725                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3726                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3727         } else {
3728                 if (IS_CHERRYVIEW(dev))
3729                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3730                 else
3731                         DP &= ~DP_LINK_TRAIN_MASK;
3732                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3733         }
3734         I915_WRITE(intel_dp->output_reg, DP);
3735         POSTING_READ(intel_dp->output_reg);
3736
3737         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3738         I915_WRITE(intel_dp->output_reg, DP);
3739         POSTING_READ(intel_dp->output_reg);
3740
3741         /*
3742          * HW workaround for IBX, we need to move the port
3743          * to transcoder A after disabling it to allow the
3744          * matching HDMI port to be enabled on transcoder A.
3745          */
3746         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3747                 /*
3748                  * We get CPU/PCH FIFO underruns on the other pipe when
3749                  * doing the workaround. Sweep them under the rug.
3750                  */
3751                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3752                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3753
3754                 /* always enable with pattern 1 (as per spec) */
3755                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3756                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3757                 I915_WRITE(intel_dp->output_reg, DP);
3758                 POSTING_READ(intel_dp->output_reg);
3759
3760                 DP &= ~DP_PORT_EN;
3761                 I915_WRITE(intel_dp->output_reg, DP);
3762                 POSTING_READ(intel_dp->output_reg);
3763
3764                 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3765                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3766                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3767         }
3768
3769         msleep(intel_dp->panel_power_down_delay);
3770
3771         intel_dp->DP = DP;
3772 }
3773
3774 static bool
3775 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3776 {
3777         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3778         struct drm_device *dev = dig_port->base.base.dev;
3779         struct drm_i915_private *dev_priv = dev->dev_private;
3780         uint8_t rev;
3781
3782         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3783                                     sizeof(intel_dp->dpcd)) < 0)
3784                 return false; /* aux transfer failed */
3785
3786         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3787
3788         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3789                 return false; /* DPCD not present */
3790
3791         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3792                                     &intel_dp->sink_count, 1) < 0)
3793                 return false;
3794
3795         /*
3796          * Sink count can change between short pulse hpd hence
3797          * a member variable in intel_dp will track any changes
3798          * between short pulse interrupts.
3799          */
3800         intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3801
3802         /*
3803          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3804          * a dongle is present but no display. Unless we require to know
3805          * if a dongle is present or not, we don't need to update
3806          * downstream port information. So, an early return here saves
3807          * time from performing other operations which are not required.
3808          */
3809         if (!intel_dp->sink_count)
3810                 return false;
3811
3812         /* Check if the panel supports PSR */
3813         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3814         if (is_edp(intel_dp)) {
3815                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3816                                         intel_dp->psr_dpcd,
3817                                         sizeof(intel_dp->psr_dpcd));
3818                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3819                         dev_priv->psr.sink_support = true;
3820                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3821                 }
3822
3823                 if (INTEL_INFO(dev)->gen >= 9 &&
3824                         (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3825                         uint8_t frame_sync_cap;
3826
3827                         dev_priv->psr.sink_support = true;
3828                         intel_dp_dpcd_read_wake(&intel_dp->aux,
3829                                         DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3830                                         &frame_sync_cap, 1);
3831                         dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3832                         /* PSR2 needs frame sync as well */
3833                         dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3834                         DRM_DEBUG_KMS("PSR2 %s on sink",
3835                                 dev_priv->psr.psr2_support ? "supported" : "not supported");
3836                 }
3837         }
3838
3839         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3840                       yesno(intel_dp_source_supports_hbr2(intel_dp)),
3841                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
3842
3843         /* Intermediate frequency support */
3844         if (is_edp(intel_dp) &&
3845             (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3846             (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3847             (rev >= 0x03)) { /* eDp v1.4 or higher */
3848                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3849                 int i;
3850
3851                 intel_dp_dpcd_read_wake(&intel_dp->aux,
3852                                 DP_SUPPORTED_LINK_RATES,
3853                                 sink_rates,
3854                                 sizeof(sink_rates));
3855
3856                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3857                         int val = le16_to_cpu(sink_rates[i]);
3858
3859                         if (val == 0)
3860                                 break;
3861
3862                         /* Value read is in kHz while drm clock is saved in deca-kHz */
3863                         intel_dp->sink_rates[i] = (val * 200) / 10;
3864                 }
3865                 intel_dp->num_sink_rates = i;
3866         }
3867
3868         intel_dp_print_rates(intel_dp);
3869
3870         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3871               DP_DWN_STRM_PORT_PRESENT))
3872                 return true; /* native DP sink */
3873
3874         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3875                 return true; /* no per-port downstream info */
3876
3877         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3878                                     intel_dp->downstream_ports,
3879                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3880                 return false; /* downstream port status fetch failed */
3881
3882         return true;
3883 }
3884
3885 static void
3886 intel_dp_probe_oui(struct intel_dp *intel_dp)
3887 {
3888         u8 buf[3];
3889
3890         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3891                 return;
3892
3893         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3894                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3895                               buf[0], buf[1], buf[2]);
3896
3897         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3898                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3899                               buf[0], buf[1], buf[2]);
3900 }
3901
3902 static bool
3903 intel_dp_probe_mst(struct intel_dp *intel_dp)
3904 {
3905         u8 buf[1];
3906
3907         if (!i915.enable_dp_mst)
3908                 return false;
3909
3910         if (!intel_dp->can_mst)
3911                 return false;
3912
3913         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3914                 return false;
3915
3916         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3917                 if (buf[0] & DP_MST_CAP) {
3918                         DRM_DEBUG_KMS("Sink is MST capable\n");
3919                         intel_dp->is_mst = true;
3920                 } else {
3921                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3922                         intel_dp->is_mst = false;
3923                 }
3924         }
3925
3926         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3927         return intel_dp->is_mst;
3928 }
3929
3930 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3931 {
3932         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3933         struct drm_device *dev = dig_port->base.base.dev;
3934         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3935         u8 buf;
3936         int ret = 0;
3937         int count = 0;
3938         int attempts = 10;
3939
3940         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3941                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3942                 ret = -EIO;
3943                 goto out;
3944         }
3945
3946         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3947                                buf & ~DP_TEST_SINK_START) < 0) {
3948                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3949                 ret = -EIO;
3950                 goto out;
3951         }
3952
3953         do {
3954                 intel_wait_for_vblank(dev, intel_crtc->pipe);
3955
3956                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3957                                       DP_TEST_SINK_MISC, &buf) < 0) {
3958                         ret = -EIO;
3959                         goto out;
3960                 }
3961                 count = buf & DP_TEST_COUNT_MASK;
3962         } while (--attempts && count);
3963
3964         if (attempts == 0) {
3965                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3966                 ret = -ETIMEDOUT;
3967         }
3968
3969  out:
3970         hsw_enable_ips(intel_crtc);
3971         return ret;
3972 }
3973
3974 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3975 {
3976         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3977         struct drm_device *dev = dig_port->base.base.dev;
3978         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3979         u8 buf;
3980         int ret;
3981
3982         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3983                 return -EIO;
3984
3985         if (!(buf & DP_TEST_CRC_SUPPORTED))
3986                 return -ENOTTY;
3987
3988         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3989                 return -EIO;
3990
3991         if (buf & DP_TEST_SINK_START) {
3992                 ret = intel_dp_sink_crc_stop(intel_dp);
3993                 if (ret)
3994                         return ret;
3995         }
3996
3997         hsw_disable_ips(intel_crtc);
3998
3999         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4000                                buf | DP_TEST_SINK_START) < 0) {
4001                 hsw_enable_ips(intel_crtc);
4002                 return -EIO;
4003         }
4004
4005         intel_wait_for_vblank(dev, intel_crtc->pipe);
4006         return 0;
4007 }
4008
4009 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
4010 {
4011         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4012         struct drm_device *dev = dig_port->base.base.dev;
4013         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4014         u8 buf;
4015         int count, ret;
4016         int attempts = 6;
4017
4018         ret = intel_dp_sink_crc_start(intel_dp);
4019         if (ret)
4020                 return ret;
4021
4022         do {
4023                 intel_wait_for_vblank(dev, intel_crtc->pipe);
4024
4025                 if (drm_dp_dpcd_readb(&intel_dp->aux,
4026                                       DP_TEST_SINK_MISC, &buf) < 0) {
4027                         ret = -EIO;
4028                         goto stop;
4029                 }
4030                 count = buf & DP_TEST_COUNT_MASK;
4031
4032         } while (--attempts && count == 0);
4033
4034         if (attempts == 0) {
4035                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4036                 ret = -ETIMEDOUT;
4037                 goto stop;
4038         }
4039
4040         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4041                 ret = -EIO;
4042                 goto stop;
4043         }
4044
4045 stop:
4046         intel_dp_sink_crc_stop(intel_dp);
4047         return ret;
4048 }
4049
4050 static bool
4051 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4052 {
4053         return intel_dp_dpcd_read_wake(&intel_dp->aux,
4054                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
4055                                        sink_irq_vector, 1) == 1;
4056 }
4057
4058 static bool
4059 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4060 {
4061         int ret;
4062
4063         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4064                                              DP_SINK_COUNT_ESI,
4065                                              sink_irq_vector, 14);
4066         if (ret != 14)
4067                 return false;
4068
4069         return true;
4070 }
4071
4072 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4073 {
4074         uint8_t test_result = DP_TEST_ACK;
4075         return test_result;
4076 }
4077
4078 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4079 {
4080         uint8_t test_result = DP_TEST_NAK;
4081         return test_result;
4082 }
4083
4084 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4085 {
4086         uint8_t test_result = DP_TEST_NAK;
4087         struct intel_connector *intel_connector = intel_dp->attached_connector;
4088         struct drm_connector *connector = &intel_connector->base;
4089
4090         if (intel_connector->detect_edid == NULL ||
4091             connector->edid_corrupt ||
4092             intel_dp->aux.i2c_defer_count > 6) {
4093                 /* Check EDID read for NACKs, DEFERs and corruption
4094                  * (DP CTS 1.2 Core r1.1)
4095                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4096                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4097                  *    4.2.2.6 : EDID corruption detected
4098                  * Use failsafe mode for all cases
4099                  */
4100                 if (intel_dp->aux.i2c_nack_count > 0 ||
4101                         intel_dp->aux.i2c_defer_count > 0)
4102                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4103                                       intel_dp->aux.i2c_nack_count,
4104                                       intel_dp->aux.i2c_defer_count);
4105                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4106         } else {
4107                 struct edid *block = intel_connector->detect_edid;
4108
4109                 /* We have to write the checksum
4110                  * of the last block read
4111                  */
4112                 block += intel_connector->detect_edid->extensions;
4113
4114                 if (!drm_dp_dpcd_write(&intel_dp->aux,
4115                                         DP_TEST_EDID_CHECKSUM,
4116                                         &block->checksum,
4117                                         1))
4118                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4119
4120                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4121                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4122         }
4123
4124         /* Set test active flag here so userspace doesn't interrupt things */
4125         intel_dp->compliance_test_active = 1;
4126
4127         return test_result;
4128 }
4129
4130 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4131 {
4132         uint8_t test_result = DP_TEST_NAK;
4133         return test_result;
4134 }
4135
4136 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4137 {
4138         uint8_t response = DP_TEST_NAK;
4139         uint8_t rxdata = 0;
4140         int status = 0;
4141
4142         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4143         if (status <= 0) {
4144                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4145                 goto update_status;
4146         }
4147
4148         switch (rxdata) {
4149         case DP_TEST_LINK_TRAINING:
4150                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4151                 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4152                 response = intel_dp_autotest_link_training(intel_dp);
4153                 break;
4154         case DP_TEST_LINK_VIDEO_PATTERN:
4155                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4156                 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4157                 response = intel_dp_autotest_video_pattern(intel_dp);
4158                 break;
4159         case DP_TEST_LINK_EDID_READ:
4160                 DRM_DEBUG_KMS("EDID test requested\n");
4161                 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4162                 response = intel_dp_autotest_edid(intel_dp);
4163                 break;
4164         case DP_TEST_LINK_PHY_TEST_PATTERN:
4165                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4166                 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4167                 response = intel_dp_autotest_phy_pattern(intel_dp);
4168                 break;
4169         default:
4170                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4171                 break;
4172         }
4173
4174 update_status:
4175         status = drm_dp_dpcd_write(&intel_dp->aux,
4176                                    DP_TEST_RESPONSE,
4177                                    &response, 1);
4178         if (status <= 0)
4179                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4180 }
4181
4182 static int
4183 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4184 {
4185         bool bret;
4186
4187         if (intel_dp->is_mst) {
4188                 u8 esi[16] = { 0 };
4189                 int ret = 0;
4190                 int retry;
4191                 bool handled;
4192                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4193 go_again:
4194                 if (bret == true) {
4195
4196                         /* check link status - esi[10] = 0x200c */
4197                         if (intel_dp->active_mst_links &&
4198                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4199                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4200                                 intel_dp_start_link_train(intel_dp);
4201                                 intel_dp_stop_link_train(intel_dp);
4202                         }
4203
4204                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4205                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4206
4207                         if (handled) {
4208                                 for (retry = 0; retry < 3; retry++) {
4209                                         int wret;
4210                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4211                                                                  DP_SINK_COUNT_ESI+1,
4212                                                                  &esi[1], 3);
4213                                         if (wret == 3) {
4214                                                 break;
4215                                         }
4216                                 }
4217
4218                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4219                                 if (bret == true) {
4220                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4221                                         goto go_again;
4222                                 }
4223                         } else
4224                                 ret = 0;
4225
4226                         return ret;
4227                 } else {
4228                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4229                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4230                         intel_dp->is_mst = false;
4231                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4232                         /* send a hotplug event */
4233                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4234                 }
4235         }
4236         return -EINVAL;
4237 }
4238
4239 static void
4240 intel_dp_check_link_status(struct intel_dp *intel_dp)
4241 {
4242         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4243         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4244         u8 link_status[DP_LINK_STATUS_SIZE];
4245
4246         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4247
4248         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4249                 DRM_ERROR("Failed to get link status\n");
4250                 return;
4251         }
4252
4253         if (!intel_encoder->base.crtc)
4254                 return;
4255
4256         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4257                 return;
4258
4259         /* if link training is requested we should perform it always */
4260         if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4261             (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4262                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4263                               intel_encoder->base.name);
4264                 intel_dp_start_link_train(intel_dp);
4265                 intel_dp_stop_link_train(intel_dp);
4266         }
4267 }
4268
4269 /*
4270  * According to DP spec
4271  * 5.1.2:
4272  *  1. Read DPCD
4273  *  2. Configure link according to Receiver Capabilities
4274  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4275  *  4. Check link status on receipt of hot-plug interrupt
4276  *
4277  * intel_dp_short_pulse -  handles short pulse interrupts
4278  * when full detection is not required.
4279  * Returns %true if short pulse is handled and full detection
4280  * is NOT required and %false otherwise.
4281  */
4282 static bool
4283 intel_dp_short_pulse(struct intel_dp *intel_dp)
4284 {
4285         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4286         u8 sink_irq_vector;
4287         u8 old_sink_count = intel_dp->sink_count;
4288         bool ret;
4289
4290         /*
4291          * Clearing compliance test variables to allow capturing
4292          * of values for next automated test request.
4293          */
4294         intel_dp->compliance_test_active = 0;
4295         intel_dp->compliance_test_type = 0;
4296         intel_dp->compliance_test_data = 0;
4297
4298         /*
4299          * Now read the DPCD to see if it's actually running
4300          * If the current value of sink count doesn't match with
4301          * the value that was stored earlier or dpcd read failed
4302          * we need to do full detection
4303          */
4304         ret = intel_dp_get_dpcd(intel_dp);
4305
4306         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4307                 /* No need to proceed if we are going to do full detect */
4308                 return false;
4309         }
4310
4311         /* Try to read the source of the interrupt */
4312         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4313             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4314                 /* Clear interrupt source */
4315                 drm_dp_dpcd_writeb(&intel_dp->aux,
4316                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4317                                    sink_irq_vector);
4318
4319                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4320                         DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4321                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4322                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4323         }
4324
4325         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4326         intel_dp_check_link_status(intel_dp);
4327         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4328
4329         return true;
4330 }
4331
4332 /* XXX this is probably wrong for multiple downstream ports */
4333 static enum drm_connector_status
4334 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4335 {
4336         uint8_t *dpcd = intel_dp->dpcd;
4337         uint8_t type;
4338
4339         if (!intel_dp_get_dpcd(intel_dp))
4340                 return connector_status_disconnected;
4341
4342         /* if there's no downstream port, we're done */
4343         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4344                 return connector_status_connected;
4345
4346         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4347         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4348             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4349
4350                 return intel_dp->sink_count ?
4351                 connector_status_connected : connector_status_disconnected;
4352         }
4353
4354         /* If no HPD, poke DDC gently */
4355         if (drm_probe_ddc(&intel_dp->aux.ddc))
4356                 return connector_status_connected;
4357
4358         /* Well we tried, say unknown for unreliable port types */
4359         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4360                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4361                 if (type == DP_DS_PORT_TYPE_VGA ||
4362                     type == DP_DS_PORT_TYPE_NON_EDID)
4363                         return connector_status_unknown;
4364         } else {
4365                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4366                         DP_DWN_STRM_PORT_TYPE_MASK;
4367                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4368                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4369                         return connector_status_unknown;
4370         }
4371
4372         /* Anything else is out of spec, warn and ignore */
4373         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4374         return connector_status_disconnected;
4375 }
4376
4377 static enum drm_connector_status
4378 edp_detect(struct intel_dp *intel_dp)
4379 {
4380         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4381         enum drm_connector_status status;
4382
4383         status = intel_panel_detect(dev);
4384         if (status == connector_status_unknown)
4385                 status = connector_status_connected;
4386
4387         return status;
4388 }
4389
4390 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4391                                        struct intel_digital_port *port)
4392 {
4393         u32 bit;
4394
4395         switch (port->port) {
4396         case PORT_A:
4397                 return true;
4398         case PORT_B:
4399                 bit = SDE_PORTB_HOTPLUG;
4400                 break;
4401         case PORT_C:
4402                 bit = SDE_PORTC_HOTPLUG;
4403                 break;
4404         case PORT_D:
4405                 bit = SDE_PORTD_HOTPLUG;
4406                 break;
4407         default:
4408                 MISSING_CASE(port->port);
4409                 return false;
4410         }
4411
4412         return I915_READ(SDEISR) & bit;
4413 }
4414
4415 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4416                                        struct intel_digital_port *port)
4417 {
4418         u32 bit;
4419
4420         switch (port->port) {
4421         case PORT_A:
4422                 return true;
4423         case PORT_B:
4424                 bit = SDE_PORTB_HOTPLUG_CPT;
4425                 break;
4426         case PORT_C:
4427                 bit = SDE_PORTC_HOTPLUG_CPT;
4428                 break;
4429         case PORT_D:
4430                 bit = SDE_PORTD_HOTPLUG_CPT;
4431                 break;
4432         case PORT_E:
4433                 bit = SDE_PORTE_HOTPLUG_SPT;
4434                 break;
4435         default:
4436                 MISSING_CASE(port->port);
4437                 return false;
4438         }
4439
4440         return I915_READ(SDEISR) & bit;
4441 }
4442
4443 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4444                                        struct intel_digital_port *port)
4445 {
4446         u32 bit;
4447
4448         switch (port->port) {
4449         case PORT_B:
4450                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4451                 break;
4452         case PORT_C:
4453                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4454                 break;
4455         case PORT_D:
4456                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4457                 break;
4458         default:
4459                 MISSING_CASE(port->port);
4460                 return false;
4461         }
4462
4463         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4464 }
4465
4466 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4467                                         struct intel_digital_port *port)
4468 {
4469         u32 bit;
4470
4471         switch (port->port) {
4472         case PORT_B:
4473                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4474                 break;
4475         case PORT_C:
4476                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4477                 break;
4478         case PORT_D:
4479                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4480                 break;
4481         default:
4482                 MISSING_CASE(port->port);
4483                 return false;
4484         }
4485
4486         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4487 }
4488
4489 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4490                                        struct intel_digital_port *intel_dig_port)
4491 {
4492         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4493         enum port port;
4494         u32 bit;
4495
4496         intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4497         switch (port) {
4498         case PORT_A:
4499                 bit = BXT_DE_PORT_HP_DDIA;
4500                 break;
4501         case PORT_B:
4502                 bit = BXT_DE_PORT_HP_DDIB;
4503                 break;
4504         case PORT_C:
4505                 bit = BXT_DE_PORT_HP_DDIC;
4506                 break;
4507         default:
4508                 MISSING_CASE(port);
4509                 return false;
4510         }
4511
4512         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4513 }
4514
4515 /*
4516  * intel_digital_port_connected - is the specified port connected?
4517  * @dev_priv: i915 private structure
4518  * @port: the port to test
4519  *
4520  * Return %true if @port is connected, %false otherwise.
4521  */
4522 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4523                                          struct intel_digital_port *port)
4524 {
4525         if (HAS_PCH_IBX(dev_priv))
4526                 return ibx_digital_port_connected(dev_priv, port);
4527         else if (HAS_PCH_SPLIT(dev_priv))
4528                 return cpt_digital_port_connected(dev_priv, port);
4529         else if (IS_BROXTON(dev_priv))
4530                 return bxt_digital_port_connected(dev_priv, port);
4531         else if (IS_GM45(dev_priv))
4532                 return gm45_digital_port_connected(dev_priv, port);
4533         else
4534                 return g4x_digital_port_connected(dev_priv, port);
4535 }
4536
4537 static struct edid *
4538 intel_dp_get_edid(struct intel_dp *intel_dp)
4539 {
4540         struct intel_connector *intel_connector = intel_dp->attached_connector;
4541
4542         /* use cached edid if we have one */
4543         if (intel_connector->edid) {
4544                 /* invalid edid */
4545                 if (IS_ERR(intel_connector->edid))
4546                         return NULL;
4547
4548                 return drm_edid_duplicate(intel_connector->edid);
4549         } else
4550                 return drm_get_edid(&intel_connector->base,
4551                                     &intel_dp->aux.ddc);
4552 }
4553
4554 static void
4555 intel_dp_set_edid(struct intel_dp *intel_dp)
4556 {
4557         struct intel_connector *intel_connector = intel_dp->attached_connector;
4558         struct edid *edid;
4559
4560         intel_dp_unset_edid(intel_dp);
4561         edid = intel_dp_get_edid(intel_dp);
4562         intel_connector->detect_edid = edid;
4563
4564         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4565                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4566         else
4567                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4568 }
4569
4570 static void
4571 intel_dp_unset_edid(struct intel_dp *intel_dp)
4572 {
4573         struct intel_connector *intel_connector = intel_dp->attached_connector;
4574
4575         kfree(intel_connector->detect_edid);
4576         intel_connector->detect_edid = NULL;
4577
4578         intel_dp->has_audio = false;
4579 }
4580
4581 static void
4582 intel_dp_long_pulse(struct intel_connector *intel_connector)
4583 {
4584         struct drm_connector *connector = &intel_connector->base;
4585         struct intel_dp *intel_dp = intel_attached_dp(connector);
4586         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4587         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4588         struct drm_device *dev = connector->dev;
4589         enum drm_connector_status status;
4590         enum intel_display_power_domain power_domain;
4591         bool ret;
4592         u8 sink_irq_vector;
4593
4594         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4595         intel_display_power_get(to_i915(dev), power_domain);
4596
4597         /* Can't disconnect eDP, but you can close the lid... */
4598         if (is_edp(intel_dp))
4599                 status = edp_detect(intel_dp);
4600         else if (intel_digital_port_connected(to_i915(dev),
4601                                               dp_to_dig_port(intel_dp)))
4602                 status = intel_dp_detect_dpcd(intel_dp);
4603         else
4604                 status = connector_status_disconnected;
4605
4606         if (status != connector_status_connected) {
4607                 intel_dp->compliance_test_active = 0;
4608                 intel_dp->compliance_test_type = 0;
4609                 intel_dp->compliance_test_data = 0;
4610
4611                 goto out;
4612         }
4613
4614         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4615                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4616
4617         intel_dp_probe_oui(intel_dp);
4618
4619         ret = intel_dp_probe_mst(intel_dp);
4620         if (ret) {
4621                 /*
4622                  * If we are in MST mode then this connector
4623                  * won't appear connected or have anything
4624                  * with EDID on it
4625                  */
4626                 status = connector_status_disconnected;
4627                 goto out;
4628         } else if (connector->status == connector_status_connected) {
4629                 /*
4630                  * If display was connected already and is still connected
4631                  * check links status, there has been known issues of
4632                  * link loss triggerring long pulse!!!!
4633                  */
4634                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4635                 intel_dp_check_link_status(intel_dp);
4636                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4637                 goto out;
4638         }
4639
4640         /*
4641          * Clearing NACK and defer counts to get their exact values
4642          * while reading EDID which are required by Compliance tests
4643          * 4.2.2.4 and 4.2.2.5
4644          */
4645         intel_dp->aux.i2c_nack_count = 0;
4646         intel_dp->aux.i2c_defer_count = 0;
4647
4648         intel_dp_set_edid(intel_dp);
4649
4650         status = connector_status_connected;
4651         intel_dp->detect_done = true;
4652
4653         /* Try to read the source of the interrupt */
4654         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4655             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4656                 /* Clear interrupt source */
4657                 drm_dp_dpcd_writeb(&intel_dp->aux,
4658                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4659                                    sink_irq_vector);
4660
4661                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4662                         intel_dp_handle_test_request(intel_dp);
4663                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4664                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4665         }
4666
4667 out:
4668         if (status != connector_status_connected) {
4669                 intel_dp_unset_edid(intel_dp);
4670                 /*
4671                  * If we were in MST mode, and device is not there,
4672                  * get out of MST mode
4673                  */
4674                 if (intel_dp->is_mst) {
4675                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4676                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4677                         intel_dp->is_mst = false;
4678                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4679                                                         intel_dp->is_mst);
4680                 }
4681         }
4682
4683         intel_display_power_put(to_i915(dev), power_domain);
4684         return;
4685 }
4686
4687 static enum drm_connector_status
4688 intel_dp_detect(struct drm_connector *connector, bool force)
4689 {
4690         struct intel_dp *intel_dp = intel_attached_dp(connector);
4691         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4692         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4693         struct intel_connector *intel_connector = to_intel_connector(connector);
4694
4695         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4696                       connector->base.id, connector->name);
4697
4698         if (intel_dp->is_mst) {
4699                 /* MST devices are disconnected from a monitor POV */
4700                 intel_dp_unset_edid(intel_dp);
4701                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4702                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4703                 return connector_status_disconnected;
4704         }
4705
4706         /* If full detect is not performed yet, do a full detect */
4707         if (!intel_dp->detect_done)
4708                 intel_dp_long_pulse(intel_dp->attached_connector);
4709
4710         intel_dp->detect_done = false;
4711
4712         if (intel_connector->detect_edid)
4713                 return connector_status_connected;
4714         else
4715                 return connector_status_disconnected;
4716 }
4717
4718 static void
4719 intel_dp_force(struct drm_connector *connector)
4720 {
4721         struct intel_dp *intel_dp = intel_attached_dp(connector);
4722         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4723         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4724         enum intel_display_power_domain power_domain;
4725
4726         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4727                       connector->base.id, connector->name);
4728         intel_dp_unset_edid(intel_dp);
4729
4730         if (connector->status != connector_status_connected)
4731                 return;
4732
4733         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4734         intel_display_power_get(dev_priv, power_domain);
4735
4736         intel_dp_set_edid(intel_dp);
4737
4738         intel_display_power_put(dev_priv, power_domain);
4739
4740         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4741                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4742 }
4743
4744 static int intel_dp_get_modes(struct drm_connector *connector)
4745 {
4746         struct intel_connector *intel_connector = to_intel_connector(connector);
4747         struct edid *edid;
4748
4749         edid = intel_connector->detect_edid;
4750         if (edid) {
4751                 int ret = intel_connector_update_modes(connector, edid);
4752                 if (ret)
4753                         return ret;
4754         }
4755
4756         /* if eDP has no EDID, fall back to fixed mode */
4757         if (is_edp(intel_attached_dp(connector)) &&
4758             intel_connector->panel.fixed_mode) {
4759                 struct drm_display_mode *mode;
4760
4761                 mode = drm_mode_duplicate(connector->dev,
4762                                           intel_connector->panel.fixed_mode);
4763                 if (mode) {
4764                         drm_mode_probed_add(connector, mode);
4765                         return 1;
4766                 }
4767         }
4768
4769         return 0;
4770 }
4771
4772 static bool
4773 intel_dp_detect_audio(struct drm_connector *connector)
4774 {
4775         bool has_audio = false;
4776         struct edid *edid;
4777
4778         edid = to_intel_connector(connector)->detect_edid;
4779         if (edid)
4780                 has_audio = drm_detect_monitor_audio(edid);
4781
4782         return has_audio;
4783 }
4784
4785 static int
4786 intel_dp_set_property(struct drm_connector *connector,
4787                       struct drm_property *property,
4788                       uint64_t val)
4789 {
4790         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4791         struct intel_connector *intel_connector = to_intel_connector(connector);
4792         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4793         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4794         int ret;
4795
4796         ret = drm_object_property_set_value(&connector->base, property, val);
4797         if (ret)
4798                 return ret;
4799
4800         if (property == dev_priv->force_audio_property) {
4801                 int i = val;
4802                 bool has_audio;
4803
4804                 if (i == intel_dp->force_audio)
4805                         return 0;
4806
4807                 intel_dp->force_audio = i;
4808
4809                 if (i == HDMI_AUDIO_AUTO)
4810                         has_audio = intel_dp_detect_audio(connector);
4811                 else
4812                         has_audio = (i == HDMI_AUDIO_ON);
4813
4814                 if (has_audio == intel_dp->has_audio)
4815                         return 0;
4816
4817                 intel_dp->has_audio = has_audio;
4818                 goto done;
4819         }
4820
4821         if (property == dev_priv->broadcast_rgb_property) {
4822                 bool old_auto = intel_dp->color_range_auto;
4823                 bool old_range = intel_dp->limited_color_range;
4824
4825                 switch (val) {
4826                 case INTEL_BROADCAST_RGB_AUTO:
4827                         intel_dp->color_range_auto = true;
4828                         break;
4829                 case INTEL_BROADCAST_RGB_FULL:
4830                         intel_dp->color_range_auto = false;
4831                         intel_dp->limited_color_range = false;
4832                         break;
4833                 case INTEL_BROADCAST_RGB_LIMITED:
4834                         intel_dp->color_range_auto = false;
4835                         intel_dp->limited_color_range = true;
4836                         break;
4837                 default:
4838                         return -EINVAL;
4839                 }
4840
4841                 if (old_auto == intel_dp->color_range_auto &&
4842                     old_range == intel_dp->limited_color_range)
4843                         return 0;
4844
4845                 goto done;
4846         }
4847
4848         if (is_edp(intel_dp) &&
4849             property == connector->dev->mode_config.scaling_mode_property) {
4850                 if (val == DRM_MODE_SCALE_NONE) {
4851                         DRM_DEBUG_KMS("no scaling not supported\n");
4852                         return -EINVAL;
4853                 }
4854
4855                 if (intel_connector->panel.fitting_mode == val) {
4856                         /* the eDP scaling property is not changed */
4857                         return 0;
4858                 }
4859                 intel_connector->panel.fitting_mode = val;
4860
4861                 goto done;
4862         }
4863
4864         return -EINVAL;
4865
4866 done:
4867         if (intel_encoder->base.crtc)
4868                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4869
4870         return 0;
4871 }
4872
4873 static void
4874 intel_dp_connector_destroy(struct drm_connector *connector)
4875 {
4876         struct intel_connector *intel_connector = to_intel_connector(connector);
4877
4878         kfree(intel_connector->detect_edid);
4879
4880         if (!IS_ERR_OR_NULL(intel_connector->edid))
4881                 kfree(intel_connector->edid);
4882
4883         /* Can't call is_edp() since the encoder may have been destroyed
4884          * already. */
4885         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4886                 intel_panel_fini(&intel_connector->panel);
4887
4888         drm_connector_cleanup(connector);
4889         kfree(connector);
4890 }
4891
4892 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4893 {
4894         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4895         struct intel_dp *intel_dp = &intel_dig_port->dp;
4896
4897         intel_dp_mst_encoder_cleanup(intel_dig_port);
4898         if (is_edp(intel_dp)) {
4899                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4900                 /*
4901                  * vdd might still be enabled do to the delayed vdd off.
4902                  * Make sure vdd is actually turned off here.
4903                  */
4904                 pps_lock(intel_dp);
4905                 edp_panel_vdd_off_sync(intel_dp);
4906                 pps_unlock(intel_dp);
4907
4908                 if (intel_dp->edp_notifier.notifier_call) {
4909                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4910                         intel_dp->edp_notifier.notifier_call = NULL;
4911                 }
4912         }
4913         drm_encoder_cleanup(encoder);
4914         kfree(intel_dig_port);
4915 }
4916
4917 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4918 {
4919         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4920
4921         if (!is_edp(intel_dp))
4922                 return;
4923
4924         /*
4925          * vdd might still be enabled do to the delayed vdd off.
4926          * Make sure vdd is actually turned off here.
4927          */
4928         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4929         pps_lock(intel_dp);
4930         edp_panel_vdd_off_sync(intel_dp);
4931         pps_unlock(intel_dp);
4932 }
4933
4934 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4935 {
4936         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4937         struct drm_device *dev = intel_dig_port->base.base.dev;
4938         struct drm_i915_private *dev_priv = dev->dev_private;
4939         enum intel_display_power_domain power_domain;
4940
4941         lockdep_assert_held(&dev_priv->pps_mutex);
4942
4943         if (!edp_have_panel_vdd(intel_dp))
4944                 return;
4945
4946         /*
4947          * The VDD bit needs a power domain reference, so if the bit is
4948          * already enabled when we boot or resume, grab this reference and
4949          * schedule a vdd off, so we don't hold on to the reference
4950          * indefinitely.
4951          */
4952         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4953         power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4954         intel_display_power_get(dev_priv, power_domain);
4955
4956         edp_panel_vdd_schedule_off(intel_dp);
4957 }
4958
4959 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4960 {
4961         struct intel_dp *intel_dp;
4962
4963         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4964                 return;
4965
4966         intel_dp = enc_to_intel_dp(encoder);
4967
4968         pps_lock(intel_dp);
4969
4970         /*
4971          * Read out the current power sequencer assignment,
4972          * in case the BIOS did something with it.
4973          */
4974         if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
4975                 vlv_initial_power_sequencer_setup(intel_dp);
4976
4977         intel_edp_panel_vdd_sanitize(intel_dp);
4978
4979         pps_unlock(intel_dp);
4980 }
4981
4982 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4983         .dpms = drm_atomic_helper_connector_dpms,
4984         .detect = intel_dp_detect,
4985         .force = intel_dp_force,
4986         .fill_modes = drm_helper_probe_single_connector_modes,
4987         .set_property = intel_dp_set_property,
4988         .atomic_get_property = intel_connector_atomic_get_property,
4989         .destroy = intel_dp_connector_destroy,
4990         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4991         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4992 };
4993
4994 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4995         .get_modes = intel_dp_get_modes,
4996         .mode_valid = intel_dp_mode_valid,
4997         .best_encoder = intel_best_encoder,
4998 };
4999
5000 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5001         .reset = intel_dp_encoder_reset,
5002         .destroy = intel_dp_encoder_destroy,
5003 };
5004
5005 enum irqreturn
5006 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5007 {
5008         struct intel_dp *intel_dp = &intel_dig_port->dp;
5009         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5010         struct drm_device *dev = intel_dig_port->base.base.dev;
5011         struct drm_i915_private *dev_priv = dev->dev_private;
5012         enum intel_display_power_domain power_domain;
5013         enum irqreturn ret = IRQ_NONE;
5014
5015         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
5016             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
5017                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
5018
5019         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5020                 /*
5021                  * vdd off can generate a long pulse on eDP which
5022                  * would require vdd on to handle it, and thus we
5023                  * would end up in an endless cycle of
5024                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5025                  */
5026                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5027                               port_name(intel_dig_port->port));
5028                 return IRQ_HANDLED;
5029         }
5030
5031         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5032                       port_name(intel_dig_port->port),
5033                       long_hpd ? "long" : "short");
5034
5035         power_domain = intel_display_port_aux_power_domain(intel_encoder);
5036         intel_display_power_get(dev_priv, power_domain);
5037
5038         if (long_hpd) {
5039                 /* indicate that we need to restart link training */
5040                 intel_dp->train_set_valid = false;
5041
5042                 intel_dp_long_pulse(intel_dp->attached_connector);
5043                 if (intel_dp->is_mst)
5044                         ret = IRQ_HANDLED;
5045                 goto put_power;
5046
5047         } else {
5048                 if (intel_dp->is_mst) {
5049                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5050                                 /*
5051                                  * If we were in MST mode, and device is not
5052                                  * there, get out of MST mode
5053                                  */
5054                                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5055                                               intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5056                                 intel_dp->is_mst = false;
5057                                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5058                                                                 intel_dp->is_mst);
5059                                 goto put_power;
5060                         }
5061                 }
5062
5063                 if (!intel_dp->is_mst) {
5064                         if (!intel_dp_short_pulse(intel_dp)) {
5065                                 intel_dp_long_pulse(intel_dp->attached_connector);
5066                                 goto put_power;
5067                         }
5068                 }
5069         }
5070
5071         ret = IRQ_HANDLED;
5072
5073 put_power:
5074         intel_display_power_put(dev_priv, power_domain);
5075
5076         return ret;
5077 }
5078
5079 /* check the VBT to see whether the eDP is on another port */
5080 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
5081 {
5082         struct drm_i915_private *dev_priv = dev->dev_private;
5083
5084         /*
5085          * eDP not supported on g4x. so bail out early just
5086          * for a bit extra safety in case the VBT is bonkers.
5087          */
5088         if (INTEL_INFO(dev)->gen < 5)
5089                 return false;
5090
5091         if (port == PORT_A)
5092                 return true;
5093
5094         return intel_bios_is_port_edp(dev_priv, port);
5095 }
5096
5097 void
5098 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5099 {
5100         struct intel_connector *intel_connector = to_intel_connector(connector);
5101
5102         intel_attach_force_audio_property(connector);
5103         intel_attach_broadcast_rgb_property(connector);
5104         intel_dp->color_range_auto = true;
5105
5106         if (is_edp(intel_dp)) {
5107                 drm_mode_create_scaling_mode_property(connector->dev);
5108                 drm_object_attach_property(
5109                         &connector->base,
5110                         connector->dev->mode_config.scaling_mode_property,
5111                         DRM_MODE_SCALE_ASPECT);
5112                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5113         }
5114 }
5115
5116 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5117 {
5118         intel_dp->panel_power_off_time = ktime_get_boottime();
5119         intel_dp->last_power_on = jiffies;
5120         intel_dp->last_backlight_off = jiffies;
5121 }
5122
5123 static void
5124 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5125                                     struct intel_dp *intel_dp)
5126 {
5127         struct drm_i915_private *dev_priv = dev->dev_private;
5128         struct edp_power_seq cur, vbt, spec,
5129                 *final = &intel_dp->pps_delays;
5130         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5131         i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
5132
5133         lockdep_assert_held(&dev_priv->pps_mutex);
5134
5135         /* already initialized? */
5136         if (final->t11_t12 != 0)
5137                 return;
5138
5139         if (IS_BROXTON(dev)) {
5140                 /*
5141                  * TODO: BXT has 2 sets of PPS registers.
5142                  * Correct Register for Broxton need to be identified
5143                  * using VBT. hardcoding for now
5144                  */
5145                 pp_ctrl_reg = BXT_PP_CONTROL(0);
5146                 pp_on_reg = BXT_PP_ON_DELAYS(0);
5147                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5148         } else if (HAS_PCH_SPLIT(dev)) {
5149                 pp_ctrl_reg = PCH_PP_CONTROL;
5150                 pp_on_reg = PCH_PP_ON_DELAYS;
5151                 pp_off_reg = PCH_PP_OFF_DELAYS;
5152                 pp_div_reg = PCH_PP_DIVISOR;
5153         } else {
5154                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5155
5156                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5157                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5158                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5159                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5160         }
5161
5162         /* Workaround: Need to write PP_CONTROL with the unlock key as
5163          * the very first thing. */
5164         pp_ctl = ironlake_get_pp_control(intel_dp);
5165
5166         pp_on = I915_READ(pp_on_reg);
5167         pp_off = I915_READ(pp_off_reg);
5168         if (!IS_BROXTON(dev)) {
5169                 I915_WRITE(pp_ctrl_reg, pp_ctl);
5170                 pp_div = I915_READ(pp_div_reg);
5171         }
5172
5173         /* Pull timing values out of registers */
5174         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5175                 PANEL_POWER_UP_DELAY_SHIFT;
5176
5177         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5178                 PANEL_LIGHT_ON_DELAY_SHIFT;
5179
5180         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5181                 PANEL_LIGHT_OFF_DELAY_SHIFT;
5182
5183         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5184                 PANEL_POWER_DOWN_DELAY_SHIFT;
5185
5186         if (IS_BROXTON(dev)) {
5187                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5188                         BXT_POWER_CYCLE_DELAY_SHIFT;
5189                 if (tmp > 0)
5190                         cur.t11_t12 = (tmp - 1) * 1000;
5191                 else
5192                         cur.t11_t12 = 0;
5193         } else {
5194                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5195                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5196         }
5197
5198         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5199                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5200
5201         vbt = dev_priv->vbt.edp.pps;
5202
5203         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5204          * our hw here, which are all in 100usec. */
5205         spec.t1_t3 = 210 * 10;
5206         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5207         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5208         spec.t10 = 500 * 10;
5209         /* This one is special and actually in units of 100ms, but zero
5210          * based in the hw (so we need to add 100 ms). But the sw vbt
5211          * table multiplies it with 1000 to make it in units of 100usec,
5212          * too. */
5213         spec.t11_t12 = (510 + 100) * 10;
5214
5215         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5216                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5217
5218         /* Use the max of the register settings and vbt. If both are
5219          * unset, fall back to the spec limits. */
5220 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5221                                        spec.field : \
5222                                        max(cur.field, vbt.field))
5223         assign_final(t1_t3);
5224         assign_final(t8);
5225         assign_final(t9);
5226         assign_final(t10);
5227         assign_final(t11_t12);
5228 #undef assign_final
5229
5230 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5231         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5232         intel_dp->backlight_on_delay = get_delay(t8);
5233         intel_dp->backlight_off_delay = get_delay(t9);
5234         intel_dp->panel_power_down_delay = get_delay(t10);
5235         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5236 #undef get_delay
5237
5238         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5239                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5240                       intel_dp->panel_power_cycle_delay);
5241
5242         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5243                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5244 }
5245
5246 static void
5247 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5248                                               struct intel_dp *intel_dp)
5249 {
5250         struct drm_i915_private *dev_priv = dev->dev_private;
5251         u32 pp_on, pp_off, pp_div, port_sel = 0;
5252         int div = dev_priv->rawclk_freq / 1000;
5253         i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg;
5254         enum port port = dp_to_dig_port(intel_dp)->port;
5255         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5256
5257         lockdep_assert_held(&dev_priv->pps_mutex);
5258
5259         if (IS_BROXTON(dev)) {
5260                 /*
5261                  * TODO: BXT has 2 sets of PPS registers.
5262                  * Correct Register for Broxton need to be identified
5263                  * using VBT. hardcoding for now
5264                  */
5265                 pp_ctrl_reg = BXT_PP_CONTROL(0);
5266                 pp_on_reg = BXT_PP_ON_DELAYS(0);
5267                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5268
5269         } else if (HAS_PCH_SPLIT(dev)) {
5270                 pp_on_reg = PCH_PP_ON_DELAYS;
5271                 pp_off_reg = PCH_PP_OFF_DELAYS;
5272                 pp_div_reg = PCH_PP_DIVISOR;
5273         } else {
5274                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5275
5276                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5277                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5278                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5279         }
5280
5281         /*
5282          * And finally store the new values in the power sequencer. The
5283          * backlight delays are set to 1 because we do manual waits on them. For
5284          * T8, even BSpec recommends doing it. For T9, if we don't do this,
5285          * we'll end up waiting for the backlight off delay twice: once when we
5286          * do the manual sleep, and once when we disable the panel and wait for
5287          * the PP_STATUS bit to become zero.
5288          */
5289         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5290                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5291         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5292                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5293         /* Compute the divisor for the pp clock, simply match the Bspec
5294          * formula. */
5295         if (IS_BROXTON(dev)) {
5296                 pp_div = I915_READ(pp_ctrl_reg);
5297                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5298                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5299                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5300         } else {
5301                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5302                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5303                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5304         }
5305
5306         /* Haswell doesn't have any port selection bits for the panel
5307          * power sequencer any more. */
5308         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5309                 port_sel = PANEL_PORT_SELECT_VLV(port);
5310         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5311                 if (port == PORT_A)
5312                         port_sel = PANEL_PORT_SELECT_DPA;
5313                 else
5314                         port_sel = PANEL_PORT_SELECT_DPD;
5315         }
5316
5317         pp_on |= port_sel;
5318
5319         I915_WRITE(pp_on_reg, pp_on);
5320         I915_WRITE(pp_off_reg, pp_off);
5321         if (IS_BROXTON(dev))
5322                 I915_WRITE(pp_ctrl_reg, pp_div);
5323         else
5324                 I915_WRITE(pp_div_reg, pp_div);
5325
5326         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5327                       I915_READ(pp_on_reg),
5328                       I915_READ(pp_off_reg),
5329                       IS_BROXTON(dev) ?
5330                       (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
5331                       I915_READ(pp_div_reg));
5332 }
5333
5334 /**
5335  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5336  * @dev: DRM device
5337  * @refresh_rate: RR to be programmed
5338  *
5339  * This function gets called when refresh rate (RR) has to be changed from
5340  * one frequency to another. Switches can be between high and low RR
5341  * supported by the panel or to any other RR based on media playback (in
5342  * this case, RR value needs to be passed from user space).
5343  *
5344  * The caller of this function needs to take a lock on dev_priv->drrs.
5345  */
5346 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5347 {
5348         struct drm_i915_private *dev_priv = dev->dev_private;
5349         struct intel_encoder *encoder;
5350         struct intel_digital_port *dig_port = NULL;
5351         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5352         struct intel_crtc_state *config = NULL;
5353         struct intel_crtc *intel_crtc = NULL;
5354         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5355
5356         if (refresh_rate <= 0) {
5357                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5358                 return;
5359         }
5360
5361         if (intel_dp == NULL) {
5362                 DRM_DEBUG_KMS("DRRS not supported.\n");
5363                 return;
5364         }
5365
5366         /*
5367          * FIXME: This needs proper synchronization with psr state for some
5368          * platforms that cannot have PSR and DRRS enabled at the same time.
5369          */
5370
5371         dig_port = dp_to_dig_port(intel_dp);
5372         encoder = &dig_port->base;
5373         intel_crtc = to_intel_crtc(encoder->base.crtc);
5374
5375         if (!intel_crtc) {
5376                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5377                 return;
5378         }
5379
5380         config = intel_crtc->config;
5381
5382         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5383                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5384                 return;
5385         }
5386
5387         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5388                         refresh_rate)
5389                 index = DRRS_LOW_RR;
5390
5391         if (index == dev_priv->drrs.refresh_rate_type) {
5392                 DRM_DEBUG_KMS(
5393                         "DRRS requested for previously set RR...ignoring\n");
5394                 return;
5395         }
5396
5397         if (!intel_crtc->active) {
5398                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5399                 return;
5400         }
5401
5402         if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5403                 switch (index) {
5404                 case DRRS_HIGH_RR:
5405                         intel_dp_set_m_n(intel_crtc, M1_N1);
5406                         break;
5407                 case DRRS_LOW_RR:
5408                         intel_dp_set_m_n(intel_crtc, M2_N2);
5409                         break;
5410                 case DRRS_MAX_RR:
5411                 default:
5412                         DRM_ERROR("Unsupported refreshrate type\n");
5413                 }
5414         } else if (INTEL_INFO(dev)->gen > 6) {
5415                 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5416                 u32 val;
5417
5418                 val = I915_READ(reg);
5419                 if (index > DRRS_HIGH_RR) {
5420                         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5421                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5422                         else
5423                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5424                 } else {
5425                         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5426                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5427                         else
5428                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5429                 }
5430                 I915_WRITE(reg, val);
5431         }
5432
5433         dev_priv->drrs.refresh_rate_type = index;
5434
5435         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5436 }
5437
5438 /**
5439  * intel_edp_drrs_enable - init drrs struct if supported
5440  * @intel_dp: DP struct
5441  *
5442  * Initializes frontbuffer_bits and drrs.dp
5443  */
5444 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5445 {
5446         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5447         struct drm_i915_private *dev_priv = dev->dev_private;
5448         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5449         struct drm_crtc *crtc = dig_port->base.base.crtc;
5450         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5451
5452         if (!intel_crtc->config->has_drrs) {
5453                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5454                 return;
5455         }
5456
5457         mutex_lock(&dev_priv->drrs.mutex);
5458         if (WARN_ON(dev_priv->drrs.dp)) {
5459                 DRM_ERROR("DRRS already enabled\n");
5460                 goto unlock;
5461         }
5462
5463         dev_priv->drrs.busy_frontbuffer_bits = 0;
5464
5465         dev_priv->drrs.dp = intel_dp;
5466
5467 unlock:
5468         mutex_unlock(&dev_priv->drrs.mutex);
5469 }
5470
5471 /**
5472  * intel_edp_drrs_disable - Disable DRRS
5473  * @intel_dp: DP struct
5474  *
5475  */
5476 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5477 {
5478         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5479         struct drm_i915_private *dev_priv = dev->dev_private;
5480         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5481         struct drm_crtc *crtc = dig_port->base.base.crtc;
5482         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5483
5484         if (!intel_crtc->config->has_drrs)
5485                 return;
5486
5487         mutex_lock(&dev_priv->drrs.mutex);
5488         if (!dev_priv->drrs.dp) {
5489                 mutex_unlock(&dev_priv->drrs.mutex);
5490                 return;
5491         }
5492
5493         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5494                 intel_dp_set_drrs_state(dev_priv->dev,
5495                         intel_dp->attached_connector->panel.
5496                         fixed_mode->vrefresh);
5497
5498         dev_priv->drrs.dp = NULL;
5499         mutex_unlock(&dev_priv->drrs.mutex);
5500
5501         cancel_delayed_work_sync(&dev_priv->drrs.work);
5502 }
5503
5504 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5505 {
5506         struct drm_i915_private *dev_priv =
5507                 container_of(work, typeof(*dev_priv), drrs.work.work);
5508         struct intel_dp *intel_dp;
5509
5510         mutex_lock(&dev_priv->drrs.mutex);
5511
5512         intel_dp = dev_priv->drrs.dp;
5513
5514         if (!intel_dp)
5515                 goto unlock;
5516
5517         /*
5518          * The delayed work can race with an invalidate hence we need to
5519          * recheck.
5520          */
5521
5522         if (dev_priv->drrs.busy_frontbuffer_bits)
5523                 goto unlock;
5524
5525         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5526                 intel_dp_set_drrs_state(dev_priv->dev,
5527                         intel_dp->attached_connector->panel.
5528                         downclock_mode->vrefresh);
5529
5530 unlock:
5531         mutex_unlock(&dev_priv->drrs.mutex);
5532 }
5533
5534 /**
5535  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5536  * @dev: DRM device
5537  * @frontbuffer_bits: frontbuffer plane tracking bits
5538  *
5539  * This function gets called everytime rendering on the given planes start.
5540  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5541  *
5542  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5543  */
5544 void intel_edp_drrs_invalidate(struct drm_device *dev,
5545                 unsigned frontbuffer_bits)
5546 {
5547         struct drm_i915_private *dev_priv = dev->dev_private;
5548         struct drm_crtc *crtc;
5549         enum pipe pipe;
5550
5551         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5552                 return;
5553
5554         cancel_delayed_work(&dev_priv->drrs.work);
5555
5556         mutex_lock(&dev_priv->drrs.mutex);
5557         if (!dev_priv->drrs.dp) {
5558                 mutex_unlock(&dev_priv->drrs.mutex);
5559                 return;
5560         }
5561
5562         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5563         pipe = to_intel_crtc(crtc)->pipe;
5564
5565         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5566         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5567
5568         /* invalidate means busy screen hence upclock */
5569         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5570                 intel_dp_set_drrs_state(dev_priv->dev,
5571                                 dev_priv->drrs.dp->attached_connector->panel.
5572                                 fixed_mode->vrefresh);
5573
5574         mutex_unlock(&dev_priv->drrs.mutex);
5575 }
5576
5577 /**
5578  * intel_edp_drrs_flush - Restart Idleness DRRS
5579  * @dev: DRM device
5580  * @frontbuffer_bits: frontbuffer plane tracking bits
5581  *
5582  * This function gets called every time rendering on the given planes has
5583  * completed or flip on a crtc is completed. So DRRS should be upclocked
5584  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5585  * if no other planes are dirty.
5586  *
5587  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5588  */
5589 void intel_edp_drrs_flush(struct drm_device *dev,
5590                 unsigned frontbuffer_bits)
5591 {
5592         struct drm_i915_private *dev_priv = dev->dev_private;
5593         struct drm_crtc *crtc;
5594         enum pipe pipe;
5595
5596         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5597                 return;
5598
5599         cancel_delayed_work(&dev_priv->drrs.work);
5600
5601         mutex_lock(&dev_priv->drrs.mutex);
5602         if (!dev_priv->drrs.dp) {
5603                 mutex_unlock(&dev_priv->drrs.mutex);
5604                 return;
5605         }
5606
5607         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5608         pipe = to_intel_crtc(crtc)->pipe;
5609
5610         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5611         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5612
5613         /* flush means busy screen hence upclock */
5614         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5615                 intel_dp_set_drrs_state(dev_priv->dev,
5616                                 dev_priv->drrs.dp->attached_connector->panel.
5617                                 fixed_mode->vrefresh);
5618
5619         /*
5620          * flush also means no more activity hence schedule downclock, if all
5621          * other fbs are quiescent too
5622          */
5623         if (!dev_priv->drrs.busy_frontbuffer_bits)
5624                 schedule_delayed_work(&dev_priv->drrs.work,
5625                                 msecs_to_jiffies(1000));
5626         mutex_unlock(&dev_priv->drrs.mutex);
5627 }
5628
5629 /**
5630  * DOC: Display Refresh Rate Switching (DRRS)
5631  *
5632  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5633  * which enables swtching between low and high refresh rates,
5634  * dynamically, based on the usage scenario. This feature is applicable
5635  * for internal panels.
5636  *
5637  * Indication that the panel supports DRRS is given by the panel EDID, which
5638  * would list multiple refresh rates for one resolution.
5639  *
5640  * DRRS is of 2 types - static and seamless.
5641  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5642  * (may appear as a blink on screen) and is used in dock-undock scenario.
5643  * Seamless DRRS involves changing RR without any visual effect to the user
5644  * and can be used during normal system usage. This is done by programming
5645  * certain registers.
5646  *
5647  * Support for static/seamless DRRS may be indicated in the VBT based on
5648  * inputs from the panel spec.
5649  *
5650  * DRRS saves power by switching to low RR based on usage scenarios.
5651  *
5652  * eDP DRRS:-
5653  *        The implementation is based on frontbuffer tracking implementation.
5654  * When there is a disturbance on the screen triggered by user activity or a
5655  * periodic system activity, DRRS is disabled (RR is changed to high RR).
5656  * When there is no movement on screen, after a timeout of 1 second, a switch
5657  * to low RR is made.
5658  *        For integration with frontbuffer tracking code,
5659  * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5660  *
5661  * DRRS can be further extended to support other internal panels and also
5662  * the scenario of video playback wherein RR is set based on the rate
5663  * requested by userspace.
5664  */
5665
5666 /**
5667  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5668  * @intel_connector: eDP connector
5669  * @fixed_mode: preferred mode of panel
5670  *
5671  * This function is  called only once at driver load to initialize basic
5672  * DRRS stuff.
5673  *
5674  * Returns:
5675  * Downclock mode if panel supports it, else return NULL.
5676  * DRRS support is determined by the presence of downclock mode (apart
5677  * from VBT setting).
5678  */
5679 static struct drm_display_mode *
5680 intel_dp_drrs_init(struct intel_connector *intel_connector,
5681                 struct drm_display_mode *fixed_mode)
5682 {
5683         struct drm_connector *connector = &intel_connector->base;
5684         struct drm_device *dev = connector->dev;
5685         struct drm_i915_private *dev_priv = dev->dev_private;
5686         struct drm_display_mode *downclock_mode = NULL;
5687
5688         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5689         mutex_init(&dev_priv->drrs.mutex);
5690
5691         if (INTEL_INFO(dev)->gen <= 6) {
5692                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5693                 return NULL;
5694         }
5695
5696         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5697                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5698                 return NULL;
5699         }
5700
5701         downclock_mode = intel_find_panel_downclock
5702                                         (dev, fixed_mode, connector);
5703
5704         if (!downclock_mode) {
5705                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5706                 return NULL;
5707         }
5708
5709         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5710
5711         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5712         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5713         return downclock_mode;
5714 }
5715
5716 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5717                                      struct intel_connector *intel_connector)
5718 {
5719         struct drm_connector *connector = &intel_connector->base;
5720         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5721         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5722         struct drm_device *dev = intel_encoder->base.dev;
5723         struct drm_i915_private *dev_priv = dev->dev_private;
5724         struct drm_display_mode *fixed_mode = NULL;
5725         struct drm_display_mode *downclock_mode = NULL;
5726         bool has_dpcd;
5727         struct drm_display_mode *scan;
5728         struct edid *edid;
5729         enum pipe pipe = INVALID_PIPE;
5730
5731         if (!is_edp(intel_dp))
5732                 return true;
5733
5734         pps_lock(intel_dp);
5735         intel_edp_panel_vdd_sanitize(intel_dp);
5736         pps_unlock(intel_dp);
5737
5738         /* Cache DPCD and EDID for edp. */
5739         has_dpcd = intel_dp_get_dpcd(intel_dp);
5740
5741         if (has_dpcd) {
5742                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5743                         dev_priv->no_aux_handshake =
5744                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5745                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5746         } else {
5747                 /* if this fails, presume the device is a ghost */
5748                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5749                 return false;
5750         }
5751
5752         /* We now know it's not a ghost, init power sequence regs. */
5753         pps_lock(intel_dp);
5754         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5755         pps_unlock(intel_dp);
5756
5757         mutex_lock(&dev->mode_config.mutex);
5758         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5759         if (edid) {
5760                 if (drm_add_edid_modes(connector, edid)) {
5761                         drm_mode_connector_update_edid_property(connector,
5762                                                                 edid);
5763                         drm_edid_to_eld(connector, edid);
5764                 } else {
5765                         kfree(edid);
5766                         edid = ERR_PTR(-EINVAL);
5767                 }
5768         } else {
5769                 edid = ERR_PTR(-ENOENT);
5770         }
5771         intel_connector->edid = edid;
5772
5773         /* prefer fixed mode from EDID if available */
5774         list_for_each_entry(scan, &connector->probed_modes, head) {
5775                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5776                         fixed_mode = drm_mode_duplicate(dev, scan);
5777                         downclock_mode = intel_dp_drrs_init(
5778                                                 intel_connector, fixed_mode);
5779                         break;
5780                 }
5781         }
5782
5783         /* fallback to VBT if available for eDP */
5784         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5785                 fixed_mode = drm_mode_duplicate(dev,
5786                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5787                 if (fixed_mode)
5788                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5789         }
5790         mutex_unlock(&dev->mode_config.mutex);
5791
5792         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5793                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5794                 register_reboot_notifier(&intel_dp->edp_notifier);
5795
5796                 /*
5797                  * Figure out the current pipe for the initial backlight setup.
5798                  * If the current pipe isn't valid, try the PPS pipe, and if that
5799                  * fails just assume pipe A.
5800                  */
5801                 if (IS_CHERRYVIEW(dev))
5802                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5803                 else
5804                         pipe = PORT_TO_PIPE(intel_dp->DP);
5805
5806                 if (pipe != PIPE_A && pipe != PIPE_B)
5807                         pipe = intel_dp->pps_pipe;
5808
5809                 if (pipe != PIPE_A && pipe != PIPE_B)
5810                         pipe = PIPE_A;
5811
5812                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5813                               pipe_name(pipe));
5814         }
5815
5816         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5817         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5818         intel_panel_setup_backlight(connector, pipe);
5819
5820         return true;
5821 }
5822
5823 bool
5824 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5825                         struct intel_connector *intel_connector)
5826 {
5827         struct drm_connector *connector = &intel_connector->base;
5828         struct intel_dp *intel_dp = &intel_dig_port->dp;
5829         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5830         struct drm_device *dev = intel_encoder->base.dev;
5831         struct drm_i915_private *dev_priv = dev->dev_private;
5832         enum port port = intel_dig_port->port;
5833         int type, ret;
5834
5835         if (WARN(intel_dig_port->max_lanes < 1,
5836                  "Not enough lanes (%d) for DP on port %c\n",
5837                  intel_dig_port->max_lanes, port_name(port)))
5838                 return false;
5839
5840         intel_dp->pps_pipe = INVALID_PIPE;
5841
5842         /* intel_dp vfuncs */
5843         if (INTEL_INFO(dev)->gen >= 9)
5844                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5845         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5846                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5847         else if (HAS_PCH_SPLIT(dev))
5848                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5849         else
5850                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5851
5852         if (INTEL_INFO(dev)->gen >= 9)
5853                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5854         else
5855                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5856
5857         if (HAS_DDI(dev))
5858                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5859
5860         /* Preserve the current hw state. */
5861         intel_dp->DP = I915_READ(intel_dp->output_reg);
5862         intel_dp->attached_connector = intel_connector;
5863
5864         if (intel_dp_is_edp(dev, port))
5865                 type = DRM_MODE_CONNECTOR_eDP;
5866         else
5867                 type = DRM_MODE_CONNECTOR_DisplayPort;
5868
5869         /*
5870          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5871          * for DP the encoder type can be set by the caller to
5872          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5873          */
5874         if (type == DRM_MODE_CONNECTOR_eDP)
5875                 intel_encoder->type = INTEL_OUTPUT_EDP;
5876
5877         /* eDP only on port B and/or C on vlv/chv */
5878         if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5879                     is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5880                 return false;
5881
5882         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5883                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5884                         port_name(port));
5885
5886         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5887         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5888
5889         connector->interlace_allowed = true;
5890         connector->doublescan_allowed = 0;
5891
5892         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5893                           edp_panel_vdd_work);
5894
5895         intel_connector_attach_encoder(intel_connector, intel_encoder);
5896         drm_connector_register(connector);
5897
5898         if (HAS_DDI(dev))
5899                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5900         else
5901                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5902         intel_connector->unregister = intel_dp_connector_unregister;
5903
5904         /* Set up the hotplug pin. */
5905         switch (port) {
5906         case PORT_A:
5907                 intel_encoder->hpd_pin = HPD_PORT_A;
5908                 break;
5909         case PORT_B:
5910                 intel_encoder->hpd_pin = HPD_PORT_B;
5911                 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
5912                         intel_encoder->hpd_pin = HPD_PORT_A;
5913                 break;
5914         case PORT_C:
5915                 intel_encoder->hpd_pin = HPD_PORT_C;
5916                 break;
5917         case PORT_D:
5918                 intel_encoder->hpd_pin = HPD_PORT_D;
5919                 break;
5920         case PORT_E:
5921                 intel_encoder->hpd_pin = HPD_PORT_E;
5922                 break;
5923         default:
5924                 BUG();
5925         }
5926
5927         if (is_edp(intel_dp)) {
5928                 pps_lock(intel_dp);
5929                 intel_dp_init_panel_power_timestamps(intel_dp);
5930                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5931                         vlv_initial_power_sequencer_setup(intel_dp);
5932                 else
5933                         intel_dp_init_panel_power_sequencer(dev, intel_dp);
5934                 pps_unlock(intel_dp);
5935         }
5936
5937         ret = intel_dp_aux_init(intel_dp, intel_connector);
5938         if (ret)
5939                 goto fail;
5940
5941         /* init MST on ports that can support it */
5942         if (HAS_DP_MST(dev) &&
5943             (port == PORT_B || port == PORT_C || port == PORT_D))
5944                 intel_dp_mst_encoder_init(intel_dig_port,
5945                                           intel_connector->base.base.id);
5946
5947         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5948                 intel_dp_aux_fini(intel_dp);
5949                 intel_dp_mst_encoder_cleanup(intel_dig_port);
5950                 goto fail;
5951         }
5952
5953         intel_dp_add_properties(intel_dp, connector);
5954
5955         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5956          * 0xd.  Failure to do so will result in spurious interrupts being
5957          * generated on the port when a cable is not attached.
5958          */
5959         if (IS_G4X(dev) && !IS_GM45(dev)) {
5960                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5961                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5962         }
5963
5964         i915_debugfs_connector_add(connector);
5965
5966         return true;
5967
5968 fail:
5969         if (is_edp(intel_dp)) {
5970                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5971                 /*
5972                  * vdd might still be enabled do to the delayed vdd off.
5973                  * Make sure vdd is actually turned off here.
5974                  */
5975                 pps_lock(intel_dp);
5976                 edp_panel_vdd_off_sync(intel_dp);
5977                 pps_unlock(intel_dp);
5978         }
5979         drm_connector_unregister(connector);
5980         drm_connector_cleanup(connector);
5981
5982         return false;
5983 }
5984
5985 void
5986 intel_dp_init(struct drm_device *dev,
5987               i915_reg_t output_reg, enum port port)
5988 {
5989         struct drm_i915_private *dev_priv = dev->dev_private;
5990         struct intel_digital_port *intel_dig_port;
5991         struct intel_encoder *intel_encoder;
5992         struct drm_encoder *encoder;
5993         struct intel_connector *intel_connector;
5994
5995         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5996         if (!intel_dig_port)
5997                 return;
5998
5999         intel_connector = intel_connector_alloc();
6000         if (!intel_connector)
6001                 goto err_connector_alloc;
6002
6003         intel_encoder = &intel_dig_port->base;
6004         encoder = &intel_encoder->base;
6005
6006         if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
6007                              DRM_MODE_ENCODER_TMDS, NULL))
6008                 goto err_encoder_init;
6009
6010         intel_encoder->compute_config = intel_dp_compute_config;
6011         intel_encoder->disable = intel_disable_dp;
6012         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6013         intel_encoder->get_config = intel_dp_get_config;
6014         intel_encoder->suspend = intel_dp_encoder_suspend;
6015         if (IS_CHERRYVIEW(dev)) {
6016                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6017                 intel_encoder->pre_enable = chv_pre_enable_dp;
6018                 intel_encoder->enable = vlv_enable_dp;
6019                 intel_encoder->post_disable = chv_post_disable_dp;
6020                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6021         } else if (IS_VALLEYVIEW(dev)) {
6022                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6023                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6024                 intel_encoder->enable = vlv_enable_dp;
6025                 intel_encoder->post_disable = vlv_post_disable_dp;
6026         } else {
6027                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6028                 intel_encoder->enable = g4x_enable_dp;
6029                 if (INTEL_INFO(dev)->gen >= 5)
6030                         intel_encoder->post_disable = ilk_post_disable_dp;
6031         }
6032
6033         intel_dig_port->port = port;
6034         intel_dig_port->dp.output_reg = output_reg;
6035         intel_dig_port->max_lanes = 4;
6036
6037         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
6038         if (IS_CHERRYVIEW(dev)) {
6039                 if (port == PORT_D)
6040                         intel_encoder->crtc_mask = 1 << 2;
6041                 else
6042                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6043         } else {
6044                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6045         }
6046         intel_encoder->cloneable = 0;
6047
6048         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6049         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6050
6051         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6052                 goto err_init_connector;
6053
6054         return;
6055
6056 err_init_connector:
6057         drm_encoder_cleanup(encoder);
6058 err_encoder_init:
6059         kfree(intel_connector);
6060 err_connector_alloc:
6061         kfree(intel_dig_port);
6062
6063         return;
6064 }
6065
6066 void intel_dp_mst_suspend(struct drm_device *dev)
6067 {
6068         struct drm_i915_private *dev_priv = dev->dev_private;
6069         int i;
6070
6071         /* disable MST */
6072         for (i = 0; i < I915_MAX_PORTS; i++) {
6073                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6074                 if (!intel_dig_port)
6075                         continue;
6076
6077                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6078                         if (!intel_dig_port->dp.can_mst)
6079                                 continue;
6080                         if (intel_dig_port->dp.is_mst)
6081                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6082                 }
6083         }
6084 }
6085
6086 void intel_dp_mst_resume(struct drm_device *dev)
6087 {
6088         struct drm_i915_private *dev_priv = dev->dev_private;
6089         int i;
6090
6091         for (i = 0; i < I915_MAX_PORTS; i++) {
6092                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6093                 if (!intel_dig_port)
6094                         continue;
6095                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6096                         int ret;
6097
6098                         if (!intel_dig_port->dp.can_mst)
6099                                 continue;
6100
6101                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6102                         if (ret != 0) {
6103                                 intel_dp_check_mst_status(&intel_dig_port->dp);
6104                         }
6105                 }
6106         }
6107 }