drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_edid.h>
  37 #include "intel_drv.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 struct dp_link_dpll {
  44         int link_bw;
  45         struct dpll dpll;
  46 };
  47
  48 static const struct dp_link_dpll gen4_dpll[] = {
  49         { DP_LINK_BW_1_62,
  50                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  51         { DP_LINK_BW_2_7,
  52                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  53 };
  54
  55 static const struct dp_link_dpll pch_dpll[] = {
  56         { DP_LINK_BW_1_62,
  57                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  58         { DP_LINK_BW_2_7,
  59                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  60 };
  61
  62 static const struct dp_link_dpll vlv_dpll[] = {
  63         { DP_LINK_BW_1_62,
  64                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  65         { DP_LINK_BW_2_7,
  66                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  67 };
  68
  69 /*
  70  * CHV supports eDP 1.4 that have  more link rates.
  71  * Below only provides the fixed rate but exclude variable rate.
  72  */
  73 static const struct dp_link_dpll chv_dpll[] = {
  74         /*
  75          * CHV requires to program fractional division for m2.
  76          * m2 is stored in fixed point format using formula below
  77          * (m2_int << 22) | m2_fraction
  78          */
  79         { DP_LINK_BW_1_62,      /* m2_int = 32, m2_fraction = 1677722 */
  80                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  81         { DP_LINK_BW_2_7,       /* m2_int = 27, m2_fraction = 0 */
  82                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  83         { DP_LINK_BW_5_4,       /* m2_int = 27, m2_fraction = 0 */
  84                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  85 };
  86
  87 /**
  88  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  89  * @intel_dp: DP struct
  90  *
  91  * If a CPU or PCH DP output is attached to an eDP panel, this function
  92  * will return true, and false otherwise.
  93  */
  94 static bool is_edp(struct intel_dp *intel_dp)
  95 {
  96         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  97
  98         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  99 }
 100
 101 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 102 {
 103         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 104
 105         return intel_dig_port->base.base.dev;
 106 }
 107
 108 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 109 {
 110         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 111 }
 112
 113 static void intel_dp_link_down(struct intel_dp *intel_dp);
 114 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 115 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 116
 117 int
 118 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 119 {
 120         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 121         struct drm_device *dev = intel_dp->attached_connector->base.dev;
 122
 123         switch (max_link_bw) {
 124         case DP_LINK_BW_1_62:
 125         case DP_LINK_BW_2_7:
 126                 break;
 127         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 128                 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
 129                      INTEL_INFO(dev)->gen >= 8) &&
 130                     intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
 131                         max_link_bw = DP_LINK_BW_5_4;
 132                 else
 133                         max_link_bw = DP_LINK_BW_2_7;
 134                 break;
 135         default:
 136                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 137                      max_link_bw);
 138                 max_link_bw = DP_LINK_BW_1_62;
 139                 break;
 140         }
 141         return max_link_bw;
 142 }
 143
 144 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 145 {
 146         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 147         struct drm_device *dev = intel_dig_port->base.base.dev;
 148         u8 source_max, sink_max;
 149
 150         source_max = 4;
 151         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 152             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 153                 source_max = 2;
 154
 155         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 156
 157         return min(source_max, sink_max);
 158 }
 159
 160 /*
 161  * The units on the numbers in the next two are... bizarre.  Examples will
 162  * make it clearer; this one parallels an example in the eDP spec.
 163  *
 164  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 165  *
 166  *     270000 * 1 * 8 / 10 == 216000
 167  *
 168  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 169  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 170  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 171  * 119000.  At 18bpp that's 2142000 kilobits per second.
 172  *
 173  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 174  * get the result in decakilobits instead of kilobits.
 175  */
 176
 177 static int
 178 intel_dp_link_required(int pixel_clock, int bpp)
 179 {
 180         return (pixel_clock * bpp + 9) / 10;
 181 }
 182
 183 static int
 184 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 185 {
 186         return (max_link_clock * max_lanes * 8) / 10;
 187 }
 188
 189 static enum drm_mode_status
 190 intel_dp_mode_valid(struct drm_connector *connector,
 191                     struct drm_display_mode *mode)
 192 {
 193         struct intel_dp *intel_dp = intel_attached_dp(connector);
 194         struct intel_connector *intel_connector = to_intel_connector(connector);
 195         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 196         int target_clock = mode->clock;
 197         int max_rate, mode_rate, max_lanes, max_link_clock;
 198
 199         if (is_edp(intel_dp) && fixed_mode) {
 200                 if (mode->hdisplay > fixed_mode->hdisplay)
 201                         return MODE_PANEL;
 202
 203                 if (mode->vdisplay > fixed_mode->vdisplay)
 204                         return MODE_PANEL;
 205
 206                 target_clock = fixed_mode->clock;
 207         }
 208
 209         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 210         max_lanes = intel_dp_max_lane_count(intel_dp);
 211
 212         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 213         mode_rate = intel_dp_link_required(target_clock, 18);
 214
 215         if (mode_rate > max_rate)
 216                 return MODE_CLOCK_HIGH;
 217
 218         if (mode->clock < 10000)
 219                 return MODE_CLOCK_LOW;
 220
 221         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 222                 return MODE_H_ILLEGAL;
 223
 224         return MODE_OK;
 225 }
 226
 227 static uint32_t
 228 pack_aux(uint8_t *src, int src_bytes)
 229 {
 230         int     i;
 231         uint32_t v = 0;
 232
 233         if (src_bytes > 4)
 234                 src_bytes = 4;
 235         for (i = 0; i < src_bytes; i++)
 236                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 237         return v;
 238 }
 239
 240 static void
 241 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 242 {
 243         int i;
 244         if (dst_bytes > 4)
 245                 dst_bytes = 4;
 246         for (i = 0; i < dst_bytes; i++)
 247                 dst[i] = src >> ((3-i) * 8);
 248 }
 249
 250 /* hrawclock is 1/4 the FSB frequency */
 251 static int
 252 intel_hrawclk(struct drm_device *dev)
 253 {
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255         uint32_t clkcfg;
 256
 257         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 258         if (IS_VALLEYVIEW(dev))
 259                 return 200;
 260
 261         clkcfg = I915_READ(CLKCFG);
 262         switch (clkcfg & CLKCFG_FSB_MASK) {
 263         case CLKCFG_FSB_400:
 264                 return 100;
 265         case CLKCFG_FSB_533:
 266                 return 133;
 267         case CLKCFG_FSB_667:
 268                 return 166;
 269         case CLKCFG_FSB_800:
 270                 return 200;
 271         case CLKCFG_FSB_1067:
 272                 return 266;
 273         case CLKCFG_FSB_1333:
 274                 return 333;
 275         /* these two are just a guess; one of them might be right */
 276         case CLKCFG_FSB_1600:
 277         case CLKCFG_FSB_1600_ALT:
 278                 return 400;
 279         default:
 280                 return 133;
 281         }
 282 }
 283
 284 static void
 285 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 286                                     struct intel_dp *intel_dp,
 287                                     struct edp_power_seq *out);
 288 static void
 289 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 290                                               struct intel_dp *intel_dp,
 291                                               struct edp_power_seq *out);
 292
 293 static enum pipe
 294 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 295 {
 296         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 297         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 298         struct drm_device *dev = intel_dig_port->base.base.dev;
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         enum port port = intel_dig_port->port;
 301         enum pipe pipe;
 302
 303         /* modeset should have pipe */
 304         if (crtc)
 305                 return to_intel_crtc(crtc)->pipe;
 306
 307         /* init time, try to find a pipe with this port selected */
 308         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 309                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 310                         PANEL_PORT_SELECT_MASK;
 311                 if (port_sel == PANEL_PORT_SELECT_VLV(port))
 312                         return pipe;
 313         }
 314
 315         /* shrug */
 316         return PIPE_A;
 317 }
 318
 319 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 320 {
 321         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 322
 323         if (HAS_PCH_SPLIT(dev))
 324                 return PCH_PP_CONTROL;
 325         else
 326                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 327 }
 328
 329 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 330 {
 331         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 332
 333         if (HAS_PCH_SPLIT(dev))
 334                 return PCH_PP_STATUS;
 335         else
 336                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 337 }
 338
 339 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 340    This function only applicable when panel PM state is not to be tracked */
 341 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 342                               void *unused)
 343 {
 344         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 345                                                  edp_notifier);
 346         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 347         struct drm_i915_private *dev_priv = dev->dev_private;
 348         u32 pp_div;
 349         u32 pp_ctrl_reg, pp_div_reg;
 350         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 351
 352         if (!is_edp(intel_dp) || code != SYS_RESTART)
 353                 return 0;
 354
 355         if (IS_VALLEYVIEW(dev)) {
 356                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 357                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 358                 pp_div = I915_READ(pp_div_reg);
 359                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 360
 361                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 362                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 363                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 364                 msleep(intel_dp->panel_power_cycle_delay);
 365         }
 366
 367         return 0;
 368 }
 369
 370 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 371 {
 372         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 373         struct drm_i915_private *dev_priv = dev->dev_private;
 374
 375         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 376 }
 377
 378 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 379 {
 380         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 383         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 384         enum intel_display_power_domain power_domain;
 385
 386         power_domain = intel_display_port_power_domain(intel_encoder);
 387         return intel_display_power_enabled(dev_priv, power_domain) &&
 388                (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 389 }
 390
 391 static void
 392 intel_dp_check_edp(struct intel_dp *intel_dp)
 393 {
 394         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 395         struct drm_i915_private *dev_priv = dev->dev_private;
 396
 397         if (!is_edp(intel_dp))
 398                 return;
 399
 400         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 401                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 402                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 403                               I915_READ(_pp_stat_reg(intel_dp)),
 404                               I915_READ(_pp_ctrl_reg(intel_dp)));
 405         }
 406 }
 407
 408 static uint32_t
 409 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 410 {
 411         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 412         struct drm_device *dev = intel_dig_port->base.base.dev;
 413         struct drm_i915_private *dev_priv = dev->dev_private;
 414         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 415         uint32_t status;
 416         bool done;
 417
 418 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 419         if (has_aux_irq)
 420                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 421                                           msecs_to_jiffies_timeout(10));
 422         else
 423                 done = wait_for_atomic(C, 10) == 0;
 424         if (!done)
 425                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 426                           has_aux_irq);
 427 #undef C
 428
 429         return status;
 430 }
 431
 432 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 433 {
 434         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 435         struct drm_device *dev = intel_dig_port->base.base.dev;
 436
 437         /*
 438          * The clock divider is based off the hrawclk, and would like to run at
 439          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 440          */
 441         return index ? 0 : intel_hrawclk(dev) / 2;
 442 }
 443
 444 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 445 {
 446         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 447         struct drm_device *dev = intel_dig_port->base.base.dev;
 448
 449         if (index)
 450                 return 0;
 451
 452         if (intel_dig_port->port == PORT_A) {
 453                 if (IS_GEN6(dev) || IS_GEN7(dev))
 454                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 455                 else
 456                         return 225; /* eDP input clock at 450Mhz */
 457         } else {
 458                 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 459         }
 460 }
 461
 462 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 463 {
 464         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 465         struct drm_device *dev = intel_dig_port->base.base.dev;
 466         struct drm_i915_private *dev_priv = dev->dev_private;
 467
 468         if (intel_dig_port->port == PORT_A) {
 469                 if (index)
 470                         return 0;
 471                 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 472         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 473                 /* Workaround for non-ULT HSW */
 474                 switch (index) {
 475                 case 0: return 63;
 476                 case 1: return 72;
 477                 default: return 0;
 478                 }
 479         } else  {
 480                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 481         }
 482 }
 483
 484 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 485 {
 486         return index ? 0 : 100;
 487 }
 488
 489 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 490                                       bool has_aux_irq,
 491                                       int send_bytes,
 492                                       uint32_t aux_clock_divider)
 493 {
 494         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 495         struct drm_device *dev = intel_dig_port->base.base.dev;
 496         uint32_t precharge, timeout;
 497
 498         if (IS_GEN6(dev))
 499                 precharge = 3;
 500         else
 501                 precharge = 5;
 502
 503         if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 504                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 505         else
 506                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 507
 508         return DP_AUX_CH_CTL_SEND_BUSY |
 509                DP_AUX_CH_CTL_DONE |
 510                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 511                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 512                timeout |
 513                DP_AUX_CH_CTL_RECEIVE_ERROR |
 514                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 515                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 516                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 517 }
 518
 519 static int
 520 intel_dp_aux_ch(struct intel_dp *intel_dp,
 521                 uint8_t *send, int send_bytes,
 522                 uint8_t *recv, int recv_size)
 523 {
 524         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 525         struct drm_device *dev = intel_dig_port->base.base.dev;
 526         struct drm_i915_private *dev_priv = dev->dev_private;
 527         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 528         uint32_t ch_data = ch_ctl + 4;
 529         uint32_t aux_clock_divider;
 530         int i, ret, recv_bytes;
 531         uint32_t status;
 532         int try, clock = 0;
 533         bool has_aux_irq = HAS_AUX_IRQ(dev);
 534         bool vdd;
 535
 536         /*
 537          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 538          * In such cases we want to leave VDD enabled and it's up to upper layers
 539          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 540          * ourselves.
 541          */
 542         vdd = edp_panel_vdd_on(intel_dp);
 543
 544         /* dp aux is extremely sensitive to irq latency, hence request the
 545          * lowest possible wakeup latency and so prevent the cpu from going into
 546          * deep sleep states.
 547          */
 548         pm_qos_update_request(&dev_priv->pm_qos, 0);
 549
 550         intel_dp_check_edp(intel_dp);
 551
 552         intel_aux_display_runtime_get(dev_priv);
 553
 554         /* Try to wait for any previous AUX channel activity */
 555         for (try = 0; try < 3; try++) {
 556                 status = I915_READ_NOTRACE(ch_ctl);
 557                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 558                         break;
 559                 msleep(1);
 560         }
 561
 562         if (try == 3) {
 563                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 564                      I915_READ(ch_ctl));
 565                 ret = -EBUSY;
 566                 goto out;
 567         }
 568
 569         /* Only 5 data registers! */
 570         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 571                 ret = -E2BIG;
 572                 goto out;
 573         }
 574
 575         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 576                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 577                                                           has_aux_irq,
 578                                                           send_bytes,
 579                                                           aux_clock_divider);
 580
 581                 /* Must try at least 3 times according to DP spec */
 582                 for (try = 0; try < 5; try++) {
 583                         /* Load the send data into the aux channel data registers */
 584                         for (i = 0; i < send_bytes; i += 4)
 585                                 I915_WRITE(ch_data + i,
 586                                            pack_aux(send + i, send_bytes - i));
 587
 588                         /* Send the command and wait for it to complete */
 589                         I915_WRITE(ch_ctl, send_ctl);
 590
 591                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 592
 593                         /* Clear done status and any errors */
 594                         I915_WRITE(ch_ctl,
 595                                    status |
 596                                    DP_AUX_CH_CTL_DONE |
 597                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 598                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 599
 600                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 601                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 602                                 continue;
 603                         if (status & DP_AUX_CH_CTL_DONE)
 604                                 break;
 605                 }
 606                 if (status & DP_AUX_CH_CTL_DONE)
 607                         break;
 608         }
 609
 610         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 611                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 612                 ret = -EBUSY;
 613                 goto out;
 614         }
 615
 616         /* Check for timeout or receive error.
 617          * Timeouts occur when the sink is not connected
 618          */
 619         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 620                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 621                 ret = -EIO;
 622                 goto out;
 623         }
 624
 625         /* Timeouts occur when the device isn't connected, so they're
 626          * "normal" -- don't fill the kernel log with these */
 627         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 628                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 629                 ret = -ETIMEDOUT;
 630                 goto out;
 631         }
 632
 633         /* Unload any bytes sent back from the other side */
 634         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 635                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 636         if (recv_bytes > recv_size)
 637                 recv_bytes = recv_size;
 638
 639         for (i = 0; i < recv_bytes; i += 4)
 640                 unpack_aux(I915_READ(ch_data + i),
 641                            recv + i, recv_bytes - i);
 642
 643         ret = recv_bytes;
 644 out:
 645         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 646         intel_aux_display_runtime_put(dev_priv);
 647
 648         if (vdd)
 649                 edp_panel_vdd_off(intel_dp, false);
 650
 651         return ret;
 652 }
 653
 654 #define BARE_ADDRESS_SIZE       3
 655 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 656 static ssize_t
 657 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 658 {
 659         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 660         uint8_t txbuf[20], rxbuf[20];
 661         size_t txsize, rxsize;
 662         int ret;
 663
 664         txbuf[0] = msg->request << 4;
 665         txbuf[1] = msg->address >> 8;
 666         txbuf[2] = msg->address & 0xff;
 667         txbuf[3] = msg->size - 1;
 668
 669         switch (msg->request & ~DP_AUX_I2C_MOT) {
 670         case DP_AUX_NATIVE_WRITE:
 671         case DP_AUX_I2C_WRITE:
 672                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 673                 rxsize = 1;
 674
 675                 if (WARN_ON(txsize > 20))
 676                         return -E2BIG;
 677
 678                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 679
 680                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 681                 if (ret > 0) {
 682                         msg->reply = rxbuf[0] >> 4;
 683
 684                         /* Return payload size. */
 685                         ret = msg->size;
 686                 }
 687                 break;
 688
 689         case DP_AUX_NATIVE_READ:
 690         case DP_AUX_I2C_READ:
 691                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 692                 rxsize = msg->size + 1;
 693
 694                 if (WARN_ON(rxsize > 20))
 695                         return -E2BIG;
 696
 697                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 698                 if (ret > 0) {
 699                         msg->reply = rxbuf[0] >> 4;
 700                         /*
 701                          * Assume happy day, and copy the data. The caller is
 702                          * expected to check msg->reply before touching it.
 703                          *
 704                          * Return payload size.
 705                          */
 706                         ret--;
 707                         memcpy(msg->buffer, rxbuf + 1, ret);
 708                 }
 709                 break;
 710
 711         default:
 712                 ret = -EINVAL;
 713                 break;
 714         }
 715
 716         return ret;
 717 }
 718
 719 static void
 720 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
 721 {
 722         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 723         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 724         enum port port = intel_dig_port->port;
 725         const char *name = NULL;
 726         int ret;
 727
 728         switch (port) {
 729         case PORT_A:
 730                 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
 731                 name = "DPDDC-A";
 732                 break;
 733         case PORT_B:
 734                 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
 735                 name = "DPDDC-B";
 736                 break;
 737         case PORT_C:
 738                 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
 739                 name = "DPDDC-C";
 740                 break;
 741         case PORT_D:
 742                 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
 743                 name = "DPDDC-D";
 744                 break;
 745         default:
 746                 BUG();
 747         }
 748
 749         if (!HAS_DDI(dev))
 750                 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
 751
 752         intel_dp->aux.name = name;
 753         intel_dp->aux.dev = dev->dev;
 754         intel_dp->aux.transfer = intel_dp_aux_transfer;
 755
 756         DRM_DEBUG_KMS("registering %s bus for %s\n", name,
 757                       connector->base.kdev->kobj.name);
 758
 759         ret = drm_dp_aux_register(&intel_dp->aux);
 760         if (ret < 0) {
 761                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
 762                           name, ret);
 763                 return;
 764         }
 765
 766         ret = sysfs_create_link(&connector->base.kdev->kobj,
 767                                 &intel_dp->aux.ddc.dev.kobj,
 768                                 intel_dp->aux.ddc.dev.kobj.name);
 769         if (ret < 0) {
 770                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
 771                 drm_dp_aux_unregister(&intel_dp->aux);
 772         }
 773 }
 774
 775 static void
 776 intel_dp_connector_unregister(struct intel_connector *intel_connector)
 777 {
 778         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
 779
 780         if (!intel_connector->mst_port)
 781                 sysfs_remove_link(&intel_connector->base.kdev->kobj,
 782                                   intel_dp->aux.ddc.dev.kobj.name);
 783         intel_connector_unregister(intel_connector);
 784 }
 785
 786 static void
 787 hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
 788 {
 789         switch (link_bw) {
 790         case DP_LINK_BW_1_62:
 791                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 792                 break;
 793         case DP_LINK_BW_2_7:
 794                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 795                 break;
 796         case DP_LINK_BW_5_4:
 797                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 798                 break;
 799         }
 800 }
 801
 802 static void
 803 intel_dp_set_clock(struct intel_encoder *encoder,
 804                    struct intel_crtc_config *pipe_config, int link_bw)
 805 {
 806         struct drm_device *dev = encoder->base.dev;
 807         const struct dp_link_dpll *divisor = NULL;
 808         int i, count = 0;
 809
 810         if (IS_G4X(dev)) {
 811                 divisor = gen4_dpll;
 812                 count = ARRAY_SIZE(gen4_dpll);
 813         } else if (HAS_PCH_SPLIT(dev)) {
 814                 divisor = pch_dpll;
 815                 count = ARRAY_SIZE(pch_dpll);
 816         } else if (IS_CHERRYVIEW(dev)) {
 817                 divisor = chv_dpll;
 818                 count = ARRAY_SIZE(chv_dpll);
 819         } else if (IS_VALLEYVIEW(dev)) {
 820                 divisor = vlv_dpll;
 821                 count = ARRAY_SIZE(vlv_dpll);
 822         }
 823
 824         if (divisor && count) {
 825                 for (i = 0; i < count; i++) {
 826                         if (link_bw == divisor[i].link_bw) {
 827                                 pipe_config->dpll = divisor[i].dpll;
 828                                 pipe_config->clock_set = true;
 829                                 break;
 830                         }
 831                 }
 832         }
 833 }
 834
 835 bool
 836 intel_dp_compute_config(struct intel_encoder *encoder,
 837                         struct intel_crtc_config *pipe_config)
 838 {
 839         struct drm_device *dev = encoder->base.dev;
 840         struct drm_i915_private *dev_priv = dev->dev_private;
 841         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 842         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 843         enum port port = dp_to_dig_port(intel_dp)->port;
 844         struct intel_crtc *intel_crtc = encoder->new_crtc;
 845         struct intel_connector *intel_connector = intel_dp->attached_connector;
 846         int lane_count, clock;
 847         int min_lane_count = 1;
 848         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 849         /* Conveniently, the link BW constants become indices with a shift...*/
 850         int min_clock = 0;
 851         int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
 852         int bpp, mode_rate;
 853         static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
 854         int link_avail, link_clock;
 855
 856         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 857                 pipe_config->has_pch_encoder = true;
 858
 859         pipe_config->has_dp_encoder = true;
 860         pipe_config->has_drrs = false;
 861         pipe_config->has_audio = intel_dp->has_audio;
 862
 863         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 864                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 865                                        adjusted_mode);
 866                 if (!HAS_PCH_SPLIT(dev))
 867                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 868                                                  intel_connector->panel.fitting_mode);
 869                 else
 870                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 871                                                 intel_connector->panel.fitting_mode);
 872         }
 873
 874         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 875                 return false;
 876
 877         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 878                       "max bw %02x pixel clock %iKHz\n",
 879                       max_lane_count, bws[max_clock],
 880                       adjusted_mode->crtc_clock);
 881
 882         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 883          * bpc in between. */
 884         bpp = pipe_config->pipe_bpp;
 885         if (is_edp(intel_dp)) {
 886                 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
 887                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 888                                       dev_priv->vbt.edp_bpp);
 889                         bpp = dev_priv->vbt.edp_bpp;
 890                 }
 891
 892                 if (IS_BROADWELL(dev)) {
 893                         /* Yes, it's an ugly hack. */
 894                         min_lane_count = max_lane_count;
 895                         DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
 896                                       min_lane_count);
 897                 } else if (dev_priv->vbt.edp_lanes) {
 898                         min_lane_count = min(dev_priv->vbt.edp_lanes,
 899                                              max_lane_count);
 900                         DRM_DEBUG_KMS("using min %u lanes per VBT\n",
 901                                       min_lane_count);
 902                 }
 903
 904                 if (dev_priv->vbt.edp_rate) {
 905                         min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
 906                         DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
 907                                       bws[min_clock]);
 908                 }
 909         }
 910
 911         for (; bpp >= 6*3; bpp -= 2*3) {
 912                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 913                                                    bpp);
 914
 915                 for (clock = min_clock; clock <= max_clock; clock++) {
 916                         for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
 917                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 918                                 link_avail = intel_dp_max_data_rate(link_clock,
 919                                                                     lane_count);
 920
 921                                 if (mode_rate <= link_avail) {
 922                                         goto found;
 923                                 }
 924                         }
 925                 }
 926         }
 927
 928         return false;
 929
 930 found:
 931         if (intel_dp->color_range_auto) {
 932                 /*
 933                  * See:
 934                  * CEA-861-E - 5.1 Default Encoding Parameters
 935                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 936                  */
 937                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 938                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 939                 else
 940                         intel_dp->color_range = 0;
 941         }
 942
 943         if (intel_dp->color_range)
 944                 pipe_config->limited_color_range = true;
 945
 946         intel_dp->link_bw = bws[clock];
 947         intel_dp->lane_count = lane_count;
 948         pipe_config->pipe_bpp = bpp;
 949         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 950
 951         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 952                       intel_dp->link_bw, intel_dp->lane_count,
 953                       pipe_config->port_clock, bpp);
 954         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 955                       mode_rate, link_avail);
 956
 957         intel_link_compute_m_n(bpp, lane_count,
 958                                adjusted_mode->crtc_clock,
 959                                pipe_config->port_clock,
 960                                &pipe_config->dp_m_n);
 961
 962         if (intel_connector->panel.downclock_mode != NULL &&
 963                 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
 964                         pipe_config->has_drrs = true;
 965                         intel_link_compute_m_n(bpp, lane_count,
 966                                 intel_connector->panel.downclock_mode->clock,
 967                                 pipe_config->port_clock,
 968                                 &pipe_config->dp_m2_n2);
 969         }
 970
 971         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 972                 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
 973         else
 974                 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 975
 976         return true;
 977 }
 978
 979 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 980 {
 981         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 982         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 983         struct drm_device *dev = crtc->base.dev;
 984         struct drm_i915_private *dev_priv = dev->dev_private;
 985         u32 dpa_ctl;
 986
 987         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 988         dpa_ctl = I915_READ(DP_A);
 989         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 990
 991         if (crtc->config.port_clock == 162000) {
 992                 /* For a long time we've carried around a ILK-DevA w/a for the
 993                  * 160MHz clock. If we're really unlucky, it's still required.
 994                  */
 995                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 996                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 997                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 998         } else {
 999                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1000                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1001         }
1002
1003         I915_WRITE(DP_A, dpa_ctl);
1004
1005         POSTING_READ(DP_A);
1006         udelay(500);
1007 }
1008
1009 static void intel_dp_prepare(struct intel_encoder *encoder)
1010 {
1011         struct drm_device *dev = encoder->base.dev;
1012         struct drm_i915_private *dev_priv = dev->dev_private;
1013         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1014         enum port port = dp_to_dig_port(intel_dp)->port;
1015         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1016         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1017
1018         /*
1019          * There are four kinds of DP registers:
1020          *
1021          *      IBX PCH
1022          *      SNB CPU
1023          *      IVB CPU
1024          *      CPT PCH
1025          *
1026          * IBX PCH and CPU are the same for almost everything,
1027          * except that the CPU DP PLL is configured in this
1028          * register
1029          *
1030          * CPT PCH is quite different, having many bits moved
1031          * to the TRANS_DP_CTL register instead. That
1032          * configuration happens (oddly) in ironlake_pch_enable
1033          */
1034
1035         /* Preserve the BIOS-computed detected bit. This is
1036          * supposed to be read-only.
1037          */
1038         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1039
1040         /* Handle DP bits in common between all three register formats */
1041         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1042         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1043
1044         if (crtc->config.has_audio) {
1045                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1046                                  pipe_name(crtc->pipe));
1047                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1048                 intel_write_eld(&encoder->base, adjusted_mode);
1049         }
1050
1051         /* Split out the IBX/CPU vs CPT settings */
1052
1053         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1054                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1055                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1056                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1057                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1058                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1059
1060                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1061                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1062
1063                 intel_dp->DP |= crtc->pipe << 29;
1064         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1065                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1066                         intel_dp->DP |= intel_dp->color_range;
1067
1068                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1069                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1070                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1071                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1072                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1073
1074                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1075                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1076
1077                 if (!IS_CHERRYVIEW(dev)) {
1078                         if (crtc->pipe == 1)
1079                                 intel_dp->DP |= DP_PIPEB_SELECT;
1080                 } else {
1081                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1082                 }
1083         } else {
1084                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1085         }
1086 }
1087
1088 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1089 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1090
1091 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1092 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1093
1094 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1095 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1096
1097 static void wait_panel_status(struct intel_dp *intel_dp,
1098                                        u32 mask,
1099                                        u32 value)
1100 {
1101         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1102         struct drm_i915_private *dev_priv = dev->dev_private;
1103         u32 pp_stat_reg, pp_ctrl_reg;
1104
1105         pp_stat_reg = _pp_stat_reg(intel_dp);
1106         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1107
1108         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1109                         mask, value,
1110                         I915_READ(pp_stat_reg),
1111                         I915_READ(pp_ctrl_reg));
1112
1113         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1114                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1115                                 I915_READ(pp_stat_reg),
1116                                 I915_READ(pp_ctrl_reg));
1117         }
1118
1119         DRM_DEBUG_KMS("Wait complete\n");
1120 }
1121
1122 static void wait_panel_on(struct intel_dp *intel_dp)
1123 {
1124         DRM_DEBUG_KMS("Wait for panel power on\n");
1125         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1126 }
1127
1128 static void wait_panel_off(struct intel_dp *intel_dp)
1129 {
1130         DRM_DEBUG_KMS("Wait for panel power off time\n");
1131         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1132 }
1133
1134 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1135 {
1136         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1137
1138         /* When we disable the VDD override bit last we have to do the manual
1139          * wait. */
1140         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1141                                        intel_dp->panel_power_cycle_delay);
1142
1143         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1144 }
1145
1146 static void wait_backlight_on(struct intel_dp *intel_dp)
1147 {
1148         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1149                                        intel_dp->backlight_on_delay);
1150 }
1151
1152 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1153 {
1154         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1155                                        intel_dp->backlight_off_delay);
1156 }
1157
1158 /* Read the current pp_control value, unlocking the register if it
1159  * is locked
1160  */
1161
1162 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1163 {
1164         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1165         struct drm_i915_private *dev_priv = dev->dev_private;
1166         u32 control;
1167
1168         control = I915_READ(_pp_ctrl_reg(intel_dp));
1169         control &= ~PANEL_UNLOCK_MASK;
1170         control |= PANEL_UNLOCK_REGS;
1171         return control;
1172 }
1173
1174 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1175 {
1176         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1177         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1178         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1179         struct drm_i915_private *dev_priv = dev->dev_private;
1180         enum intel_display_power_domain power_domain;
1181         u32 pp;
1182         u32 pp_stat_reg, pp_ctrl_reg;
1183         bool need_to_disable = !intel_dp->want_panel_vdd;
1184
1185         if (!is_edp(intel_dp))
1186                 return false;
1187
1188         intel_dp->want_panel_vdd = true;
1189
1190         if (edp_have_panel_vdd(intel_dp))
1191                 return need_to_disable;
1192
1193         power_domain = intel_display_port_power_domain(intel_encoder);
1194         intel_display_power_get(dev_priv, power_domain);
1195
1196         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1197
1198         if (!edp_have_panel_power(intel_dp))
1199                 wait_panel_power_cycle(intel_dp);
1200
1201         pp = ironlake_get_pp_control(intel_dp);
1202         pp |= EDP_FORCE_VDD;
1203
1204         pp_stat_reg = _pp_stat_reg(intel_dp);
1205         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1206
1207         I915_WRITE(pp_ctrl_reg, pp);
1208         POSTING_READ(pp_ctrl_reg);
1209         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1210                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1211         /*
1212          * If the panel wasn't on, delay before accessing aux channel
1213          */
1214         if (!edp_have_panel_power(intel_dp)) {
1215                 DRM_DEBUG_KMS("eDP was not running\n");
1216                 msleep(intel_dp->panel_power_up_delay);
1217         }
1218
1219         return need_to_disable;
1220 }
1221
1222 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1223 {
1224         bool vdd;
1225
1226         if (!is_edp(intel_dp))
1227                 return;
1228
1229         vdd = edp_panel_vdd_on(intel_dp);
1230
1231         WARN(!vdd, "eDP VDD already requested on\n");
1232 }
1233
1234 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1235 {
1236         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1237         struct drm_i915_private *dev_priv = dev->dev_private;
1238         struct intel_digital_port *intel_dig_port =
1239                 dp_to_dig_port(intel_dp);
1240         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1241         enum intel_display_power_domain power_domain;
1242         u32 pp;
1243         u32 pp_stat_reg, pp_ctrl_reg;
1244
1245         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1246
1247         WARN_ON(intel_dp->want_panel_vdd);
1248
1249         if (!edp_have_panel_vdd(intel_dp))
1250                 return;
1251
1252         DRM_DEBUG_KMS("Turning eDP VDD off\n");
1253
1254         pp = ironlake_get_pp_control(intel_dp);
1255         pp &= ~EDP_FORCE_VDD;
1256
1257         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1258         pp_stat_reg = _pp_stat_reg(intel_dp);
1259
1260         I915_WRITE(pp_ctrl_reg, pp);
1261         POSTING_READ(pp_ctrl_reg);
1262
1263         /* Make sure sequencer is idle before allowing subsequent activity */
1264         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1265         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1266
1267         if ((pp & POWER_TARGET_ON) == 0)
1268                 intel_dp->last_power_cycle = jiffies;
1269
1270         power_domain = intel_display_port_power_domain(intel_encoder);
1271         intel_display_power_put(dev_priv, power_domain);
1272 }
1273
1274 static void edp_panel_vdd_work(struct work_struct *__work)
1275 {
1276         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1277                                                  struct intel_dp, panel_vdd_work);
1278         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1279
1280         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1281         if (!intel_dp->want_panel_vdd)
1282                 edp_panel_vdd_off_sync(intel_dp);
1283         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1284 }
1285
1286 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1287 {
1288         unsigned long delay;
1289
1290         /*
1291          * Queue the timer to fire a long time from now (relative to the power
1292          * down delay) to keep the panel power up across a sequence of
1293          * operations.
1294          */
1295         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1296         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1297 }
1298
1299 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1300 {
1301         if (!is_edp(intel_dp))
1302                 return;
1303
1304         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1305
1306         intel_dp->want_panel_vdd = false;
1307
1308         if (sync)
1309                 edp_panel_vdd_off_sync(intel_dp);
1310         else
1311                 edp_panel_vdd_schedule_off(intel_dp);
1312 }
1313
1314 static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1315 {
1316         edp_panel_vdd_off(intel_dp, sync);
1317 }
1318
1319 void intel_edp_panel_on(struct intel_dp *intel_dp)
1320 {
1321         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1322         struct drm_i915_private *dev_priv = dev->dev_private;
1323         u32 pp;
1324         u32 pp_ctrl_reg;
1325
1326         if (!is_edp(intel_dp))
1327                 return;
1328
1329         DRM_DEBUG_KMS("Turn eDP power on\n");
1330
1331         if (edp_have_panel_power(intel_dp)) {
1332                 DRM_DEBUG_KMS("eDP power already on\n");
1333                 return;
1334         }
1335
1336         wait_panel_power_cycle(intel_dp);
1337
1338         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1339         pp = ironlake_get_pp_control(intel_dp);
1340         if (IS_GEN5(dev)) {
1341                 /* ILK workaround: disable reset around power sequence */
1342                 pp &= ~PANEL_POWER_RESET;
1343                 I915_WRITE(pp_ctrl_reg, pp);
1344                 POSTING_READ(pp_ctrl_reg);
1345         }
1346
1347         pp |= POWER_TARGET_ON;
1348         if (!IS_GEN5(dev))
1349                 pp |= PANEL_POWER_RESET;
1350
1351         I915_WRITE(pp_ctrl_reg, pp);
1352         POSTING_READ(pp_ctrl_reg);
1353
1354         wait_panel_on(intel_dp);
1355         intel_dp->last_power_on = jiffies;
1356
1357         if (IS_GEN5(dev)) {
1358                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1359                 I915_WRITE(pp_ctrl_reg, pp);
1360                 POSTING_READ(pp_ctrl_reg);
1361         }
1362 }
1363
1364 void intel_edp_panel_off(struct intel_dp *intel_dp)
1365 {
1366         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1367         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1368         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1369         struct drm_i915_private *dev_priv = dev->dev_private;
1370         enum intel_display_power_domain power_domain;
1371         u32 pp;
1372         u32 pp_ctrl_reg;
1373
1374         if (!is_edp(intel_dp))
1375                 return;
1376
1377         DRM_DEBUG_KMS("Turn eDP power off\n");
1378
1379         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1380
1381         pp = ironlake_get_pp_control(intel_dp);
1382         /* We need to switch off panel power _and_ force vdd, for otherwise some
1383          * panels get very unhappy and cease to work. */
1384         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1385                 EDP_BLC_ENABLE);
1386
1387         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1388
1389         intel_dp->want_panel_vdd = false;
1390
1391         I915_WRITE(pp_ctrl_reg, pp);
1392         POSTING_READ(pp_ctrl_reg);
1393
1394         intel_dp->last_power_cycle = jiffies;
1395         wait_panel_off(intel_dp);
1396
1397         /* We got a reference when we enabled the VDD. */
1398         power_domain = intel_display_port_power_domain(intel_encoder);
1399         intel_display_power_put(dev_priv, power_domain);
1400 }
1401
1402 /* Enable backlight in the panel power control. */
1403 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1404 {
1405         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1406         struct drm_device *dev = intel_dig_port->base.base.dev;
1407         struct drm_i915_private *dev_priv = dev->dev_private;
1408         u32 pp;
1409         u32 pp_ctrl_reg;
1410
1411         /*
1412          * If we enable the backlight right away following a panel power
1413          * on, we may see slight flicker as the panel syncs with the eDP
1414          * link.  So delay a bit to make sure the image is solid before
1415          * allowing it to appear.
1416          */
1417         wait_backlight_on(intel_dp);
1418         pp = ironlake_get_pp_control(intel_dp);
1419         pp |= EDP_BLC_ENABLE;
1420
1421         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1422
1423         I915_WRITE(pp_ctrl_reg, pp);
1424         POSTING_READ(pp_ctrl_reg);
1425 }
1426
1427 /* Enable backlight PWM and backlight PP control. */
1428 void intel_edp_backlight_on(struct intel_dp *intel_dp)
1429 {
1430         if (!is_edp(intel_dp))
1431                 return;
1432
1433         DRM_DEBUG_KMS("\n");
1434
1435         intel_panel_enable_backlight(intel_dp->attached_connector);
1436         _intel_edp_backlight_on(intel_dp);
1437 }
1438
1439 /* Disable backlight in the panel power control. */
1440 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1441 {
1442         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1443         struct drm_i915_private *dev_priv = dev->dev_private;
1444         u32 pp;
1445         u32 pp_ctrl_reg;
1446
1447         pp = ironlake_get_pp_control(intel_dp);
1448         pp &= ~EDP_BLC_ENABLE;
1449
1450         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1451
1452         I915_WRITE(pp_ctrl_reg, pp);
1453         POSTING_READ(pp_ctrl_reg);
1454         intel_dp->last_backlight_off = jiffies;
1455
1456         edp_wait_backlight_off(intel_dp);
1457 }
1458
1459 /* Disable backlight PP control and backlight PWM. */
1460 void intel_edp_backlight_off(struct intel_dp *intel_dp)
1461 {
1462         if (!is_edp(intel_dp))
1463                 return;
1464
1465         DRM_DEBUG_KMS("\n");
1466
1467         _intel_edp_backlight_off(intel_dp);
1468         intel_panel_disable_backlight(intel_dp->attached_connector);
1469 }
1470
1471 /*
1472  * Hook for controlling the panel power control backlight through the bl_power
1473  * sysfs attribute. Take care to handle multiple calls.
1474  */
1475 static void intel_edp_backlight_power(struct intel_connector *connector,
1476                                       bool enable)
1477 {
1478         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1479         bool is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1480
1481         if (is_enabled == enable)
1482                 return;
1483
1484         DRM_DEBUG_KMS("panel power control backlight %s\n",
1485                       enable ? "enable" : "disable");
1486
1487         if (enable)
1488                 _intel_edp_backlight_on(intel_dp);
1489         else
1490                 _intel_edp_backlight_off(intel_dp);
1491 }
1492
1493 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1494 {
1495         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1496         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1497         struct drm_device *dev = crtc->dev;
1498         struct drm_i915_private *dev_priv = dev->dev_private;
1499         u32 dpa_ctl;
1500
1501         assert_pipe_disabled(dev_priv,
1502                              to_intel_crtc(crtc)->pipe);
1503
1504         DRM_DEBUG_KMS("\n");
1505         dpa_ctl = I915_READ(DP_A);
1506         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1507         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1508
1509         /* We don't adjust intel_dp->DP while tearing down the link, to
1510          * facilitate link retraining (e.g. after hotplug). Hence clear all
1511          * enable bits here to ensure that we don't enable too much. */
1512         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1513         intel_dp->DP |= DP_PLL_ENABLE;
1514         I915_WRITE(DP_A, intel_dp->DP);
1515         POSTING_READ(DP_A);
1516         udelay(200);
1517 }
1518
1519 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1520 {
1521         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1522         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1523         struct drm_device *dev = crtc->dev;
1524         struct drm_i915_private *dev_priv = dev->dev_private;
1525         u32 dpa_ctl;
1526
1527         assert_pipe_disabled(dev_priv,
1528                              to_intel_crtc(crtc)->pipe);
1529
1530         dpa_ctl = I915_READ(DP_A);
1531         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1532              "dp pll off, should be on\n");
1533         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1534
1535         /* We can't rely on the value tracked for the DP register in
1536          * intel_dp->DP because link_down must not change that (otherwise link
1537          * re-training will fail. */
1538         dpa_ctl &= ~DP_PLL_ENABLE;
1539         I915_WRITE(DP_A, dpa_ctl);
1540         POSTING_READ(DP_A);
1541         udelay(200);
1542 }
1543
1544 /* If the sink supports it, try to set the power state appropriately */
1545 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1546 {
1547         int ret, i;
1548
1549         /* Should have a valid DPCD by this point */
1550         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1551                 return;
1552
1553         if (mode != DRM_MODE_DPMS_ON) {
1554                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1555                                          DP_SET_POWER_D3);
1556                 if (ret != 1)
1557                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1558         } else {
1559                 /*
1560                  * When turning on, we need to retry for 1ms to give the sink
1561                  * time to wake up.
1562                  */
1563                 for (i = 0; i < 3; i++) {
1564                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1565                                                  DP_SET_POWER_D0);
1566                         if (ret == 1)
1567                                 break;
1568                         msleep(1);
1569                 }
1570         }
1571 }
1572
1573 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1574                                   enum pipe *pipe)
1575 {
1576         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1577         enum port port = dp_to_dig_port(intel_dp)->port;
1578         struct drm_device *dev = encoder->base.dev;
1579         struct drm_i915_private *dev_priv = dev->dev_private;
1580         enum intel_display_power_domain power_domain;
1581         u32 tmp;
1582
1583         power_domain = intel_display_port_power_domain(encoder);
1584         if (!intel_display_power_enabled(dev_priv, power_domain))
1585                 return false;
1586
1587         tmp = I915_READ(intel_dp->output_reg);
1588
1589         if (!(tmp & DP_PORT_EN))
1590                 return false;
1591
1592         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1593                 *pipe = PORT_TO_PIPE_CPT(tmp);
1594         } else if (IS_CHERRYVIEW(dev)) {
1595                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
1596         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1597                 *pipe = PORT_TO_PIPE(tmp);
1598         } else {
1599                 u32 trans_sel;
1600                 u32 trans_dp;
1601                 int i;
1602
1603                 switch (intel_dp->output_reg) {
1604                 case PCH_DP_B:
1605                         trans_sel = TRANS_DP_PORT_SEL_B;
1606                         break;
1607                 case PCH_DP_C:
1608                         trans_sel = TRANS_DP_PORT_SEL_C;
1609                         break;
1610                 case PCH_DP_D:
1611                         trans_sel = TRANS_DP_PORT_SEL_D;
1612                         break;
1613                 default:
1614                         return true;
1615                 }
1616
1617                 for_each_pipe(dev_priv, i) {
1618                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1619                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1620                                 *pipe = i;
1621                                 return true;
1622                         }
1623                 }
1624
1625                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1626                               intel_dp->output_reg);
1627         }
1628
1629         return true;
1630 }
1631
1632 static void intel_dp_get_config(struct intel_encoder *encoder,
1633                                 struct intel_crtc_config *pipe_config)
1634 {
1635         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1636         u32 tmp, flags = 0;
1637         struct drm_device *dev = encoder->base.dev;
1638         struct drm_i915_private *dev_priv = dev->dev_private;
1639         enum port port = dp_to_dig_port(intel_dp)->port;
1640         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1641         int dotclock;
1642
1643         tmp = I915_READ(intel_dp->output_reg);
1644         if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1645                 pipe_config->has_audio = true;
1646
1647         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1648                 if (tmp & DP_SYNC_HS_HIGH)
1649                         flags |= DRM_MODE_FLAG_PHSYNC;
1650                 else
1651                         flags |= DRM_MODE_FLAG_NHSYNC;
1652
1653                 if (tmp & DP_SYNC_VS_HIGH)
1654                         flags |= DRM_MODE_FLAG_PVSYNC;
1655                 else
1656                         flags |= DRM_MODE_FLAG_NVSYNC;
1657         } else {
1658                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1659                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1660                         flags |= DRM_MODE_FLAG_PHSYNC;
1661                 else
1662                         flags |= DRM_MODE_FLAG_NHSYNC;
1663
1664                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1665                         flags |= DRM_MODE_FLAG_PVSYNC;
1666                 else
1667                         flags |= DRM_MODE_FLAG_NVSYNC;
1668         }
1669
1670         pipe_config->adjusted_mode.flags |= flags;
1671
1672         pipe_config->has_dp_encoder = true;
1673
1674         intel_dp_get_m_n(crtc, pipe_config);
1675
1676         if (port == PORT_A) {
1677                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1678                         pipe_config->port_clock = 162000;
1679                 else
1680                         pipe_config->port_clock = 270000;
1681         }
1682
1683         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1684                                             &pipe_config->dp_m_n);
1685
1686         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1687                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1688
1689         pipe_config->adjusted_mode.crtc_clock = dotclock;
1690
1691         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1692             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1693                 /*
1694                  * This is a big fat ugly hack.
1695                  *
1696                  * Some machines in UEFI boot mode provide us a VBT that has 18
1697                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1698                  * unknown we fail to light up. Yet the same BIOS boots up with
1699                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1700                  * max, not what it tells us to use.
1701                  *
1702                  * Note: This will still be broken if the eDP panel is not lit
1703                  * up by the BIOS, and thus we can't get the mode at module
1704                  * load.
1705                  */
1706                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1707                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1708                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1709         }
1710 }
1711
1712 static bool is_edp_psr(struct intel_dp *intel_dp)
1713 {
1714         return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1715 }
1716
1717 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1718 {
1719         struct drm_i915_private *dev_priv = dev->dev_private;
1720
1721         if (!HAS_PSR(dev))
1722                 return false;
1723
1724         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1725 }
1726
1727 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1728                                     struct edp_vsc_psr *vsc_psr)
1729 {
1730         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1731         struct drm_device *dev = dig_port->base.base.dev;
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1734         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1735         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1736         uint32_t *data = (uint32_t *) vsc_psr;
1737         unsigned int i;
1738
1739         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1740            the video DIP being updated before program video DIP data buffer
1741            registers for DIP being updated. */
1742         I915_WRITE(ctl_reg, 0);
1743         POSTING_READ(ctl_reg);
1744
1745         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1746                 if (i < sizeof(struct edp_vsc_psr))
1747                         I915_WRITE(data_reg + i, *data++);
1748                 else
1749                         I915_WRITE(data_reg + i, 0);
1750         }
1751
1752         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1753         POSTING_READ(ctl_reg);
1754 }
1755
1756 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1757 {
1758         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1759         struct drm_i915_private *dev_priv = dev->dev_private;
1760         struct edp_vsc_psr psr_vsc;
1761
1762         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1763         memset(&psr_vsc, 0, sizeof(psr_vsc));
1764         psr_vsc.sdp_header.HB0 = 0;
1765         psr_vsc.sdp_header.HB1 = 0x7;
1766         psr_vsc.sdp_header.HB2 = 0x2;
1767         psr_vsc.sdp_header.HB3 = 0x8;
1768         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1769
1770         /* Avoid continuous PSR exit by masking memup and hpd */
1771         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1772                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1773 }
1774
1775 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1776 {
1777         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1778         struct drm_device *dev = dig_port->base.base.dev;
1779         struct drm_i915_private *dev_priv = dev->dev_private;
1780         uint32_t aux_clock_divider;
1781         int precharge = 0x3;
1782         int msg_size = 5;       /* Header(4) + Message(1) */
1783         bool only_standby = false;
1784
1785         aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1786
1787         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1788                 only_standby = true;
1789
1790         /* Enable PSR in sink */
1791         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
1792                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1793                                    DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
1794         else
1795                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1796                                    DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
1797
1798         /* Setup AUX registers */
1799         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1800         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1801         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1802                    DP_AUX_CH_CTL_TIME_OUT_400us |
1803                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1804                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1805                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1806 }
1807
1808 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1809 {
1810         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1811         struct drm_device *dev = dig_port->base.base.dev;
1812         struct drm_i915_private *dev_priv = dev->dev_private;
1813         uint32_t max_sleep_time = 0x1f;
1814         uint32_t idle_frames = 1;
1815         uint32_t val = 0x0;
1816         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1817         bool only_standby = false;
1818
1819         if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1820                 only_standby = true;
1821
1822         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
1823                 val |= EDP_PSR_LINK_STANDBY;
1824                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1825                 val |= EDP_PSR_TP1_TIME_0us;
1826                 val |= EDP_PSR_SKIP_AUX_EXIT;
1827                 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
1828         } else
1829                 val |= EDP_PSR_LINK_DISABLE;
1830
1831         I915_WRITE(EDP_PSR_CTL(dev), val |
1832                    (IS_BROADWELL(dev) ? 0 : link_entry_time) |
1833                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1834                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1835                    EDP_PSR_ENABLE);
1836 }
1837
1838 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1839 {
1840         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1841         struct drm_device *dev = dig_port->base.base.dev;
1842         struct drm_i915_private *dev_priv = dev->dev_private;
1843         struct drm_crtc *crtc = dig_port->base.base.crtc;
1844         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1845
1846         lockdep_assert_held(&dev_priv->psr.lock);
1847         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1848         WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1849
1850         dev_priv->psr.source_ok = false;
1851
1852         if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
1853                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1854                 return false;
1855         }
1856
1857         if (!i915.enable_psr) {
1858                 DRM_DEBUG_KMS("PSR disable by flag\n");
1859                 return false;
1860         }
1861
1862         /* Below limitations aren't valid for Broadwell */
1863         if (IS_BROADWELL(dev))
1864                 goto out;
1865
1866         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1867             S3D_ENABLE) {
1868                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1869                 return false;
1870         }
1871
1872         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1873                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1874                 return false;
1875         }
1876
1877  out:
1878         dev_priv->psr.source_ok = true;
1879         return true;
1880 }
1881
1882 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1883 {
1884         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1885         struct drm_device *dev = intel_dig_port->base.base.dev;
1886         struct drm_i915_private *dev_priv = dev->dev_private;
1887
1888         WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1889         WARN_ON(dev_priv->psr.active);
1890         lockdep_assert_held(&dev_priv->psr.lock);
1891
1892         /* Enable PSR on the panel */
1893         intel_edp_psr_enable_sink(intel_dp);
1894
1895         /* Enable PSR on the host */
1896         intel_edp_psr_enable_source(intel_dp);
1897
1898         dev_priv->psr.active = true;
1899 }
1900
1901 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1902 {
1903         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1904         struct drm_i915_private *dev_priv = dev->dev_private;
1905
1906         if (!HAS_PSR(dev)) {
1907                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1908                 return;
1909         }
1910
1911         if (!is_edp_psr(intel_dp)) {
1912                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1913                 return;
1914         }
1915
1916         mutex_lock(&dev_priv->psr.lock);
1917         if (dev_priv->psr.enabled) {
1918                 DRM_DEBUG_KMS("PSR already in use\n");
1919                 mutex_unlock(&dev_priv->psr.lock);
1920                 return;
1921         }
1922
1923         dev_priv->psr.busy_frontbuffer_bits = 0;
1924
1925         /* Setup PSR once */
1926         intel_edp_psr_setup(intel_dp);
1927
1928         if (intel_edp_psr_match_conditions(intel_dp))
1929                 dev_priv->psr.enabled = intel_dp;
1930         mutex_unlock(&dev_priv->psr.lock);
1931 }
1932
1933 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1934 {
1935         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1936         struct drm_i915_private *dev_priv = dev->dev_private;
1937
1938         mutex_lock(&dev_priv->psr.lock);
1939         if (!dev_priv->psr.enabled) {
1940                 mutex_unlock(&dev_priv->psr.lock);
1941                 return;
1942         }
1943
1944         if (dev_priv->psr.active) {
1945                 I915_WRITE(EDP_PSR_CTL(dev),
1946                            I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1947
1948                 /* Wait till PSR is idle */
1949                 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1950                                EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1951                         DRM_ERROR("Timed out waiting for PSR Idle State\n");
1952
1953                 dev_priv->psr.active = false;
1954         } else {
1955                 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1956         }
1957
1958         dev_priv->psr.enabled = NULL;
1959         mutex_unlock(&dev_priv->psr.lock);
1960
1961         cancel_delayed_work_sync(&dev_priv->psr.work);
1962 }
1963
1964 static void intel_edp_psr_work(struct work_struct *work)
1965 {
1966         struct drm_i915_private *dev_priv =
1967                 container_of(work, typeof(*dev_priv), psr.work.work);
1968         struct intel_dp *intel_dp = dev_priv->psr.enabled;
1969
1970         mutex_lock(&dev_priv->psr.lock);
1971         intel_dp = dev_priv->psr.enabled;
1972
1973         if (!intel_dp)
1974                 goto unlock;
1975
1976         /*
1977          * The delayed work can race with an invalidate hence we need to
1978          * recheck. Since psr_flush first clears this and then reschedules we
1979          * won't ever miss a flush when bailing out here.
1980          */
1981         if (dev_priv->psr.busy_frontbuffer_bits)
1982                 goto unlock;
1983
1984         intel_edp_psr_do_enable(intel_dp);
1985 unlock:
1986         mutex_unlock(&dev_priv->psr.lock);
1987 }
1988
1989 static void intel_edp_psr_do_exit(struct drm_device *dev)
1990 {
1991         struct drm_i915_private *dev_priv = dev->dev_private;
1992
1993         if (dev_priv->psr.active) {
1994                 u32 val = I915_READ(EDP_PSR_CTL(dev));
1995
1996                 WARN_ON(!(val & EDP_PSR_ENABLE));
1997
1998                 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1999
2000                 dev_priv->psr.active = false;
2001         }
2002
2003 }
2004
2005 void intel_edp_psr_invalidate(struct drm_device *dev,
2006                               unsigned frontbuffer_bits)
2007 {
2008         struct drm_i915_private *dev_priv = dev->dev_private;
2009         struct drm_crtc *crtc;
2010         enum pipe pipe;
2011
2012         mutex_lock(&dev_priv->psr.lock);
2013         if (!dev_priv->psr.enabled) {
2014                 mutex_unlock(&dev_priv->psr.lock);
2015                 return;
2016         }
2017
2018         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2019         pipe = to_intel_crtc(crtc)->pipe;
2020
2021         intel_edp_psr_do_exit(dev);
2022
2023         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2024
2025         dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2026         mutex_unlock(&dev_priv->psr.lock);
2027 }
2028
2029 void intel_edp_psr_flush(struct drm_device *dev,
2030                          unsigned frontbuffer_bits)
2031 {
2032         struct drm_i915_private *dev_priv = dev->dev_private;
2033         struct drm_crtc *crtc;
2034         enum pipe pipe;
2035
2036         mutex_lock(&dev_priv->psr.lock);
2037         if (!dev_priv->psr.enabled) {
2038                 mutex_unlock(&dev_priv->psr.lock);
2039                 return;
2040         }
2041
2042         crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2043         pipe = to_intel_crtc(crtc)->pipe;
2044         dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2045
2046         /*
2047          * On Haswell sprite plane updates don't result in a psr invalidating
2048          * signal in the hardware. Which means we need to manually fake this in
2049          * software for all flushes, not just when we've seen a preceding
2050          * invalidation through frontbuffer rendering.
2051          */
2052         if (IS_HASWELL(dev) &&
2053             (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2054                 intel_edp_psr_do_exit(dev);
2055
2056         if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2057                 schedule_delayed_work(&dev_priv->psr.work,
2058                                       msecs_to_jiffies(100));
2059         mutex_unlock(&dev_priv->psr.lock);
2060 }
2061
2062 void intel_edp_psr_init(struct drm_device *dev)
2063 {
2064         struct drm_i915_private *dev_priv = dev->dev_private;
2065
2066         INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2067         mutex_init(&dev_priv->psr.lock);
2068 }
2069
2070 static void intel_disable_dp(struct intel_encoder *encoder)
2071 {
2072         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2073         enum port port = dp_to_dig_port(intel_dp)->port;
2074         struct drm_device *dev = encoder->base.dev;
2075
2076         /* Make sure the panel is off before trying to change the mode. But also
2077          * ensure that we have vdd while we switch off the panel. */
2078         intel_edp_panel_vdd_on(intel_dp);
2079         intel_edp_backlight_off(intel_dp);
2080         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2081         intel_edp_panel_off(intel_dp);
2082
2083         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2084         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
2085                 intel_dp_link_down(intel_dp);
2086 }
2087
2088 static void g4x_post_disable_dp(struct intel_encoder *encoder)
2089 {
2090         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2091         enum port port = dp_to_dig_port(intel_dp)->port;
2092
2093         if (port != PORT_A)
2094                 return;
2095
2096         intel_dp_link_down(intel_dp);
2097         ironlake_edp_pll_off(intel_dp);
2098 }
2099
2100 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2101 {
2102         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2103
2104         intel_dp_link_down(intel_dp);
2105 }
2106
2107 static void chv_post_disable_dp(struct intel_encoder *encoder)
2108 {
2109         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2110         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2111         struct drm_device *dev = encoder->base.dev;
2112         struct drm_i915_private *dev_priv = dev->dev_private;
2113         struct intel_crtc *intel_crtc =
2114                 to_intel_crtc(encoder->base.crtc);
2115         enum dpio_channel ch = vlv_dport_to_channel(dport);
2116         enum pipe pipe = intel_crtc->pipe;
2117         u32 val;
2118
2119         intel_dp_link_down(intel_dp);
2120
2121         mutex_lock(&dev_priv->dpio_lock);
2122
2123         /* Propagate soft reset to data lane reset */
2124         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2125         val |= CHV_PCS_REQ_SOFTRESET_EN;
2126         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2127
2128         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2129         val |= CHV_PCS_REQ_SOFTRESET_EN;
2130         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2131
2132         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2133         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2134         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2135
2136         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2137         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2138         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2139
2140         mutex_unlock(&dev_priv->dpio_lock);
2141 }
2142
2143 static void intel_enable_dp(struct intel_encoder *encoder)
2144 {
2145         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2146         struct drm_device *dev = encoder->base.dev;
2147         struct drm_i915_private *dev_priv = dev->dev_private;
2148         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2149
2150         if (WARN_ON(dp_reg & DP_PORT_EN))
2151                 return;
2152
2153         intel_edp_panel_vdd_on(intel_dp);
2154         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2155         intel_dp_start_link_train(intel_dp);
2156         intel_edp_panel_on(intel_dp);
2157         intel_edp_panel_vdd_off(intel_dp, true);
2158         intel_dp_complete_link_train(intel_dp);
2159         intel_dp_stop_link_train(intel_dp);
2160 }
2161
2162 static void g4x_enable_dp(struct intel_encoder *encoder)
2163 {
2164         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2165
2166         intel_enable_dp(encoder);
2167         intel_edp_backlight_on(intel_dp);
2168 }
2169
2170 static void vlv_enable_dp(struct intel_encoder *encoder)
2171 {
2172         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2173
2174         intel_edp_backlight_on(intel_dp);
2175 }
2176
2177 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2178 {
2179         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2180         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2181
2182         intel_dp_prepare(encoder);
2183
2184         /* Only ilk+ has port A */
2185         if (dport->port == PORT_A) {
2186                 ironlake_set_pll_cpu_edp(intel_dp);
2187                 ironlake_edp_pll_on(intel_dp);
2188         }
2189 }
2190
2191 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2192 {
2193         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2194         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2195         struct drm_device *dev = encoder->base.dev;
2196         struct drm_i915_private *dev_priv = dev->dev_private;
2197         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2198         enum dpio_channel port = vlv_dport_to_channel(dport);
2199         int pipe = intel_crtc->pipe;
2200         struct edp_power_seq power_seq;
2201         u32 val;
2202
2203         mutex_lock(&dev_priv->dpio_lock);
2204
2205         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2206         val = 0;
2207         if (pipe)
2208                 val |= (1<<21);
2209         else
2210                 val &= ~(1<<21);
2211         val |= 0x001000c4;
2212         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2213         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2214         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2215
2216         mutex_unlock(&dev_priv->dpio_lock);
2217
2218         if (is_edp(intel_dp)) {
2219                 /* init power sequencer on this pipe and port */
2220                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2221                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2222                                                               &power_seq);
2223         }
2224
2225         intel_enable_dp(encoder);
2226
2227         vlv_wait_port_ready(dev_priv, dport);
2228 }
2229
2230 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2231 {
2232         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2233         struct drm_device *dev = encoder->base.dev;
2234         struct drm_i915_private *dev_priv = dev->dev_private;
2235         struct intel_crtc *intel_crtc =
2236                 to_intel_crtc(encoder->base.crtc);
2237         enum dpio_channel port = vlv_dport_to_channel(dport);
2238         int pipe = intel_crtc->pipe;
2239
2240         intel_dp_prepare(encoder);
2241
2242         /* Program Tx lane resets to default */
2243         mutex_lock(&dev_priv->dpio_lock);
2244         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2245                          DPIO_PCS_TX_LANE2_RESET |
2246                          DPIO_PCS_TX_LANE1_RESET);
2247         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2248                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2249                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2250                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2251                                  DPIO_PCS_CLK_SOFT_RESET);
2252
2253         /* Fix up inter-pair skew failure */
2254         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2255         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2256         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2257         mutex_unlock(&dev_priv->dpio_lock);
2258 }
2259
2260 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2261 {
2262         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2263         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2264         struct drm_device *dev = encoder->base.dev;
2265         struct drm_i915_private *dev_priv = dev->dev_private;
2266         struct edp_power_seq power_seq;
2267         struct intel_crtc *intel_crtc =
2268                 to_intel_crtc(encoder->base.crtc);
2269         enum dpio_channel ch = vlv_dport_to_channel(dport);
2270         int pipe = intel_crtc->pipe;
2271         int data, i;
2272         u32 val;
2273
2274         mutex_lock(&dev_priv->dpio_lock);
2275
2276         /* Deassert soft data lane reset*/
2277         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2278         val |= CHV_PCS_REQ_SOFTRESET_EN;
2279         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2280
2281         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2282         val |= CHV_PCS_REQ_SOFTRESET_EN;
2283         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2284
2285         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2286         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2287         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2288
2289         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2290         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2291         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2292
2293         /* Program Tx lane latency optimal setting*/
2294         for (i = 0; i < 4; i++) {
2295                 /* Set the latency optimal bit */
2296                 data = (i == 1) ? 0x0 : 0x6;
2297                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2298                                 data << DPIO_FRC_LATENCY_SHFIT);
2299
2300                 /* Set the upar bit */
2301                 data = (i == 1) ? 0x0 : 0x1;
2302                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2303                                 data << DPIO_UPAR_SHIFT);
2304         }
2305
2306         /* Data lane stagger programming */
2307         /* FIXME: Fix up value only after power analysis */
2308
2309         mutex_unlock(&dev_priv->dpio_lock);
2310
2311         if (is_edp(intel_dp)) {
2312                 /* init power sequencer on this pipe and port */
2313                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2314                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2315                                                               &power_seq);
2316         }
2317
2318         intel_enable_dp(encoder);
2319
2320         vlv_wait_port_ready(dev_priv, dport);
2321 }
2322
2323 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2324 {
2325         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2326         struct drm_device *dev = encoder->base.dev;
2327         struct drm_i915_private *dev_priv = dev->dev_private;
2328         struct intel_crtc *intel_crtc =
2329                 to_intel_crtc(encoder->base.crtc);
2330         enum dpio_channel ch = vlv_dport_to_channel(dport);
2331         enum pipe pipe = intel_crtc->pipe;
2332         u32 val;
2333
2334         intel_dp_prepare(encoder);
2335
2336         mutex_lock(&dev_priv->dpio_lock);
2337
2338         /* program left/right clock distribution */
2339         if (pipe != PIPE_B) {
2340                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2341                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2342                 if (ch == DPIO_CH0)
2343                         val |= CHV_BUFLEFTENA1_FORCE;
2344                 if (ch == DPIO_CH1)
2345                         val |= CHV_BUFRIGHTENA1_FORCE;
2346                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2347         } else {
2348                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2349                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2350                 if (ch == DPIO_CH0)
2351                         val |= CHV_BUFLEFTENA2_FORCE;
2352                 if (ch == DPIO_CH1)
2353                         val |= CHV_BUFRIGHTENA2_FORCE;
2354                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2355         }
2356
2357         /* program clock channel usage */
2358         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2359         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2360         if (pipe != PIPE_B)
2361                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2362         else
2363                 val |= CHV_PCS_USEDCLKCHANNEL;
2364         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2365
2366         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2367         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2368         if (pipe != PIPE_B)
2369                 val &= ~CHV_PCS_USEDCLKCHANNEL;
2370         else
2371                 val |= CHV_PCS_USEDCLKCHANNEL;
2372         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2373
2374         /*
2375          * This a a bit weird since generally CL
2376          * matches the pipe, but here we need to
2377          * pick the CL based on the port.
2378          */
2379         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2380         if (pipe != PIPE_B)
2381                 val &= ~CHV_CMN_USEDCLKCHANNEL;
2382         else
2383                 val |= CHV_CMN_USEDCLKCHANNEL;
2384         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2385
2386         mutex_unlock(&dev_priv->dpio_lock);
2387 }
2388
2389 /*
2390  * Native read with retry for link status and receiver capability reads for
2391  * cases where the sink may still be asleep.
2392  *
2393  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2394  * supposed to retry 3 times per the spec.
2395  */
2396 static ssize_t
2397 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2398                         void *buffer, size_t size)
2399 {
2400         ssize_t ret;
2401         int i;
2402
2403         for (i = 0; i < 3; i++) {
2404                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2405                 if (ret == size)
2406                         return ret;
2407                 msleep(1);
2408         }
2409
2410         return ret;
2411 }
2412
2413 /*
2414  * Fetch AUX CH registers 0x202 - 0x207 which contain
2415  * link status information
2416  */
2417 static bool
2418 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2419 {
2420         return intel_dp_dpcd_read_wake(&intel_dp->aux,
2421                                        DP_LANE0_1_STATUS,
2422                                        link_status,
2423                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2424 }
2425
2426 /* These are source-specific values. */
2427 static uint8_t
2428 intel_dp_voltage_max(struct intel_dp *intel_dp)
2429 {
2430         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2431         enum port port = dp_to_dig_port(intel_dp)->port;
2432
2433         if (IS_VALLEYVIEW(dev))
2434                 return DP_TRAIN_VOLTAGE_SWING_1200;
2435         else if (IS_GEN7(dev) && port == PORT_A)
2436                 return DP_TRAIN_VOLTAGE_SWING_800;
2437         else if (HAS_PCH_CPT(dev) && port != PORT_A)
2438                 return DP_TRAIN_VOLTAGE_SWING_1200;
2439         else
2440                 return DP_TRAIN_VOLTAGE_SWING_800;
2441 }
2442
2443 static uint8_t
2444 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2445 {
2446         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2447         enum port port = dp_to_dig_port(intel_dp)->port;
2448
2449         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2450                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2451                 case DP_TRAIN_VOLTAGE_SWING_400:
2452                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2453                 case DP_TRAIN_VOLTAGE_SWING_600:
2454                         return DP_TRAIN_PRE_EMPHASIS_6;
2455                 case DP_TRAIN_VOLTAGE_SWING_800:
2456                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2457                 case DP_TRAIN_VOLTAGE_SWING_1200:
2458                 default:
2459                         return DP_TRAIN_PRE_EMPHASIS_0;
2460                 }
2461         } else if (IS_VALLEYVIEW(dev)) {
2462                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2463                 case DP_TRAIN_VOLTAGE_SWING_400:
2464                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2465                 case DP_TRAIN_VOLTAGE_SWING_600:
2466                         return DP_TRAIN_PRE_EMPHASIS_6;
2467                 case DP_TRAIN_VOLTAGE_SWING_800:
2468                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2469                 case DP_TRAIN_VOLTAGE_SWING_1200:
2470                 default:
2471                         return DP_TRAIN_PRE_EMPHASIS_0;
2472                 }
2473         } else if (IS_GEN7(dev) && port == PORT_A) {
2474                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2475                 case DP_TRAIN_VOLTAGE_SWING_400:
2476                         return DP_TRAIN_PRE_EMPHASIS_6;
2477                 case DP_TRAIN_VOLTAGE_SWING_600:
2478                 case DP_TRAIN_VOLTAGE_SWING_800:
2479                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2480                 default:
2481                         return DP_TRAIN_PRE_EMPHASIS_0;
2482                 }
2483         } else {
2484                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2485                 case DP_TRAIN_VOLTAGE_SWING_400:
2486                         return DP_TRAIN_PRE_EMPHASIS_6;
2487                 case DP_TRAIN_VOLTAGE_SWING_600:
2488                         return DP_TRAIN_PRE_EMPHASIS_6;
2489                 case DP_TRAIN_VOLTAGE_SWING_800:
2490                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2491                 case DP_TRAIN_VOLTAGE_SWING_1200:
2492                 default:
2493                         return DP_TRAIN_PRE_EMPHASIS_0;
2494                 }
2495         }
2496 }
2497
2498 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2499 {
2500         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2501         struct drm_i915_private *dev_priv = dev->dev_private;
2502         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2503         struct intel_crtc *intel_crtc =
2504                 to_intel_crtc(dport->base.base.crtc);
2505         unsigned long demph_reg_value, preemph_reg_value,
2506                 uniqtranscale_reg_value;
2507         uint8_t train_set = intel_dp->train_set[0];
2508         enum dpio_channel port = vlv_dport_to_channel(dport);
2509         int pipe = intel_crtc->pipe;
2510
2511         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2512         case DP_TRAIN_PRE_EMPHASIS_0:
2513                 preemph_reg_value = 0x0004000;
2514                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2515                 case DP_TRAIN_VOLTAGE_SWING_400:
2516                         demph_reg_value = 0x2B405555;
2517                         uniqtranscale_reg_value = 0x552AB83A;
2518                         break;
2519                 case DP_TRAIN_VOLTAGE_SWING_600:
2520                         demph_reg_value = 0x2B404040;
2521                         uniqtranscale_reg_value = 0x5548B83A;
2522                         break;
2523                 case DP_TRAIN_VOLTAGE_SWING_800:
2524                         demph_reg_value = 0x2B245555;
2525                         uniqtranscale_reg_value = 0x5560B83A;
2526                         break;
2527                 case DP_TRAIN_VOLTAGE_SWING_1200:
2528                         demph_reg_value = 0x2B405555;
2529                         uniqtranscale_reg_value = 0x5598DA3A;
2530                         break;
2531                 default:
2532                         return 0;
2533                 }
2534                 break;
2535         case DP_TRAIN_PRE_EMPHASIS_3_5:
2536                 preemph_reg_value = 0x0002000;
2537                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2538                 case DP_TRAIN_VOLTAGE_SWING_400:
2539                         demph_reg_value = 0x2B404040;
2540                         uniqtranscale_reg_value = 0x5552B83A;
2541                         break;
2542                 case DP_TRAIN_VOLTAGE_SWING_600:
2543                         demph_reg_value = 0x2B404848;
2544                         uniqtranscale_reg_value = 0x5580B83A;
2545                         break;
2546                 case DP_TRAIN_VOLTAGE_SWING_800:
2547                         demph_reg_value = 0x2B404040;
2548                         uniqtranscale_reg_value = 0x55ADDA3A;
2549                         break;
2550                 default:
2551                         return 0;
2552                 }
2553                 break;
2554         case DP_TRAIN_PRE_EMPHASIS_6:
2555                 preemph_reg_value = 0x0000000;
2556                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2557                 case DP_TRAIN_VOLTAGE_SWING_400:
2558                         demph_reg_value = 0x2B305555;
2559                         uniqtranscale_reg_value = 0x5570B83A;
2560                         break;
2561                 case DP_TRAIN_VOLTAGE_SWING_600:
2562                         demph_reg_value = 0x2B2B4040;
2563                         uniqtranscale_reg_value = 0x55ADDA3A;
2564                         break;
2565                 default:
2566                         return 0;
2567                 }
2568                 break;
2569         case DP_TRAIN_PRE_EMPHASIS_9_5:
2570                 preemph_reg_value = 0x0006000;
2571                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2572                 case DP_TRAIN_VOLTAGE_SWING_400:
2573                         demph_reg_value = 0x1B405555;
2574                         uniqtranscale_reg_value = 0x55ADDA3A;
2575                         break;
2576                 default:
2577                         return 0;
2578                 }
2579                 break;
2580         default:
2581                 return 0;
2582         }
2583
2584         mutex_lock(&dev_priv->dpio_lock);
2585         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2586         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2587         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2588                          uniqtranscale_reg_value);
2589         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2590         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2591         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2592         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2593         mutex_unlock(&dev_priv->dpio_lock);
2594
2595         return 0;
2596 }
2597
2598 static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2599 {
2600         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2601         struct drm_i915_private *dev_priv = dev->dev_private;
2602         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2603         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2604         u32 deemph_reg_value, margin_reg_value, val;
2605         uint8_t train_set = intel_dp->train_set[0];
2606         enum dpio_channel ch = vlv_dport_to_channel(dport);
2607         enum pipe pipe = intel_crtc->pipe;
2608         int i;
2609
2610         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2611         case DP_TRAIN_PRE_EMPHASIS_0:
2612                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2613                 case DP_TRAIN_VOLTAGE_SWING_400:
2614                         deemph_reg_value = 128;
2615                         margin_reg_value = 52;
2616                         break;
2617                 case DP_TRAIN_VOLTAGE_SWING_600:
2618                         deemph_reg_value = 128;
2619                         margin_reg_value = 77;
2620                         break;
2621                 case DP_TRAIN_VOLTAGE_SWING_800:
2622                         deemph_reg_value = 128;
2623                         margin_reg_value = 102;
2624                         break;
2625                 case DP_TRAIN_VOLTAGE_SWING_1200:
2626                         deemph_reg_value = 128;
2627                         margin_reg_value = 154;
2628                         /* FIXME extra to set for 1200 */
2629                         break;
2630                 default:
2631                         return 0;
2632                 }
2633                 break;
2634         case DP_TRAIN_PRE_EMPHASIS_3_5:
2635                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2636                 case DP_TRAIN_VOLTAGE_SWING_400:
2637                         deemph_reg_value = 85;
2638                         margin_reg_value = 78;
2639                         break;
2640                 case DP_TRAIN_VOLTAGE_SWING_600:
2641                         deemph_reg_value = 85;
2642                         margin_reg_value = 116;
2643                         break;
2644                 case DP_TRAIN_VOLTAGE_SWING_800:
2645                         deemph_reg_value = 85;
2646                         margin_reg_value = 154;
2647                         break;
2648                 default:
2649                         return 0;
2650                 }
2651                 break;
2652         case DP_TRAIN_PRE_EMPHASIS_6:
2653                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2654                 case DP_TRAIN_VOLTAGE_SWING_400:
2655                         deemph_reg_value = 64;
2656                         margin_reg_value = 104;
2657                         break;
2658                 case DP_TRAIN_VOLTAGE_SWING_600:
2659                         deemph_reg_value = 64;
2660                         margin_reg_value = 154;
2661                         break;
2662                 default:
2663                         return 0;
2664                 }
2665                 break;
2666         case DP_TRAIN_PRE_EMPHASIS_9_5:
2667                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2668                 case DP_TRAIN_VOLTAGE_SWING_400:
2669                         deemph_reg_value = 43;
2670                         margin_reg_value = 154;
2671                         break;
2672                 default:
2673                         return 0;
2674                 }
2675                 break;
2676         default:
2677                 return 0;
2678         }
2679
2680         mutex_lock(&dev_priv->dpio_lock);
2681
2682         /* Clear calc init */
2683         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2684         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2685         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2686
2687         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2688         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2689         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2690
2691         /* Program swing deemph */
2692         for (i = 0; i < 4; i++) {
2693                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2694                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2695                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2696                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2697         }
2698
2699         /* Program swing margin */
2700         for (i = 0; i < 4; i++) {
2701                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2702                 val &= ~DPIO_SWING_MARGIN000_MASK;
2703                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
2704                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2705         }
2706
2707         /* Disable unique transition scale */
2708         for (i = 0; i < 4; i++) {
2709                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2710                 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2711                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2712         }
2713
2714         if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2715                         == DP_TRAIN_PRE_EMPHASIS_0) &&
2716                 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2717                         == DP_TRAIN_VOLTAGE_SWING_1200)) {
2718
2719                 /*
2720                  * The document said it needs to set bit 27 for ch0 and bit 26
2721                  * for ch1. Might be a typo in the doc.
2722                  * For now, for this unique transition scale selection, set bit
2723                  * 27 for ch0 and ch1.
2724                  */
2725                 for (i = 0; i < 4; i++) {
2726                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2727                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2728                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2729                 }
2730
2731                 for (i = 0; i < 4; i++) {
2732                         val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2733                         val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2734                         val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2735                         vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2736                 }
2737         }
2738
2739         /* Start swing calculation */
2740         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2741         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2742         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2743
2744         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2745         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2746         vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2747
2748         /* LRC Bypass */
2749         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2750         val |= DPIO_LRC_BYPASS;
2751         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2752
2753         mutex_unlock(&dev_priv->dpio_lock);
2754
2755         return 0;
2756 }
2757
2758 static void
2759 intel_get_adjust_train(struct intel_dp *intel_dp,
2760                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2761 {
2762         uint8_t v = 0;
2763         uint8_t p = 0;
2764         int lane;
2765         uint8_t voltage_max;
2766         uint8_t preemph_max;
2767
2768         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2769                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2770                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2771
2772                 if (this_v > v)
2773                         v = this_v;
2774                 if (this_p > p)
2775                         p = this_p;
2776         }
2777
2778         voltage_max = intel_dp_voltage_max(intel_dp);
2779         if (v >= voltage_max)
2780                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2781
2782         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2783         if (p >= preemph_max)
2784                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2785
2786         for (lane = 0; lane < 4; lane++)
2787                 intel_dp->train_set[lane] = v | p;
2788 }
2789
2790 static uint32_t
2791 intel_gen4_signal_levels(uint8_t train_set)
2792 {
2793         uint32_t        signal_levels = 0;
2794
2795         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2796         case DP_TRAIN_VOLTAGE_SWING_400:
2797         default:
2798                 signal_levels |= DP_VOLTAGE_0_4;
2799                 break;
2800         case DP_TRAIN_VOLTAGE_SWING_600:
2801                 signal_levels |= DP_VOLTAGE_0_6;
2802                 break;
2803         case DP_TRAIN_VOLTAGE_SWING_800:
2804                 signal_levels |= DP_VOLTAGE_0_8;
2805                 break;
2806         case DP_TRAIN_VOLTAGE_SWING_1200:
2807                 signal_levels |= DP_VOLTAGE_1_2;
2808                 break;
2809         }
2810         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2811         case DP_TRAIN_PRE_EMPHASIS_0:
2812         default:
2813                 signal_levels |= DP_PRE_EMPHASIS_0;
2814                 break;
2815         case DP_TRAIN_PRE_EMPHASIS_3_5:
2816                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2817                 break;
2818         case DP_TRAIN_PRE_EMPHASIS_6:
2819                 signal_levels |= DP_PRE_EMPHASIS_6;
2820                 break;
2821         case DP_TRAIN_PRE_EMPHASIS_9_5:
2822                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2823                 break;
2824         }
2825         return signal_levels;
2826 }
2827
2828 /* Gen6's DP voltage swing and pre-emphasis control */
2829 static uint32_t
2830 intel_gen6_edp_signal_levels(uint8_t train_set)
2831 {
2832         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2833                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2834         switch (signal_levels) {
2835         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2836         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2837                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2838         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2839                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2840         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2841         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2842                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2843         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2844         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2845                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2846         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2847         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2848                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2849         default:
2850                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2851                               "0x%x\n", signal_levels);
2852                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2853         }
2854 }
2855
2856 /* Gen7's DP voltage swing and pre-emphasis control */
2857 static uint32_t
2858 intel_gen7_edp_signal_levels(uint8_t train_set)
2859 {
2860         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2861                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2862         switch (signal_levels) {
2863         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2864                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2865         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2866                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2867         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2868                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2869
2870         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2871                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2872         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2873                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2874
2875         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2876                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2877         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2878                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2879
2880         default:
2881                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2882                               "0x%x\n", signal_levels);
2883                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2884         }
2885 }
2886
2887 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2888 static uint32_t
2889 intel_hsw_signal_levels(uint8_t train_set)
2890 {
2891         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2892                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2893         switch (signal_levels) {
2894         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2895                 return DDI_BUF_TRANS_SELECT(0);
2896         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2897                 return DDI_BUF_TRANS_SELECT(1);
2898         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2899                 return DDI_BUF_TRANS_SELECT(2);
2900         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2901                 return DDI_BUF_TRANS_SELECT(3);
2902
2903         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2904                 return DDI_BUF_TRANS_SELECT(4);
2905         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2906                 return DDI_BUF_TRANS_SELECT(5);
2907         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2908                 return DDI_BUF_TRANS_SELECT(6);
2909
2910         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2911                 return DDI_BUF_TRANS_SELECT(7);
2912         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2913                 return DDI_BUF_TRANS_SELECT(8);
2914         default:
2915                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2916                               "0x%x\n", signal_levels);
2917                 return DDI_BUF_TRANS_SELECT(0);
2918         }
2919 }
2920
2921 /* Properly updates "DP" with the correct signal levels. */
2922 static void
2923 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2924 {
2925         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2926         enum port port = intel_dig_port->port;
2927         struct drm_device *dev = intel_dig_port->base.base.dev;
2928         uint32_t signal_levels, mask;
2929         uint8_t train_set = intel_dp->train_set[0];
2930
2931         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2932                 signal_levels = intel_hsw_signal_levels(train_set);
2933                 mask = DDI_BUF_EMP_MASK;
2934         } else if (IS_CHERRYVIEW(dev)) {
2935                 signal_levels = intel_chv_signal_levels(intel_dp);
2936                 mask = 0;
2937         } else if (IS_VALLEYVIEW(dev)) {
2938                 signal_levels = intel_vlv_signal_levels(intel_dp);
2939                 mask = 0;
2940         } else if (IS_GEN7(dev) && port == PORT_A) {
2941                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2942                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2943         } else if (IS_GEN6(dev) && port == PORT_A) {
2944                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2945                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2946         } else {
2947                 signal_levels = intel_gen4_signal_levels(train_set);
2948                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2949         }
2950
2951         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2952
2953         *DP = (*DP & ~mask) | signal_levels;
2954 }
2955
2956 static bool
2957 intel_dp_set_link_train(struct intel_dp *intel_dp,
2958                         uint32_t *DP,
2959                         uint8_t dp_train_pat)
2960 {
2961         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2962         struct drm_device *dev = intel_dig_port->base.base.dev;
2963         struct drm_i915_private *dev_priv = dev->dev_private;
2964         enum port port = intel_dig_port->port;
2965         uint8_t buf[sizeof(intel_dp->train_set) + 1];
2966         int ret, len;
2967
2968         if (HAS_DDI(dev)) {
2969                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2970
2971                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2972                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2973                 else
2974                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2975
2976                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2977                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2978                 case DP_TRAINING_PATTERN_DISABLE:
2979                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2980
2981                         break;
2982                 case DP_TRAINING_PATTERN_1:
2983                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2984                         break;
2985                 case DP_TRAINING_PATTERN_2:
2986                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2987                         break;
2988                 case DP_TRAINING_PATTERN_3:
2989                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2990                         break;
2991                 }
2992                 I915_WRITE(DP_TP_CTL(port), temp);
2993
2994         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2995                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2996
2997                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2998                 case DP_TRAINING_PATTERN_DISABLE:
2999                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3000                         break;
3001                 case DP_TRAINING_PATTERN_1:
3002                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3003                         break;
3004                 case DP_TRAINING_PATTERN_2:
3005                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3006                         break;
3007                 case DP_TRAINING_PATTERN_3:
3008                         DRM_ERROR("DP training pattern 3 not supported\n");
3009                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3010                         break;
3011                 }
3012
3013         } else {
3014                 if (IS_CHERRYVIEW(dev))
3015                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
3016                 else
3017                         *DP &= ~DP_LINK_TRAIN_MASK;
3018
3019                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3020                 case DP_TRAINING_PATTERN_DISABLE:
3021                         *DP |= DP_LINK_TRAIN_OFF;
3022                         break;
3023                 case DP_TRAINING_PATTERN_1:
3024                         *DP |= DP_LINK_TRAIN_PAT_1;
3025                         break;
3026                 case DP_TRAINING_PATTERN_2:
3027                         *DP |= DP_LINK_TRAIN_PAT_2;
3028                         break;
3029                 case DP_TRAINING_PATTERN_3:
3030                         if (IS_CHERRYVIEW(dev)) {
3031                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
3032                         } else {
3033                                 DRM_ERROR("DP training pattern 3 not supported\n");
3034                                 *DP |= DP_LINK_TRAIN_PAT_2;
3035                         }
3036                         break;
3037                 }
3038         }
3039
3040         I915_WRITE(intel_dp->output_reg, *DP);
3041         POSTING_READ(intel_dp->output_reg);
3042
3043         buf[0] = dp_train_pat;
3044         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3045             DP_TRAINING_PATTERN_DISABLE) {
3046                 /* don't write DP_TRAINING_LANEx_SET on disable */
3047                 len = 1;
3048         } else {
3049                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3050                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3051                 len = intel_dp->lane_count + 1;
3052         }
3053
3054         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3055                                 buf, len);
3056
3057         return ret == len;
3058 }
3059
3060 static bool
3061 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3062                         uint8_t dp_train_pat)
3063 {
3064         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3065         intel_dp_set_signal_levels(intel_dp, DP);
3066         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3067 }
3068
3069 static bool
3070 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3071                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
3072 {
3073         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3074         struct drm_device *dev = intel_dig_port->base.base.dev;
3075         struct drm_i915_private *dev_priv = dev->dev_private;
3076         int ret;
3077
3078         intel_get_adjust_train(intel_dp, link_status);
3079         intel_dp_set_signal_levels(intel_dp, DP);
3080
3081         I915_WRITE(intel_dp->output_reg, *DP);
3082         POSTING_READ(intel_dp->output_reg);
3083
3084         ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3085                                 intel_dp->train_set, intel_dp->lane_count);
3086
3087         return ret == intel_dp->lane_count;
3088 }
3089
3090 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3091 {
3092         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3093         struct drm_device *dev = intel_dig_port->base.base.dev;
3094         struct drm_i915_private *dev_priv = dev->dev_private;
3095         enum port port = intel_dig_port->port;
3096         uint32_t val;
3097
3098         if (!HAS_DDI(dev))
3099                 return;
3100
3101         val = I915_READ(DP_TP_CTL(port));
3102         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3103         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3104         I915_WRITE(DP_TP_CTL(port), val);
3105
3106         /*
3107          * On PORT_A we can have only eDP in SST mode. There the only reason
3108          * we need to set idle transmission mode is to work around a HW issue
3109          * where we enable the pipe while not in idle link-training mode.
3110          * In this case there is requirement to wait for a minimum number of
3111          * idle patterns to be sent.
3112          */
3113         if (port == PORT_A)
3114                 return;
3115
3116         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3117                      1))
3118                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3119 }
3120
3121 /* Enable corresponding port and start training pattern 1 */
3122 void
3123 intel_dp_start_link_train(struct intel_dp *intel_dp)
3124 {
3125         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3126         struct drm_device *dev = encoder->dev;
3127         int i;
3128         uint8_t voltage;
3129         int voltage_tries, loop_tries;
3130         uint32_t DP = intel_dp->DP;
3131         uint8_t link_config[2];
3132
3133         if (HAS_DDI(dev))
3134                 intel_ddi_prepare_link_retrain(encoder);
3135
3136         /* Write the link configuration data */
3137         link_config[0] = intel_dp->link_bw;
3138         link_config[1] = intel_dp->lane_count;
3139         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3140                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3141         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3142
3143         link_config[0] = 0;
3144         link_config[1] = DP_SET_ANSI_8B10B;
3145         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3146
3147         DP |= DP_PORT_EN;
3148
3149         /* clock recovery */
3150         if (!intel_dp_reset_link_train(intel_dp, &DP,
3151                                        DP_TRAINING_PATTERN_1 |
3152                                        DP_LINK_SCRAMBLING_DISABLE)) {
3153                 DRM_ERROR("failed to enable link training\n");
3154                 return;
3155         }
3156
3157         voltage = 0xff;
3158         voltage_tries = 0;
3159         loop_tries = 0;
3160         for (;;) {
3161                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3162
3163                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3164                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3165                         DRM_ERROR("failed to get link status\n");
3166                         break;
3167                 }
3168
3169                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3170                         DRM_DEBUG_KMS("clock recovery OK\n");
3171                         break;
3172                 }
3173
3174                 /* Check to see if we've tried the max voltage */
3175                 for (i = 0; i < intel_dp->lane_count; i++)
3176                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3177                                 break;
3178                 if (i == intel_dp->lane_count) {
3179                         ++loop_tries;
3180                         if (loop_tries == 5) {
3181                                 DRM_ERROR("too many full retries, give up\n");
3182                                 break;
3183                         }
3184                         intel_dp_reset_link_train(intel_dp, &DP,
3185                                                   DP_TRAINING_PATTERN_1 |
3186                                                   DP_LINK_SCRAMBLING_DISABLE);
3187                         voltage_tries = 0;
3188                         continue;
3189                 }
3190
3191                 /* Check to see if we've tried the same voltage 5 times */
3192                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3193                         ++voltage_tries;
3194                         if (voltage_tries == 5) {
3195                                 DRM_ERROR("too many voltage retries, give up\n");
3196                                 break;
3197                         }
3198                 } else
3199                         voltage_tries = 0;
3200                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3201
3202                 /* Update training set as requested by target */
3203                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3204                         DRM_ERROR("failed to update link training\n");
3205                         break;
3206                 }
3207         }
3208
3209         intel_dp->DP = DP;
3210 }
3211
3212 void
3213 intel_dp_complete_link_train(struct intel_dp *intel_dp)
3214 {
3215         bool channel_eq = false;
3216         int tries, cr_tries;
3217         uint32_t DP = intel_dp->DP;
3218         uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3219
3220         /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3221         if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3222                 training_pattern = DP_TRAINING_PATTERN_3;
3223
3224         /* channel equalization */
3225         if (!intel_dp_set_link_train(intel_dp, &DP,
3226                                      training_pattern |
3227                                      DP_LINK_SCRAMBLING_DISABLE)) {
3228                 DRM_ERROR("failed to start channel equalization\n");
3229                 return;
3230         }
3231
3232         tries = 0;
3233         cr_tries = 0;
3234         channel_eq = false;
3235         for (;;) {
3236                 uint8_t link_status[DP_LINK_STATUS_SIZE];
3237
3238                 if (cr_tries > 5) {
3239                         DRM_ERROR("failed to train DP, aborting\n");
3240                         break;
3241                 }
3242
3243                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3244                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3245                         DRM_ERROR("failed to get link status\n");
3246                         break;
3247                 }
3248
3249                 /* Make sure clock is still ok */
3250                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3251                         intel_dp_start_link_train(intel_dp);
3252                         intel_dp_set_link_train(intel_dp, &DP,
3253                                                 training_pattern |
3254                                                 DP_LINK_SCRAMBLING_DISABLE);
3255                         cr_tries++;
3256                         continue;
3257                 }
3258
3259                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3260                         channel_eq = true;
3261                         break;
3262                 }
3263
3264                 /* Try 5 times, then try clock recovery if that fails */
3265                 if (tries > 5) {
3266                         intel_dp_link_down(intel_dp);
3267                         intel_dp_start_link_train(intel_dp);
3268                         intel_dp_set_link_train(intel_dp, &DP,
3269                                                 training_pattern |
3270                                                 DP_LINK_SCRAMBLING_DISABLE);
3271                         tries = 0;
3272                         cr_tries++;
3273                         continue;
3274                 }
3275
3276                 /* Update training set as requested by target */
3277                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3278                         DRM_ERROR("failed to update link training\n");
3279                         break;
3280                 }
3281                 ++tries;
3282         }
3283
3284         intel_dp_set_idle_link_train(intel_dp);
3285
3286         intel_dp->DP = DP;
3287
3288         if (channel_eq)
3289                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3290
3291 }
3292
3293 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3294 {
3295         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3296                                 DP_TRAINING_PATTERN_DISABLE);
3297 }
3298
3299 static void
3300 intel_dp_link_down(struct intel_dp *intel_dp)
3301 {
3302         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3303         enum port port = intel_dig_port->port;
3304         struct drm_device *dev = intel_dig_port->base.base.dev;
3305         struct drm_i915_private *dev_priv = dev->dev_private;
3306         struct intel_crtc *intel_crtc =
3307                 to_intel_crtc(intel_dig_port->base.base.crtc);
3308         uint32_t DP = intel_dp->DP;
3309
3310         if (WARN_ON(HAS_DDI(dev)))
3311                 return;
3312
3313         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3314                 return;
3315
3316         DRM_DEBUG_KMS("\n");
3317
3318         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3319                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3320                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3321         } else {
3322                 if (IS_CHERRYVIEW(dev))
3323                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3324                 else
3325                         DP &= ~DP_LINK_TRAIN_MASK;
3326                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3327         }
3328         POSTING_READ(intel_dp->output_reg);
3329
3330         if (HAS_PCH_IBX(dev) &&
3331             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3332                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3333
3334                 /* Hardware workaround: leaving our transcoder select
3335                  * set to transcoder B while it's off will prevent the
3336                  * corresponding HDMI output on transcoder A.
3337                  *
3338                  * Combine this with another hardware workaround:
3339                  * transcoder select bit can only be cleared while the
3340                  * port is enabled.
3341                  */
3342                 DP &= ~DP_PIPEB_SELECT;
3343                 I915_WRITE(intel_dp->output_reg, DP);
3344
3345                 /* Changes to enable or select take place the vblank
3346                  * after being written.
3347                  */
3348                 if (WARN_ON(crtc == NULL)) {
3349                         /* We should never try to disable a port without a crtc
3350                          * attached. For paranoia keep the code around for a
3351                          * bit. */
3352                         POSTING_READ(intel_dp->output_reg);
3353                         msleep(50);
3354                 } else
3355                         intel_wait_for_vblank(dev, intel_crtc->pipe);
3356         }
3357
3358         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
3359         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3360         POSTING_READ(intel_dp->output_reg);
3361         msleep(intel_dp->panel_power_down_delay);
3362 }
3363
3364 static bool
3365 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3366 {
3367         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3368         struct drm_device *dev = dig_port->base.base.dev;
3369         struct drm_i915_private *dev_priv = dev->dev_private;
3370
3371         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3372
3373         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3374                                     sizeof(intel_dp->dpcd)) < 0)
3375                 return false; /* aux transfer failed */
3376
3377         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3378                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3379         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3380
3381         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3382                 return false; /* DPCD not present */
3383
3384         /* Check if the panel supports PSR */
3385         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3386         if (is_edp(intel_dp)) {
3387                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3388                                         intel_dp->psr_dpcd,
3389                                         sizeof(intel_dp->psr_dpcd));
3390                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3391                         dev_priv->psr.sink_support = true;
3392                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3393                 }
3394         }
3395
3396         /* Training Pattern 3 support */
3397         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3398             intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3399                 intel_dp->use_tps3 = true;
3400                 DRM_DEBUG_KMS("Displayport TPS3 supported");
3401         } else
3402                 intel_dp->use_tps3 = false;
3403
3404         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3405               DP_DWN_STRM_PORT_PRESENT))
3406                 return true; /* native DP sink */
3407
3408         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3409                 return true; /* no per-port downstream info */
3410
3411         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3412                                     intel_dp->downstream_ports,
3413                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3414                 return false; /* downstream port status fetch failed */
3415
3416         return true;
3417 }
3418
3419 static void
3420 intel_dp_probe_oui(struct intel_dp *intel_dp)
3421 {
3422         u8 buf[3];
3423
3424         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3425                 return;
3426
3427         intel_edp_panel_vdd_on(intel_dp);
3428
3429         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3430                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3431                               buf[0], buf[1], buf[2]);
3432
3433         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3434                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3435                               buf[0], buf[1], buf[2]);
3436
3437         intel_edp_panel_vdd_off(intel_dp, false);
3438 }
3439
3440 static bool
3441 intel_dp_probe_mst(struct intel_dp *intel_dp)
3442 {
3443         u8 buf[1];
3444
3445         if (!intel_dp->can_mst)
3446                 return false;
3447
3448         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3449                 return false;
3450
3451         intel_edp_panel_vdd_on(intel_dp);
3452         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3453                 if (buf[0] & DP_MST_CAP) {
3454                         DRM_DEBUG_KMS("Sink is MST capable\n");
3455                         intel_dp->is_mst = true;
3456                 } else {
3457                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3458                         intel_dp->is_mst = false;
3459                 }
3460         }
3461         intel_edp_panel_vdd_off(intel_dp, false);
3462
3463         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3464         return intel_dp->is_mst;
3465 }
3466
3467 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3468 {
3469         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3470         struct drm_device *dev = intel_dig_port->base.base.dev;
3471         struct intel_crtc *intel_crtc =
3472                 to_intel_crtc(intel_dig_port->base.base.crtc);
3473         u8 buf[1];
3474
3475         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3476                 return -EAGAIN;
3477
3478         if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3479                 return -ENOTTY;
3480
3481         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3482                                DP_TEST_SINK_START) < 0)
3483                 return -EAGAIN;
3484
3485         /* Wait 2 vblanks to be sure we will have the correct CRC value */
3486         intel_wait_for_vblank(dev, intel_crtc->pipe);
3487         intel_wait_for_vblank(dev, intel_crtc->pipe);
3488
3489         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3490                 return -EAGAIN;
3491
3492         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3493         return 0;
3494 }
3495
3496 static bool
3497 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3498 {
3499         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3500                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
3501                                        sink_irq_vector, 1) == 1;
3502 }
3503
3504 static bool
3505 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3506 {
3507         int ret;
3508
3509         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3510                                              DP_SINK_COUNT_ESI,
3511                                              sink_irq_vector, 14);
3512         if (ret != 14)
3513                 return false;
3514
3515         return true;
3516 }
3517
3518 static void
3519 intel_dp_handle_test_request(struct intel_dp *intel_dp)
3520 {
3521         /* NAK by default */
3522         drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3523 }
3524
3525 static int
3526 intel_dp_check_mst_status(struct intel_dp *intel_dp)
3527 {
3528         bool bret;
3529
3530         if (intel_dp->is_mst) {
3531                 u8 esi[16] = { 0 };
3532                 int ret = 0;
3533                 int retry;
3534                 bool handled;
3535                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3536 go_again:
3537                 if (bret == true) {
3538
3539                         /* check link status - esi[10] = 0x200c */
3540                         if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3541                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3542                                 intel_dp_start_link_train(intel_dp);
3543                                 intel_dp_complete_link_train(intel_dp);
3544                                 intel_dp_stop_link_train(intel_dp);
3545                         }
3546
3547                         DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3548                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3549
3550                         if (handled) {
3551                                 for (retry = 0; retry < 3; retry++) {
3552                                         int wret;
3553                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
3554                                                                  DP_SINK_COUNT_ESI+1,
3555                                                                  &esi[1], 3);
3556                                         if (wret == 3) {
3557                                                 break;
3558                                         }
3559                                 }
3560
3561                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3562                                 if (bret == true) {
3563                                         DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3564                                         goto go_again;
3565                                 }
3566                         } else
3567                                 ret = 0;
3568
3569                         return ret;
3570                 } else {
3571                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3572                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3573                         intel_dp->is_mst = false;
3574                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3575                         /* send a hotplug event */
3576                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3577                 }
3578         }
3579         return -EINVAL;
3580 }
3581
3582 /*
3583  * According to DP spec
3584  * 5.1.2:
3585  *  1. Read DPCD
3586  *  2. Configure link according to Receiver Capabilities
3587  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
3588  *  4. Check link status on receipt of hot-plug interrupt
3589  */
3590 void
3591 intel_dp_check_link_status(struct intel_dp *intel_dp)
3592 {
3593         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3594         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3595         u8 sink_irq_vector;
3596         u8 link_status[DP_LINK_STATUS_SIZE];
3597
3598         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3599
3600         if (!intel_encoder->connectors_active)
3601                 return;
3602
3603         if (WARN_ON(!intel_encoder->base.crtc))
3604                 return;
3605
3606         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3607                 return;
3608
3609         /* Try to read receiver status if the link appears to be up */
3610         if (!intel_dp_get_link_status(intel_dp, link_status)) {
3611                 return;
3612         }
3613
3614         /* Now read the DPCD to see if it's actually running */
3615         if (!intel_dp_get_dpcd(intel_dp)) {
3616                 return;
3617         }
3618
3619         /* Try to read the source of the interrupt */
3620         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3621             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3622                 /* Clear interrupt source */
3623                 drm_dp_dpcd_writeb(&intel_dp->aux,
3624                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
3625                                    sink_irq_vector);
3626
3627                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3628                         intel_dp_handle_test_request(intel_dp);
3629                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3630                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3631         }
3632
3633         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3634                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3635                               intel_encoder->base.name);
3636                 intel_dp_start_link_train(intel_dp);
3637                 intel_dp_complete_link_train(intel_dp);
3638                 intel_dp_stop_link_train(intel_dp);
3639         }
3640 }
3641
3642 /* XXX this is probably wrong for multiple downstream ports */
3643 static enum drm_connector_status
3644 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3645 {
3646         uint8_t *dpcd = intel_dp->dpcd;
3647         uint8_t type;
3648
3649         if (!intel_dp_get_dpcd(intel_dp))
3650                 return connector_status_disconnected;
3651
3652         /* if there's no downstream port, we're done */
3653         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3654                 return connector_status_connected;
3655
3656         /* If we're HPD-aware, SINK_COUNT changes dynamically */
3657         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3658             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3659                 uint8_t reg;
3660
3661                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3662                                             &reg, 1) < 0)
3663                         return connector_status_unknown;
3664
3665                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3666                                               : connector_status_disconnected;
3667         }
3668
3669         /* If no HPD, poke DDC gently */
3670         if (drm_probe_ddc(&intel_dp->aux.ddc))
3671                 return connector_status_connected;
3672
3673         /* Well we tried, say unknown for unreliable port types */
3674         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3675                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3676                 if (type == DP_DS_PORT_TYPE_VGA ||
3677                     type == DP_DS_PORT_TYPE_NON_EDID)
3678                         return connector_status_unknown;
3679         } else {
3680                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3681                         DP_DWN_STRM_PORT_TYPE_MASK;
3682                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3683                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
3684                         return connector_status_unknown;
3685         }
3686
3687         /* Anything else is out of spec, warn and ignore */
3688         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3689         return connector_status_disconnected;
3690 }
3691
3692 static enum drm_connector_status
3693 ironlake_dp_detect(struct intel_dp *intel_dp)
3694 {
3695         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3696         struct drm_i915_private *dev_priv = dev->dev_private;
3697         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3698         enum drm_connector_status status;
3699
3700         /* Can't disconnect eDP, but you can close the lid... */
3701         if (is_edp(intel_dp)) {
3702                 status = intel_panel_detect(dev);
3703                 if (status == connector_status_unknown)
3704                         status = connector_status_connected;
3705                 return status;
3706         }
3707
3708         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3709                 return connector_status_disconnected;
3710
3711         return intel_dp_detect_dpcd(intel_dp);
3712 }
3713
3714 static enum drm_connector_status
3715 g4x_dp_detect(struct intel_dp *intel_dp)
3716 {
3717         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3718         struct drm_i915_private *dev_priv = dev->dev_private;
3719         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3720         uint32_t bit;
3721
3722         /* Can't disconnect eDP, but you can close the lid... */
3723         if (is_edp(intel_dp)) {
3724                 enum drm_connector_status status;
3725
3726                 status = intel_panel_detect(dev);
3727                 if (status == connector_status_unknown)
3728                         status = connector_status_connected;
3729                 return status;
3730         }
3731
3732         if (IS_VALLEYVIEW(dev)) {
3733                 switch (intel_dig_port->port) {
3734                 case PORT_B:
3735                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3736                         break;
3737                 case PORT_C:
3738                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3739                         break;
3740                 case PORT_D:
3741                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3742                         break;
3743                 default:
3744                         return connector_status_unknown;
3745                 }
3746         } else {
3747                 switch (intel_dig_port->port) {
3748                 case PORT_B:
3749                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3750                         break;
3751                 case PORT_C:
3752                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3753                         break;
3754                 case PORT_D:
3755                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3756                         break;
3757                 default:
3758                         return connector_status_unknown;
3759                 }
3760         }
3761
3762         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3763                 return connector_status_disconnected;
3764
3765         return intel_dp_detect_dpcd(intel_dp);
3766 }
3767
3768 static struct edid *
3769 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3770 {
3771         struct intel_connector *intel_connector = to_intel_connector(connector);
3772
3773         /* use cached edid if we have one */
3774         if (intel_connector->edid) {
3775                 /* invalid edid */
3776                 if (IS_ERR(intel_connector->edid))
3777                         return NULL;
3778
3779                 return drm_edid_duplicate(intel_connector->edid);
3780         }
3781
3782         return drm_get_edid(connector, adapter);
3783 }
3784
3785 static int
3786 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3787 {
3788         struct intel_connector *intel_connector = to_intel_connector(connector);
3789
3790         /* use cached edid if we have one */
3791         if (intel_connector->edid) {
3792                 /* invalid edid */
3793                 if (IS_ERR(intel_connector->edid))
3794                         return 0;
3795
3796                 return intel_connector_update_modes(connector,
3797                                                     intel_connector->edid);
3798         }
3799
3800         return intel_ddc_get_modes(connector, adapter);
3801 }
3802
3803 static enum drm_connector_status
3804 intel_dp_detect(struct drm_connector *connector, bool force)
3805 {
3806         struct intel_dp *intel_dp = intel_attached_dp(connector);
3807         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3808         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3809         struct drm_device *dev = connector->dev;
3810         struct drm_i915_private *dev_priv = dev->dev_private;
3811         enum drm_connector_status status;
3812         enum intel_display_power_domain power_domain;
3813         struct edid *edid = NULL;
3814         bool ret;
3815
3816         power_domain = intel_display_port_power_domain(intel_encoder);
3817         intel_display_power_get(dev_priv, power_domain);
3818
3819         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3820                       connector->base.id, connector->name);
3821
3822         if (intel_dp->is_mst) {
3823                 /* MST devices are disconnected from a monitor POV */
3824                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3825                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3826                 status = connector_status_disconnected;
3827                 goto out;
3828         }
3829
3830         intel_dp->has_audio = false;
3831
3832         if (HAS_PCH_SPLIT(dev))
3833                 status = ironlake_dp_detect(intel_dp);
3834         else
3835                 status = g4x_dp_detect(intel_dp);
3836
3837         if (status != connector_status_connected)
3838                 goto out;
3839
3840         intel_dp_probe_oui(intel_dp);
3841
3842         ret = intel_dp_probe_mst(intel_dp);
3843         if (ret) {
3844                 /* if we are in MST mode then this connector
3845                    won't appear connected or have anything with EDID on it */
3846                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3847                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3848                 status = connector_status_disconnected;
3849                 goto out;
3850         }
3851
3852         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3853                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3854         } else {
3855                 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3856                 if (edid) {
3857                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3858                         kfree(edid);
3859                 }
3860         }
3861
3862         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3863                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3864         status = connector_status_connected;
3865
3866 out:
3867         intel_display_power_put(dev_priv, power_domain);
3868         return status;
3869 }
3870
3871 static int intel_dp_get_modes(struct drm_connector *connector)
3872 {
3873         struct intel_dp *intel_dp = intel_attached_dp(connector);
3874         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3875         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3876         struct intel_connector *intel_connector = to_intel_connector(connector);
3877         struct drm_device *dev = connector->dev;
3878         struct drm_i915_private *dev_priv = dev->dev_private;
3879         enum intel_display_power_domain power_domain;
3880         int ret;
3881
3882         /* We should parse the EDID data and find out if it has an audio sink
3883          */
3884
3885         power_domain = intel_display_port_power_domain(intel_encoder);
3886         intel_display_power_get(dev_priv, power_domain);
3887
3888         ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3889         intel_display_power_put(dev_priv, power_domain);
3890         if (ret)
3891                 return ret;
3892
3893         /* if eDP has no EDID, fall back to fixed mode */
3894         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3895                 struct drm_display_mode *mode;
3896                 mode = drm_mode_duplicate(dev,
3897                                           intel_connector->panel.fixed_mode);
3898                 if (mode) {
3899                         drm_mode_probed_add(connector, mode);
3900                         return 1;
3901                 }
3902         }
3903         return 0;
3904 }
3905
3906 static bool
3907 intel_dp_detect_audio(struct drm_connector *connector)
3908 {
3909         struct intel_dp *intel_dp = intel_attached_dp(connector);
3910         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3911         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3912         struct drm_device *dev = connector->dev;
3913         struct drm_i915_private *dev_priv = dev->dev_private;
3914         enum intel_display_power_domain power_domain;
3915         struct edid *edid;
3916         bool has_audio = false;
3917
3918         power_domain = intel_display_port_power_domain(intel_encoder);
3919         intel_display_power_get(dev_priv, power_domain);
3920
3921         edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3922         if (edid) {
3923                 has_audio = drm_detect_monitor_audio(edid);
3924                 kfree(edid);
3925         }
3926
3927         intel_display_power_put(dev_priv, power_domain);
3928
3929         return has_audio;
3930 }
3931
3932 static int
3933 intel_dp_set_property(struct drm_connector *connector,
3934                       struct drm_property *property,
3935                       uint64_t val)
3936 {
3937         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3938         struct intel_connector *intel_connector = to_intel_connector(connector);
3939         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3940         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3941         int ret;
3942
3943         ret = drm_object_property_set_value(&connector->base, property, val);
3944         if (ret)
3945                 return ret;
3946
3947         if (property == dev_priv->force_audio_property) {
3948                 int i = val;
3949                 bool has_audio;
3950
3951                 if (i == intel_dp->force_audio)
3952                         return 0;
3953
3954                 intel_dp->force_audio = i;
3955
3956                 if (i == HDMI_AUDIO_AUTO)
3957                         has_audio = intel_dp_detect_audio(connector);
3958                 else
3959                         has_audio = (i == HDMI_AUDIO_ON);
3960
3961                 if (has_audio == intel_dp->has_audio)
3962                         return 0;
3963
3964                 intel_dp->has_audio = has_audio;
3965                 goto done;
3966         }
3967
3968         if (property == dev_priv->broadcast_rgb_property) {
3969                 bool old_auto = intel_dp->color_range_auto;
3970                 uint32_t old_range = intel_dp->color_range;
3971
3972                 switch (val) {
3973                 case INTEL_BROADCAST_RGB_AUTO:
3974                         intel_dp->color_range_auto = true;
3975                         break;
3976                 case INTEL_BROADCAST_RGB_FULL:
3977                         intel_dp->color_range_auto = false;
3978                         intel_dp->color_range = 0;
3979                         break;
3980                 case INTEL_BROADCAST_RGB_LIMITED:
3981                         intel_dp->color_range_auto = false;
3982                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3983                         break;
3984                 default:
3985                         return -EINVAL;
3986                 }
3987
3988                 if (old_auto == intel_dp->color_range_auto &&
3989                     old_range == intel_dp->color_range)
3990                         return 0;
3991
3992                 goto done;
3993         }
3994
3995         if (is_edp(intel_dp) &&
3996             property == connector->dev->mode_config.scaling_mode_property) {
3997                 if (val == DRM_MODE_SCALE_NONE) {
3998                         DRM_DEBUG_KMS("no scaling not supported\n");
3999                         return -EINVAL;
4000                 }
4001
4002                 if (intel_connector->panel.fitting_mode == val) {
4003                         /* the eDP scaling property is not changed */
4004                         return 0;
4005                 }
4006                 intel_connector->panel.fitting_mode = val;
4007
4008                 goto done;
4009         }
4010
4011         return -EINVAL;
4012
4013 done:
4014         if (intel_encoder->base.crtc)
4015                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4016
4017         return 0;
4018 }
4019
4020 static void
4021 intel_dp_connector_destroy(struct drm_connector *connector)
4022 {
4023         struct intel_connector *intel_connector = to_intel_connector(connector);
4024
4025         if (!IS_ERR_OR_NULL(intel_connector->edid))
4026                 kfree(intel_connector->edid);
4027
4028         /* Can't call is_edp() since the encoder may have been destroyed
4029          * already. */
4030         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4031                 intel_panel_fini(&intel_connector->panel);
4032
4033         drm_connector_cleanup(connector);
4034         kfree(connector);
4035 }
4036
4037 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4038 {
4039         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4040         struct intel_dp *intel_dp = &intel_dig_port->dp;
4041         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4042
4043         drm_dp_aux_unregister(&intel_dp->aux);
4044         intel_dp_mst_encoder_cleanup(intel_dig_port);
4045         drm_encoder_cleanup(encoder);
4046         if (is_edp(intel_dp)) {
4047                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4048                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4049                 edp_panel_vdd_off_sync(intel_dp);
4050                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4051                 if (intel_dp->edp_notifier.notifier_call) {
4052                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4053                         intel_dp->edp_notifier.notifier_call = NULL;
4054                 }
4055         }
4056         kfree(intel_dig_port);
4057 }
4058
4059 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4060 {
4061         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4062
4063         if (!is_edp(intel_dp))
4064                 return;
4065
4066         edp_panel_vdd_off_sync(intel_dp);
4067 }
4068
4069 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4070 {
4071         intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4072 }
4073
4074 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4075         .dpms = intel_connector_dpms,
4076         .detect = intel_dp_detect,
4077         .fill_modes = drm_helper_probe_single_connector_modes,
4078         .set_property = intel_dp_set_property,
4079         .destroy = intel_dp_connector_destroy,
4080 };
4081
4082 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4083         .get_modes = intel_dp_get_modes,
4084         .mode_valid = intel_dp_mode_valid,
4085         .best_encoder = intel_best_encoder,
4086 };
4087
4088 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4089         .reset = intel_dp_encoder_reset,
4090         .destroy = intel_dp_encoder_destroy,
4091 };
4092
4093 void
4094 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4095 {
4096         return;
4097 }
4098
4099 bool
4100 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4101 {
4102         struct intel_dp *intel_dp = &intel_dig_port->dp;
4103         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4104         struct drm_device *dev = intel_dig_port->base.base.dev;
4105         struct drm_i915_private *dev_priv = dev->dev_private;
4106         enum intel_display_power_domain power_domain;
4107         bool ret = true;
4108
4109         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4110                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4111
4112         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4113                       port_name(intel_dig_port->port),
4114                       long_hpd ? "long" : "short");
4115
4116         power_domain = intel_display_port_power_domain(intel_encoder);
4117         intel_display_power_get(dev_priv, power_domain);
4118
4119         if (long_hpd) {
4120                 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4121                         goto mst_fail;
4122
4123                 if (!intel_dp_get_dpcd(intel_dp)) {
4124                         goto mst_fail;
4125                 }
4126
4127                 intel_dp_probe_oui(intel_dp);
4128
4129                 if (!intel_dp_probe_mst(intel_dp))
4130                         goto mst_fail;
4131
4132         } else {
4133                 if (intel_dp->is_mst) {
4134                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4135                                 goto mst_fail;
4136                 }
4137
4138                 if (!intel_dp->is_mst) {
4139                         /*
4140                          * we'll check the link status via the normal hot plug path later -
4141                          * but for short hpds we should check it now
4142                          */
4143                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4144                         intel_dp_check_link_status(intel_dp);
4145                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4146                 }
4147         }
4148         ret = false;
4149         goto put_power;
4150 mst_fail:
4151         /* if we were in MST mode, and device is not there get out of MST mode */
4152         if (intel_dp->is_mst) {
4153                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4154                 intel_dp->is_mst = false;
4155                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4156         }
4157 put_power:
4158         intel_display_power_put(dev_priv, power_domain);
4159
4160         return ret;
4161 }
4162
4163 /* Return which DP Port should be selected for Transcoder DP control */
4164 int
4165 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4166 {
4167         struct drm_device *dev = crtc->dev;
4168         struct intel_encoder *intel_encoder;
4169         struct intel_dp *intel_dp;
4170
4171         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4172                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4173
4174                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4175                     intel_encoder->type == INTEL_OUTPUT_EDP)
4176                         return intel_dp->output_reg;
4177         }
4178
4179         return -1;
4180 }
4181
4182 /* check the VBT to see whether the eDP is on DP-D port */
4183 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4184 {
4185         struct drm_i915_private *dev_priv = dev->dev_private;
4186         union child_device_config *p_child;
4187         int i;
4188         static const short port_mapping[] = {
4189                 [PORT_B] = PORT_IDPB,
4190                 [PORT_C] = PORT_IDPC,
4191                 [PORT_D] = PORT_IDPD,
4192         };
4193
4194         if (port == PORT_A)
4195                 return true;
4196
4197         if (!dev_priv->vbt.child_dev_num)
4198                 return false;
4199
4200         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4201                 p_child = dev_priv->vbt.child_dev + i;
4202
4203                 if (p_child->common.dvo_port == port_mapping[port] &&
4204                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4205                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4206                         return true;
4207         }
4208         return false;
4209 }
4210
4211 void
4212 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4213 {
4214         struct intel_connector *intel_connector = to_intel_connector(connector);
4215
4216         intel_attach_force_audio_property(connector);
4217         intel_attach_broadcast_rgb_property(connector);
4218         intel_dp->color_range_auto = true;
4219
4220         if (is_edp(intel_dp)) {
4221                 drm_mode_create_scaling_mode_property(connector->dev);
4222                 drm_object_attach_property(
4223                         &connector->base,
4224                         connector->dev->mode_config.scaling_mode_property,
4225                         DRM_MODE_SCALE_ASPECT);
4226                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4227         }
4228 }
4229
4230 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4231 {
4232         intel_dp->last_power_cycle = jiffies;
4233         intel_dp->last_power_on = jiffies;
4234         intel_dp->last_backlight_off = jiffies;
4235 }
4236
4237 static void
4238 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4239                                     struct intel_dp *intel_dp,
4240                                     struct edp_power_seq *out)
4241 {
4242         struct drm_i915_private *dev_priv = dev->dev_private;
4243         struct edp_power_seq cur, vbt, spec, final;
4244         u32 pp_on, pp_off, pp_div, pp;
4245         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4246
4247         if (HAS_PCH_SPLIT(dev)) {
4248                 pp_ctrl_reg = PCH_PP_CONTROL;
4249                 pp_on_reg = PCH_PP_ON_DELAYS;
4250                 pp_off_reg = PCH_PP_OFF_DELAYS;
4251                 pp_div_reg = PCH_PP_DIVISOR;
4252         } else {
4253                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4254
4255                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4256                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4257                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4258                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4259         }
4260
4261         /* Workaround: Need to write PP_CONTROL with the unlock key as
4262          * the very first thing. */
4263         pp = ironlake_get_pp_control(intel_dp);
4264         I915_WRITE(pp_ctrl_reg, pp);
4265
4266         pp_on = I915_READ(pp_on_reg);
4267         pp_off = I915_READ(pp_off_reg);
4268         pp_div = I915_READ(pp_div_reg);
4269
4270         /* Pull timing values out of registers */
4271         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4272                 PANEL_POWER_UP_DELAY_SHIFT;
4273
4274         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4275                 PANEL_LIGHT_ON_DELAY_SHIFT;
4276
4277         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4278                 PANEL_LIGHT_OFF_DELAY_SHIFT;
4279
4280         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4281                 PANEL_POWER_DOWN_DELAY_SHIFT;
4282
4283         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4284                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4285
4286         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4287                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4288
4289         vbt = dev_priv->vbt.edp_pps;
4290
4291         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4292          * our hw here, which are all in 100usec. */
4293         spec.t1_t3 = 210 * 10;
4294         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4295         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4296         spec.t10 = 500 * 10;
4297         /* This one is special and actually in units of 100ms, but zero
4298          * based in the hw (so we need to add 100 ms). But the sw vbt
4299          * table multiplies it with 1000 to make it in units of 100usec,
4300          * too. */
4301         spec.t11_t12 = (510 + 100) * 10;
4302
4303         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4304                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4305
4306         /* Use the max of the register settings and vbt. If both are
4307          * unset, fall back to the spec limits. */
4308 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
4309                                        spec.field : \
4310                                        max(cur.field, vbt.field))
4311         assign_final(t1_t3);
4312         assign_final(t8);
4313         assign_final(t9);
4314         assign_final(t10);
4315         assign_final(t11_t12);
4316 #undef assign_final
4317
4318 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
4319         intel_dp->panel_power_up_delay = get_delay(t1_t3);
4320         intel_dp->backlight_on_delay = get_delay(t8);
4321         intel_dp->backlight_off_delay = get_delay(t9);
4322         intel_dp->panel_power_down_delay = get_delay(t10);
4323         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4324 #undef get_delay
4325
4326         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4327                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4328                       intel_dp->panel_power_cycle_delay);
4329
4330         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4331                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4332
4333         if (out)
4334                 *out = final;
4335 }
4336
4337 static void
4338 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4339                                               struct intel_dp *intel_dp,
4340                                               struct edp_power_seq *seq)
4341 {
4342         struct drm_i915_private *dev_priv = dev->dev_private;
4343         u32 pp_on, pp_off, pp_div, port_sel = 0;
4344         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4345         int pp_on_reg, pp_off_reg, pp_div_reg;
4346         enum port port = dp_to_dig_port(intel_dp)->port;
4347
4348         if (HAS_PCH_SPLIT(dev)) {
4349                 pp_on_reg = PCH_PP_ON_DELAYS;
4350                 pp_off_reg = PCH_PP_OFF_DELAYS;
4351                 pp_div_reg = PCH_PP_DIVISOR;
4352         } else {
4353                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4354
4355                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4356                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4357                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4358         }
4359
4360         /*
4361          * And finally store the new values in the power sequencer. The
4362          * backlight delays are set to 1 because we do manual waits on them. For
4363          * T8, even BSpec recommends doing it. For T9, if we don't do this,
4364          * we'll end up waiting for the backlight off delay twice: once when we
4365          * do the manual sleep, and once when we disable the panel and wait for
4366          * the PP_STATUS bit to become zero.
4367          */
4368         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4369                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4370         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4371                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4372         /* Compute the divisor for the pp clock, simply match the Bspec
4373          * formula. */
4374         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4375         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4376                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
4377
4378         /* Haswell doesn't have any port selection bits for the panel
4379          * power sequencer any more. */
4380         if (IS_VALLEYVIEW(dev)) {
4381                 port_sel = PANEL_PORT_SELECT_VLV(port);
4382         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4383                 if (port == PORT_A)
4384                         port_sel = PANEL_PORT_SELECT_DPA;
4385                 else
4386                         port_sel = PANEL_PORT_SELECT_DPD;
4387         }
4388
4389         pp_on |= port_sel;
4390
4391         I915_WRITE(pp_on_reg, pp_on);
4392         I915_WRITE(pp_off_reg, pp_off);
4393         I915_WRITE(pp_div_reg, pp_div);
4394
4395         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4396                       I915_READ(pp_on_reg),
4397                       I915_READ(pp_off_reg),
4398                       I915_READ(pp_div_reg));
4399 }
4400
4401 void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4402 {
4403         struct drm_i915_private *dev_priv = dev->dev_private;
4404         struct intel_encoder *encoder;
4405         struct intel_dp *intel_dp = NULL;
4406         struct intel_crtc_config *config = NULL;
4407         struct intel_crtc *intel_crtc = NULL;
4408         struct intel_connector *intel_connector = dev_priv->drrs.connector;
4409         u32 reg, val;
4410         enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4411
4412         if (refresh_rate <= 0) {
4413                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4414                 return;
4415         }
4416
4417         if (intel_connector == NULL) {
4418                 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4419                 return;
4420         }
4421
4422         /*
4423          * FIXME: This needs proper synchronization with psr state. But really
4424          * hard to tell without seeing the user of this function of this code.
4425          * Check locking and ordering once that lands.
4426          */
4427         if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4428                 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4429                 return;
4430         }
4431
4432         encoder = intel_attached_encoder(&intel_connector->base);
4433         intel_dp = enc_to_intel_dp(&encoder->base);
4434         intel_crtc = encoder->new_crtc;
4435
4436         if (!intel_crtc) {
4437                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4438                 return;
4439         }
4440
4441         config = &intel_crtc->config;
4442
4443         if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4444                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4445                 return;
4446         }
4447
4448         if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4449                 index = DRRS_LOW_RR;
4450
4451         if (index == intel_dp->drrs_state.refresh_rate_type) {
4452                 DRM_DEBUG_KMS(
4453                         "DRRS requested for previously set RR...ignoring\n");
4454                 return;
4455         }
4456
4457         if (!intel_crtc->active) {
4458                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4459                 return;
4460         }
4461
4462         if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4463                 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4464                 val = I915_READ(reg);
4465                 if (index > DRRS_HIGH_RR) {
4466                         val |= PIPECONF_EDP_RR_MODE_SWITCH;
4467                         intel_dp_set_m_n(intel_crtc);
4468                 } else {
4469                         val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4470                 }
4471                 I915_WRITE(reg, val);
4472         }
4473
4474         /*
4475          * mutex taken to ensure that there is no race between differnt
4476          * drrs calls trying to update refresh rate. This scenario may occur
4477          * in future when idleness detection based DRRS in kernel and
4478          * possible calls from user space to set differnt RR are made.
4479          */
4480
4481         mutex_lock(&intel_dp->drrs_state.mutex);
4482
4483         intel_dp->drrs_state.refresh_rate_type = index;
4484
4485         mutex_unlock(&intel_dp->drrs_state.mutex);
4486
4487         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4488 }
4489
4490 static struct drm_display_mode *
4491 intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4492                         struct intel_connector *intel_connector,
4493                         struct drm_display_mode *fixed_mode)
4494 {
4495         struct drm_connector *connector = &intel_connector->base;
4496         struct intel_dp *intel_dp = &intel_dig_port->dp;
4497         struct drm_device *dev = intel_dig_port->base.base.dev;
4498         struct drm_i915_private *dev_priv = dev->dev_private;
4499         struct drm_display_mode *downclock_mode = NULL;
4500
4501         if (INTEL_INFO(dev)->gen <= 6) {
4502                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4503                 return NULL;
4504         }
4505
4506         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4507                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4508                 return NULL;
4509         }
4510
4511         downclock_mode = intel_find_panel_downclock
4512                                         (dev, fixed_mode, connector);
4513
4514         if (!downclock_mode) {
4515                 DRM_DEBUG_KMS("DRRS not supported\n");
4516                 return NULL;
4517         }
4518
4519         dev_priv->drrs.connector = intel_connector;
4520
4521         mutex_init(&intel_dp->drrs_state.mutex);
4522
4523         intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4524
4525         intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4526         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4527         return downclock_mode;
4528 }
4529
4530 void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4531 {
4532         struct drm_device *dev = intel_encoder->base.dev;
4533         struct drm_i915_private *dev_priv = dev->dev_private;
4534         struct intel_dp *intel_dp;
4535         enum intel_display_power_domain power_domain;
4536
4537         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4538                 return;
4539
4540         intel_dp = enc_to_intel_dp(&intel_encoder->base);
4541         if (!edp_have_panel_vdd(intel_dp))
4542                 return;
4543         /*
4544          * The VDD bit needs a power domain reference, so if the bit is
4545          * already enabled when we boot or resume, grab this reference and
4546          * schedule a vdd off, so we don't hold on to the reference
4547          * indefinitely.
4548          */
4549         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4550         power_domain = intel_display_port_power_domain(intel_encoder);
4551         intel_display_power_get(dev_priv, power_domain);
4552
4553         edp_panel_vdd_schedule_off(intel_dp);
4554 }
4555
4556 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4557                                      struct intel_connector *intel_connector,
4558                                      struct edp_power_seq *power_seq)
4559 {
4560         struct drm_connector *connector = &intel_connector->base;
4561         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4562         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4563         struct drm_device *dev = intel_encoder->base.dev;
4564         struct drm_i915_private *dev_priv = dev->dev_private;
4565         struct drm_display_mode *fixed_mode = NULL;
4566         struct drm_display_mode *downclock_mode = NULL;
4567         bool has_dpcd;
4568         struct drm_display_mode *scan;
4569         struct edid *edid;
4570
4571         intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4572
4573         if (!is_edp(intel_dp))
4574                 return true;
4575
4576         intel_edp_panel_vdd_sanitize(intel_encoder);
4577
4578         /* Cache DPCD and EDID for edp. */
4579         intel_edp_panel_vdd_on(intel_dp);
4580         has_dpcd = intel_dp_get_dpcd(intel_dp);
4581         intel_edp_panel_vdd_off(intel_dp, false);
4582
4583         if (has_dpcd) {
4584                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4585                         dev_priv->no_aux_handshake =
4586                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4587                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4588         } else {
4589                 /* if this fails, presume the device is a ghost */
4590                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
4591                 return false;
4592         }
4593
4594         /* We now know it's not a ghost, init power sequence regs. */
4595         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4596
4597         mutex_lock(&dev->mode_config.mutex);
4598         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4599         if (edid) {
4600                 if (drm_add_edid_modes(connector, edid)) {
4601                         drm_mode_connector_update_edid_property(connector,
4602                                                                 edid);
4603                         drm_edid_to_eld(connector, edid);
4604                 } else {
4605                         kfree(edid);
4606                         edid = ERR_PTR(-EINVAL);
4607                 }
4608         } else {
4609                 edid = ERR_PTR(-ENOENT);
4610         }
4611         intel_connector->edid = edid;
4612
4613         /* prefer fixed mode from EDID if available */
4614         list_for_each_entry(scan, &connector->probed_modes, head) {
4615                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4616                         fixed_mode = drm_mode_duplicate(dev, scan);
4617                         downclock_mode = intel_dp_drrs_init(
4618                                                 intel_dig_port,
4619                                                 intel_connector, fixed_mode);
4620                         break;
4621                 }
4622         }
4623
4624         /* fallback to VBT if available for eDP */
4625         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4626                 fixed_mode = drm_mode_duplicate(dev,
4627                                         dev_priv->vbt.lfp_lvds_vbt_mode);
4628                 if (fixed_mode)
4629                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4630         }
4631         mutex_unlock(&dev->mode_config.mutex);
4632
4633         if (IS_VALLEYVIEW(dev)) {
4634                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4635                 register_reboot_notifier(&intel_dp->edp_notifier);
4636         }
4637
4638         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4639         intel_connector->panel.backlight_power = intel_edp_backlight_power;
4640         intel_panel_setup_backlight(connector);
4641
4642         return true;
4643 }
4644
4645 bool
4646 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4647                         struct intel_connector *intel_connector)
4648 {
4649         struct drm_connector *connector = &intel_connector->base;
4650         struct intel_dp *intel_dp = &intel_dig_port->dp;
4651         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4652         struct drm_device *dev = intel_encoder->base.dev;
4653         struct drm_i915_private *dev_priv = dev->dev_private;
4654         enum port port = intel_dig_port->port;
4655         struct edp_power_seq power_seq = { 0 };
4656         int type;
4657
4658         /* intel_dp vfuncs */
4659         if (IS_VALLEYVIEW(dev))
4660                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4661         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4662                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4663         else if (HAS_PCH_SPLIT(dev))
4664                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4665         else
4666                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4667
4668         intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4669
4670         /* Preserve the current hw state. */
4671         intel_dp->DP = I915_READ(intel_dp->output_reg);
4672         intel_dp->attached_connector = intel_connector;
4673
4674         if (intel_dp_is_edp(dev, port))
4675                 type = DRM_MODE_CONNECTOR_eDP;
4676         else
4677                 type = DRM_MODE_CONNECTOR_DisplayPort;
4678
4679         /*
4680          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4681          * for DP the encoder type can be set by the caller to
4682          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4683          */
4684         if (type == DRM_MODE_CONNECTOR_eDP)
4685                 intel_encoder->type = INTEL_OUTPUT_EDP;
4686
4687         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4688                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4689                         port_name(port));
4690
4691         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4692         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4693
4694         connector->interlace_allowed = true;
4695         connector->doublescan_allowed = 0;
4696
4697         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4698                           edp_panel_vdd_work);
4699
4700         intel_connector_attach_encoder(intel_connector, intel_encoder);
4701         drm_connector_register(connector);
4702
4703         if (HAS_DDI(dev))
4704                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4705         else
4706                 intel_connector->get_hw_state = intel_connector_get_hw_state;
4707         intel_connector->unregister = intel_dp_connector_unregister;
4708
4709         /* Set up the hotplug pin. */
4710         switch (port) {
4711         case PORT_A:
4712                 intel_encoder->hpd_pin = HPD_PORT_A;
4713                 break;
4714         case PORT_B:
4715                 intel_encoder->hpd_pin = HPD_PORT_B;
4716                 break;
4717         case PORT_C:
4718                 intel_encoder->hpd_pin = HPD_PORT_C;
4719                 break;
4720         case PORT_D:
4721                 intel_encoder->hpd_pin = HPD_PORT_D;
4722                 break;
4723         default:
4724                 BUG();
4725         }
4726
4727         if (is_edp(intel_dp)) {
4728                 intel_dp_init_panel_power_timestamps(intel_dp);
4729                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4730         }
4731
4732         intel_dp_aux_init(intel_dp, intel_connector);
4733
4734         /* init MST on ports that can support it */
4735         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4736                 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4737                         intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4738                 }
4739         }
4740
4741         if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4742                 drm_dp_aux_unregister(&intel_dp->aux);
4743                 if (is_edp(intel_dp)) {
4744                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4745                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4746                         edp_panel_vdd_off_sync(intel_dp);
4747                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4748                 }
4749                 drm_connector_unregister(connector);
4750                 drm_connector_cleanup(connector);
4751                 return false;
4752         }
4753
4754         intel_dp_add_properties(intel_dp, connector);
4755
4756         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4757          * 0xd.  Failure to do so will result in spurious interrupts being
4758          * generated on the port when a cable is not attached.
4759          */
4760         if (IS_G4X(dev) && !IS_GM45(dev)) {
4761                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4762                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4763         }
4764
4765         return true;
4766 }
4767
4768 void
4769 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4770 {
4771         struct drm_i915_private *dev_priv = dev->dev_private;
4772         struct intel_digital_port *intel_dig_port;
4773         struct intel_encoder *intel_encoder;
4774         struct drm_encoder *encoder;
4775         struct intel_connector *intel_connector;
4776
4777         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4778         if (!intel_dig_port)
4779                 return;
4780
4781         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4782         if (!intel_connector) {
4783                 kfree(intel_dig_port);
4784                 return;
4785         }
4786
4787         intel_encoder = &intel_dig_port->base;
4788         encoder = &intel_encoder->base;
4789
4790         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4791                          DRM_MODE_ENCODER_TMDS);
4792
4793         intel_encoder->compute_config = intel_dp_compute_config;
4794         intel_encoder->disable = intel_disable_dp;
4795         intel_encoder->get_hw_state = intel_dp_get_hw_state;
4796         intel_encoder->get_config = intel_dp_get_config;
4797         intel_encoder->suspend = intel_dp_encoder_suspend;
4798         if (IS_CHERRYVIEW(dev)) {
4799                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
4800                 intel_encoder->pre_enable = chv_pre_enable_dp;
4801                 intel_encoder->enable = vlv_enable_dp;
4802                 intel_encoder->post_disable = chv_post_disable_dp;
4803         } else if (IS_VALLEYVIEW(dev)) {
4804                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4805                 intel_encoder->pre_enable = vlv_pre_enable_dp;
4806                 intel_encoder->enable = vlv_enable_dp;
4807                 intel_encoder->post_disable = vlv_post_disable_dp;
4808         } else {
4809                 intel_encoder->pre_enable = g4x_pre_enable_dp;
4810                 intel_encoder->enable = g4x_enable_dp;
4811                 intel_encoder->post_disable = g4x_post_disable_dp;
4812         }
4813
4814         intel_dig_port->port = port;
4815         intel_dig_port->dp.output_reg = output_reg;
4816
4817         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4818         if (IS_CHERRYVIEW(dev)) {
4819                 if (port == PORT_D)
4820                         intel_encoder->crtc_mask = 1 << 2;
4821                 else
4822                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4823         } else {
4824                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4825         }
4826         intel_encoder->cloneable = 0;
4827         intel_encoder->hot_plug = intel_dp_hot_plug;
4828
4829         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4830         dev_priv->hpd_irq_port[port] = intel_dig_port;
4831
4832         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4833                 drm_encoder_cleanup(encoder);
4834                 kfree(intel_dig_port);
4835                 kfree(intel_connector);
4836         }
4837 }
4838
4839 void intel_dp_mst_suspend(struct drm_device *dev)
4840 {
4841         struct drm_i915_private *dev_priv = dev->dev_private;
4842         int i;
4843
4844         /* disable MST */
4845         for (i = 0; i < I915_MAX_PORTS; i++) {
4846                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4847                 if (!intel_dig_port)
4848                         continue;
4849
4850                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4851                         if (!intel_dig_port->dp.can_mst)
4852                                 continue;
4853                         if (intel_dig_port->dp.is_mst)
4854                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4855                 }
4856         }
4857 }
4858
4859 void intel_dp_mst_resume(struct drm_device *dev)
4860 {
4861         struct drm_i915_private *dev_priv = dev->dev_private;
4862         int i;
4863
4864         for (i = 0; i < I915_MAX_PORTS; i++) {
4865                 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4866                 if (!intel_dig_port)
4867                         continue;
4868                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4869                         int ret;
4870
4871                         if (!intel_dig_port->dp.can_mst)
4872                                 continue;
4873
4874                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4875                         if (ret != 0) {
4876                                 intel_dp_check_mst_status(&intel_dig_port->dp);
4877                         }
4878                 }
4879         }
4880 }