drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "intel_dsi.h"
  40 #include "i915_trace.h"
  41 #include <drm/drm_atomic.h>
  42 #include <drm/drm_atomic_helper.h>
  43 #include <drm/drm_dp_helper.h>
  44 #include <drm/drm_crtc_helper.h>
  45 #include <drm/drm_plane_helper.h>
  46 #include <drm/drm_rect.h>
  47 #include <linux/dma_remapping.h>
  48 #include <linux/reservation.h>
  49 #include <linux/dma-buf.h>
  50
  51 /* Primary plane formats for gen <= 3 */
  52 static const uint32_t i8xx_primary_formats[] = {
  53         DRM_FORMAT_C8,
  54         DRM_FORMAT_RGB565,
  55         DRM_FORMAT_XRGB1555,
  56         DRM_FORMAT_XRGB8888,
  57 };
  58
  59 /* Primary plane formats for gen >= 4 */
  60 static const uint32_t i965_primary_formats[] = {
  61         DRM_FORMAT_C8,
  62         DRM_FORMAT_RGB565,
  63         DRM_FORMAT_XRGB8888,
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_XBGR2101010,
  67 };
  68
  69 static const uint32_t skl_primary_formats[] = {
  70         DRM_FORMAT_C8,
  71         DRM_FORMAT_RGB565,
  72         DRM_FORMAT_XRGB8888,
  73         DRM_FORMAT_XBGR8888,
  74         DRM_FORMAT_ARGB8888,
  75         DRM_FORMAT_ABGR8888,
  76         DRM_FORMAT_XRGB2101010,
  77         DRM_FORMAT_XBGR2101010,
  78         DRM_FORMAT_YUYV,
  79         DRM_FORMAT_YVYU,
  80         DRM_FORMAT_UYVY,
  81         DRM_FORMAT_VYUY,
  82 };
  83
  84 /* Cursor formats */
  85 static const uint32_t intel_cursor_formats[] = {
  86         DRM_FORMAT_ARGB8888,
  87 };
  88
  89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  90                                 struct intel_crtc_state *pipe_config);
  91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  92                                    struct intel_crtc_state *pipe_config);
  93
  94 static int intel_framebuffer_init(struct drm_device *dev,
  95                                   struct intel_framebuffer *ifb,
  96                                   struct drm_mode_fb_cmd2 *mode_cmd,
  97                                   struct drm_i915_gem_object *obj);
  98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 102                                          struct intel_link_m_n *m_n,
 103                                          struct intel_link_m_n *m2_n2);
 104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 107 static void vlv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void chv_prepare_pll(struct intel_crtc *crtc,
 110                             const struct intel_crtc_state *pipe_config);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static void skylake_pfit_enable(struct intel_crtc *crtc);
 114 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 115 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 116 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 117 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 118 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 119 static void intel_modeset_verify_crtc(struct drm_crtc *crtc,
 120                                       struct drm_crtc_state *old_state,
 121                                       struct drm_crtc_state *new_state);
 122
 123 struct intel_limit {
 124         struct {
 125                 int min, max;
 126         } dot, vco, n, m, m1, m2, p, p1;
 127
 128         struct {
 129                 int dot_limit;
 130                 int p2_slow, p2_fast;
 131         } p2;
 132 };
 133
 134 /* returns HPLL frequency in kHz */
 135 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 136 {
 137         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 138
 139         /* Obtain SKU information */
 140         mutex_lock(&dev_priv->sb_lock);
 141         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 142                 CCK_FUSE_HPLL_FREQ_MASK;
 143         mutex_unlock(&dev_priv->sb_lock);
 144
 145         return vco_freq[hpll_freq] * 1000;
 146 }
 147
 148 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 149                       const char *name, u32 reg, int ref_freq)
 150 {
 151         u32 val;
 152         int divider;
 153
 154         mutex_lock(&dev_priv->sb_lock);
 155         val = vlv_cck_read(dev_priv, reg);
 156         mutex_unlock(&dev_priv->sb_lock);
 157
 158         divider = val & CCK_FREQUENCY_VALUES;
 159
 160         WARN((val & CCK_FREQUENCY_STATUS) !=
 161              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 162              "%s change in progress\n", name);
 163
 164         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 165 }
 166
 167 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 168                                   const char *name, u32 reg)
 169 {
 170         if (dev_priv->hpll_freq == 0)
 171                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 172
 173         return vlv_get_cck_clock(dev_priv, name, reg,
 174                                  dev_priv->hpll_freq);
 175 }
 176
 177 static int
 178 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 179 {
 180         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 181 }
 182
 183 static int
 184 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 185 {
 186         /* RAWCLK_FREQ_VLV register updated from power well code */
 187         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 188                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 189 }
 190
 191 static int
 192 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 193 {
 194         uint32_t clkcfg;
 195
 196         /* hrawclock is 1/4 the FSB frequency */
 197         clkcfg = I915_READ(CLKCFG);
 198         switch (clkcfg & CLKCFG_FSB_MASK) {
 199         case CLKCFG_FSB_400:
 200                 return 100000;
 201         case CLKCFG_FSB_533:
 202                 return 133333;
 203         case CLKCFG_FSB_667:
 204                 return 166667;
 205         case CLKCFG_FSB_800:
 206                 return 200000;
 207         case CLKCFG_FSB_1067:
 208                 return 266667;
 209         case CLKCFG_FSB_1333:
 210                 return 333333;
 211         /* these two are just a guess; one of them might be right */
 212         case CLKCFG_FSB_1600:
 213         case CLKCFG_FSB_1600_ALT:
 214                 return 400000;
 215         default:
 216                 return 133333;
 217         }
 218 }
 219
 220 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 221 {
 222         if (HAS_PCH_SPLIT(dev_priv))
 223                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 224         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 225                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 226         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 227                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 228         else
 229                 return; /* no rawclk on other platforms, or no need to know it */
 230
 231         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 232 }
 233
 234 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 235 {
 236         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 237                 return;
 238
 239         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 240                                                       CCK_CZ_CLOCK_CONTROL);
 241
 242         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 243 }
 244
 245 static inline u32 /* units of 100MHz */
 246 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 247                     const struct intel_crtc_state *pipe_config)
 248 {
 249         if (HAS_DDI(dev_priv))
 250                 return pipe_config->port_clock; /* SPLL */
 251         else if (IS_GEN5(dev_priv))
 252                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 253         else
 254                 return 270000;
 255 }
 256
 257 static const struct intel_limit intel_limits_i8xx_dac = {
 258         .dot = { .min = 25000, .max = 350000 },
 259         .vco = { .min = 908000, .max = 1512000 },
 260         .n = { .min = 2, .max = 16 },
 261         .m = { .min = 96, .max = 140 },
 262         .m1 = { .min = 18, .max = 26 },
 263         .m2 = { .min = 6, .max = 16 },
 264         .p = { .min = 4, .max = 128 },
 265         .p1 = { .min = 2, .max = 33 },
 266         .p2 = { .dot_limit = 165000,
 267                 .p2_slow = 4, .p2_fast = 2 },
 268 };
 269
 270 static const struct intel_limit intel_limits_i8xx_dvo = {
 271         .dot = { .min = 25000, .max = 350000 },
 272         .vco = { .min = 908000, .max = 1512000 },
 273         .n = { .min = 2, .max = 16 },
 274         .m = { .min = 96, .max = 140 },
 275         .m1 = { .min = 18, .max = 26 },
 276         .m2 = { .min = 6, .max = 16 },
 277         .p = { .min = 4, .max = 128 },
 278         .p1 = { .min = 2, .max = 33 },
 279         .p2 = { .dot_limit = 165000,
 280                 .p2_slow = 4, .p2_fast = 4 },
 281 };
 282
 283 static const struct intel_limit intel_limits_i8xx_lvds = {
 284         .dot = { .min = 25000, .max = 350000 },
 285         .vco = { .min = 908000, .max = 1512000 },
 286         .n = { .min = 2, .max = 16 },
 287         .m = { .min = 96, .max = 140 },
 288         .m1 = { .min = 18, .max = 26 },
 289         .m2 = { .min = 6, .max = 16 },
 290         .p = { .min = 4, .max = 128 },
 291         .p1 = { .min = 1, .max = 6 },
 292         .p2 = { .dot_limit = 165000,
 293                 .p2_slow = 14, .p2_fast = 7 },
 294 };
 295
 296 static const struct intel_limit intel_limits_i9xx_sdvo = {
 297         .dot = { .min = 20000, .max = 400000 },
 298         .vco = { .min = 1400000, .max = 2800000 },
 299         .n = { .min = 1, .max = 6 },
 300         .m = { .min = 70, .max = 120 },
 301         .m1 = { .min = 8, .max = 18 },
 302         .m2 = { .min = 3, .max = 7 },
 303         .p = { .min = 5, .max = 80 },
 304         .p1 = { .min = 1, .max = 8 },
 305         .p2 = { .dot_limit = 200000,
 306                 .p2_slow = 10, .p2_fast = 5 },
 307 };
 308
 309 static const struct intel_limit intel_limits_i9xx_lvds = {
 310         .dot = { .min = 20000, .max = 400000 },
 311         .vco = { .min = 1400000, .max = 2800000 },
 312         .n = { .min = 1, .max = 6 },
 313         .m = { .min = 70, .max = 120 },
 314         .m1 = { .min = 8, .max = 18 },
 315         .m2 = { .min = 3, .max = 7 },
 316         .p = { .min = 7, .max = 98 },
 317         .p1 = { .min = 1, .max = 8 },
 318         .p2 = { .dot_limit = 112000,
 319                 .p2_slow = 14, .p2_fast = 7 },
 320 };
 321
 322
 323 static const struct intel_limit intel_limits_g4x_sdvo = {
 324         .dot = { .min = 25000, .max = 270000 },
 325         .vco = { .min = 1750000, .max = 3500000},
 326         .n = { .min = 1, .max = 4 },
 327         .m = { .min = 104, .max = 138 },
 328         .m1 = { .min = 17, .max = 23 },
 329         .m2 = { .min = 5, .max = 11 },
 330         .p = { .min = 10, .max = 30 },
 331         .p1 = { .min = 1, .max = 3},
 332         .p2 = { .dot_limit = 270000,
 333                 .p2_slow = 10,
 334                 .p2_fast = 10
 335         },
 336 };
 337
 338 static const struct intel_limit intel_limits_g4x_hdmi = {
 339         .dot = { .min = 22000, .max = 400000 },
 340         .vco = { .min = 1750000, .max = 3500000},
 341         .n = { .min = 1, .max = 4 },
 342         .m = { .min = 104, .max = 138 },
 343         .m1 = { .min = 16, .max = 23 },
 344         .m2 = { .min = 5, .max = 11 },
 345         .p = { .min = 5, .max = 80 },
 346         .p1 = { .min = 1, .max = 8},
 347         .p2 = { .dot_limit = 165000,
 348                 .p2_slow = 10, .p2_fast = 5 },
 349 };
 350
 351 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 352         .dot = { .min = 20000, .max = 115000 },
 353         .vco = { .min = 1750000, .max = 3500000 },
 354         .n = { .min = 1, .max = 3 },
 355         .m = { .min = 104, .max = 138 },
 356         .m1 = { .min = 17, .max = 23 },
 357         .m2 = { .min = 5, .max = 11 },
 358         .p = { .min = 28, .max = 112 },
 359         .p1 = { .min = 2, .max = 8 },
 360         .p2 = { .dot_limit = 0,
 361                 .p2_slow = 14, .p2_fast = 14
 362         },
 363 };
 364
 365 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 366         .dot = { .min = 80000, .max = 224000 },
 367         .vco = { .min = 1750000, .max = 3500000 },
 368         .n = { .min = 1, .max = 3 },
 369         .m = { .min = 104, .max = 138 },
 370         .m1 = { .min = 17, .max = 23 },
 371         .m2 = { .min = 5, .max = 11 },
 372         .p = { .min = 14, .max = 42 },
 373         .p1 = { .min = 2, .max = 6 },
 374         .p2 = { .dot_limit = 0,
 375                 .p2_slow = 7, .p2_fast = 7
 376         },
 377 };
 378
 379 static const struct intel_limit intel_limits_pineview_sdvo = {
 380         .dot = { .min = 20000, .max = 400000},
 381         .vco = { .min = 1700000, .max = 3500000 },
 382         /* Pineview's Ncounter is a ring counter */
 383         .n = { .min = 3, .max = 6 },
 384         .m = { .min = 2, .max = 256 },
 385         /* Pineview only has one combined m divider, which we treat as m2. */
 386         .m1 = { .min = 0, .max = 0 },
 387         .m2 = { .min = 0, .max = 254 },
 388         .p = { .min = 5, .max = 80 },
 389         .p1 = { .min = 1, .max = 8 },
 390         .p2 = { .dot_limit = 200000,
 391                 .p2_slow = 10, .p2_fast = 5 },
 392 };
 393
 394 static const struct intel_limit intel_limits_pineview_lvds = {
 395         .dot = { .min = 20000, .max = 400000 },
 396         .vco = { .min = 1700000, .max = 3500000 },
 397         .n = { .min = 3, .max = 6 },
 398         .m = { .min = 2, .max = 256 },
 399         .m1 = { .min = 0, .max = 0 },
 400         .m2 = { .min = 0, .max = 254 },
 401         .p = { .min = 7, .max = 112 },
 402         .p1 = { .min = 1, .max = 8 },
 403         .p2 = { .dot_limit = 112000,
 404                 .p2_slow = 14, .p2_fast = 14 },
 405 };
 406
 407 /* Ironlake / Sandybridge
 408  *
 409  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 410  * the range value for them is (actual_value - 2).
 411  */
 412 static const struct intel_limit intel_limits_ironlake_dac = {
 413         .dot = { .min = 25000, .max = 350000 },
 414         .vco = { .min = 1760000, .max = 3510000 },
 415         .n = { .min = 1, .max = 5 },
 416         .m = { .min = 79, .max = 127 },
 417         .m1 = { .min = 12, .max = 22 },
 418         .m2 = { .min = 5, .max = 9 },
 419         .p = { .min = 5, .max = 80 },
 420         .p1 = { .min = 1, .max = 8 },
 421         .p2 = { .dot_limit = 225000,
 422                 .p2_slow = 10, .p2_fast = 5 },
 423 };
 424
 425 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 426         .dot = { .min = 25000, .max = 350000 },
 427         .vco = { .min = 1760000, .max = 3510000 },
 428         .n = { .min = 1, .max = 3 },
 429         .m = { .min = 79, .max = 118 },
 430         .m1 = { .min = 12, .max = 22 },
 431         .m2 = { .min = 5, .max = 9 },
 432         .p = { .min = 28, .max = 112 },
 433         .p1 = { .min = 2, .max = 8 },
 434         .p2 = { .dot_limit = 225000,
 435                 .p2_slow = 14, .p2_fast = 14 },
 436 };
 437
 438 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 439         .dot = { .min = 25000, .max = 350000 },
 440         .vco = { .min = 1760000, .max = 3510000 },
 441         .n = { .min = 1, .max = 3 },
 442         .m = { .min = 79, .max = 127 },
 443         .m1 = { .min = 12, .max = 22 },
 444         .m2 = { .min = 5, .max = 9 },
 445         .p = { .min = 14, .max = 56 },
 446         .p1 = { .min = 2, .max = 8 },
 447         .p2 = { .dot_limit = 225000,
 448                 .p2_slow = 7, .p2_fast = 7 },
 449 };
 450
 451 /* LVDS 100mhz refclk limits. */
 452 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 453         .dot = { .min = 25000, .max = 350000 },
 454         .vco = { .min = 1760000, .max = 3510000 },
 455         .n = { .min = 1, .max = 2 },
 456         .m = { .min = 79, .max = 126 },
 457         .m1 = { .min = 12, .max = 22 },
 458         .m2 = { .min = 5, .max = 9 },
 459         .p = { .min = 28, .max = 112 },
 460         .p1 = { .min = 2, .max = 8 },
 461         .p2 = { .dot_limit = 225000,
 462                 .p2_slow = 14, .p2_fast = 14 },
 463 };
 464
 465 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 466         .dot = { .min = 25000, .max = 350000 },
 467         .vco = { .min = 1760000, .max = 3510000 },
 468         .n = { .min = 1, .max = 3 },
 469         .m = { .min = 79, .max = 126 },
 470         .m1 = { .min = 12, .max = 22 },
 471         .m2 = { .min = 5, .max = 9 },
 472         .p = { .min = 14, .max = 42 },
 473         .p1 = { .min = 2, .max = 6 },
 474         .p2 = { .dot_limit = 225000,
 475                 .p2_slow = 7, .p2_fast = 7 },
 476 };
 477
 478 static const struct intel_limit intel_limits_vlv = {
 479          /*
 480           * These are the data rate limits (measured in fast clocks)
 481           * since those are the strictest limits we have. The fast
 482           * clock and actual rate limits are more relaxed, so checking
 483           * them would make no difference.
 484           */
 485         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 486         .vco = { .min = 4000000, .max = 6000000 },
 487         .n = { .min = 1, .max = 7 },
 488         .m1 = { .min = 2, .max = 3 },
 489         .m2 = { .min = 11, .max = 156 },
 490         .p1 = { .min = 2, .max = 3 },
 491         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 492 };
 493
 494 static const struct intel_limit intel_limits_chv = {
 495         /*
 496          * These are the data rate limits (measured in fast clocks)
 497          * since those are the strictest limits we have.  The fast
 498          * clock and actual rate limits are more relaxed, so checking
 499          * them would make no difference.
 500          */
 501         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 502         .vco = { .min = 4800000, .max = 6480000 },
 503         .n = { .min = 1, .max = 1 },
 504         .m1 = { .min = 2, .max = 2 },
 505         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 506         .p1 = { .min = 2, .max = 4 },
 507         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 508 };
 509
 510 static const struct intel_limit intel_limits_bxt = {
 511         /* FIXME: find real dot limits */
 512         .dot = { .min = 0, .max = INT_MAX },
 513         .vco = { .min = 4800000, .max = 6700000 },
 514         .n = { .min = 1, .max = 1 },
 515         .m1 = { .min = 2, .max = 2 },
 516         /* FIXME: find real m2 limits */
 517         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 518         .p1 = { .min = 2, .max = 4 },
 519         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 520 };
 521
 522 static bool
 523 needs_modeset(struct drm_crtc_state *state)
 524 {
 525         return drm_atomic_crtc_needs_modeset(state);
 526 }
 527
 528 /**
 529  * Returns whether any output on the specified pipe is of the specified type
 530  */
 531 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 532 {
 533         struct drm_device *dev = crtc->base.dev;
 534         struct intel_encoder *encoder;
 535
 536         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 537                 if (encoder->type == type)
 538                         return true;
 539
 540         return false;
 541 }
 542
 543 /**
 544  * Returns whether any output on the specified pipe will have the specified
 545  * type after a staged modeset is complete, i.e., the same as
 546  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 547  * encoder->crtc.
 548  */
 549 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 550                                       int type)
 551 {
 552         struct drm_atomic_state *state = crtc_state->base.state;
 553         struct drm_connector *connector;
 554         struct drm_connector_state *connector_state;
 555         struct intel_encoder *encoder;
 556         int i, num_connectors = 0;
 557
 558         for_each_connector_in_state(state, connector, connector_state, i) {
 559                 if (connector_state->crtc != crtc_state->base.crtc)
 560                         continue;
 561
 562                 num_connectors++;
 563
 564                 encoder = to_intel_encoder(connector_state->best_encoder);
 565                 if (encoder->type == type)
 566                         return true;
 567         }
 568
 569         WARN_ON(num_connectors == 0);
 570
 571         return false;
 572 }
 573
 574 /*
 575  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 576  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 577  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 578  * The helpers' return value is the rate of the clock that is fed to the
 579  * display engine's pipe which can be the above fast dot clock rate or a
 580  * divided-down version of it.
 581  */
 582 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 583 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 584 {
 585         clock->m = clock->m2 + 2;
 586         clock->p = clock->p1 * clock->p2;
 587         if (WARN_ON(clock->n == 0 || clock->p == 0))
 588                 return 0;
 589         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 590         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 591
 592         return clock->dot;
 593 }
 594
 595 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 596 {
 597         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 598 }
 599
 600 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 601 {
 602         clock->m = i9xx_dpll_compute_m(clock);
 603         clock->p = clock->p1 * clock->p2;
 604         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 605                 return 0;
 606         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 607         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 608
 609         return clock->dot;
 610 }
 611
 612 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 613 {
 614         clock->m = clock->m1 * clock->m2;
 615         clock->p = clock->p1 * clock->p2;
 616         if (WARN_ON(clock->n == 0 || clock->p == 0))
 617                 return 0;
 618         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 619         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 620
 621         return clock->dot / 5;
 622 }
 623
 624 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 625 {
 626         clock->m = clock->m1 * clock->m2;
 627         clock->p = clock->p1 * clock->p2;
 628         if (WARN_ON(clock->n == 0 || clock->p == 0))
 629                 return 0;
 630         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 631                         clock->n << 22);
 632         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 633
 634         return clock->dot / 5;
 635 }
 636
 637 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 638 /**
 639  * Returns whether the given set of divisors are valid for a given refclk with
 640  * the given connectors.
 641  */
 642
 643 static bool intel_PLL_is_valid(struct drm_device *dev,
 644                                const struct intel_limit *limit,
 645                                const struct dpll *clock)
 646 {
 647         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 648                 INTELPllInvalid("n out of range\n");
 649         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 650                 INTELPllInvalid("p1 out of range\n");
 651         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 652                 INTELPllInvalid("m2 out of range\n");
 653         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 654                 INTELPllInvalid("m1 out of range\n");
 655
 656         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 657             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 658                 if (clock->m1 <= clock->m2)
 659                         INTELPllInvalid("m1 <= m2\n");
 660
 661         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 662                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 663                         INTELPllInvalid("p out of range\n");
 664                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 665                         INTELPllInvalid("m out of range\n");
 666         }
 667
 668         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 669                 INTELPllInvalid("vco out of range\n");
 670         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 671          * connector, etc., rather than just a single range.
 672          */
 673         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 674                 INTELPllInvalid("dot out of range\n");
 675
 676         return true;
 677 }
 678
 679 static int
 680 i9xx_select_p2_div(const struct intel_limit *limit,
 681                    const struct intel_crtc_state *crtc_state,
 682                    int target)
 683 {
 684         struct drm_device *dev = crtc_state->base.crtc->dev;
 685
 686         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 687                 /*
 688                  * For LVDS just rely on its current settings for dual-channel.
 689                  * We haven't figured out how to reliably set up different
 690                  * single/dual channel state, if we even can.
 691                  */
 692                 if (intel_is_dual_link_lvds(dev))
 693                         return limit->p2.p2_fast;
 694                 else
 695                         return limit->p2.p2_slow;
 696         } else {
 697                 if (target < limit->p2.dot_limit)
 698                         return limit->p2.p2_slow;
 699                 else
 700                         return limit->p2.p2_fast;
 701         }
 702 }
 703
 704 /*
 705  * Returns a set of divisors for the desired target clock with the given
 706  * refclk, or FALSE.  The returned values represent the clock equation:
 707  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 708  *
 709  * Target and reference clocks are specified in kHz.
 710  *
 711  * If match_clock is provided, then best_clock P divider must match the P
 712  * divider from @match_clock used for LVDS downclocking.
 713  */
 714 static bool
 715 i9xx_find_best_dpll(const struct intel_limit *limit,
 716                     struct intel_crtc_state *crtc_state,
 717                     int target, int refclk, struct dpll *match_clock,
 718                     struct dpll *best_clock)
 719 {
 720         struct drm_device *dev = crtc_state->base.crtc->dev;
 721         struct dpll clock;
 722         int err = target;
 723
 724         memset(best_clock, 0, sizeof(*best_clock));
 725
 726         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 727
 728         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 729              clock.m1++) {
 730                 for (clock.m2 = limit->m2.min;
 731                      clock.m2 <= limit->m2.max; clock.m2++) {
 732                         if (clock.m2 >= clock.m1)
 733                                 break;
 734                         for (clock.n = limit->n.min;
 735                              clock.n <= limit->n.max; clock.n++) {
 736                                 for (clock.p1 = limit->p1.min;
 737                                         clock.p1 <= limit->p1.max; clock.p1++) {
 738                                         int this_err;
 739
 740                                         i9xx_calc_dpll_params(refclk, &clock);
 741                                         if (!intel_PLL_is_valid(dev, limit,
 742                                                                 &clock))
 743                                                 continue;
 744                                         if (match_clock &&
 745                                             clock.p != match_clock->p)
 746                                                 continue;
 747
 748                                         this_err = abs(clock.dot - target);
 749                                         if (this_err < err) {
 750                                                 *best_clock = clock;
 751                                                 err = this_err;
 752                                         }
 753                                 }
 754                         }
 755                 }
 756         }
 757
 758         return (err != target);
 759 }
 760
 761 /*
 762  * Returns a set of divisors for the desired target clock with the given
 763  * refclk, or FALSE.  The returned values represent the clock equation:
 764  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 765  *
 766  * Target and reference clocks are specified in kHz.
 767  *
 768  * If match_clock is provided, then best_clock P divider must match the P
 769  * divider from @match_clock used for LVDS downclocking.
 770  */
 771 static bool
 772 pnv_find_best_dpll(const struct intel_limit *limit,
 773                    struct intel_crtc_state *crtc_state,
 774                    int target, int refclk, struct dpll *match_clock,
 775                    struct dpll *best_clock)
 776 {
 777         struct drm_device *dev = crtc_state->base.crtc->dev;
 778         struct dpll clock;
 779         int err = target;
 780
 781         memset(best_clock, 0, sizeof(*best_clock));
 782
 783         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 784
 785         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 786              clock.m1++) {
 787                 for (clock.m2 = limit->m2.min;
 788                      clock.m2 <= limit->m2.max; clock.m2++) {
 789                         for (clock.n = limit->n.min;
 790                              clock.n <= limit->n.max; clock.n++) {
 791                                 for (clock.p1 = limit->p1.min;
 792                                         clock.p1 <= limit->p1.max; clock.p1++) {
 793                                         int this_err;
 794
 795                                         pnv_calc_dpll_params(refclk, &clock);
 796                                         if (!intel_PLL_is_valid(dev, limit,
 797                                                                 &clock))
 798                                                 continue;
 799                                         if (match_clock &&
 800                                             clock.p != match_clock->p)
 801                                                 continue;
 802
 803                                         this_err = abs(clock.dot - target);
 804                                         if (this_err < err) {
 805                                                 *best_clock = clock;
 806                                                 err = this_err;
 807                                         }
 808                                 }
 809                         }
 810                 }
 811         }
 812
 813         return (err != target);
 814 }
 815
 816 /*
 817  * Returns a set of divisors for the desired target clock with the given
 818  * refclk, or FALSE.  The returned values represent the clock equation:
 819  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 820  *
 821  * Target and reference clocks are specified in kHz.
 822  *
 823  * If match_clock is provided, then best_clock P divider must match the P
 824  * divider from @match_clock used for LVDS downclocking.
 825  */
 826 static bool
 827 g4x_find_best_dpll(const struct intel_limit *limit,
 828                    struct intel_crtc_state *crtc_state,
 829                    int target, int refclk, struct dpll *match_clock,
 830                    struct dpll *best_clock)
 831 {
 832         struct drm_device *dev = crtc_state->base.crtc->dev;
 833         struct dpll clock;
 834         int max_n;
 835         bool found = false;
 836         /* approximately equals target * 0.00585 */
 837         int err_most = (target >> 8) + (target >> 9);
 838
 839         memset(best_clock, 0, sizeof(*best_clock));
 840
 841         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 842
 843         max_n = limit->n.max;
 844         /* based on hardware requirement, prefer smaller n to precision */
 845         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 846                 /* based on hardware requirement, prefere larger m1,m2 */
 847                 for (clock.m1 = limit->m1.max;
 848                      clock.m1 >= limit->m1.min; clock.m1--) {
 849                         for (clock.m2 = limit->m2.max;
 850                              clock.m2 >= limit->m2.min; clock.m2--) {
 851                                 for (clock.p1 = limit->p1.max;
 852                                      clock.p1 >= limit->p1.min; clock.p1--) {
 853                                         int this_err;
 854
 855                                         i9xx_calc_dpll_params(refclk, &clock);
 856                                         if (!intel_PLL_is_valid(dev, limit,
 857                                                                 &clock))
 858                                                 continue;
 859
 860                                         this_err = abs(clock.dot - target);
 861                                         if (this_err < err_most) {
 862                                                 *best_clock = clock;
 863                                                 err_most = this_err;
 864                                                 max_n = clock.n;
 865                                                 found = true;
 866                                         }
 867                                 }
 868                         }
 869                 }
 870         }
 871         return found;
 872 }
 873
 874 /*
 875  * Check if the calculated PLL configuration is more optimal compared to the
 876  * best configuration and error found so far. Return the calculated error.
 877  */
 878 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 879                                const struct dpll *calculated_clock,
 880                                const struct dpll *best_clock,
 881                                unsigned int best_error_ppm,
 882                                unsigned int *error_ppm)
 883 {
 884         /*
 885          * For CHV ignore the error and consider only the P value.
 886          * Prefer a bigger P value based on HW requirements.
 887          */
 888         if (IS_CHERRYVIEW(dev)) {
 889                 *error_ppm = 0;
 890
 891                 return calculated_clock->p > best_clock->p;
 892         }
 893
 894         if (WARN_ON_ONCE(!target_freq))
 895                 return false;
 896
 897         *error_ppm = div_u64(1000000ULL *
 898                                 abs(target_freq - calculated_clock->dot),
 899                              target_freq);
 900         /*
 901          * Prefer a better P value over a better (smaller) error if the error
 902          * is small. Ensure this preference for future configurations too by
 903          * setting the error to 0.
 904          */
 905         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 906                 *error_ppm = 0;
 907
 908                 return true;
 909         }
 910
 911         return *error_ppm + 10 < best_error_ppm;
 912 }
 913
 914 /*
 915  * Returns a set of divisors for the desired target clock with the given
 916  * refclk, or FALSE.  The returned values represent the clock equation:
 917  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 918  */
 919 static bool
 920 vlv_find_best_dpll(const struct intel_limit *limit,
 921                    struct intel_crtc_state *crtc_state,
 922                    int target, int refclk, struct dpll *match_clock,
 923                    struct dpll *best_clock)
 924 {
 925         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 926         struct drm_device *dev = crtc->base.dev;
 927         struct dpll clock;
 928         unsigned int bestppm = 1000000;
 929         /* min update 19.2 MHz */
 930         int max_n = min(limit->n.max, refclk / 19200);
 931         bool found = false;
 932
 933         target *= 5; /* fast clock */
 934
 935         memset(best_clock, 0, sizeof(*best_clock));
 936
 937         /* based on hardware requirement, prefer smaller n to precision */
 938         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 939                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 940                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 941                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 942                                 clock.p = clock.p1 * clock.p2;
 943                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 944                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 945                                         unsigned int ppm;
 946
 947                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 948                                                                      refclk * clock.m1);
 949
 950                                         vlv_calc_dpll_params(refclk, &clock);
 951
 952                                         if (!intel_PLL_is_valid(dev, limit,
 953                                                                 &clock))
 954                                                 continue;
 955
 956                                         if (!vlv_PLL_is_optimal(dev, target,
 957                                                                 &clock,
 958                                                                 best_clock,
 959                                                                 bestppm, &ppm))
 960                                                 continue;
 961
 962                                         *best_clock = clock;
 963                                         bestppm = ppm;
 964                                         found = true;
 965                                 }
 966                         }
 967                 }
 968         }
 969
 970         return found;
 971 }
 972
 973 /*
 974  * Returns a set of divisors for the desired target clock with the given
 975  * refclk, or FALSE.  The returned values represent the clock equation:
 976  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 977  */
 978 static bool
 979 chv_find_best_dpll(const struct intel_limit *limit,
 980                    struct intel_crtc_state *crtc_state,
 981                    int target, int refclk, struct dpll *match_clock,
 982                    struct dpll *best_clock)
 983 {
 984         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 985         struct drm_device *dev = crtc->base.dev;
 986         unsigned int best_error_ppm;
 987         struct dpll clock;
 988         uint64_t m2;
 989         int found = false;
 990
 991         memset(best_clock, 0, sizeof(*best_clock));
 992         best_error_ppm = 1000000;
 993
 994         /*
 995          * Based on hardware doc, the n always set to 1, and m1 always
 996          * set to 2.  If requires to support 200Mhz refclk, we need to
 997          * revisit this because n may not 1 anymore.
 998          */
 999         clock.n = 1, clock.m1 = 2;
1000         target *= 5;    /* fast clock */
1001
1002         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1003                 for (clock.p2 = limit->p2.p2_fast;
1004                                 clock.p2 >= limit->p2.p2_slow;
1005                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1006                         unsigned int error_ppm;
1007
1008                         clock.p = clock.p1 * clock.p2;
1009
1010                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1011                                         clock.n) << 22, refclk * clock.m1);
1012
1013                         if (m2 > INT_MAX/clock.m1)
1014                                 continue;
1015
1016                         clock.m2 = m2;
1017
1018                         chv_calc_dpll_params(refclk, &clock);
1019
1020                         if (!intel_PLL_is_valid(dev, limit, &clock))
1021                                 continue;
1022
1023                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1024                                                 best_error_ppm, &error_ppm))
1025                                 continue;
1026
1027                         *best_clock = clock;
1028                         best_error_ppm = error_ppm;
1029                         found = true;
1030                 }
1031         }
1032
1033         return found;
1034 }
1035
1036 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1037                         struct dpll *best_clock)
1038 {
1039         int refclk = 100000;
1040         const struct intel_limit *limit = &intel_limits_bxt;
1041
1042         return chv_find_best_dpll(limit, crtc_state,
1043                                   target_clock, refclk, NULL, best_clock);
1044 }
1045
1046 bool intel_crtc_active(struct drm_crtc *crtc)
1047 {
1048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1049
1050         /* Be paranoid as we can arrive here with only partial
1051          * state retrieved from the hardware during setup.
1052          *
1053          * We can ditch the adjusted_mode.crtc_clock check as soon
1054          * as Haswell has gained clock readout/fastboot support.
1055          *
1056          * We can ditch the crtc->primary->fb check as soon as we can
1057          * properly reconstruct framebuffers.
1058          *
1059          * FIXME: The intel_crtc->active here should be switched to
1060          * crtc->state->active once we have proper CRTC states wired up
1061          * for atomic.
1062          */
1063         return intel_crtc->active && crtc->primary->state->fb &&
1064                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1065 }
1066
1067 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1068                                              enum pipe pipe)
1069 {
1070         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1072
1073         return intel_crtc->config->cpu_transcoder;
1074 }
1075
1076 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1077 {
1078         struct drm_i915_private *dev_priv = dev->dev_private;
1079         i915_reg_t reg = PIPEDSL(pipe);
1080         u32 line1, line2;
1081         u32 line_mask;
1082
1083         if (IS_GEN2(dev))
1084                 line_mask = DSL_LINEMASK_GEN2;
1085         else
1086                 line_mask = DSL_LINEMASK_GEN3;
1087
1088         line1 = I915_READ(reg) & line_mask;
1089         msleep(5);
1090         line2 = I915_READ(reg) & line_mask;
1091
1092         return line1 == line2;
1093 }
1094
1095 /*
1096  * intel_wait_for_pipe_off - wait for pipe to turn off
1097  * @crtc: crtc whose pipe to wait for
1098  *
1099  * After disabling a pipe, we can't wait for vblank in the usual way,
1100  * spinning on the vblank interrupt status bit, since we won't actually
1101  * see an interrupt when the pipe is disabled.
1102  *
1103  * On Gen4 and above:
1104  *   wait for the pipe register state bit to turn off
1105  *
1106  * Otherwise:
1107  *   wait for the display line value to settle (it usually
1108  *   ends up stopping at the start of the next frame).
1109  *
1110  */
1111 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1112 {
1113         struct drm_device *dev = crtc->base.dev;
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1116         enum pipe pipe = crtc->pipe;
1117
1118         if (INTEL_INFO(dev)->gen >= 4) {
1119                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1120
1121                 /* Wait for the Pipe State to go off */
1122                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1123                              100))
1124                         WARN(1, "pipe_off wait timed out\n");
1125         } else {
1126                 /* Wait for the display line to settle */
1127                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1128                         WARN(1, "pipe_off wait timed out\n");
1129         }
1130 }
1131
1132 /* Only for pre-ILK configs */
1133 void assert_pll(struct drm_i915_private *dev_priv,
1134                 enum pipe pipe, bool state)
1135 {
1136         u32 val;
1137         bool cur_state;
1138
1139         val = I915_READ(DPLL(pipe));
1140         cur_state = !!(val & DPLL_VCO_ENABLE);
1141         I915_STATE_WARN(cur_state != state,
1142              "PLL state assertion failure (expected %s, current %s)\n",
1143                         onoff(state), onoff(cur_state));
1144 }
1145
1146 /* XXX: the dsi pll is shared between MIPI DSI ports */
1147 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1148 {
1149         u32 val;
1150         bool cur_state;
1151
1152         mutex_lock(&dev_priv->sb_lock);
1153         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1154         mutex_unlock(&dev_priv->sb_lock);
1155
1156         cur_state = val & DSI_PLL_VCO_EN;
1157         I915_STATE_WARN(cur_state != state,
1158              "DSI PLL state assertion failure (expected %s, current %s)\n",
1159                         onoff(state), onoff(cur_state));
1160 }
1161
1162 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1163                           enum pipe pipe, bool state)
1164 {
1165         bool cur_state;
1166         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1167                                                                       pipe);
1168
1169         if (HAS_DDI(dev_priv)) {
1170                 /* DDI does not have a specific FDI_TX register */
1171                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1172                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1173         } else {
1174                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1175                 cur_state = !!(val & FDI_TX_ENABLE);
1176         }
1177         I915_STATE_WARN(cur_state != state,
1178              "FDI TX state assertion failure (expected %s, current %s)\n",
1179                         onoff(state), onoff(cur_state));
1180 }
1181 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1182 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1183
1184 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1185                           enum pipe pipe, bool state)
1186 {
1187         u32 val;
1188         bool cur_state;
1189
1190         val = I915_READ(FDI_RX_CTL(pipe));
1191         cur_state = !!(val & FDI_RX_ENABLE);
1192         I915_STATE_WARN(cur_state != state,
1193              "FDI RX state assertion failure (expected %s, current %s)\n",
1194                         onoff(state), onoff(cur_state));
1195 }
1196 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1197 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1198
1199 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1200                                       enum pipe pipe)
1201 {
1202         u32 val;
1203
1204         /* ILK FDI PLL is always enabled */
1205         if (IS_GEN5(dev_priv))
1206                 return;
1207
1208         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1209         if (HAS_DDI(dev_priv))
1210                 return;
1211
1212         val = I915_READ(FDI_TX_CTL(pipe));
1213         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1214 }
1215
1216 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1217                        enum pipe pipe, bool state)
1218 {
1219         u32 val;
1220         bool cur_state;
1221
1222         val = I915_READ(FDI_RX_CTL(pipe));
1223         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1224         I915_STATE_WARN(cur_state != state,
1225              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1226                         onoff(state), onoff(cur_state));
1227 }
1228
1229 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1230                            enum pipe pipe)
1231 {
1232         struct drm_device *dev = dev_priv->dev;
1233         i915_reg_t pp_reg;
1234         u32 val;
1235         enum pipe panel_pipe = PIPE_A;
1236         bool locked = true;
1237
1238         if (WARN_ON(HAS_DDI(dev)))
1239                 return;
1240
1241         if (HAS_PCH_SPLIT(dev)) {
1242                 u32 port_sel;
1243
1244                 pp_reg = PCH_PP_CONTROL;
1245                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1246
1247                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1248                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1249                         panel_pipe = PIPE_B;
1250                 /* XXX: else fix for eDP */
1251         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1252                 /* presumably write lock depends on pipe, not port select */
1253                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1254                 panel_pipe = pipe;
1255         } else {
1256                 pp_reg = PP_CONTROL;
1257                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1258                         panel_pipe = PIPE_B;
1259         }
1260
1261         val = I915_READ(pp_reg);
1262         if (!(val & PANEL_POWER_ON) ||
1263             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1264                 locked = false;
1265
1266         I915_STATE_WARN(panel_pipe == pipe && locked,
1267              "panel assertion failure, pipe %c regs locked\n",
1268              pipe_name(pipe));
1269 }
1270
1271 static void assert_cursor(struct drm_i915_private *dev_priv,
1272                           enum pipe pipe, bool state)
1273 {
1274         struct drm_device *dev = dev_priv->dev;
1275         bool cur_state;
1276
1277         if (IS_845G(dev) || IS_I865G(dev))
1278                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1279         else
1280                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1281
1282         I915_STATE_WARN(cur_state != state,
1283              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1284                         pipe_name(pipe), onoff(state), onoff(cur_state));
1285 }
1286 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1287 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1288
1289 void assert_pipe(struct drm_i915_private *dev_priv,
1290                  enum pipe pipe, bool state)
1291 {
1292         bool cur_state;
1293         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1294                                                                       pipe);
1295         enum intel_display_power_domain power_domain;
1296
1297         /* if we need the pipe quirk it must be always on */
1298         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1299             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1300                 state = true;
1301
1302         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1303         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1304                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1305                 cur_state = !!(val & PIPECONF_ENABLE);
1306
1307                 intel_display_power_put(dev_priv, power_domain);
1308         } else {
1309                 cur_state = false;
1310         }
1311
1312         I915_STATE_WARN(cur_state != state,
1313              "pipe %c assertion failure (expected %s, current %s)\n",
1314                         pipe_name(pipe), onoff(state), onoff(cur_state));
1315 }
1316
1317 static void assert_plane(struct drm_i915_private *dev_priv,
1318                          enum plane plane, bool state)
1319 {
1320         u32 val;
1321         bool cur_state;
1322
1323         val = I915_READ(DSPCNTR(plane));
1324         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1325         I915_STATE_WARN(cur_state != state,
1326              "plane %c assertion failure (expected %s, current %s)\n",
1327                         plane_name(plane), onoff(state), onoff(cur_state));
1328 }
1329
1330 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1331 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1332
1333 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1334                                    enum pipe pipe)
1335 {
1336         struct drm_device *dev = dev_priv->dev;
1337         int i;
1338
1339         /* Primary planes are fixed to pipes on gen4+ */
1340         if (INTEL_INFO(dev)->gen >= 4) {
1341                 u32 val = I915_READ(DSPCNTR(pipe));
1342                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1343                      "plane %c assertion failure, should be disabled but not\n",
1344                      plane_name(pipe));
1345                 return;
1346         }
1347
1348         /* Need to check both planes against the pipe */
1349         for_each_pipe(dev_priv, i) {
1350                 u32 val = I915_READ(DSPCNTR(i));
1351                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1352                         DISPPLANE_SEL_PIPE_SHIFT;
1353                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1354                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1355                      plane_name(i), pipe_name(pipe));
1356         }
1357 }
1358
1359 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1360                                     enum pipe pipe)
1361 {
1362         struct drm_device *dev = dev_priv->dev;
1363         int sprite;
1364
1365         if (INTEL_INFO(dev)->gen >= 9) {
1366                 for_each_sprite(dev_priv, pipe, sprite) {
1367                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1368                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1369                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1370                              sprite, pipe_name(pipe));
1371                 }
1372         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1373                 for_each_sprite(dev_priv, pipe, sprite) {
1374                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1375                         I915_STATE_WARN(val & SP_ENABLE,
1376                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1377                              sprite_name(pipe, sprite), pipe_name(pipe));
1378                 }
1379         } else if (INTEL_INFO(dev)->gen >= 7) {
1380                 u32 val = I915_READ(SPRCTL(pipe));
1381                 I915_STATE_WARN(val & SPRITE_ENABLE,
1382                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1383                      plane_name(pipe), pipe_name(pipe));
1384         } else if (INTEL_INFO(dev)->gen >= 5) {
1385                 u32 val = I915_READ(DVSCNTR(pipe));
1386                 I915_STATE_WARN(val & DVS_ENABLE,
1387                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1388                      plane_name(pipe), pipe_name(pipe));
1389         }
1390 }
1391
1392 static void assert_vblank_disabled(struct drm_crtc *crtc)
1393 {
1394         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1395                 drm_crtc_vblank_put(crtc);
1396 }
1397
1398 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1399                                     enum pipe pipe)
1400 {
1401         u32 val;
1402         bool enabled;
1403
1404         val = I915_READ(PCH_TRANSCONF(pipe));
1405         enabled = !!(val & TRANS_ENABLE);
1406         I915_STATE_WARN(enabled,
1407              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1408              pipe_name(pipe));
1409 }
1410
1411 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1412                             enum pipe pipe, u32 port_sel, u32 val)
1413 {
1414         if ((val & DP_PORT_EN) == 0)
1415                 return false;
1416
1417         if (HAS_PCH_CPT(dev_priv)) {
1418                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1419                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1420                         return false;
1421         } else if (IS_CHERRYVIEW(dev_priv)) {
1422                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1423                         return false;
1424         } else {
1425                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1426                         return false;
1427         }
1428         return true;
1429 }
1430
1431 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1432                               enum pipe pipe, u32 val)
1433 {
1434         if ((val & SDVO_ENABLE) == 0)
1435                 return false;
1436
1437         if (HAS_PCH_CPT(dev_priv)) {
1438                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1439                         return false;
1440         } else if (IS_CHERRYVIEW(dev_priv)) {
1441                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1442                         return false;
1443         } else {
1444                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1445                         return false;
1446         }
1447         return true;
1448 }
1449
1450 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1451                               enum pipe pipe, u32 val)
1452 {
1453         if ((val & LVDS_PORT_EN) == 0)
1454                 return false;
1455
1456         if (HAS_PCH_CPT(dev_priv)) {
1457                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1458                         return false;
1459         } else {
1460                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1461                         return false;
1462         }
1463         return true;
1464 }
1465
1466 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1467                               enum pipe pipe, u32 val)
1468 {
1469         if ((val & ADPA_DAC_ENABLE) == 0)
1470                 return false;
1471         if (HAS_PCH_CPT(dev_priv)) {
1472                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1473                         return false;
1474         } else {
1475                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1476                         return false;
1477         }
1478         return true;
1479 }
1480
1481 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1482                                    enum pipe pipe, i915_reg_t reg,
1483                                    u32 port_sel)
1484 {
1485         u32 val = I915_READ(reg);
1486         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1487              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1488              i915_mmio_reg_offset(reg), pipe_name(pipe));
1489
1490         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1491              && (val & DP_PIPEB_SELECT),
1492              "IBX PCH dp port still using transcoder B\n");
1493 }
1494
1495 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1496                                      enum pipe pipe, i915_reg_t reg)
1497 {
1498         u32 val = I915_READ(reg);
1499         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1500              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1501              i915_mmio_reg_offset(reg), pipe_name(pipe));
1502
1503         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1504              && (val & SDVO_PIPE_B_SELECT),
1505              "IBX PCH hdmi port still using transcoder B\n");
1506 }
1507
1508 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1509                                       enum pipe pipe)
1510 {
1511         u32 val;
1512
1513         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1514         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1515         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1516
1517         val = I915_READ(PCH_ADPA);
1518         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1519              "PCH VGA enabled on transcoder %c, should be disabled\n",
1520              pipe_name(pipe));
1521
1522         val = I915_READ(PCH_LVDS);
1523         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1524              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1525              pipe_name(pipe));
1526
1527         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1528         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1529         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1530 }
1531
1532 static void _vlv_enable_pll(struct intel_crtc *crtc,
1533                             const struct intel_crtc_state *pipe_config)
1534 {
1535         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1536         enum pipe pipe = crtc->pipe;
1537
1538         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1539         POSTING_READ(DPLL(pipe));
1540         udelay(150);
1541
1542         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1543                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1544 }
1545
1546 static void vlv_enable_pll(struct intel_crtc *crtc,
1547                            const struct intel_crtc_state *pipe_config)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550         enum pipe pipe = crtc->pipe;
1551
1552         assert_pipe_disabled(dev_priv, pipe);
1553
1554         /* PLL is protected by panel, make sure we can write it */
1555         assert_panel_unlocked(dev_priv, pipe);
1556
1557         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1558                 _vlv_enable_pll(crtc, pipe_config);
1559
1560         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1561         POSTING_READ(DPLL_MD(pipe));
1562 }
1563
1564
1565 static void _chv_enable_pll(struct intel_crtc *crtc,
1566                             const struct intel_crtc_state *pipe_config)
1567 {
1568         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1569         enum pipe pipe = crtc->pipe;
1570         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1571         u32 tmp;
1572
1573         mutex_lock(&dev_priv->sb_lock);
1574
1575         /* Enable back the 10bit clock to display controller */
1576         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1577         tmp |= DPIO_DCLKP_EN;
1578         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1579
1580         mutex_unlock(&dev_priv->sb_lock);
1581
1582         /*
1583          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1584          */
1585         udelay(1);
1586
1587         /* Enable PLL */
1588         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1589
1590         /* Check PLL is locked */
1591         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1592                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1593 }
1594
1595 static void chv_enable_pll(struct intel_crtc *crtc,
1596                            const struct intel_crtc_state *pipe_config)
1597 {
1598         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1599         enum pipe pipe = crtc->pipe;
1600
1601         assert_pipe_disabled(dev_priv, pipe);
1602
1603         /* PLL is protected by panel, make sure we can write it */
1604         assert_panel_unlocked(dev_priv, pipe);
1605
1606         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1607                 _chv_enable_pll(crtc, pipe_config);
1608
1609         if (pipe != PIPE_A) {
1610                 /*
1611                  * WaPixelRepeatModeFixForC0:chv
1612                  *
1613                  * DPLLCMD is AWOL. Use chicken bits to propagate
1614                  * the value from DPLLBMD to either pipe B or C.
1615                  */
1616                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1617                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1618                 I915_WRITE(CBR4_VLV, 0);
1619                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1620
1621                 /*
1622                  * DPLLB VGA mode also seems to cause problems.
1623                  * We should always have it disabled.
1624                  */
1625                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1626         } else {
1627                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1628                 POSTING_READ(DPLL_MD(pipe));
1629         }
1630 }
1631
1632 static int intel_num_dvo_pipes(struct drm_device *dev)
1633 {
1634         struct intel_crtc *crtc;
1635         int count = 0;
1636
1637         for_each_intel_crtc(dev, crtc)
1638                 count += crtc->base.state->active &&
1639                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1640
1641         return count;
1642 }
1643
1644 static void i9xx_enable_pll(struct intel_crtc *crtc)
1645 {
1646         struct drm_device *dev = crtc->base.dev;
1647         struct drm_i915_private *dev_priv = dev->dev_private;
1648         i915_reg_t reg = DPLL(crtc->pipe);
1649         u32 dpll = crtc->config->dpll_hw_state.dpll;
1650
1651         assert_pipe_disabled(dev_priv, crtc->pipe);
1652
1653         /* PLL is protected by panel, make sure we can write it */
1654         if (IS_MOBILE(dev) && !IS_I830(dev))
1655                 assert_panel_unlocked(dev_priv, crtc->pipe);
1656
1657         /* Enable DVO 2x clock on both PLLs if necessary */
1658         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1659                 /*
1660                  * It appears to be important that we don't enable this
1661                  * for the current pipe before otherwise configuring the
1662                  * PLL. No idea how this should be handled if multiple
1663                  * DVO outputs are enabled simultaneosly.
1664                  */
1665                 dpll |= DPLL_DVO_2X_MODE;
1666                 I915_WRITE(DPLL(!crtc->pipe),
1667                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1668         }
1669
1670         /*
1671          * Apparently we need to have VGA mode enabled prior to changing
1672          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1673          * dividers, even though the register value does change.
1674          */
1675         I915_WRITE(reg, 0);
1676
1677         I915_WRITE(reg, dpll);
1678
1679         /* Wait for the clocks to stabilize. */
1680         POSTING_READ(reg);
1681         udelay(150);
1682
1683         if (INTEL_INFO(dev)->gen >= 4) {
1684                 I915_WRITE(DPLL_MD(crtc->pipe),
1685                            crtc->config->dpll_hw_state.dpll_md);
1686         } else {
1687                 /* The pixel multiplier can only be updated once the
1688                  * DPLL is enabled and the clocks are stable.
1689                  *
1690                  * So write it again.
1691                  */
1692                 I915_WRITE(reg, dpll);
1693         }
1694
1695         /* We do this three times for luck */
1696         I915_WRITE(reg, dpll);
1697         POSTING_READ(reg);
1698         udelay(150); /* wait for warmup */
1699         I915_WRITE(reg, dpll);
1700         POSTING_READ(reg);
1701         udelay(150); /* wait for warmup */
1702         I915_WRITE(reg, dpll);
1703         POSTING_READ(reg);
1704         udelay(150); /* wait for warmup */
1705 }
1706
1707 /**
1708  * i9xx_disable_pll - disable a PLL
1709  * @dev_priv: i915 private structure
1710  * @pipe: pipe PLL to disable
1711  *
1712  * Disable the PLL for @pipe, making sure the pipe is off first.
1713  *
1714  * Note!  This is for pre-ILK only.
1715  */
1716 static void i9xx_disable_pll(struct intel_crtc *crtc)
1717 {
1718         struct drm_device *dev = crtc->base.dev;
1719         struct drm_i915_private *dev_priv = dev->dev_private;
1720         enum pipe pipe = crtc->pipe;
1721
1722         /* Disable DVO 2x clock on both PLLs if necessary */
1723         if (IS_I830(dev) &&
1724             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1725             !intel_num_dvo_pipes(dev)) {
1726                 I915_WRITE(DPLL(PIPE_B),
1727                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1728                 I915_WRITE(DPLL(PIPE_A),
1729                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1730         }
1731
1732         /* Don't disable pipe or pipe PLLs if needed */
1733         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1734             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1735                 return;
1736
1737         /* Make sure the pipe isn't still relying on us */
1738         assert_pipe_disabled(dev_priv, pipe);
1739
1740         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1741         POSTING_READ(DPLL(pipe));
1742 }
1743
1744 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1745 {
1746         u32 val;
1747
1748         /* Make sure the pipe isn't still relying on us */
1749         assert_pipe_disabled(dev_priv, pipe);
1750
1751         val = DPLL_INTEGRATED_REF_CLK_VLV |
1752                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1753         if (pipe != PIPE_A)
1754                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1755
1756         I915_WRITE(DPLL(pipe), val);
1757         POSTING_READ(DPLL(pipe));
1758 }
1759
1760 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1761 {
1762         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1763         u32 val;
1764
1765         /* Make sure the pipe isn't still relying on us */
1766         assert_pipe_disabled(dev_priv, pipe);
1767
1768         val = DPLL_SSC_REF_CLK_CHV |
1769                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1770         if (pipe != PIPE_A)
1771                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1772
1773         I915_WRITE(DPLL(pipe), val);
1774         POSTING_READ(DPLL(pipe));
1775
1776         mutex_lock(&dev_priv->sb_lock);
1777
1778         /* Disable 10bit clock to display controller */
1779         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1780         val &= ~DPIO_DCLKP_EN;
1781         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1782
1783         mutex_unlock(&dev_priv->sb_lock);
1784 }
1785
1786 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1787                          struct intel_digital_port *dport,
1788                          unsigned int expected_mask)
1789 {
1790         u32 port_mask;
1791         i915_reg_t dpll_reg;
1792
1793         switch (dport->port) {
1794         case PORT_B:
1795                 port_mask = DPLL_PORTB_READY_MASK;
1796                 dpll_reg = DPLL(0);
1797                 break;
1798         case PORT_C:
1799                 port_mask = DPLL_PORTC_READY_MASK;
1800                 dpll_reg = DPLL(0);
1801                 expected_mask <<= 4;
1802                 break;
1803         case PORT_D:
1804                 port_mask = DPLL_PORTD_READY_MASK;
1805                 dpll_reg = DPIO_PHY_STATUS;
1806                 break;
1807         default:
1808                 BUG();
1809         }
1810
1811         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1812                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1813                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1814 }
1815
1816 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1817                                            enum pipe pipe)
1818 {
1819         struct drm_device *dev = dev_priv->dev;
1820         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1822         i915_reg_t reg;
1823         uint32_t val, pipeconf_val;
1824
1825         /* Make sure PCH DPLL is enabled */
1826         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1827
1828         /* FDI must be feeding us bits for PCH ports */
1829         assert_fdi_tx_enabled(dev_priv, pipe);
1830         assert_fdi_rx_enabled(dev_priv, pipe);
1831
1832         if (HAS_PCH_CPT(dev)) {
1833                 /* Workaround: Set the timing override bit before enabling the
1834                  * pch transcoder. */
1835                 reg = TRANS_CHICKEN2(pipe);
1836                 val = I915_READ(reg);
1837                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1838                 I915_WRITE(reg, val);
1839         }
1840
1841         reg = PCH_TRANSCONF(pipe);
1842         val = I915_READ(reg);
1843         pipeconf_val = I915_READ(PIPECONF(pipe));
1844
1845         if (HAS_PCH_IBX(dev_priv)) {
1846                 /*
1847                  * Make the BPC in transcoder be consistent with
1848                  * that in pipeconf reg. For HDMI we must use 8bpc
1849                  * here for both 8bpc and 12bpc.
1850                  */
1851                 val &= ~PIPECONF_BPC_MASK;
1852                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1853                         val |= PIPECONF_8BPC;
1854                 else
1855                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1856         }
1857
1858         val &= ~TRANS_INTERLACE_MASK;
1859         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1860                 if (HAS_PCH_IBX(dev_priv) &&
1861                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1862                         val |= TRANS_LEGACY_INTERLACED_ILK;
1863                 else
1864                         val |= TRANS_INTERLACED;
1865         else
1866                 val |= TRANS_PROGRESSIVE;
1867
1868         I915_WRITE(reg, val | TRANS_ENABLE);
1869         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1870                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1871 }
1872
1873 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1874                                       enum transcoder cpu_transcoder)
1875 {
1876         u32 val, pipeconf_val;
1877
1878         /* FDI must be feeding us bits for PCH ports */
1879         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1880         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1881
1882         /* Workaround: set timing override bit. */
1883         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1884         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1885         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1886
1887         val = TRANS_ENABLE;
1888         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1889
1890         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1891             PIPECONF_INTERLACED_ILK)
1892                 val |= TRANS_INTERLACED;
1893         else
1894                 val |= TRANS_PROGRESSIVE;
1895
1896         I915_WRITE(LPT_TRANSCONF, val);
1897         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1898                 DRM_ERROR("Failed to enable PCH transcoder\n");
1899 }
1900
1901 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1902                                             enum pipe pipe)
1903 {
1904         struct drm_device *dev = dev_priv->dev;
1905         i915_reg_t reg;
1906         uint32_t val;
1907
1908         /* FDI relies on the transcoder */
1909         assert_fdi_tx_disabled(dev_priv, pipe);
1910         assert_fdi_rx_disabled(dev_priv, pipe);
1911
1912         /* Ports must be off as well */
1913         assert_pch_ports_disabled(dev_priv, pipe);
1914
1915         reg = PCH_TRANSCONF(pipe);
1916         val = I915_READ(reg);
1917         val &= ~TRANS_ENABLE;
1918         I915_WRITE(reg, val);
1919         /* wait for PCH transcoder off, transcoder state */
1920         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1921                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1922
1923         if (HAS_PCH_CPT(dev)) {
1924                 /* Workaround: Clear the timing override chicken bit again. */
1925                 reg = TRANS_CHICKEN2(pipe);
1926                 val = I915_READ(reg);
1927                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1928                 I915_WRITE(reg, val);
1929         }
1930 }
1931
1932 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1933 {
1934         u32 val;
1935
1936         val = I915_READ(LPT_TRANSCONF);
1937         val &= ~TRANS_ENABLE;
1938         I915_WRITE(LPT_TRANSCONF, val);
1939         /* wait for PCH transcoder off, transcoder state */
1940         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1941                 DRM_ERROR("Failed to disable PCH transcoder\n");
1942
1943         /* Workaround: clear timing override bit. */
1944         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1945         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1946         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1947 }
1948
1949 /**
1950  * intel_enable_pipe - enable a pipe, asserting requirements
1951  * @crtc: crtc responsible for the pipe
1952  *
1953  * Enable @crtc's pipe, making sure that various hardware specific requirements
1954  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1955  */
1956 static void intel_enable_pipe(struct intel_crtc *crtc)
1957 {
1958         struct drm_device *dev = crtc->base.dev;
1959         struct drm_i915_private *dev_priv = dev->dev_private;
1960         enum pipe pipe = crtc->pipe;
1961         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1962         enum pipe pch_transcoder;
1963         i915_reg_t reg;
1964         u32 val;
1965
1966         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1967
1968         assert_planes_disabled(dev_priv, pipe);
1969         assert_cursor_disabled(dev_priv, pipe);
1970         assert_sprites_disabled(dev_priv, pipe);
1971
1972         if (HAS_PCH_LPT(dev_priv))
1973                 pch_transcoder = TRANSCODER_A;
1974         else
1975                 pch_transcoder = pipe;
1976
1977         /*
1978          * A pipe without a PLL won't actually be able to drive bits from
1979          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1980          * need the check.
1981          */
1982         if (HAS_GMCH_DISPLAY(dev_priv))
1983                 if (crtc->config->has_dsi_encoder)
1984                         assert_dsi_pll_enabled(dev_priv);
1985                 else
1986                         assert_pll_enabled(dev_priv, pipe);
1987         else {
1988                 if (crtc->config->has_pch_encoder) {
1989                         /* if driving the PCH, we need FDI enabled */
1990                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1991                         assert_fdi_tx_pll_enabled(dev_priv,
1992                                                   (enum pipe) cpu_transcoder);
1993                 }
1994                 /* FIXME: assert CPU port conditions for SNB+ */
1995         }
1996
1997         reg = PIPECONF(cpu_transcoder);
1998         val = I915_READ(reg);
1999         if (val & PIPECONF_ENABLE) {
2000                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2001                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2002                 return;
2003         }
2004
2005         I915_WRITE(reg, val | PIPECONF_ENABLE);
2006         POSTING_READ(reg);
2007
2008         /*
2009          * Until the pipe starts DSL will read as 0, which would cause
2010          * an apparent vblank timestamp jump, which messes up also the
2011          * frame count when it's derived from the timestamps. So let's
2012          * wait for the pipe to start properly before we call
2013          * drm_crtc_vblank_on()
2014          */
2015         if (dev->max_vblank_count == 0 &&
2016             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2017                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2018 }
2019
2020 /**
2021  * intel_disable_pipe - disable a pipe, asserting requirements
2022  * @crtc: crtc whose pipes is to be disabled
2023  *
2024  * Disable the pipe of @crtc, making sure that various hardware
2025  * specific requirements are met, if applicable, e.g. plane
2026  * disabled, panel fitter off, etc.
2027  *
2028  * Will wait until the pipe has shut down before returning.
2029  */
2030 static void intel_disable_pipe(struct intel_crtc *crtc)
2031 {
2032         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2033         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2034         enum pipe pipe = crtc->pipe;
2035         i915_reg_t reg;
2036         u32 val;
2037
2038         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2039
2040         /*
2041          * Make sure planes won't keep trying to pump pixels to us,
2042          * or we might hang the display.
2043          */
2044         assert_planes_disabled(dev_priv, pipe);
2045         assert_cursor_disabled(dev_priv, pipe);
2046         assert_sprites_disabled(dev_priv, pipe);
2047
2048         reg = PIPECONF(cpu_transcoder);
2049         val = I915_READ(reg);
2050         if ((val & PIPECONF_ENABLE) == 0)
2051                 return;
2052
2053         /*
2054          * Double wide has implications for planes
2055          * so best keep it disabled when not needed.
2056          */
2057         if (crtc->config->double_wide)
2058                 val &= ~PIPECONF_DOUBLE_WIDE;
2059
2060         /* Don't disable pipe or pipe PLLs if needed */
2061         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2062             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2063                 val &= ~PIPECONF_ENABLE;
2064
2065         I915_WRITE(reg, val);
2066         if ((val & PIPECONF_ENABLE) == 0)
2067                 intel_wait_for_pipe_off(crtc);
2068 }
2069
2070 static bool need_vtd_wa(struct drm_device *dev)
2071 {
2072 #ifdef CONFIG_INTEL_IOMMU
2073         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2074                 return true;
2075 #endif
2076         return false;
2077 }
2078
2079 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2080 {
2081         return IS_GEN2(dev_priv) ? 2048 : 4096;
2082 }
2083
2084 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2085                                            uint64_t fb_modifier, unsigned int cpp)
2086 {
2087         switch (fb_modifier) {
2088         case DRM_FORMAT_MOD_NONE:
2089                 return cpp;
2090         case I915_FORMAT_MOD_X_TILED:
2091                 if (IS_GEN2(dev_priv))
2092                         return 128;
2093                 else
2094                         return 512;
2095         case I915_FORMAT_MOD_Y_TILED:
2096                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2097                         return 128;
2098                 else
2099                         return 512;
2100         case I915_FORMAT_MOD_Yf_TILED:
2101                 switch (cpp) {
2102                 case 1:
2103                         return 64;
2104                 case 2:
2105                 case 4:
2106                         return 128;
2107                 case 8:
2108                 case 16:
2109                         return 256;
2110                 default:
2111                         MISSING_CASE(cpp);
2112                         return cpp;
2113                 }
2114                 break;
2115         default:
2116                 MISSING_CASE(fb_modifier);
2117                 return cpp;
2118         }
2119 }
2120
2121 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2122                                uint64_t fb_modifier, unsigned int cpp)
2123 {
2124         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2125                 return 1;
2126         else
2127                 return intel_tile_size(dev_priv) /
2128                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2129 }
2130
2131 /* Return the tile dimensions in pixel units */
2132 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2133                             unsigned int *tile_width,
2134                             unsigned int *tile_height,
2135                             uint64_t fb_modifier,
2136                             unsigned int cpp)
2137 {
2138         unsigned int tile_width_bytes =
2139                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2140
2141         *tile_width = tile_width_bytes / cpp;
2142         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2143 }
2144
2145 unsigned int
2146 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2147                       uint32_t pixel_format, uint64_t fb_modifier)
2148 {
2149         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2150         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2151
2152         return ALIGN(height, tile_height);
2153 }
2154
2155 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2156 {
2157         unsigned int size = 0;
2158         int i;
2159
2160         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2161                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2162
2163         return size;
2164 }
2165
2166 static void
2167 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2168                         const struct drm_framebuffer *fb,
2169                         unsigned int rotation)
2170 {
2171         if (intel_rotation_90_or_270(rotation)) {
2172                 *view = i915_ggtt_view_rotated;
2173                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2174         } else {
2175                 *view = i915_ggtt_view_normal;
2176         }
2177 }
2178
2179 static void
2180 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2181                    struct drm_framebuffer *fb)
2182 {
2183         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2184         unsigned int tile_size, tile_width, tile_height, cpp;
2185
2186         tile_size = intel_tile_size(dev_priv);
2187
2188         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2189         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2190                         fb->modifier[0], cpp);
2191
2192         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2193         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2194
2195         if (info->pixel_format == DRM_FORMAT_NV12) {
2196                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2197                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2198                                 fb->modifier[1], cpp);
2199
2200                 info->uv_offset = fb->offsets[1];
2201                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2202                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2203         }
2204 }
2205
2206 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2207 {
2208         if (INTEL_INFO(dev_priv)->gen >= 9)
2209                 return 256 * 1024;
2210         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2211                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2212                 return 128 * 1024;
2213         else if (INTEL_INFO(dev_priv)->gen >= 4)
2214                 return 4 * 1024;
2215         else
2216                 return 0;
2217 }
2218
2219 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2220                                          uint64_t fb_modifier)
2221 {
2222         switch (fb_modifier) {
2223         case DRM_FORMAT_MOD_NONE:
2224                 return intel_linear_alignment(dev_priv);
2225         case I915_FORMAT_MOD_X_TILED:
2226                 if (INTEL_INFO(dev_priv)->gen >= 9)
2227                         return 256 * 1024;
2228                 return 0;
2229         case I915_FORMAT_MOD_Y_TILED:
2230         case I915_FORMAT_MOD_Yf_TILED:
2231                 return 1 * 1024 * 1024;
2232         default:
2233                 MISSING_CASE(fb_modifier);
2234                 return 0;
2235         }
2236 }
2237
2238 int
2239 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2240                            unsigned int rotation)
2241 {
2242         struct drm_device *dev = fb->dev;
2243         struct drm_i915_private *dev_priv = dev->dev_private;
2244         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2245         struct i915_ggtt_view view;
2246         u32 alignment;
2247         int ret;
2248
2249         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2250
2251         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2252
2253         intel_fill_fb_ggtt_view(&view, fb, rotation);
2254
2255         /* Note that the w/a also requires 64 PTE of padding following the
2256          * bo. We currently fill all unused PTE with the shadow page and so
2257          * we should always have valid PTE following the scanout preventing
2258          * the VT-d warning.
2259          */
2260         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2261                 alignment = 256 * 1024;
2262
2263         /*
2264          * Global gtt pte registers are special registers which actually forward
2265          * writes to a chunk of system memory. Which means that there is no risk
2266          * that the register values disappear as soon as we call
2267          * intel_runtime_pm_put(), so it is correct to wrap only the
2268          * pin/unpin/fence and not more.
2269          */
2270         intel_runtime_pm_get(dev_priv);
2271
2272         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2273                                                    &view);
2274         if (ret)
2275                 goto err_pm;
2276
2277         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2278          * fence, whereas 965+ only requires a fence if using
2279          * framebuffer compression.  For simplicity, we always install
2280          * a fence as the cost is not that onerous.
2281          */
2282         if (view.type == I915_GGTT_VIEW_NORMAL) {
2283                 ret = i915_gem_object_get_fence(obj);
2284                 if (ret == -EDEADLK) {
2285                         /*
2286                          * -EDEADLK means there are no free fences
2287                          * no pending flips.
2288                          *
2289                          * This is propagated to atomic, but it uses
2290                          * -EDEADLK to force a locking recovery, so
2291                          * change the returned error to -EBUSY.
2292                          */
2293                         ret = -EBUSY;
2294                         goto err_unpin;
2295                 } else if (ret)
2296                         goto err_unpin;
2297
2298                 i915_gem_object_pin_fence(obj);
2299         }
2300
2301         intel_runtime_pm_put(dev_priv);
2302         return 0;
2303
2304 err_unpin:
2305         i915_gem_object_unpin_from_display_plane(obj, &view);
2306 err_pm:
2307         intel_runtime_pm_put(dev_priv);
2308         return ret;
2309 }
2310
2311 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2312 {
2313         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2314         struct i915_ggtt_view view;
2315
2316         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2317
2318         intel_fill_fb_ggtt_view(&view, fb, rotation);
2319
2320         if (view.type == I915_GGTT_VIEW_NORMAL)
2321                 i915_gem_object_unpin_fence(obj);
2322
2323         i915_gem_object_unpin_from_display_plane(obj, &view);
2324 }
2325
2326 /*
2327  * Adjust the tile offset by moving the difference into
2328  * the x/y offsets.
2329  *
2330  * Input tile dimensions and pitch must already be
2331  * rotated to match x and y, and in pixel units.
2332  */
2333 static u32 intel_adjust_tile_offset(int *x, int *y,
2334                                     unsigned int tile_width,
2335                                     unsigned int tile_height,
2336                                     unsigned int tile_size,
2337                                     unsigned int pitch_tiles,
2338                                     u32 old_offset,
2339                                     u32 new_offset)
2340 {
2341         unsigned int tiles;
2342
2343         WARN_ON(old_offset & (tile_size - 1));
2344         WARN_ON(new_offset & (tile_size - 1));
2345         WARN_ON(new_offset > old_offset);
2346
2347         tiles = (old_offset - new_offset) / tile_size;
2348
2349         *y += tiles / pitch_tiles * tile_height;
2350         *x += tiles % pitch_tiles * tile_width;
2351
2352         return new_offset;
2353 }
2354
2355 /*
2356  * Computes the linear offset to the base tile and adjusts
2357  * x, y. bytes per pixel is assumed to be a power-of-two.
2358  *
2359  * In the 90/270 rotated case, x and y are assumed
2360  * to be already rotated to match the rotated GTT view, and
2361  * pitch is the tile_height aligned framebuffer height.
2362  */
2363 u32 intel_compute_tile_offset(int *x, int *y,
2364                               const struct drm_framebuffer *fb, int plane,
2365                               unsigned int pitch,
2366                               unsigned int rotation)
2367 {
2368         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2369         uint64_t fb_modifier = fb->modifier[plane];
2370         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2371         u32 offset, offset_aligned, alignment;
2372
2373         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2374         if (alignment)
2375                 alignment--;
2376
2377         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2378                 unsigned int tile_size, tile_width, tile_height;
2379                 unsigned int tile_rows, tiles, pitch_tiles;
2380
2381                 tile_size = intel_tile_size(dev_priv);
2382                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2383                                 fb_modifier, cpp);
2384
2385                 if (intel_rotation_90_or_270(rotation)) {
2386                         pitch_tiles = pitch / tile_height;
2387                         swap(tile_width, tile_height);
2388                 } else {
2389                         pitch_tiles = pitch / (tile_width * cpp);
2390                 }
2391
2392                 tile_rows = *y / tile_height;
2393                 *y %= tile_height;
2394
2395                 tiles = *x / tile_width;
2396                 *x %= tile_width;
2397
2398                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2399                 offset_aligned = offset & ~alignment;
2400
2401                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2402                                          tile_size, pitch_tiles,
2403                                          offset, offset_aligned);
2404         } else {
2405                 offset = *y * pitch + *x * cpp;
2406                 offset_aligned = offset & ~alignment;
2407
2408                 *y = (offset & alignment) / pitch;
2409                 *x = ((offset & alignment) - *y * pitch) / cpp;
2410         }
2411
2412         return offset_aligned;
2413 }
2414
2415 static int i9xx_format_to_fourcc(int format)
2416 {
2417         switch (format) {
2418         case DISPPLANE_8BPP:
2419                 return DRM_FORMAT_C8;
2420         case DISPPLANE_BGRX555:
2421                 return DRM_FORMAT_XRGB1555;
2422         case DISPPLANE_BGRX565:
2423                 return DRM_FORMAT_RGB565;
2424         default:
2425         case DISPPLANE_BGRX888:
2426                 return DRM_FORMAT_XRGB8888;
2427         case DISPPLANE_RGBX888:
2428                 return DRM_FORMAT_XBGR8888;
2429         case DISPPLANE_BGRX101010:
2430                 return DRM_FORMAT_XRGB2101010;
2431         case DISPPLANE_RGBX101010:
2432                 return DRM_FORMAT_XBGR2101010;
2433         }
2434 }
2435
2436 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2437 {
2438         switch (format) {
2439         case PLANE_CTL_FORMAT_RGB_565:
2440                 return DRM_FORMAT_RGB565;
2441         default:
2442         case PLANE_CTL_FORMAT_XRGB_8888:
2443                 if (rgb_order) {
2444                         if (alpha)
2445                                 return DRM_FORMAT_ABGR8888;
2446                         else
2447                                 return DRM_FORMAT_XBGR8888;
2448                 } else {
2449                         if (alpha)
2450                                 return DRM_FORMAT_ARGB8888;
2451                         else
2452                                 return DRM_FORMAT_XRGB8888;
2453                 }
2454         case PLANE_CTL_FORMAT_XRGB_2101010:
2455                 if (rgb_order)
2456                         return DRM_FORMAT_XBGR2101010;
2457                 else
2458                         return DRM_FORMAT_XRGB2101010;
2459         }
2460 }
2461
2462 static bool
2463 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2464                               struct intel_initial_plane_config *plane_config)
2465 {
2466         struct drm_device *dev = crtc->base.dev;
2467         struct drm_i915_private *dev_priv = to_i915(dev);
2468         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2469         struct drm_i915_gem_object *obj = NULL;
2470         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2471         struct drm_framebuffer *fb = &plane_config->fb->base;
2472         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2473         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2474                                     PAGE_SIZE);
2475
2476         size_aligned -= base_aligned;
2477
2478         if (plane_config->size == 0)
2479                 return false;
2480
2481         /* If the FB is too big, just don't use it since fbdev is not very
2482          * important and we should probably use that space with FBC or other
2483          * features. */
2484         if (size_aligned * 2 > ggtt->stolen_usable_size)
2485                 return false;
2486
2487         mutex_lock(&dev->struct_mutex);
2488
2489         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2490                                                              base_aligned,
2491                                                              base_aligned,
2492                                                              size_aligned);
2493         if (!obj) {
2494                 mutex_unlock(&dev->struct_mutex);
2495                 return false;
2496         }
2497
2498         obj->tiling_mode = plane_config->tiling;
2499         if (obj->tiling_mode == I915_TILING_X)
2500                 obj->stride = fb->pitches[0];
2501
2502         mode_cmd.pixel_format = fb->pixel_format;
2503         mode_cmd.width = fb->width;
2504         mode_cmd.height = fb->height;
2505         mode_cmd.pitches[0] = fb->pitches[0];
2506         mode_cmd.modifier[0] = fb->modifier[0];
2507         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2508
2509         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2510                                    &mode_cmd, obj)) {
2511                 DRM_DEBUG_KMS("intel fb init failed\n");
2512                 goto out_unref_obj;
2513         }
2514
2515         mutex_unlock(&dev->struct_mutex);
2516
2517         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2518         return true;
2519
2520 out_unref_obj:
2521         drm_gem_object_unreference(&obj->base);
2522         mutex_unlock(&dev->struct_mutex);
2523         return false;
2524 }
2525
2526 static void
2527 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2528                              struct intel_initial_plane_config *plane_config)
2529 {
2530         struct drm_device *dev = intel_crtc->base.dev;
2531         struct drm_i915_private *dev_priv = dev->dev_private;
2532         struct drm_crtc *c;
2533         struct intel_crtc *i;
2534         struct drm_i915_gem_object *obj;
2535         struct drm_plane *primary = intel_crtc->base.primary;
2536         struct drm_plane_state *plane_state = primary->state;
2537         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2538         struct intel_plane *intel_plane = to_intel_plane(primary);
2539         struct intel_plane_state *intel_state =
2540                 to_intel_plane_state(plane_state);
2541         struct drm_framebuffer *fb;
2542
2543         if (!plane_config->fb)
2544                 return;
2545
2546         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2547                 fb = &plane_config->fb->base;
2548                 goto valid_fb;
2549         }
2550
2551         kfree(plane_config->fb);
2552
2553         /*
2554          * Failed to alloc the obj, check to see if we should share
2555          * an fb with another CRTC instead
2556          */
2557         for_each_crtc(dev, c) {
2558                 i = to_intel_crtc(c);
2559
2560                 if (c == &intel_crtc->base)
2561                         continue;
2562
2563                 if (!i->active)
2564                         continue;
2565
2566                 fb = c->primary->fb;
2567                 if (!fb)
2568                         continue;
2569
2570                 obj = intel_fb_obj(fb);
2571                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2572                         drm_framebuffer_reference(fb);
2573                         goto valid_fb;
2574                 }
2575         }
2576
2577         /*
2578          * We've failed to reconstruct the BIOS FB.  Current display state
2579          * indicates that the primary plane is visible, but has a NULL FB,
2580          * which will lead to problems later if we don't fix it up.  The
2581          * simplest solution is to just disable the primary plane now and
2582          * pretend the BIOS never had it enabled.
2583          */
2584         to_intel_plane_state(plane_state)->visible = false;
2585         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2586         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2587         intel_plane->disable_plane(primary, &intel_crtc->base);
2588
2589         return;
2590
2591 valid_fb:
2592         plane_state->src_x = 0;
2593         plane_state->src_y = 0;
2594         plane_state->src_w = fb->width << 16;
2595         plane_state->src_h = fb->height << 16;
2596
2597         plane_state->crtc_x = 0;
2598         plane_state->crtc_y = 0;
2599         plane_state->crtc_w = fb->width;
2600         plane_state->crtc_h = fb->height;
2601
2602         intel_state->src.x1 = plane_state->src_x;
2603         intel_state->src.y1 = plane_state->src_y;
2604         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2605         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2606         intel_state->dst.x1 = plane_state->crtc_x;
2607         intel_state->dst.y1 = plane_state->crtc_y;
2608         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2609         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2610
2611         obj = intel_fb_obj(fb);
2612         if (obj->tiling_mode != I915_TILING_NONE)
2613                 dev_priv->preserve_bios_swizzle = true;
2614
2615         drm_framebuffer_reference(fb);
2616         primary->fb = primary->state->fb = fb;
2617         primary->crtc = primary->state->crtc = &intel_crtc->base;
2618         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2619         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2620 }
2621
2622 static void i9xx_update_primary_plane(struct drm_plane *primary,
2623                                       const struct intel_crtc_state *crtc_state,
2624                                       const struct intel_plane_state *plane_state)
2625 {
2626         struct drm_device *dev = primary->dev;
2627         struct drm_i915_private *dev_priv = dev->dev_private;
2628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2629         struct drm_framebuffer *fb = plane_state->base.fb;
2630         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2631         int plane = intel_crtc->plane;
2632         u32 linear_offset;
2633         u32 dspcntr;
2634         i915_reg_t reg = DSPCNTR(plane);
2635         unsigned int rotation = plane_state->base.rotation;
2636         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2637         int x = plane_state->src.x1 >> 16;
2638         int y = plane_state->src.y1 >> 16;
2639
2640         dspcntr = DISPPLANE_GAMMA_ENABLE;
2641
2642         dspcntr |= DISPLAY_PLANE_ENABLE;
2643
2644         if (INTEL_INFO(dev)->gen < 4) {
2645                 if (intel_crtc->pipe == PIPE_B)
2646                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2647
2648                 /* pipesrc and dspsize control the size that is scaled from,
2649                  * which should always be the user's requested size.
2650                  */
2651                 I915_WRITE(DSPSIZE(plane),
2652                            ((crtc_state->pipe_src_h - 1) << 16) |
2653                            (crtc_state->pipe_src_w - 1));
2654                 I915_WRITE(DSPPOS(plane), 0);
2655         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2656                 I915_WRITE(PRIMSIZE(plane),
2657                            ((crtc_state->pipe_src_h - 1) << 16) |
2658                            (crtc_state->pipe_src_w - 1));
2659                 I915_WRITE(PRIMPOS(plane), 0);
2660                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2661         }
2662
2663         switch (fb->pixel_format) {
2664         case DRM_FORMAT_C8:
2665                 dspcntr |= DISPPLANE_8BPP;
2666                 break;
2667         case DRM_FORMAT_XRGB1555:
2668                 dspcntr |= DISPPLANE_BGRX555;
2669                 break;
2670         case DRM_FORMAT_RGB565:
2671                 dspcntr |= DISPPLANE_BGRX565;
2672                 break;
2673         case DRM_FORMAT_XRGB8888:
2674                 dspcntr |= DISPPLANE_BGRX888;
2675                 break;
2676         case DRM_FORMAT_XBGR8888:
2677                 dspcntr |= DISPPLANE_RGBX888;
2678                 break;
2679         case DRM_FORMAT_XRGB2101010:
2680                 dspcntr |= DISPPLANE_BGRX101010;
2681                 break;
2682         case DRM_FORMAT_XBGR2101010:
2683                 dspcntr |= DISPPLANE_RGBX101010;
2684                 break;
2685         default:
2686                 BUG();
2687         }
2688
2689         if (INTEL_INFO(dev)->gen >= 4 &&
2690             obj->tiling_mode != I915_TILING_NONE)
2691                 dspcntr |= DISPPLANE_TILED;
2692
2693         if (IS_G4X(dev))
2694                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2695
2696         linear_offset = y * fb->pitches[0] + x * cpp;
2697
2698         if (INTEL_INFO(dev)->gen >= 4) {
2699                 intel_crtc->dspaddr_offset =
2700                         intel_compute_tile_offset(&x, &y, fb, 0,
2701                                                   fb->pitches[0], rotation);
2702                 linear_offset -= intel_crtc->dspaddr_offset;
2703         } else {
2704                 intel_crtc->dspaddr_offset = linear_offset;
2705         }
2706
2707         if (rotation == BIT(DRM_ROTATE_180)) {
2708                 dspcntr |= DISPPLANE_ROTATE_180;
2709
2710                 x += (crtc_state->pipe_src_w - 1);
2711                 y += (crtc_state->pipe_src_h - 1);
2712
2713                 /* Finding the last pixel of the last line of the display
2714                 data and adding to linear_offset*/
2715                 linear_offset +=
2716                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2717                         (crtc_state->pipe_src_w - 1) * cpp;
2718         }
2719
2720         intel_crtc->adjusted_x = x;
2721         intel_crtc->adjusted_y = y;
2722
2723         I915_WRITE(reg, dspcntr);
2724
2725         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2726         if (INTEL_INFO(dev)->gen >= 4) {
2727                 I915_WRITE(DSPSURF(plane),
2728                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2729                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2730                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2731         } else
2732                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2733         POSTING_READ(reg);
2734 }
2735
2736 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2737                                        struct drm_crtc *crtc)
2738 {
2739         struct drm_device *dev = crtc->dev;
2740         struct drm_i915_private *dev_priv = dev->dev_private;
2741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2742         int plane = intel_crtc->plane;
2743
2744         I915_WRITE(DSPCNTR(plane), 0);
2745         if (INTEL_INFO(dev_priv)->gen >= 4)
2746                 I915_WRITE(DSPSURF(plane), 0);
2747         else
2748                 I915_WRITE(DSPADDR(plane), 0);
2749         POSTING_READ(DSPCNTR(plane));
2750 }
2751
2752 static void ironlake_update_primary_plane(struct drm_plane *primary,
2753                                           const struct intel_crtc_state *crtc_state,
2754                                           const struct intel_plane_state *plane_state)
2755 {
2756         struct drm_device *dev = primary->dev;
2757         struct drm_i915_private *dev_priv = dev->dev_private;
2758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2759         struct drm_framebuffer *fb = plane_state->base.fb;
2760         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2761         int plane = intel_crtc->plane;
2762         u32 linear_offset;
2763         u32 dspcntr;
2764         i915_reg_t reg = DSPCNTR(plane);
2765         unsigned int rotation = plane_state->base.rotation;
2766         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2767         int x = plane_state->src.x1 >> 16;
2768         int y = plane_state->src.y1 >> 16;
2769
2770         dspcntr = DISPPLANE_GAMMA_ENABLE;
2771         dspcntr |= DISPLAY_PLANE_ENABLE;
2772
2773         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2774                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2775
2776         switch (fb->pixel_format) {
2777         case DRM_FORMAT_C8:
2778                 dspcntr |= DISPPLANE_8BPP;
2779                 break;
2780         case DRM_FORMAT_RGB565:
2781                 dspcntr |= DISPPLANE_BGRX565;
2782                 break;
2783         case DRM_FORMAT_XRGB8888:
2784                 dspcntr |= DISPPLANE_BGRX888;
2785                 break;
2786         case DRM_FORMAT_XBGR8888:
2787                 dspcntr |= DISPPLANE_RGBX888;
2788                 break;
2789         case DRM_FORMAT_XRGB2101010:
2790                 dspcntr |= DISPPLANE_BGRX101010;
2791                 break;
2792         case DRM_FORMAT_XBGR2101010:
2793                 dspcntr |= DISPPLANE_RGBX101010;
2794                 break;
2795         default:
2796                 BUG();
2797         }
2798
2799         if (obj->tiling_mode != I915_TILING_NONE)
2800                 dspcntr |= DISPPLANE_TILED;
2801
2802         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2803                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2804
2805         linear_offset = y * fb->pitches[0] + x * cpp;
2806         intel_crtc->dspaddr_offset =
2807                 intel_compute_tile_offset(&x, &y, fb, 0,
2808                                           fb->pitches[0], rotation);
2809         linear_offset -= intel_crtc->dspaddr_offset;
2810         if (rotation == BIT(DRM_ROTATE_180)) {
2811                 dspcntr |= DISPPLANE_ROTATE_180;
2812
2813                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2814                         x += (crtc_state->pipe_src_w - 1);
2815                         y += (crtc_state->pipe_src_h - 1);
2816
2817                         /* Finding the last pixel of the last line of the display
2818                         data and adding to linear_offset*/
2819                         linear_offset +=
2820                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2821                                 (crtc_state->pipe_src_w - 1) * cpp;
2822                 }
2823         }
2824
2825         intel_crtc->adjusted_x = x;
2826         intel_crtc->adjusted_y = y;
2827
2828         I915_WRITE(reg, dspcntr);
2829
2830         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2831         I915_WRITE(DSPSURF(plane),
2832                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2833         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2834                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2835         } else {
2836                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2837                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2838         }
2839         POSTING_READ(reg);
2840 }
2841
2842 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2843                               uint64_t fb_modifier, uint32_t pixel_format)
2844 {
2845         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2846                 return 64;
2847         } else {
2848                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2849
2850                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2851         }
2852 }
2853
2854 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2855                            struct drm_i915_gem_object *obj,
2856                            unsigned int plane)
2857 {
2858         struct i915_ggtt_view view;
2859         struct i915_vma *vma;
2860         u64 offset;
2861
2862         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2863                                 intel_plane->base.state->rotation);
2864
2865         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2866         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2867                 view.type))
2868                 return -1;
2869
2870         offset = vma->node.start;
2871
2872         if (plane == 1) {
2873                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2874                           PAGE_SIZE;
2875         }
2876
2877         WARN_ON(upper_32_bits(offset));
2878
2879         return lower_32_bits(offset);
2880 }
2881
2882 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2883 {
2884         struct drm_device *dev = intel_crtc->base.dev;
2885         struct drm_i915_private *dev_priv = dev->dev_private;
2886
2887         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2888         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2889         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2890 }
2891
2892 /*
2893  * This function detaches (aka. unbinds) unused scalers in hardware
2894  */
2895 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2896 {
2897         struct intel_crtc_scaler_state *scaler_state;
2898         int i;
2899
2900         scaler_state = &intel_crtc->config->scaler_state;
2901
2902         /* loop through and disable scalers that aren't in use */
2903         for (i = 0; i < intel_crtc->num_scalers; i++) {
2904                 if (!scaler_state->scalers[i].in_use)
2905                         skl_detach_scaler(intel_crtc, i);
2906         }
2907 }
2908
2909 u32 skl_plane_ctl_format(uint32_t pixel_format)
2910 {
2911         switch (pixel_format) {
2912         case DRM_FORMAT_C8:
2913                 return PLANE_CTL_FORMAT_INDEXED;
2914         case DRM_FORMAT_RGB565:
2915                 return PLANE_CTL_FORMAT_RGB_565;
2916         case DRM_FORMAT_XBGR8888:
2917                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2918         case DRM_FORMAT_XRGB8888:
2919                 return PLANE_CTL_FORMAT_XRGB_8888;
2920         /*
2921          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2922          * to be already pre-multiplied. We need to add a knob (or a different
2923          * DRM_FORMAT) for user-space to configure that.
2924          */
2925         case DRM_FORMAT_ABGR8888:
2926                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2927                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2928         case DRM_FORMAT_ARGB8888:
2929                 return PLANE_CTL_FORMAT_XRGB_8888 |
2930                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2931         case DRM_FORMAT_XRGB2101010:
2932                 return PLANE_CTL_FORMAT_XRGB_2101010;
2933         case DRM_FORMAT_XBGR2101010:
2934                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2935         case DRM_FORMAT_YUYV:
2936                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2937         case DRM_FORMAT_YVYU:
2938                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2939         case DRM_FORMAT_UYVY:
2940                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2941         case DRM_FORMAT_VYUY:
2942                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2943         default:
2944                 MISSING_CASE(pixel_format);
2945         }
2946
2947         return 0;
2948 }
2949
2950 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2951 {
2952         switch (fb_modifier) {
2953         case DRM_FORMAT_MOD_NONE:
2954                 break;
2955         case I915_FORMAT_MOD_X_TILED:
2956                 return PLANE_CTL_TILED_X;
2957         case I915_FORMAT_MOD_Y_TILED:
2958                 return PLANE_CTL_TILED_Y;
2959         case I915_FORMAT_MOD_Yf_TILED:
2960                 return PLANE_CTL_TILED_YF;
2961         default:
2962                 MISSING_CASE(fb_modifier);
2963         }
2964
2965         return 0;
2966 }
2967
2968 u32 skl_plane_ctl_rotation(unsigned int rotation)
2969 {
2970         switch (rotation) {
2971         case BIT(DRM_ROTATE_0):
2972                 break;
2973         /*
2974          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2975          * while i915 HW rotation is clockwise, thats why this swapping.
2976          */
2977         case BIT(DRM_ROTATE_90):
2978                 return PLANE_CTL_ROTATE_270;
2979         case BIT(DRM_ROTATE_180):
2980                 return PLANE_CTL_ROTATE_180;
2981         case BIT(DRM_ROTATE_270):
2982                 return PLANE_CTL_ROTATE_90;
2983         default:
2984                 MISSING_CASE(rotation);
2985         }
2986
2987         return 0;
2988 }
2989
2990 static void skylake_update_primary_plane(struct drm_plane *plane,
2991                                          const struct intel_crtc_state *crtc_state,
2992                                          const struct intel_plane_state *plane_state)
2993 {
2994         struct drm_device *dev = plane->dev;
2995         struct drm_i915_private *dev_priv = dev->dev_private;
2996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2997         struct drm_framebuffer *fb = plane_state->base.fb;
2998         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2999         int pipe = intel_crtc->pipe;
3000         u32 plane_ctl, stride_div, stride;
3001         u32 tile_height, plane_offset, plane_size;
3002         unsigned int rotation = plane_state->base.rotation;
3003         int x_offset, y_offset;
3004         u32 surf_addr;
3005         int scaler_id = plane_state->scaler_id;
3006         int src_x = plane_state->src.x1 >> 16;
3007         int src_y = plane_state->src.y1 >> 16;
3008         int src_w = drm_rect_width(&plane_state->src) >> 16;
3009         int src_h = drm_rect_height(&plane_state->src) >> 16;
3010         int dst_x = plane_state->dst.x1;
3011         int dst_y = plane_state->dst.y1;
3012         int dst_w = drm_rect_width(&plane_state->dst);
3013         int dst_h = drm_rect_height(&plane_state->dst);
3014
3015         plane_ctl = PLANE_CTL_ENABLE |
3016                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3017                     PLANE_CTL_PIPE_CSC_ENABLE;
3018
3019         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3020         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3021         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3022         plane_ctl |= skl_plane_ctl_rotation(rotation);
3023
3024         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3025                                                fb->pixel_format);
3026         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3027
3028         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3029
3030         if (intel_rotation_90_or_270(rotation)) {
3031                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3032
3033                 /* stride = Surface height in tiles */
3034                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3035                 stride = DIV_ROUND_UP(fb->height, tile_height);
3036                 x_offset = stride * tile_height - src_y - src_h;
3037                 y_offset = src_x;
3038                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3039         } else {
3040                 stride = fb->pitches[0] / stride_div;
3041                 x_offset = src_x;
3042                 y_offset = src_y;
3043                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3044         }
3045         plane_offset = y_offset << 16 | x_offset;
3046
3047         intel_crtc->adjusted_x = x_offset;
3048         intel_crtc->adjusted_y = y_offset;
3049
3050         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3051         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3052         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3053         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3054
3055         if (scaler_id >= 0) {
3056                 uint32_t ps_ctrl = 0;
3057
3058                 WARN_ON(!dst_w || !dst_h);
3059                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3060                         crtc_state->scaler_state.scalers[scaler_id].mode;
3061                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3062                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3063                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3064                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3065                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3066         } else {
3067                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3068         }
3069
3070         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3071
3072         POSTING_READ(PLANE_SURF(pipe, 0));
3073 }
3074
3075 static void skylake_disable_primary_plane(struct drm_plane *primary,
3076                                           struct drm_crtc *crtc)
3077 {
3078         struct drm_device *dev = crtc->dev;
3079         struct drm_i915_private *dev_priv = dev->dev_private;
3080         int pipe = to_intel_crtc(crtc)->pipe;
3081
3082         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3083         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3084         POSTING_READ(PLANE_SURF(pipe, 0));
3085 }
3086
3087 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3088 static int
3089 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3090                            int x, int y, enum mode_set_atomic state)
3091 {
3092         /* Support for kgdboc is disabled, this needs a major rework. */
3093         DRM_ERROR("legacy panic handler not supported any more.\n");
3094
3095         return -ENODEV;
3096 }
3097
3098 static void intel_update_primary_planes(struct drm_device *dev)
3099 {
3100         struct drm_crtc *crtc;
3101
3102         for_each_crtc(dev, crtc) {
3103                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3104                 struct intel_plane_state *plane_state;
3105
3106                 drm_modeset_lock_crtc(crtc, &plane->base);
3107                 plane_state = to_intel_plane_state(plane->base.state);
3108
3109                 if (plane_state->visible)
3110                         plane->update_plane(&plane->base,
3111                                             to_intel_crtc_state(crtc->state),
3112                                             plane_state);
3113
3114                 drm_modeset_unlock_crtc(crtc);
3115         }
3116 }
3117
3118 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3119 {
3120         /* no reset support for gen2 */
3121         if (IS_GEN2(dev_priv))
3122                 return;
3123
3124         /* reset doesn't touch the display */
3125         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3126                 return;
3127
3128         drm_modeset_lock_all(dev_priv->dev);
3129         /*
3130          * Disabling the crtcs gracefully seems nicer. Also the
3131          * g33 docs say we should at least disable all the planes.
3132          */
3133         intel_display_suspend(dev_priv->dev);
3134 }
3135
3136 void intel_finish_reset(struct drm_i915_private *dev_priv)
3137 {
3138         /* no reset support for gen2 */
3139         if (IS_GEN2(dev_priv))
3140                 return;
3141
3142         /* reset doesn't touch the display */
3143         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3144                 /*
3145                  * Flips in the rings have been nuked by the reset,
3146                  * so update the base address of all primary
3147                  * planes to the the last fb to make sure we're
3148                  * showing the correct fb after a reset.
3149                  *
3150                  * FIXME: Atomic will make this obsolete since we won't schedule
3151                  * CS-based flips (which might get lost in gpu resets) any more.
3152                  */
3153                 intel_update_primary_planes(dev_priv->dev);
3154                 return;
3155         }
3156
3157         /*
3158          * The display has been reset as well,
3159          * so need a full re-initialization.
3160          */
3161         intel_runtime_pm_disable_interrupts(dev_priv);
3162         intel_runtime_pm_enable_interrupts(dev_priv);
3163
3164         intel_modeset_init_hw(dev_priv->dev);
3165
3166         spin_lock_irq(&dev_priv->irq_lock);
3167         if (dev_priv->display.hpd_irq_setup)
3168                 dev_priv->display.hpd_irq_setup(dev_priv);
3169         spin_unlock_irq(&dev_priv->irq_lock);
3170
3171         intel_display_resume(dev_priv->dev);
3172
3173         intel_hpd_init(dev_priv);
3174
3175         drm_modeset_unlock_all(dev_priv->dev);
3176 }
3177
3178 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3179 {
3180         return !list_empty_careful(&to_intel_crtc(crtc)->flip_work);
3181 }
3182
3183 static void intel_update_pipe_config(struct intel_crtc *crtc,
3184                                      struct intel_crtc_state *old_crtc_state)
3185 {
3186         struct drm_device *dev = crtc->base.dev;
3187         struct drm_i915_private *dev_priv = dev->dev_private;
3188         struct intel_crtc_state *pipe_config =
3189                 to_intel_crtc_state(crtc->base.state);
3190
3191         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3192         crtc->base.mode = crtc->base.state->mode;
3193
3194         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3195                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3196                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3197
3198         /*
3199          * Update pipe size and adjust fitter if needed: the reason for this is
3200          * that in compute_mode_changes we check the native mode (not the pfit
3201          * mode) to see if we can flip rather than do a full mode set. In the
3202          * fastboot case, we'll flip, but if we don't update the pipesrc and
3203          * pfit state, we'll end up with a big fb scanned out into the wrong
3204          * sized surface.
3205          */
3206
3207         I915_WRITE(PIPESRC(crtc->pipe),
3208                    ((pipe_config->pipe_src_w - 1) << 16) |
3209                    (pipe_config->pipe_src_h - 1));
3210
3211         /* on skylake this is done by detaching scalers */
3212         if (INTEL_INFO(dev)->gen >= 9) {
3213                 skl_detach_scalers(crtc);
3214
3215                 if (pipe_config->pch_pfit.enabled)
3216                         skylake_pfit_enable(crtc);
3217         } else if (HAS_PCH_SPLIT(dev)) {
3218                 if (pipe_config->pch_pfit.enabled)
3219                         ironlake_pfit_enable(crtc);
3220                 else if (old_crtc_state->pch_pfit.enabled)
3221                         ironlake_pfit_disable(crtc, true);
3222         }
3223 }
3224
3225 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3226 {
3227         struct drm_device *dev = crtc->dev;
3228         struct drm_i915_private *dev_priv = dev->dev_private;
3229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3230         int pipe = intel_crtc->pipe;
3231         i915_reg_t reg;
3232         u32 temp;
3233
3234         /* enable normal train */
3235         reg = FDI_TX_CTL(pipe);
3236         temp = I915_READ(reg);
3237         if (IS_IVYBRIDGE(dev)) {
3238                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3239                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3240         } else {
3241                 temp &= ~FDI_LINK_TRAIN_NONE;
3242                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3243         }
3244         I915_WRITE(reg, temp);
3245
3246         reg = FDI_RX_CTL(pipe);
3247         temp = I915_READ(reg);
3248         if (HAS_PCH_CPT(dev)) {
3249                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3250                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3251         } else {
3252                 temp &= ~FDI_LINK_TRAIN_NONE;
3253                 temp |= FDI_LINK_TRAIN_NONE;
3254         }
3255         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3256
3257         /* wait one idle pattern time */
3258         POSTING_READ(reg);
3259         udelay(1000);
3260
3261         /* IVB wants error correction enabled */
3262         if (IS_IVYBRIDGE(dev))
3263                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3264                            FDI_FE_ERRC_ENABLE);
3265 }
3266
3267 /* The FDI link training functions for ILK/Ibexpeak. */
3268 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3269 {
3270         struct drm_device *dev = crtc->dev;
3271         struct drm_i915_private *dev_priv = dev->dev_private;
3272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3273         int pipe = intel_crtc->pipe;
3274         i915_reg_t reg;
3275         u32 temp, tries;
3276
3277         /* FDI needs bits from pipe first */
3278         assert_pipe_enabled(dev_priv, pipe);
3279
3280         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3281            for train result */
3282         reg = FDI_RX_IMR(pipe);
3283         temp = I915_READ(reg);
3284         temp &= ~FDI_RX_SYMBOL_LOCK;
3285         temp &= ~FDI_RX_BIT_LOCK;
3286         I915_WRITE(reg, temp);
3287         I915_READ(reg);
3288         udelay(150);
3289
3290         /* enable CPU FDI TX and PCH FDI RX */
3291         reg = FDI_TX_CTL(pipe);
3292         temp = I915_READ(reg);
3293         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3294         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3295         temp &= ~FDI_LINK_TRAIN_NONE;
3296         temp |= FDI_LINK_TRAIN_PATTERN_1;
3297         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3298
3299         reg = FDI_RX_CTL(pipe);
3300         temp = I915_READ(reg);
3301         temp &= ~FDI_LINK_TRAIN_NONE;
3302         temp |= FDI_LINK_TRAIN_PATTERN_1;
3303         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3304
3305         POSTING_READ(reg);
3306         udelay(150);
3307
3308         /* Ironlake workaround, enable clock pointer after FDI enable*/
3309         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3310         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3311                    FDI_RX_PHASE_SYNC_POINTER_EN);
3312
3313         reg = FDI_RX_IIR(pipe);
3314         for (tries = 0; tries < 5; tries++) {
3315                 temp = I915_READ(reg);
3316                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3317
3318                 if ((temp & FDI_RX_BIT_LOCK)) {
3319                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3320                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3321                         break;
3322                 }
3323         }
3324         if (tries == 5)
3325                 DRM_ERROR("FDI train 1 fail!\n");
3326
3327         /* Train 2 */
3328         reg = FDI_TX_CTL(pipe);
3329         temp = I915_READ(reg);
3330         temp &= ~FDI_LINK_TRAIN_NONE;
3331         temp |= FDI_LINK_TRAIN_PATTERN_2;
3332         I915_WRITE(reg, temp);
3333
3334         reg = FDI_RX_CTL(pipe);
3335         temp = I915_READ(reg);
3336         temp &= ~FDI_LINK_TRAIN_NONE;
3337         temp |= FDI_LINK_TRAIN_PATTERN_2;
3338         I915_WRITE(reg, temp);
3339
3340         POSTING_READ(reg);
3341         udelay(150);
3342
3343         reg = FDI_RX_IIR(pipe);
3344         for (tries = 0; tries < 5; tries++) {
3345                 temp = I915_READ(reg);
3346                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3347
3348                 if (temp & FDI_RX_SYMBOL_LOCK) {
3349                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3350                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3351                         break;
3352                 }
3353         }
3354         if (tries == 5)
3355                 DRM_ERROR("FDI train 2 fail!\n");
3356
3357         DRM_DEBUG_KMS("FDI train done\n");
3358
3359 }
3360
3361 static const int snb_b_fdi_train_param[] = {
3362         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3363         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3364         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3365         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3366 };
3367
3368 /* The FDI link training functions for SNB/Cougarpoint. */
3369 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3370 {
3371         struct drm_device *dev = crtc->dev;
3372         struct drm_i915_private *dev_priv = dev->dev_private;
3373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3374         int pipe = intel_crtc->pipe;
3375         i915_reg_t reg;
3376         u32 temp, i, retry;
3377
3378         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3379            for train result */
3380         reg = FDI_RX_IMR(pipe);
3381         temp = I915_READ(reg);
3382         temp &= ~FDI_RX_SYMBOL_LOCK;
3383         temp &= ~FDI_RX_BIT_LOCK;
3384         I915_WRITE(reg, temp);
3385
3386         POSTING_READ(reg);
3387         udelay(150);
3388
3389         /* enable CPU FDI TX and PCH FDI RX */
3390         reg = FDI_TX_CTL(pipe);
3391         temp = I915_READ(reg);
3392         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3393         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3394         temp &= ~FDI_LINK_TRAIN_NONE;
3395         temp |= FDI_LINK_TRAIN_PATTERN_1;
3396         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3397         /* SNB-B */
3398         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3399         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3400
3401         I915_WRITE(FDI_RX_MISC(pipe),
3402                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3403
3404         reg = FDI_RX_CTL(pipe);
3405         temp = I915_READ(reg);
3406         if (HAS_PCH_CPT(dev)) {
3407                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3408                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3409         } else {
3410                 temp &= ~FDI_LINK_TRAIN_NONE;
3411                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3412         }
3413         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3414
3415         POSTING_READ(reg);
3416         udelay(150);
3417
3418         for (i = 0; i < 4; i++) {
3419                 reg = FDI_TX_CTL(pipe);
3420                 temp = I915_READ(reg);
3421                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3422                 temp |= snb_b_fdi_train_param[i];
3423                 I915_WRITE(reg, temp);
3424
3425                 POSTING_READ(reg);
3426                 udelay(500);
3427
3428                 for (retry = 0; retry < 5; retry++) {
3429                         reg = FDI_RX_IIR(pipe);
3430                         temp = I915_READ(reg);
3431                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3432                         if (temp & FDI_RX_BIT_LOCK) {
3433                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3434                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3435                                 break;
3436                         }
3437                         udelay(50);
3438                 }
3439                 if (retry < 5)
3440                         break;
3441         }
3442         if (i == 4)
3443                 DRM_ERROR("FDI train 1 fail!\n");
3444
3445         /* Train 2 */
3446         reg = FDI_TX_CTL(pipe);
3447         temp = I915_READ(reg);
3448         temp &= ~FDI_LINK_TRAIN_NONE;
3449         temp |= FDI_LINK_TRAIN_PATTERN_2;
3450         if (IS_GEN6(dev)) {
3451                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3452                 /* SNB-B */
3453                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3454         }
3455         I915_WRITE(reg, temp);
3456
3457         reg = FDI_RX_CTL(pipe);
3458         temp = I915_READ(reg);
3459         if (HAS_PCH_CPT(dev)) {
3460                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3461                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3462         } else {
3463                 temp &= ~FDI_LINK_TRAIN_NONE;
3464                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3465         }
3466         I915_WRITE(reg, temp);
3467
3468         POSTING_READ(reg);
3469         udelay(150);
3470
3471         for (i = 0; i < 4; i++) {
3472                 reg = FDI_TX_CTL(pipe);
3473                 temp = I915_READ(reg);
3474                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3475                 temp |= snb_b_fdi_train_param[i];
3476                 I915_WRITE(reg, temp);
3477
3478                 POSTING_READ(reg);
3479                 udelay(500);
3480
3481                 for (retry = 0; retry < 5; retry++) {
3482                         reg = FDI_RX_IIR(pipe);
3483                         temp = I915_READ(reg);
3484                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3485                         if (temp & FDI_RX_SYMBOL_LOCK) {
3486                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3487                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3488                                 break;
3489                         }
3490                         udelay(50);
3491                 }
3492                 if (retry < 5)
3493                         break;
3494         }
3495         if (i == 4)
3496                 DRM_ERROR("FDI train 2 fail!\n");
3497
3498         DRM_DEBUG_KMS("FDI train done.\n");
3499 }
3500
3501 /* Manual link training for Ivy Bridge A0 parts */
3502 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3503 {
3504         struct drm_device *dev = crtc->dev;
3505         struct drm_i915_private *dev_priv = dev->dev_private;
3506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507         int pipe = intel_crtc->pipe;
3508         i915_reg_t reg;
3509         u32 temp, i, j;
3510
3511         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3512            for train result */
3513         reg = FDI_RX_IMR(pipe);
3514         temp = I915_READ(reg);
3515         temp &= ~FDI_RX_SYMBOL_LOCK;
3516         temp &= ~FDI_RX_BIT_LOCK;
3517         I915_WRITE(reg, temp);
3518
3519         POSTING_READ(reg);
3520         udelay(150);
3521
3522         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3523                       I915_READ(FDI_RX_IIR(pipe)));
3524
3525         /* Try each vswing and preemphasis setting twice before moving on */
3526         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3527                 /* disable first in case we need to retry */
3528                 reg = FDI_TX_CTL(pipe);
3529                 temp = I915_READ(reg);
3530                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3531                 temp &= ~FDI_TX_ENABLE;
3532                 I915_WRITE(reg, temp);
3533
3534                 reg = FDI_RX_CTL(pipe);
3535                 temp = I915_READ(reg);
3536                 temp &= ~FDI_LINK_TRAIN_AUTO;
3537                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3538                 temp &= ~FDI_RX_ENABLE;
3539                 I915_WRITE(reg, temp);
3540
3541                 /* enable CPU FDI TX and PCH FDI RX */
3542                 reg = FDI_TX_CTL(pipe);
3543                 temp = I915_READ(reg);
3544                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3545                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3546                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3547                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3548                 temp |= snb_b_fdi_train_param[j/2];
3549                 temp |= FDI_COMPOSITE_SYNC;
3550                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3551
3552                 I915_WRITE(FDI_RX_MISC(pipe),
3553                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3554
3555                 reg = FDI_RX_CTL(pipe);
3556                 temp = I915_READ(reg);
3557                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3558                 temp |= FDI_COMPOSITE_SYNC;
3559                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3560
3561                 POSTING_READ(reg);
3562                 udelay(1); /* should be 0.5us */
3563
3564                 for (i = 0; i < 4; i++) {
3565                         reg = FDI_RX_IIR(pipe);
3566                         temp = I915_READ(reg);
3567                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3568
3569                         if (temp & FDI_RX_BIT_LOCK ||
3570                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3571                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3572                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3573                                               i);
3574                                 break;
3575                         }
3576                         udelay(1); /* should be 0.5us */
3577                 }
3578                 if (i == 4) {
3579                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3580                         continue;
3581                 }
3582
3583                 /* Train 2 */
3584                 reg = FDI_TX_CTL(pipe);
3585                 temp = I915_READ(reg);
3586                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3587                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3588                 I915_WRITE(reg, temp);
3589
3590                 reg = FDI_RX_CTL(pipe);
3591                 temp = I915_READ(reg);
3592                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3593                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3594                 I915_WRITE(reg, temp);
3595
3596                 POSTING_READ(reg);
3597                 udelay(2); /* should be 1.5us */
3598
3599                 for (i = 0; i < 4; i++) {
3600                         reg = FDI_RX_IIR(pipe);
3601                         temp = I915_READ(reg);
3602                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3603
3604                         if (temp & FDI_RX_SYMBOL_LOCK ||
3605                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3606                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3607                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3608                                               i);
3609                                 goto train_done;
3610                         }
3611                         udelay(2); /* should be 1.5us */
3612                 }
3613                 if (i == 4)
3614                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3615         }
3616
3617 train_done:
3618         DRM_DEBUG_KMS("FDI train done.\n");
3619 }
3620
3621 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3622 {
3623         struct drm_device *dev = intel_crtc->base.dev;
3624         struct drm_i915_private *dev_priv = dev->dev_private;
3625         int pipe = intel_crtc->pipe;
3626         i915_reg_t reg;
3627         u32 temp;
3628
3629         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3630         reg = FDI_RX_CTL(pipe);
3631         temp = I915_READ(reg);
3632         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3633         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3634         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3635         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3636
3637         POSTING_READ(reg);
3638         udelay(200);
3639
3640         /* Switch from Rawclk to PCDclk */
3641         temp = I915_READ(reg);
3642         I915_WRITE(reg, temp | FDI_PCDCLK);
3643
3644         POSTING_READ(reg);
3645         udelay(200);
3646
3647         /* Enable CPU FDI TX PLL, always on for Ironlake */
3648         reg = FDI_TX_CTL(pipe);
3649         temp = I915_READ(reg);
3650         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3651                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3652
3653                 POSTING_READ(reg);
3654                 udelay(100);
3655         }
3656 }
3657
3658 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3659 {
3660         struct drm_device *dev = intel_crtc->base.dev;
3661         struct drm_i915_private *dev_priv = dev->dev_private;
3662         int pipe = intel_crtc->pipe;
3663         i915_reg_t reg;
3664         u32 temp;
3665
3666         /* Switch from PCDclk to Rawclk */
3667         reg = FDI_RX_CTL(pipe);
3668         temp = I915_READ(reg);
3669         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3670
3671         /* Disable CPU FDI TX PLL */
3672         reg = FDI_TX_CTL(pipe);
3673         temp = I915_READ(reg);
3674         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3675
3676         POSTING_READ(reg);
3677         udelay(100);
3678
3679         reg = FDI_RX_CTL(pipe);
3680         temp = I915_READ(reg);
3681         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3682
3683         /* Wait for the clocks to turn off. */
3684         POSTING_READ(reg);
3685         udelay(100);
3686 }
3687
3688 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3689 {
3690         struct drm_device *dev = crtc->dev;
3691         struct drm_i915_private *dev_priv = dev->dev_private;
3692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3693         int pipe = intel_crtc->pipe;
3694         i915_reg_t reg;
3695         u32 temp;
3696
3697         /* disable CPU FDI tx and PCH FDI rx */
3698         reg = FDI_TX_CTL(pipe);
3699         temp = I915_READ(reg);
3700         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3701         POSTING_READ(reg);
3702
3703         reg = FDI_RX_CTL(pipe);
3704         temp = I915_READ(reg);
3705         temp &= ~(0x7 << 16);
3706         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3707         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3708
3709         POSTING_READ(reg);
3710         udelay(100);
3711
3712         /* Ironlake workaround, disable clock pointer after downing FDI */
3713         if (HAS_PCH_IBX(dev))
3714                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3715
3716         /* still set train pattern 1 */
3717         reg = FDI_TX_CTL(pipe);
3718         temp = I915_READ(reg);
3719         temp &= ~FDI_LINK_TRAIN_NONE;
3720         temp |= FDI_LINK_TRAIN_PATTERN_1;
3721         I915_WRITE(reg, temp);
3722
3723         reg = FDI_RX_CTL(pipe);
3724         temp = I915_READ(reg);
3725         if (HAS_PCH_CPT(dev)) {
3726                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3727                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3728         } else {
3729                 temp &= ~FDI_LINK_TRAIN_NONE;
3730                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3731         }
3732         /* BPC in FDI rx is consistent with that in PIPECONF */
3733         temp &= ~(0x07 << 16);
3734         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3735         I915_WRITE(reg, temp);
3736
3737         POSTING_READ(reg);
3738         udelay(100);
3739 }
3740
3741 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3742 {
3743         struct intel_crtc *crtc;
3744
3745         /* Note that we don't need to be called with mode_config.lock here
3746          * as our list of CRTC objects is static for the lifetime of the
3747          * device and so cannot disappear as we iterate. Similarly, we can
3748          * happily treat the predicates as racy, atomic checks as userspace
3749          * cannot claim and pin a new fb without at least acquring the
3750          * struct_mutex and so serialising with us.
3751          */
3752         for_each_intel_crtc(dev, crtc) {
3753                 if (atomic_read(&crtc->unpin_work_count) == 0)
3754                         continue;
3755
3756                 if (!list_empty_careful(&crtc->flip_work))
3757                         intel_wait_for_vblank(dev, crtc->pipe);
3758
3759                 return true;
3760         }
3761
3762         return false;
3763 }
3764
3765 static void page_flip_completed(struct intel_crtc *intel_crtc, struct intel_flip_work *work)
3766 {
3767         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3768         struct drm_plane_state *new_plane_state;
3769         struct drm_plane *primary = intel_crtc->base.primary;
3770
3771         if (work->event)
3772                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3773
3774         drm_crtc_vblank_put(&intel_crtc->base);
3775
3776         new_plane_state = &work->old_plane_state[0]->base;
3777         if (work->num_planes >= 1 &&
3778             new_plane_state->plane == primary &&
3779             new_plane_state->fb)
3780                 trace_i915_flip_complete(intel_crtc->plane,
3781                                          intel_fb_obj(new_plane_state->fb));
3782
3783         if (work->can_async_unpin) {
3784                 list_del_init(&work->head);
3785                 wake_up_all(&dev_priv->pending_flip_queue);
3786         }
3787
3788         queue_work(dev_priv->wq, &work->unpin_work);
3789 }
3790
3791 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3792 {
3793         struct drm_device *dev = crtc->dev;
3794         struct drm_i915_private *dev_priv = dev->dev_private;
3795         long ret;
3796
3797         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3798
3799         ret = wait_event_interruptible_timeout(
3800                                         dev_priv->pending_flip_queue,
3801                                         !intel_crtc_has_pending_flip(crtc),
3802                                         60*HZ);
3803
3804         if (ret < 0)
3805                 return ret;
3806
3807         WARN(ret == 0, "Stuck page flip\n");
3808
3809         return 0;
3810 }
3811
3812 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3813 {
3814         u32 temp;
3815
3816         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3817
3818         mutex_lock(&dev_priv->sb_lock);
3819
3820         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3821         temp |= SBI_SSCCTL_DISABLE;
3822         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3823
3824         mutex_unlock(&dev_priv->sb_lock);
3825 }
3826
3827 /* Program iCLKIP clock to the desired frequency */
3828 static void lpt_program_iclkip(struct drm_crtc *crtc)
3829 {
3830         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3831         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3832         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3833         u32 temp;
3834
3835         lpt_disable_iclkip(dev_priv);
3836
3837         /* The iCLK virtual clock root frequency is in MHz,
3838          * but the adjusted_mode->crtc_clock in in KHz. To get the
3839          * divisors, it is necessary to divide one by another, so we
3840          * convert the virtual clock precision to KHz here for higher
3841          * precision.
3842          */
3843         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3844                 u32 iclk_virtual_root_freq = 172800 * 1000;
3845                 u32 iclk_pi_range = 64;
3846                 u32 desired_divisor;
3847
3848                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3849                                                     clock << auxdiv);
3850                 divsel = (desired_divisor / iclk_pi_range) - 2;
3851                 phaseinc = desired_divisor % iclk_pi_range;
3852
3853                 /*
3854                  * Near 20MHz is a corner case which is
3855                  * out of range for the 7-bit divisor
3856                  */
3857                 if (divsel <= 0x7f)
3858                         break;
3859         }
3860
3861         /* This should not happen with any sane values */
3862         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3863                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3864         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3865                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3866
3867         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3868                         clock,
3869                         auxdiv,
3870                         divsel,
3871                         phasedir,
3872                         phaseinc);
3873
3874         mutex_lock(&dev_priv->sb_lock);
3875
3876         /* Program SSCDIVINTPHASE6 */
3877         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3878         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3879         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3880         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3881         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3882         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3883         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3884         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3885
3886         /* Program SSCAUXDIV */
3887         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3888         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3889         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3890         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3891
3892         /* Enable modulator and associated divider */
3893         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3894         temp &= ~SBI_SSCCTL_DISABLE;
3895         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3896
3897         mutex_unlock(&dev_priv->sb_lock);
3898
3899         /* Wait for initialization time */
3900         udelay(24);
3901
3902         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3903 }
3904
3905 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3906 {
3907         u32 divsel, phaseinc, auxdiv;
3908         u32 iclk_virtual_root_freq = 172800 * 1000;
3909         u32 iclk_pi_range = 64;
3910         u32 desired_divisor;
3911         u32 temp;
3912
3913         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3914                 return 0;
3915
3916         mutex_lock(&dev_priv->sb_lock);
3917
3918         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3919         if (temp & SBI_SSCCTL_DISABLE) {
3920                 mutex_unlock(&dev_priv->sb_lock);
3921                 return 0;
3922         }
3923
3924         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3925         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3926                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3927         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3928                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3929
3930         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3931         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3932                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3933
3934         mutex_unlock(&dev_priv->sb_lock);
3935
3936         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3937
3938         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3939                                  desired_divisor << auxdiv);
3940 }
3941
3942 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3943                                                 enum pipe pch_transcoder)
3944 {
3945         struct drm_device *dev = crtc->base.dev;
3946         struct drm_i915_private *dev_priv = dev->dev_private;
3947         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3948
3949         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3950                    I915_READ(HTOTAL(cpu_transcoder)));
3951         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3952                    I915_READ(HBLANK(cpu_transcoder)));
3953         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3954                    I915_READ(HSYNC(cpu_transcoder)));
3955
3956         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3957                    I915_READ(VTOTAL(cpu_transcoder)));
3958         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3959                    I915_READ(VBLANK(cpu_transcoder)));
3960         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3961                    I915_READ(VSYNC(cpu_transcoder)));
3962         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3963                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3964 }
3965
3966 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3967 {
3968         struct drm_i915_private *dev_priv = dev->dev_private;
3969         uint32_t temp;
3970
3971         temp = I915_READ(SOUTH_CHICKEN1);
3972         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3973                 return;
3974
3975         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3976         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3977
3978         temp &= ~FDI_BC_BIFURCATION_SELECT;
3979         if (enable)
3980                 temp |= FDI_BC_BIFURCATION_SELECT;
3981
3982         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3983         I915_WRITE(SOUTH_CHICKEN1, temp);
3984         POSTING_READ(SOUTH_CHICKEN1);
3985 }
3986
3987 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3988 {
3989         struct drm_device *dev = intel_crtc->base.dev;
3990
3991         switch (intel_crtc->pipe) {
3992         case PIPE_A:
3993                 break;
3994         case PIPE_B:
3995                 if (intel_crtc->config->fdi_lanes > 2)
3996                         cpt_set_fdi_bc_bifurcation(dev, false);
3997                 else
3998                         cpt_set_fdi_bc_bifurcation(dev, true);
3999
4000                 break;
4001         case PIPE_C:
4002                 cpt_set_fdi_bc_bifurcation(dev, true);
4003
4004                 break;
4005         default:
4006                 BUG();
4007         }
4008 }
4009
4010 /* Return which DP Port should be selected for Transcoder DP control */
4011 static enum port
4012 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4013 {
4014         struct drm_device *dev = crtc->dev;
4015         struct intel_encoder *encoder;
4016
4017         for_each_encoder_on_crtc(dev, crtc, encoder) {
4018                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4019                     encoder->type == INTEL_OUTPUT_EDP)
4020                         return enc_to_dig_port(&encoder->base)->port;
4021         }
4022
4023         return -1;
4024 }
4025
4026 /*
4027  * Enable PCH resources required for PCH ports:
4028  *   - PCH PLLs
4029  *   - FDI training & RX/TX
4030  *   - update transcoder timings
4031  *   - DP transcoding bits
4032  *   - transcoder
4033  */
4034 static void ironlake_pch_enable(struct drm_crtc *crtc)
4035 {
4036         struct drm_device *dev = crtc->dev;
4037         struct drm_i915_private *dev_priv = dev->dev_private;
4038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4039         int pipe = intel_crtc->pipe;
4040         u32 temp;
4041
4042         assert_pch_transcoder_disabled(dev_priv, pipe);
4043
4044         if (IS_IVYBRIDGE(dev))
4045                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4046
4047         /* Write the TU size bits before fdi link training, so that error
4048          * detection works. */
4049         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4050                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4051
4052         /* For PCH output, training FDI link */
4053         dev_priv->display.fdi_link_train(crtc);
4054
4055         /* We need to program the right clock selection before writing the pixel
4056          * mutliplier into the DPLL. */
4057         if (HAS_PCH_CPT(dev)) {
4058                 u32 sel;
4059
4060                 temp = I915_READ(PCH_DPLL_SEL);
4061                 temp |= TRANS_DPLL_ENABLE(pipe);
4062                 sel = TRANS_DPLLB_SEL(pipe);
4063                 if (intel_crtc->config->shared_dpll ==
4064                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4065                         temp |= sel;
4066                 else
4067                         temp &= ~sel;
4068                 I915_WRITE(PCH_DPLL_SEL, temp);
4069         }
4070
4071         /* XXX: pch pll's can be enabled any time before we enable the PCH
4072          * transcoder, and we actually should do this to not upset any PCH
4073          * transcoder that already use the clock when we share it.
4074          *
4075          * Note that enable_shared_dpll tries to do the right thing, but
4076          * get_shared_dpll unconditionally resets the pll - we need that to have
4077          * the right LVDS enable sequence. */
4078         intel_enable_shared_dpll(intel_crtc);
4079
4080         /* set transcoder timing, panel must allow it */
4081         assert_panel_unlocked(dev_priv, pipe);
4082         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4083
4084         intel_fdi_normal_train(crtc);
4085
4086         /* For PCH DP, enable TRANS_DP_CTL */
4087         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4088                 const struct drm_display_mode *adjusted_mode =
4089                         &intel_crtc->config->base.adjusted_mode;
4090                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4091                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4092                 temp = I915_READ(reg);
4093                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4094                           TRANS_DP_SYNC_MASK |
4095                           TRANS_DP_BPC_MASK);
4096                 temp |= TRANS_DP_OUTPUT_ENABLE;
4097                 temp |= bpc << 9; /* same format but at 11:9 */
4098
4099                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4100                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4101                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4102                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4103
4104                 switch (intel_trans_dp_port_sel(crtc)) {
4105                 case PORT_B:
4106                         temp |= TRANS_DP_PORT_SEL_B;
4107                         break;
4108                 case PORT_C:
4109                         temp |= TRANS_DP_PORT_SEL_C;
4110                         break;
4111                 case PORT_D:
4112                         temp |= TRANS_DP_PORT_SEL_D;
4113                         break;
4114                 default:
4115                         BUG();
4116                 }
4117
4118                 I915_WRITE(reg, temp);
4119         }
4120
4121         ironlake_enable_pch_transcoder(dev_priv, pipe);
4122 }
4123
4124 static void lpt_pch_enable(struct drm_crtc *crtc)
4125 {
4126         struct drm_device *dev = crtc->dev;
4127         struct drm_i915_private *dev_priv = dev->dev_private;
4128         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4129         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4130
4131         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4132
4133         lpt_program_iclkip(crtc);
4134
4135         /* Set transcoder timing. */
4136         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4137
4138         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4139 }
4140
4141 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4142 {
4143         struct drm_i915_private *dev_priv = dev->dev_private;
4144         i915_reg_t dslreg = PIPEDSL(pipe);
4145         u32 temp;
4146
4147         temp = I915_READ(dslreg);
4148         udelay(500);
4149         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4150                 if (wait_for(I915_READ(dslreg) != temp, 5))
4151                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4152         }
4153 }
4154
4155 static int
4156 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4157                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4158                   int src_w, int src_h, int dst_w, int dst_h)
4159 {
4160         struct intel_crtc_scaler_state *scaler_state =
4161                 &crtc_state->scaler_state;
4162         struct intel_crtc *intel_crtc =
4163                 to_intel_crtc(crtc_state->base.crtc);
4164         int need_scaling;
4165
4166         need_scaling = intel_rotation_90_or_270(rotation) ?
4167                 (src_h != dst_w || src_w != dst_h):
4168                 (src_w != dst_w || src_h != dst_h);
4169
4170         /*
4171          * if plane is being disabled or scaler is no more required or force detach
4172          *  - free scaler binded to this plane/crtc
4173          *  - in order to do this, update crtc->scaler_usage
4174          *
4175          * Here scaler state in crtc_state is set free so that
4176          * scaler can be assigned to other user. Actual register
4177          * update to free the scaler is done in plane/panel-fit programming.
4178          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4179          */
4180         if (force_detach || !need_scaling) {
4181                 if (*scaler_id >= 0) {
4182                         scaler_state->scaler_users &= ~(1 << scaler_user);
4183                         scaler_state->scalers[*scaler_id].in_use = 0;
4184
4185                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4186                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4187                                 intel_crtc->pipe, scaler_user, *scaler_id,
4188                                 scaler_state->scaler_users);
4189                         *scaler_id = -1;
4190                 }
4191                 return 0;
4192         }
4193
4194         /* range checks */
4195         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4196                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4197
4198                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4199                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4200                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4201                         "size is out of scaler range\n",
4202                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4203                 return -EINVAL;
4204         }
4205
4206         /* mark this plane as a scaler user in crtc_state */
4207         scaler_state->scaler_users |= (1 << scaler_user);
4208         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4209                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4210                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4211                 scaler_state->scaler_users);
4212
4213         return 0;
4214 }
4215
4216 /**
4217  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4218  *
4219  * @state: crtc's scaler state
4220  *
4221  * Return
4222  *     0 - scaler_usage updated successfully
4223  *    error - requested scaling cannot be supported or other error condition
4224  */
4225 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4226 {
4227         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4228         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4229
4230         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4231                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4232
4233         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4234                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4235                 state->pipe_src_w, state->pipe_src_h,
4236                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4237 }
4238
4239 /**
4240  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4241  *
4242  * @state: crtc's scaler state
4243  * @plane_state: atomic plane state to update
4244  *
4245  * Return
4246  *     0 - scaler_usage updated successfully
4247  *    error - requested scaling cannot be supported or other error condition
4248  */
4249 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4250                                    struct intel_plane_state *plane_state)
4251 {
4252
4253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4254         struct intel_plane *intel_plane =
4255                 to_intel_plane(plane_state->base.plane);
4256         struct drm_framebuffer *fb = plane_state->base.fb;
4257         int ret;
4258
4259         bool force_detach = !fb || !plane_state->visible;
4260
4261         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4262                       intel_plane->base.base.id, intel_crtc->pipe,
4263                       drm_plane_index(&intel_plane->base));
4264
4265         ret = skl_update_scaler(crtc_state, force_detach,
4266                                 drm_plane_index(&intel_plane->base),
4267                                 &plane_state->scaler_id,
4268                                 plane_state->base.rotation,
4269                                 drm_rect_width(&plane_state->src) >> 16,
4270                                 drm_rect_height(&plane_state->src) >> 16,
4271                                 drm_rect_width(&plane_state->dst),
4272                                 drm_rect_height(&plane_state->dst));
4273
4274         if (ret || plane_state->scaler_id < 0)
4275                 return ret;
4276
4277         /* check colorkey */
4278         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4279                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4280                               intel_plane->base.base.id);
4281                 return -EINVAL;
4282         }
4283
4284         /* Check src format */
4285         switch (fb->pixel_format) {
4286         case DRM_FORMAT_RGB565:
4287         case DRM_FORMAT_XBGR8888:
4288         case DRM_FORMAT_XRGB8888:
4289         case DRM_FORMAT_ABGR8888:
4290         case DRM_FORMAT_ARGB8888:
4291         case DRM_FORMAT_XRGB2101010:
4292         case DRM_FORMAT_XBGR2101010:
4293         case DRM_FORMAT_YUYV:
4294         case DRM_FORMAT_YVYU:
4295         case DRM_FORMAT_UYVY:
4296         case DRM_FORMAT_VYUY:
4297                 break;
4298         default:
4299                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4300                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4301                 return -EINVAL;
4302         }
4303
4304         return 0;
4305 }
4306
4307 static void skylake_scaler_disable(struct intel_crtc *crtc)
4308 {
4309         int i;
4310
4311         for (i = 0; i < crtc->num_scalers; i++)
4312                 skl_detach_scaler(crtc, i);
4313 }
4314
4315 static void skylake_pfit_enable(struct intel_crtc *crtc)
4316 {
4317         struct drm_device *dev = crtc->base.dev;
4318         struct drm_i915_private *dev_priv = dev->dev_private;
4319         int pipe = crtc->pipe;
4320         struct intel_crtc_scaler_state *scaler_state =
4321                 &crtc->config->scaler_state;
4322
4323         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4324
4325         if (crtc->config->pch_pfit.enabled) {
4326                 int id;
4327
4328                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4329                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4330                         return;
4331                 }
4332
4333                 id = scaler_state->scaler_id;
4334                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4335                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4336                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4337                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4338
4339                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4340         }
4341 }
4342
4343 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4344 {
4345         struct drm_device *dev = crtc->base.dev;
4346         struct drm_i915_private *dev_priv = dev->dev_private;
4347         int pipe = crtc->pipe;
4348
4349         if (crtc->config->pch_pfit.enabled) {
4350                 /* Force use of hard-coded filter coefficients
4351                  * as some pre-programmed values are broken,
4352                  * e.g. x201.
4353                  */
4354                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4355                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4356                                                  PF_PIPE_SEL_IVB(pipe));
4357                 else
4358                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4359                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4360                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4361         }
4362 }
4363
4364 void hsw_enable_ips(struct intel_crtc *crtc)
4365 {
4366         struct drm_device *dev = crtc->base.dev;
4367         struct drm_i915_private *dev_priv = dev->dev_private;
4368
4369         if (!crtc->config->ips_enabled)
4370                 return;
4371
4372         /*
4373          * We can only enable IPS after we enable a plane and wait for a vblank
4374          * This function is called from post_plane_update, which is run after
4375          * a vblank wait.
4376          */
4377
4378         assert_plane_enabled(dev_priv, crtc->plane);
4379         if (IS_BROADWELL(dev)) {
4380                 mutex_lock(&dev_priv->rps.hw_lock);
4381                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4382                 mutex_unlock(&dev_priv->rps.hw_lock);
4383                 /* Quoting Art Runyan: "its not safe to expect any particular
4384                  * value in IPS_CTL bit 31 after enabling IPS through the
4385                  * mailbox." Moreover, the mailbox may return a bogus state,
4386                  * so we need to just enable it and continue on.
4387                  */
4388         } else {
4389                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4390                 /* The bit only becomes 1 in the next vblank, so this wait here
4391                  * is essentially intel_wait_for_vblank. If we don't have this
4392                  * and don't wait for vblanks until the end of crtc_enable, then
4393                  * the HW state readout code will complain that the expected
4394                  * IPS_CTL value is not the one we read. */
4395                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4396                         DRM_ERROR("Timed out waiting for IPS enable\n");
4397         }
4398 }
4399
4400 void hsw_disable_ips(struct intel_crtc *crtc)
4401 {
4402         struct drm_device *dev = crtc->base.dev;
4403         struct drm_i915_private *dev_priv = dev->dev_private;
4404
4405         if (!crtc->config->ips_enabled)
4406                 return;
4407
4408         assert_plane_enabled(dev_priv, crtc->plane);
4409         if (IS_BROADWELL(dev)) {
4410                 mutex_lock(&dev_priv->rps.hw_lock);
4411                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4412                 mutex_unlock(&dev_priv->rps.hw_lock);
4413                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4414                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4415                         DRM_ERROR("Timed out waiting for IPS disable\n");
4416         } else {
4417                 I915_WRITE(IPS_CTL, 0);
4418                 POSTING_READ(IPS_CTL);
4419         }
4420
4421         /* We need to wait for a vblank before we can disable the plane. */
4422         intel_wait_for_vblank(dev, crtc->pipe);
4423 }
4424
4425 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4426 {
4427         if (intel_crtc->overlay) {
4428                 struct drm_device *dev = intel_crtc->base.dev;
4429                 struct drm_i915_private *dev_priv = dev->dev_private;
4430
4431                 mutex_lock(&dev->struct_mutex);
4432                 dev_priv->mm.interruptible = false;
4433                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4434                 dev_priv->mm.interruptible = true;
4435                 mutex_unlock(&dev->struct_mutex);
4436         }
4437
4438         /* Let userspace switch the overlay on again. In most cases userspace
4439          * has to recompute where to put it anyway.
4440          */
4441 }
4442
4443 /**
4444  * intel_post_enable_primary - Perform operations after enabling primary plane
4445  * @crtc: the CRTC whose primary plane was just enabled
4446  *
4447  * Performs potentially sleeping operations that must be done after the primary
4448  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4449  * called due to an explicit primary plane update, or due to an implicit
4450  * re-enable that is caused when a sprite plane is updated to no longer
4451  * completely hide the primary plane.
4452  */
4453 static void
4454 intel_post_enable_primary(struct drm_crtc *crtc)
4455 {
4456         struct drm_device *dev = crtc->dev;
4457         struct drm_i915_private *dev_priv = dev->dev_private;
4458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4459         int pipe = intel_crtc->pipe;
4460
4461         /*
4462          * FIXME IPS should be fine as long as one plane is
4463          * enabled, but in practice it seems to have problems
4464          * when going from primary only to sprite only and vice
4465          * versa.
4466          */
4467         hsw_enable_ips(intel_crtc);
4468
4469         /*
4470          * Gen2 reports pipe underruns whenever all planes are disabled.
4471          * So don't enable underrun reporting before at least some planes
4472          * are enabled.
4473          * FIXME: Need to fix the logic to work when we turn off all planes
4474          * but leave the pipe running.
4475          */
4476         if (IS_GEN2(dev))
4477                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4478
4479         /* Underruns don't always raise interrupts, so check manually. */
4480         intel_check_cpu_fifo_underruns(dev_priv);
4481         intel_check_pch_fifo_underruns(dev_priv);
4482 }
4483
4484 /* FIXME move all this to pre_plane_update() with proper state tracking */
4485 static void
4486 intel_pre_disable_primary(struct drm_crtc *crtc)
4487 {
4488         struct drm_device *dev = crtc->dev;
4489         struct drm_i915_private *dev_priv = dev->dev_private;
4490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4491         int pipe = intel_crtc->pipe;
4492
4493         /*
4494          * Gen2 reports pipe underruns whenever all planes are disabled.
4495          * So diasble underrun reporting before all the planes get disabled.
4496          * FIXME: Need to fix the logic to work when we turn off all planes
4497          * but leave the pipe running.
4498          */
4499         if (IS_GEN2(dev))
4500                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4501
4502         /*
4503          * FIXME IPS should be fine as long as one plane is
4504          * enabled, but in practice it seems to have problems
4505          * when going from primary only to sprite only and vice
4506          * versa.
4507          */
4508         hsw_disable_ips(intel_crtc);
4509 }
4510
4511 /* FIXME get rid of this and use pre_plane_update */
4512 static void
4513 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4514 {
4515         struct drm_device *dev = crtc->dev;
4516         struct drm_i915_private *dev_priv = dev->dev_private;
4517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4518         int pipe = intel_crtc->pipe;
4519
4520         intel_pre_disable_primary(crtc);
4521
4522         /*
4523          * Vblank time updates from the shadow to live plane control register
4524          * are blocked if the memory self-refresh mode is active at that
4525          * moment. So to make sure the plane gets truly disabled, disable
4526          * first the self-refresh mode. The self-refresh enable bit in turn
4527          * will be checked/applied by the HW only at the next frame start
4528          * event which is after the vblank start event, so we need to have a
4529          * wait-for-vblank between disabling the plane and the pipe.
4530          */
4531         if (HAS_GMCH_DISPLAY(dev)) {
4532                 intel_set_memory_cxsr(dev_priv, false);
4533                 dev_priv->wm.vlv.cxsr = false;
4534                 intel_wait_for_vblank(dev, pipe);
4535         }
4536 }
4537
4538 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4539 {
4540         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4541         struct drm_device *dev = crtc->base.dev;
4542         struct drm_i915_private *dev_priv = dev->dev_private;
4543         struct intel_crtc_state *pipe_config =
4544                 to_intel_crtc_state(crtc->base.state);
4545         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4546         struct drm_plane *primary = crtc->base.primary;
4547         struct drm_plane_state *old_pri_state =
4548                 drm_atomic_get_existing_plane_state(old_state, primary);
4549         bool modeset = needs_modeset(&pipe_config->base);
4550
4551         if (old_pri_state) {
4552                 struct intel_plane_state *primary_state =
4553                         to_intel_plane_state(primary->state);
4554                 struct intel_plane_state *old_primary_state =
4555                         to_intel_plane_state(old_pri_state);
4556
4557                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
4558
4559                 if (old_primary_state->visible &&
4560                     (modeset || !primary_state->visible))
4561                         intel_pre_disable_primary(&crtc->base);
4562         }
4563
4564         if (pipe_config->disable_cxsr) {
4565                 crtc->wm.cxsr_allowed = false;
4566
4567                 /*
4568                  * Vblank time updates from the shadow to live plane control register
4569                  * are blocked if the memory self-refresh mode is active at that
4570                  * moment. So to make sure the plane gets truly disabled, disable
4571                  * first the self-refresh mode. The self-refresh enable bit in turn
4572                  * will be checked/applied by the HW only at the next frame start
4573                  * event which is after the vblank start event, so we need to have a
4574                  * wait-for-vblank between disabling the plane and the pipe.
4575                  */
4576                 if (old_crtc_state->base.active) {
4577                         intel_set_memory_cxsr(dev_priv, false);
4578                         dev_priv->wm.vlv.cxsr = false;
4579                         intel_wait_for_vblank(dev, crtc->pipe);
4580                 }
4581         }
4582
4583         /*
4584          * IVB workaround: must disable low power watermarks for at least
4585          * one frame before enabling scaling.  LP watermarks can be re-enabled
4586          * when scaling is disabled.
4587          *
4588          * WaCxSRDisabledForSpriteScaling:ivb
4589          */
4590         if (pipe_config->disable_lp_wm) {
4591                 ilk_disable_lp_wm(dev);
4592                 intel_wait_for_vblank(dev, crtc->pipe);
4593         }
4594
4595         /*
4596          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4597          * watermark programming here.
4598          */
4599         if (needs_modeset(&pipe_config->base))
4600                 return;
4601
4602         /*
4603          * For platforms that support atomic watermarks, program the
4604          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4605          * will be the intermediate values that are safe for both pre- and
4606          * post- vblank; when vblank happens, the 'active' values will be set
4607          * to the final 'target' values and we'll do this again to get the
4608          * optimal watermarks.  For gen9+ platforms, the values we program here
4609          * will be the final target values which will get automatically latched
4610          * at vblank time; no further programming will be necessary.
4611          *
4612          * If a platform hasn't been transitioned to atomic watermarks yet,
4613          * we'll continue to update watermarks the old way, if flags tell
4614          * us to.
4615          */
4616         if (dev_priv->display.initial_watermarks != NULL)
4617                 dev_priv->display.initial_watermarks(pipe_config);
4618         else if (pipe_config->update_wm_pre)
4619                 intel_update_watermarks(&crtc->base);
4620 }
4621
4622 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4623 {
4624         struct drm_device *dev = crtc->dev;
4625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4626         struct drm_plane *p;
4627         int pipe = intel_crtc->pipe;
4628
4629         intel_crtc_dpms_overlay_disable(intel_crtc);
4630
4631         drm_for_each_plane_mask(p, dev, plane_mask)
4632                 to_intel_plane(p)->disable_plane(p, crtc);
4633
4634         /*
4635          * FIXME: Once we grow proper nuclear flip support out of this we need
4636          * to compute the mask of flip planes precisely. For the time being
4637          * consider this a flip to a NULL plane.
4638          */
4639         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4640 }
4641
4642 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4643 {
4644         struct drm_device *dev = crtc->dev;
4645         struct drm_i915_private *dev_priv = dev->dev_private;
4646         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4647         struct intel_encoder *encoder;
4648         int pipe = intel_crtc->pipe;
4649         struct intel_crtc_state *pipe_config =
4650                 to_intel_crtc_state(crtc->state);
4651
4652         if (WARN_ON(intel_crtc->active))
4653                 return;
4654
4655         /*
4656          * Sometimes spurious CPU pipe underruns happen during FDI
4657          * training, at least with VGA+HDMI cloning. Suppress them.
4658          *
4659          * On ILK we get an occasional spurious CPU pipe underruns
4660          * between eDP port A enable and vdd enable. Also PCH port
4661          * enable seems to result in the occasional CPU pipe underrun.
4662          *
4663          * Spurious PCH underruns also occur during PCH enabling.
4664          */
4665         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4666                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4667         if (intel_crtc->config->has_pch_encoder)
4668                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4669
4670         if (intel_crtc->config->has_pch_encoder)
4671                 intel_prepare_shared_dpll(intel_crtc);
4672
4673         if (intel_crtc->config->has_dp_encoder)
4674                 intel_dp_set_m_n(intel_crtc, M1_N1);
4675
4676         intel_set_pipe_timings(intel_crtc);
4677         intel_set_pipe_src_size(intel_crtc);
4678
4679         if (intel_crtc->config->has_pch_encoder) {
4680                 intel_cpu_transcoder_set_m_n(intel_crtc,
4681                                      &intel_crtc->config->fdi_m_n, NULL);
4682         }
4683
4684         ironlake_set_pipeconf(crtc);
4685
4686         intel_crtc->active = true;
4687
4688         for_each_encoder_on_crtc(dev, crtc, encoder)
4689                 if (encoder->pre_enable)
4690                         encoder->pre_enable(encoder);
4691
4692         if (intel_crtc->config->has_pch_encoder) {
4693                 /* Note: FDI PLL enabling _must_ be done before we enable the
4694                  * cpu pipes, hence this is separate from all the other fdi/pch
4695                  * enabling. */
4696                 ironlake_fdi_pll_enable(intel_crtc);
4697         } else {
4698                 assert_fdi_tx_disabled(dev_priv, pipe);
4699                 assert_fdi_rx_disabled(dev_priv, pipe);
4700         }
4701
4702         ironlake_pfit_enable(intel_crtc);
4703
4704         /*
4705          * On ILK+ LUT must be loaded before the pipe is running but with
4706          * clocks enabled
4707          */
4708         intel_color_load_luts(&pipe_config->base);
4709
4710         if (dev_priv->display.initial_watermarks != NULL)
4711                 dev_priv->display.initial_watermarks(intel_crtc->config);
4712         intel_enable_pipe(intel_crtc);
4713
4714         if (intel_crtc->config->has_pch_encoder)
4715                 ironlake_pch_enable(crtc);
4716
4717         assert_vblank_disabled(crtc);
4718         drm_crtc_vblank_on(crtc);
4719
4720         for_each_encoder_on_crtc(dev, crtc, encoder)
4721                 encoder->enable(encoder);
4722
4723         if (HAS_PCH_CPT(dev))
4724                 cpt_verify_modeset(dev, intel_crtc->pipe);
4725
4726         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4727         if (intel_crtc->config->has_pch_encoder)
4728                 intel_wait_for_vblank(dev, pipe);
4729         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4730         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4731 }
4732
4733 /* IPS only exists on ULT machines and is tied to pipe A. */
4734 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4735 {
4736         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4737 }
4738
4739 static void haswell_crtc_enable(struct drm_crtc *crtc)
4740 {
4741         struct drm_device *dev = crtc->dev;
4742         struct drm_i915_private *dev_priv = dev->dev_private;
4743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4744         struct intel_encoder *encoder;
4745         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4746         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4747         struct intel_crtc_state *pipe_config =
4748                 to_intel_crtc_state(crtc->state);
4749
4750         if (WARN_ON(intel_crtc->active))
4751                 return;
4752
4753         if (intel_crtc->config->has_pch_encoder)
4754                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4755                                                       false);
4756
4757         if (intel_crtc->config->shared_dpll)
4758                 intel_enable_shared_dpll(intel_crtc);
4759
4760         if (intel_crtc->config->has_dp_encoder)
4761                 intel_dp_set_m_n(intel_crtc, M1_N1);
4762
4763         if (!intel_crtc->config->has_dsi_encoder)
4764                 intel_set_pipe_timings(intel_crtc);
4765
4766         intel_set_pipe_src_size(intel_crtc);
4767
4768         if (cpu_transcoder != TRANSCODER_EDP &&
4769             !transcoder_is_dsi(cpu_transcoder)) {
4770                 I915_WRITE(PIPE_MULT(cpu_transcoder),
4771                            intel_crtc->config->pixel_multiplier - 1);
4772         }
4773
4774         if (intel_crtc->config->has_pch_encoder) {
4775                 intel_cpu_transcoder_set_m_n(intel_crtc,
4776                                      &intel_crtc->config->fdi_m_n, NULL);
4777         }
4778
4779         if (!intel_crtc->config->has_dsi_encoder)
4780                 haswell_set_pipeconf(crtc);
4781
4782         haswell_set_pipemisc(crtc);
4783
4784         intel_color_set_csc(&pipe_config->base);
4785
4786         intel_crtc->active = true;
4787
4788         if (intel_crtc->config->has_pch_encoder)
4789                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4790         else
4791                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4792
4793         for_each_encoder_on_crtc(dev, crtc, encoder) {
4794                 if (encoder->pre_enable)
4795                         encoder->pre_enable(encoder);
4796         }
4797
4798         if (intel_crtc->config->has_pch_encoder)
4799                 dev_priv->display.fdi_link_train(crtc);
4800
4801         if (!intel_crtc->config->has_dsi_encoder)
4802                 intel_ddi_enable_pipe_clock(intel_crtc);
4803
4804         if (INTEL_INFO(dev)->gen >= 9)
4805                 skylake_pfit_enable(intel_crtc);
4806         else
4807                 ironlake_pfit_enable(intel_crtc);
4808
4809         /*
4810          * On ILK+ LUT must be loaded before the pipe is running but with
4811          * clocks enabled
4812          */
4813         intel_color_load_luts(&pipe_config->base);
4814
4815         intel_ddi_set_pipe_settings(crtc);
4816         if (!intel_crtc->config->has_dsi_encoder)
4817                 intel_ddi_enable_transcoder_func(crtc);
4818
4819         if (dev_priv->display.initial_watermarks != NULL)
4820                 dev_priv->display.initial_watermarks(pipe_config);
4821         else
4822                 intel_update_watermarks(crtc);
4823
4824         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4825         if (!intel_crtc->config->has_dsi_encoder)
4826                 intel_enable_pipe(intel_crtc);
4827
4828         if (intel_crtc->config->has_pch_encoder)
4829                 lpt_pch_enable(crtc);
4830
4831         if (intel_crtc->config->dp_encoder_is_mst)
4832                 intel_ddi_set_vc_payload_alloc(crtc, true);
4833
4834         assert_vblank_disabled(crtc);
4835         drm_crtc_vblank_on(crtc);
4836
4837         for_each_encoder_on_crtc(dev, crtc, encoder) {
4838                 encoder->enable(encoder);
4839                 intel_opregion_notify_encoder(encoder, true);
4840         }
4841
4842         if (intel_crtc->config->has_pch_encoder) {
4843                 intel_wait_for_vblank(dev, pipe);
4844                 intel_wait_for_vblank(dev, pipe);
4845                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4846                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4847                                                       true);
4848         }
4849
4850         /* If we change the relative order between pipe/planes enabling, we need
4851          * to change the workaround. */
4852         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4853         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4854                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4855                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4856         }
4857 }
4858
4859 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4860 {
4861         struct drm_device *dev = crtc->base.dev;
4862         struct drm_i915_private *dev_priv = dev->dev_private;
4863         int pipe = crtc->pipe;
4864
4865         /* To avoid upsetting the power well on haswell only disable the pfit if
4866          * it's in use. The hw state code will make sure we get this right. */
4867         if (force || crtc->config->pch_pfit.enabled) {
4868                 I915_WRITE(PF_CTL(pipe), 0);
4869                 I915_WRITE(PF_WIN_POS(pipe), 0);
4870                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4871         }
4872 }
4873
4874 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4875 {
4876         struct drm_device *dev = crtc->dev;
4877         struct drm_i915_private *dev_priv = dev->dev_private;
4878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4879         struct intel_encoder *encoder;
4880         int pipe = intel_crtc->pipe;
4881
4882         /*
4883          * Sometimes spurious CPU pipe underruns happen when the
4884          * pipe is already disabled, but FDI RX/TX is still enabled.
4885          * Happens at least with VGA+HDMI cloning. Suppress them.
4886          */
4887         if (intel_crtc->config->has_pch_encoder) {
4888                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4889                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4890         }
4891
4892         for_each_encoder_on_crtc(dev, crtc, encoder)
4893                 encoder->disable(encoder);
4894
4895         drm_crtc_vblank_off(crtc);
4896         assert_vblank_disabled(crtc);
4897
4898         intel_disable_pipe(intel_crtc);
4899
4900         ironlake_pfit_disable(intel_crtc, false);
4901
4902         if (intel_crtc->config->has_pch_encoder)
4903                 ironlake_fdi_disable(crtc);
4904
4905         for_each_encoder_on_crtc(dev, crtc, encoder)
4906                 if (encoder->post_disable)
4907                         encoder->post_disable(encoder);
4908
4909         if (intel_crtc->config->has_pch_encoder) {
4910                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4911
4912                 if (HAS_PCH_CPT(dev)) {
4913                         i915_reg_t reg;
4914                         u32 temp;
4915
4916                         /* disable TRANS_DP_CTL */
4917                         reg = TRANS_DP_CTL(pipe);
4918                         temp = I915_READ(reg);
4919                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4920                                   TRANS_DP_PORT_SEL_MASK);
4921                         temp |= TRANS_DP_PORT_SEL_NONE;
4922                         I915_WRITE(reg, temp);
4923
4924                         /* disable DPLL_SEL */
4925                         temp = I915_READ(PCH_DPLL_SEL);
4926                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4927                         I915_WRITE(PCH_DPLL_SEL, temp);
4928                 }
4929
4930                 ironlake_fdi_pll_disable(intel_crtc);
4931         }
4932
4933         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4934         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4935 }
4936
4937 static void haswell_crtc_disable(struct drm_crtc *crtc)
4938 {
4939         struct drm_device *dev = crtc->dev;
4940         struct drm_i915_private *dev_priv = dev->dev_private;
4941         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4942         struct intel_encoder *encoder;
4943         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4944
4945         if (intel_crtc->config->has_pch_encoder)
4946                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4947                                                       false);
4948
4949         for_each_encoder_on_crtc(dev, crtc, encoder) {
4950                 intel_opregion_notify_encoder(encoder, false);
4951                 encoder->disable(encoder);
4952         }
4953
4954         drm_crtc_vblank_off(crtc);
4955         assert_vblank_disabled(crtc);
4956
4957         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4958         if (!intel_crtc->config->has_dsi_encoder)
4959                 intel_disable_pipe(intel_crtc);
4960
4961         if (intel_crtc->config->dp_encoder_is_mst)
4962                 intel_ddi_set_vc_payload_alloc(crtc, false);
4963
4964         if (!intel_crtc->config->has_dsi_encoder)
4965                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4966
4967         if (INTEL_INFO(dev)->gen >= 9)
4968                 skylake_scaler_disable(intel_crtc);
4969         else
4970                 ironlake_pfit_disable(intel_crtc, false);
4971
4972         if (!intel_crtc->config->has_dsi_encoder)
4973                 intel_ddi_disable_pipe_clock(intel_crtc);
4974
4975         for_each_encoder_on_crtc(dev, crtc, encoder)
4976                 if (encoder->post_disable)
4977                         encoder->post_disable(encoder);
4978
4979         if (intel_crtc->config->has_pch_encoder) {
4980                 lpt_disable_pch_transcoder(dev_priv);
4981                 lpt_disable_iclkip(dev_priv);
4982                 intel_ddi_fdi_disable(crtc);
4983
4984                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4985                                                       true);
4986         }
4987 }
4988
4989 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4990 {
4991         struct drm_device *dev = crtc->base.dev;
4992         struct drm_i915_private *dev_priv = dev->dev_private;
4993         struct intel_crtc_state *pipe_config = crtc->config;
4994
4995         if (!pipe_config->gmch_pfit.control)
4996                 return;
4997
4998         /*
4999          * The panel fitter should only be adjusted whilst the pipe is disabled,
5000          * according to register description and PRM.
5001          */
5002         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5003         assert_pipe_disabled(dev_priv, crtc->pipe);
5004
5005         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5006         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5007
5008         /* Border color in case we don't scale up to the full screen. Black by
5009          * default, change to something else for debugging. */
5010         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5011 }
5012
5013 static enum intel_display_power_domain port_to_power_domain(enum port port)
5014 {
5015         switch (port) {
5016         case PORT_A:
5017                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5018         case PORT_B:
5019                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5020         case PORT_C:
5021                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5022         case PORT_D:
5023                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5024         case PORT_E:
5025                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5026         default:
5027                 MISSING_CASE(port);
5028                 return POWER_DOMAIN_PORT_OTHER;
5029         }
5030 }
5031
5032 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5033 {
5034         switch (port) {
5035         case PORT_A:
5036                 return POWER_DOMAIN_AUX_A;
5037         case PORT_B:
5038                 return POWER_DOMAIN_AUX_B;
5039         case PORT_C:
5040                 return POWER_DOMAIN_AUX_C;
5041         case PORT_D:
5042                 return POWER_DOMAIN_AUX_D;
5043         case PORT_E:
5044                 /* FIXME: Check VBT for actual wiring of PORT E */
5045                 return POWER_DOMAIN_AUX_D;
5046         default:
5047                 MISSING_CASE(port);
5048                 return POWER_DOMAIN_AUX_A;
5049         }
5050 }
5051
5052 enum intel_display_power_domain
5053 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5054 {
5055         struct drm_device *dev = intel_encoder->base.dev;
5056         struct intel_digital_port *intel_dig_port;
5057
5058         switch (intel_encoder->type) {
5059         case INTEL_OUTPUT_UNKNOWN:
5060                 /* Only DDI platforms should ever use this output type */
5061                 WARN_ON_ONCE(!HAS_DDI(dev));
5062         case INTEL_OUTPUT_DISPLAYPORT:
5063         case INTEL_OUTPUT_HDMI:
5064         case INTEL_OUTPUT_EDP:
5065                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5066                 return port_to_power_domain(intel_dig_port->port);
5067         case INTEL_OUTPUT_DP_MST:
5068                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5069                 return port_to_power_domain(intel_dig_port->port);
5070         case INTEL_OUTPUT_ANALOG:
5071                 return POWER_DOMAIN_PORT_CRT;
5072         case INTEL_OUTPUT_DSI:
5073                 return POWER_DOMAIN_PORT_DSI;
5074         default:
5075                 return POWER_DOMAIN_PORT_OTHER;
5076         }
5077 }
5078
5079 enum intel_display_power_domain
5080 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5081 {
5082         struct drm_device *dev = intel_encoder->base.dev;
5083         struct intel_digital_port *intel_dig_port;
5084
5085         switch (intel_encoder->type) {
5086         case INTEL_OUTPUT_UNKNOWN:
5087         case INTEL_OUTPUT_HDMI:
5088                 /*
5089                  * Only DDI platforms should ever use these output types.
5090                  * We can get here after the HDMI detect code has already set
5091                  * the type of the shared encoder. Since we can't be sure
5092                  * what's the status of the given connectors, play safe and
5093                  * run the DP detection too.
5094                  */
5095                 WARN_ON_ONCE(!HAS_DDI(dev));
5096         case INTEL_OUTPUT_DISPLAYPORT:
5097         case INTEL_OUTPUT_EDP:
5098                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5099                 return port_to_aux_power_domain(intel_dig_port->port);
5100         case INTEL_OUTPUT_DP_MST:
5101                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5102                 return port_to_aux_power_domain(intel_dig_port->port);
5103         default:
5104                 MISSING_CASE(intel_encoder->type);
5105                 return POWER_DOMAIN_AUX_A;
5106         }
5107 }
5108
5109 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5110                                             struct intel_crtc_state *crtc_state)
5111 {
5112         struct drm_device *dev = crtc->dev;
5113         struct drm_encoder *encoder;
5114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5115         enum pipe pipe = intel_crtc->pipe;
5116         unsigned long mask;
5117         enum transcoder transcoder = crtc_state->cpu_transcoder;
5118
5119         if (!crtc_state->base.active)
5120                 return 0;
5121
5122         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5123         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5124         if (crtc_state->pch_pfit.enabled ||
5125             crtc_state->pch_pfit.force_thru)
5126                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5127
5128         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5129                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5130
5131                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5132         }
5133
5134         if (crtc_state->shared_dpll)
5135                 mask |= BIT(POWER_DOMAIN_PLLS);
5136
5137         return mask;
5138 }
5139
5140 static unsigned long
5141 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5142                                struct intel_crtc_state *crtc_state)
5143 {
5144         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5145         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5146         enum intel_display_power_domain domain;
5147         unsigned long domains, new_domains, old_domains, ms_domain = 0;
5148
5149         old_domains = intel_crtc->enabled_power_domains;
5150         intel_crtc->enabled_power_domains = new_domains =
5151                 get_crtc_power_domains(crtc, crtc_state);
5152
5153         if (needs_modeset(&crtc_state->base))
5154                 ms_domain = BIT(POWER_DOMAIN_MODESET);
5155
5156         domains = (new_domains & ~old_domains) | ms_domain;
5157
5158         for_each_power_domain(domain, domains)
5159                 intel_display_power_get(dev_priv, domain);
5160
5161         return (old_domains & ~new_domains) | ms_domain;
5162 }
5163
5164 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5165                                       unsigned long domains)
5166 {
5167         enum intel_display_power_domain domain;
5168
5169         for_each_power_domain(domain, domains)
5170                 intel_display_power_put(dev_priv, domain);
5171 }
5172
5173 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5174 {
5175         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5176
5177         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5178             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5179                 return max_cdclk_freq;
5180         else if (IS_CHERRYVIEW(dev_priv))
5181                 return max_cdclk_freq*95/100;
5182         else if (INTEL_INFO(dev_priv)->gen < 4)
5183                 return 2*max_cdclk_freq*90/100;
5184         else
5185                 return max_cdclk_freq*90/100;
5186 }
5187
5188 static int skl_calc_cdclk(int max_pixclk, int vco);
5189
5190 static void intel_update_max_cdclk(struct drm_device *dev)
5191 {
5192         struct drm_i915_private *dev_priv = dev->dev_private;
5193
5194         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5195                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5196                 int max_cdclk, vco;
5197
5198                 vco = dev_priv->skl_preferred_vco_freq;
5199                 WARN_ON(vco != 8100000 && vco != 8640000);
5200
5201                 /*
5202                  * Use the lower (vco 8640) cdclk values as a
5203                  * first guess. skl_calc_cdclk() will correct it
5204                  * if the preferred vco is 8100 instead.
5205                  */
5206                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5207                         max_cdclk = 617143;
5208                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5209                         max_cdclk = 540000;
5210                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5211                         max_cdclk = 432000;
5212                 else
5213                         max_cdclk = 308571;
5214
5215                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5216         } else if (IS_BROXTON(dev)) {
5217                 dev_priv->max_cdclk_freq = 624000;
5218         } else if (IS_BROADWELL(dev))  {
5219                 /*
5220                  * FIXME with extra cooling we can allow
5221                  * 540 MHz for ULX and 675 Mhz for ULT.
5222                  * How can we know if extra cooling is
5223                  * available? PCI ID, VTB, something else?
5224                  */
5225                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5226                         dev_priv->max_cdclk_freq = 450000;
5227                 else if (IS_BDW_ULX(dev))
5228                         dev_priv->max_cdclk_freq = 450000;
5229                 else if (IS_BDW_ULT(dev))
5230                         dev_priv->max_cdclk_freq = 540000;
5231                 else
5232                         dev_priv->max_cdclk_freq = 675000;
5233         } else if (IS_CHERRYVIEW(dev)) {
5234                 dev_priv->max_cdclk_freq = 320000;
5235         } else if (IS_VALLEYVIEW(dev)) {
5236                 dev_priv->max_cdclk_freq = 400000;
5237         } else {
5238                 /* otherwise assume cdclk is fixed */
5239                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5240         }
5241
5242         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5243
5244         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5245                          dev_priv->max_cdclk_freq);
5246
5247         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5248                          dev_priv->max_dotclk_freq);
5249 }
5250
5251 static void intel_update_cdclk(struct drm_device *dev)
5252 {
5253         struct drm_i915_private *dev_priv = dev->dev_private;
5254
5255         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5256
5257         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5258                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5259                                  dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5260                                  dev_priv->cdclk_pll.ref);
5261         else
5262                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5263                                  dev_priv->cdclk_freq);
5264
5265         /*
5266          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5267          * Programmng [sic] note: bit[9:2] should be programmed to the number
5268          * of cdclk that generates 4MHz reference clock freq which is used to
5269          * generate GMBus clock. This will vary with the cdclk freq.
5270          */
5271         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5272                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5273 }
5274
5275 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5276 static int skl_cdclk_decimal(int cdclk)
5277 {
5278         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5279 }
5280
5281 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5282 {
5283         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5284
5285         /* Timeout 200us */
5286         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
5287                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5288 }
5289
5290 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, u32 ratio)
5291 {
5292         u32 val;
5293
5294         val = I915_READ(BXT_DE_PLL_CTL);
5295         val &= ~BXT_DE_PLL_RATIO_MASK;
5296         val |= ratio;
5297         I915_WRITE(BXT_DE_PLL_CTL, val);
5298
5299         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5300
5301         /* Timeout 200us */
5302         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
5303                 DRM_ERROR("timeout waiting for DE PLL lock\n");
5304 }
5305
5306 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5307 {
5308         uint32_t divider;
5309         uint32_t ratio;
5310         uint32_t current_cdclk;
5311         int ret;
5312
5313         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5314         switch (cdclk) {
5315         case 144000:
5316                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5317                 ratio = BXT_DE_PLL_RATIO(60);
5318                 break;
5319         case 288000:
5320                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5321                 ratio = BXT_DE_PLL_RATIO(60);
5322                 break;
5323         case 384000:
5324                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5325                 ratio = BXT_DE_PLL_RATIO(60);
5326                 break;
5327         case 576000:
5328                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5329                 ratio = BXT_DE_PLL_RATIO(60);
5330                 break;
5331         case 624000:
5332                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5333                 ratio = BXT_DE_PLL_RATIO(65);
5334                 break;
5335         case 19200:
5336                 /*
5337                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5338                  * to suppress GCC warning.
5339                  */
5340                 ratio = 0;
5341                 divider = 0;
5342                 break;
5343         default:
5344                 DRM_ERROR("unsupported CDCLK freq %d", cdclk);
5345
5346                 return;
5347         }
5348
5349         mutex_lock(&dev_priv->rps.hw_lock);
5350         /* Inform power controller of upcoming frequency change */
5351         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5352                                       0x80000000);
5353         mutex_unlock(&dev_priv->rps.hw_lock);
5354
5355         if (ret) {
5356                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5357                           ret, cdclk);
5358                 return;
5359         }
5360
5361         current_cdclk = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5362         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5363         current_cdclk = current_cdclk * 500 + 1000;
5364
5365         /*
5366          * DE PLL has to be disabled when
5367          * - setting to 19.2MHz (bypass, PLL isn't used)
5368          * - before setting to 624MHz (PLL needs toggling)
5369          * - before setting to any frequency from 624MHz (PLL needs toggling)
5370          */
5371         if (cdclk == 19200 || cdclk == 624000 ||
5372             current_cdclk == 624000) {
5373                 bxt_de_pll_disable(dev_priv);
5374         }
5375
5376         if (cdclk != 19200) {
5377                 uint32_t val;
5378
5379                 bxt_de_pll_enable(dev_priv, ratio);
5380
5381                 val = divider | skl_cdclk_decimal(cdclk);
5382                 /*
5383                  * FIXME if only the cd2x divider needs changing, it could be done
5384                  * without shutting off the pipe (if only one pipe is active).
5385                  */
5386                 val |= BXT_CDCLK_CD2X_PIPE_NONE;
5387                 /*
5388                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5389                  * enable otherwise.
5390                  */
5391                 if (cdclk >= 500000)
5392                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5393                 I915_WRITE(CDCLK_CTL, val);
5394         }
5395
5396         mutex_lock(&dev_priv->rps.hw_lock);
5397         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5398                                       DIV_ROUND_UP(cdclk, 25000));
5399         mutex_unlock(&dev_priv->rps.hw_lock);
5400
5401         if (ret) {
5402                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5403                           ret, cdclk);
5404                 return;
5405         }
5406
5407         intel_update_cdclk(dev_priv->dev);
5408 }
5409
5410 static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
5411 {
5412         if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
5413                 return false;
5414
5415         /* TODO: Check for a valid CDCLK rate */
5416
5417         return true;
5418 }
5419
5420 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
5421 {
5422         return broxton_cdclk_is_enabled(dev_priv);
5423 }
5424
5425 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5426 {
5427         /* check if cd clock is enabled */
5428         if (broxton_cdclk_is_enabled(dev_priv)) {
5429                 DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
5430                 return;
5431         }
5432
5433         DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
5434
5435         /*
5436          * FIXME:
5437          * - The initial CDCLK needs to be read from VBT.
5438          *   Need to make this change after VBT has changes for BXT.
5439          * - check if setting the max (or any) cdclk freq is really necessary
5440          *   here, it belongs to modeset time
5441          */
5442         broxton_set_cdclk(dev_priv, 624000);
5443 }
5444
5445 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
5446 {
5447         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5448         broxton_set_cdclk(dev_priv, 19200);
5449 }
5450
5451 static int skl_calc_cdclk(int max_pixclk, int vco)
5452 {
5453         if (vco == 8640000) {
5454                 if (max_pixclk > 540000)
5455                         return 617143;
5456                 else if (max_pixclk > 432000)
5457                         return 540000;
5458                 else if (max_pixclk > 308571)
5459                         return 432000;
5460                 else
5461                         return 308571;
5462         } else {
5463                 if (max_pixclk > 540000)
5464                         return 675000;
5465                 else if (max_pixclk > 450000)
5466                         return 540000;
5467                 else if (max_pixclk > 337500)
5468                         return 450000;
5469                 else
5470                         return 337500;
5471         }
5472 }
5473
5474 static void
5475 skl_dpll0_update(struct drm_i915_private *dev_priv)
5476 {
5477         u32 val;
5478
5479         dev_priv->cdclk_pll.ref = 24000;
5480
5481         val = I915_READ(LCPLL1_CTL);
5482         if ((val & LCPLL_PLL_ENABLE) == 0) {
5483                 dev_priv->cdclk_pll.vco = 0;
5484                 return;
5485         }
5486
5487         WARN_ON((val & LCPLL_PLL_LOCK) == 0);
5488
5489         val = I915_READ(DPLL_CTRL1);
5490
5491         WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5492                         DPLL_CTRL1_SSC(SKL_DPLL0) |
5493                         DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5494                 DPLL_CTRL1_OVERRIDE(SKL_DPLL0));
5495
5496         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
5497         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
5498         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
5499         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
5500         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
5501                 dev_priv->cdclk_pll.vco = 8100000;
5502                 break;
5503         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
5504         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
5505                 dev_priv->cdclk_pll.vco = 8640000;
5506                 break;
5507         default:
5508                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5509                 dev_priv->cdclk_pll.vco = 0;
5510                 break;
5511         }
5512 }
5513
5514 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5515 {
5516         bool changed = dev_priv->skl_preferred_vco_freq != vco;
5517
5518         dev_priv->skl_preferred_vco_freq = vco;
5519
5520         if (changed)
5521                 intel_update_max_cdclk(dev_priv->dev);
5522 }
5523
5524 static void
5525 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5526 {
5527         int min_cdclk = skl_calc_cdclk(0, vco);
5528         u32 val;
5529
5530         WARN_ON(vco != 8100000 && vco != 8640000);
5531
5532         /* select the minimum CDCLK before enabling DPLL 0 */
5533         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5534         I915_WRITE(CDCLK_CTL, val);
5535         POSTING_READ(CDCLK_CTL);
5536
5537         /*
5538          * We always enable DPLL0 with the lowest link rate possible, but still
5539          * taking into account the VCO required to operate the eDP panel at the
5540          * desired frequency. The usual DP link rates operate with a VCO of
5541          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5542          * The modeset code is responsible for the selection of the exact link
5543          * rate later on, with the constraint of choosing a frequency that
5544          * works with vco.
5545          */
5546         val = I915_READ(DPLL_CTRL1);
5547
5548         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5549                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5550         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5551         if (vco == 8640000)
5552                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5553                                             SKL_DPLL0);
5554         else
5555                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5556                                             SKL_DPLL0);
5557
5558         I915_WRITE(DPLL_CTRL1, val);
5559         POSTING_READ(DPLL_CTRL1);
5560
5561         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5562
5563         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5564                 DRM_ERROR("DPLL0 not locked\n");
5565
5566         dev_priv->cdclk_pll.vco = vco;
5567
5568         /* We'll want to keep using the current vco from now on. */
5569         skl_set_preferred_cdclk_vco(dev_priv, vco);
5570 }
5571
5572 static void
5573 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5574 {
5575         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5576         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5577                 DRM_ERROR("Couldn't disable DPLL0\n");
5578
5579         dev_priv->cdclk_pll.vco = 0;
5580 }
5581
5582 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5583 {
5584         int ret;
5585         u32 val;
5586
5587         /* inform PCU we want to change CDCLK */
5588         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5589         mutex_lock(&dev_priv->rps.hw_lock);
5590         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5591         mutex_unlock(&dev_priv->rps.hw_lock);
5592
5593         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5594 }
5595
5596 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5597 {
5598         unsigned int i;
5599
5600         for (i = 0; i < 15; i++) {
5601                 if (skl_cdclk_pcu_ready(dev_priv))
5602                         return true;
5603                 udelay(10);
5604         }
5605
5606         return false;
5607 }
5608
5609 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5610 {
5611         struct drm_device *dev = dev_priv->dev;
5612         u32 freq_select, pcu_ack;
5613
5614         WARN_ON((cdclk == 24000) != (vco == 0));
5615
5616         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5617
5618         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5619                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5620                 return;
5621         }
5622
5623         /* set CDCLK_CTL */
5624         switch (cdclk) {
5625         case 450000:
5626         case 432000:
5627                 freq_select = CDCLK_FREQ_450_432;
5628                 pcu_ack = 1;
5629                 break;
5630         case 540000:
5631                 freq_select = CDCLK_FREQ_540;
5632                 pcu_ack = 2;
5633                 break;
5634         case 308571:
5635         case 337500:
5636         default:
5637                 freq_select = CDCLK_FREQ_337_308;
5638                 pcu_ack = 0;
5639                 break;
5640         case 617143:
5641         case 675000:
5642                 freq_select = CDCLK_FREQ_675_617;
5643                 pcu_ack = 3;
5644                 break;
5645         }
5646
5647         if (dev_priv->cdclk_pll.vco != 0 &&
5648             dev_priv->cdclk_pll.vco != vco)
5649                 skl_dpll0_disable(dev_priv);
5650
5651         if (dev_priv->cdclk_pll.vco != vco)
5652                 skl_dpll0_enable(dev_priv, vco);
5653
5654         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5655         POSTING_READ(CDCLK_CTL);
5656
5657         /* inform PCU of the change */
5658         mutex_lock(&dev_priv->rps.hw_lock);
5659         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5660         mutex_unlock(&dev_priv->rps.hw_lock);
5661
5662         intel_update_cdclk(dev);
5663 }
5664
5665 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
5666
5667 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5668 {
5669         skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
5670 }
5671
5672 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5673 {
5674         int cdclk, vco;
5675
5676         skl_sanitize_cdclk(dev_priv);
5677
5678         if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
5679                 /*
5680                  * Use the current vco as our initial
5681                  * guess as to what the preferred vco is.
5682                  */
5683                 if (dev_priv->skl_preferred_vco_freq == 0)
5684                         skl_set_preferred_cdclk_vco(dev_priv,
5685                                                     dev_priv->cdclk_pll.vco);
5686                 return;
5687         }
5688
5689         vco = dev_priv->skl_preferred_vco_freq;
5690         if (vco == 0)
5691                 vco = 8100000;
5692         cdclk = skl_calc_cdclk(0, vco);
5693
5694         skl_set_cdclk(dev_priv, cdclk, vco);
5695 }
5696
5697 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5698 {
5699         uint32_t cdctl, expected;
5700
5701         /*
5702          * check if the pre-os intialized the display
5703          * There is SWF18 scratchpad register defined which is set by the
5704          * pre-os which can be used by the OS drivers to check the status
5705          */
5706         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5707                 goto sanitize;
5708
5709         /* Is PLL enabled and locked ? */
5710         if ((I915_READ(LCPLL1_CTL) & (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK)) !=
5711             (LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK))
5712                 goto sanitize;
5713
5714         if ((I915_READ(DPLL_CTRL1) & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
5715                                       DPLL_CTRL1_SSC(SKL_DPLL0) |
5716                                       DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
5717             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))
5718                 goto sanitize;
5719
5720         intel_update_cdclk(dev_priv->dev);
5721
5722         /* DPLL okay; verify the cdclock
5723          *
5724          * Noticed in some instances that the freq selection is correct but
5725          * decimal part is programmed wrong from BIOS where pre-os does not
5726          * enable display. Verify the same as well.
5727          */
5728         cdctl = I915_READ(CDCLK_CTL);
5729         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
5730                 skl_cdclk_decimal(dev_priv->cdclk_freq);
5731         if (cdctl == expected)
5732                 /* All well; nothing to sanitize */
5733                 return;
5734
5735 sanitize:
5736         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
5737
5738         /* force cdclk programming */
5739         dev_priv->cdclk_freq = 0;
5740         /* force full PLL disable + enable */
5741         dev_priv->cdclk_pll.vco = -1;
5742 }
5743
5744 /* Adjust CDclk dividers to allow high res or save power if possible */
5745 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5746 {
5747         struct drm_i915_private *dev_priv = dev->dev_private;
5748         u32 val, cmd;
5749
5750         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5751                                         != dev_priv->cdclk_freq);
5752
5753         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5754                 cmd = 2;
5755         else if (cdclk == 266667)
5756                 cmd = 1;
5757         else
5758                 cmd = 0;
5759
5760         mutex_lock(&dev_priv->rps.hw_lock);
5761         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5762         val &= ~DSPFREQGUAR_MASK;
5763         val |= (cmd << DSPFREQGUAR_SHIFT);
5764         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5765         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5766                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5767                      50)) {
5768                 DRM_ERROR("timed out waiting for CDclk change\n");
5769         }
5770         mutex_unlock(&dev_priv->rps.hw_lock);
5771
5772         mutex_lock(&dev_priv->sb_lock);
5773
5774         if (cdclk == 400000) {
5775                 u32 divider;
5776
5777                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5778
5779                 /* adjust cdclk divider */
5780                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5781                 val &= ~CCK_FREQUENCY_VALUES;
5782                 val |= divider;
5783                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5784
5785                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5786                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5787                              50))
5788                         DRM_ERROR("timed out waiting for CDclk change\n");
5789         }
5790
5791         /* adjust self-refresh exit latency value */
5792         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5793         val &= ~0x7f;
5794
5795         /*
5796          * For high bandwidth configs, we set a higher latency in the bunit
5797          * so that the core display fetch happens in time to avoid underruns.
5798          */
5799         if (cdclk == 400000)
5800                 val |= 4500 / 250; /* 4.5 usec */
5801         else
5802                 val |= 3000 / 250; /* 3.0 usec */
5803         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5804
5805         mutex_unlock(&dev_priv->sb_lock);
5806
5807         intel_update_cdclk(dev);
5808 }
5809
5810 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5811 {
5812         struct drm_i915_private *dev_priv = dev->dev_private;
5813         u32 val, cmd;
5814
5815         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5816                                                 != dev_priv->cdclk_freq);
5817
5818         switch (cdclk) {
5819         case 333333:
5820         case 320000:
5821         case 266667:
5822         case 200000:
5823                 break;
5824         default:
5825                 MISSING_CASE(cdclk);
5826                 return;
5827         }
5828
5829         /*
5830          * Specs are full of misinformation, but testing on actual
5831          * hardware has shown that we just need to write the desired
5832          * CCK divider into the Punit register.
5833          */
5834         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5835
5836         mutex_lock(&dev_priv->rps.hw_lock);
5837         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5838         val &= ~DSPFREQGUAR_MASK_CHV;
5839         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5840         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5841         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5842                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5843                      50)) {
5844                 DRM_ERROR("timed out waiting for CDclk change\n");
5845         }
5846         mutex_unlock(&dev_priv->rps.hw_lock);
5847
5848         intel_update_cdclk(dev);
5849 }
5850
5851 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5852                                  int max_pixclk)
5853 {
5854         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5855         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5856
5857         /*
5858          * Really only a few cases to deal with, as only 4 CDclks are supported:
5859          *   200MHz
5860          *   267MHz
5861          *   320/333MHz (depends on HPLL freq)
5862          *   400MHz (VLV only)
5863          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5864          * of the lower bin and adjust if needed.
5865          *
5866          * We seem to get an unstable or solid color picture at 200MHz.
5867          * Not sure what's wrong. For now use 200MHz only when all pipes
5868          * are off.
5869          */
5870         if (!IS_CHERRYVIEW(dev_priv) &&
5871             max_pixclk > freq_320*limit/100)
5872                 return 400000;
5873         else if (max_pixclk > 266667*limit/100)
5874                 return freq_320;
5875         else if (max_pixclk > 0)
5876                 return 266667;
5877         else
5878                 return 200000;
5879 }
5880
5881 static int broxton_calc_cdclk(int max_pixclk)
5882 {
5883         /*
5884          * FIXME:
5885          * - set 19.2MHz bypass frequency if there are no active pipes
5886          */
5887         if (max_pixclk > 576000)
5888                 return 624000;
5889         else if (max_pixclk > 384000)
5890                 return 576000;
5891         else if (max_pixclk > 288000)
5892                 return 384000;
5893         else if (max_pixclk > 144000)
5894                 return 288000;
5895         else
5896                 return 144000;
5897 }
5898
5899 /* Compute the max pixel clock for new configuration. */
5900 static int intel_mode_max_pixclk(struct drm_device *dev,
5901                                  struct drm_atomic_state *state)
5902 {
5903         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5904         struct drm_i915_private *dev_priv = dev->dev_private;
5905         struct drm_crtc *crtc;
5906         struct drm_crtc_state *crtc_state;
5907         unsigned max_pixclk = 0, i;
5908         enum pipe pipe;
5909
5910         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5911                sizeof(intel_state->min_pixclk));
5912
5913         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5914                 int pixclk = 0;
5915
5916                 if (crtc_state->enable)
5917                         pixclk = crtc_state->adjusted_mode.crtc_clock;
5918
5919                 intel_state->min_pixclk[i] = pixclk;
5920         }
5921
5922         for_each_pipe(dev_priv, pipe)
5923                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5924
5925         return max_pixclk;
5926 }
5927
5928 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5929 {
5930         struct drm_device *dev = state->dev;
5931         struct drm_i915_private *dev_priv = dev->dev_private;
5932         int max_pixclk = intel_mode_max_pixclk(dev, state);
5933         struct intel_atomic_state *intel_state =
5934                 to_intel_atomic_state(state);
5935
5936         intel_state->cdclk = intel_state->dev_cdclk =
5937                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5938
5939         if (!intel_state->active_crtcs)
5940                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5941
5942         return 0;
5943 }
5944
5945 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5946 {
5947         int max_pixclk = ilk_max_pixel_rate(state);
5948         struct intel_atomic_state *intel_state =
5949                 to_intel_atomic_state(state);
5950
5951         intel_state->cdclk = intel_state->dev_cdclk =
5952                 broxton_calc_cdclk(max_pixclk);
5953
5954         if (!intel_state->active_crtcs)
5955                 intel_state->dev_cdclk = broxton_calc_cdclk(0);
5956
5957         return 0;
5958 }
5959
5960 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5961 {
5962         unsigned int credits, default_credits;
5963
5964         if (IS_CHERRYVIEW(dev_priv))
5965                 default_credits = PFI_CREDIT(12);
5966         else
5967                 default_credits = PFI_CREDIT(8);
5968
5969         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5970                 /* CHV suggested value is 31 or 63 */
5971                 if (IS_CHERRYVIEW(dev_priv))
5972                         credits = PFI_CREDIT_63;
5973                 else
5974                         credits = PFI_CREDIT(15);
5975         } else {
5976                 credits = default_credits;
5977         }
5978
5979         /*
5980          * WA - write default credits before re-programming
5981          * FIXME: should we also set the resend bit here?
5982          */
5983         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5984                    default_credits);
5985
5986         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5987                    credits | PFI_CREDIT_RESEND);
5988
5989         /*
5990          * FIXME is this guaranteed to clear
5991          * immediately or should we poll for it?
5992          */
5993         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5994 }
5995
5996 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5997 {
5998         struct drm_device *dev = old_state->dev;
5999         struct drm_i915_private *dev_priv = dev->dev_private;
6000         struct intel_atomic_state *old_intel_state =
6001                 to_intel_atomic_state(old_state);
6002         unsigned req_cdclk = old_intel_state->dev_cdclk;
6003
6004         /*
6005          * FIXME: We can end up here with all power domains off, yet
6006          * with a CDCLK frequency other than the minimum. To account
6007          * for this take the PIPE-A power domain, which covers the HW
6008          * blocks needed for the following programming. This can be
6009          * removed once it's guaranteed that we get here either with
6010          * the minimum CDCLK set, or the required power domains
6011          * enabled.
6012          */
6013         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6014
6015         if (IS_CHERRYVIEW(dev))
6016                 cherryview_set_cdclk(dev, req_cdclk);
6017         else
6018                 valleyview_set_cdclk(dev, req_cdclk);
6019
6020         vlv_program_pfi_credits(dev_priv);
6021
6022         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6023 }
6024
6025 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6026 {
6027         struct drm_device *dev = crtc->dev;
6028         struct drm_i915_private *dev_priv = to_i915(dev);
6029         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6030         struct intel_encoder *encoder;
6031         struct intel_crtc_state *pipe_config =
6032                 to_intel_crtc_state(crtc->state);
6033         int pipe = intel_crtc->pipe;
6034
6035         if (WARN_ON(intel_crtc->active))
6036                 return;
6037
6038         if (intel_crtc->config->has_dp_encoder)
6039                 intel_dp_set_m_n(intel_crtc, M1_N1);
6040
6041         intel_set_pipe_timings(intel_crtc);
6042         intel_set_pipe_src_size(intel_crtc);
6043
6044         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6045                 struct drm_i915_private *dev_priv = dev->dev_private;
6046
6047                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6048                 I915_WRITE(CHV_CANVAS(pipe), 0);
6049         }
6050
6051         i9xx_set_pipeconf(intel_crtc);
6052
6053         intel_crtc->active = true;
6054
6055         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6056
6057         for_each_encoder_on_crtc(dev, crtc, encoder)
6058                 if (encoder->pre_pll_enable)
6059                         encoder->pre_pll_enable(encoder);
6060
6061         if (IS_CHERRYVIEW(dev)) {
6062                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6063                 chv_enable_pll(intel_crtc, intel_crtc->config);
6064         } else {
6065                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6066                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6067         }
6068
6069         for_each_encoder_on_crtc(dev, crtc, encoder)
6070                 if (encoder->pre_enable)
6071                         encoder->pre_enable(encoder);
6072
6073         i9xx_pfit_enable(intel_crtc);
6074
6075         intel_color_load_luts(&pipe_config->base);
6076
6077         intel_update_watermarks(crtc);
6078         intel_enable_pipe(intel_crtc);
6079
6080         assert_vblank_disabled(crtc);
6081         drm_crtc_vblank_on(crtc);
6082
6083         for_each_encoder_on_crtc(dev, crtc, encoder)
6084                 encoder->enable(encoder);
6085 }
6086
6087 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6088 {
6089         struct drm_device *dev = crtc->base.dev;
6090         struct drm_i915_private *dev_priv = dev->dev_private;
6091
6092         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6093         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6094 }
6095
6096 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6097 {
6098         struct drm_device *dev = crtc->dev;
6099         struct drm_i915_private *dev_priv = to_i915(dev);
6100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6101         struct intel_encoder *encoder;
6102         struct intel_crtc_state *pipe_config =
6103                 to_intel_crtc_state(crtc->state);
6104         enum pipe pipe = intel_crtc->pipe;
6105
6106         if (WARN_ON(intel_crtc->active))
6107                 return;
6108
6109         i9xx_set_pll_dividers(intel_crtc);
6110
6111         if (intel_crtc->config->has_dp_encoder)
6112                 intel_dp_set_m_n(intel_crtc, M1_N1);
6113
6114         intel_set_pipe_timings(intel_crtc);
6115         intel_set_pipe_src_size(intel_crtc);
6116
6117         i9xx_set_pipeconf(intel_crtc);
6118
6119         intel_crtc->active = true;
6120
6121         if (!IS_GEN2(dev))
6122                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6123
6124         for_each_encoder_on_crtc(dev, crtc, encoder)
6125                 if (encoder->pre_enable)
6126                         encoder->pre_enable(encoder);
6127
6128         i9xx_enable_pll(intel_crtc);
6129
6130         i9xx_pfit_enable(intel_crtc);
6131
6132         intel_color_load_luts(&pipe_config->base);
6133
6134         intel_update_watermarks(crtc);
6135         intel_enable_pipe(intel_crtc);
6136
6137         assert_vblank_disabled(crtc);
6138         drm_crtc_vblank_on(crtc);
6139
6140         for_each_encoder_on_crtc(dev, crtc, encoder)
6141                 encoder->enable(encoder);
6142 }
6143
6144 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6145 {
6146         struct drm_device *dev = crtc->base.dev;
6147         struct drm_i915_private *dev_priv = dev->dev_private;
6148
6149         if (!crtc->config->gmch_pfit.control)
6150                 return;
6151
6152         assert_pipe_disabled(dev_priv, crtc->pipe);
6153
6154         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6155                          I915_READ(PFIT_CONTROL));
6156         I915_WRITE(PFIT_CONTROL, 0);
6157 }
6158
6159 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6160 {
6161         struct drm_device *dev = crtc->dev;
6162         struct drm_i915_private *dev_priv = dev->dev_private;
6163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6164         struct intel_encoder *encoder;
6165         int pipe = intel_crtc->pipe;
6166
6167         /*
6168          * On gen2 planes are double buffered but the pipe isn't, so we must
6169          * wait for planes to fully turn off before disabling the pipe.
6170          */
6171         if (IS_GEN2(dev))
6172                 intel_wait_for_vblank(dev, pipe);
6173
6174         for_each_encoder_on_crtc(dev, crtc, encoder)
6175                 encoder->disable(encoder);
6176
6177         drm_crtc_vblank_off(crtc);
6178         assert_vblank_disabled(crtc);
6179
6180         intel_disable_pipe(intel_crtc);
6181
6182         i9xx_pfit_disable(intel_crtc);
6183
6184         for_each_encoder_on_crtc(dev, crtc, encoder)
6185                 if (encoder->post_disable)
6186                         encoder->post_disable(encoder);
6187
6188         if (!intel_crtc->config->has_dsi_encoder) {
6189                 if (IS_CHERRYVIEW(dev))
6190                         chv_disable_pll(dev_priv, pipe);
6191                 else if (IS_VALLEYVIEW(dev))
6192                         vlv_disable_pll(dev_priv, pipe);
6193                 else
6194                         i9xx_disable_pll(intel_crtc);
6195         }
6196
6197         for_each_encoder_on_crtc(dev, crtc, encoder)
6198                 if (encoder->post_pll_disable)
6199                         encoder->post_pll_disable(encoder);
6200
6201         if (!IS_GEN2(dev))
6202                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6203 }
6204
6205 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6206 {
6207         struct intel_encoder *encoder;
6208         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6209         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6210         enum intel_display_power_domain domain;
6211         unsigned long domains;
6212
6213         if (!intel_crtc->active)
6214                 return;
6215
6216         if (to_intel_plane_state(crtc->primary->state)->visible) {
6217                 WARN_ON(list_empty(&intel_crtc->flip_work));
6218
6219                 intel_pre_disable_primary_noatomic(crtc);
6220
6221                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6222                 to_intel_plane_state(crtc->primary->state)->visible = false;
6223         }
6224
6225         dev_priv->display.crtc_disable(crtc);
6226
6227         DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6228                       crtc->base.id);
6229
6230         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6231         crtc->state->active = false;
6232         intel_crtc->active = false;
6233         crtc->enabled = false;
6234         crtc->state->connector_mask = 0;
6235         crtc->state->encoder_mask = 0;
6236
6237         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6238                 encoder->base.crtc = NULL;
6239
6240         intel_fbc_disable(intel_crtc);
6241         intel_update_watermarks(crtc);
6242         intel_disable_shared_dpll(intel_crtc);
6243
6244         domains = intel_crtc->enabled_power_domains;
6245         for_each_power_domain(domain, domains)
6246                 intel_display_power_put(dev_priv, domain);
6247         intel_crtc->enabled_power_domains = 0;
6248
6249         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6250         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6251 }
6252
6253 /*
6254  * turn all crtc's off, but do not adjust state
6255  * This has to be paired with a call to intel_modeset_setup_hw_state.
6256  */
6257 int intel_display_suspend(struct drm_device *dev)
6258 {
6259         struct drm_i915_private *dev_priv = to_i915(dev);
6260         struct drm_atomic_state *state;
6261         int ret;
6262
6263         state = drm_atomic_helper_suspend(dev);
6264         ret = PTR_ERR_OR_ZERO(state);
6265         if (ret)
6266                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6267         else
6268                 dev_priv->modeset_restore_state = state;
6269
6270         /*
6271          * Make sure all unpin_work completes before returning.
6272          */
6273         flush_workqueue(dev_priv->wq);
6274
6275         return ret;
6276 }
6277
6278 void intel_encoder_destroy(struct drm_encoder *encoder)
6279 {
6280         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6281
6282         drm_encoder_cleanup(encoder);
6283         kfree(intel_encoder);
6284 }
6285
6286 /* Cross check the actual hw state with our own modeset state tracking (and it's
6287  * internal consistency). */
6288 static void intel_connector_verify_state(struct intel_connector *connector,
6289                                          struct drm_connector_state *conn_state)
6290 {
6291         struct drm_crtc *crtc = conn_state->crtc;
6292
6293         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6294                       connector->base.base.id,
6295                       connector->base.name);
6296
6297         if (connector->get_hw_state(connector)) {
6298                 struct intel_encoder *encoder = connector->encoder;
6299
6300                 I915_STATE_WARN(!crtc,
6301                          "connector enabled without attached crtc\n");
6302
6303                 if (!crtc)
6304                         return;
6305
6306                 I915_STATE_WARN(!crtc->state->active,
6307                       "connector is active, but attached crtc isn't\n");
6308
6309                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6310                         return;
6311
6312                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6313                         "atomic encoder doesn't match attached encoder\n");
6314
6315                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6316                         "attached encoder crtc differs from connector crtc\n");
6317         } else {
6318                 I915_STATE_WARN(crtc && crtc->state->active,
6319                         "attached crtc is active, but connector isn't\n");
6320                 I915_STATE_WARN(!crtc && conn_state->best_encoder,
6321                         "best encoder set without crtc!\n");
6322         }
6323 }
6324
6325 int intel_connector_init(struct intel_connector *connector)
6326 {
6327         drm_atomic_helper_connector_reset(&connector->base);
6328
6329         if (!connector->base.state)
6330                 return -ENOMEM;
6331
6332         return 0;
6333 }
6334
6335 struct intel_connector *intel_connector_alloc(void)
6336 {
6337         struct intel_connector *connector;
6338
6339         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6340         if (!connector)
6341                 return NULL;
6342
6343         if (intel_connector_init(connector) < 0) {
6344                 kfree(connector);
6345                 return NULL;
6346         }
6347
6348         return connector;
6349 }
6350
6351 /* Simple connector->get_hw_state implementation for encoders that support only
6352  * one connector and no cloning and hence the encoder state determines the state
6353  * of the connector. */
6354 bool intel_connector_get_hw_state(struct intel_connector *connector)
6355 {
6356         enum pipe pipe = 0;
6357         struct intel_encoder *encoder = connector->encoder;
6358
6359         return encoder->get_hw_state(encoder, &pipe);
6360 }
6361
6362 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6363 {
6364         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6365                 return crtc_state->fdi_lanes;
6366
6367         return 0;
6368 }
6369
6370 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6371                                      struct intel_crtc_state *pipe_config)
6372 {
6373         struct drm_atomic_state *state = pipe_config->base.state;
6374         struct intel_crtc *other_crtc;
6375         struct intel_crtc_state *other_crtc_state;
6376
6377         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6378                       pipe_name(pipe), pipe_config->fdi_lanes);
6379         if (pipe_config->fdi_lanes > 4) {
6380                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6381                               pipe_name(pipe), pipe_config->fdi_lanes);
6382                 return -EINVAL;
6383         }
6384
6385         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6386                 if (pipe_config->fdi_lanes > 2) {
6387                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6388                                       pipe_config->fdi_lanes);
6389                         return -EINVAL;
6390                 } else {
6391                         return 0;
6392                 }
6393         }
6394
6395         if (INTEL_INFO(dev)->num_pipes == 2)
6396                 return 0;
6397
6398         /* Ivybridge 3 pipe is really complicated */
6399         switch (pipe) {
6400         case PIPE_A:
6401                 return 0;
6402         case PIPE_B:
6403                 if (pipe_config->fdi_lanes <= 2)
6404                         return 0;
6405
6406                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6407                 other_crtc_state =
6408                         intel_atomic_get_crtc_state(state, other_crtc);
6409                 if (IS_ERR(other_crtc_state))
6410                         return PTR_ERR(other_crtc_state);
6411
6412                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6413                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6414                                       pipe_name(pipe), pipe_config->fdi_lanes);
6415                         return -EINVAL;
6416                 }
6417                 return 0;
6418         case PIPE_C:
6419                 if (pipe_config->fdi_lanes > 2) {
6420                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6421                                       pipe_name(pipe), pipe_config->fdi_lanes);
6422                         return -EINVAL;
6423                 }
6424
6425                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6426                 other_crtc_state =
6427                         intel_atomic_get_crtc_state(state, other_crtc);
6428                 if (IS_ERR(other_crtc_state))
6429                         return PTR_ERR(other_crtc_state);
6430
6431                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6432                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6433                         return -EINVAL;
6434                 }
6435                 return 0;
6436         default:
6437                 BUG();
6438         }
6439 }
6440
6441 #define RETRY 1
6442 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6443                                        struct intel_crtc_state *pipe_config)
6444 {
6445         struct drm_device *dev = intel_crtc->base.dev;
6446         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6447         int lane, link_bw, fdi_dotclock, ret;
6448         bool needs_recompute = false;
6449
6450 retry:
6451         /* FDI is a binary signal running at ~2.7GHz, encoding
6452          * each output octet as 10 bits. The actual frequency
6453          * is stored as a divider into a 100MHz clock, and the
6454          * mode pixel clock is stored in units of 1KHz.
6455          * Hence the bw of each lane in terms of the mode signal
6456          * is:
6457          */
6458         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6459
6460         fdi_dotclock = adjusted_mode->crtc_clock;
6461
6462         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6463                                            pipe_config->pipe_bpp);
6464
6465         pipe_config->fdi_lanes = lane;
6466
6467         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6468                                link_bw, &pipe_config->fdi_m_n);
6469
6470         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6471         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6472                 pipe_config->pipe_bpp -= 2*3;
6473                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6474                               pipe_config->pipe_bpp);
6475                 needs_recompute = true;
6476                 pipe_config->bw_constrained = true;
6477
6478                 goto retry;
6479         }
6480
6481         if (needs_recompute)
6482                 return RETRY;
6483
6484         return ret;
6485 }
6486
6487 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6488                                      struct intel_crtc_state *pipe_config)
6489 {
6490         if (pipe_config->pipe_bpp > 24)
6491                 return false;
6492
6493         /* HSW can handle pixel rate up to cdclk? */
6494         if (IS_HASWELL(dev_priv))
6495                 return true;
6496
6497         /*
6498          * We compare against max which means we must take
6499          * the increased cdclk requirement into account when
6500          * calculating the new cdclk.
6501          *
6502          * Should measure whether using a lower cdclk w/o IPS
6503          */
6504         return ilk_pipe_pixel_rate(pipe_config) <=
6505                 dev_priv->max_cdclk_freq * 95 / 100;
6506 }
6507
6508 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6509                                    struct intel_crtc_state *pipe_config)
6510 {
6511         struct drm_device *dev = crtc->base.dev;
6512         struct drm_i915_private *dev_priv = dev->dev_private;
6513
6514         pipe_config->ips_enabled = i915.enable_ips &&
6515                 hsw_crtc_supports_ips(crtc) &&
6516                 pipe_config_supports_ips(dev_priv, pipe_config);
6517 }
6518
6519 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6520 {
6521         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6522
6523         /* GDG double wide on either pipe, otherwise pipe A only */
6524         return INTEL_INFO(dev_priv)->gen < 4 &&
6525                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6526 }
6527
6528 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6529                                      struct intel_crtc_state *pipe_config)
6530 {
6531         struct drm_device *dev = crtc->base.dev;
6532         struct drm_i915_private *dev_priv = dev->dev_private;
6533         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6534
6535         /* FIXME should check pixel clock limits on all platforms */
6536         if (INTEL_INFO(dev)->gen < 4) {
6537                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6538
6539                 /*
6540                  * Enable double wide mode when the dot clock
6541                  * is > 90% of the (display) core speed.
6542                  */
6543                 if (intel_crtc_supports_double_wide(crtc) &&
6544                     adjusted_mode->crtc_clock > clock_limit) {
6545                         clock_limit *= 2;
6546                         pipe_config->double_wide = true;
6547                 }
6548
6549                 if (adjusted_mode->crtc_clock > clock_limit) {
6550                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6551                                       adjusted_mode->crtc_clock, clock_limit,
6552                                       yesno(pipe_config->double_wide));
6553                         return -EINVAL;
6554                 }
6555         }
6556
6557         /*
6558          * Pipe horizontal size must be even in:
6559          * - DVO ganged mode
6560          * - LVDS dual channel mode
6561          * - Double wide pipe
6562          */
6563         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6564              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6565                 pipe_config->pipe_src_w &= ~1;
6566
6567         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6568          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6569          */
6570         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6571                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6572                 return -EINVAL;
6573
6574         if (HAS_IPS(dev))
6575                 hsw_compute_ips_config(crtc, pipe_config);
6576
6577         if (pipe_config->has_pch_encoder)
6578                 return ironlake_fdi_compute_config(crtc, pipe_config);
6579
6580         return 0;
6581 }
6582
6583 static int skylake_get_display_clock_speed(struct drm_device *dev)
6584 {
6585         struct drm_i915_private *dev_priv = to_i915(dev);
6586         uint32_t cdctl;
6587
6588         skl_dpll0_update(dev_priv);
6589
6590         if (dev_priv->cdclk_pll.vco == 0)
6591                 return dev_priv->cdclk_pll.ref;
6592
6593         cdctl = I915_READ(CDCLK_CTL);
6594
6595         if (dev_priv->cdclk_pll.vco == 8640000) {
6596                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6597                 case CDCLK_FREQ_450_432:
6598                         return 432000;
6599                 case CDCLK_FREQ_337_308:
6600                         return 308571;
6601                 case CDCLK_FREQ_540:
6602                         return 540000;
6603                 case CDCLK_FREQ_675_617:
6604                         return 617143;
6605                 default:
6606                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6607                 }
6608         } else {
6609                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6610                 case CDCLK_FREQ_450_432:
6611                         return 450000;
6612                 case CDCLK_FREQ_337_308:
6613                         return 337500;
6614                 case CDCLK_FREQ_540:
6615                         return 540000;
6616                 case CDCLK_FREQ_675_617:
6617                         return 675000;
6618                 default:
6619                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6620                 }
6621         }
6622
6623         return dev_priv->cdclk_pll.ref;
6624 }
6625
6626 static int broxton_get_display_clock_speed(struct drm_device *dev)
6627 {
6628         struct drm_i915_private *dev_priv = to_i915(dev);
6629         uint32_t cdctl = I915_READ(CDCLK_CTL);
6630         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6631         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6632         int cdclk;
6633
6634         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6635                 return 19200;
6636
6637         cdclk = 19200 * pll_ratio / 2;
6638
6639         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6640         case BXT_CDCLK_CD2X_DIV_SEL_1:
6641                 return cdclk;  /* 576MHz or 624MHz */
6642         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6643                 return cdclk * 2 / 3; /* 384MHz */
6644         case BXT_CDCLK_CD2X_DIV_SEL_2:
6645                 return cdclk / 2; /* 288MHz */
6646         case BXT_CDCLK_CD2X_DIV_SEL_4:
6647                 return cdclk / 4; /* 144MHz */
6648         }
6649
6650         /* error case, do as if DE PLL isn't enabled */
6651         return 19200;
6652 }
6653
6654 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6655 {
6656         struct drm_i915_private *dev_priv = dev->dev_private;
6657         uint32_t lcpll = I915_READ(LCPLL_CTL);
6658         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6659
6660         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6661                 return 800000;
6662         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6663                 return 450000;
6664         else if (freq == LCPLL_CLK_FREQ_450)
6665                 return 450000;
6666         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6667                 return 540000;
6668         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6669                 return 337500;
6670         else
6671                 return 675000;
6672 }
6673
6674 static int haswell_get_display_clock_speed(struct drm_device *dev)
6675 {
6676         struct drm_i915_private *dev_priv = dev->dev_private;
6677         uint32_t lcpll = I915_READ(LCPLL_CTL);
6678         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6679
6680         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6681                 return 800000;
6682         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6683                 return 450000;
6684         else if (freq == LCPLL_CLK_FREQ_450)
6685                 return 450000;
6686         else if (IS_HSW_ULT(dev))
6687                 return 337500;
6688         else
6689                 return 540000;
6690 }
6691
6692 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6693 {
6694         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6695                                       CCK_DISPLAY_CLOCK_CONTROL);
6696 }
6697
6698 static int ilk_get_display_clock_speed(struct drm_device *dev)
6699 {
6700         return 450000;
6701 }
6702
6703 static int i945_get_display_clock_speed(struct drm_device *dev)
6704 {
6705         return 400000;
6706 }
6707
6708 static int i915_get_display_clock_speed(struct drm_device *dev)
6709 {
6710         return 333333;
6711 }
6712
6713 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6714 {
6715         return 200000;
6716 }
6717
6718 static int pnv_get_display_clock_speed(struct drm_device *dev)
6719 {
6720         u16 gcfgc = 0;
6721
6722         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6723
6724         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6725         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6726                 return 266667;
6727         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6728                 return 333333;
6729         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6730                 return 444444;
6731         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6732                 return 200000;
6733         default:
6734                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6735         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6736                 return 133333;
6737         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6738                 return 166667;
6739         }
6740 }
6741
6742 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6743 {
6744         u16 gcfgc = 0;
6745
6746         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6747
6748         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6749                 return 133333;
6750         else {
6751                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6752                 case GC_DISPLAY_CLOCK_333_MHZ:
6753                         return 333333;
6754                 default:
6755                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6756                         return 190000;
6757                 }
6758         }
6759 }
6760
6761 static int i865_get_display_clock_speed(struct drm_device *dev)
6762 {
6763         return 266667;
6764 }
6765
6766 static int i85x_get_display_clock_speed(struct drm_device *dev)
6767 {
6768         u16 hpllcc = 0;
6769
6770         /*
6771          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6772          * encoding is different :(
6773          * FIXME is this the right way to detect 852GM/852GMV?
6774          */
6775         if (dev->pdev->revision == 0x1)
6776                 return 133333;
6777
6778         pci_bus_read_config_word(dev->pdev->bus,
6779                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6780
6781         /* Assume that the hardware is in the high speed state.  This
6782          * should be the default.
6783          */
6784         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6785         case GC_CLOCK_133_200:
6786         case GC_CLOCK_133_200_2:
6787         case GC_CLOCK_100_200:
6788                 return 200000;
6789         case GC_CLOCK_166_250:
6790                 return 250000;
6791         case GC_CLOCK_100_133:
6792                 return 133333;
6793         case GC_CLOCK_133_266:
6794         case GC_CLOCK_133_266_2:
6795         case GC_CLOCK_166_266:
6796                 return 266667;
6797         }
6798
6799         /* Shouldn't happen */
6800         return 0;
6801 }
6802
6803 static int i830_get_display_clock_speed(struct drm_device *dev)
6804 {
6805         return 133333;
6806 }
6807
6808 static unsigned int intel_hpll_vco(struct drm_device *dev)
6809 {
6810         struct drm_i915_private *dev_priv = dev->dev_private;
6811         static const unsigned int blb_vco[8] = {
6812                 [0] = 3200000,
6813                 [1] = 4000000,
6814                 [2] = 5333333,
6815                 [3] = 4800000,
6816                 [4] = 6400000,
6817         };
6818         static const unsigned int pnv_vco[8] = {
6819                 [0] = 3200000,
6820                 [1] = 4000000,
6821                 [2] = 5333333,
6822                 [3] = 4800000,
6823                 [4] = 2666667,
6824         };
6825         static const unsigned int cl_vco[8] = {
6826                 [0] = 3200000,
6827                 [1] = 4000000,
6828                 [2] = 5333333,
6829                 [3] = 6400000,
6830                 [4] = 3333333,
6831                 [5] = 3566667,
6832                 [6] = 4266667,
6833         };
6834         static const unsigned int elk_vco[8] = {
6835                 [0] = 3200000,
6836                 [1] = 4000000,
6837                 [2] = 5333333,
6838                 [3] = 4800000,
6839         };
6840         static const unsigned int ctg_vco[8] = {
6841                 [0] = 3200000,
6842                 [1] = 4000000,
6843                 [2] = 5333333,
6844                 [3] = 6400000,
6845                 [4] = 2666667,
6846                 [5] = 4266667,
6847         };
6848         const unsigned int *vco_table;
6849         unsigned int vco;
6850         uint8_t tmp = 0;
6851
6852         /* FIXME other chipsets? */
6853         if (IS_GM45(dev))
6854                 vco_table = ctg_vco;
6855         else if (IS_G4X(dev))
6856                 vco_table = elk_vco;
6857         else if (IS_CRESTLINE(dev))
6858                 vco_table = cl_vco;
6859         else if (IS_PINEVIEW(dev))
6860                 vco_table = pnv_vco;
6861         else if (IS_G33(dev))
6862                 vco_table = blb_vco;
6863         else
6864                 return 0;
6865
6866         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6867
6868         vco = vco_table[tmp & 0x7];
6869         if (vco == 0)
6870                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6871         else
6872                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6873
6874         return vco;
6875 }
6876
6877 static int gm45_get_display_clock_speed(struct drm_device *dev)
6878 {
6879         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6880         uint16_t tmp = 0;
6881
6882         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6883
6884         cdclk_sel = (tmp >> 12) & 0x1;
6885
6886         switch (vco) {
6887         case 2666667:
6888         case 4000000:
6889         case 5333333:
6890                 return cdclk_sel ? 333333 : 222222;
6891         case 3200000:
6892                 return cdclk_sel ? 320000 : 228571;
6893         default:
6894                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6895                 return 222222;
6896         }
6897 }
6898
6899 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6900 {
6901         static const uint8_t div_3200[] = { 16, 10,  8 };
6902         static const uint8_t div_4000[] = { 20, 12, 10 };
6903         static const uint8_t div_5333[] = { 24, 16, 14 };
6904         const uint8_t *div_table;
6905         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6906         uint16_t tmp = 0;
6907
6908         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6909
6910         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6911
6912         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6913                 goto fail;
6914
6915         switch (vco) {
6916         case 3200000:
6917                 div_table = div_3200;
6918                 break;
6919         case 4000000:
6920                 div_table = div_4000;
6921                 break;
6922         case 5333333:
6923                 div_table = div_5333;
6924                 break;
6925         default:
6926                 goto fail;
6927         }
6928
6929         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6930
6931 fail:
6932         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6933         return 200000;
6934 }
6935
6936 static int g33_get_display_clock_speed(struct drm_device *dev)
6937 {
6938         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6939         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6940         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6941         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6942         const uint8_t *div_table;
6943         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6944         uint16_t tmp = 0;
6945
6946         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6947
6948         cdclk_sel = (tmp >> 4) & 0x7;
6949
6950         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6951                 goto fail;
6952
6953         switch (vco) {
6954         case 3200000:
6955                 div_table = div_3200;
6956                 break;
6957         case 4000000:
6958                 div_table = div_4000;
6959                 break;
6960         case 4800000:
6961                 div_table = div_4800;
6962                 break;
6963         case 5333333:
6964                 div_table = div_5333;
6965                 break;
6966         default:
6967                 goto fail;
6968         }
6969
6970         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6971
6972 fail:
6973         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6974         return 190476;
6975 }
6976
6977 static void
6978 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6979 {
6980         while (*num > DATA_LINK_M_N_MASK ||
6981                *den > DATA_LINK_M_N_MASK) {
6982                 *num >>= 1;
6983                 *den >>= 1;
6984         }
6985 }
6986
6987 static void compute_m_n(unsigned int m, unsigned int n,
6988                         uint32_t *ret_m, uint32_t *ret_n)
6989 {
6990         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6991         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6992         intel_reduce_m_n_ratio(ret_m, ret_n);
6993 }
6994
6995 void
6996 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6997                        int pixel_clock, int link_clock,
6998                        struct intel_link_m_n *m_n)
6999 {
7000         m_n->tu = 64;
7001
7002         compute_m_n(bits_per_pixel * pixel_clock,
7003                     link_clock * nlanes * 8,
7004                     &m_n->gmch_m, &m_n->gmch_n);
7005
7006         compute_m_n(pixel_clock, link_clock,
7007                     &m_n->link_m, &m_n->link_n);
7008 }
7009
7010 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7011 {
7012         if (i915.panel_use_ssc >= 0)
7013                 return i915.panel_use_ssc != 0;
7014         return dev_priv->vbt.lvds_use_ssc
7015                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7016 }
7017
7018 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7019 {
7020         return (1 << dpll->n) << 16 | dpll->m2;
7021 }
7022
7023 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7024 {
7025         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7026 }
7027
7028 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7029                                      struct intel_crtc_state *crtc_state,
7030                                      struct dpll *reduced_clock)
7031 {
7032         struct drm_device *dev = crtc->base.dev;
7033         u32 fp, fp2 = 0;
7034
7035         if (IS_PINEVIEW(dev)) {
7036                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7037                 if (reduced_clock)
7038                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7039         } else {
7040                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7041                 if (reduced_clock)
7042                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7043         }
7044
7045         crtc_state->dpll_hw_state.fp0 = fp;
7046
7047         crtc->lowfreq_avail = false;
7048         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7049             reduced_clock) {
7050                 crtc_state->dpll_hw_state.fp1 = fp2;
7051                 crtc->lowfreq_avail = true;
7052         } else {
7053                 crtc_state->dpll_hw_state.fp1 = fp;
7054         }
7055 }
7056
7057 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7058                 pipe)
7059 {
7060         u32 reg_val;
7061
7062         /*
7063          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7064          * and set it to a reasonable value instead.
7065          */
7066         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7067         reg_val &= 0xffffff00;
7068         reg_val |= 0x00000030;
7069         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7070
7071         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7072         reg_val &= 0x8cffffff;
7073         reg_val = 0x8c000000;
7074         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7075
7076         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7077         reg_val &= 0xffffff00;
7078         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7079
7080         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7081         reg_val &= 0x00ffffff;
7082         reg_val |= 0xb0000000;
7083         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7084 }
7085
7086 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7087                                          struct intel_link_m_n *m_n)
7088 {
7089         struct drm_device *dev = crtc->base.dev;
7090         struct drm_i915_private *dev_priv = dev->dev_private;
7091         int pipe = crtc->pipe;
7092
7093         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7094         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7095         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7096         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7097 }
7098
7099 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7100                                          struct intel_link_m_n *m_n,
7101                                          struct intel_link_m_n *m2_n2)
7102 {
7103         struct drm_device *dev = crtc->base.dev;
7104         struct drm_i915_private *dev_priv = dev->dev_private;
7105         int pipe = crtc->pipe;
7106         enum transcoder transcoder = crtc->config->cpu_transcoder;
7107
7108         if (INTEL_INFO(dev)->gen >= 5) {
7109                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7110                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7111                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7112                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7113                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7114                  * for gen < 8) and if DRRS is supported (to make sure the
7115                  * registers are not unnecessarily accessed).
7116                  */
7117                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7118                         crtc->config->has_drrs) {
7119                         I915_WRITE(PIPE_DATA_M2(transcoder),
7120                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7121                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7122                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7123                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7124                 }
7125         } else {
7126                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7127                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7128                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7129                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7130         }
7131 }
7132
7133 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7134 {
7135         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7136
7137         if (m_n == M1_N1) {
7138                 dp_m_n = &crtc->config->dp_m_n;
7139                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7140         } else if (m_n == M2_N2) {
7141
7142                 /*
7143                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7144                  * needs to be programmed into M1_N1.
7145                  */
7146                 dp_m_n = &crtc->config->dp_m2_n2;
7147         } else {
7148                 DRM_ERROR("Unsupported divider value\n");
7149                 return;
7150         }
7151
7152         if (crtc->config->has_pch_encoder)
7153                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7154         else
7155                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7156 }
7157
7158 static void vlv_compute_dpll(struct intel_crtc *crtc,
7159                              struct intel_crtc_state *pipe_config)
7160 {
7161         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7162                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7163         if (crtc->pipe != PIPE_A)
7164                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7165
7166         /* DPLL not used with DSI, but still need the rest set up */
7167         if (!pipe_config->has_dsi_encoder)
7168                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7169                         DPLL_EXT_BUFFER_ENABLE_VLV;
7170
7171         pipe_config->dpll_hw_state.dpll_md =
7172                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7173 }
7174
7175 static void chv_compute_dpll(struct intel_crtc *crtc,
7176                              struct intel_crtc_state *pipe_config)
7177 {
7178         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7179                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7180         if (crtc->pipe != PIPE_A)
7181                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7182
7183         /* DPLL not used with DSI, but still need the rest set up */
7184         if (!pipe_config->has_dsi_encoder)
7185                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7186
7187         pipe_config->dpll_hw_state.dpll_md =
7188                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7189 }
7190
7191 static void vlv_prepare_pll(struct intel_crtc *crtc,
7192                             const struct intel_crtc_state *pipe_config)
7193 {
7194         struct drm_device *dev = crtc->base.dev;
7195         struct drm_i915_private *dev_priv = dev->dev_private;
7196         enum pipe pipe = crtc->pipe;
7197         u32 mdiv;
7198         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7199         u32 coreclk, reg_val;
7200
7201         /* Enable Refclk */
7202         I915_WRITE(DPLL(pipe),
7203                    pipe_config->dpll_hw_state.dpll &
7204                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7205
7206         /* No need to actually set up the DPLL with DSI */
7207         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7208                 return;
7209
7210         mutex_lock(&dev_priv->sb_lock);
7211
7212         bestn = pipe_config->dpll.n;
7213         bestm1 = pipe_config->dpll.m1;
7214         bestm2 = pipe_config->dpll.m2;
7215         bestp1 = pipe_config->dpll.p1;
7216         bestp2 = pipe_config->dpll.p2;
7217
7218         /* See eDP HDMI DPIO driver vbios notes doc */
7219
7220         /* PLL B needs special handling */
7221         if (pipe == PIPE_B)
7222                 vlv_pllb_recal_opamp(dev_priv, pipe);
7223
7224         /* Set up Tx target for periodic Rcomp update */
7225         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7226
7227         /* Disable target IRef on PLL */
7228         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7229         reg_val &= 0x00ffffff;
7230         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7231
7232         /* Disable fast lock */
7233         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7234
7235         /* Set idtafcrecal before PLL is enabled */
7236         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7237         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7238         mdiv |= ((bestn << DPIO_N_SHIFT));
7239         mdiv |= (1 << DPIO_K_SHIFT);
7240
7241         /*
7242          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7243          * but we don't support that).
7244          * Note: don't use the DAC post divider as it seems unstable.
7245          */
7246         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7247         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7248
7249         mdiv |= DPIO_ENABLE_CALIBRATION;
7250         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7251
7252         /* Set HBR and RBR LPF coefficients */
7253         if (pipe_config->port_clock == 162000 ||
7254             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7255             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7256                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7257                                  0x009f0003);
7258         else
7259                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7260                                  0x00d0000f);
7261
7262         if (pipe_config->has_dp_encoder) {
7263                 /* Use SSC source */
7264                 if (pipe == PIPE_A)
7265                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7266                                          0x0df40000);
7267                 else
7268                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7269                                          0x0df70000);
7270         } else { /* HDMI or VGA */
7271                 /* Use bend source */
7272                 if (pipe == PIPE_A)
7273                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7274                                          0x0df70000);
7275                 else
7276                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7277                                          0x0df40000);
7278         }
7279
7280         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7281         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7282         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7283             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7284                 coreclk |= 0x01000000;
7285         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7286
7287         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7288         mutex_unlock(&dev_priv->sb_lock);
7289 }
7290
7291 static void chv_prepare_pll(struct intel_crtc *crtc,
7292                             const struct intel_crtc_state *pipe_config)
7293 {
7294         struct drm_device *dev = crtc->base.dev;
7295         struct drm_i915_private *dev_priv = dev->dev_private;
7296         enum pipe pipe = crtc->pipe;
7297         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7298         u32 loopfilter, tribuf_calcntr;
7299         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7300         u32 dpio_val;
7301         int vco;
7302
7303         /* Enable Refclk and SSC */
7304         I915_WRITE(DPLL(pipe),
7305                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7306
7307         /* No need to actually set up the DPLL with DSI */
7308         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7309                 return;
7310
7311         bestn = pipe_config->dpll.n;
7312         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7313         bestm1 = pipe_config->dpll.m1;
7314         bestm2 = pipe_config->dpll.m2 >> 22;
7315         bestp1 = pipe_config->dpll.p1;
7316         bestp2 = pipe_config->dpll.p2;
7317         vco = pipe_config->dpll.vco;
7318         dpio_val = 0;
7319         loopfilter = 0;
7320
7321         mutex_lock(&dev_priv->sb_lock);
7322
7323         /* p1 and p2 divider */
7324         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7325                         5 << DPIO_CHV_S1_DIV_SHIFT |
7326                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7327                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7328                         1 << DPIO_CHV_K_DIV_SHIFT);
7329
7330         /* Feedback post-divider - m2 */
7331         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7332
7333         /* Feedback refclk divider - n and m1 */
7334         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7335                         DPIO_CHV_M1_DIV_BY_2 |
7336                         1 << DPIO_CHV_N_DIV_SHIFT);
7337
7338         /* M2 fraction division */
7339         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7340
7341         /* M2 fraction division enable */
7342         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7343         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7344         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7345         if (bestm2_frac)
7346                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7347         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7348
7349         /* Program digital lock detect threshold */
7350         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7351         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7352                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7353         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7354         if (!bestm2_frac)
7355                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7356         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7357
7358         /* Loop filter */
7359         if (vco == 5400000) {
7360                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7361                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7362                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7363                 tribuf_calcntr = 0x9;
7364         } else if (vco <= 6200000) {
7365                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7366                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7367                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7368                 tribuf_calcntr = 0x9;
7369         } else if (vco <= 6480000) {
7370                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7371                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7372                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7373                 tribuf_calcntr = 0x8;
7374         } else {
7375                 /* Not supported. Apply the same limits as in the max case */
7376                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7377                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7378                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7379                 tribuf_calcntr = 0;
7380         }
7381         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7382
7383         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7384         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7385         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7386         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7387
7388         /* AFC Recal */
7389         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7390                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7391                         DPIO_AFC_RECAL);
7392
7393         mutex_unlock(&dev_priv->sb_lock);
7394 }
7395
7396 /**
7397  * vlv_force_pll_on - forcibly enable just the PLL
7398  * @dev_priv: i915 private structure
7399  * @pipe: pipe PLL to enable
7400  * @dpll: PLL configuration
7401  *
7402  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7403  * in cases where we need the PLL enabled even when @pipe is not going to
7404  * be enabled.
7405  */
7406 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7407                      const struct dpll *dpll)
7408 {
7409         struct intel_crtc *crtc =
7410                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7411         struct intel_crtc_state *pipe_config;
7412
7413         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7414         if (!pipe_config)
7415                 return -ENOMEM;
7416
7417         pipe_config->base.crtc = &crtc->base;
7418         pipe_config->pixel_multiplier = 1;
7419         pipe_config->dpll = *dpll;
7420
7421         if (IS_CHERRYVIEW(dev)) {
7422                 chv_compute_dpll(crtc, pipe_config);
7423                 chv_prepare_pll(crtc, pipe_config);
7424                 chv_enable_pll(crtc, pipe_config);
7425         } else {
7426                 vlv_compute_dpll(crtc, pipe_config);
7427                 vlv_prepare_pll(crtc, pipe_config);
7428                 vlv_enable_pll(crtc, pipe_config);
7429         }
7430
7431         kfree(pipe_config);
7432
7433         return 0;
7434 }
7435
7436 /**
7437  * vlv_force_pll_off - forcibly disable just the PLL
7438  * @dev_priv: i915 private structure
7439  * @pipe: pipe PLL to disable
7440  *
7441  * Disable the PLL for @pipe. To be used in cases where we need
7442  * the PLL enabled even when @pipe is not going to be enabled.
7443  */
7444 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7445 {
7446         if (IS_CHERRYVIEW(dev))
7447                 chv_disable_pll(to_i915(dev), pipe);
7448         else
7449                 vlv_disable_pll(to_i915(dev), pipe);
7450 }
7451
7452 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7453                               struct intel_crtc_state *crtc_state,
7454                               struct dpll *reduced_clock)
7455 {
7456         struct drm_device *dev = crtc->base.dev;
7457         struct drm_i915_private *dev_priv = dev->dev_private;
7458         u32 dpll;
7459         bool is_sdvo;
7460         struct dpll *clock = &crtc_state->dpll;
7461
7462         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7463
7464         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7465                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7466
7467         dpll = DPLL_VGA_MODE_DIS;
7468
7469         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7470                 dpll |= DPLLB_MODE_LVDS;
7471         else
7472                 dpll |= DPLLB_MODE_DAC_SERIAL;
7473
7474         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7475                 dpll |= (crtc_state->pixel_multiplier - 1)
7476                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7477         }
7478
7479         if (is_sdvo)
7480                 dpll |= DPLL_SDVO_HIGH_SPEED;
7481
7482         if (crtc_state->has_dp_encoder)
7483                 dpll |= DPLL_SDVO_HIGH_SPEED;
7484
7485         /* compute bitmask from p1 value */
7486         if (IS_PINEVIEW(dev))
7487                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7488         else {
7489                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7490                 if (IS_G4X(dev) && reduced_clock)
7491                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7492         }
7493         switch (clock->p2) {
7494         case 5:
7495                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7496                 break;
7497         case 7:
7498                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7499                 break;
7500         case 10:
7501                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7502                 break;
7503         case 14:
7504                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7505                 break;
7506         }
7507         if (INTEL_INFO(dev)->gen >= 4)
7508                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7509
7510         if (crtc_state->sdvo_tv_clock)
7511                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7512         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7513                  intel_panel_use_ssc(dev_priv))
7514                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7515         else
7516                 dpll |= PLL_REF_INPUT_DREFCLK;
7517
7518         dpll |= DPLL_VCO_ENABLE;
7519         crtc_state->dpll_hw_state.dpll = dpll;
7520
7521         if (INTEL_INFO(dev)->gen >= 4) {
7522                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7523                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7524                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7525         }
7526 }
7527
7528 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7529                               struct intel_crtc_state *crtc_state,
7530                               struct dpll *reduced_clock)
7531 {
7532         struct drm_device *dev = crtc->base.dev;
7533         struct drm_i915_private *dev_priv = dev->dev_private;
7534         u32 dpll;
7535         struct dpll *clock = &crtc_state->dpll;
7536
7537         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7538
7539         dpll = DPLL_VGA_MODE_DIS;
7540
7541         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7542                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7543         } else {
7544                 if (clock->p1 == 2)
7545                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7546                 else
7547                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7548                 if (clock->p2 == 4)
7549                         dpll |= PLL_P2_DIVIDE_BY_4;
7550         }
7551
7552         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7553                 dpll |= DPLL_DVO_2X_MODE;
7554
7555         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7556             intel_panel_use_ssc(dev_priv))
7557                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7558         else
7559                 dpll |= PLL_REF_INPUT_DREFCLK;
7560
7561         dpll |= DPLL_VCO_ENABLE;
7562         crtc_state->dpll_hw_state.dpll = dpll;
7563 }
7564
7565 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7566 {
7567         struct drm_device *dev = intel_crtc->base.dev;
7568         struct drm_i915_private *dev_priv = dev->dev_private;
7569         enum pipe pipe = intel_crtc->pipe;
7570         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7571         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7572         uint32_t crtc_vtotal, crtc_vblank_end;
7573         int vsyncshift = 0;
7574
7575         /* We need to be careful not to changed the adjusted mode, for otherwise
7576          * the hw state checker will get angry at the mismatch. */
7577         crtc_vtotal = adjusted_mode->crtc_vtotal;
7578         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7579
7580         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7581                 /* the chip adds 2 halflines automatically */
7582                 crtc_vtotal -= 1;
7583                 crtc_vblank_end -= 1;
7584
7585                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7586                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7587                 else
7588                         vsyncshift = adjusted_mode->crtc_hsync_start -
7589                                 adjusted_mode->crtc_htotal / 2;
7590                 if (vsyncshift < 0)
7591                         vsyncshift += adjusted_mode->crtc_htotal;
7592         }
7593
7594         if (INTEL_INFO(dev)->gen > 3)
7595                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7596
7597         I915_WRITE(HTOTAL(cpu_transcoder),
7598                    (adjusted_mode->crtc_hdisplay - 1) |
7599                    ((adjusted_mode->crtc_htotal - 1) << 16));
7600         I915_WRITE(HBLANK(cpu_transcoder),
7601                    (adjusted_mode->crtc_hblank_start - 1) |
7602                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7603         I915_WRITE(HSYNC(cpu_transcoder),
7604                    (adjusted_mode->crtc_hsync_start - 1) |
7605                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7606
7607         I915_WRITE(VTOTAL(cpu_transcoder),
7608                    (adjusted_mode->crtc_vdisplay - 1) |
7609                    ((crtc_vtotal - 1) << 16));
7610         I915_WRITE(VBLANK(cpu_transcoder),
7611                    (adjusted_mode->crtc_vblank_start - 1) |
7612                    ((crtc_vblank_end - 1) << 16));
7613         I915_WRITE(VSYNC(cpu_transcoder),
7614                    (adjusted_mode->crtc_vsync_start - 1) |
7615                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7616
7617         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7618          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7619          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7620          * bits. */
7621         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7622             (pipe == PIPE_B || pipe == PIPE_C))
7623                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7624
7625 }
7626
7627 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7628 {
7629         struct drm_device *dev = intel_crtc->base.dev;
7630         struct drm_i915_private *dev_priv = dev->dev_private;
7631         enum pipe pipe = intel_crtc->pipe;
7632
7633         /* pipesrc controls the size that is scaled from, which should
7634          * always be the user's requested size.
7635          */
7636         I915_WRITE(PIPESRC(pipe),
7637                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7638                    (intel_crtc->config->pipe_src_h - 1));
7639 }
7640
7641 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7642                                    struct intel_crtc_state *pipe_config)
7643 {
7644         struct drm_device *dev = crtc->base.dev;
7645         struct drm_i915_private *dev_priv = dev->dev_private;
7646         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7647         uint32_t tmp;
7648
7649         tmp = I915_READ(HTOTAL(cpu_transcoder));
7650         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7651         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7652         tmp = I915_READ(HBLANK(cpu_transcoder));
7653         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7654         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7655         tmp = I915_READ(HSYNC(cpu_transcoder));
7656         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7657         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7658
7659         tmp = I915_READ(VTOTAL(cpu_transcoder));
7660         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7661         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7662         tmp = I915_READ(VBLANK(cpu_transcoder));
7663         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7664         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7665         tmp = I915_READ(VSYNC(cpu_transcoder));
7666         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7667         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7668
7669         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7670                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7671                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7672                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7673         }
7674 }
7675
7676 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7677                                     struct intel_crtc_state *pipe_config)
7678 {
7679         struct drm_device *dev = crtc->base.dev;
7680         struct drm_i915_private *dev_priv = dev->dev_private;
7681         u32 tmp;
7682
7683         tmp = I915_READ(PIPESRC(crtc->pipe));
7684         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7685         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7686
7687         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7688         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7689 }
7690
7691 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7692                                  struct intel_crtc_state *pipe_config)
7693 {
7694         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7695         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7696         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7697         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7698
7699         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7700         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7701         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7702         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7703
7704         mode->flags = pipe_config->base.adjusted_mode.flags;
7705         mode->type = DRM_MODE_TYPE_DRIVER;
7706
7707         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7708         mode->flags |= pipe_config->base.adjusted_mode.flags;
7709
7710         mode->hsync = drm_mode_hsync(mode);
7711         mode->vrefresh = drm_mode_vrefresh(mode);
7712         drm_mode_set_name(mode);
7713 }
7714
7715 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7716 {
7717         struct drm_device *dev = intel_crtc->base.dev;
7718         struct drm_i915_private *dev_priv = dev->dev_private;
7719         uint32_t pipeconf;
7720
7721         pipeconf = 0;
7722
7723         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7724             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7725                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7726
7727         if (intel_crtc->config->double_wide)
7728                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7729
7730         /* only g4x and later have fancy bpc/dither controls */
7731         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7732                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7733                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7734                         pipeconf |= PIPECONF_DITHER_EN |
7735                                     PIPECONF_DITHER_TYPE_SP;
7736
7737                 switch (intel_crtc->config->pipe_bpp) {
7738                 case 18:
7739                         pipeconf |= PIPECONF_6BPC;
7740                         break;
7741                 case 24:
7742                         pipeconf |= PIPECONF_8BPC;
7743                         break;
7744                 case 30:
7745                         pipeconf |= PIPECONF_10BPC;
7746                         break;
7747                 default:
7748                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7749                         BUG();
7750                 }
7751         }
7752
7753         if (HAS_PIPE_CXSR(dev)) {
7754                 if (intel_crtc->lowfreq_avail) {
7755                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7756                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7757                 } else {
7758                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7759                 }
7760         }
7761
7762         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7763                 if (INTEL_INFO(dev)->gen < 4 ||
7764                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7765                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7766                 else
7767                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7768         } else
7769                 pipeconf |= PIPECONF_PROGRESSIVE;
7770
7771         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7772              intel_crtc->config->limited_color_range)
7773                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7774
7775         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7776         POSTING_READ(PIPECONF(intel_crtc->pipe));
7777 }
7778
7779 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7780                                    struct intel_crtc_state *crtc_state)
7781 {
7782         struct drm_device *dev = crtc->base.dev;
7783         struct drm_i915_private *dev_priv = dev->dev_private;
7784         const struct intel_limit *limit;
7785         int refclk = 48000;
7786
7787         memset(&crtc_state->dpll_hw_state, 0,
7788                sizeof(crtc_state->dpll_hw_state));
7789
7790         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7791                 if (intel_panel_use_ssc(dev_priv)) {
7792                         refclk = dev_priv->vbt.lvds_ssc_freq;
7793                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7794                 }
7795
7796                 limit = &intel_limits_i8xx_lvds;
7797         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7798                 limit = &intel_limits_i8xx_dvo;
7799         } else {
7800                 limit = &intel_limits_i8xx_dac;
7801         }
7802
7803         if (!crtc_state->clock_set &&
7804             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7805                                  refclk, NULL, &crtc_state->dpll)) {
7806                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7807                 return -EINVAL;
7808         }
7809
7810         i8xx_compute_dpll(crtc, crtc_state, NULL);
7811
7812         return 0;
7813 }
7814
7815 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7816                                   struct intel_crtc_state *crtc_state)
7817 {
7818         struct drm_device *dev = crtc->base.dev;
7819         struct drm_i915_private *dev_priv = dev->dev_private;
7820         const struct intel_limit *limit;
7821         int refclk = 96000;
7822
7823         memset(&crtc_state->dpll_hw_state, 0,
7824                sizeof(crtc_state->dpll_hw_state));
7825
7826         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7827                 if (intel_panel_use_ssc(dev_priv)) {
7828                         refclk = dev_priv->vbt.lvds_ssc_freq;
7829                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7830                 }
7831
7832                 if (intel_is_dual_link_lvds(dev))
7833                         limit = &intel_limits_g4x_dual_channel_lvds;
7834                 else
7835                         limit = &intel_limits_g4x_single_channel_lvds;
7836         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7837                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7838                 limit = &intel_limits_g4x_hdmi;
7839         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7840                 limit = &intel_limits_g4x_sdvo;
7841         } else {
7842                 /* The option is for other outputs */
7843                 limit = &intel_limits_i9xx_sdvo;
7844         }
7845
7846         if (!crtc_state->clock_set &&
7847             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7848                                 refclk, NULL, &crtc_state->dpll)) {
7849                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7850                 return -EINVAL;
7851         }
7852
7853         i9xx_compute_dpll(crtc, crtc_state, NULL);
7854
7855         return 0;
7856 }
7857
7858 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7859                                   struct intel_crtc_state *crtc_state)
7860 {
7861         struct drm_device *dev = crtc->base.dev;
7862         struct drm_i915_private *dev_priv = dev->dev_private;
7863         const struct intel_limit *limit;
7864         int refclk = 96000;
7865
7866         memset(&crtc_state->dpll_hw_state, 0,
7867                sizeof(crtc_state->dpll_hw_state));
7868
7869         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7870                 if (intel_panel_use_ssc(dev_priv)) {
7871                         refclk = dev_priv->vbt.lvds_ssc_freq;
7872                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7873                 }
7874
7875                 limit = &intel_limits_pineview_lvds;
7876         } else {
7877                 limit = &intel_limits_pineview_sdvo;
7878         }
7879
7880         if (!crtc_state->clock_set &&
7881             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7882                                 refclk, NULL, &crtc_state->dpll)) {
7883                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7884                 return -EINVAL;
7885         }
7886
7887         i9xx_compute_dpll(crtc, crtc_state, NULL);
7888
7889         return 0;
7890 }
7891
7892 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7893                                    struct intel_crtc_state *crtc_state)
7894 {
7895         struct drm_device *dev = crtc->base.dev;
7896         struct drm_i915_private *dev_priv = dev->dev_private;
7897         const struct intel_limit *limit;
7898         int refclk = 96000;
7899
7900         memset(&crtc_state->dpll_hw_state, 0,
7901                sizeof(crtc_state->dpll_hw_state));
7902
7903         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7904                 if (intel_panel_use_ssc(dev_priv)) {
7905                         refclk = dev_priv->vbt.lvds_ssc_freq;
7906                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7907                 }
7908
7909                 limit = &intel_limits_i9xx_lvds;
7910         } else {
7911                 limit = &intel_limits_i9xx_sdvo;
7912         }
7913
7914         if (!crtc_state->clock_set &&
7915             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7916                                  refclk, NULL, &crtc_state->dpll)) {
7917                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7918                 return -EINVAL;
7919         }
7920
7921         i9xx_compute_dpll(crtc, crtc_state, NULL);
7922
7923         return 0;
7924 }
7925
7926 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7927                                   struct intel_crtc_state *crtc_state)
7928 {
7929         int refclk = 100000;
7930         const struct intel_limit *limit = &intel_limits_chv;
7931
7932         memset(&crtc_state->dpll_hw_state, 0,
7933                sizeof(crtc_state->dpll_hw_state));
7934
7935         if (!crtc_state->clock_set &&
7936             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7937                                 refclk, NULL, &crtc_state->dpll)) {
7938                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7939                 return -EINVAL;
7940         }
7941
7942         chv_compute_dpll(crtc, crtc_state);
7943
7944         return 0;
7945 }
7946
7947 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7948                                   struct intel_crtc_state *crtc_state)
7949 {
7950         int refclk = 100000;
7951         const struct intel_limit *limit = &intel_limits_vlv;
7952
7953         memset(&crtc_state->dpll_hw_state, 0,
7954                sizeof(crtc_state->dpll_hw_state));
7955
7956         if (!crtc_state->clock_set &&
7957             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7958                                 refclk, NULL, &crtc_state->dpll)) {
7959                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7960                 return -EINVAL;
7961         }
7962
7963         vlv_compute_dpll(crtc, crtc_state);
7964
7965         return 0;
7966 }
7967
7968 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7969                                  struct intel_crtc_state *pipe_config)
7970 {
7971         struct drm_device *dev = crtc->base.dev;
7972         struct drm_i915_private *dev_priv = dev->dev_private;
7973         uint32_t tmp;
7974
7975         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7976                 return;
7977
7978         tmp = I915_READ(PFIT_CONTROL);
7979         if (!(tmp & PFIT_ENABLE))
7980                 return;
7981
7982         /* Check whether the pfit is attached to our pipe. */
7983         if (INTEL_INFO(dev)->gen < 4) {
7984                 if (crtc->pipe != PIPE_B)
7985                         return;
7986         } else {
7987                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7988                         return;
7989         }
7990
7991         pipe_config->gmch_pfit.control = tmp;
7992         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7993 }
7994
7995 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7996                                struct intel_crtc_state *pipe_config)
7997 {
7998         struct drm_device *dev = crtc->base.dev;
7999         struct drm_i915_private *dev_priv = dev->dev_private;
8000         int pipe = pipe_config->cpu_transcoder;
8001         struct dpll clock;
8002         u32 mdiv;
8003         int refclk = 100000;
8004
8005         /* In case of DSI, DPLL will not be used */
8006         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8007                 return;
8008
8009         mutex_lock(&dev_priv->sb_lock);
8010         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8011         mutex_unlock(&dev_priv->sb_lock);
8012
8013         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8014         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8015         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8016         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8017         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8018
8019         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8020 }
8021
8022 static void
8023 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8024                               struct intel_initial_plane_config *plane_config)
8025 {
8026         struct drm_device *dev = crtc->base.dev;
8027         struct drm_i915_private *dev_priv = dev->dev_private;
8028         u32 val, base, offset;
8029         int pipe = crtc->pipe, plane = crtc->plane;
8030         int fourcc, pixel_format;
8031         unsigned int aligned_height;
8032         struct drm_framebuffer *fb;
8033         struct intel_framebuffer *intel_fb;
8034
8035         val = I915_READ(DSPCNTR(plane));
8036         if (!(val & DISPLAY_PLANE_ENABLE))
8037                 return;
8038
8039         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8040         if (!intel_fb) {
8041                 DRM_DEBUG_KMS("failed to alloc fb\n");
8042                 return;
8043         }
8044
8045         fb = &intel_fb->base;
8046
8047         if (INTEL_INFO(dev)->gen >= 4) {
8048                 if (val & DISPPLANE_TILED) {
8049                         plane_config->tiling = I915_TILING_X;
8050                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8051                 }
8052         }
8053
8054         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8055         fourcc = i9xx_format_to_fourcc(pixel_format);
8056         fb->pixel_format = fourcc;
8057         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8058
8059         if (INTEL_INFO(dev)->gen >= 4) {
8060                 if (plane_config->tiling)
8061                         offset = I915_READ(DSPTILEOFF(plane));
8062                 else
8063                         offset = I915_READ(DSPLINOFF(plane));
8064                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8065         } else {
8066                 base = I915_READ(DSPADDR(plane));
8067         }
8068         plane_config->base = base;
8069
8070         val = I915_READ(PIPESRC(pipe));
8071         fb->width = ((val >> 16) & 0xfff) + 1;
8072         fb->height = ((val >> 0) & 0xfff) + 1;
8073
8074         val = I915_READ(DSPSTRIDE(pipe));
8075         fb->pitches[0] = val & 0xffffffc0;
8076
8077         aligned_height = intel_fb_align_height(dev, fb->height,
8078                                                fb->pixel_format,
8079                                                fb->modifier[0]);
8080
8081         plane_config->size = fb->pitches[0] * aligned_height;
8082
8083         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8084                       pipe_name(pipe), plane, fb->width, fb->height,
8085                       fb->bits_per_pixel, base, fb->pitches[0],
8086                       plane_config->size);
8087
8088         plane_config->fb = intel_fb;
8089 }
8090
8091 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8092                                struct intel_crtc_state *pipe_config)
8093 {
8094         struct drm_device *dev = crtc->base.dev;
8095         struct drm_i915_private *dev_priv = dev->dev_private;
8096         int pipe = pipe_config->cpu_transcoder;
8097         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8098         struct dpll clock;
8099         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8100         int refclk = 100000;
8101
8102         /* In case of DSI, DPLL will not be used */
8103         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8104                 return;
8105
8106         mutex_lock(&dev_priv->sb_lock);
8107         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8108         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8109         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8110         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8111         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8112         mutex_unlock(&dev_priv->sb_lock);
8113
8114         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8115         clock.m2 = (pll_dw0 & 0xff) << 22;
8116         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8117                 clock.m2 |= pll_dw2 & 0x3fffff;
8118         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8119         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8120         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8121
8122         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8123 }
8124
8125 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8126                                  struct intel_crtc_state *pipe_config)
8127 {
8128         struct drm_device *dev = crtc->base.dev;
8129         struct drm_i915_private *dev_priv = dev->dev_private;
8130         enum intel_display_power_domain power_domain;
8131         uint32_t tmp;
8132         bool ret;
8133
8134         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8135         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8136                 return false;
8137
8138         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8139         pipe_config->shared_dpll = NULL;
8140
8141         ret = false;
8142
8143         tmp = I915_READ(PIPECONF(crtc->pipe));
8144         if (!(tmp & PIPECONF_ENABLE))
8145                 goto out;
8146
8147         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8148                 switch (tmp & PIPECONF_BPC_MASK) {
8149                 case PIPECONF_6BPC:
8150                         pipe_config->pipe_bpp = 18;
8151                         break;
8152                 case PIPECONF_8BPC:
8153                         pipe_config->pipe_bpp = 24;
8154                         break;
8155                 case PIPECONF_10BPC:
8156                         pipe_config->pipe_bpp = 30;
8157                         break;
8158                 default:
8159                         break;
8160                 }
8161         }
8162
8163         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8164             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8165                 pipe_config->limited_color_range = true;
8166
8167         if (INTEL_INFO(dev)->gen < 4)
8168                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8169
8170         intel_get_pipe_timings(crtc, pipe_config);
8171         intel_get_pipe_src_size(crtc, pipe_config);
8172
8173         i9xx_get_pfit_config(crtc, pipe_config);
8174
8175         if (INTEL_INFO(dev)->gen >= 4) {
8176                 /* No way to read it out on pipes B and C */
8177                 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8178                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8179                 else
8180                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8181                 pipe_config->pixel_multiplier =
8182                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8183                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8184                 pipe_config->dpll_hw_state.dpll_md = tmp;
8185         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8186                 tmp = I915_READ(DPLL(crtc->pipe));
8187                 pipe_config->pixel_multiplier =
8188                         ((tmp & SDVO_MULTIPLIER_MASK)
8189                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8190         } else {
8191                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8192                  * port and will be fixed up in the encoder->get_config
8193                  * function. */
8194                 pipe_config->pixel_multiplier = 1;
8195         }
8196         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8197         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8198                 /*
8199                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8200                  * on 830. Filter it out here so that we don't
8201                  * report errors due to that.
8202                  */
8203                 if (IS_I830(dev))
8204                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8205
8206                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8207                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8208         } else {
8209                 /* Mask out read-only status bits. */
8210                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8211                                                      DPLL_PORTC_READY_MASK |
8212                                                      DPLL_PORTB_READY_MASK);
8213         }
8214
8215         if (IS_CHERRYVIEW(dev))
8216                 chv_crtc_clock_get(crtc, pipe_config);
8217         else if (IS_VALLEYVIEW(dev))
8218                 vlv_crtc_clock_get(crtc, pipe_config);
8219         else
8220                 i9xx_crtc_clock_get(crtc, pipe_config);
8221
8222         /*
8223          * Normally the dotclock is filled in by the encoder .get_config()
8224          * but in case the pipe is enabled w/o any ports we need a sane
8225          * default.
8226          */
8227         pipe_config->base.adjusted_mode.crtc_clock =
8228                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8229
8230         ret = true;
8231
8232 out:
8233         intel_display_power_put(dev_priv, power_domain);
8234
8235         return ret;
8236 }
8237
8238 static void ironlake_init_pch_refclk(struct drm_device *dev)
8239 {
8240         struct drm_i915_private *dev_priv = dev->dev_private;
8241         struct intel_encoder *encoder;
8242         u32 val, final;
8243         bool has_lvds = false;
8244         bool has_cpu_edp = false;
8245         bool has_panel = false;
8246         bool has_ck505 = false;
8247         bool can_ssc = false;
8248
8249         /* We need to take the global config into account */
8250         for_each_intel_encoder(dev, encoder) {
8251                 switch (encoder->type) {
8252                 case INTEL_OUTPUT_LVDS:
8253                         has_panel = true;
8254                         has_lvds = true;
8255                         break;
8256                 case INTEL_OUTPUT_EDP:
8257                         has_panel = true;
8258                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8259                                 has_cpu_edp = true;
8260                         break;
8261                 default:
8262                         break;
8263                 }
8264         }
8265
8266         if (HAS_PCH_IBX(dev)) {
8267                 has_ck505 = dev_priv->vbt.display_clock_mode;
8268                 can_ssc = has_ck505;
8269         } else {
8270                 has_ck505 = false;
8271                 can_ssc = true;
8272         }
8273
8274         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8275                       has_panel, has_lvds, has_ck505);
8276
8277         /* Ironlake: try to setup display ref clock before DPLL
8278          * enabling. This is only under driver's control after
8279          * PCH B stepping, previous chipset stepping should be
8280          * ignoring this setting.
8281          */
8282         val = I915_READ(PCH_DREF_CONTROL);
8283
8284         /* As we must carefully and slowly disable/enable each source in turn,
8285          * compute the final state we want first and check if we need to
8286          * make any changes at all.
8287          */
8288         final = val;
8289         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8290         if (has_ck505)
8291                 final |= DREF_NONSPREAD_CK505_ENABLE;
8292         else
8293                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8294
8295         final &= ~DREF_SSC_SOURCE_MASK;
8296         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8297         final &= ~DREF_SSC1_ENABLE;
8298
8299         if (has_panel) {
8300                 final |= DREF_SSC_SOURCE_ENABLE;
8301
8302                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8303                         final |= DREF_SSC1_ENABLE;
8304
8305                 if (has_cpu_edp) {
8306                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8307                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8308                         else
8309                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8310                 } else
8311                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8312         } else {
8313                 final |= DREF_SSC_SOURCE_DISABLE;
8314                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8315         }
8316
8317         if (final == val)
8318                 return;
8319
8320         /* Always enable nonspread source */
8321         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8322
8323         if (has_ck505)
8324                 val |= DREF_NONSPREAD_CK505_ENABLE;
8325         else
8326                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8327
8328         if (has_panel) {
8329                 val &= ~DREF_SSC_SOURCE_MASK;
8330                 val |= DREF_SSC_SOURCE_ENABLE;
8331
8332                 /* SSC must be turned on before enabling the CPU output  */
8333                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8334                         DRM_DEBUG_KMS("Using SSC on panel\n");
8335                         val |= DREF_SSC1_ENABLE;
8336                 } else
8337                         val &= ~DREF_SSC1_ENABLE;
8338
8339                 /* Get SSC going before enabling the outputs */
8340                 I915_WRITE(PCH_DREF_CONTROL, val);
8341                 POSTING_READ(PCH_DREF_CONTROL);
8342                 udelay(200);
8343
8344                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8345
8346                 /* Enable CPU source on CPU attached eDP */
8347                 if (has_cpu_edp) {
8348                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8349                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8350                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8351                         } else
8352                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8353                 } else
8354                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8355
8356                 I915_WRITE(PCH_DREF_CONTROL, val);
8357                 POSTING_READ(PCH_DREF_CONTROL);
8358                 udelay(200);
8359         } else {
8360                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8361
8362                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8363
8364                 /* Turn off CPU output */
8365                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8366
8367                 I915_WRITE(PCH_DREF_CONTROL, val);
8368                 POSTING_READ(PCH_DREF_CONTROL);
8369                 udelay(200);
8370
8371                 /* Turn off the SSC source */
8372                 val &= ~DREF_SSC_SOURCE_MASK;
8373                 val |= DREF_SSC_SOURCE_DISABLE;
8374
8375                 /* Turn off SSC1 */
8376                 val &= ~DREF_SSC1_ENABLE;
8377
8378                 I915_WRITE(PCH_DREF_CONTROL, val);
8379                 POSTING_READ(PCH_DREF_CONTROL);
8380                 udelay(200);
8381         }
8382
8383         BUG_ON(val != final);
8384 }
8385
8386 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8387 {
8388         uint32_t tmp;
8389
8390         tmp = I915_READ(SOUTH_CHICKEN2);
8391         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8392         I915_WRITE(SOUTH_CHICKEN2, tmp);
8393
8394         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8395                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8396                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8397
8398         tmp = I915_READ(SOUTH_CHICKEN2);
8399         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8400         I915_WRITE(SOUTH_CHICKEN2, tmp);
8401
8402         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8403                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8404                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8405 }
8406
8407 /* WaMPhyProgramming:hsw */
8408 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8409 {
8410         uint32_t tmp;
8411
8412         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8413         tmp &= ~(0xFF << 24);
8414         tmp |= (0x12 << 24);
8415         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8416
8417         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8418         tmp |= (1 << 11);
8419         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8420
8421         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8422         tmp |= (1 << 11);
8423         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8424
8425         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8426         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8427         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8428
8429         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8430         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8431         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8432
8433         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8434         tmp &= ~(7 << 13);
8435         tmp |= (5 << 13);
8436         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8437
8438         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8439         tmp &= ~(7 << 13);
8440         tmp |= (5 << 13);
8441         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8442
8443         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8444         tmp &= ~0xFF;
8445         tmp |= 0x1C;
8446         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8447
8448         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8449         tmp &= ~0xFF;
8450         tmp |= 0x1C;
8451         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8452
8453         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8454         tmp &= ~(0xFF << 16);
8455         tmp |= (0x1C << 16);
8456         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8457
8458         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8459         tmp &= ~(0xFF << 16);
8460         tmp |= (0x1C << 16);
8461         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8462
8463         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8464         tmp |= (1 << 27);
8465         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8466
8467         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8468         tmp |= (1 << 27);
8469         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8470
8471         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8472         tmp &= ~(0xF << 28);
8473         tmp |= (4 << 28);
8474         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8475
8476         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8477         tmp &= ~(0xF << 28);
8478         tmp |= (4 << 28);
8479         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8480 }
8481
8482 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8483  * Programming" based on the parameters passed:
8484  * - Sequence to enable CLKOUT_DP
8485  * - Sequence to enable CLKOUT_DP without spread
8486  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8487  */
8488 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8489                                  bool with_fdi)
8490 {
8491         struct drm_i915_private *dev_priv = dev->dev_private;
8492         uint32_t reg, tmp;
8493
8494         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8495                 with_spread = true;
8496         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8497                 with_fdi = false;
8498
8499         mutex_lock(&dev_priv->sb_lock);
8500
8501         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8502         tmp &= ~SBI_SSCCTL_DISABLE;
8503         tmp |= SBI_SSCCTL_PATHALT;
8504         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8505
8506         udelay(24);
8507
8508         if (with_spread) {
8509                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8510                 tmp &= ~SBI_SSCCTL_PATHALT;
8511                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8512
8513                 if (with_fdi) {
8514                         lpt_reset_fdi_mphy(dev_priv);
8515                         lpt_program_fdi_mphy(dev_priv);
8516                 }
8517         }
8518
8519         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8520         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8521         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8522         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8523
8524         mutex_unlock(&dev_priv->sb_lock);
8525 }
8526
8527 /* Sequence to disable CLKOUT_DP */
8528 static void lpt_disable_clkout_dp(struct drm_device *dev)
8529 {
8530         struct drm_i915_private *dev_priv = dev->dev_private;
8531         uint32_t reg, tmp;
8532
8533         mutex_lock(&dev_priv->sb_lock);
8534
8535         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8536         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8537         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8538         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8539
8540         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8541         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8542                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8543                         tmp |= SBI_SSCCTL_PATHALT;
8544                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8545                         udelay(32);
8546                 }
8547                 tmp |= SBI_SSCCTL_DISABLE;
8548                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8549         }
8550
8551         mutex_unlock(&dev_priv->sb_lock);
8552 }
8553
8554 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8555
8556 static const uint16_t sscdivintphase[] = {
8557         [BEND_IDX( 50)] = 0x3B23,
8558         [BEND_IDX( 45)] = 0x3B23,
8559         [BEND_IDX( 40)] = 0x3C23,
8560         [BEND_IDX( 35)] = 0x3C23,
8561         [BEND_IDX( 30)] = 0x3D23,
8562         [BEND_IDX( 25)] = 0x3D23,
8563         [BEND_IDX( 20)] = 0x3E23,
8564         [BEND_IDX( 15)] = 0x3E23,
8565         [BEND_IDX( 10)] = 0x3F23,
8566         [BEND_IDX(  5)] = 0x3F23,
8567         [BEND_IDX(  0)] = 0x0025,
8568         [BEND_IDX( -5)] = 0x0025,
8569         [BEND_IDX(-10)] = 0x0125,
8570         [BEND_IDX(-15)] = 0x0125,
8571         [BEND_IDX(-20)] = 0x0225,
8572         [BEND_IDX(-25)] = 0x0225,
8573         [BEND_IDX(-30)] = 0x0325,
8574         [BEND_IDX(-35)] = 0x0325,
8575         [BEND_IDX(-40)] = 0x0425,
8576         [BEND_IDX(-45)] = 0x0425,
8577         [BEND_IDX(-50)] = 0x0525,
8578 };
8579
8580 /*
8581  * Bend CLKOUT_DP
8582  * steps -50 to 50 inclusive, in steps of 5
8583  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8584  * change in clock period = -(steps / 10) * 5.787 ps
8585  */
8586 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8587 {
8588         uint32_t tmp;
8589         int idx = BEND_IDX(steps);
8590
8591         if (WARN_ON(steps % 5 != 0))
8592                 return;
8593
8594         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8595                 return;
8596
8597         mutex_lock(&dev_priv->sb_lock);
8598
8599         if (steps % 10 != 0)
8600                 tmp = 0xAAAAAAAB;
8601         else
8602                 tmp = 0x00000000;
8603         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8604
8605         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8606         tmp &= 0xffff0000;
8607         tmp |= sscdivintphase[idx];
8608         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8609
8610         mutex_unlock(&dev_priv->sb_lock);
8611 }
8612
8613 #undef BEND_IDX
8614
8615 static void lpt_init_pch_refclk(struct drm_device *dev)
8616 {
8617         struct intel_encoder *encoder;
8618         bool has_vga = false;
8619
8620         for_each_intel_encoder(dev, encoder) {
8621                 switch (encoder->type) {
8622                 case INTEL_OUTPUT_ANALOG:
8623                         has_vga = true;
8624                         break;
8625                 default:
8626                         break;
8627                 }
8628         }
8629
8630         if (has_vga) {
8631                 lpt_bend_clkout_dp(to_i915(dev), 0);
8632                 lpt_enable_clkout_dp(dev, true, true);
8633         } else {
8634                 lpt_disable_clkout_dp(dev);
8635         }
8636 }
8637
8638 /*
8639  * Initialize reference clocks when the driver loads
8640  */
8641 void intel_init_pch_refclk(struct drm_device *dev)
8642 {
8643         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8644                 ironlake_init_pch_refclk(dev);
8645         else if (HAS_PCH_LPT(dev))
8646                 lpt_init_pch_refclk(dev);
8647 }
8648
8649 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8650 {
8651         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8652         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8653         int pipe = intel_crtc->pipe;
8654         uint32_t val;
8655
8656         val = 0;
8657
8658         switch (intel_crtc->config->pipe_bpp) {
8659         case 18:
8660                 val |= PIPECONF_6BPC;
8661                 break;
8662         case 24:
8663                 val |= PIPECONF_8BPC;
8664                 break;
8665         case 30:
8666                 val |= PIPECONF_10BPC;
8667                 break;
8668         case 36:
8669                 val |= PIPECONF_12BPC;
8670                 break;
8671         default:
8672                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8673                 BUG();
8674         }
8675
8676         if (intel_crtc->config->dither)
8677                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8678
8679         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8680                 val |= PIPECONF_INTERLACED_ILK;
8681         else
8682                 val |= PIPECONF_PROGRESSIVE;
8683
8684         if (intel_crtc->config->limited_color_range)
8685                 val |= PIPECONF_COLOR_RANGE_SELECT;
8686
8687         I915_WRITE(PIPECONF(pipe), val);
8688         POSTING_READ(PIPECONF(pipe));
8689 }
8690
8691 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8692 {
8693         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8695         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8696         u32 val = 0;
8697
8698         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8699                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8700
8701         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8702                 val |= PIPECONF_INTERLACED_ILK;
8703         else
8704                 val |= PIPECONF_PROGRESSIVE;
8705
8706         I915_WRITE(PIPECONF(cpu_transcoder), val);
8707         POSTING_READ(PIPECONF(cpu_transcoder));
8708 }
8709
8710 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8711 {
8712         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8713         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8714
8715         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8716                 u32 val = 0;
8717
8718                 switch (intel_crtc->config->pipe_bpp) {
8719                 case 18:
8720                         val |= PIPEMISC_DITHER_6_BPC;
8721                         break;
8722                 case 24:
8723                         val |= PIPEMISC_DITHER_8_BPC;
8724                         break;
8725                 case 30:
8726                         val |= PIPEMISC_DITHER_10_BPC;
8727                         break;
8728                 case 36:
8729                         val |= PIPEMISC_DITHER_12_BPC;
8730                         break;
8731                 default:
8732                         /* Case prevented by pipe_config_set_bpp. */
8733                         BUG();
8734                 }
8735
8736                 if (intel_crtc->config->dither)
8737                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8738
8739                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8740         }
8741 }
8742
8743 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8744 {
8745         /*
8746          * Account for spread spectrum to avoid
8747          * oversubscribing the link. Max center spread
8748          * is 2.5%; use 5% for safety's sake.
8749          */
8750         u32 bps = target_clock * bpp * 21 / 20;
8751         return DIV_ROUND_UP(bps, link_bw * 8);
8752 }
8753
8754 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8755 {
8756         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8757 }
8758
8759 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8760                                   struct intel_crtc_state *crtc_state,
8761                                   struct dpll *reduced_clock)
8762 {
8763         struct drm_crtc *crtc = &intel_crtc->base;
8764         struct drm_device *dev = crtc->dev;
8765         struct drm_i915_private *dev_priv = dev->dev_private;
8766         struct drm_atomic_state *state = crtc_state->base.state;
8767         struct drm_connector *connector;
8768         struct drm_connector_state *connector_state;
8769         struct intel_encoder *encoder;
8770         u32 dpll, fp, fp2;
8771         int factor, i;
8772         bool is_lvds = false, is_sdvo = false;
8773
8774         for_each_connector_in_state(state, connector, connector_state, i) {
8775                 if (connector_state->crtc != crtc_state->base.crtc)
8776                         continue;
8777
8778                 encoder = to_intel_encoder(connector_state->best_encoder);
8779
8780                 switch (encoder->type) {
8781                 case INTEL_OUTPUT_LVDS:
8782                         is_lvds = true;
8783                         break;
8784                 case INTEL_OUTPUT_SDVO:
8785                 case INTEL_OUTPUT_HDMI:
8786                         is_sdvo = true;
8787                         break;
8788                 default:
8789                         break;
8790                 }
8791         }
8792
8793         /* Enable autotuning of the PLL clock (if permissible) */
8794         factor = 21;
8795         if (is_lvds) {
8796                 if ((intel_panel_use_ssc(dev_priv) &&
8797                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8798                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8799                         factor = 25;
8800         } else if (crtc_state->sdvo_tv_clock)
8801                 factor = 20;
8802
8803         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8804
8805         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8806                 fp |= FP_CB_TUNE;
8807
8808         if (reduced_clock) {
8809                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8810
8811                 if (reduced_clock->m < factor * reduced_clock->n)
8812                         fp2 |= FP_CB_TUNE;
8813         } else {
8814                 fp2 = fp;
8815         }
8816
8817         dpll = 0;
8818
8819         if (is_lvds)
8820                 dpll |= DPLLB_MODE_LVDS;
8821         else
8822                 dpll |= DPLLB_MODE_DAC_SERIAL;
8823
8824         dpll |= (crtc_state->pixel_multiplier - 1)
8825                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8826
8827         if (is_sdvo)
8828                 dpll |= DPLL_SDVO_HIGH_SPEED;
8829         if (crtc_state->has_dp_encoder)
8830                 dpll |= DPLL_SDVO_HIGH_SPEED;
8831
8832         /* compute bitmask from p1 value */
8833         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8834         /* also FPA1 */
8835         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8836
8837         switch (crtc_state->dpll.p2) {
8838         case 5:
8839                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8840                 break;
8841         case 7:
8842                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8843                 break;
8844         case 10:
8845                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8846                 break;
8847         case 14:
8848                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8849                 break;
8850         }
8851
8852         if (is_lvds && intel_panel_use_ssc(dev_priv))
8853                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8854         else
8855                 dpll |= PLL_REF_INPUT_DREFCLK;
8856
8857         dpll |= DPLL_VCO_ENABLE;
8858
8859         crtc_state->dpll_hw_state.dpll = dpll;
8860         crtc_state->dpll_hw_state.fp0 = fp;
8861         crtc_state->dpll_hw_state.fp1 = fp2;
8862 }
8863
8864 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8865                                        struct intel_crtc_state *crtc_state)
8866 {
8867         struct drm_device *dev = crtc->base.dev;
8868         struct drm_i915_private *dev_priv = dev->dev_private;
8869         struct dpll reduced_clock;
8870         bool has_reduced_clock = false;
8871         struct intel_shared_dpll *pll;
8872         const struct intel_limit *limit;
8873         int refclk = 120000;
8874
8875         memset(&crtc_state->dpll_hw_state, 0,
8876                sizeof(crtc_state->dpll_hw_state));
8877
8878         crtc->lowfreq_avail = false;
8879
8880         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8881         if (!crtc_state->has_pch_encoder)
8882                 return 0;
8883
8884         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8885                 if (intel_panel_use_ssc(dev_priv)) {
8886                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8887                                       dev_priv->vbt.lvds_ssc_freq);
8888                         refclk = dev_priv->vbt.lvds_ssc_freq;
8889                 }
8890
8891                 if (intel_is_dual_link_lvds(dev)) {
8892                         if (refclk == 100000)
8893                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8894                         else
8895                                 limit = &intel_limits_ironlake_dual_lvds;
8896                 } else {
8897                         if (refclk == 100000)
8898                                 limit = &intel_limits_ironlake_single_lvds_100m;
8899                         else
8900                                 limit = &intel_limits_ironlake_single_lvds;
8901                 }
8902         } else {
8903                 limit = &intel_limits_ironlake_dac;
8904         }
8905
8906         if (!crtc_state->clock_set &&
8907             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8908                                 refclk, NULL, &crtc_state->dpll)) {
8909                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8910                 return -EINVAL;
8911         }
8912
8913         ironlake_compute_dpll(crtc, crtc_state,
8914                               has_reduced_clock ? &reduced_clock : NULL);
8915
8916         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8917         if (pll == NULL) {
8918                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8919                                  pipe_name(crtc->pipe));
8920                 return -EINVAL;
8921         }
8922
8923         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8924             has_reduced_clock)
8925                 crtc->lowfreq_avail = true;
8926
8927         return 0;
8928 }
8929
8930 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8931                                          struct intel_link_m_n *m_n)
8932 {
8933         struct drm_device *dev = crtc->base.dev;
8934         struct drm_i915_private *dev_priv = dev->dev_private;
8935         enum pipe pipe = crtc->pipe;
8936
8937         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8938         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8939         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8940                 & ~TU_SIZE_MASK;
8941         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8942         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8943                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8944 }
8945
8946 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8947                                          enum transcoder transcoder,
8948                                          struct intel_link_m_n *m_n,
8949                                          struct intel_link_m_n *m2_n2)
8950 {
8951         struct drm_device *dev = crtc->base.dev;
8952         struct drm_i915_private *dev_priv = dev->dev_private;
8953         enum pipe pipe = crtc->pipe;
8954
8955         if (INTEL_INFO(dev)->gen >= 5) {
8956                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8957                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8958                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8959                         & ~TU_SIZE_MASK;
8960                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8961                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8962                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8963                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8964                  * gen < 8) and if DRRS is supported (to make sure the
8965                  * registers are not unnecessarily read).
8966                  */
8967                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8968                         crtc->config->has_drrs) {
8969                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8970                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8971                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8972                                         & ~TU_SIZE_MASK;
8973                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8974                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8975                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8976                 }
8977         } else {
8978                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8979                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8980                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8981                         & ~TU_SIZE_MASK;
8982                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8983                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8984                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8985         }
8986 }
8987
8988 void intel_dp_get_m_n(struct intel_crtc *crtc,
8989                       struct intel_crtc_state *pipe_config)
8990 {
8991         if (pipe_config->has_pch_encoder)
8992                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8993         else
8994                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8995                                              &pipe_config->dp_m_n,
8996                                              &pipe_config->dp_m2_n2);
8997 }
8998
8999 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9000                                         struct intel_crtc_state *pipe_config)
9001 {
9002         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9003                                      &pipe_config->fdi_m_n, NULL);
9004 }
9005
9006 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9007                                     struct intel_crtc_state *pipe_config)
9008 {
9009         struct drm_device *dev = crtc->base.dev;
9010         struct drm_i915_private *dev_priv = dev->dev_private;
9011         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9012         uint32_t ps_ctrl = 0;
9013         int id = -1;
9014         int i;
9015
9016         /* find scaler attached to this pipe */
9017         for (i = 0; i < crtc->num_scalers; i++) {
9018                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9019                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9020                         id = i;
9021                         pipe_config->pch_pfit.enabled = true;
9022                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9023                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9024                         break;
9025                 }
9026         }
9027
9028         scaler_state->scaler_id = id;
9029         if (id >= 0) {
9030                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9031         } else {
9032                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9033         }
9034 }
9035
9036 static void
9037 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9038                                  struct intel_initial_plane_config *plane_config)
9039 {
9040         struct drm_device *dev = crtc->base.dev;
9041         struct drm_i915_private *dev_priv = dev->dev_private;
9042         u32 val, base, offset, stride_mult, tiling;
9043         int pipe = crtc->pipe;
9044         int fourcc, pixel_format;
9045         unsigned int aligned_height;
9046         struct drm_framebuffer *fb;
9047         struct intel_framebuffer *intel_fb;
9048
9049         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9050         if (!intel_fb) {
9051                 DRM_DEBUG_KMS("failed to alloc fb\n");
9052                 return;
9053         }
9054
9055         fb = &intel_fb->base;
9056
9057         val = I915_READ(PLANE_CTL(pipe, 0));
9058         if (!(val & PLANE_CTL_ENABLE))
9059                 goto error;
9060
9061         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9062         fourcc = skl_format_to_fourcc(pixel_format,
9063                                       val & PLANE_CTL_ORDER_RGBX,
9064                                       val & PLANE_CTL_ALPHA_MASK);
9065         fb->pixel_format = fourcc;
9066         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9067
9068         tiling = val & PLANE_CTL_TILED_MASK;
9069         switch (tiling) {
9070         case PLANE_CTL_TILED_LINEAR:
9071                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9072                 break;
9073         case PLANE_CTL_TILED_X:
9074                 plane_config->tiling = I915_TILING_X;
9075                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9076                 break;
9077         case PLANE_CTL_TILED_Y:
9078                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9079                 break;
9080         case PLANE_CTL_TILED_YF:
9081                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9082                 break;
9083         default:
9084                 MISSING_CASE(tiling);
9085                 goto error;
9086         }
9087
9088         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9089         plane_config->base = base;
9090
9091         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9092
9093         val = I915_READ(PLANE_SIZE(pipe, 0));
9094         fb->height = ((val >> 16) & 0xfff) + 1;
9095         fb->width = ((val >> 0) & 0x1fff) + 1;
9096
9097         val = I915_READ(PLANE_STRIDE(pipe, 0));
9098         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9099                                                 fb->pixel_format);
9100         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9101
9102         aligned_height = intel_fb_align_height(dev, fb->height,
9103                                                fb->pixel_format,
9104                                                fb->modifier[0]);
9105
9106         plane_config->size = fb->pitches[0] * aligned_height;
9107
9108         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9109                       pipe_name(pipe), fb->width, fb->height,
9110                       fb->bits_per_pixel, base, fb->pitches[0],
9111                       plane_config->size);
9112
9113         plane_config->fb = intel_fb;
9114         return;
9115
9116 error:
9117         kfree(fb);
9118 }
9119
9120 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9121                                      struct intel_crtc_state *pipe_config)
9122 {
9123         struct drm_device *dev = crtc->base.dev;
9124         struct drm_i915_private *dev_priv = dev->dev_private;
9125         uint32_t tmp;
9126
9127         tmp = I915_READ(PF_CTL(crtc->pipe));
9128
9129         if (tmp & PF_ENABLE) {
9130                 pipe_config->pch_pfit.enabled = true;
9131                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9132                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9133
9134                 /* We currently do not free assignements of panel fitters on
9135                  * ivb/hsw (since we don't use the higher upscaling modes which
9136                  * differentiates them) so just WARN about this case for now. */
9137                 if (IS_GEN7(dev)) {
9138                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9139                                 PF_PIPE_SEL_IVB(crtc->pipe));
9140                 }
9141         }
9142 }
9143
9144 static void
9145 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9146                                   struct intel_initial_plane_config *plane_config)
9147 {
9148         struct drm_device *dev = crtc->base.dev;
9149         struct drm_i915_private *dev_priv = dev->dev_private;
9150         u32 val, base, offset;
9151         int pipe = crtc->pipe;
9152         int fourcc, pixel_format;
9153         unsigned int aligned_height;
9154         struct drm_framebuffer *fb;
9155         struct intel_framebuffer *intel_fb;
9156
9157         val = I915_READ(DSPCNTR(pipe));
9158         if (!(val & DISPLAY_PLANE_ENABLE))
9159                 return;
9160
9161         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9162         if (!intel_fb) {
9163                 DRM_DEBUG_KMS("failed to alloc fb\n");
9164                 return;
9165         }
9166
9167         fb = &intel_fb->base;
9168
9169         if (INTEL_INFO(dev)->gen >= 4) {
9170                 if (val & DISPPLANE_TILED) {
9171                         plane_config->tiling = I915_TILING_X;
9172                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9173                 }
9174         }
9175
9176         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9177         fourcc = i9xx_format_to_fourcc(pixel_format);
9178         fb->pixel_format = fourcc;
9179         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9180
9181         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9182         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9183                 offset = I915_READ(DSPOFFSET(pipe));
9184         } else {
9185                 if (plane_config->tiling)
9186                         offset = I915_READ(DSPTILEOFF(pipe));
9187                 else
9188                         offset = I915_READ(DSPLINOFF(pipe));
9189         }
9190         plane_config->base = base;
9191
9192         val = I915_READ(PIPESRC(pipe));
9193         fb->width = ((val >> 16) & 0xfff) + 1;
9194         fb->height = ((val >> 0) & 0xfff) + 1;
9195
9196         val = I915_READ(DSPSTRIDE(pipe));
9197         fb->pitches[0] = val & 0xffffffc0;
9198
9199         aligned_height = intel_fb_align_height(dev, fb->height,
9200                                                fb->pixel_format,
9201                                                fb->modifier[0]);
9202
9203         plane_config->size = fb->pitches[0] * aligned_height;
9204
9205         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9206                       pipe_name(pipe), fb->width, fb->height,
9207                       fb->bits_per_pixel, base, fb->pitches[0],
9208                       plane_config->size);
9209
9210         plane_config->fb = intel_fb;
9211 }
9212
9213 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9214                                      struct intel_crtc_state *pipe_config)
9215 {
9216         struct drm_device *dev = crtc->base.dev;
9217         struct drm_i915_private *dev_priv = dev->dev_private;
9218         enum intel_display_power_domain power_domain;
9219         uint32_t tmp;
9220         bool ret;
9221
9222         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9223         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9224                 return false;
9225
9226         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9227         pipe_config->shared_dpll = NULL;
9228
9229         ret = false;
9230         tmp = I915_READ(PIPECONF(crtc->pipe));
9231         if (!(tmp & PIPECONF_ENABLE))
9232                 goto out;
9233
9234         switch (tmp & PIPECONF_BPC_MASK) {
9235         case PIPECONF_6BPC:
9236                 pipe_config->pipe_bpp = 18;
9237                 break;
9238         case PIPECONF_8BPC:
9239                 pipe_config->pipe_bpp = 24;
9240                 break;
9241         case PIPECONF_10BPC:
9242                 pipe_config->pipe_bpp = 30;
9243                 break;
9244         case PIPECONF_12BPC:
9245                 pipe_config->pipe_bpp = 36;
9246                 break;
9247         default:
9248                 break;
9249         }
9250
9251         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9252                 pipe_config->limited_color_range = true;
9253
9254         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9255                 struct intel_shared_dpll *pll;
9256                 enum intel_dpll_id pll_id;
9257
9258                 pipe_config->has_pch_encoder = true;
9259
9260                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9261                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9262                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9263
9264                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9265
9266                 if (HAS_PCH_IBX(dev_priv)) {
9267                         /*
9268                          * The pipe->pch transcoder and pch transcoder->pll
9269                          * mapping is fixed.
9270                          */
9271                         pll_id = (enum intel_dpll_id) crtc->pipe;
9272                 } else {
9273                         tmp = I915_READ(PCH_DPLL_SEL);
9274                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9275                                 pll_id = DPLL_ID_PCH_PLL_B;
9276                         else
9277                                 pll_id= DPLL_ID_PCH_PLL_A;
9278                 }
9279
9280                 pipe_config->shared_dpll =
9281                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9282                 pll = pipe_config->shared_dpll;
9283
9284                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9285                                                  &pipe_config->dpll_hw_state));
9286
9287                 tmp = pipe_config->dpll_hw_state.dpll;
9288                 pipe_config->pixel_multiplier =
9289                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9290                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9291
9292                 ironlake_pch_clock_get(crtc, pipe_config);
9293         } else {
9294                 pipe_config->pixel_multiplier = 1;
9295         }
9296
9297         intel_get_pipe_timings(crtc, pipe_config);
9298         intel_get_pipe_src_size(crtc, pipe_config);
9299
9300         ironlake_get_pfit_config(crtc, pipe_config);
9301
9302         ret = true;
9303
9304 out:
9305         intel_display_power_put(dev_priv, power_domain);
9306
9307         return ret;
9308 }
9309
9310 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9311 {
9312         struct drm_device *dev = dev_priv->dev;
9313         struct intel_crtc *crtc;
9314
9315         for_each_intel_crtc(dev, crtc)
9316                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9317                      pipe_name(crtc->pipe));
9318
9319         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9320         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9321         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9322         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9323         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9324         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9325              "CPU PWM1 enabled\n");
9326         if (IS_HASWELL(dev))
9327                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9328                      "CPU PWM2 enabled\n");
9329         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9330              "PCH PWM1 enabled\n");
9331         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9332              "Utility pin enabled\n");
9333         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9334
9335         /*
9336          * In theory we can still leave IRQs enabled, as long as only the HPD
9337          * interrupts remain enabled. We used to check for that, but since it's
9338          * gen-specific and since we only disable LCPLL after we fully disable
9339          * the interrupts, the check below should be enough.
9340          */
9341         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9342 }
9343
9344 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9345 {
9346         struct drm_device *dev = dev_priv->dev;
9347
9348         if (IS_HASWELL(dev))
9349                 return I915_READ(D_COMP_HSW);
9350         else
9351                 return I915_READ(D_COMP_BDW);
9352 }
9353
9354 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9355 {
9356         struct drm_device *dev = dev_priv->dev;
9357
9358         if (IS_HASWELL(dev)) {
9359                 mutex_lock(&dev_priv->rps.hw_lock);
9360                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9361                                             val))
9362                         DRM_ERROR("Failed to write to D_COMP\n");
9363                 mutex_unlock(&dev_priv->rps.hw_lock);
9364         } else {
9365                 I915_WRITE(D_COMP_BDW, val);
9366                 POSTING_READ(D_COMP_BDW);
9367         }
9368 }
9369
9370 /*
9371  * This function implements pieces of two sequences from BSpec:
9372  * - Sequence for display software to disable LCPLL
9373  * - Sequence for display software to allow package C8+
9374  * The steps implemented here are just the steps that actually touch the LCPLL
9375  * register. Callers should take care of disabling all the display engine
9376  * functions, doing the mode unset, fixing interrupts, etc.
9377  */
9378 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9379                               bool switch_to_fclk, bool allow_power_down)
9380 {
9381         uint32_t val;
9382
9383         assert_can_disable_lcpll(dev_priv);
9384
9385         val = I915_READ(LCPLL_CTL);
9386
9387         if (switch_to_fclk) {
9388                 val |= LCPLL_CD_SOURCE_FCLK;
9389                 I915_WRITE(LCPLL_CTL, val);
9390
9391                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9392                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9393                         DRM_ERROR("Switching to FCLK failed\n");
9394
9395                 val = I915_READ(LCPLL_CTL);
9396         }
9397
9398         val |= LCPLL_PLL_DISABLE;
9399         I915_WRITE(LCPLL_CTL, val);
9400         POSTING_READ(LCPLL_CTL);
9401
9402         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9403                 DRM_ERROR("LCPLL still locked\n");
9404
9405         val = hsw_read_dcomp(dev_priv);
9406         val |= D_COMP_COMP_DISABLE;
9407         hsw_write_dcomp(dev_priv, val);
9408         ndelay(100);
9409
9410         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9411                      1))
9412                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9413
9414         if (allow_power_down) {
9415                 val = I915_READ(LCPLL_CTL);
9416                 val |= LCPLL_POWER_DOWN_ALLOW;
9417                 I915_WRITE(LCPLL_CTL, val);
9418                 POSTING_READ(LCPLL_CTL);
9419         }
9420 }
9421
9422 /*
9423  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9424  * source.
9425  */
9426 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9427 {
9428         uint32_t val;
9429
9430         val = I915_READ(LCPLL_CTL);
9431
9432         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9433                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9434                 return;
9435
9436         /*
9437          * Make sure we're not on PC8 state before disabling PC8, otherwise
9438          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9439          */
9440         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9441
9442         if (val & LCPLL_POWER_DOWN_ALLOW) {
9443                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9444                 I915_WRITE(LCPLL_CTL, val);
9445                 POSTING_READ(LCPLL_CTL);
9446         }
9447
9448         val = hsw_read_dcomp(dev_priv);
9449         val |= D_COMP_COMP_FORCE;
9450         val &= ~D_COMP_COMP_DISABLE;
9451         hsw_write_dcomp(dev_priv, val);
9452
9453         val = I915_READ(LCPLL_CTL);
9454         val &= ~LCPLL_PLL_DISABLE;
9455         I915_WRITE(LCPLL_CTL, val);
9456
9457         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9458                 DRM_ERROR("LCPLL not locked yet\n");
9459
9460         if (val & LCPLL_CD_SOURCE_FCLK) {
9461                 val = I915_READ(LCPLL_CTL);
9462                 val &= ~LCPLL_CD_SOURCE_FCLK;
9463                 I915_WRITE(LCPLL_CTL, val);
9464
9465                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9466                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9467                         DRM_ERROR("Switching back to LCPLL failed\n");
9468         }
9469
9470         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9471         intel_update_cdclk(dev_priv->dev);
9472 }
9473
9474 /*
9475  * Package states C8 and deeper are really deep PC states that can only be
9476  * reached when all the devices on the system allow it, so even if the graphics
9477  * device allows PC8+, it doesn't mean the system will actually get to these
9478  * states. Our driver only allows PC8+ when going into runtime PM.
9479  *
9480  * The requirements for PC8+ are that all the outputs are disabled, the power
9481  * well is disabled and most interrupts are disabled, and these are also
9482  * requirements for runtime PM. When these conditions are met, we manually do
9483  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9484  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9485  * hang the machine.
9486  *
9487  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9488  * the state of some registers, so when we come back from PC8+ we need to
9489  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9490  * need to take care of the registers kept by RC6. Notice that this happens even
9491  * if we don't put the device in PCI D3 state (which is what currently happens
9492  * because of the runtime PM support).
9493  *
9494  * For more, read "Display Sequences for Package C8" on the hardware
9495  * documentation.
9496  */
9497 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9498 {
9499         struct drm_device *dev = dev_priv->dev;
9500         uint32_t val;
9501
9502         DRM_DEBUG_KMS("Enabling package C8+\n");
9503
9504         if (HAS_PCH_LPT_LP(dev)) {
9505                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9506                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9507                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9508         }
9509
9510         lpt_disable_clkout_dp(dev);
9511         hsw_disable_lcpll(dev_priv, true, true);
9512 }
9513
9514 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9515 {
9516         struct drm_device *dev = dev_priv->dev;
9517         uint32_t val;
9518
9519         DRM_DEBUG_KMS("Disabling package C8+\n");
9520
9521         hsw_restore_lcpll(dev_priv);
9522         lpt_init_pch_refclk(dev);
9523
9524         if (HAS_PCH_LPT_LP(dev)) {
9525                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9526                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9527                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9528         }
9529 }
9530
9531 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9532 {
9533         struct drm_device *dev = old_state->dev;
9534         struct intel_atomic_state *old_intel_state =
9535                 to_intel_atomic_state(old_state);
9536         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9537
9538         broxton_set_cdclk(to_i915(dev), req_cdclk);
9539 }
9540
9541 /* compute the max rate for new configuration */
9542 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9543 {
9544         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9545         struct drm_i915_private *dev_priv = state->dev->dev_private;
9546         struct drm_crtc *crtc;
9547         struct drm_crtc_state *cstate;
9548         struct intel_crtc_state *crtc_state;
9549         unsigned max_pixel_rate = 0, i;
9550         enum pipe pipe;
9551
9552         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9553                sizeof(intel_state->min_pixclk));
9554
9555         for_each_crtc_in_state(state, crtc, cstate, i) {
9556                 int pixel_rate;
9557
9558                 crtc_state = to_intel_crtc_state(cstate);
9559                 if (!crtc_state->base.enable) {
9560                         intel_state->min_pixclk[i] = 0;
9561                         continue;
9562                 }
9563
9564                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9565
9566                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9567                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9568                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9569
9570                 intel_state->min_pixclk[i] = pixel_rate;
9571         }
9572
9573         for_each_pipe(dev_priv, pipe)
9574                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9575
9576         return max_pixel_rate;
9577 }
9578
9579 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9580 {
9581         struct drm_i915_private *dev_priv = dev->dev_private;
9582         uint32_t val, data;
9583         int ret;
9584
9585         if (WARN((I915_READ(LCPLL_CTL) &
9586                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9587                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9588                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9589                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9590                  "trying to change cdclk frequency with cdclk not enabled\n"))
9591                 return;
9592
9593         mutex_lock(&dev_priv->rps.hw_lock);
9594         ret = sandybridge_pcode_write(dev_priv,
9595                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9596         mutex_unlock(&dev_priv->rps.hw_lock);
9597         if (ret) {
9598                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9599                 return;
9600         }
9601
9602         val = I915_READ(LCPLL_CTL);
9603         val |= LCPLL_CD_SOURCE_FCLK;
9604         I915_WRITE(LCPLL_CTL, val);
9605
9606         if (wait_for_us(I915_READ(LCPLL_CTL) &
9607                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
9608                 DRM_ERROR("Switching to FCLK failed\n");
9609
9610         val = I915_READ(LCPLL_CTL);
9611         val &= ~LCPLL_CLK_FREQ_MASK;
9612
9613         switch (cdclk) {
9614         case 450000:
9615                 val |= LCPLL_CLK_FREQ_450;
9616                 data = 0;
9617                 break;
9618         case 540000:
9619                 val |= LCPLL_CLK_FREQ_54O_BDW;
9620                 data = 1;
9621                 break;
9622         case 337500:
9623                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9624                 data = 2;
9625                 break;
9626         case 675000:
9627                 val |= LCPLL_CLK_FREQ_675_BDW;
9628                 data = 3;
9629                 break;
9630         default:
9631                 WARN(1, "invalid cdclk frequency\n");
9632                 return;
9633         }
9634
9635         I915_WRITE(LCPLL_CTL, val);
9636
9637         val = I915_READ(LCPLL_CTL);
9638         val &= ~LCPLL_CD_SOURCE_FCLK;
9639         I915_WRITE(LCPLL_CTL, val);
9640
9641         if (wait_for_us((I915_READ(LCPLL_CTL) &
9642                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9643                 DRM_ERROR("Switching back to LCPLL failed\n");
9644
9645         mutex_lock(&dev_priv->rps.hw_lock);
9646         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9647         mutex_unlock(&dev_priv->rps.hw_lock);
9648
9649         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9650
9651         intel_update_cdclk(dev);
9652
9653         WARN(cdclk != dev_priv->cdclk_freq,
9654              "cdclk requested %d kHz but got %d kHz\n",
9655              cdclk, dev_priv->cdclk_freq);
9656 }
9657
9658 static int broadwell_calc_cdclk(int max_pixclk)
9659 {
9660         if (max_pixclk > 540000)
9661                 return 675000;
9662         else if (max_pixclk > 450000)
9663                 return 540000;
9664         else if (max_pixclk > 337500)
9665                 return 450000;
9666         else
9667                 return 337500;
9668 }
9669
9670 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9671 {
9672         struct drm_i915_private *dev_priv = to_i915(state->dev);
9673         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9674         int max_pixclk = ilk_max_pixel_rate(state);
9675         int cdclk;
9676
9677         /*
9678          * FIXME should also account for plane ratio
9679          * once 64bpp pixel formats are supported.
9680          */
9681         cdclk = broadwell_calc_cdclk(max_pixclk);
9682
9683         if (cdclk > dev_priv->max_cdclk_freq) {
9684                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9685                               cdclk, dev_priv->max_cdclk_freq);
9686                 return -EINVAL;
9687         }
9688
9689         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9690         if (!intel_state->active_crtcs)
9691                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9692
9693         return 0;
9694 }
9695
9696 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9697 {
9698         struct drm_device *dev = old_state->dev;
9699         struct intel_atomic_state *old_intel_state =
9700                 to_intel_atomic_state(old_state);
9701         unsigned req_cdclk = old_intel_state->dev_cdclk;
9702
9703         broadwell_set_cdclk(dev, req_cdclk);
9704 }
9705
9706 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
9707 {
9708         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9709         struct drm_i915_private *dev_priv = to_i915(state->dev);
9710         const int max_pixclk = ilk_max_pixel_rate(state);
9711         int vco = intel_state->cdclk_pll_vco;
9712         int cdclk;
9713
9714         /*
9715          * FIXME should also account for plane ratio
9716          * once 64bpp pixel formats are supported.
9717          */
9718         cdclk = skl_calc_cdclk(max_pixclk, vco);
9719
9720         /*
9721          * FIXME move the cdclk caclulation to
9722          * compute_config() so we can fail gracegully.
9723          */
9724         if (cdclk > dev_priv->max_cdclk_freq) {
9725                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9726                           cdclk, dev_priv->max_cdclk_freq);
9727                 cdclk = dev_priv->max_cdclk_freq;
9728         }
9729
9730         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9731         if (!intel_state->active_crtcs)
9732                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
9733
9734         return 0;
9735 }
9736
9737 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9738 {
9739         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
9740         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
9741         unsigned int req_cdclk = intel_state->dev_cdclk;
9742         unsigned int req_vco = intel_state->cdclk_pll_vco;
9743
9744         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
9745 }
9746
9747 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9748                                       struct intel_crtc_state *crtc_state)
9749 {
9750         struct intel_encoder *intel_encoder =
9751                 intel_ddi_get_crtc_new_encoder(crtc_state);
9752
9753         if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9754                 if (!intel_ddi_pll_select(crtc, crtc_state))
9755                         return -EINVAL;
9756         }
9757
9758         crtc->lowfreq_avail = false;
9759
9760         return 0;
9761 }
9762
9763 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9764                                 enum port port,
9765                                 struct intel_crtc_state *pipe_config)
9766 {
9767         enum intel_dpll_id id;
9768
9769         switch (port) {
9770         case PORT_A:
9771                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9772                 id = DPLL_ID_SKL_DPLL0;
9773                 break;
9774         case PORT_B:
9775                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9776                 id = DPLL_ID_SKL_DPLL1;
9777                 break;
9778         case PORT_C:
9779                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9780                 id = DPLL_ID_SKL_DPLL2;
9781                 break;
9782         default:
9783                 DRM_ERROR("Incorrect port type\n");
9784                 return;
9785         }
9786
9787         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9788 }
9789
9790 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9791                                 enum port port,
9792                                 struct intel_crtc_state *pipe_config)
9793 {
9794         enum intel_dpll_id id;
9795         u32 temp;
9796
9797         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9798         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9799
9800         switch (pipe_config->ddi_pll_sel) {
9801         case SKL_DPLL0:
9802                 id = DPLL_ID_SKL_DPLL0;
9803                 break;
9804         case SKL_DPLL1:
9805                 id = DPLL_ID_SKL_DPLL1;
9806                 break;
9807         case SKL_DPLL2:
9808                 id = DPLL_ID_SKL_DPLL2;
9809                 break;
9810         case SKL_DPLL3:
9811                 id = DPLL_ID_SKL_DPLL3;
9812                 break;
9813         default:
9814                 MISSING_CASE(pipe_config->ddi_pll_sel);
9815                 return;
9816         }
9817
9818         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9819 }
9820
9821 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9822                                 enum port port,
9823                                 struct intel_crtc_state *pipe_config)
9824 {
9825         enum intel_dpll_id id;
9826
9827         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9828
9829         switch (pipe_config->ddi_pll_sel) {
9830         case PORT_CLK_SEL_WRPLL1:
9831                 id = DPLL_ID_WRPLL1;
9832                 break;
9833         case PORT_CLK_SEL_WRPLL2:
9834                 id = DPLL_ID_WRPLL2;
9835                 break;
9836         case PORT_CLK_SEL_SPLL:
9837                 id = DPLL_ID_SPLL;
9838                 break;
9839         case PORT_CLK_SEL_LCPLL_810:
9840                 id = DPLL_ID_LCPLL_810;
9841                 break;
9842         case PORT_CLK_SEL_LCPLL_1350:
9843                 id = DPLL_ID_LCPLL_1350;
9844                 break;
9845         case PORT_CLK_SEL_LCPLL_2700:
9846                 id = DPLL_ID_LCPLL_2700;
9847                 break;
9848         default:
9849                 MISSING_CASE(pipe_config->ddi_pll_sel);
9850                 /* fall through */
9851         case PORT_CLK_SEL_NONE:
9852                 return;
9853         }
9854
9855         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9856 }
9857
9858 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9859                                      struct intel_crtc_state *pipe_config,
9860                                      unsigned long *power_domain_mask)
9861 {
9862         struct drm_device *dev = crtc->base.dev;
9863         struct drm_i915_private *dev_priv = dev->dev_private;
9864         enum intel_display_power_domain power_domain;
9865         u32 tmp;
9866
9867         /*
9868          * The pipe->transcoder mapping is fixed with the exception of the eDP
9869          * transcoder handled below.
9870          */
9871         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9872
9873         /*
9874          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9875          * consistency and less surprising code; it's in always on power).
9876          */
9877         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9878         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9879                 enum pipe trans_edp_pipe;
9880                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9881                 default:
9882                         WARN(1, "unknown pipe linked to edp transcoder\n");
9883                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9884                 case TRANS_DDI_EDP_INPUT_A_ON:
9885                         trans_edp_pipe = PIPE_A;
9886                         break;
9887                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9888                         trans_edp_pipe = PIPE_B;
9889                         break;
9890                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9891                         trans_edp_pipe = PIPE_C;
9892                         break;
9893                 }
9894
9895                 if (trans_edp_pipe == crtc->pipe)
9896                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9897         }
9898
9899         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9900         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9901                 return false;
9902         *power_domain_mask |= BIT(power_domain);
9903
9904         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9905
9906         return tmp & PIPECONF_ENABLE;
9907 }
9908
9909 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9910                                          struct intel_crtc_state *pipe_config,
9911                                          unsigned long *power_domain_mask)
9912 {
9913         struct drm_device *dev = crtc->base.dev;
9914         struct drm_i915_private *dev_priv = dev->dev_private;
9915         enum intel_display_power_domain power_domain;
9916         enum port port;
9917         enum transcoder cpu_transcoder;
9918         u32 tmp;
9919
9920         pipe_config->has_dsi_encoder = false;
9921
9922         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9923                 if (port == PORT_A)
9924                         cpu_transcoder = TRANSCODER_DSI_A;
9925                 else
9926                         cpu_transcoder = TRANSCODER_DSI_C;
9927
9928                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9929                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9930                         continue;
9931                 *power_domain_mask |= BIT(power_domain);
9932
9933                 /*
9934                  * The PLL needs to be enabled with a valid divider
9935                  * configuration, otherwise accessing DSI registers will hang
9936                  * the machine. See BSpec North Display Engine
9937                  * registers/MIPI[BXT]. We can break out here early, since we
9938                  * need the same DSI PLL to be enabled for both DSI ports.
9939                  */
9940                 if (!intel_dsi_pll_is_enabled(dev_priv))
9941                         break;
9942
9943                 /* XXX: this works for video mode only */
9944                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9945                 if (!(tmp & DPI_ENABLE))
9946                         continue;
9947
9948                 tmp = I915_READ(MIPI_CTRL(port));
9949                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9950                         continue;
9951
9952                 pipe_config->cpu_transcoder = cpu_transcoder;
9953                 pipe_config->has_dsi_encoder = true;
9954                 break;
9955         }
9956
9957         return pipe_config->has_dsi_encoder;
9958 }
9959
9960 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9961                                        struct intel_crtc_state *pipe_config)
9962 {
9963         struct drm_device *dev = crtc->base.dev;
9964         struct drm_i915_private *dev_priv = dev->dev_private;
9965         struct intel_shared_dpll *pll;
9966         enum port port;
9967         uint32_t tmp;
9968
9969         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9970
9971         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9972
9973         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9974                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9975         else if (IS_BROXTON(dev))
9976                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9977         else
9978                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9979
9980         pll = pipe_config->shared_dpll;
9981         if (pll) {
9982                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9983                                                  &pipe_config->dpll_hw_state));
9984         }
9985
9986         /*
9987          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9988          * DDI E. So just check whether this pipe is wired to DDI E and whether
9989          * the PCH transcoder is on.
9990          */
9991         if (INTEL_INFO(dev)->gen < 9 &&
9992             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9993                 pipe_config->has_pch_encoder = true;
9994
9995                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9996                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9997                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9998
9999                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10000         }
10001 }
10002
10003 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10004                                     struct intel_crtc_state *pipe_config)
10005 {
10006         struct drm_device *dev = crtc->base.dev;
10007         struct drm_i915_private *dev_priv = dev->dev_private;
10008         enum intel_display_power_domain power_domain;
10009         unsigned long power_domain_mask;
10010         bool active;
10011
10012         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10013         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10014                 return false;
10015         power_domain_mask = BIT(power_domain);
10016
10017         pipe_config->shared_dpll = NULL;
10018
10019         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10020
10021         if (IS_BROXTON(dev_priv)) {
10022                 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10023                                              &power_domain_mask);
10024                 WARN_ON(active && pipe_config->has_dsi_encoder);
10025                 if (pipe_config->has_dsi_encoder)
10026                         active = true;
10027         }
10028
10029         if (!active)
10030                 goto out;
10031
10032         if (!pipe_config->has_dsi_encoder) {
10033                 haswell_get_ddi_port_state(crtc, pipe_config);
10034                 intel_get_pipe_timings(crtc, pipe_config);
10035         }
10036
10037         intel_get_pipe_src_size(crtc, pipe_config);
10038
10039         pipe_config->gamma_mode =
10040                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10041
10042         if (INTEL_INFO(dev)->gen >= 9) {
10043                 skl_init_scalers(dev, crtc, pipe_config);
10044         }
10045
10046         if (INTEL_INFO(dev)->gen >= 9) {
10047                 pipe_config->scaler_state.scaler_id = -1;
10048                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10049         }
10050
10051         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10052         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10053                 power_domain_mask |= BIT(power_domain);
10054                 if (INTEL_INFO(dev)->gen >= 9)
10055                         skylake_get_pfit_config(crtc, pipe_config);
10056                 else
10057                         ironlake_get_pfit_config(crtc, pipe_config);
10058         }
10059
10060         if (IS_HASWELL(dev))
10061                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10062                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10063
10064         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10065             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10066                 pipe_config->pixel_multiplier =
10067                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10068         } else {
10069                 pipe_config->pixel_multiplier = 1;
10070         }
10071
10072 out:
10073         for_each_power_domain(power_domain, power_domain_mask)
10074                 intel_display_power_put(dev_priv, power_domain);
10075
10076         return active;
10077 }
10078
10079 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10080                                const struct intel_plane_state *plane_state)
10081 {
10082         struct drm_device *dev = crtc->dev;
10083         struct drm_i915_private *dev_priv = dev->dev_private;
10084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10085         uint32_t cntl = 0, size = 0;
10086
10087         if (plane_state && plane_state->visible) {
10088                 unsigned int width = plane_state->base.crtc_w;
10089                 unsigned int height = plane_state->base.crtc_h;
10090                 unsigned int stride = roundup_pow_of_two(width) * 4;
10091
10092                 switch (stride) {
10093                 default:
10094                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10095                                   width, stride);
10096                         stride = 256;
10097                         /* fallthrough */
10098                 case 256:
10099                 case 512:
10100                 case 1024:
10101                 case 2048:
10102                         break;
10103                 }
10104
10105                 cntl |= CURSOR_ENABLE |
10106                         CURSOR_GAMMA_ENABLE |
10107                         CURSOR_FORMAT_ARGB |
10108                         CURSOR_STRIDE(stride);
10109
10110                 size = (height << 12) | width;
10111         }
10112
10113         if (intel_crtc->cursor_cntl != 0 &&
10114             (intel_crtc->cursor_base != base ||
10115              intel_crtc->cursor_size != size ||
10116              intel_crtc->cursor_cntl != cntl)) {
10117                 /* On these chipsets we can only modify the base/size/stride
10118                  * whilst the cursor is disabled.
10119                  */
10120                 I915_WRITE(CURCNTR(PIPE_A), 0);
10121                 POSTING_READ(CURCNTR(PIPE_A));
10122                 intel_crtc->cursor_cntl = 0;
10123         }
10124
10125         if (intel_crtc->cursor_base != base) {
10126                 I915_WRITE(CURBASE(PIPE_A), base);
10127                 intel_crtc->cursor_base = base;
10128         }
10129
10130         if (intel_crtc->cursor_size != size) {
10131                 I915_WRITE(CURSIZE, size);
10132                 intel_crtc->cursor_size = size;
10133         }
10134
10135         if (intel_crtc->cursor_cntl != cntl) {
10136                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10137                 POSTING_READ(CURCNTR(PIPE_A));
10138                 intel_crtc->cursor_cntl = cntl;
10139         }
10140 }
10141
10142 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10143                                const struct intel_plane_state *plane_state)
10144 {
10145         struct drm_device *dev = crtc->dev;
10146         struct drm_i915_private *dev_priv = dev->dev_private;
10147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10148         int pipe = intel_crtc->pipe;
10149         uint32_t cntl = 0;
10150
10151         if (plane_state && plane_state->visible) {
10152                 cntl = MCURSOR_GAMMA_ENABLE;
10153                 switch (plane_state->base.crtc_w) {
10154                         case 64:
10155                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10156                                 break;
10157                         case 128:
10158                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10159                                 break;
10160                         case 256:
10161                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10162                                 break;
10163                         default:
10164                                 MISSING_CASE(plane_state->base.crtc_w);
10165                                 return;
10166                 }
10167                 cntl |= pipe << 28; /* Connect to correct pipe */
10168
10169                 if (HAS_DDI(dev))
10170                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10171
10172                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10173                         cntl |= CURSOR_ROTATE_180;
10174         }
10175
10176         if (intel_crtc->cursor_cntl != cntl) {
10177                 I915_WRITE(CURCNTR(pipe), cntl);
10178                 POSTING_READ(CURCNTR(pipe));
10179                 intel_crtc->cursor_cntl = cntl;
10180         }
10181
10182         /* and commit changes on next vblank */
10183         I915_WRITE(CURBASE(pipe), base);
10184         POSTING_READ(CURBASE(pipe));
10185
10186         intel_crtc->cursor_base = base;
10187 }
10188
10189 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10190 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10191                                      const struct intel_plane_state *plane_state)
10192 {
10193         struct drm_device *dev = crtc->dev;
10194         struct drm_i915_private *dev_priv = dev->dev_private;
10195         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10196         int pipe = intel_crtc->pipe;
10197         u32 base = intel_crtc->cursor_addr;
10198         u32 pos = 0;
10199
10200         if (plane_state) {
10201                 int x = plane_state->base.crtc_x;
10202                 int y = plane_state->base.crtc_y;
10203
10204                 if (x < 0) {
10205                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10206                         x = -x;
10207                 }
10208                 pos |= x << CURSOR_X_SHIFT;
10209
10210                 if (y < 0) {
10211                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10212                         y = -y;
10213                 }
10214                 pos |= y << CURSOR_Y_SHIFT;
10215
10216                 /* ILK+ do this automagically */
10217                 if (HAS_GMCH_DISPLAY(dev) &&
10218                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10219                         base += (plane_state->base.crtc_h *
10220                                  plane_state->base.crtc_w - 1) * 4;
10221                 }
10222         }
10223
10224         I915_WRITE(CURPOS(pipe), pos);
10225
10226         if (IS_845G(dev) || IS_I865G(dev))
10227                 i845_update_cursor(crtc, base, plane_state);
10228         else
10229                 i9xx_update_cursor(crtc, base, plane_state);
10230 }
10231
10232 static bool cursor_size_ok(struct drm_device *dev,
10233                            uint32_t width, uint32_t height)
10234 {
10235         if (width == 0 || height == 0)
10236                 return false;
10237
10238         /*
10239          * 845g/865g are special in that they are only limited by
10240          * the width of their cursors, the height is arbitrary up to
10241          * the precision of the register. Everything else requires
10242          * square cursors, limited to a few power-of-two sizes.
10243          */
10244         if (IS_845G(dev) || IS_I865G(dev)) {
10245                 if ((width & 63) != 0)
10246                         return false;
10247
10248                 if (width > (IS_845G(dev) ? 64 : 512))
10249                         return false;
10250
10251                 if (height > 1023)
10252                         return false;
10253         } else {
10254                 switch (width | height) {
10255                 case 256:
10256                 case 128:
10257                         if (IS_GEN2(dev))
10258                                 return false;
10259                 case 64:
10260                         break;
10261                 default:
10262                         return false;
10263                 }
10264         }
10265
10266         return true;
10267 }
10268
10269 /* VESA 640x480x72Hz mode to set on the pipe */
10270 static struct drm_display_mode load_detect_mode = {
10271         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10272                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10273 };
10274
10275 struct drm_framebuffer *
10276 __intel_framebuffer_create(struct drm_device *dev,
10277                            struct drm_mode_fb_cmd2 *mode_cmd,
10278                            struct drm_i915_gem_object *obj)
10279 {
10280         struct intel_framebuffer *intel_fb;
10281         int ret;
10282
10283         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10284         if (!intel_fb)
10285                 return ERR_PTR(-ENOMEM);
10286
10287         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10288         if (ret)
10289                 goto err;
10290
10291         return &intel_fb->base;
10292
10293 err:
10294         kfree(intel_fb);
10295         return ERR_PTR(ret);
10296 }
10297
10298 static struct drm_framebuffer *
10299 intel_framebuffer_create(struct drm_device *dev,
10300                          struct drm_mode_fb_cmd2 *mode_cmd,
10301                          struct drm_i915_gem_object *obj)
10302 {
10303         struct drm_framebuffer *fb;
10304         int ret;
10305
10306         ret = i915_mutex_lock_interruptible(dev);
10307         if (ret)
10308                 return ERR_PTR(ret);
10309         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10310         mutex_unlock(&dev->struct_mutex);
10311
10312         return fb;
10313 }
10314
10315 static u32
10316 intel_framebuffer_pitch_for_width(int width, int bpp)
10317 {
10318         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10319         return ALIGN(pitch, 64);
10320 }
10321
10322 static u32
10323 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10324 {
10325         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10326         return PAGE_ALIGN(pitch * mode->vdisplay);
10327 }
10328
10329 static struct drm_framebuffer *
10330 intel_framebuffer_create_for_mode(struct drm_device *dev,
10331                                   struct drm_display_mode *mode,
10332                                   int depth, int bpp)
10333 {
10334         struct drm_framebuffer *fb;
10335         struct drm_i915_gem_object *obj;
10336         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10337
10338         obj = i915_gem_object_create(dev,
10339                                     intel_framebuffer_size_for_mode(mode, bpp));
10340         if (IS_ERR(obj))
10341                 return ERR_CAST(obj);
10342
10343         mode_cmd.width = mode->hdisplay;
10344         mode_cmd.height = mode->vdisplay;
10345         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10346                                                                 bpp);
10347         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10348
10349         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10350         if (IS_ERR(fb))
10351                 drm_gem_object_unreference_unlocked(&obj->base);
10352
10353         return fb;
10354 }
10355
10356 static struct drm_framebuffer *
10357 mode_fits_in_fbdev(struct drm_device *dev,
10358                    struct drm_display_mode *mode)
10359 {
10360 #ifdef CONFIG_DRM_FBDEV_EMULATION
10361         struct drm_i915_private *dev_priv = dev->dev_private;
10362         struct drm_i915_gem_object *obj;
10363         struct drm_framebuffer *fb;
10364
10365         if (!dev_priv->fbdev)
10366                 return NULL;
10367
10368         if (!dev_priv->fbdev->fb)
10369                 return NULL;
10370
10371         obj = dev_priv->fbdev->fb->obj;
10372         BUG_ON(!obj);
10373
10374         fb = &dev_priv->fbdev->fb->base;
10375         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10376                                                                fb->bits_per_pixel))
10377                 return NULL;
10378
10379         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10380                 return NULL;
10381
10382         drm_framebuffer_reference(fb);
10383         return fb;
10384 #else
10385         return NULL;
10386 #endif
10387 }
10388
10389 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10390                                            struct drm_crtc *crtc,
10391                                            struct drm_display_mode *mode,
10392                                            struct drm_framebuffer *fb,
10393                                            int x, int y)
10394 {
10395         struct drm_plane_state *plane_state;
10396         int hdisplay, vdisplay;
10397         int ret;
10398
10399         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10400         if (IS_ERR(plane_state))
10401                 return PTR_ERR(plane_state);
10402
10403         if (mode)
10404                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10405         else
10406                 hdisplay = vdisplay = 0;
10407
10408         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10409         if (ret)
10410                 return ret;
10411         drm_atomic_set_fb_for_plane(plane_state, fb);
10412         plane_state->crtc_x = 0;
10413         plane_state->crtc_y = 0;
10414         plane_state->crtc_w = hdisplay;
10415         plane_state->crtc_h = vdisplay;
10416         plane_state->src_x = x << 16;
10417         plane_state->src_y = y << 16;
10418         plane_state->src_w = hdisplay << 16;
10419         plane_state->src_h = vdisplay << 16;
10420
10421         return 0;
10422 }
10423
10424 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10425                                 struct drm_display_mode *mode,
10426                                 struct intel_load_detect_pipe *old,
10427                                 struct drm_modeset_acquire_ctx *ctx)
10428 {
10429         struct intel_crtc *intel_crtc;
10430         struct intel_encoder *intel_encoder =
10431                 intel_attached_encoder(connector);
10432         struct drm_crtc *possible_crtc;
10433         struct drm_encoder *encoder = &intel_encoder->base;
10434         struct drm_crtc *crtc = NULL;
10435         struct drm_device *dev = encoder->dev;
10436         struct drm_framebuffer *fb;
10437         struct drm_mode_config *config = &dev->mode_config;
10438         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10439         struct drm_connector_state *connector_state;
10440         struct intel_crtc_state *crtc_state;
10441         int ret, i = -1;
10442
10443         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10444                       connector->base.id, connector->name,
10445                       encoder->base.id, encoder->name);
10446
10447         old->restore_state = NULL;
10448
10449 retry:
10450         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10451         if (ret)
10452                 goto fail;
10453
10454         /*
10455          * Algorithm gets a little messy:
10456          *
10457          *   - if the connector already has an assigned crtc, use it (but make
10458          *     sure it's on first)
10459          *
10460          *   - try to find the first unused crtc that can drive this connector,
10461          *     and use that if we find one
10462          */
10463
10464         /* See if we already have a CRTC for this connector */
10465         if (connector->state->crtc) {
10466                 crtc = connector->state->crtc;
10467
10468                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10469                 if (ret)
10470                         goto fail;
10471
10472                 /* Make sure the crtc and connector are running */
10473                 goto found;
10474         }
10475
10476         /* Find an unused one (if possible) */
10477         for_each_crtc(dev, possible_crtc) {
10478                 i++;
10479                 if (!(encoder->possible_crtcs & (1 << i)))
10480                         continue;
10481
10482                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10483                 if (ret)
10484                         goto fail;
10485
10486                 if (possible_crtc->state->enable) {
10487                         drm_modeset_unlock(&possible_crtc->mutex);
10488                         continue;
10489                 }
10490
10491                 crtc = possible_crtc;
10492                 break;
10493         }
10494
10495         /*
10496          * If we didn't find an unused CRTC, don't use any.
10497          */
10498         if (!crtc) {
10499                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10500                 goto fail;
10501         }
10502
10503 found:
10504         intel_crtc = to_intel_crtc(crtc);
10505
10506         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10507         if (ret)
10508                 goto fail;
10509
10510         state = drm_atomic_state_alloc(dev);
10511         restore_state = drm_atomic_state_alloc(dev);
10512         if (!state || !restore_state) {
10513                 ret = -ENOMEM;
10514                 goto fail;
10515         }
10516
10517         state->acquire_ctx = ctx;
10518         restore_state->acquire_ctx = ctx;
10519
10520         connector_state = drm_atomic_get_connector_state(state, connector);
10521         if (IS_ERR(connector_state)) {
10522                 ret = PTR_ERR(connector_state);
10523                 goto fail;
10524         }
10525
10526         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10527         if (ret)
10528                 goto fail;
10529
10530         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10531         if (IS_ERR(crtc_state)) {
10532                 ret = PTR_ERR(crtc_state);
10533                 goto fail;
10534         }
10535
10536         crtc_state->base.active = crtc_state->base.enable = true;
10537
10538         if (!mode)
10539                 mode = &load_detect_mode;
10540
10541         /* We need a framebuffer large enough to accommodate all accesses
10542          * that the plane may generate whilst we perform load detection.
10543          * We can not rely on the fbcon either being present (we get called
10544          * during its initialisation to detect all boot displays, or it may
10545          * not even exist) or that it is large enough to satisfy the
10546          * requested mode.
10547          */
10548         fb = mode_fits_in_fbdev(dev, mode);
10549         if (fb == NULL) {
10550                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10551                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10552         } else
10553                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10554         if (IS_ERR(fb)) {
10555                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10556                 goto fail;
10557         }
10558
10559         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10560         if (ret)
10561                 goto fail;
10562
10563         drm_framebuffer_unreference(fb);
10564
10565         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10566         if (ret)
10567                 goto fail;
10568
10569         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10570         if (!ret)
10571                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10572         if (!ret)
10573                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10574         if (ret) {
10575                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10576                 goto fail;
10577         }
10578
10579         ret = drm_atomic_commit(state);
10580         if (ret) {
10581                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10582                 goto fail;
10583         }
10584
10585         old->restore_state = restore_state;
10586
10587         /* let the connector get through one full cycle before testing */
10588         intel_wait_for_vblank(dev, intel_crtc->pipe);
10589         return true;
10590
10591 fail:
10592         drm_atomic_state_free(state);
10593         drm_atomic_state_free(restore_state);
10594         restore_state = state = NULL;
10595
10596         if (ret == -EDEADLK) {
10597                 drm_modeset_backoff(ctx);
10598                 goto retry;
10599         }
10600
10601         return false;
10602 }
10603
10604 void intel_release_load_detect_pipe(struct drm_connector *connector,
10605                                     struct intel_load_detect_pipe *old,
10606                                     struct drm_modeset_acquire_ctx *ctx)
10607 {
10608         struct intel_encoder *intel_encoder =
10609                 intel_attached_encoder(connector);
10610         struct drm_encoder *encoder = &intel_encoder->base;
10611         struct drm_atomic_state *state = old->restore_state;
10612         int ret;
10613
10614         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10615                       connector->base.id, connector->name,
10616                       encoder->base.id, encoder->name);
10617
10618         if (!state)
10619                 return;
10620
10621         ret = drm_atomic_commit(state);
10622         if (ret) {
10623                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10624                 drm_atomic_state_free(state);
10625         }
10626 }
10627
10628 static int i9xx_pll_refclk(struct drm_device *dev,
10629                            const struct intel_crtc_state *pipe_config)
10630 {
10631         struct drm_i915_private *dev_priv = dev->dev_private;
10632         u32 dpll = pipe_config->dpll_hw_state.dpll;
10633
10634         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10635                 return dev_priv->vbt.lvds_ssc_freq;
10636         else if (HAS_PCH_SPLIT(dev))
10637                 return 120000;
10638         else if (!IS_GEN2(dev))
10639                 return 96000;
10640         else
10641                 return 48000;
10642 }
10643
10644 /* Returns the clock of the currently programmed mode of the given pipe. */
10645 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10646                                 struct intel_crtc_state *pipe_config)
10647 {
10648         struct drm_device *dev = crtc->base.dev;
10649         struct drm_i915_private *dev_priv = dev->dev_private;
10650         int pipe = pipe_config->cpu_transcoder;
10651         u32 dpll = pipe_config->dpll_hw_state.dpll;
10652         u32 fp;
10653         struct dpll clock;
10654         int port_clock;
10655         int refclk = i9xx_pll_refclk(dev, pipe_config);
10656
10657         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10658                 fp = pipe_config->dpll_hw_state.fp0;
10659         else
10660                 fp = pipe_config->dpll_hw_state.fp1;
10661
10662         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10663         if (IS_PINEVIEW(dev)) {
10664                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10665                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10666         } else {
10667                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10668                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10669         }
10670
10671         if (!IS_GEN2(dev)) {
10672                 if (IS_PINEVIEW(dev))
10673                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10674                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10675                 else
10676                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10677                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10678
10679                 switch (dpll & DPLL_MODE_MASK) {
10680                 case DPLLB_MODE_DAC_SERIAL:
10681                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10682                                 5 : 10;
10683                         break;
10684                 case DPLLB_MODE_LVDS:
10685                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10686                                 7 : 14;
10687                         break;
10688                 default:
10689                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10690                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10691                         return;
10692                 }
10693
10694                 if (IS_PINEVIEW(dev))
10695                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10696                 else
10697                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10698         } else {
10699                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10700                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10701
10702                 if (is_lvds) {
10703                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10704                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10705
10706                         if (lvds & LVDS_CLKB_POWER_UP)
10707                                 clock.p2 = 7;
10708                         else
10709                                 clock.p2 = 14;
10710                 } else {
10711                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10712                                 clock.p1 = 2;
10713                         else {
10714                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10715                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10716                         }
10717                         if (dpll & PLL_P2_DIVIDE_BY_4)
10718                                 clock.p2 = 4;
10719                         else
10720                                 clock.p2 = 2;
10721                 }
10722
10723                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10724         }
10725
10726         /*
10727          * This value includes pixel_multiplier. We will use
10728          * port_clock to compute adjusted_mode.crtc_clock in the
10729          * encoder's get_config() function.
10730          */
10731         pipe_config->port_clock = port_clock;
10732 }
10733
10734 int intel_dotclock_calculate(int link_freq,
10735                              const struct intel_link_m_n *m_n)
10736 {
10737         /*
10738          * The calculation for the data clock is:
10739          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10740          * But we want to avoid losing precison if possible, so:
10741          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10742          *
10743          * and the link clock is simpler:
10744          * link_clock = (m * link_clock) / n
10745          */
10746
10747         if (!m_n->link_n)
10748                 return 0;
10749
10750         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10751 }
10752
10753 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10754                                    struct intel_crtc_state *pipe_config)
10755 {
10756         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10757
10758         /* read out port_clock from the DPLL */
10759         i9xx_crtc_clock_get(crtc, pipe_config);
10760
10761         /*
10762          * In case there is an active pipe without active ports,
10763          * we may need some idea for the dotclock anyway.
10764          * Calculate one based on the FDI configuration.
10765          */
10766         pipe_config->base.adjusted_mode.crtc_clock =
10767                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10768                                          &pipe_config->fdi_m_n);
10769 }
10770
10771 /** Returns the currently programmed mode of the given pipe. */
10772 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10773                                              struct drm_crtc *crtc)
10774 {
10775         struct drm_i915_private *dev_priv = dev->dev_private;
10776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10777         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10778         struct drm_display_mode *mode;
10779         struct intel_crtc_state *pipe_config;
10780         int htot = I915_READ(HTOTAL(cpu_transcoder));
10781         int hsync = I915_READ(HSYNC(cpu_transcoder));
10782         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10783         int vsync = I915_READ(VSYNC(cpu_transcoder));
10784         enum pipe pipe = intel_crtc->pipe;
10785
10786         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10787         if (!mode)
10788                 return NULL;
10789
10790         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10791         if (!pipe_config) {
10792                 kfree(mode);
10793                 return NULL;
10794         }
10795
10796         /*
10797          * Construct a pipe_config sufficient for getting the clock info
10798          * back out of crtc_clock_get.
10799          *
10800          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10801          * to use a real value here instead.
10802          */
10803         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10804         pipe_config->pixel_multiplier = 1;
10805         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10806         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10807         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10808         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10809
10810         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10811         mode->hdisplay = (htot & 0xffff) + 1;
10812         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10813         mode->hsync_start = (hsync & 0xffff) + 1;
10814         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10815         mode->vdisplay = (vtot & 0xffff) + 1;
10816         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10817         mode->vsync_start = (vsync & 0xffff) + 1;
10818         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10819
10820         drm_mode_set_name(mode);
10821
10822         kfree(pipe_config);
10823
10824         return mode;
10825 }
10826
10827 void intel_mark_busy(struct drm_i915_private *dev_priv)
10828 {
10829         if (dev_priv->mm.busy)
10830                 return;
10831
10832         intel_runtime_pm_get(dev_priv);
10833         i915_update_gfx_val(dev_priv);
10834         if (INTEL_GEN(dev_priv) >= 6)
10835                 gen6_rps_busy(dev_priv);
10836         dev_priv->mm.busy = true;
10837 }
10838
10839 void intel_mark_idle(struct drm_i915_private *dev_priv)
10840 {
10841         if (!dev_priv->mm.busy)
10842                 return;
10843
10844         dev_priv->mm.busy = false;
10845
10846         if (INTEL_GEN(dev_priv) >= 6)
10847                 gen6_rps_idle(dev_priv);
10848
10849         intel_runtime_pm_put(dev_priv);
10850 }
10851
10852 void intel_free_flip_work(struct intel_flip_work *work)
10853 {
10854         kfree(work->old_connector_state);
10855         kfree(work->new_connector_state);
10856         kfree(work);
10857 }
10858
10859 static void intel_crtc_destroy(struct drm_crtc *crtc)
10860 {
10861         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10862         struct drm_device *dev = crtc->dev;
10863         struct intel_flip_work *work;
10864
10865         spin_lock_irq(&dev->event_lock);
10866         while (!list_empty(&intel_crtc->flip_work)) {
10867                 work = list_first_entry(&intel_crtc->flip_work,
10868                                         struct intel_flip_work, head);
10869                 list_del_init(&work->head);
10870                 spin_unlock_irq(&dev->event_lock);
10871
10872                 cancel_work_sync(&work->mmio_work);
10873                 cancel_work_sync(&work->unpin_work);
10874                 intel_free_flip_work(work);
10875
10876                 spin_lock_irq(&dev->event_lock);
10877         }
10878         spin_unlock_irq(&dev->event_lock);
10879
10880         drm_crtc_cleanup(crtc);
10881
10882         kfree(intel_crtc);
10883 }
10884
10885 static void intel_crtc_post_flip_update(struct intel_flip_work *work,
10886                                         struct drm_crtc *crtc)
10887 {
10888         struct intel_crtc_state *crtc_state = work->new_crtc_state;
10889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10890
10891         if (crtc_state->disable_cxsr)
10892                 intel_crtc->wm.cxsr_allowed = true;
10893
10894         if (crtc_state->update_wm_post && crtc_state->base.active)
10895                 intel_update_watermarks(crtc);
10896
10897         if (work->num_planes > 0 &&
10898             work->old_plane_state[0]->base.plane == crtc->primary) {
10899                 struct intel_plane_state *plane_state =
10900                         work->new_plane_state[0];
10901
10902                 if (plane_state->visible &&
10903                     (needs_modeset(&crtc_state->base) ||
10904                      !work->old_plane_state[0]->visible))
10905                         intel_post_enable_primary(crtc);
10906         }
10907 }
10908
10909 static void intel_unpin_work_fn(struct work_struct *__work)
10910 {
10911         struct intel_flip_work *work =
10912                 container_of(__work, struct intel_flip_work, unpin_work);
10913         struct drm_crtc *crtc = work->old_crtc_state->base.crtc;
10914         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10915         struct drm_device *dev = crtc->dev;
10916         struct drm_i915_private *dev_priv = dev->dev_private;
10917         int i;
10918
10919         if (work->fb_bits)
10920                 intel_frontbuffer_flip_complete(dev, work->fb_bits);
10921
10922         /*
10923          * Unless work->can_async_unpin is false, there's no way to ensure
10924          * that work->new_crtc_state contains valid memory during unpin
10925          * because intel_atomic_commit may free it before this runs.
10926          */
10927         if (!work->can_async_unpin) {
10928                 intel_crtc_post_flip_update(work, crtc);
10929
10930                 if (dev_priv->display.optimize_watermarks)
10931                         dev_priv->display.optimize_watermarks(work->new_crtc_state);
10932         }
10933
10934         if (work->fb_bits & to_intel_plane(crtc->primary)->frontbuffer_bit)
10935                 intel_fbc_post_update(intel_crtc);
10936
10937         if (work->put_power_domains)
10938                 modeset_put_power_domains(dev_priv, work->put_power_domains);
10939
10940         /* Make sure mmio work is completely finished before freeing all state here. */
10941         flush_work(&work->mmio_work);
10942
10943         if (!work->can_async_unpin &&
10944             (work->new_crtc_state->update_pipe ||
10945              needs_modeset(&work->new_crtc_state->base))) {
10946                 /* This must be called before work is unpinned for serialization. */
10947                 intel_modeset_verify_crtc(crtc, &work->old_crtc_state->base,
10948                                           &work->new_crtc_state->base);
10949
10950                 for (i = 0; i < work->num_new_connectors; i++) {
10951                         struct drm_connector_state *conn_state =
10952                                 work->new_connector_state[i];
10953                         struct drm_connector *con = conn_state->connector;
10954
10955                         WARN_ON(!con);
10956
10957                         intel_connector_verify_state(to_intel_connector(con),
10958                                                      conn_state);
10959                 }
10960         }
10961
10962         for (i = 0; i < work->num_old_connectors; i++) {
10963                 struct drm_connector_state *old_con_state =
10964                         work->old_connector_state[i];
10965                 struct drm_connector *con =
10966                         old_con_state->connector;
10967
10968                 con->funcs->atomic_destroy_state(con, old_con_state);
10969         }
10970
10971         if (!work->can_async_unpin || !list_empty(&work->head)) {
10972                 spin_lock_irq(&dev->event_lock);
10973                 WARN(list_empty(&work->head) != work->can_async_unpin,
10974                      "[CRTC:%i] Pin work %p async %i with %i planes, active %i -> %i ms %i\n",
10975                      crtc->base.id, work, work->can_async_unpin, work->num_planes,
10976                      work->old_crtc_state->base.active, work->new_crtc_state->base.active,
10977                      needs_modeset(&work->new_crtc_state->base));
10978
10979                 if (!list_empty(&work->head))
10980                         list_del(&work->head);
10981
10982                 wake_up_all(&dev_priv->pending_flip_queue);
10983                 spin_unlock_irq(&dev->event_lock);
10984         }
10985
10986         /* New crtc_state freed? */
10987         if (work->free_new_crtc_state)
10988                 intel_crtc_destroy_state(crtc, &work->new_crtc_state->base);
10989
10990         intel_crtc_destroy_state(crtc, &work->old_crtc_state->base);
10991
10992         for (i = 0; i < work->num_planes; i++) {
10993                 struct intel_plane_state *old_plane_state =
10994                         work->old_plane_state[i];
10995                 struct drm_framebuffer *old_fb = old_plane_state->base.fb;
10996                 struct drm_plane *plane = old_plane_state->base.plane;
10997                 struct drm_i915_gem_request *req;
10998
10999                 req = old_plane_state->wait_req;
11000                 old_plane_state->wait_req = NULL;
11001                 if (req)
11002                         i915_gem_request_unreference(req);
11003
11004                 fence_put(old_plane_state->base.fence);
11005                 old_plane_state->base.fence = NULL;
11006
11007                 if (old_fb &&
11008                     (plane->type != DRM_PLANE_TYPE_CURSOR ||
11009                      !INTEL_INFO(dev_priv)->cursor_needs_physical)) {
11010                         mutex_lock(&dev->struct_mutex);
11011                         intel_unpin_fb_obj(old_fb, old_plane_state->base.rotation);
11012                         mutex_unlock(&dev->struct_mutex);
11013                 }
11014
11015                 intel_plane_destroy_state(plane, &old_plane_state->base);
11016         }
11017
11018         if (!WARN_ON(atomic_read(&intel_crtc->unpin_work_count) == 0))
11019                 atomic_dec(&intel_crtc->unpin_work_count);
11020
11021         intel_free_flip_work(work);
11022 }
11023
11024
11025 static bool pageflip_finished(struct intel_crtc *crtc,
11026                               struct intel_flip_work *work)
11027 {
11028         if (!atomic_read(&work->pending))
11029                 return false;
11030
11031         smp_rmb();
11032
11033         /*
11034          * MMIO work completes when vblank is different from
11035          * flip_queued_vblank.
11036          */
11037         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11038 }
11039
11040 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11041 {
11042         struct drm_device *dev = dev_priv->dev;
11043         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11044         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11045         struct intel_flip_work *work;
11046         unsigned long flags;
11047
11048         /* Ignore early vblank irqs */
11049         if (!crtc)
11050                 return;
11051
11052         /*
11053          * This is called both by irq handlers and the reset code (to complete
11054          * lost pageflips) so needs the full irqsave spinlocks.
11055          */
11056         spin_lock_irqsave(&dev->event_lock, flags);
11057         while (!list_empty(&intel_crtc->flip_work)) {
11058                 work = list_first_entry(&intel_crtc->flip_work,
11059                                         struct intel_flip_work,
11060                                         head);
11061
11062                 if (!pageflip_finished(intel_crtc, work) ||
11063                     work_busy(&work->unpin_work))
11064                         break;
11065
11066                 page_flip_completed(intel_crtc, work);
11067         }
11068         spin_unlock_irqrestore(&dev->event_lock, flags);
11069 }
11070
11071 static void intel_mmio_flip_work_func(struct work_struct *w)
11072 {
11073         struct intel_flip_work *work =
11074                 container_of(w, struct intel_flip_work, mmio_work);
11075         struct drm_crtc *crtc = work->old_crtc_state->base.crtc;
11076         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11077         struct intel_crtc_state *crtc_state = work->new_crtc_state;
11078         struct drm_device *dev = crtc->dev;
11079         struct drm_i915_private *dev_priv = dev->dev_private;
11080         struct drm_i915_gem_request *req;
11081         int i, ret;
11082
11083         if (!needs_modeset(&crtc_state->base) && crtc_state->update_pipe) {
11084                 work->put_power_domains =
11085                         modeset_get_crtc_power_domains(crtc, crtc_state);
11086         }
11087
11088         for (i = 0; i < work->num_planes; i++) {
11089                 struct intel_plane_state *old_plane_state = work->old_plane_state[i];
11090
11091                 /* For framebuffer backed by dmabuf, wait for fence */
11092                 if (old_plane_state->base.fence)
11093                         WARN_ON(fence_wait(old_plane_state->base.fence, false) < 0);
11094
11095                 req = old_plane_state->wait_req;
11096                 if (!req)
11097                         continue;
11098
11099                 WARN_ON(__i915_wait_request(req, false, NULL,
11100                                             &dev_priv->rps.mmioflips));
11101         }
11102
11103         ret = drm_crtc_vblank_get(crtc);
11104         I915_STATE_WARN(ret < 0, "enabling vblank failed with %i\n", ret);
11105
11106         if (work->num_planes &&
11107             work->old_plane_state[0]->base.plane == crtc->primary)
11108                 intel_fbc_enable(intel_crtc, work->new_crtc_state, work->new_plane_state[0]);
11109
11110         intel_frontbuffer_flip_prepare(dev, work->fb_bits);
11111
11112         intel_pipe_update_start(intel_crtc);
11113         if (!needs_modeset(&crtc_state->base)) {
11114                 if (crtc_state->base.color_mgmt_changed || crtc_state->update_pipe) {
11115                         intel_color_set_csc(&crtc_state->base);
11116                         intel_color_load_luts(&crtc_state->base);
11117                 }
11118
11119                 if (crtc_state->update_pipe)
11120                         intel_update_pipe_config(intel_crtc, work->old_crtc_state);
11121                 else if (INTEL_INFO(dev)->gen >= 9)
11122                         skl_detach_scalers(intel_crtc);
11123         }
11124
11125         for (i = 0; i < work->num_planes; i++) {
11126                 struct intel_plane_state *new_plane_state = work->new_plane_state[i];
11127                 struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
11128
11129                 if (new_plane_state->visible)
11130                         plane->update_plane(&plane->base, crtc_state, new_plane_state);
11131                 else
11132                         plane->disable_plane(&plane->base, crtc);
11133         }
11134
11135         intel_pipe_update_end(intel_crtc, work);
11136 }
11137
11138 /**
11139  * intel_wm_need_update - Check whether watermarks need updating
11140  * @plane: drm plane
11141  * @state: new plane state
11142  *
11143  * Check current plane state versus the new one to determine whether
11144  * watermarks need to be recalculated.
11145  *
11146  * Returns true or false.
11147  */
11148 static bool intel_wm_need_update(struct drm_plane *plane,
11149                                  struct drm_plane_state *state)
11150 {
11151         struct intel_plane_state *new = to_intel_plane_state(state);
11152         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11153
11154         /* Update watermarks on tiling or size changes. */
11155         if (new->visible != cur->visible)
11156                 return true;
11157
11158         if (!cur->base.fb || !new->base.fb)
11159                 return false;
11160
11161         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11162             cur->base.rotation != new->base.rotation ||
11163             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11164             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11165             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11166             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11167                 return true;
11168
11169         return false;
11170 }
11171
11172 static bool needs_scaling(struct intel_plane_state *state)
11173 {
11174         int src_w = drm_rect_width(&state->src) >> 16;
11175         int src_h = drm_rect_height(&state->src) >> 16;
11176         int dst_w = drm_rect_width(&state->dst);
11177         int dst_h = drm_rect_height(&state->dst);
11178
11179         return (src_w != dst_w || src_h != dst_h);
11180 }
11181
11182 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11183                                     struct drm_plane_state *plane_state)
11184 {
11185         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11186         struct drm_crtc *crtc = crtc_state->crtc;
11187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11188         struct drm_plane *plane = plane_state->plane;
11189         struct drm_device *dev = crtc->dev;
11190         struct drm_i915_private *dev_priv = to_i915(dev);
11191         struct intel_plane_state *old_plane_state =
11192                 to_intel_plane_state(plane->state);
11193         int idx = intel_crtc->base.base.id, ret;
11194         bool mode_changed = needs_modeset(crtc_state);
11195         bool was_crtc_enabled = crtc->state->active;
11196         bool is_crtc_enabled = crtc_state->active;
11197         bool turn_off, turn_on, visible, was_visible;
11198         struct drm_framebuffer *fb = plane_state->fb;
11199
11200         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11201             plane->type != DRM_PLANE_TYPE_CURSOR) {
11202                 ret = skl_update_scaler_plane(
11203                         to_intel_crtc_state(crtc_state),
11204                         to_intel_plane_state(plane_state));
11205                 if (ret)
11206                         return ret;
11207         }
11208
11209         was_visible = old_plane_state->visible;
11210         visible = to_intel_plane_state(plane_state)->visible;
11211
11212         if (!was_crtc_enabled && WARN_ON(was_visible))
11213                 was_visible = false;
11214
11215         /*
11216          * Visibility is calculated as if the crtc was on, but
11217          * after scaler setup everything depends on it being off
11218          * when the crtc isn't active.
11219          *
11220          * FIXME this is wrong for watermarks. Watermarks should also
11221          * be computed as if the pipe would be active. Perhaps move
11222          * per-plane wm computation to the .check_plane() hook, and
11223          * only combine the results from all planes in the current place?
11224          */
11225         if (!is_crtc_enabled)
11226                 to_intel_plane_state(plane_state)->visible = visible = false;
11227
11228         if (!was_visible && !visible)
11229                 return 0;
11230
11231         if (fb != old_plane_state->base.fb)
11232                 pipe_config->fb_changed = true;
11233
11234         turn_off = was_visible && (!visible || mode_changed);
11235         turn_on = visible && (!was_visible || mode_changed);
11236
11237         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11238                          plane->base.id, fb ? fb->base.id : -1);
11239
11240         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11241                          plane->base.id, was_visible, visible,
11242                          turn_off, turn_on, mode_changed);
11243
11244         if (turn_on) {
11245                 pipe_config->update_wm_pre = true;
11246
11247                 /* must disable cxsr around plane enable/disable */
11248                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11249                         pipe_config->disable_cxsr = true;
11250         } else if (turn_off) {
11251                 pipe_config->update_wm_post = true;
11252
11253                 /* must disable cxsr around plane enable/disable */
11254                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11255                         pipe_config->disable_cxsr = true;
11256         } else if (intel_wm_need_update(plane, plane_state)) {
11257                 /* FIXME bollocks */
11258                 pipe_config->update_wm_pre = true;
11259                 pipe_config->update_wm_post = true;
11260         }
11261
11262         /* Pre-gen9 platforms need two-step watermark updates */
11263         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11264             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11265                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11266
11267         if (visible || was_visible)
11268                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11269
11270         /*
11271          * WaCxSRDisabledForSpriteScaling:ivb
11272          *
11273          * cstate->update_wm was already set above, so this flag will
11274          * take effect when we commit and program watermarks.
11275          */
11276         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11277             needs_scaling(to_intel_plane_state(plane_state)) &&
11278             !needs_scaling(old_plane_state))
11279                 pipe_config->disable_lp_wm = true;
11280
11281         return 0;
11282 }
11283
11284 static bool encoders_cloneable(const struct intel_encoder *a,
11285                                const struct intel_encoder *b)
11286 {
11287         /* masks could be asymmetric, so check both ways */
11288         return a == b || (a->cloneable & (1 << b->type) &&
11289                           b->cloneable & (1 << a->type));
11290 }
11291
11292 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11293                                          struct intel_crtc *crtc,
11294                                          struct intel_encoder *encoder)
11295 {
11296         struct intel_encoder *source_encoder;
11297         struct drm_connector *connector;
11298         struct drm_connector_state *connector_state;
11299         int i;
11300
11301         for_each_connector_in_state(state, connector, connector_state, i) {
11302                 if (connector_state->crtc != &crtc->base)
11303                         continue;
11304
11305                 source_encoder =
11306                         to_intel_encoder(connector_state->best_encoder);
11307                 if (!encoders_cloneable(encoder, source_encoder))
11308                         return false;
11309         }
11310
11311         return true;
11312 }
11313
11314 static bool check_encoder_cloning(struct drm_atomic_state *state,
11315                                   struct intel_crtc *crtc)
11316 {
11317         struct intel_encoder *encoder;
11318         struct drm_connector *connector;
11319         struct drm_connector_state *connector_state;
11320         int i;
11321
11322         for_each_connector_in_state(state, connector, connector_state, i) {
11323                 if (connector_state->crtc != &crtc->base)
11324                         continue;
11325
11326                 encoder = to_intel_encoder(connector_state->best_encoder);
11327                 if (!check_single_encoder_cloning(state, crtc, encoder))
11328                         return false;
11329         }
11330
11331         return true;
11332 }
11333
11334 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11335                                    struct drm_crtc_state *crtc_state)
11336 {
11337         struct drm_device *dev = crtc->dev;
11338         struct drm_i915_private *dev_priv = dev->dev_private;
11339         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11340         struct intel_crtc_state *pipe_config =
11341                 to_intel_crtc_state(crtc_state);
11342         struct drm_atomic_state *state = crtc_state->state;
11343         int ret;
11344         bool mode_changed = needs_modeset(crtc_state);
11345
11346         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11347                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11348                 return -EINVAL;
11349         }
11350
11351         if (mode_changed && !crtc_state->active)
11352                 pipe_config->update_wm_post = true;
11353
11354         if (mode_changed && crtc_state->enable &&
11355             dev_priv->display.crtc_compute_clock &&
11356             !WARN_ON(pipe_config->shared_dpll)) {
11357                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11358                                                            pipe_config);
11359                 if (ret)
11360                         return ret;
11361         }
11362
11363         if (crtc_state->color_mgmt_changed) {
11364                 ret = intel_color_check(crtc, crtc_state);
11365                 if (ret)
11366                         return ret;
11367         }
11368
11369         ret = 0;
11370         if (dev_priv->display.compute_pipe_wm) {
11371                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11372                 if (ret) {
11373                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11374                         return ret;
11375                 }
11376         }
11377
11378         if (dev_priv->display.compute_intermediate_wm &&
11379             !to_intel_atomic_state(state)->skip_intermediate_wm) {
11380                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11381                         return 0;
11382
11383                 /*
11384                  * Calculate 'intermediate' watermarks that satisfy both the
11385                  * old state and the new state.  We can program these
11386                  * immediately.
11387                  */
11388                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11389                                                                 intel_crtc,
11390                                                                 pipe_config);
11391                 if (ret) {
11392                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11393                         return ret;
11394                 }
11395         } else if (dev_priv->display.compute_intermediate_wm) {
11396                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11397                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11398         }
11399
11400         if (INTEL_INFO(dev)->gen >= 9) {
11401                 if (mode_changed)
11402                         ret = skl_update_scaler_crtc(pipe_config);
11403
11404                 if (!ret)
11405                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11406                                                          pipe_config);
11407         }
11408
11409         return ret;
11410 }
11411
11412 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11413         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11414         .atomic_check = intel_crtc_atomic_check,
11415 };
11416
11417 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11418 {
11419         struct intel_connector *connector;
11420
11421         for_each_intel_connector(dev, connector) {
11422                 if (connector->base.state->crtc)
11423                         drm_connector_unreference(&connector->base);
11424
11425                 if (connector->base.encoder) {
11426                         connector->base.state->best_encoder =
11427                                 connector->base.encoder;
11428                         connector->base.state->crtc =
11429                                 connector->base.encoder->crtc;
11430
11431                         drm_connector_reference(&connector->base);
11432                 } else {
11433                         connector->base.state->best_encoder = NULL;
11434                         connector->base.state->crtc = NULL;
11435                 }
11436         }
11437 }
11438
11439 static void
11440 connected_sink_compute_bpp(struct intel_connector *connector,
11441                            struct intel_crtc_state *pipe_config)
11442 {
11443         int bpp = pipe_config->pipe_bpp;
11444
11445         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11446                 connector->base.base.id,
11447                 connector->base.name);
11448
11449         /* Don't use an invalid EDID bpc value */
11450         if (connector->base.display_info.bpc &&
11451             connector->base.display_info.bpc * 3 < bpp) {
11452                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11453                               bpp, connector->base.display_info.bpc*3);
11454                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11455         }
11456
11457         /* Clamp bpp to default limit on screens without EDID 1.4 */
11458         if (connector->base.display_info.bpc == 0) {
11459                 int type = connector->base.connector_type;
11460                 int clamp_bpp = 24;
11461
11462                 /* Fall back to 18 bpp when DP sink capability is unknown. */
11463                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
11464                     type == DRM_MODE_CONNECTOR_eDP)
11465                         clamp_bpp = 18;
11466
11467                 if (bpp > clamp_bpp) {
11468                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
11469                                       bpp, clamp_bpp);
11470                         pipe_config->pipe_bpp = clamp_bpp;
11471                 }
11472         }
11473 }
11474
11475 static int
11476 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11477                           struct intel_crtc_state *pipe_config)
11478 {
11479         struct drm_device *dev = crtc->base.dev;
11480         struct drm_atomic_state *state;
11481         struct drm_connector *connector;
11482         struct drm_connector_state *connector_state;
11483         int bpp, i;
11484
11485         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
11486                 bpp = 10*3;
11487         else if (INTEL_INFO(dev)->gen >= 5)
11488                 bpp = 12*3;
11489         else
11490                 bpp = 8*3;
11491
11492
11493         pipe_config->pipe_bpp = bpp;
11494
11495         state = pipe_config->base.state;
11496
11497         /* Clamp display bpp to EDID value */
11498         for_each_connector_in_state(state, connector, connector_state, i) {
11499                 if (connector_state->crtc != &crtc->base)
11500                         continue;
11501
11502                 connected_sink_compute_bpp(to_intel_connector(connector),
11503                                            pipe_config);
11504         }
11505
11506         return bpp;
11507 }
11508
11509 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11510 {
11511         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11512                         "type: 0x%x flags: 0x%x\n",
11513                 mode->crtc_clock,
11514                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11515                 mode->crtc_hsync_end, mode->crtc_htotal,
11516                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11517                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11518 }
11519
11520 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11521                                    struct intel_crtc_state *pipe_config,
11522                                    const char *context)
11523 {
11524         struct drm_device *dev = crtc->base.dev;
11525         struct drm_plane *plane;
11526         struct intel_plane *intel_plane;
11527         struct intel_plane_state *state;
11528         struct drm_framebuffer *fb;
11529
11530         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11531                       context, pipe_config, pipe_name(crtc->pipe));
11532
11533         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
11534         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11535                       pipe_config->pipe_bpp, pipe_config->dither);
11536         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11537                       pipe_config->has_pch_encoder,
11538                       pipe_config->fdi_lanes,
11539                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11540                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11541                       pipe_config->fdi_m_n.tu);
11542         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11543                       pipe_config->has_dp_encoder,
11544                       pipe_config->lane_count,
11545                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11546                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11547                       pipe_config->dp_m_n.tu);
11548
11549         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11550                       pipe_config->has_dp_encoder,
11551                       pipe_config->lane_count,
11552                       pipe_config->dp_m2_n2.gmch_m,
11553                       pipe_config->dp_m2_n2.gmch_n,
11554                       pipe_config->dp_m2_n2.link_m,
11555                       pipe_config->dp_m2_n2.link_n,
11556                       pipe_config->dp_m2_n2.tu);
11557
11558         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11559                       pipe_config->has_audio,
11560                       pipe_config->has_infoframe);
11561
11562         DRM_DEBUG_KMS("requested mode:\n");
11563         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11564         DRM_DEBUG_KMS("adjusted mode:\n");
11565         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11566         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11567         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11568         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11569                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11570         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11571                       crtc->num_scalers,
11572                       pipe_config->scaler_state.scaler_users,
11573                       pipe_config->scaler_state.scaler_id);
11574         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11575                       pipe_config->gmch_pfit.control,
11576                       pipe_config->gmch_pfit.pgm_ratios,
11577                       pipe_config->gmch_pfit.lvds_border_bits);
11578         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11579                       pipe_config->pch_pfit.pos,
11580                       pipe_config->pch_pfit.size,
11581                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11582         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11583         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11584
11585         if (IS_BROXTON(dev)) {
11586                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11587                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11588                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11589                               pipe_config->ddi_pll_sel,
11590                               pipe_config->dpll_hw_state.ebb0,
11591                               pipe_config->dpll_hw_state.ebb4,
11592                               pipe_config->dpll_hw_state.pll0,
11593                               pipe_config->dpll_hw_state.pll1,
11594                               pipe_config->dpll_hw_state.pll2,
11595                               pipe_config->dpll_hw_state.pll3,
11596                               pipe_config->dpll_hw_state.pll6,
11597                               pipe_config->dpll_hw_state.pll8,
11598                               pipe_config->dpll_hw_state.pll9,
11599                               pipe_config->dpll_hw_state.pll10,
11600                               pipe_config->dpll_hw_state.pcsdw12);
11601         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
11602                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11603                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11604                               pipe_config->ddi_pll_sel,
11605                               pipe_config->dpll_hw_state.ctrl1,
11606                               pipe_config->dpll_hw_state.cfgcr1,
11607                               pipe_config->dpll_hw_state.cfgcr2);
11608         } else if (HAS_DDI(dev)) {
11609                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
11610                               pipe_config->ddi_pll_sel,
11611                               pipe_config->dpll_hw_state.wrpll,
11612                               pipe_config->dpll_hw_state.spll);
11613         } else {
11614                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11615                               "fp0: 0x%x, fp1: 0x%x\n",
11616                               pipe_config->dpll_hw_state.dpll,
11617                               pipe_config->dpll_hw_state.dpll_md,
11618                               pipe_config->dpll_hw_state.fp0,
11619                               pipe_config->dpll_hw_state.fp1);
11620         }
11621
11622         DRM_DEBUG_KMS("planes on this crtc\n");
11623         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11624                 intel_plane = to_intel_plane(plane);
11625                 if (intel_plane->pipe != crtc->pipe)
11626                         continue;
11627
11628                 state = to_intel_plane_state(plane->state);
11629                 fb = state->base.fb;
11630                 if (!fb) {
11631                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11632                                 "disabled, scaler_id = %d\n",
11633                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11634                                 plane->base.id, intel_plane->pipe,
11635                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11636                                 drm_plane_index(plane), state->scaler_id);
11637                         continue;
11638                 }
11639
11640                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11641                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11642                         plane->base.id, intel_plane->pipe,
11643                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11644                         drm_plane_index(plane));
11645                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11646                         fb->base.id, fb->width, fb->height, fb->pixel_format);
11647                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11648                         state->scaler_id,
11649                         state->src.x1 >> 16, state->src.y1 >> 16,
11650                         drm_rect_width(&state->src) >> 16,
11651                         drm_rect_height(&state->src) >> 16,
11652                         state->dst.x1, state->dst.y1,
11653                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11654         }
11655 }
11656
11657 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11658 {
11659         struct drm_device *dev = state->dev;
11660         struct drm_connector *connector;
11661         unsigned int used_ports = 0;
11662
11663         /*
11664          * Walk the connector list instead of the encoder
11665          * list to detect the problem on ddi platforms
11666          * where there's just one encoder per digital port.
11667          */
11668         drm_for_each_connector(connector, dev) {
11669                 struct drm_connector_state *connector_state;
11670                 struct intel_encoder *encoder;
11671
11672                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11673                 if (!connector_state)
11674                         connector_state = connector->state;
11675
11676                 if (!connector_state->best_encoder)
11677                         continue;
11678
11679                 encoder = to_intel_encoder(connector_state->best_encoder);
11680
11681                 WARN_ON(!connector_state->crtc);
11682
11683                 switch (encoder->type) {
11684                         unsigned int port_mask;
11685                 case INTEL_OUTPUT_UNKNOWN:
11686                         if (WARN_ON(!HAS_DDI(dev)))
11687                                 break;
11688                 case INTEL_OUTPUT_DISPLAYPORT:
11689                 case INTEL_OUTPUT_HDMI:
11690                 case INTEL_OUTPUT_EDP:
11691                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11692
11693                         /* the same port mustn't appear more than once */
11694                         if (used_ports & port_mask)
11695                                 return false;
11696
11697                         used_ports |= port_mask;
11698                 default:
11699                         break;
11700                 }
11701         }
11702
11703         return true;
11704 }
11705
11706 static void
11707 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11708 {
11709         struct drm_crtc_state tmp_state;
11710         struct intel_crtc_scaler_state scaler_state;
11711         struct intel_dpll_hw_state dpll_hw_state;
11712         struct intel_shared_dpll *shared_dpll;
11713         uint32_t ddi_pll_sel;
11714         bool force_thru;
11715
11716         /* FIXME: before the switch to atomic started, a new pipe_config was
11717          * kzalloc'd. Code that depends on any field being zero should be
11718          * fixed, so that the crtc_state can be safely duplicated. For now,
11719          * only fields that are know to not cause problems are preserved. */
11720
11721         tmp_state = crtc_state->base;
11722         scaler_state = crtc_state->scaler_state;
11723         shared_dpll = crtc_state->shared_dpll;
11724         dpll_hw_state = crtc_state->dpll_hw_state;
11725         ddi_pll_sel = crtc_state->ddi_pll_sel;
11726         force_thru = crtc_state->pch_pfit.force_thru;
11727
11728         memset(crtc_state, 0, sizeof *crtc_state);
11729
11730         crtc_state->base = tmp_state;
11731         crtc_state->scaler_state = scaler_state;
11732         crtc_state->shared_dpll = shared_dpll;
11733         crtc_state->dpll_hw_state = dpll_hw_state;
11734         crtc_state->ddi_pll_sel = ddi_pll_sel;
11735         crtc_state->pch_pfit.force_thru = force_thru;
11736 }
11737
11738 static int
11739 intel_modeset_pipe_config(struct drm_crtc *crtc,
11740                           struct intel_crtc_state *pipe_config)
11741 {
11742         struct drm_atomic_state *state = pipe_config->base.state;
11743         struct intel_encoder *encoder;
11744         struct drm_connector *connector;
11745         struct drm_connector_state *connector_state;
11746         int base_bpp, ret = -EINVAL;
11747         int i;
11748         bool retry = true;
11749
11750         clear_intel_crtc_state(pipe_config);
11751
11752         pipe_config->cpu_transcoder =
11753                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11754
11755         /*
11756          * Sanitize sync polarity flags based on requested ones. If neither
11757          * positive or negative polarity is requested, treat this as meaning
11758          * negative polarity.
11759          */
11760         if (!(pipe_config->base.adjusted_mode.flags &
11761               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11762                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11763
11764         if (!(pipe_config->base.adjusted_mode.flags &
11765               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11766                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11767
11768         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11769                                              pipe_config);
11770         if (base_bpp < 0)
11771                 goto fail;
11772
11773         /*
11774          * Determine the real pipe dimensions. Note that stereo modes can
11775          * increase the actual pipe size due to the frame doubling and
11776          * insertion of additional space for blanks between the frame. This
11777          * is stored in the crtc timings. We use the requested mode to do this
11778          * computation to clearly distinguish it from the adjusted mode, which
11779          * can be changed by the connectors in the below retry loop.
11780          */
11781         drm_crtc_get_hv_timing(&pipe_config->base.mode,
11782                                &pipe_config->pipe_src_w,
11783                                &pipe_config->pipe_src_h);
11784
11785 encoder_retry:
11786         /* Ensure the port clock defaults are reset when retrying. */
11787         pipe_config->port_clock = 0;
11788         pipe_config->pixel_multiplier = 1;
11789
11790         /* Fill in default crtc timings, allow encoders to overwrite them. */
11791         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11792                               CRTC_STEREO_DOUBLE);
11793
11794         /* Pass our mode to the connectors and the CRTC to give them a chance to
11795          * adjust it according to limitations or connector properties, and also
11796          * a chance to reject the mode entirely.
11797          */
11798         for_each_connector_in_state(state, connector, connector_state, i) {
11799                 if (connector_state->crtc != crtc)
11800                         continue;
11801
11802                 encoder = to_intel_encoder(connector_state->best_encoder);
11803
11804                 if (!(encoder->compute_config(encoder, pipe_config))) {
11805                         DRM_DEBUG_KMS("Encoder config failure\n");
11806                         goto fail;
11807                 }
11808         }
11809
11810         /* Set default port clock if not overwritten by the encoder. Needs to be
11811          * done afterwards in case the encoder adjusts the mode. */
11812         if (!pipe_config->port_clock)
11813                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11814                         * pipe_config->pixel_multiplier;
11815
11816         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11817         if (ret < 0) {
11818                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11819                 goto fail;
11820         }
11821
11822         if (ret == RETRY) {
11823                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11824                         ret = -EINVAL;
11825                         goto fail;
11826                 }
11827
11828                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11829                 retry = false;
11830                 goto encoder_retry;
11831         }
11832
11833         /* Dithering seems to not pass-through bits correctly when it should, so
11834          * only enable it on 6bpc panels. */
11835         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
11836         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11837                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11838
11839 fail:
11840         return ret;
11841 }
11842
11843 static void
11844 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11845 {
11846         struct drm_crtc *crtc;
11847         struct drm_crtc_state *crtc_state;
11848         int i;
11849
11850         /* Double check state. */
11851         for_each_crtc_in_state(state, crtc, crtc_state, i) {
11852                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
11853
11854                 /* Update hwmode for vblank functions */
11855                 if (crtc->state->active)
11856                         crtc->hwmode = crtc->state->adjusted_mode;
11857                 else
11858                         crtc->hwmode.crtc_clock = 0;
11859
11860                 /*
11861                  * Update legacy state to satisfy fbc code. This can
11862                  * be removed when fbc uses the atomic state.
11863                  */
11864                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11865                         struct drm_plane_state *plane_state = crtc->primary->state;
11866
11867                         crtc->primary->fb = plane_state->fb;
11868                         crtc->x = plane_state->src_x >> 16;
11869                         crtc->y = plane_state->src_y >> 16;
11870                 }
11871         }
11872 }
11873
11874 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11875 {
11876         int diff;
11877
11878         if (clock1 == clock2)
11879                 return true;
11880
11881         if (!clock1 || !clock2)
11882                 return false;
11883
11884         diff = abs(clock1 - clock2);
11885
11886         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11887                 return true;
11888
11889         return false;
11890 }
11891
11892 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11893         list_for_each_entry((intel_crtc), \
11894                             &(dev)->mode_config.crtc_list, \
11895                             base.head) \
11896                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
11897
11898 static bool
11899 intel_compare_m_n(unsigned int m, unsigned int n,
11900                   unsigned int m2, unsigned int n2,
11901                   bool exact)
11902 {
11903         if (m == m2 && n == n2)
11904                 return true;
11905
11906         if (exact || !m || !n || !m2 || !n2)
11907                 return false;
11908
11909         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11910
11911         if (n > n2) {
11912                 while (n > n2) {
11913                         m2 <<= 1;
11914                         n2 <<= 1;
11915                 }
11916         } else if (n < n2) {
11917                 while (n < n2) {
11918                         m <<= 1;
11919                         n <<= 1;
11920                 }
11921         }
11922
11923         if (n != n2)
11924                 return false;
11925
11926         return intel_fuzzy_clock_check(m, m2);
11927 }
11928
11929 static bool
11930 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11931                        struct intel_link_m_n *m2_n2,
11932                        bool adjust)
11933 {
11934         if (m_n->tu == m2_n2->tu &&
11935             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11936                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11937             intel_compare_m_n(m_n->link_m, m_n->link_n,
11938                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11939                 if (adjust)
11940                         *m2_n2 = *m_n;
11941
11942                 return true;
11943         }
11944
11945         return false;
11946 }
11947
11948 static bool
11949 intel_pipe_config_compare(struct drm_device *dev,
11950                           struct intel_crtc_state *current_config,
11951                           struct intel_crtc_state *pipe_config,
11952                           bool adjust)
11953 {
11954         bool ret = true;
11955
11956 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
11957         do { \
11958                 if (!adjust) \
11959                         DRM_ERROR(fmt, ##__VA_ARGS__); \
11960                 else \
11961                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
11962         } while (0)
11963
11964 #define PIPE_CONF_CHECK_X(name) \
11965         if (current_config->name != pipe_config->name) { \
11966                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
11967                           "(expected 0x%08x, found 0x%08x)\n", \
11968                           current_config->name, \
11969                           pipe_config->name); \
11970                 ret = false; \
11971         }
11972
11973 #define PIPE_CONF_CHECK_I(name) \
11974         if (current_config->name != pipe_config->name) { \
11975                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
11976                           "(expected %i, found %i)\n", \
11977                           current_config->name, \
11978                           pipe_config->name); \
11979                 ret = false; \
11980         }
11981
11982 #define PIPE_CONF_CHECK_P(name) \
11983         if (current_config->name != pipe_config->name) { \
11984                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
11985                           "(expected %p, found %p)\n", \
11986                           current_config->name, \
11987                           pipe_config->name); \
11988                 ret = false; \
11989         }
11990
11991 #define PIPE_CONF_CHECK_M_N(name) \
11992         if (!intel_compare_link_m_n(&current_config->name, \
11993                                     &pipe_config->name,\
11994                                     adjust)) { \
11995                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
11996                           "(expected tu %i gmch %i/%i link %i/%i, " \
11997                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11998                           current_config->name.tu, \
11999                           current_config->name.gmch_m, \
12000                           current_config->name.gmch_n, \
12001                           current_config->name.link_m, \
12002                           current_config->name.link_n, \
12003                           pipe_config->name.tu, \
12004                           pipe_config->name.gmch_m, \
12005                           pipe_config->name.gmch_n, \
12006                           pipe_config->name.link_m, \
12007                           pipe_config->name.link_n); \
12008                 ret = false; \
12009         }
12010
12011 /* This is required for BDW+ where there is only one set of registers for
12012  * switching between high and low RR.
12013  * This macro can be used whenever a comparison has to be made between one
12014  * hw state and multiple sw state variables.
12015  */
12016 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12017         if (!intel_compare_link_m_n(&current_config->name, \
12018                                     &pipe_config->name, adjust) && \
12019             !intel_compare_link_m_n(&current_config->alt_name, \
12020                                     &pipe_config->name, adjust)) { \
12021                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12022                           "(expected tu %i gmch %i/%i link %i/%i, " \
12023                           "or tu %i gmch %i/%i link %i/%i, " \
12024                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12025                           current_config->name.tu, \
12026                           current_config->name.gmch_m, \
12027                           current_config->name.gmch_n, \
12028                           current_config->name.link_m, \
12029                           current_config->name.link_n, \
12030                           current_config->alt_name.tu, \
12031                           current_config->alt_name.gmch_m, \
12032                           current_config->alt_name.gmch_n, \
12033                           current_config->alt_name.link_m, \
12034                           current_config->alt_name.link_n, \
12035                           pipe_config->name.tu, \
12036                           pipe_config->name.gmch_m, \
12037                           pipe_config->name.gmch_n, \
12038                           pipe_config->name.link_m, \
12039                           pipe_config->name.link_n); \
12040                 ret = false; \
12041         }
12042
12043 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12044         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12045                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12046                           "(expected %i, found %i)\n", \
12047                           current_config->name & (mask), \
12048                           pipe_config->name & (mask)); \
12049                 ret = false; \
12050         }
12051
12052 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12053         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12054                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12055                           "(expected %i, found %i)\n", \
12056                           current_config->name, \
12057                           pipe_config->name); \
12058                 ret = false; \
12059         }
12060
12061 #define PIPE_CONF_QUIRK(quirk)  \
12062         ((current_config->quirks | pipe_config->quirks) & (quirk))
12063
12064         PIPE_CONF_CHECK_I(cpu_transcoder);
12065
12066         PIPE_CONF_CHECK_I(has_pch_encoder);
12067         PIPE_CONF_CHECK_I(fdi_lanes);
12068         PIPE_CONF_CHECK_M_N(fdi_m_n);
12069
12070         PIPE_CONF_CHECK_I(has_dp_encoder);
12071         PIPE_CONF_CHECK_I(lane_count);
12072
12073         if (INTEL_INFO(dev)->gen < 8) {
12074                 PIPE_CONF_CHECK_M_N(dp_m_n);
12075
12076                 if (current_config->has_drrs)
12077                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12078         } else
12079                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12080
12081         PIPE_CONF_CHECK_I(has_dsi_encoder);
12082
12083         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12084         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12085         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12086         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12087         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12088         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12089
12090         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12091         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12092         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12093         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12094         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12095         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12096
12097         PIPE_CONF_CHECK_I(pixel_multiplier);
12098         PIPE_CONF_CHECK_I(has_hdmi_sink);
12099         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12100             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12101                 PIPE_CONF_CHECK_I(limited_color_range);
12102         PIPE_CONF_CHECK_I(has_infoframe);
12103
12104         PIPE_CONF_CHECK_I(has_audio);
12105
12106         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12107                               DRM_MODE_FLAG_INTERLACE);
12108
12109         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12110                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12111                                       DRM_MODE_FLAG_PHSYNC);
12112                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12113                                       DRM_MODE_FLAG_NHSYNC);
12114                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12115                                       DRM_MODE_FLAG_PVSYNC);
12116                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12117                                       DRM_MODE_FLAG_NVSYNC);
12118         }
12119
12120         PIPE_CONF_CHECK_X(gmch_pfit.control);
12121         /* pfit ratios are autocomputed by the hw on gen4+ */
12122         if (INTEL_INFO(dev)->gen < 4)
12123                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12124         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12125
12126         if (!adjust) {
12127                 PIPE_CONF_CHECK_I(pipe_src_w);
12128                 PIPE_CONF_CHECK_I(pipe_src_h);
12129
12130                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12131                 if (current_config->pch_pfit.enabled) {
12132                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12133                         PIPE_CONF_CHECK_X(pch_pfit.size);
12134                 }
12135
12136                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12137         }
12138
12139         /* BDW+ don't expose a synchronous way to read the state */
12140         if (IS_HASWELL(dev))
12141                 PIPE_CONF_CHECK_I(ips_enabled);
12142
12143         PIPE_CONF_CHECK_I(double_wide);
12144
12145         PIPE_CONF_CHECK_X(ddi_pll_sel);
12146
12147         PIPE_CONF_CHECK_P(shared_dpll);
12148         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12149         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12150         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12151         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12152         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12153         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12154         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12155         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12156         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12157
12158         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12159         PIPE_CONF_CHECK_X(dsi_pll.div);
12160
12161         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12162                 PIPE_CONF_CHECK_I(pipe_bpp);
12163
12164         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12165         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12166
12167 #undef PIPE_CONF_CHECK_X
12168 #undef PIPE_CONF_CHECK_I
12169 #undef PIPE_CONF_CHECK_P
12170 #undef PIPE_CONF_CHECK_FLAGS
12171 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12172 #undef PIPE_CONF_QUIRK
12173 #undef INTEL_ERR_OR_DBG_KMS
12174
12175         return ret;
12176 }
12177
12178 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12179                                            const struct intel_crtc_state *pipe_config)
12180 {
12181         if (pipe_config->has_pch_encoder) {
12182                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12183                                                             &pipe_config->fdi_m_n);
12184                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12185
12186                 /*
12187                  * FDI already provided one idea for the dotclock.
12188                  * Yell if the encoder disagrees.
12189                  */
12190                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12191                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12192                      fdi_dotclock, dotclock);
12193         }
12194 }
12195
12196 static void verify_wm_state(struct drm_crtc *crtc,
12197                             struct drm_crtc_state *new_state)
12198 {
12199         struct drm_device *dev = crtc->dev;
12200         struct drm_i915_private *dev_priv = dev->dev_private;
12201         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12202         struct skl_ddb_entry *hw_entry, *sw_entry;
12203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12204         const enum pipe pipe = intel_crtc->pipe;
12205         int plane;
12206
12207         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12208                 return;
12209
12210         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12211         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12212
12213         /* planes */
12214         for_each_plane(dev_priv, pipe, plane) {
12215                 hw_entry = &hw_ddb.plane[pipe][plane];
12216                 sw_entry = &sw_ddb->plane[pipe][plane];
12217
12218                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12219                         continue;
12220
12221                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12222                           "(expected (%u,%u), found (%u,%u))\n",
12223                           pipe_name(pipe), plane + 1,
12224                           sw_entry->start, sw_entry->end,
12225                           hw_entry->start, hw_entry->end);
12226         }
12227
12228         /* cursor */
12229         hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12230         sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12231
12232         if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12233                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12234                           "(expected (%u,%u), found (%u,%u))\n",
12235                           pipe_name(pipe),
12236                           sw_entry->start, sw_entry->end,
12237                           hw_entry->start, hw_entry->end);
12238         }
12239 }
12240
12241 static void
12242 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12243 {
12244         struct drm_connector *connector;
12245
12246         drm_for_each_connector(connector, dev) {
12247                 struct drm_encoder *encoder = connector->encoder;
12248                 struct drm_connector_state *state = connector->state;
12249
12250                 if (state->crtc != crtc)
12251                         continue;
12252
12253                 intel_connector_verify_state(to_intel_connector(connector),
12254                                              connector->state);
12255
12256                 I915_STATE_WARN(state->best_encoder != encoder,
12257                      "connector's atomic encoder doesn't match legacy encoder\n");
12258         }
12259 }
12260
12261 static void
12262 verify_encoder_state(struct drm_device *dev)
12263 {
12264         struct intel_encoder *encoder;
12265         struct intel_connector *connector;
12266
12267         for_each_intel_encoder(dev, encoder) {
12268                 bool enabled = false;
12269                 enum pipe pipe;
12270
12271                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12272                               encoder->base.base.id,
12273                               encoder->base.name);
12274
12275                 for_each_intel_connector(dev, connector) {
12276                         if (connector->base.state->best_encoder != &encoder->base)
12277                                 continue;
12278                         enabled = true;
12279
12280                         I915_STATE_WARN(connector->base.state->crtc !=
12281                                         encoder->base.crtc,
12282                              "connector's crtc doesn't match encoder crtc\n");
12283                 }
12284
12285                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12286                      "encoder's enabled state mismatch "
12287                      "(expected %i, found %i)\n",
12288                      !!encoder->base.crtc, enabled);
12289
12290                 if (!encoder->base.crtc) {
12291                         bool active;
12292
12293                         active = encoder->get_hw_state(encoder, &pipe);
12294                         I915_STATE_WARN(active,
12295                              "encoder detached but still enabled on pipe %c.\n",
12296                              pipe_name(pipe));
12297                 }
12298         }
12299 }
12300
12301 static void
12302 verify_crtc_state(struct drm_crtc *crtc,
12303                   struct drm_crtc_state *old_crtc_state,
12304                   struct drm_crtc_state *new_crtc_state)
12305 {
12306         struct drm_device *dev = crtc->dev;
12307         struct drm_i915_private *dev_priv = dev->dev_private;
12308         struct intel_encoder *encoder;
12309         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12310         struct intel_crtc_state *pipe_config, *sw_config;
12311         struct drm_atomic_state *old_state;
12312         bool active;
12313
12314         old_state = old_crtc_state->state;
12315         __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12316         pipe_config = to_intel_crtc_state(old_crtc_state);
12317         memset(pipe_config, 0, sizeof(*pipe_config));
12318         pipe_config->base.crtc = crtc;
12319         pipe_config->base.state = old_state;
12320
12321         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12322
12323         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12324
12325         /* hw state is inconsistent with the pipe quirk */
12326         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12327             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12328                 active = new_crtc_state->active;
12329
12330         I915_STATE_WARN(new_crtc_state->active != active,
12331              "crtc active state doesn't match with hw state "
12332              "(expected %i, found %i)\n", new_crtc_state->active, active);
12333
12334         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12335              "transitional active state does not match atomic hw state "
12336              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12337
12338         for_each_encoder_on_crtc(dev, crtc, encoder) {
12339                 enum pipe pipe;
12340
12341                 active = encoder->get_hw_state(encoder, &pipe);
12342                 I915_STATE_WARN(active != new_crtc_state->active,
12343                         "[ENCODER:%i] active %i with crtc active %i\n",
12344                         encoder->base.base.id, active, new_crtc_state->active);
12345
12346                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12347                                 "Encoder connected to wrong pipe %c\n",
12348                                 pipe_name(pipe));
12349
12350                 if (active)
12351                         encoder->get_config(encoder, pipe_config);
12352         }
12353
12354         if (!new_crtc_state->active)
12355                 return;
12356
12357         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12358
12359         sw_config = to_intel_crtc_state(crtc->state);
12360         if (!intel_pipe_config_compare(dev, sw_config,
12361                                        pipe_config, false)) {
12362                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12363                 intel_dump_pipe_config(intel_crtc, pipe_config,
12364                                        "[hw state]");
12365                 intel_dump_pipe_config(intel_crtc, sw_config,
12366                                        "[sw state]");
12367         }
12368 }
12369
12370 static void
12371 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12372                          struct intel_shared_dpll *pll,
12373                          struct drm_crtc *crtc,
12374                          struct drm_crtc_state *new_state)
12375 {
12376         struct intel_dpll_hw_state dpll_hw_state;
12377         unsigned crtc_mask;
12378         bool active;
12379
12380         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12381
12382         DRM_DEBUG_KMS("%s\n", pll->name);
12383
12384         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12385
12386         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12387                 I915_STATE_WARN(!pll->on && pll->active_mask,
12388                      "pll in active use but not on in sw tracking\n");
12389                 I915_STATE_WARN(pll->on && !pll->active_mask,
12390                      "pll is on but not used by any active crtc\n");
12391                 I915_STATE_WARN(pll->on != active,
12392                      "pll on state mismatch (expected %i, found %i)\n",
12393                      pll->on, active);
12394         }
12395
12396         if (!crtc) {
12397                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12398                                 "more active pll users than references: %x vs %x\n",
12399                                 pll->active_mask, pll->config.crtc_mask);
12400
12401                 return;
12402         }
12403
12404         crtc_mask = 1 << drm_crtc_index(crtc);
12405
12406         if (new_state->active)
12407                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12408                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12409                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12410         else
12411                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12412                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12413                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12414
12415         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
12416                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12417                         crtc_mask, pll->config.crtc_mask);
12418
12419         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
12420                                           &dpll_hw_state,
12421                                           sizeof(dpll_hw_state)),
12422                         "pll hw state mismatch\n");
12423 }
12424
12425 static void
12426 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12427                          struct drm_crtc_state *old_crtc_state,
12428                          struct drm_crtc_state *new_crtc_state)
12429 {
12430         struct drm_i915_private *dev_priv = dev->dev_private;
12431         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12432         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12433
12434         if (new_state->shared_dpll)
12435                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12436
12437         if (old_state->shared_dpll &&
12438             old_state->shared_dpll != new_state->shared_dpll) {
12439                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12440                 struct intel_shared_dpll *pll = old_state->shared_dpll;
12441
12442                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12443                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12444                                 pipe_name(drm_crtc_index(crtc)));
12445                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
12446                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12447                                 pipe_name(drm_crtc_index(crtc)));
12448         }
12449 }
12450
12451 static void
12452 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12453                          struct drm_crtc_state *old_state,
12454                          struct drm_crtc_state *new_state)
12455 {
12456         verify_wm_state(crtc, new_state);
12457         verify_crtc_state(crtc, old_state, new_state);
12458         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12459 }
12460
12461 static void
12462 verify_disabled_dpll_state(struct drm_device *dev)
12463 {
12464         struct drm_i915_private *dev_priv = dev->dev_private;
12465         int i;
12466
12467         for (i = 0; i < dev_priv->num_shared_dpll; i++)
12468                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12469 }
12470
12471 static void
12472 intel_modeset_verify_disabled(struct drm_device *dev)
12473 {
12474         verify_encoder_state(dev);
12475         verify_connector_state(dev, NULL);
12476         verify_disabled_dpll_state(dev);
12477 }
12478
12479 static void update_scanline_offset(struct intel_crtc *crtc)
12480 {
12481         struct drm_device *dev = crtc->base.dev;
12482
12483         /*
12484          * The scanline counter increments at the leading edge of hsync.
12485          *
12486          * On most platforms it starts counting from vtotal-1 on the
12487          * first active line. That means the scanline counter value is
12488          * always one less than what we would expect. Ie. just after
12489          * start of vblank, which also occurs at start of hsync (on the
12490          * last active line), the scanline counter will read vblank_start-1.
12491          *
12492          * On gen2 the scanline counter starts counting from 1 instead
12493          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12494          * to keep the value positive), instead of adding one.
12495          *
12496          * On HSW+ the behaviour of the scanline counter depends on the output
12497          * type. For DP ports it behaves like most other platforms, but on HDMI
12498          * there's an extra 1 line difference. So we need to add two instead of
12499          * one to the value.
12500          */
12501         if (IS_GEN2(dev)) {
12502                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12503                 int vtotal;
12504
12505                 vtotal = adjusted_mode->crtc_vtotal;
12506                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12507                         vtotal /= 2;
12508
12509                 crtc->scanline_offset = vtotal - 1;
12510         } else if (HAS_DDI(dev) &&
12511                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12512                 crtc->scanline_offset = 2;
12513         } else
12514                 crtc->scanline_offset = 1;
12515 }
12516
12517 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12518 {
12519         struct drm_device *dev = state->dev;
12520         struct drm_i915_private *dev_priv = to_i915(dev);
12521         struct intel_shared_dpll_config *shared_dpll = NULL;
12522         struct drm_crtc *crtc;
12523         struct drm_crtc_state *crtc_state;
12524         int i;
12525
12526         if (!dev_priv->display.crtc_compute_clock)
12527                 return;
12528
12529         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12530                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12531                 struct intel_shared_dpll *old_dpll =
12532                         to_intel_crtc_state(crtc->state)->shared_dpll;
12533
12534                 if (!needs_modeset(crtc_state))
12535                         continue;
12536
12537                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
12538
12539                 if (!old_dpll)
12540                         continue;
12541
12542                 if (!shared_dpll)
12543                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12544
12545                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
12546         }
12547 }
12548
12549 /*
12550  * This implements the workaround described in the "notes" section of the mode
12551  * set sequence documentation. When going from no pipes or single pipe to
12552  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12553  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12554  */
12555 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12556 {
12557         struct drm_crtc_state *crtc_state;
12558         struct intel_crtc *intel_crtc;
12559         struct drm_crtc *crtc;
12560         struct intel_crtc_state *first_crtc_state = NULL;
12561         struct intel_crtc_state *other_crtc_state = NULL;
12562         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12563         int i;
12564
12565         /* look at all crtc's that are going to be enabled in during modeset */
12566         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12567                 intel_crtc = to_intel_crtc(crtc);
12568
12569                 if (!crtc_state->active || !needs_modeset(crtc_state))
12570                         continue;
12571
12572                 if (first_crtc_state) {
12573                         other_crtc_state = to_intel_crtc_state(crtc_state);
12574                         break;
12575                 } else {
12576                         first_crtc_state = to_intel_crtc_state(crtc_state);
12577                         first_pipe = intel_crtc->pipe;
12578                 }
12579         }
12580
12581         /* No workaround needed? */
12582         if (!first_crtc_state)
12583                 return 0;
12584
12585         /* w/a possibly needed, check how many crtc's are already enabled. */
12586         for_each_intel_crtc(state->dev, intel_crtc) {
12587                 struct intel_crtc_state *pipe_config;
12588
12589                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12590                 if (IS_ERR(pipe_config))
12591                         return PTR_ERR(pipe_config);
12592
12593                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12594
12595                 if (!pipe_config->base.active ||
12596                     needs_modeset(&pipe_config->base))
12597                         continue;
12598
12599                 /* 2 or more enabled crtcs means no need for w/a */
12600                 if (enabled_pipe != INVALID_PIPE)
12601                         return 0;
12602
12603                 enabled_pipe = intel_crtc->pipe;
12604         }
12605
12606         if (enabled_pipe != INVALID_PIPE)
12607                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12608         else if (other_crtc_state)
12609                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12610
12611         return 0;
12612 }
12613
12614 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12615 {
12616         struct drm_crtc *crtc;
12617         struct drm_crtc_state *crtc_state;
12618         int ret = 0;
12619
12620         /* add all active pipes to the state */
12621         for_each_crtc(state->dev, crtc) {
12622                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12623                 if (IS_ERR(crtc_state))
12624                         return PTR_ERR(crtc_state);
12625
12626                 if (!crtc_state->active || needs_modeset(crtc_state))
12627                         continue;
12628
12629                 crtc_state->mode_changed = true;
12630
12631                 ret = drm_atomic_add_affected_connectors(state, crtc);
12632                 if (ret)
12633                         break;
12634
12635                 ret = drm_atomic_add_affected_planes(state, crtc);
12636                 if (ret)
12637                         break;
12638         }
12639
12640         return ret;
12641 }
12642
12643 static int intel_modeset_checks(struct drm_atomic_state *state)
12644 {
12645         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12646         struct drm_i915_private *dev_priv = state->dev->dev_private;
12647         struct drm_crtc *crtc;
12648         struct drm_crtc_state *crtc_state;
12649         int ret = 0, i;
12650
12651         if (!check_digital_port_conflicts(state)) {
12652                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12653                 return -EINVAL;
12654         }
12655
12656         intel_state->modeset = true;
12657         intel_state->active_crtcs = dev_priv->active_crtcs;
12658
12659         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12660                 if (crtc_state->active)
12661                         intel_state->active_crtcs |= 1 << i;
12662                 else
12663                         intel_state->active_crtcs &= ~(1 << i);
12664
12665                 if (crtc_state->active != crtc->state->active)
12666                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12667         }
12668
12669         /*
12670          * See if the config requires any additional preparation, e.g.
12671          * to adjust global state with pipes off.  We need to do this
12672          * here so we can get the modeset_pipe updated config for the new
12673          * mode set on this crtc.  For other crtcs we need to use the
12674          * adjusted_mode bits in the crtc directly.
12675          */
12676         if (dev_priv->display.modeset_calc_cdclk) {
12677                 if (!intel_state->cdclk_pll_vco)
12678                         intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
12679                 if (!intel_state->cdclk_pll_vco)
12680                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
12681
12682                 ret = dev_priv->display.modeset_calc_cdclk(state);
12683                 if (ret < 0)
12684                         return ret;
12685
12686                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
12687                     intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
12688                         ret = intel_modeset_all_pipes(state);
12689
12690                 if (ret < 0)
12691                         return ret;
12692
12693                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
12694                               intel_state->cdclk, intel_state->dev_cdclk);
12695         } else
12696                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
12697
12698         intel_modeset_clear_plls(state);
12699
12700         if (IS_HASWELL(dev_priv))
12701                 return haswell_mode_set_planes_workaround(state);
12702
12703         return 0;
12704 }
12705
12706 /*
12707  * Handle calculation of various watermark data at the end of the atomic check
12708  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12709  * handlers to ensure that all derived state has been updated.
12710  */
12711 static int calc_watermark_data(struct drm_atomic_state *state)
12712 {
12713         struct drm_device *dev = state->dev;
12714         struct drm_i915_private *dev_priv = to_i915(dev);
12715
12716         /* Is there platform-specific watermark information to calculate? */
12717         if (dev_priv->display.compute_global_watermarks)
12718                 return dev_priv->display.compute_global_watermarks(state);
12719
12720         return 0;
12721 }
12722
12723 /**
12724  * intel_atomic_check - validate state object
12725  * @dev: drm device
12726  * @state: state to validate
12727  */
12728 static int intel_atomic_check(struct drm_device *dev,
12729                               struct drm_atomic_state *state)
12730 {
12731         struct drm_i915_private *dev_priv = to_i915(dev);
12732         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12733         struct drm_crtc *crtc;
12734         struct drm_crtc_state *crtc_state;
12735         int ret, i;
12736         bool any_ms = false;
12737
12738         ret = drm_atomic_helper_check_modeset(dev, state);
12739         if (ret)
12740                 return ret;
12741
12742         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12743                 struct intel_crtc_state *pipe_config =
12744                         to_intel_crtc_state(crtc_state);
12745
12746                 /* Catch I915_MODE_FLAG_INHERITED */
12747                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
12748                         crtc_state->mode_changed = true;
12749
12750                 if (!needs_modeset(crtc_state))
12751                         continue;
12752
12753                 if (!crtc_state->enable) {
12754                         any_ms = true;
12755                         continue;
12756                 }
12757
12758                 /* FIXME: For only active_changed we shouldn't need to do any
12759                  * state recomputation at all. */
12760
12761                 ret = drm_atomic_add_affected_connectors(state, crtc);
12762                 if (ret)
12763                         return ret;
12764
12765                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12766                 if (ret) {
12767                         intel_dump_pipe_config(to_intel_crtc(crtc),
12768                                                pipe_config, "[failed]");
12769                         return ret;
12770                 }
12771
12772                 if (i915.fastboot &&
12773                     intel_pipe_config_compare(dev,
12774                                         to_intel_crtc_state(crtc->state),
12775                                         pipe_config, true)) {
12776                         crtc_state->mode_changed = false;
12777                         to_intel_crtc_state(crtc_state)->update_pipe = true;
12778                 }
12779
12780                 if (needs_modeset(crtc_state))
12781                         any_ms = true;
12782
12783                 ret = drm_atomic_add_affected_planes(state, crtc);
12784                 if (ret)
12785                         return ret;
12786
12787                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12788                                        needs_modeset(crtc_state) ?
12789                                        "[modeset]" : "[fastset]");
12790         }
12791
12792         if (any_ms) {
12793                 ret = intel_modeset_checks(state);
12794
12795                 if (ret)
12796                         return ret;
12797         } else
12798                 intel_state->cdclk = dev_priv->cdclk_freq;
12799
12800         ret = drm_atomic_helper_check_planes(dev, state);
12801         if (ret)
12802                 return ret;
12803
12804         intel_fbc_choose_crtc(dev_priv, state);
12805         return calc_watermark_data(state);
12806 }
12807
12808 static bool needs_work(struct drm_crtc_state *crtc_state)
12809 {
12810         /* hw state checker needs to run */
12811         if (needs_modeset(crtc_state))
12812                 return true;
12813
12814         /* unpin old fb's, possibly vblank update */
12815         if (crtc_state->planes_changed)
12816                 return true;
12817
12818         /* pipe parameters need to be updated, and hw state checker */
12819         if (to_intel_crtc_state(crtc_state)->update_pipe)
12820                 return true;
12821
12822         /* vblank event requested? */
12823         if (crtc_state->event)
12824                 return true;
12825
12826         return false;
12827 }
12828
12829 static int intel_atomic_prepare_commit(struct drm_device *dev,
12830                                        struct drm_atomic_state *state,
12831                                        bool nonblock)
12832 {
12833         struct drm_i915_private *dev_priv = dev->dev_private;
12834         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12835         struct drm_plane_state *plane_state;
12836         struct drm_crtc_state *crtc_state;
12837         struct drm_plane *plane;
12838         struct drm_crtc *crtc;
12839         int i, ret;
12840
12841         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12842                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12843                 struct intel_flip_work *work;
12844
12845                 if (!state->legacy_cursor_update) {
12846                         ret = intel_crtc_wait_for_pending_flips(crtc);
12847                         if (ret)
12848                                 return ret;
12849
12850                         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12851                                 flush_workqueue(dev_priv->wq);
12852                 }
12853
12854                 /* test if we need to update something */
12855                 if (!needs_work(crtc_state))
12856                         continue;
12857
12858                 intel_state->work[i] = work =
12859                         kzalloc(sizeof(**intel_state->work), GFP_KERNEL);
12860
12861                 if (!work)
12862                         return -ENOMEM;
12863
12864                 if (needs_modeset(crtc_state) ||
12865                     to_intel_crtc_state(crtc_state)->update_pipe) {
12866                         work->num_old_connectors = hweight32(crtc->state->connector_mask);
12867
12868                         work->old_connector_state = kcalloc(work->num_old_connectors,
12869                                                             sizeof(*work->old_connector_state),
12870                                                             GFP_KERNEL);
12871
12872                         work->num_new_connectors = hweight32(crtc_state->connector_mask);
12873                         work->new_connector_state = kcalloc(work->num_new_connectors,
12874                                                             sizeof(*work->new_connector_state),
12875                                                             GFP_KERNEL);
12876
12877                         if (!work->old_connector_state || !work->new_connector_state)
12878                                 return -ENOMEM;
12879                 }
12880         }
12881
12882         if (intel_state->modeset && nonblock) {
12883                 DRM_DEBUG_ATOMIC("Nonblock modesets are not yet supported!\n");
12884                 return -EINVAL;
12885         }
12886
12887         ret = mutex_lock_interruptible(&dev->struct_mutex);
12888         if (ret)
12889                 return ret;
12890
12891         ret = drm_atomic_helper_prepare_planes(dev, state);
12892         mutex_unlock(&dev->struct_mutex);
12893
12894         if (!ret && !nonblock) {
12895                 for_each_plane_in_state(state, plane, plane_state, i) {
12896                         struct intel_plane_state *intel_plane_state =
12897                                 to_intel_plane_state(plane_state);
12898
12899                         if (plane_state->fence) {
12900                                 long lret = fence_wait(plane_state->fence, true);
12901
12902                                 if (lret < 0) {
12903                                         ret = lret;
12904                                         break;
12905                                 }
12906                         }
12907
12908                         if (!intel_plane_state->wait_req)
12909                                 continue;
12910
12911                         ret = __i915_wait_request(intel_plane_state->wait_req,
12912                                                   true, NULL, NULL);
12913                         if (ret) {
12914                                 /* Any hang should be swallowed by the wait */
12915                                 WARN_ON(ret == -EIO);
12916                                 mutex_lock(&dev->struct_mutex);
12917                                 drm_atomic_helper_cleanup_planes(dev, state);
12918                                 mutex_unlock(&dev->struct_mutex);
12919                                 break;
12920                         }
12921                 }
12922         }
12923
12924         return ret;
12925 }
12926
12927 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12928 {
12929         struct drm_device *dev = crtc->base.dev;
12930
12931         if (!dev->max_vblank_count)
12932                 return drm_accurate_vblank_count(&crtc->base);
12933
12934         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12935 }
12936
12937 static void intel_prepare_work(struct drm_crtc *crtc,
12938                                struct intel_flip_work *work,
12939                                struct drm_atomic_state *state,
12940                                struct drm_crtc_state *old_crtc_state)
12941 {
12942         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12943         struct drm_plane_state *old_plane_state;
12944         struct drm_plane *plane;
12945         int i, j = 0;
12946
12947         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12948         INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12949         atomic_inc(&intel_crtc->unpin_work_count);
12950
12951         for_each_plane_in_state(state, plane, old_plane_state, i) {
12952                 struct intel_plane_state *old_state = to_intel_plane_state(old_plane_state);
12953                 struct intel_plane_state *new_state = to_intel_plane_state(plane->state);
12954
12955                 if (old_state->base.crtc != crtc &&
12956                     new_state->base.crtc != crtc)
12957                         continue;
12958
12959                 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
12960                         plane->fb = new_state->base.fb;
12961                         crtc->x = new_state->base.src_x >> 16;
12962                         crtc->y = new_state->base.src_y >> 16;
12963                 }
12964
12965                 old_state->wait_req = new_state->wait_req;
12966                 new_state->wait_req = NULL;
12967
12968                 old_state->base.fence = new_state->base.fence;
12969                 new_state->base.fence = NULL;
12970
12971                 /* remove plane state from the atomic state and move it to work */
12972                 old_plane_state->state = NULL;
12973                 state->planes[i] = NULL;
12974                 state->plane_states[i] = NULL;
12975
12976                 work->old_plane_state[j] = old_state;
12977                 work->new_plane_state[j++] = new_state;
12978         }
12979
12980         old_crtc_state->state = NULL;
12981         state->crtcs[drm_crtc_index(crtc)] = NULL;
12982         state->crtc_states[drm_crtc_index(crtc)] = NULL;
12983
12984         work->old_crtc_state = to_intel_crtc_state(old_crtc_state);
12985         work->new_crtc_state = to_intel_crtc_state(crtc->state);
12986         work->num_planes = j;
12987
12988         work->event = crtc->state->event;
12989         crtc->state->event = NULL;
12990
12991         if (needs_modeset(crtc->state) || work->new_crtc_state->update_pipe) {
12992                 struct drm_connector *conn;
12993                 struct drm_connector_state *old_conn_state;
12994                 int k = 0;
12995
12996                 j = 0;
12997
12998                 /*
12999                  * intel_unpin_work_fn cannot depend on the connector list
13000                  * because it may be freed from underneath it, so add
13001                  * them all to the work struct while we're holding locks.
13002                  */
13003                 for_each_connector_in_state(state, conn, old_conn_state, i) {
13004                         if (old_conn_state->crtc == crtc) {
13005                                 work->old_connector_state[j++] = old_conn_state;
13006
13007                                 state->connectors[i] = NULL;
13008                                 state->connector_states[i] = NULL;
13009                         }
13010                 }
13011
13012                 /* If another crtc has stolen the connector from state,
13013                  * then for_each_connector_in_state is no longer reliable,
13014                  * so use drm_for_each_connector here.
13015                  */
13016                 drm_for_each_connector(conn, state->dev)
13017                         if (conn->state->crtc == crtc)
13018                                 work->new_connector_state[k++] = conn->state;
13019
13020                 WARN(j != work->num_old_connectors, "j = %i, expected %i\n", j, work->num_old_connectors);
13021                 WARN(k != work->num_new_connectors, "k = %i, expected %i\n", k, work->num_new_connectors);
13022         } else if (!work->new_crtc_state->update_wm_post)
13023                 work->can_async_unpin = true;
13024
13025         work->fb_bits = work->new_crtc_state->fb_bits;
13026 }
13027
13028 static void intel_schedule_unpin(struct drm_crtc *crtc,
13029                                  struct intel_atomic_state *state,
13030                                  struct intel_flip_work *work)
13031 {
13032         struct drm_device *dev = crtc->dev;
13033         struct drm_i915_private *dev_priv = dev->dev_private;
13034
13035         to_intel_crtc(crtc)->config = work->new_crtc_state;
13036
13037         queue_work(dev_priv->wq, &work->unpin_work);
13038 }
13039
13040 static void intel_schedule_flip(struct drm_crtc *crtc,
13041                                 struct intel_atomic_state *state,
13042                                 struct intel_flip_work *work,
13043                                 bool nonblock)
13044 {
13045         struct intel_crtc_state *crtc_state = work->new_crtc_state;
13046
13047         if (crtc_state->base.planes_changed ||
13048             needs_modeset(&crtc_state->base) ||
13049             crtc_state->update_pipe) {
13050                 if (nonblock)
13051                         schedule_work(&work->mmio_work);
13052                 else
13053                         intel_mmio_flip_work_func(&work->mmio_work);
13054         } else {
13055                 int ret;
13056
13057                 ret = drm_crtc_vblank_get(crtc);
13058                 I915_STATE_WARN(ret < 0, "enabling vblank failed with %i\n", ret);
13059
13060                 work->flip_queued_vblank = intel_crtc_get_vblank_counter(to_intel_crtc(crtc));
13061                 smp_mb__before_atomic();
13062                 atomic_set(&work->pending, 1);
13063         }
13064 }
13065
13066 static void intel_schedule_update(struct drm_crtc *crtc,
13067                                   struct intel_atomic_state *state,
13068                                   struct intel_flip_work *work,
13069                                   bool nonblock)
13070 {
13071         struct drm_device *dev = crtc->dev;
13072         struct intel_crtc_state *pipe_config = work->new_crtc_state;
13073
13074         if (!pipe_config->base.active && work->can_async_unpin) {
13075                 INIT_LIST_HEAD(&work->head);
13076                 intel_schedule_unpin(crtc, state, work);
13077                 return;
13078         }
13079
13080         spin_lock_irq(&dev->event_lock);
13081         list_add_tail(&work->head, &to_intel_crtc(crtc)->flip_work);
13082         spin_unlock_irq(&dev->event_lock);
13083
13084         if (!pipe_config->base.active)
13085                 intel_schedule_unpin(crtc, state, work);
13086         else
13087                 intel_schedule_flip(crtc, state, work, nonblock);
13088 }
13089
13090 /**
13091  * intel_atomic_commit - commit validated state object
13092  * @dev: DRM device
13093  * @state: the top-level driver state object
13094  * @nonblock: nonblocking commit
13095  *
13096  * This function commits a top-level state object that has been validated
13097  * with drm_atomic_helper_check().
13098  *
13099  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13100  * we can only handle plane-related operations and do not yet support
13101  * nonblocking commit.
13102  *
13103  * RETURNS
13104  * Zero for success or -errno.
13105  */
13106 static int intel_atomic_commit(struct drm_device *dev,
13107                                struct drm_atomic_state *state,
13108                                bool nonblock)
13109 {
13110         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13111         struct drm_i915_private *dev_priv = dev->dev_private;
13112         struct drm_crtc_state *old_crtc_state;
13113         struct drm_crtc *crtc;
13114         int ret = 0, i;
13115
13116         ret = intel_atomic_prepare_commit(dev, state, nonblock);
13117         if (ret) {
13118                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13119                 return ret;
13120         }
13121
13122         drm_atomic_helper_swap_state(dev, state);
13123         dev_priv->wm.distrust_bios_wm = false;
13124         dev_priv->wm.skl_results = intel_state->wm_results;
13125         intel_shared_dpll_commit(state);
13126
13127         if (intel_state->modeset) {
13128                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13129                        sizeof(intel_state->min_pixclk));
13130                 dev_priv->active_crtcs = intel_state->active_crtcs;
13131                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13132         }
13133
13134         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13135                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13136
13137                 if (!needs_modeset(crtc->state))
13138                         continue;
13139
13140                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13141
13142                 intel_state->work[i]->put_power_domains =
13143                         modeset_get_crtc_power_domains(crtc,
13144                                 to_intel_crtc_state(crtc->state));
13145
13146                 if (old_crtc_state->active) {
13147                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13148                         dev_priv->display.crtc_disable(crtc);
13149                         intel_crtc->active = false;
13150                         intel_fbc_disable(intel_crtc);
13151                         intel_disable_shared_dpll(intel_crtc);
13152
13153                         /*
13154                          * Underruns don't always raise
13155                          * interrupts, so check manually.
13156                          */
13157                         intel_check_cpu_fifo_underruns(dev_priv);
13158                         intel_check_pch_fifo_underruns(dev_priv);
13159
13160                         if (!crtc->state->active)
13161                                 intel_update_watermarks(crtc);
13162                 }
13163         }
13164
13165         /* Only after disabling all output pipelines that will be changed can we
13166          * update the the output configuration. */
13167         intel_modeset_update_crtc_state(state);
13168
13169         if (intel_state->modeset) {
13170                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13171
13172                 if (dev_priv->display.modeset_commit_cdclk &&
13173                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13174                      intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
13175                         dev_priv->display.modeset_commit_cdclk(state);
13176
13177                 intel_modeset_verify_disabled(dev);
13178         }
13179
13180         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13181         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13182                 struct intel_flip_work *work = intel_state->work[i];
13183                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13184                 bool modeset = needs_modeset(crtc->state);
13185
13186                 if (modeset && crtc->state->active) {
13187                         update_scanline_offset(to_intel_crtc(crtc));
13188                         dev_priv->display.crtc_enable(crtc);
13189                 }
13190
13191                 if (!modeset)
13192                         intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13193
13194                 if (!work) {
13195                         if (!list_empty_careful(&intel_crtc->flip_work)) {
13196                                 spin_lock_irq(&dev->event_lock);
13197                                 if (!list_empty(&intel_crtc->flip_work))
13198                                         work = list_last_entry(&intel_crtc->flip_work,
13199                                                                struct intel_flip_work, head);
13200
13201                                 if (work && work->new_crtc_state == to_intel_crtc_state(old_crtc_state)) {
13202                                         work->free_new_crtc_state = true;
13203                                         state->crtc_states[i] = NULL;
13204                                         state->crtcs[i] = NULL;
13205                                 }
13206                                 spin_unlock_irq(&dev->event_lock);
13207                         }
13208                         continue;
13209                 }
13210
13211                 intel_state->work[i] = NULL;
13212                 intel_prepare_work(crtc, work, state, old_crtc_state);
13213                 intel_schedule_update(crtc, intel_state, work, nonblock);
13214         }
13215
13216         /* FIXME: add subpixel order */
13217
13218         drm_atomic_state_free(state);
13219
13220         /* As one of the primary mmio accessors, KMS has a high likelihood
13221          * of triggering bugs in unclaimed access. After we finish
13222          * modesetting, see if an error has been flagged, and if so
13223          * enable debugging for the next modeset - and hope we catch
13224          * the culprit.
13225          *
13226          * XXX note that we assume display power is on at this point.
13227          * This might hold true now but we need to add pm helper to check
13228          * unclaimed only when the hardware is on, as atomic commits
13229          * can happen also when the device is completely off.
13230          */
13231         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13232
13233         return 0;
13234 }
13235
13236 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13237 {
13238         struct drm_device *dev = crtc->dev;
13239         struct drm_atomic_state *state;
13240         struct drm_crtc_state *crtc_state;
13241         int ret;
13242
13243         state = drm_atomic_state_alloc(dev);
13244         if (!state) {
13245                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13246                               crtc->base.id);
13247                 return;
13248         }
13249
13250         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13251
13252 retry:
13253         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13254         ret = PTR_ERR_OR_ZERO(crtc_state);
13255         if (!ret) {
13256                 if (!crtc_state->active)
13257                         goto out;
13258
13259                 crtc_state->mode_changed = true;
13260                 ret = drm_atomic_commit(state);
13261         }
13262
13263         if (ret == -EDEADLK) {
13264                 drm_atomic_state_clear(state);
13265                 drm_modeset_backoff(state->acquire_ctx);
13266                 goto retry;
13267         }
13268
13269         if (ret)
13270 out:
13271                 drm_atomic_state_free(state);
13272 }
13273
13274 #undef for_each_intel_crtc_masked
13275
13276 static const struct drm_crtc_funcs intel_crtc_funcs = {
13277         .gamma_set = drm_atomic_helper_legacy_gamma_set,
13278         .set_config = drm_atomic_helper_set_config,
13279         .set_property = drm_atomic_helper_crtc_set_property,
13280         .destroy = intel_crtc_destroy,
13281         .page_flip = drm_atomic_helper_page_flip,
13282         .atomic_duplicate_state = intel_crtc_duplicate_state,
13283         .atomic_destroy_state = intel_crtc_destroy_state,
13284 };
13285
13286 static struct fence *intel_get_excl_fence(struct drm_i915_gem_object *obj)
13287 {
13288         struct reservation_object *resv;
13289
13290
13291         if (!obj->base.dma_buf)
13292                 return NULL;
13293
13294         resv = obj->base.dma_buf->resv;
13295
13296         /* For framebuffer backed by dmabuf, wait for fence */
13297         while (1) {
13298                 struct fence *fence_excl, *ret = NULL;
13299
13300                 rcu_read_lock();
13301
13302                 fence_excl = rcu_dereference(resv->fence_excl);
13303                 if (fence_excl)
13304                         ret = fence_get_rcu(fence_excl);
13305
13306                 rcu_read_unlock();
13307
13308                 if (ret == fence_excl)
13309                         return ret;
13310         }
13311 }
13312
13313 /**
13314  * intel_prepare_plane_fb - Prepare fb for usage on plane
13315  * @plane: drm plane to prepare for
13316  * @fb: framebuffer to prepare for presentation
13317  *
13318  * Prepares a framebuffer for usage on a display plane.  Generally this
13319  * involves pinning the underlying object and updating the frontbuffer tracking
13320  * bits.  Some older platforms need special physical address handling for
13321  * cursor planes.
13322  *
13323  * Must be called with struct_mutex held.
13324  *
13325  * Returns 0 on success, negative error code on failure.
13326  */
13327 int
13328 intel_prepare_plane_fb(struct drm_plane *plane,
13329                        const struct drm_plane_state *new_state)
13330 {
13331         struct drm_device *dev = plane->dev;
13332         struct drm_framebuffer *fb = new_state->fb;
13333         struct intel_plane *intel_plane = to_intel_plane(plane);
13334         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13335         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13336         struct drm_crtc *crtc = new_state->crtc ?: plane->state->crtc;
13337         int ret = 0;
13338
13339         if (!obj && !old_obj)
13340                 return 0;
13341
13342         if (WARN_ON(!new_state->state) || WARN_ON(!crtc) ||
13343             WARN_ON(!to_intel_atomic_state(new_state->state)->work[to_intel_crtc(crtc)->pipe])) {
13344                 if (WARN_ON(old_obj != obj))
13345                         return -EINVAL;
13346
13347                 return 0;
13348         }
13349
13350         if (old_obj) {
13351                 struct drm_crtc_state *crtc_state =
13352                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13353
13354                 /* Big Hammer, we also need to ensure that any pending
13355                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13356                  * current scanout is retired before unpinning the old
13357                  * framebuffer. Note that we rely on userspace rendering
13358                  * into the buffer attached to the pipe they are waiting
13359                  * on. If not, userspace generates a GPU hang with IPEHR
13360                  * point to the MI_WAIT_FOR_EVENT.
13361                  *
13362                  * This should only fail upon a hung GPU, in which case we
13363                  * can safely continue.
13364                  */
13365                 if (needs_modeset(crtc_state))
13366                         ret = i915_gem_object_wait_rendering(old_obj, true);
13367                 if (ret) {
13368                         /* GPU hangs should have been swallowed by the wait */
13369                         WARN_ON(ret == -EIO);
13370                         return ret;
13371                 }
13372         }
13373
13374         if (!obj) {
13375                 ret = 0;
13376         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13377             INTEL_INFO(dev)->cursor_needs_physical) {
13378                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13379                 ret = i915_gem_object_attach_phys(obj, align);
13380                 if (ret)
13381                         DRM_DEBUG_KMS("failed to attach phys object\n");
13382         } else {
13383                 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13384         }
13385
13386         if (ret == 0) {
13387                 if (obj) {
13388                         struct intel_plane_state *plane_state =
13389                                 to_intel_plane_state(new_state);
13390
13391                         i915_gem_request_assign(&plane_state->wait_req,
13392                                                 obj->last_write_req);
13393
13394                         plane_state->base.fence = intel_get_excl_fence(obj);
13395                 }
13396
13397                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13398         }
13399
13400         return ret;
13401 }
13402
13403 /**
13404  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13405  * @plane: drm plane to clean up for
13406  * @fb: old framebuffer that was on plane
13407  *
13408  * Cleans up a framebuffer that has just been removed from a plane.
13409  *
13410  * Must be called with struct_mutex held.
13411  */
13412 void
13413 intel_cleanup_plane_fb(struct drm_plane *plane,
13414                        const struct drm_plane_state *old_state)
13415 {
13416         struct drm_device *dev = plane->dev;
13417         struct intel_plane *intel_plane = to_intel_plane(plane);
13418         struct intel_plane_state *old_intel_state;
13419         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13420         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13421
13422         old_intel_state = to_intel_plane_state(old_state);
13423
13424         if (!obj && !old_obj)
13425                 return;
13426
13427         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13428             !INTEL_INFO(dev)->cursor_needs_physical))
13429                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13430
13431         /* prepare_fb aborted? */
13432         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13433             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13434                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13435
13436         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13437
13438         fence_put(old_intel_state->base.fence);
13439         old_intel_state->base.fence = NULL;
13440 }
13441
13442 int
13443 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13444 {
13445         int max_scale;
13446         struct drm_device *dev;
13447         struct drm_i915_private *dev_priv;
13448         int crtc_clock, cdclk;
13449
13450         if (!intel_crtc || !crtc_state->base.enable)
13451                 return DRM_PLANE_HELPER_NO_SCALING;
13452
13453         dev = intel_crtc->base.dev;
13454         dev_priv = dev->dev_private;
13455         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13456         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13457
13458         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13459                 return DRM_PLANE_HELPER_NO_SCALING;
13460
13461         /*
13462          * skl max scale is lower of:
13463          *    close to 3 but not 3, -1 is for that purpose
13464          *            or
13465          *    cdclk/crtc_clock
13466          */
13467         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13468
13469         return max_scale;
13470 }
13471
13472 static int
13473 intel_check_primary_plane(struct drm_plane *plane,
13474                           struct intel_crtc_state *crtc_state,
13475                           struct intel_plane_state *state)
13476 {
13477         struct drm_crtc *crtc = state->base.crtc;
13478         struct drm_framebuffer *fb = state->base.fb;
13479         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13480         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13481         bool can_position = false;
13482
13483         if (INTEL_INFO(plane->dev)->gen >= 9) {
13484                 /* use scaler when colorkey is not required */
13485                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13486                         min_scale = 1;
13487                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13488                 }
13489                 can_position = true;
13490         }
13491
13492         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13493                                              &state->dst, &state->clip,
13494                                              min_scale, max_scale,
13495                                              can_position, true,
13496                                              &state->visible);
13497 }
13498
13499 /**
13500  * intel_plane_destroy - destroy a plane
13501  * @plane: plane to destroy
13502  *
13503  * Common destruction function for all types of planes (primary, cursor,
13504  * sprite).
13505  */
13506 void intel_plane_destroy(struct drm_plane *plane)
13507 {
13508         struct intel_plane *intel_plane = to_intel_plane(plane);
13509         drm_plane_cleanup(plane);
13510         kfree(intel_plane);
13511 }
13512
13513 const struct drm_plane_funcs intel_plane_funcs = {
13514         .update_plane = drm_atomic_helper_update_plane,
13515         .disable_plane = drm_atomic_helper_disable_plane,
13516         .destroy = intel_plane_destroy,
13517         .set_property = drm_atomic_helper_plane_set_property,
13518         .atomic_get_property = intel_plane_atomic_get_property,
13519         .atomic_set_property = intel_plane_atomic_set_property,
13520         .atomic_duplicate_state = intel_plane_duplicate_state,
13521         .atomic_destroy_state = intel_plane_destroy_state,
13522
13523 };
13524
13525 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13526                                                     int pipe)
13527 {
13528         struct intel_plane *primary = NULL;
13529         struct intel_plane_state *state = NULL;
13530         const uint32_t *intel_primary_formats;
13531         unsigned int num_formats;
13532         int ret;
13533
13534         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13535         if (!primary)
13536                 goto fail;
13537
13538         state = intel_create_plane_state(&primary->base);
13539         if (!state)
13540                 goto fail;
13541         primary->base.state = &state->base;
13542
13543         primary->can_scale = false;
13544         primary->max_downscale = 1;
13545         if (INTEL_INFO(dev)->gen >= 9) {
13546                 primary->can_scale = true;
13547                 state->scaler_id = -1;
13548         }
13549         primary->pipe = pipe;
13550         primary->plane = pipe;
13551         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13552         primary->check_plane = intel_check_primary_plane;
13553         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13554                 primary->plane = !pipe;
13555
13556         if (INTEL_INFO(dev)->gen >= 9) {
13557                 intel_primary_formats = skl_primary_formats;
13558                 num_formats = ARRAY_SIZE(skl_primary_formats);
13559
13560                 primary->update_plane = skylake_update_primary_plane;
13561                 primary->disable_plane = skylake_disable_primary_plane;
13562         } else if (HAS_PCH_SPLIT(dev)) {
13563                 intel_primary_formats = i965_primary_formats;
13564                 num_formats = ARRAY_SIZE(i965_primary_formats);
13565
13566                 primary->update_plane = ironlake_update_primary_plane;
13567                 primary->disable_plane = i9xx_disable_primary_plane;
13568         } else if (INTEL_INFO(dev)->gen >= 4) {
13569                 intel_primary_formats = i965_primary_formats;
13570                 num_formats = ARRAY_SIZE(i965_primary_formats);
13571
13572                 primary->update_plane = i9xx_update_primary_plane;
13573                 primary->disable_plane = i9xx_disable_primary_plane;
13574         } else {
13575                 intel_primary_formats = i8xx_primary_formats;
13576                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13577
13578                 primary->update_plane = i9xx_update_primary_plane;
13579                 primary->disable_plane = i9xx_disable_primary_plane;
13580         }
13581
13582         ret = drm_universal_plane_init(dev, &primary->base, 0,
13583                                        &intel_plane_funcs,
13584                                        intel_primary_formats, num_formats,
13585                                        DRM_PLANE_TYPE_PRIMARY, NULL);
13586         if (ret)
13587                 goto fail;
13588
13589         if (INTEL_INFO(dev)->gen >= 4)
13590                 intel_create_rotation_property(dev, primary);
13591
13592         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13593
13594         return &primary->base;
13595
13596 fail:
13597         kfree(state);
13598         kfree(primary);
13599
13600         return NULL;
13601 }
13602
13603 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13604 {
13605         if (!dev->mode_config.rotation_property) {
13606                 unsigned long flags = BIT(DRM_ROTATE_0) |
13607                         BIT(DRM_ROTATE_180);
13608
13609                 if (INTEL_INFO(dev)->gen >= 9)
13610                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13611
13612                 dev->mode_config.rotation_property =
13613                         drm_mode_create_rotation_property(dev, flags);
13614         }
13615         if (dev->mode_config.rotation_property)
13616                 drm_object_attach_property(&plane->base.base,
13617                                 dev->mode_config.rotation_property,
13618                                 plane->base.state->rotation);
13619 }
13620
13621 static int
13622 intel_check_cursor_plane(struct drm_plane *plane,
13623                          struct intel_crtc_state *crtc_state,
13624                          struct intel_plane_state *state)
13625 {
13626         struct drm_crtc *crtc = crtc_state->base.crtc;
13627         struct drm_framebuffer *fb = state->base.fb;
13628         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13629         enum pipe pipe = to_intel_plane(plane)->pipe;
13630         unsigned stride;
13631         int ret;
13632
13633         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13634                                             &state->dst, &state->clip,
13635                                             DRM_PLANE_HELPER_NO_SCALING,
13636                                             DRM_PLANE_HELPER_NO_SCALING,
13637                                             true, true, &state->visible);
13638         if (ret)
13639                 return ret;
13640
13641         /* if we want to turn off the cursor ignore width and height */
13642         if (!obj)
13643                 return 0;
13644
13645         /* Check for which cursor types we support */
13646         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13647                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13648                           state->base.crtc_w, state->base.crtc_h);
13649                 return -EINVAL;
13650         }
13651
13652         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13653         if (obj->base.size < stride * state->base.crtc_h) {
13654                 DRM_DEBUG_KMS("buffer is too small\n");
13655                 return -ENOMEM;
13656         }
13657
13658         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13659                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13660                 return -EINVAL;
13661         }
13662
13663         /*
13664          * There's something wrong with the cursor on CHV pipe C.
13665          * If it straddles the left edge of the screen then
13666          * moving it away from the edge or disabling it often
13667          * results in a pipe underrun, and often that can lead to
13668          * dead pipe (constant underrun reported, and it scans
13669          * out just a solid color). To recover from that, the
13670          * display power well must be turned off and on again.
13671          * Refuse the put the cursor into that compromised position.
13672          */
13673         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
13674             state->visible && state->base.crtc_x < 0) {
13675                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13676                 return -EINVAL;
13677         }
13678
13679         return 0;
13680 }
13681
13682 static void
13683 intel_disable_cursor_plane(struct drm_plane *plane,
13684                            struct drm_crtc *crtc)
13685 {
13686         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13687
13688         intel_crtc->cursor_addr = 0;
13689         intel_crtc_update_cursor(crtc, NULL);
13690 }
13691
13692 static void
13693 intel_update_cursor_plane(struct drm_plane *plane,
13694                           const struct intel_crtc_state *crtc_state,
13695                           const struct intel_plane_state *state)
13696 {
13697         struct drm_crtc *crtc = crtc_state->base.crtc;
13698         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13699         struct drm_device *dev = plane->dev;
13700         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13701         uint32_t addr;
13702
13703         if (!obj)
13704                 addr = 0;
13705         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13706                 addr = i915_gem_obj_ggtt_offset(obj);
13707         else
13708                 addr = obj->phys_handle->busaddr;
13709
13710         intel_crtc->cursor_addr = addr;
13711         intel_crtc_update_cursor(crtc, state);
13712 }
13713
13714 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13715                                                    int pipe)
13716 {
13717         struct intel_plane *cursor = NULL;
13718         struct intel_plane_state *state = NULL;
13719         int ret;
13720
13721         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13722         if (!cursor)
13723                 goto fail;
13724
13725         state = intel_create_plane_state(&cursor->base);
13726         if (!state)
13727                 goto fail;
13728         cursor->base.state = &state->base;
13729
13730         cursor->can_scale = false;
13731         cursor->max_downscale = 1;
13732         cursor->pipe = pipe;
13733         cursor->plane = pipe;
13734         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13735         cursor->check_plane = intel_check_cursor_plane;
13736         cursor->update_plane = intel_update_cursor_plane;
13737         cursor->disable_plane = intel_disable_cursor_plane;
13738
13739         ret = drm_universal_plane_init(dev, &cursor->base, 0,
13740                                        &intel_plane_funcs,
13741                                        intel_cursor_formats,
13742                                        ARRAY_SIZE(intel_cursor_formats),
13743                                        DRM_PLANE_TYPE_CURSOR, NULL);
13744         if (ret)
13745                 goto fail;
13746
13747         if (INTEL_INFO(dev)->gen >= 4) {
13748                 if (!dev->mode_config.rotation_property)
13749                         dev->mode_config.rotation_property =
13750                                 drm_mode_create_rotation_property(dev,
13751                                                         BIT(DRM_ROTATE_0) |
13752                                                         BIT(DRM_ROTATE_180));
13753                 if (dev->mode_config.rotation_property)
13754                         drm_object_attach_property(&cursor->base.base,
13755                                 dev->mode_config.rotation_property,
13756                                 state->base.rotation);
13757         }
13758
13759         if (INTEL_INFO(dev)->gen >=9)
13760                 state->scaler_id = -1;
13761
13762         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13763
13764         return &cursor->base;
13765
13766 fail:
13767         kfree(state);
13768         kfree(cursor);
13769
13770         return NULL;
13771 }
13772
13773 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13774         struct intel_crtc_state *crtc_state)
13775 {
13776         int i;
13777         struct intel_scaler *intel_scaler;
13778         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13779
13780         for (i = 0; i < intel_crtc->num_scalers; i++) {
13781                 intel_scaler = &scaler_state->scalers[i];
13782                 intel_scaler->in_use = 0;
13783                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13784         }
13785
13786         scaler_state->scaler_id = -1;
13787 }
13788
13789 static void intel_crtc_init(struct drm_device *dev, int pipe)
13790 {
13791         struct drm_i915_private *dev_priv = dev->dev_private;
13792         struct intel_crtc *intel_crtc;
13793         struct intel_crtc_state *crtc_state = NULL;
13794         struct drm_plane *primary = NULL;
13795         struct drm_plane *cursor = NULL;
13796         int ret;
13797
13798         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13799         if (intel_crtc == NULL)
13800                 return;
13801
13802         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13803         if (!crtc_state)
13804                 goto fail;
13805         intel_crtc->config = crtc_state;
13806         intel_crtc->base.state = &crtc_state->base;
13807         crtc_state->base.crtc = &intel_crtc->base;
13808
13809         INIT_LIST_HEAD(&intel_crtc->flip_work);
13810
13811         /* initialize shared scalers */
13812         if (INTEL_INFO(dev)->gen >= 9) {
13813                 if (pipe == PIPE_C)
13814                         intel_crtc->num_scalers = 1;
13815                 else
13816                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13817
13818                 skl_init_scalers(dev, intel_crtc, crtc_state);
13819         }
13820
13821         primary = intel_primary_plane_create(dev, pipe);
13822         if (!primary)
13823                 goto fail;
13824
13825         cursor = intel_cursor_plane_create(dev, pipe);
13826         if (!cursor)
13827                 goto fail;
13828
13829         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13830                                         cursor, &intel_crtc_funcs, NULL);
13831         if (ret)
13832                 goto fail;
13833
13834         /*
13835          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13836          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13837          */
13838         intel_crtc->pipe = pipe;
13839         intel_crtc->plane = pipe;
13840         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13841                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13842                 intel_crtc->plane = !pipe;
13843         }
13844
13845         intel_crtc->cursor_base = ~0;
13846         intel_crtc->cursor_cntl = ~0;
13847         intel_crtc->cursor_size = ~0;
13848
13849         intel_crtc->wm.cxsr_allowed = true;
13850
13851         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13852                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13853         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13854         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13855
13856         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13857
13858         intel_color_init(&intel_crtc->base);
13859
13860         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13861         return;
13862
13863 fail:
13864         if (primary)
13865                 drm_plane_cleanup(primary);
13866         if (cursor)
13867                 drm_plane_cleanup(cursor);
13868         kfree(crtc_state);
13869         kfree(intel_crtc);
13870 }
13871
13872 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13873 {
13874         struct drm_encoder *encoder = connector->base.encoder;
13875         struct drm_device *dev = connector->base.dev;
13876
13877         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13878
13879         if (!encoder || WARN_ON(!encoder->crtc))
13880                 return INVALID_PIPE;
13881
13882         return to_intel_crtc(encoder->crtc)->pipe;
13883 }
13884
13885 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13886                                 struct drm_file *file)
13887 {
13888         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13889         struct drm_crtc *drmmode_crtc;
13890         struct intel_crtc *crtc;
13891
13892         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13893
13894         if (!drmmode_crtc) {
13895                 DRM_ERROR("no such CRTC id\n");
13896                 return -ENOENT;
13897         }
13898
13899         crtc = to_intel_crtc(drmmode_crtc);
13900         pipe_from_crtc_id->pipe = crtc->pipe;
13901
13902         return 0;
13903 }
13904
13905 static int intel_encoder_clones(struct intel_encoder *encoder)
13906 {
13907         struct drm_device *dev = encoder->base.dev;
13908         struct intel_encoder *source_encoder;
13909         int index_mask = 0;
13910         int entry = 0;
13911
13912         for_each_intel_encoder(dev, source_encoder) {
13913                 if (encoders_cloneable(encoder, source_encoder))
13914                         index_mask |= (1 << entry);
13915
13916                 entry++;
13917         }
13918
13919         return index_mask;
13920 }
13921
13922 static bool has_edp_a(struct drm_device *dev)
13923 {
13924         struct drm_i915_private *dev_priv = dev->dev_private;
13925
13926         if (!IS_MOBILE(dev))
13927                 return false;
13928
13929         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13930                 return false;
13931
13932         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13933                 return false;
13934
13935         return true;
13936 }
13937
13938 static bool intel_crt_present(struct drm_device *dev)
13939 {
13940         struct drm_i915_private *dev_priv = dev->dev_private;
13941
13942         if (INTEL_INFO(dev)->gen >= 9)
13943                 return false;
13944
13945         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13946                 return false;
13947
13948         if (IS_CHERRYVIEW(dev))
13949                 return false;
13950
13951         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13952                 return false;
13953
13954         /* DDI E can't be used if DDI A requires 4 lanes */
13955         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13956                 return false;
13957
13958         if (!dev_priv->vbt.int_crt_support)
13959                 return false;
13960
13961         return true;
13962 }
13963
13964 static void intel_setup_outputs(struct drm_device *dev)
13965 {
13966         struct drm_i915_private *dev_priv = dev->dev_private;
13967         struct intel_encoder *encoder;
13968         bool dpd_is_edp = false;
13969
13970         intel_lvds_init(dev);
13971
13972         if (intel_crt_present(dev))
13973                 intel_crt_init(dev);
13974
13975         if (IS_BROXTON(dev)) {
13976                 /*
13977                  * FIXME: Broxton doesn't support port detection via the
13978                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13979                  * detect the ports.
13980                  */
13981                 intel_ddi_init(dev, PORT_A);
13982                 intel_ddi_init(dev, PORT_B);
13983                 intel_ddi_init(dev, PORT_C);
13984
13985                 intel_dsi_init(dev);
13986         } else if (HAS_DDI(dev)) {
13987                 int found;
13988
13989                 /*
13990                  * Haswell uses DDI functions to detect digital outputs.
13991                  * On SKL pre-D0 the strap isn't connected, so we assume
13992                  * it's there.
13993                  */
13994                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13995                 /* WaIgnoreDDIAStrap: skl */
13996                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
13997                         intel_ddi_init(dev, PORT_A);
13998
13999                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14000                  * register */
14001                 found = I915_READ(SFUSE_STRAP);
14002
14003                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14004                         intel_ddi_init(dev, PORT_B);
14005                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14006                         intel_ddi_init(dev, PORT_C);
14007                 if (found & SFUSE_STRAP_DDID_DETECTED)
14008                         intel_ddi_init(dev, PORT_D);
14009                 /*
14010                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14011                  */
14012                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14013                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14014                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14015                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14016                         intel_ddi_init(dev, PORT_E);
14017
14018         } else if (HAS_PCH_SPLIT(dev)) {
14019                 int found;
14020                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14021
14022                 if (has_edp_a(dev))
14023                         intel_dp_init(dev, DP_A, PORT_A);
14024
14025                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14026                         /* PCH SDVOB multiplex with HDMIB */
14027                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14028                         if (!found)
14029                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14030                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14031                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14032                 }
14033
14034                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14035                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14036
14037                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14038                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14039
14040                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14041                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14042
14043                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14044                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14045         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14046                 /*
14047                  * The DP_DETECTED bit is the latched state of the DDC
14048                  * SDA pin at boot. However since eDP doesn't require DDC
14049                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14050                  * eDP ports may have been muxed to an alternate function.
14051                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14052                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14053                  * detect eDP ports.
14054                  */
14055                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14056                     !intel_dp_is_edp(dev, PORT_B))
14057                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14058                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14059                     intel_dp_is_edp(dev, PORT_B))
14060                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14061
14062                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14063                     !intel_dp_is_edp(dev, PORT_C))
14064                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14065                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14066                     intel_dp_is_edp(dev, PORT_C))
14067                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14068
14069                 if (IS_CHERRYVIEW(dev)) {
14070                         /* eDP not supported on port D, so don't check VBT */
14071                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14072                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14073                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14074                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14075                 }
14076
14077                 intel_dsi_init(dev);
14078         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14079                 bool found = false;
14080
14081                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14082                         DRM_DEBUG_KMS("probing SDVOB\n");
14083                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14084                         if (!found && IS_G4X(dev)) {
14085                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14086                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14087                         }
14088
14089                         if (!found && IS_G4X(dev))
14090                                 intel_dp_init(dev, DP_B, PORT_B);
14091                 }
14092
14093                 /* Before G4X SDVOC doesn't have its own detect register */
14094
14095                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14096                         DRM_DEBUG_KMS("probing SDVOC\n");
14097                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14098                 }
14099
14100                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14101
14102                         if (IS_G4X(dev)) {
14103                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14104                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14105                         }
14106                         if (IS_G4X(dev))
14107                                 intel_dp_init(dev, DP_C, PORT_C);
14108                 }
14109
14110                 if (IS_G4X(dev) &&
14111                     (I915_READ(DP_D) & DP_DETECTED))
14112                         intel_dp_init(dev, DP_D, PORT_D);
14113         } else if (IS_GEN2(dev))
14114                 intel_dvo_init(dev);
14115
14116         if (SUPPORTS_TV(dev))
14117                 intel_tv_init(dev);
14118
14119         intel_psr_init(dev);
14120
14121         for_each_intel_encoder(dev, encoder) {
14122                 encoder->base.possible_crtcs = encoder->crtc_mask;
14123                 encoder->base.possible_clones =
14124                         intel_encoder_clones(encoder);
14125         }
14126
14127         intel_init_pch_refclk(dev);
14128
14129         drm_helper_move_panel_connectors_to_head(dev);
14130 }
14131
14132 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14133 {
14134         struct drm_device *dev = fb->dev;
14135         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14136
14137         drm_framebuffer_cleanup(fb);
14138         mutex_lock(&dev->struct_mutex);
14139         WARN_ON(!intel_fb->obj->framebuffer_references--);
14140         drm_gem_object_unreference(&intel_fb->obj->base);
14141         mutex_unlock(&dev->struct_mutex);
14142         kfree(intel_fb);
14143 }
14144
14145 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14146                                                 struct drm_file *file,
14147                                                 unsigned int *handle)
14148 {
14149         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14150         struct drm_i915_gem_object *obj = intel_fb->obj;
14151
14152         if (obj->userptr.mm) {
14153                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14154                 return -EINVAL;
14155         }
14156
14157         return drm_gem_handle_create(file, &obj->base, handle);
14158 }
14159
14160 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14161                                         struct drm_file *file,
14162                                         unsigned flags, unsigned color,
14163                                         struct drm_clip_rect *clips,
14164                                         unsigned num_clips)
14165 {
14166         struct drm_device *dev = fb->dev;
14167         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14168         struct drm_i915_gem_object *obj = intel_fb->obj;
14169
14170         mutex_lock(&dev->struct_mutex);
14171         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14172         mutex_unlock(&dev->struct_mutex);
14173
14174         return 0;
14175 }
14176
14177 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14178         .destroy = intel_user_framebuffer_destroy,
14179         .create_handle = intel_user_framebuffer_create_handle,
14180         .dirty = intel_user_framebuffer_dirty,
14181 };
14182
14183 static
14184 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14185                          uint32_t pixel_format)
14186 {
14187         u32 gen = INTEL_INFO(dev)->gen;
14188
14189         if (gen >= 9) {
14190                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14191
14192                 /* "The stride in bytes must not exceed the of the size of 8K
14193                  *  pixels and 32K bytes."
14194                  */
14195                 return min(8192 * cpp, 32768);
14196         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14197                 return 32*1024;
14198         } else if (gen >= 4) {
14199                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14200                         return 16*1024;
14201                 else
14202                         return 32*1024;
14203         } else if (gen >= 3) {
14204                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14205                         return 8*1024;
14206                 else
14207                         return 16*1024;
14208         } else {
14209                 /* XXX DSPC is limited to 4k tiled */
14210                 return 8*1024;
14211         }
14212 }
14213
14214 static int intel_framebuffer_init(struct drm_device *dev,
14215                                   struct intel_framebuffer *intel_fb,
14216                                   struct drm_mode_fb_cmd2 *mode_cmd,
14217                                   struct drm_i915_gem_object *obj)
14218 {
14219         struct drm_i915_private *dev_priv = to_i915(dev);
14220         unsigned int aligned_height;
14221         int ret;
14222         u32 pitch_limit, stride_alignment;
14223
14224         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14225
14226         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14227                 /* Enforce that fb modifier and tiling mode match, but only for
14228                  * X-tiled. This is needed for FBC. */
14229                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14230                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14231                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14232                         return -EINVAL;
14233                 }
14234         } else {
14235                 if (obj->tiling_mode == I915_TILING_X)
14236                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14237                 else if (obj->tiling_mode == I915_TILING_Y) {
14238                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14239                         return -EINVAL;
14240                 }
14241         }
14242
14243         /* Passed in modifier sanity checking. */
14244         switch (mode_cmd->modifier[0]) {
14245         case I915_FORMAT_MOD_Y_TILED:
14246         case I915_FORMAT_MOD_Yf_TILED:
14247                 if (INTEL_INFO(dev)->gen < 9) {
14248                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14249                                   mode_cmd->modifier[0]);
14250                         return -EINVAL;
14251                 }
14252         case DRM_FORMAT_MOD_NONE:
14253         case I915_FORMAT_MOD_X_TILED:
14254                 break;
14255         default:
14256                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14257                           mode_cmd->modifier[0]);
14258                 return -EINVAL;
14259         }
14260
14261         stride_alignment = intel_fb_stride_alignment(dev_priv,
14262                                                      mode_cmd->modifier[0],
14263                                                      mode_cmd->pixel_format);
14264         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14265                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14266                           mode_cmd->pitches[0], stride_alignment);
14267                 return -EINVAL;
14268         }
14269
14270         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14271                                            mode_cmd->pixel_format);
14272         if (mode_cmd->pitches[0] > pitch_limit) {
14273                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14274                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14275                           "tiled" : "linear",
14276                           mode_cmd->pitches[0], pitch_limit);
14277                 return -EINVAL;
14278         }
14279
14280         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14281             mode_cmd->pitches[0] != obj->stride) {
14282                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14283                           mode_cmd->pitches[0], obj->stride);
14284                 return -EINVAL;
14285         }
14286
14287         /* Reject formats not supported by any plane early. */
14288         switch (mode_cmd->pixel_format) {
14289         case DRM_FORMAT_C8:
14290         case DRM_FORMAT_RGB565:
14291         case DRM_FORMAT_XRGB8888:
14292         case DRM_FORMAT_ARGB8888:
14293                 break;
14294         case DRM_FORMAT_XRGB1555:
14295                 if (INTEL_INFO(dev)->gen > 3) {
14296                         DRM_DEBUG("unsupported pixel format: %s\n",
14297                                   drm_get_format_name(mode_cmd->pixel_format));
14298                         return -EINVAL;
14299                 }
14300                 break;
14301         case DRM_FORMAT_ABGR8888:
14302                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14303                     INTEL_INFO(dev)->gen < 9) {
14304                         DRM_DEBUG("unsupported pixel format: %s\n",
14305                                   drm_get_format_name(mode_cmd->pixel_format));
14306                         return -EINVAL;
14307                 }
14308                 break;
14309         case DRM_FORMAT_XBGR8888:
14310         case DRM_FORMAT_XRGB2101010:
14311         case DRM_FORMAT_XBGR2101010:
14312                 if (INTEL_INFO(dev)->gen < 4) {
14313                         DRM_DEBUG("unsupported pixel format: %s\n",
14314                                   drm_get_format_name(mode_cmd->pixel_format));
14315                         return -EINVAL;
14316                 }
14317                 break;
14318         case DRM_FORMAT_ABGR2101010:
14319                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14320                         DRM_DEBUG("unsupported pixel format: %s\n",
14321                                   drm_get_format_name(mode_cmd->pixel_format));
14322                         return -EINVAL;
14323                 }
14324                 break;
14325         case DRM_FORMAT_YUYV:
14326         case DRM_FORMAT_UYVY:
14327         case DRM_FORMAT_YVYU:
14328         case DRM_FORMAT_VYUY:
14329                 if (INTEL_INFO(dev)->gen < 5) {
14330                         DRM_DEBUG("unsupported pixel format: %s\n",
14331                                   drm_get_format_name(mode_cmd->pixel_format));
14332                         return -EINVAL;
14333                 }
14334                 break;
14335         default:
14336                 DRM_DEBUG("unsupported pixel format: %s\n",
14337                           drm_get_format_name(mode_cmd->pixel_format));
14338                 return -EINVAL;
14339         }
14340
14341         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14342         if (mode_cmd->offsets[0] != 0)
14343                 return -EINVAL;
14344
14345         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14346                                                mode_cmd->pixel_format,
14347                                                mode_cmd->modifier[0]);
14348         /* FIXME drm helper for size checks (especially planar formats)? */
14349         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14350                 return -EINVAL;
14351
14352         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14353         intel_fb->obj = obj;
14354
14355         intel_fill_fb_info(dev_priv, &intel_fb->base);
14356
14357         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14358         if (ret) {
14359                 DRM_ERROR("framebuffer init failed %d\n", ret);
14360                 return ret;
14361         }
14362
14363         intel_fb->obj->framebuffer_references++;
14364
14365         return 0;
14366 }
14367
14368 static struct drm_framebuffer *
14369 intel_user_framebuffer_create(struct drm_device *dev,
14370                               struct drm_file *filp,
14371                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14372 {
14373         struct drm_framebuffer *fb;
14374         struct drm_i915_gem_object *obj;
14375         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14376
14377         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14378                                                 mode_cmd.handles[0]));
14379         if (&obj->base == NULL)
14380                 return ERR_PTR(-ENOENT);
14381
14382         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14383         if (IS_ERR(fb))
14384                 drm_gem_object_unreference_unlocked(&obj->base);
14385
14386         return fb;
14387 }
14388
14389 #ifndef CONFIG_DRM_FBDEV_EMULATION
14390 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14391 {
14392 }
14393 #endif
14394
14395 static const struct drm_mode_config_funcs intel_mode_funcs = {
14396         .fb_create = intel_user_framebuffer_create,
14397         .output_poll_changed = intel_fbdev_output_poll_changed,
14398         .atomic_check = intel_atomic_check,
14399         .atomic_commit = intel_atomic_commit,
14400         .atomic_state_alloc = intel_atomic_state_alloc,
14401         .atomic_state_clear = intel_atomic_state_clear,
14402 };
14403
14404 /**
14405  * intel_init_display_hooks - initialize the display modesetting hooks
14406  * @dev_priv: device private
14407  */
14408 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14409 {
14410         if (INTEL_INFO(dev_priv)->gen >= 9) {
14411                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14412                 dev_priv->display.get_initial_plane_config =
14413                         skylake_get_initial_plane_config;
14414                 dev_priv->display.crtc_compute_clock =
14415                         haswell_crtc_compute_clock;
14416                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14417                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14418         } else if (HAS_DDI(dev_priv)) {
14419                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14420                 dev_priv->display.get_initial_plane_config =
14421                         ironlake_get_initial_plane_config;
14422                 dev_priv->display.crtc_compute_clock =
14423                         haswell_crtc_compute_clock;
14424                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14425                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14426         } else if (HAS_PCH_SPLIT(dev_priv)) {
14427                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14428                 dev_priv->display.get_initial_plane_config =
14429                         ironlake_get_initial_plane_config;
14430                 dev_priv->display.crtc_compute_clock =
14431                         ironlake_crtc_compute_clock;
14432                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14433                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14434         } else if (IS_CHERRYVIEW(dev_priv)) {
14435                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14436                 dev_priv->display.get_initial_plane_config =
14437                         i9xx_get_initial_plane_config;
14438                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14439                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14440                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14441         } else if (IS_VALLEYVIEW(dev_priv)) {
14442                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14443                 dev_priv->display.get_initial_plane_config =
14444                         i9xx_get_initial_plane_config;
14445                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14446                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14447                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14448         } else if (IS_G4X(dev_priv)) {
14449                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14450                 dev_priv->display.get_initial_plane_config =
14451                         i9xx_get_initial_plane_config;
14452                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14453                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14454                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14455         } else if (IS_PINEVIEW(dev_priv)) {
14456                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14457                 dev_priv->display.get_initial_plane_config =
14458                         i9xx_get_initial_plane_config;
14459                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14460                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14461                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14462         } else if (!IS_GEN2(dev_priv)) {
14463                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14464                 dev_priv->display.get_initial_plane_config =
14465                         i9xx_get_initial_plane_config;
14466                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14467                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14468                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14469         } else {
14470                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14471                 dev_priv->display.get_initial_plane_config =
14472                         i9xx_get_initial_plane_config;
14473                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14474                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14475                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14476         }
14477
14478         /* Returns the core display clock speed */
14479         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14480                 dev_priv->display.get_display_clock_speed =
14481                         skylake_get_display_clock_speed;
14482         else if (IS_BROXTON(dev_priv))
14483                 dev_priv->display.get_display_clock_speed =
14484                         broxton_get_display_clock_speed;
14485         else if (IS_BROADWELL(dev_priv))
14486                 dev_priv->display.get_display_clock_speed =
14487                         broadwell_get_display_clock_speed;
14488         else if (IS_HASWELL(dev_priv))
14489                 dev_priv->display.get_display_clock_speed =
14490                         haswell_get_display_clock_speed;
14491         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14492                 dev_priv->display.get_display_clock_speed =
14493                         valleyview_get_display_clock_speed;
14494         else if (IS_GEN5(dev_priv))
14495                 dev_priv->display.get_display_clock_speed =
14496                         ilk_get_display_clock_speed;
14497         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14498                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14499                 dev_priv->display.get_display_clock_speed =
14500                         i945_get_display_clock_speed;
14501         else if (IS_GM45(dev_priv))
14502                 dev_priv->display.get_display_clock_speed =
14503                         gm45_get_display_clock_speed;
14504         else if (IS_CRESTLINE(dev_priv))
14505                 dev_priv->display.get_display_clock_speed =
14506                         i965gm_get_display_clock_speed;
14507         else if (IS_PINEVIEW(dev_priv))
14508                 dev_priv->display.get_display_clock_speed =
14509                         pnv_get_display_clock_speed;
14510         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
14511                 dev_priv->display.get_display_clock_speed =
14512                         g33_get_display_clock_speed;
14513         else if (IS_I915G(dev_priv))
14514                 dev_priv->display.get_display_clock_speed =
14515                         i915_get_display_clock_speed;
14516         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
14517                 dev_priv->display.get_display_clock_speed =
14518                         i9xx_misc_get_display_clock_speed;
14519         else if (IS_I915GM(dev_priv))
14520                 dev_priv->display.get_display_clock_speed =
14521                         i915gm_get_display_clock_speed;
14522         else if (IS_I865G(dev_priv))
14523                 dev_priv->display.get_display_clock_speed =
14524                         i865_get_display_clock_speed;
14525         else if (IS_I85X(dev_priv))
14526                 dev_priv->display.get_display_clock_speed =
14527                         i85x_get_display_clock_speed;
14528         else { /* 830 */
14529                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
14530                 dev_priv->display.get_display_clock_speed =
14531                         i830_get_display_clock_speed;
14532         }
14533
14534         if (IS_GEN5(dev_priv)) {
14535                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14536         } else if (IS_GEN6(dev_priv)) {
14537                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14538         } else if (IS_IVYBRIDGE(dev_priv)) {
14539                 /* FIXME: detect B0+ stepping and use auto training */
14540                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14541         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14542                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14543         }
14544
14545         if (IS_BROADWELL(dev_priv)) {
14546                 dev_priv->display.modeset_commit_cdclk =
14547                         broadwell_modeset_commit_cdclk;
14548                 dev_priv->display.modeset_calc_cdclk =
14549                         broadwell_modeset_calc_cdclk;
14550         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14551                 dev_priv->display.modeset_commit_cdclk =
14552                         valleyview_modeset_commit_cdclk;
14553                 dev_priv->display.modeset_calc_cdclk =
14554                         valleyview_modeset_calc_cdclk;
14555         } else if (IS_BROXTON(dev_priv)) {
14556                 dev_priv->display.modeset_commit_cdclk =
14557                         broxton_modeset_commit_cdclk;
14558                 dev_priv->display.modeset_calc_cdclk =
14559                         broxton_modeset_calc_cdclk;
14560         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
14561                 dev_priv->display.modeset_commit_cdclk =
14562                         skl_modeset_commit_cdclk;
14563                 dev_priv->display.modeset_calc_cdclk =
14564                         skl_modeset_calc_cdclk;
14565         }
14566 }
14567
14568 /*
14569  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14570  * resume, or other times.  This quirk makes sure that's the case for
14571  * affected systems.
14572  */
14573 static void quirk_pipea_force(struct drm_device *dev)
14574 {
14575         struct drm_i915_private *dev_priv = dev->dev_private;
14576
14577         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14578         DRM_INFO("applying pipe a force quirk\n");
14579 }
14580
14581 static void quirk_pipeb_force(struct drm_device *dev)
14582 {
14583         struct drm_i915_private *dev_priv = dev->dev_private;
14584
14585         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14586         DRM_INFO("applying pipe b force quirk\n");
14587 }
14588
14589 /*
14590  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14591  */
14592 static void quirk_ssc_force_disable(struct drm_device *dev)
14593 {
14594         struct drm_i915_private *dev_priv = dev->dev_private;
14595         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14596         DRM_INFO("applying lvds SSC disable quirk\n");
14597 }
14598
14599 /*
14600  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14601  * brightness value
14602  */
14603 static void quirk_invert_brightness(struct drm_device *dev)
14604 {
14605         struct drm_i915_private *dev_priv = dev->dev_private;
14606         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14607         DRM_INFO("applying inverted panel brightness quirk\n");
14608 }
14609
14610 /* Some VBT's incorrectly indicate no backlight is present */
14611 static void quirk_backlight_present(struct drm_device *dev)
14612 {
14613         struct drm_i915_private *dev_priv = dev->dev_private;
14614         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14615         DRM_INFO("applying backlight present quirk\n");
14616 }
14617
14618 struct intel_quirk {
14619         int device;
14620         int subsystem_vendor;
14621         int subsystem_device;
14622         void (*hook)(struct drm_device *dev);
14623 };
14624
14625 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14626 struct intel_dmi_quirk {
14627         void (*hook)(struct drm_device *dev);
14628         const struct dmi_system_id (*dmi_id_list)[];
14629 };
14630
14631 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14632 {
14633         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14634         return 1;
14635 }
14636
14637 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14638         {
14639                 .dmi_id_list = &(const struct dmi_system_id[]) {
14640                         {
14641                                 .callback = intel_dmi_reverse_brightness,
14642                                 .ident = "NCR Corporation",
14643                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14644                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14645                                 },
14646                         },
14647                         { }  /* terminating entry */
14648                 },
14649                 .hook = quirk_invert_brightness,
14650         },
14651 };
14652
14653 static struct intel_quirk intel_quirks[] = {
14654         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14655         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14656
14657         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14658         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14659
14660         /* 830 needs to leave pipe A & dpll A up */
14661         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14662
14663         /* 830 needs to leave pipe B & dpll B up */
14664         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14665
14666         /* Lenovo U160 cannot use SSC on LVDS */
14667         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14668
14669         /* Sony Vaio Y cannot use SSC on LVDS */
14670         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14671
14672         /* Acer Aspire 5734Z must invert backlight brightness */
14673         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14674
14675         /* Acer/eMachines G725 */
14676         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14677
14678         /* Acer/eMachines e725 */
14679         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14680
14681         /* Acer/Packard Bell NCL20 */
14682         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14683
14684         /* Acer Aspire 4736Z */
14685         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14686
14687         /* Acer Aspire 5336 */
14688         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14689
14690         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14691         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14692
14693         /* Acer C720 Chromebook (Core i3 4005U) */
14694         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14695
14696         /* Apple Macbook 2,1 (Core 2 T7400) */
14697         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14698
14699         /* Apple Macbook 4,1 */
14700         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14701
14702         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14703         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14704
14705         /* HP Chromebook 14 (Celeron 2955U) */
14706         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14707
14708         /* Dell Chromebook 11 */
14709         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14710
14711         /* Dell Chromebook 11 (2015 version) */
14712         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14713 };
14714
14715 static void intel_init_quirks(struct drm_device *dev)
14716 {
14717         struct pci_dev *d = dev->pdev;
14718         int i;
14719
14720         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14721                 struct intel_quirk *q = &intel_quirks[i];
14722
14723                 if (d->device == q->device &&
14724                     (d->subsystem_vendor == q->subsystem_vendor ||
14725                      q->subsystem_vendor == PCI_ANY_ID) &&
14726                     (d->subsystem_device == q->subsystem_device ||
14727                      q->subsystem_device == PCI_ANY_ID))
14728                         q->hook(dev);
14729         }
14730         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14731                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14732                         intel_dmi_quirks[i].hook(dev);
14733         }
14734 }
14735
14736 /* Disable the VGA plane that we never use */
14737 static void i915_disable_vga(struct drm_device *dev)
14738 {
14739         struct drm_i915_private *dev_priv = dev->dev_private;
14740         u8 sr1;
14741         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
14742
14743         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14744         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14745         outb(SR01, VGA_SR_INDEX);
14746         sr1 = inb(VGA_SR_DATA);
14747         outb(sr1 | 1<<5, VGA_SR_DATA);
14748         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14749         udelay(300);
14750
14751         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14752         POSTING_READ(vga_reg);
14753 }
14754
14755 void intel_modeset_init_hw(struct drm_device *dev)
14756 {
14757         struct drm_i915_private *dev_priv = dev->dev_private;
14758
14759         intel_update_cdclk(dev);
14760
14761         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
14762
14763         intel_init_clock_gating(dev);
14764         intel_enable_gt_powersave(dev_priv);
14765 }
14766
14767 /*
14768  * Calculate what we think the watermarks should be for the state we've read
14769  * out of the hardware and then immediately program those watermarks so that
14770  * we ensure the hardware settings match our internal state.
14771  *
14772  * We can calculate what we think WM's should be by creating a duplicate of the
14773  * current state (which was constructed during hardware readout) and running it
14774  * through the atomic check code to calculate new watermark values in the
14775  * state object.
14776  */
14777 static void sanitize_watermarks(struct drm_device *dev)
14778 {
14779         struct drm_i915_private *dev_priv = to_i915(dev);
14780         struct drm_atomic_state *state;
14781         struct drm_crtc *crtc;
14782         struct drm_crtc_state *cstate;
14783         struct drm_modeset_acquire_ctx ctx;
14784         int ret;
14785         int i;
14786
14787         /* Only supported on platforms that use atomic watermark design */
14788         if (!dev_priv->display.optimize_watermarks)
14789                 return;
14790
14791         /*
14792          * We need to hold connection_mutex before calling duplicate_state so
14793          * that the connector loop is protected.
14794          */
14795         drm_modeset_acquire_init(&ctx, 0);
14796 retry:
14797         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14798         if (ret == -EDEADLK) {
14799                 drm_modeset_backoff(&ctx);
14800                 goto retry;
14801         } else if (WARN_ON(ret)) {
14802                 goto fail;
14803         }
14804
14805         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14806         if (WARN_ON(IS_ERR(state)))
14807                 goto fail;
14808
14809         /*
14810          * Hardware readout is the only time we don't want to calculate
14811          * intermediate watermarks (since we don't trust the current
14812          * watermarks).
14813          */
14814         to_intel_atomic_state(state)->skip_intermediate_wm = true;
14815
14816         ret = intel_atomic_check(dev, state);
14817         if (ret) {
14818                 /*
14819                  * If we fail here, it means that the hardware appears to be
14820                  * programmed in a way that shouldn't be possible, given our
14821                  * understanding of watermark requirements.  This might mean a
14822                  * mistake in the hardware readout code or a mistake in the
14823                  * watermark calculations for a given platform.  Raise a WARN
14824                  * so that this is noticeable.
14825                  *
14826                  * If this actually happens, we'll have to just leave the
14827                  * BIOS-programmed watermarks untouched and hope for the best.
14828                  */
14829                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14830                 goto fail;
14831         }
14832
14833         /* Write calculated watermark values back */
14834         for_each_crtc_in_state(state, crtc, cstate, i) {
14835                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14836
14837                 cs->wm.need_postvbl_update = true;
14838                 dev_priv->display.optimize_watermarks(cs);
14839         }
14840
14841         drm_atomic_state_free(state);
14842 fail:
14843         drm_modeset_drop_locks(&ctx);
14844         drm_modeset_acquire_fini(&ctx);
14845 }
14846
14847 void intel_modeset_init(struct drm_device *dev)
14848 {
14849         struct drm_i915_private *dev_priv = to_i915(dev);
14850         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14851         int sprite, ret;
14852         enum pipe pipe;
14853         struct intel_crtc *crtc;
14854
14855         drm_mode_config_init(dev);
14856
14857         dev->mode_config.min_width = 0;
14858         dev->mode_config.min_height = 0;
14859
14860         dev->mode_config.preferred_depth = 24;
14861         dev->mode_config.prefer_shadow = 1;
14862
14863         dev->mode_config.allow_fb_modifiers = true;
14864
14865         dev->mode_config.funcs = &intel_mode_funcs;
14866
14867         intel_init_quirks(dev);
14868
14869         intel_init_pm(dev);
14870
14871         if (INTEL_INFO(dev)->num_pipes == 0)
14872                 return;
14873
14874         /*
14875          * There may be no VBT; and if the BIOS enabled SSC we can
14876          * just keep using it to avoid unnecessary flicker.  Whereas if the
14877          * BIOS isn't using it, don't assume it will work even if the VBT
14878          * indicates as much.
14879          */
14880         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14881                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14882                                             DREF_SSC1_ENABLE);
14883
14884                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14885                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14886                                      bios_lvds_use_ssc ? "en" : "dis",
14887                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14888                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14889                 }
14890         }
14891
14892         if (IS_GEN2(dev)) {
14893                 dev->mode_config.max_width = 2048;
14894                 dev->mode_config.max_height = 2048;
14895         } else if (IS_GEN3(dev)) {
14896                 dev->mode_config.max_width = 4096;
14897                 dev->mode_config.max_height = 4096;
14898         } else {
14899                 dev->mode_config.max_width = 8192;
14900                 dev->mode_config.max_height = 8192;
14901         }
14902
14903         if (IS_845G(dev) || IS_I865G(dev)) {
14904                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14905                 dev->mode_config.cursor_height = 1023;
14906         } else if (IS_GEN2(dev)) {
14907                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14908                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14909         } else {
14910                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14911                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14912         }
14913
14914         dev->mode_config.fb_base = ggtt->mappable_base;
14915
14916         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14917                       INTEL_INFO(dev)->num_pipes,
14918                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14919
14920         for_each_pipe(dev_priv, pipe) {
14921                 intel_crtc_init(dev, pipe);
14922                 for_each_sprite(dev_priv, pipe, sprite) {
14923                         ret = intel_plane_init(dev, pipe, sprite);
14924                         if (ret)
14925                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14926                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14927                 }
14928         }
14929
14930         intel_update_czclk(dev_priv);
14931         intel_update_cdclk(dev);
14932
14933         intel_shared_dpll_init(dev);
14934
14935         if (dev_priv->max_cdclk_freq == 0)
14936                 intel_update_max_cdclk(dev);
14937
14938         /* Just disable it once at startup */
14939         i915_disable_vga(dev);
14940         intel_setup_outputs(dev);
14941
14942         drm_modeset_lock_all(dev);
14943         intel_modeset_setup_hw_state(dev);
14944         drm_modeset_unlock_all(dev);
14945
14946         for_each_intel_crtc(dev, crtc) {
14947                 struct intel_initial_plane_config plane_config = {};
14948
14949                 if (!crtc->active)
14950                         continue;
14951
14952                 /*
14953                  * Note that reserving the BIOS fb up front prevents us
14954                  * from stuffing other stolen allocations like the ring
14955                  * on top.  This prevents some ugliness at boot time, and
14956                  * can even allow for smooth boot transitions if the BIOS
14957                  * fb is large enough for the active pipe configuration.
14958                  */
14959                 dev_priv->display.get_initial_plane_config(crtc,
14960                                                            &plane_config);
14961
14962                 /*
14963                  * If the fb is shared between multiple heads, we'll
14964                  * just get the first one.
14965                  */
14966                 intel_find_initial_plane_obj(crtc, &plane_config);
14967         }
14968
14969         /*
14970          * Make sure hardware watermarks really match the state we read out.
14971          * Note that we need to do this after reconstructing the BIOS fb's
14972          * since the watermark calculation done here will use pstate->fb.
14973          */
14974         sanitize_watermarks(dev);
14975 }
14976
14977 static void intel_enable_pipe_a(struct drm_device *dev)
14978 {
14979         struct intel_connector *connector;
14980         struct drm_connector *crt = NULL;
14981         struct intel_load_detect_pipe load_detect_temp;
14982         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14983
14984         /* We can't just switch on the pipe A, we need to set things up with a
14985          * proper mode and output configuration. As a gross hack, enable pipe A
14986          * by enabling the load detect pipe once. */
14987         for_each_intel_connector(dev, connector) {
14988                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14989                         crt = &connector->base;
14990                         break;
14991                 }
14992         }
14993
14994         if (!crt)
14995                 return;
14996
14997         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14998                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14999 }
15000
15001 static bool
15002 intel_check_plane_mapping(struct intel_crtc *crtc)
15003 {
15004         struct drm_device *dev = crtc->base.dev;
15005         struct drm_i915_private *dev_priv = dev->dev_private;
15006         u32 val;
15007
15008         if (INTEL_INFO(dev)->num_pipes == 1)
15009                 return true;
15010
15011         val = I915_READ(DSPCNTR(!crtc->plane));
15012
15013         if ((val & DISPLAY_PLANE_ENABLE) &&
15014             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15015                 return false;
15016
15017         return true;
15018 }
15019
15020 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15021 {
15022         struct drm_device *dev = crtc->base.dev;
15023         struct intel_encoder *encoder;
15024
15025         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15026                 return true;
15027
15028         return false;
15029 }
15030
15031 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15032 {
15033         struct drm_device *dev = encoder->base.dev;
15034         struct intel_connector *connector;
15035
15036         for_each_connector_on_encoder(dev, &encoder->base, connector)
15037                 return true;
15038
15039         return false;
15040 }
15041
15042 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15043 {
15044         struct drm_device *dev = crtc->base.dev;
15045         struct drm_i915_private *dev_priv = dev->dev_private;
15046         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15047
15048         /* Clear any frame start delays used for debugging left by the BIOS */
15049         if (!transcoder_is_dsi(cpu_transcoder)) {
15050                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15051
15052                 I915_WRITE(reg,
15053                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15054         }
15055
15056         /* restore vblank interrupts to correct state */
15057         drm_crtc_vblank_reset(&crtc->base);
15058         if (crtc->active) {
15059                 struct intel_plane *plane;
15060
15061                 drm_crtc_vblank_on(&crtc->base);
15062
15063                 /* Disable everything but the primary plane */
15064                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15065                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15066                                 continue;
15067
15068                         plane->disable_plane(&plane->base, &crtc->base);
15069                 }
15070         }
15071
15072         /* We need to sanitize the plane -> pipe mapping first because this will
15073          * disable the crtc (and hence change the state) if it is wrong. Note
15074          * that gen4+ has a fixed plane -> pipe mapping.  */
15075         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15076                 bool plane;
15077
15078                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15079                               crtc->base.base.id);
15080
15081                 /* Pipe has the wrong plane attached and the plane is active.
15082                  * Temporarily change the plane mapping and disable everything
15083                  * ...  */
15084                 plane = crtc->plane;
15085                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15086                 crtc->plane = !plane;
15087                 intel_crtc_disable_noatomic(&crtc->base);
15088                 crtc->plane = plane;
15089         }
15090
15091         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15092             crtc->pipe == PIPE_A && !crtc->active) {
15093                 /* BIOS forgot to enable pipe A, this mostly happens after
15094                  * resume. Force-enable the pipe to fix this, the update_dpms
15095                  * call below we restore the pipe to the right state, but leave
15096                  * the required bits on. */
15097                 intel_enable_pipe_a(dev);
15098         }
15099
15100         /* Adjust the state of the output pipe according to whether we
15101          * have active connectors/encoders. */
15102         if (crtc->active && !intel_crtc_has_encoders(crtc))
15103                 intel_crtc_disable_noatomic(&crtc->base);
15104
15105         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15106                 /*
15107                  * We start out with underrun reporting disabled to avoid races.
15108                  * For correct bookkeeping mark this on active crtcs.
15109                  *
15110                  * Also on gmch platforms we dont have any hardware bits to
15111                  * disable the underrun reporting. Which means we need to start
15112                  * out with underrun reporting disabled also on inactive pipes,
15113                  * since otherwise we'll complain about the garbage we read when
15114                  * e.g. coming up after runtime pm.
15115                  *
15116                  * No protection against concurrent access is required - at
15117                  * worst a fifo underrun happens which also sets this to false.
15118                  */
15119                 crtc->cpu_fifo_underrun_disabled = true;
15120                 crtc->pch_fifo_underrun_disabled = true;
15121         }
15122 }
15123
15124 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15125 {
15126         struct intel_connector *connector;
15127         struct drm_device *dev = encoder->base.dev;
15128
15129         /* We need to check both for a crtc link (meaning that the
15130          * encoder is active and trying to read from a pipe) and the
15131          * pipe itself being active. */
15132         bool has_active_crtc = encoder->base.crtc &&
15133                 to_intel_crtc(encoder->base.crtc)->active;
15134
15135         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15136                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15137                               encoder->base.base.id,
15138                               encoder->base.name);
15139
15140                 /* Connector is active, but has no active pipe. This is
15141                  * fallout from our resume register restoring. Disable
15142                  * the encoder manually again. */
15143                 if (encoder->base.crtc) {
15144                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15145                                       encoder->base.base.id,
15146                                       encoder->base.name);
15147                         encoder->disable(encoder);
15148                         if (encoder->post_disable)
15149                                 encoder->post_disable(encoder);
15150                 }
15151                 encoder->base.crtc = NULL;
15152
15153                 /* Inconsistent output/port/pipe state happens presumably due to
15154                  * a bug in one of the get_hw_state functions. Or someplace else
15155                  * in our code, like the register restore mess on resume. Clamp
15156                  * things to off as a safer default. */
15157                 for_each_intel_connector(dev, connector) {
15158                         if (connector->encoder != encoder)
15159                                 continue;
15160                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15161                         connector->base.encoder = NULL;
15162                 }
15163         }
15164         /* Enabled encoders without active connectors will be fixed in
15165          * the crtc fixup. */
15166 }
15167
15168 void i915_redisable_vga_power_on(struct drm_device *dev)
15169 {
15170         struct drm_i915_private *dev_priv = dev->dev_private;
15171         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15172
15173         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15174                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15175                 i915_disable_vga(dev);
15176         }
15177 }
15178
15179 void i915_redisable_vga(struct drm_device *dev)
15180 {
15181         struct drm_i915_private *dev_priv = dev->dev_private;
15182
15183         /* This function can be called both from intel_modeset_setup_hw_state or
15184          * at a very early point in our resume sequence, where the power well
15185          * structures are not yet restored. Since this function is at a very
15186          * paranoid "someone might have enabled VGA while we were not looking"
15187          * level, just check if the power well is enabled instead of trying to
15188          * follow the "don't touch the power well if we don't need it" policy
15189          * the rest of the driver uses. */
15190         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15191                 return;
15192
15193         i915_redisable_vga_power_on(dev);
15194
15195         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15196 }
15197
15198 static bool primary_get_hw_state(struct intel_plane *plane)
15199 {
15200         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15201
15202         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15203 }
15204
15205 /* FIXME read out full plane state for all planes */
15206 static void readout_plane_state(struct intel_crtc *crtc)
15207 {
15208         struct drm_plane *primary = crtc->base.primary;
15209         struct intel_plane_state *plane_state =
15210                 to_intel_plane_state(primary->state);
15211
15212         plane_state->visible = crtc->active &&
15213                 primary_get_hw_state(to_intel_plane(primary));
15214
15215         if (plane_state->visible)
15216                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15217 }
15218
15219 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15220 {
15221         struct drm_i915_private *dev_priv = dev->dev_private;
15222         enum pipe pipe;
15223         struct intel_crtc *crtc;
15224         struct intel_encoder *encoder;
15225         struct intel_connector *connector;
15226         int i;
15227
15228         dev_priv->active_crtcs = 0;
15229
15230         for_each_intel_crtc(dev, crtc) {
15231                 struct intel_crtc_state *crtc_state = crtc->config;
15232                 int pixclk = 0;
15233
15234                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15235                 memset(crtc_state, 0, sizeof(*crtc_state));
15236                 crtc_state->base.crtc = &crtc->base;
15237
15238                 crtc_state->base.active = crtc_state->base.enable =
15239                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15240
15241                 crtc->base.enabled = crtc_state->base.enable;
15242                 crtc->active = crtc_state->base.active;
15243
15244                 if (crtc_state->base.active) {
15245                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15246
15247                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15248                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15249                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15250                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15251                         else
15252                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15253
15254                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15255                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15256                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15257                 }
15258
15259                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15260
15261                 readout_plane_state(crtc);
15262
15263                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15264                               crtc->base.base.id,
15265                               crtc->active ? "enabled" : "disabled");
15266         }
15267
15268         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15269                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15270
15271                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15272                                                   &pll->config.hw_state);
15273                 pll->config.crtc_mask = 0;
15274                 for_each_intel_crtc(dev, crtc) {
15275                         if (crtc->active && crtc->config->shared_dpll == pll)
15276                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15277                 }
15278                 pll->active_mask = pll->config.crtc_mask;
15279
15280                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15281                               pll->name, pll->config.crtc_mask, pll->on);
15282         }
15283
15284         for_each_intel_encoder(dev, encoder) {
15285                 pipe = 0;
15286
15287                 if (encoder->get_hw_state(encoder, &pipe)) {
15288                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15289                         encoder->base.crtc = &crtc->base;
15290                         encoder->get_config(encoder, crtc->config);
15291                 } else {
15292                         encoder->base.crtc = NULL;
15293                 }
15294
15295                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15296                               encoder->base.base.id,
15297                               encoder->base.name,
15298                               encoder->base.crtc ? "enabled" : "disabled",
15299                               pipe_name(pipe));
15300         }
15301
15302         for_each_intel_connector(dev, connector) {
15303                 if (connector->get_hw_state(connector)) {
15304                         connector->base.dpms = DRM_MODE_DPMS_ON;
15305
15306                         encoder = connector->encoder;
15307                         connector->base.encoder = &encoder->base;
15308
15309                         if (encoder->base.crtc &&
15310                             encoder->base.crtc->state->active) {
15311                                 /*
15312                                  * This has to be done during hardware readout
15313                                  * because anything calling .crtc_disable may
15314                                  * rely on the connector_mask being accurate.
15315                                  */
15316                                 encoder->base.crtc->state->connector_mask |=
15317                                         1 << drm_connector_index(&connector->base);
15318                                 encoder->base.crtc->state->encoder_mask |=
15319                                         1 << drm_encoder_index(&encoder->base);
15320                         }
15321
15322                 } else {
15323                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15324                         connector->base.encoder = NULL;
15325                 }
15326                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15327                               connector->base.base.id,
15328                               connector->base.name,
15329                               connector->base.encoder ? "enabled" : "disabled");
15330         }
15331
15332         for_each_intel_crtc(dev, crtc) {
15333                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15334
15335                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15336                 if (crtc->base.state->active) {
15337                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15338                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15339                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15340
15341                         /*
15342                          * The initial mode needs to be set in order to keep
15343                          * the atomic core happy. It wants a valid mode if the
15344                          * crtc's enabled, so we do the above call.
15345                          *
15346                          * At this point some state updated by the connectors
15347                          * in their ->detect() callback has not run yet, so
15348                          * no recalculation can be done yet.
15349                          *
15350                          * Even if we could do a recalculation and modeset
15351                          * right now it would cause a double modeset if
15352                          * fbdev or userspace chooses a different initial mode.
15353                          *
15354                          * If that happens, someone indicated they wanted a
15355                          * mode change, which means it's safe to do a full
15356                          * recalculation.
15357                          */
15358                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15359
15360                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15361                         update_scanline_offset(crtc);
15362                 }
15363
15364                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15365         }
15366 }
15367
15368 /* Scan out the current hw modeset state,
15369  * and sanitizes it to the current state
15370  */
15371 static void
15372 intel_modeset_setup_hw_state(struct drm_device *dev)
15373 {
15374         struct drm_i915_private *dev_priv = dev->dev_private;
15375         enum pipe pipe;
15376         struct intel_crtc *crtc;
15377         struct intel_encoder *encoder;
15378         int i;
15379
15380         intel_modeset_readout_hw_state(dev);
15381
15382         /* HW state is read out, now we need to sanitize this mess. */
15383         for_each_intel_encoder(dev, encoder) {
15384                 intel_sanitize_encoder(encoder);
15385         }
15386
15387         for_each_pipe(dev_priv, pipe) {
15388                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15389                 intel_sanitize_crtc(crtc);
15390                 intel_dump_pipe_config(crtc, crtc->config,
15391                                        "[setup_hw_state]");
15392         }
15393
15394         intel_modeset_update_connector_atomic_state(dev);
15395
15396         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15397                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15398
15399                 if (!pll->on || pll->active_mask)
15400                         continue;
15401
15402                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15403
15404                 pll->funcs.disable(dev_priv, pll);
15405                 pll->on = false;
15406         }
15407
15408         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15409                 vlv_wm_get_hw_state(dev);
15410         else if (IS_GEN9(dev))
15411                 skl_wm_get_hw_state(dev);
15412         else if (HAS_PCH_SPLIT(dev))
15413                 ilk_wm_get_hw_state(dev);
15414
15415         for_each_intel_crtc(dev, crtc) {
15416                 unsigned long put_domains;
15417
15418                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15419                 if (WARN_ON(put_domains))
15420                         modeset_put_power_domains(dev_priv, put_domains);
15421         }
15422         intel_display_set_init_power(dev_priv, false);
15423
15424         intel_fbc_init_pipe_state(dev_priv);
15425 }
15426
15427 void intel_display_resume(struct drm_device *dev)
15428 {
15429         struct drm_i915_private *dev_priv = to_i915(dev);
15430         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15431         struct drm_modeset_acquire_ctx ctx;
15432         int ret;
15433         bool setup = false;
15434
15435         dev_priv->modeset_restore_state = NULL;
15436
15437         /*
15438          * This is a cludge because with real atomic modeset mode_config.mutex
15439          * won't be taken. Unfortunately some probed state like
15440          * audio_codec_enable is still protected by mode_config.mutex, so lock
15441          * it here for now.
15442          */
15443         mutex_lock(&dev->mode_config.mutex);
15444         drm_modeset_acquire_init(&ctx, 0);
15445
15446 retry:
15447         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15448
15449         if (ret == 0 && !setup) {
15450                 setup = true;
15451
15452                 intel_modeset_setup_hw_state(dev);
15453                 i915_redisable_vga(dev);
15454         }
15455
15456         if (ret == 0 && state) {
15457                 struct drm_crtc_state *crtc_state;
15458                 struct drm_crtc *crtc;
15459                 int i;
15460
15461                 state->acquire_ctx = &ctx;
15462
15463                 /* ignore any reset values/BIOS leftovers in the WM registers */
15464                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15465
15466                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15467                         /*
15468                          * Force recalculation even if we restore
15469                          * current state. With fast modeset this may not result
15470                          * in a modeset when the state is compatible.
15471                          */
15472                         crtc_state->mode_changed = true;
15473                 }
15474
15475                 ret = drm_atomic_commit(state);
15476         }
15477
15478         if (ret == -EDEADLK) {
15479                 drm_modeset_backoff(&ctx);
15480                 goto retry;
15481         }
15482
15483         drm_modeset_drop_locks(&ctx);
15484         drm_modeset_acquire_fini(&ctx);
15485         mutex_unlock(&dev->mode_config.mutex);
15486
15487         if (ret) {
15488                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15489                 drm_atomic_state_free(state);
15490         }
15491 }
15492
15493 void intel_modeset_gem_init(struct drm_device *dev)
15494 {
15495         struct drm_i915_private *dev_priv = to_i915(dev);
15496         struct drm_crtc *c;
15497         struct drm_i915_gem_object *obj;
15498         int ret;
15499
15500         intel_init_gt_powersave(dev_priv);
15501
15502         intel_modeset_init_hw(dev);
15503
15504         intel_setup_overlay(dev_priv);
15505
15506         /*
15507          * Make sure any fbs we allocated at startup are properly
15508          * pinned & fenced.  When we do the allocation it's too early
15509          * for this.
15510          */
15511         for_each_crtc(dev, c) {
15512                 obj = intel_fb_obj(c->primary->fb);
15513                 if (obj == NULL)
15514                         continue;
15515
15516                 mutex_lock(&dev->struct_mutex);
15517                 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
15518                                                  c->primary->state->rotation);
15519                 mutex_unlock(&dev->struct_mutex);
15520                 if (ret) {
15521                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15522                                   to_intel_crtc(c)->pipe);
15523                         drm_framebuffer_unreference(c->primary->fb);
15524                         drm_framebuffer_unreference(c->primary->state->fb);
15525                         c->primary->fb = c->primary->state->fb = NULL;
15526                         c->primary->crtc = c->primary->state->crtc = NULL;
15527                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15528                 }
15529         }
15530
15531         intel_backlight_register(dev);
15532 }
15533
15534 void intel_connector_unregister(struct intel_connector *intel_connector)
15535 {
15536         struct drm_connector *connector = &intel_connector->base;
15537
15538         intel_panel_destroy_backlight(connector);
15539         drm_connector_unregister(connector);
15540 }
15541
15542 void intel_modeset_cleanup(struct drm_device *dev)
15543 {
15544         struct drm_i915_private *dev_priv = dev->dev_private;
15545         struct intel_connector *connector;
15546
15547         intel_disable_gt_powersave(dev_priv);
15548
15549         intel_backlight_unregister(dev);
15550
15551         /*
15552          * Interrupts and polling as the first thing to avoid creating havoc.
15553          * Too much stuff here (turning of connectors, ...) would
15554          * experience fancy races otherwise.
15555          */
15556         intel_irq_uninstall(dev_priv);
15557
15558         /*
15559          * Due to the hpd irq storm handling the hotplug work can re-arm the
15560          * poll handlers. Hence disable polling after hpd handling is shut down.
15561          */
15562         drm_kms_helper_poll_fini(dev);
15563
15564         intel_unregister_dsm_handler();
15565
15566         intel_fbc_global_disable(dev_priv);
15567
15568         /* flush any delayed tasks or pending work */
15569         flush_scheduled_work();
15570
15571         /* destroy the backlight and sysfs files before encoders/connectors */
15572         for_each_intel_connector(dev, connector)
15573                 connector->unregister(connector);
15574
15575         drm_mode_config_cleanup(dev);
15576
15577         intel_cleanup_overlay(dev_priv);
15578
15579         intel_cleanup_gt_powersave(dev_priv);
15580
15581         intel_teardown_gmbus(dev);
15582 }
15583
15584 /*
15585  * Return which encoder is currently attached for connector.
15586  */
15587 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15588 {
15589         return &intel_attached_encoder(connector)->base;
15590 }
15591
15592 void intel_connector_attach_encoder(struct intel_connector *connector,
15593                                     struct intel_encoder *encoder)
15594 {
15595         connector->encoder = encoder;
15596         drm_mode_connector_attach_encoder(&connector->base,
15597                                           &encoder->base);
15598 }
15599
15600 /*
15601  * set vga decode state - true == enable VGA decode
15602  */
15603 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15604 {
15605         struct drm_i915_private *dev_priv = dev->dev_private;
15606         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15607         u16 gmch_ctrl;
15608
15609         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15610                 DRM_ERROR("failed to read control word\n");
15611                 return -EIO;
15612         }
15613
15614         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15615                 return 0;
15616
15617         if (state)
15618                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15619         else
15620                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15621
15622         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15623                 DRM_ERROR("failed to write control word\n");
15624                 return -EIO;
15625         }
15626
15627         return 0;
15628 }
15629
15630 struct intel_display_error_state {
15631
15632         u32 power_well_driver;
15633
15634         int num_transcoders;
15635
15636         struct intel_cursor_error_state {
15637                 u32 control;
15638                 u32 position;
15639                 u32 base;
15640                 u32 size;
15641         } cursor[I915_MAX_PIPES];
15642
15643         struct intel_pipe_error_state {
15644                 bool power_domain_on;
15645                 u32 source;
15646                 u32 stat;
15647         } pipe[I915_MAX_PIPES];
15648
15649         struct intel_plane_error_state {
15650                 u32 control;
15651                 u32 stride;
15652                 u32 size;
15653                 u32 pos;
15654                 u32 addr;
15655                 u32 surface;
15656                 u32 tile_offset;
15657         } plane[I915_MAX_PIPES];
15658
15659         struct intel_transcoder_error_state {
15660                 bool power_domain_on;
15661                 enum transcoder cpu_transcoder;
15662
15663                 u32 conf;
15664
15665                 u32 htotal;
15666                 u32 hblank;
15667                 u32 hsync;
15668                 u32 vtotal;
15669                 u32 vblank;
15670                 u32 vsync;
15671         } transcoder[4];
15672 };
15673
15674 struct intel_display_error_state *
15675 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15676 {
15677         struct intel_display_error_state *error;
15678         int transcoders[] = {
15679                 TRANSCODER_A,
15680                 TRANSCODER_B,
15681                 TRANSCODER_C,
15682                 TRANSCODER_EDP,
15683         };
15684         int i;
15685
15686         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15687                 return NULL;
15688
15689         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15690         if (error == NULL)
15691                 return NULL;
15692
15693         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15694                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15695
15696         for_each_pipe(dev_priv, i) {
15697                 error->pipe[i].power_domain_on =
15698                         __intel_display_power_is_enabled(dev_priv,
15699                                                          POWER_DOMAIN_PIPE(i));
15700                 if (!error->pipe[i].power_domain_on)
15701                         continue;
15702
15703                 error->cursor[i].control = I915_READ(CURCNTR(i));
15704                 error->cursor[i].position = I915_READ(CURPOS(i));
15705                 error->cursor[i].base = I915_READ(CURBASE(i));
15706
15707                 error->plane[i].control = I915_READ(DSPCNTR(i));
15708                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15709                 if (INTEL_GEN(dev_priv) <= 3) {
15710                         error->plane[i].size = I915_READ(DSPSIZE(i));
15711                         error->plane[i].pos = I915_READ(DSPPOS(i));
15712                 }
15713                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15714                         error->plane[i].addr = I915_READ(DSPADDR(i));
15715                 if (INTEL_GEN(dev_priv) >= 4) {
15716                         error->plane[i].surface = I915_READ(DSPSURF(i));
15717                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15718                 }
15719
15720                 error->pipe[i].source = I915_READ(PIPESRC(i));
15721
15722                 if (HAS_GMCH_DISPLAY(dev_priv))
15723                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15724         }
15725
15726         /* Note: this does not include DSI transcoders. */
15727         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15728         if (HAS_DDI(dev_priv))
15729                 error->num_transcoders++; /* Account for eDP. */
15730
15731         for (i = 0; i < error->num_transcoders; i++) {
15732                 enum transcoder cpu_transcoder = transcoders[i];
15733
15734                 error->transcoder[i].power_domain_on =
15735                         __intel_display_power_is_enabled(dev_priv,
15736                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15737                 if (!error->transcoder[i].power_domain_on)
15738                         continue;
15739
15740                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15741
15742                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15743                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15744                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15745                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15746                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15747                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15748                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15749         }
15750
15751         return error;
15752 }
15753
15754 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15755
15756 void
15757 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15758                                 struct drm_device *dev,
15759                                 struct intel_display_error_state *error)
15760 {
15761         struct drm_i915_private *dev_priv = dev->dev_private;
15762         int i;
15763
15764         if (!error)
15765                 return;
15766
15767         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15768         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15769                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15770                            error->power_well_driver);
15771         for_each_pipe(dev_priv, i) {
15772                 err_printf(m, "Pipe [%d]:\n", i);
15773                 err_printf(m, "  Power: %s\n",
15774                            onoff(error->pipe[i].power_domain_on));
15775                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15776                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15777
15778                 err_printf(m, "Plane [%d]:\n", i);
15779                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15780                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15781                 if (INTEL_INFO(dev)->gen <= 3) {
15782                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15783                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15784                 }
15785                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15786                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15787                 if (INTEL_INFO(dev)->gen >= 4) {
15788                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15789                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15790                 }
15791
15792                 err_printf(m, "Cursor [%d]:\n", i);
15793                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15794                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15795                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15796         }
15797
15798         for (i = 0; i < error->num_transcoders; i++) {
15799                 err_printf(m, "CPU transcoder: %s\n",
15800                            transcoder_name(error->transcoder[i].cpu_transcoder));
15801                 err_printf(m, "  Power: %s\n",
15802                            onoff(error->transcoder[i].power_domain_on));
15803                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15804                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15805                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15806                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15807                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15808                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15809                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15810         }
15811 }