drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "intel_dsi.h"
  40 #include "i915_trace.h"
  41 #include <drm/drm_atomic.h>
  42 #include <drm/drm_atomic_helper.h>
  43 #include <drm/drm_dp_helper.h>
  44 #include <drm/drm_crtc_helper.h>
  45 #include <drm/drm_plane_helper.h>
  46 #include <drm/drm_rect.h>
  47 #include <linux/dma_remapping.h>
  48 #include <linux/reservation.h>
  49 #include <linux/dma-buf.h>
  50
  51 /* Primary plane formats for gen <= 3 */
  52 static const uint32_t i8xx_primary_formats[] = {
  53         DRM_FORMAT_C8,
  54         DRM_FORMAT_RGB565,
  55         DRM_FORMAT_XRGB1555,
  56         DRM_FORMAT_XRGB8888,
  57 };
  58
  59 /* Primary plane formats for gen >= 4 */
  60 static const uint32_t i965_primary_formats[] = {
  61         DRM_FORMAT_C8,
  62         DRM_FORMAT_RGB565,
  63         DRM_FORMAT_XRGB8888,
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_XRGB2101010,
  66         DRM_FORMAT_XBGR2101010,
  67 };
  68
  69 static const uint32_t skl_primary_formats[] = {
  70         DRM_FORMAT_C8,
  71         DRM_FORMAT_RGB565,
  72         DRM_FORMAT_XRGB8888,
  73         DRM_FORMAT_XBGR8888,
  74         DRM_FORMAT_ARGB8888,
  75         DRM_FORMAT_ABGR8888,
  76         DRM_FORMAT_XRGB2101010,
  77         DRM_FORMAT_XBGR2101010,
  78         DRM_FORMAT_YUYV,
  79         DRM_FORMAT_YVYU,
  80         DRM_FORMAT_UYVY,
  81         DRM_FORMAT_VYUY,
  82 };
  83
  84 /* Cursor formats */
  85 static const uint32_t intel_cursor_formats[] = {
  86         DRM_FORMAT_ARGB8888,
  87 };
  88
  89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  90                                 struct intel_crtc_state *pipe_config);
  91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  92                                    struct intel_crtc_state *pipe_config);
  93
  94 static int intel_framebuffer_init(struct drm_device *dev,
  95                                   struct intel_framebuffer *ifb,
  96                                   struct drm_mode_fb_cmd2 *mode_cmd,
  97                                   struct drm_i915_gem_object *obj);
  98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
  99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 102                                          struct intel_link_m_n *m_n,
 103                                          struct intel_link_m_n *m2_n2);
 104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 107 static void vlv_prepare_pll(struct intel_crtc *crtc,
 108                             const struct intel_crtc_state *pipe_config);
 109 static void chv_prepare_pll(struct intel_crtc *crtc,
 110                             const struct intel_crtc_state *pipe_config);
 111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 112         struct intel_crtc_state *crtc_state);
 113 static void skylake_pfit_enable(struct intel_crtc *crtc);
 114 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 115 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 116 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 117 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 118 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
 119 static void intel_modeset_verify_crtc(struct drm_crtc *crtc,
 120                                       struct drm_crtc_state *old_state,
 121                                       struct drm_crtc_state *new_state);
 122
 123 struct intel_limit {
 124         struct {
 125                 int min, max;
 126         } dot, vco, n, m, m1, m2, p, p1;
 127
 128         struct {
 129                 int dot_limit;
 130                 int p2_slow, p2_fast;
 131         } p2;
 132 };
 133
 134 /* returns HPLL frequency in kHz */
 135 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
 136 {
 137         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 138
 139         /* Obtain SKU information */
 140         mutex_lock(&dev_priv->sb_lock);
 141         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 142                 CCK_FUSE_HPLL_FREQ_MASK;
 143         mutex_unlock(&dev_priv->sb_lock);
 144
 145         return vco_freq[hpll_freq] * 1000;
 146 }
 147
 148 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 149                       const char *name, u32 reg, int ref_freq)
 150 {
 151         u32 val;
 152         int divider;
 153
 154         mutex_lock(&dev_priv->sb_lock);
 155         val = vlv_cck_read(dev_priv, reg);
 156         mutex_unlock(&dev_priv->sb_lock);
 157
 158         divider = val & CCK_FREQUENCY_VALUES;
 159
 160         WARN((val & CCK_FREQUENCY_STATUS) !=
 161              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 162              "%s change in progress\n", name);
 163
 164         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 165 }
 166
 167 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 168                                   const char *name, u32 reg)
 169 {
 170         if (dev_priv->hpll_freq == 0)
 171                 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 172
 173         return vlv_get_cck_clock(dev_priv, name, reg,
 174                                  dev_priv->hpll_freq);
 175 }
 176
 177 static int
 178 intel_pch_rawclk(struct drm_i915_private *dev_priv)
 179 {
 180         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
 181 }
 182
 183 static int
 184 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
 185 {
 186         /* RAWCLK_FREQ_VLV register updated from power well code */
 187         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
 188                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
 189 }
 190
 191 static int
 192 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
 193 {
 194         uint32_t clkcfg;
 195
 196         /* hrawclock is 1/4 the FSB frequency */
 197         clkcfg = I915_READ(CLKCFG);
 198         switch (clkcfg & CLKCFG_FSB_MASK) {
 199         case CLKCFG_FSB_400:
 200                 return 100000;
 201         case CLKCFG_FSB_533:
 202                 return 133333;
 203         case CLKCFG_FSB_667:
 204                 return 166667;
 205         case CLKCFG_FSB_800:
 206                 return 200000;
 207         case CLKCFG_FSB_1067:
 208                 return 266667;
 209         case CLKCFG_FSB_1333:
 210                 return 333333;
 211         /* these two are just a guess; one of them might be right */
 212         case CLKCFG_FSB_1600:
 213         case CLKCFG_FSB_1600_ALT:
 214                 return 400000;
 215         default:
 216                 return 133333;
 217         }
 218 }
 219
 220 void intel_update_rawclk(struct drm_i915_private *dev_priv)
 221 {
 222         if (HAS_PCH_SPLIT(dev_priv))
 223                 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
 224         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 225                 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
 226         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
 227                 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
 228         else
 229                 return; /* no rawclk on other platforms, or no need to know it */
 230
 231         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
 232 }
 233
 234 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 235 {
 236         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 237                 return;
 238
 239         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 240                                                       CCK_CZ_CLOCK_CONTROL);
 241
 242         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 243 }
 244
 245 static inline u32 /* units of 100MHz */
 246 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 247                     const struct intel_crtc_state *pipe_config)
 248 {
 249         if (HAS_DDI(dev_priv))
 250                 return pipe_config->port_clock; /* SPLL */
 251         else if (IS_GEN5(dev_priv))
 252                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 253         else
 254                 return 270000;
 255 }
 256
 257 static const struct intel_limit intel_limits_i8xx_dac = {
 258         .dot = { .min = 25000, .max = 350000 },
 259         .vco = { .min = 908000, .max = 1512000 },
 260         .n = { .min = 2, .max = 16 },
 261         .m = { .min = 96, .max = 140 },
 262         .m1 = { .min = 18, .max = 26 },
 263         .m2 = { .min = 6, .max = 16 },
 264         .p = { .min = 4, .max = 128 },
 265         .p1 = { .min = 2, .max = 33 },
 266         .p2 = { .dot_limit = 165000,
 267                 .p2_slow = 4, .p2_fast = 2 },
 268 };
 269
 270 static const struct intel_limit intel_limits_i8xx_dvo = {
 271         .dot = { .min = 25000, .max = 350000 },
 272         .vco = { .min = 908000, .max = 1512000 },
 273         .n = { .min = 2, .max = 16 },
 274         .m = { .min = 96, .max = 140 },
 275         .m1 = { .min = 18, .max = 26 },
 276         .m2 = { .min = 6, .max = 16 },
 277         .p = { .min = 4, .max = 128 },
 278         .p1 = { .min = 2, .max = 33 },
 279         .p2 = { .dot_limit = 165000,
 280                 .p2_slow = 4, .p2_fast = 4 },
 281 };
 282
 283 static const struct intel_limit intel_limits_i8xx_lvds = {
 284         .dot = { .min = 25000, .max = 350000 },
 285         .vco = { .min = 908000, .max = 1512000 },
 286         .n = { .min = 2, .max = 16 },
 287         .m = { .min = 96, .max = 140 },
 288         .m1 = { .min = 18, .max = 26 },
 289         .m2 = { .min = 6, .max = 16 },
 290         .p = { .min = 4, .max = 128 },
 291         .p1 = { .min = 1, .max = 6 },
 292         .p2 = { .dot_limit = 165000,
 293                 .p2_slow = 14, .p2_fast = 7 },
 294 };
 295
 296 static const struct intel_limit intel_limits_i9xx_sdvo = {
 297         .dot = { .min = 20000, .max = 400000 },
 298         .vco = { .min = 1400000, .max = 2800000 },
 299         .n = { .min = 1, .max = 6 },
 300         .m = { .min = 70, .max = 120 },
 301         .m1 = { .min = 8, .max = 18 },
 302         .m2 = { .min = 3, .max = 7 },
 303         .p = { .min = 5, .max = 80 },
 304         .p1 = { .min = 1, .max = 8 },
 305         .p2 = { .dot_limit = 200000,
 306                 .p2_slow = 10, .p2_fast = 5 },
 307 };
 308
 309 static const struct intel_limit intel_limits_i9xx_lvds = {
 310         .dot = { .min = 20000, .max = 400000 },
 311         .vco = { .min = 1400000, .max = 2800000 },
 312         .n = { .min = 1, .max = 6 },
 313         .m = { .min = 70, .max = 120 },
 314         .m1 = { .min = 8, .max = 18 },
 315         .m2 = { .min = 3, .max = 7 },
 316         .p = { .min = 7, .max = 98 },
 317         .p1 = { .min = 1, .max = 8 },
 318         .p2 = { .dot_limit = 112000,
 319                 .p2_slow = 14, .p2_fast = 7 },
 320 };
 321
 322
 323 static const struct intel_limit intel_limits_g4x_sdvo = {
 324         .dot = { .min = 25000, .max = 270000 },
 325         .vco = { .min = 1750000, .max = 3500000},
 326         .n = { .min = 1, .max = 4 },
 327         .m = { .min = 104, .max = 138 },
 328         .m1 = { .min = 17, .max = 23 },
 329         .m2 = { .min = 5, .max = 11 },
 330         .p = { .min = 10, .max = 30 },
 331         .p1 = { .min = 1, .max = 3},
 332         .p2 = { .dot_limit = 270000,
 333                 .p2_slow = 10,
 334                 .p2_fast = 10
 335         },
 336 };
 337
 338 static const struct intel_limit intel_limits_g4x_hdmi = {
 339         .dot = { .min = 22000, .max = 400000 },
 340         .vco = { .min = 1750000, .max = 3500000},
 341         .n = { .min = 1, .max = 4 },
 342         .m = { .min = 104, .max = 138 },
 343         .m1 = { .min = 16, .max = 23 },
 344         .m2 = { .min = 5, .max = 11 },
 345         .p = { .min = 5, .max = 80 },
 346         .p1 = { .min = 1, .max = 8},
 347         .p2 = { .dot_limit = 165000,
 348                 .p2_slow = 10, .p2_fast = 5 },
 349 };
 350
 351 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 352         .dot = { .min = 20000, .max = 115000 },
 353         .vco = { .min = 1750000, .max = 3500000 },
 354         .n = { .min = 1, .max = 3 },
 355         .m = { .min = 104, .max = 138 },
 356         .m1 = { .min = 17, .max = 23 },
 357         .m2 = { .min = 5, .max = 11 },
 358         .p = { .min = 28, .max = 112 },
 359         .p1 = { .min = 2, .max = 8 },
 360         .p2 = { .dot_limit = 0,
 361                 .p2_slow = 14, .p2_fast = 14
 362         },
 363 };
 364
 365 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 366         .dot = { .min = 80000, .max = 224000 },
 367         .vco = { .min = 1750000, .max = 3500000 },
 368         .n = { .min = 1, .max = 3 },
 369         .m = { .min = 104, .max = 138 },
 370         .m1 = { .min = 17, .max = 23 },
 371         .m2 = { .min = 5, .max = 11 },
 372         .p = { .min = 14, .max = 42 },
 373         .p1 = { .min = 2, .max = 6 },
 374         .p2 = { .dot_limit = 0,
 375                 .p2_slow = 7, .p2_fast = 7
 376         },
 377 };
 378
 379 static const struct intel_limit intel_limits_pineview_sdvo = {
 380         .dot = { .min = 20000, .max = 400000},
 381         .vco = { .min = 1700000, .max = 3500000 },
 382         /* Pineview's Ncounter is a ring counter */
 383         .n = { .min = 3, .max = 6 },
 384         .m = { .min = 2, .max = 256 },
 385         /* Pineview only has one combined m divider, which we treat as m2. */
 386         .m1 = { .min = 0, .max = 0 },
 387         .m2 = { .min = 0, .max = 254 },
 388         .p = { .min = 5, .max = 80 },
 389         .p1 = { .min = 1, .max = 8 },
 390         .p2 = { .dot_limit = 200000,
 391                 .p2_slow = 10, .p2_fast = 5 },
 392 };
 393
 394 static const struct intel_limit intel_limits_pineview_lvds = {
 395         .dot = { .min = 20000, .max = 400000 },
 396         .vco = { .min = 1700000, .max = 3500000 },
 397         .n = { .min = 3, .max = 6 },
 398         .m = { .min = 2, .max = 256 },
 399         .m1 = { .min = 0, .max = 0 },
 400         .m2 = { .min = 0, .max = 254 },
 401         .p = { .min = 7, .max = 112 },
 402         .p1 = { .min = 1, .max = 8 },
 403         .p2 = { .dot_limit = 112000,
 404                 .p2_slow = 14, .p2_fast = 14 },
 405 };
 406
 407 /* Ironlake / Sandybridge
 408  *
 409  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 410  * the range value for them is (actual_value - 2).
 411  */
 412 static const struct intel_limit intel_limits_ironlake_dac = {
 413         .dot = { .min = 25000, .max = 350000 },
 414         .vco = { .min = 1760000, .max = 3510000 },
 415         .n = { .min = 1, .max = 5 },
 416         .m = { .min = 79, .max = 127 },
 417         .m1 = { .min = 12, .max = 22 },
 418         .m2 = { .min = 5, .max = 9 },
 419         .p = { .min = 5, .max = 80 },
 420         .p1 = { .min = 1, .max = 8 },
 421         .p2 = { .dot_limit = 225000,
 422                 .p2_slow = 10, .p2_fast = 5 },
 423 };
 424
 425 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 426         .dot = { .min = 25000, .max = 350000 },
 427         .vco = { .min = 1760000, .max = 3510000 },
 428         .n = { .min = 1, .max = 3 },
 429         .m = { .min = 79, .max = 118 },
 430         .m1 = { .min = 12, .max = 22 },
 431         .m2 = { .min = 5, .max = 9 },
 432         .p = { .min = 28, .max = 112 },
 433         .p1 = { .min = 2, .max = 8 },
 434         .p2 = { .dot_limit = 225000,
 435                 .p2_slow = 14, .p2_fast = 14 },
 436 };
 437
 438 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 439         .dot = { .min = 25000, .max = 350000 },
 440         .vco = { .min = 1760000, .max = 3510000 },
 441         .n = { .min = 1, .max = 3 },
 442         .m = { .min = 79, .max = 127 },
 443         .m1 = { .min = 12, .max = 22 },
 444         .m2 = { .min = 5, .max = 9 },
 445         .p = { .min = 14, .max = 56 },
 446         .p1 = { .min = 2, .max = 8 },
 447         .p2 = { .dot_limit = 225000,
 448                 .p2_slow = 7, .p2_fast = 7 },
 449 };
 450
 451 /* LVDS 100mhz refclk limits. */
 452 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 453         .dot = { .min = 25000, .max = 350000 },
 454         .vco = { .min = 1760000, .max = 3510000 },
 455         .n = { .min = 1, .max = 2 },
 456         .m = { .min = 79, .max = 126 },
 457         .m1 = { .min = 12, .max = 22 },
 458         .m2 = { .min = 5, .max = 9 },
 459         .p = { .min = 28, .max = 112 },
 460         .p1 = { .min = 2, .max = 8 },
 461         .p2 = { .dot_limit = 225000,
 462                 .p2_slow = 14, .p2_fast = 14 },
 463 };
 464
 465 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 466         .dot = { .min = 25000, .max = 350000 },
 467         .vco = { .min = 1760000, .max = 3510000 },
 468         .n = { .min = 1, .max = 3 },
 469         .m = { .min = 79, .max = 126 },
 470         .m1 = { .min = 12, .max = 22 },
 471         .m2 = { .min = 5, .max = 9 },
 472         .p = { .min = 14, .max = 42 },
 473         .p1 = { .min = 2, .max = 6 },
 474         .p2 = { .dot_limit = 225000,
 475                 .p2_slow = 7, .p2_fast = 7 },
 476 };
 477
 478 static const struct intel_limit intel_limits_vlv = {
 479          /*
 480           * These are the data rate limits (measured in fast clocks)
 481           * since those are the strictest limits we have. The fast
 482           * clock and actual rate limits are more relaxed, so checking
 483           * them would make no difference.
 484           */
 485         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 486         .vco = { .min = 4000000, .max = 6000000 },
 487         .n = { .min = 1, .max = 7 },
 488         .m1 = { .min = 2, .max = 3 },
 489         .m2 = { .min = 11, .max = 156 },
 490         .p1 = { .min = 2, .max = 3 },
 491         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 492 };
 493
 494 static const struct intel_limit intel_limits_chv = {
 495         /*
 496          * These are the data rate limits (measured in fast clocks)
 497          * since those are the strictest limits we have.  The fast
 498          * clock and actual rate limits are more relaxed, so checking
 499          * them would make no difference.
 500          */
 501         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 502         .vco = { .min = 4800000, .max = 6480000 },
 503         .n = { .min = 1, .max = 1 },
 504         .m1 = { .min = 2, .max = 2 },
 505         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 506         .p1 = { .min = 2, .max = 4 },
 507         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 508 };
 509
 510 static const struct intel_limit intel_limits_bxt = {
 511         /* FIXME: find real dot limits */
 512         .dot = { .min = 0, .max = INT_MAX },
 513         .vco = { .min = 4800000, .max = 6700000 },
 514         .n = { .min = 1, .max = 1 },
 515         .m1 = { .min = 2, .max = 2 },
 516         /* FIXME: find real m2 limits */
 517         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 518         .p1 = { .min = 2, .max = 4 },
 519         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 520 };
 521
 522 static bool
 523 needs_modeset(struct drm_crtc_state *state)
 524 {
 525         return drm_atomic_crtc_needs_modeset(state);
 526 }
 527
 528 /**
 529  * Returns whether any output on the specified pipe is of the specified type
 530  */
 531 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
 532 {
 533         struct drm_device *dev = crtc->base.dev;
 534         struct intel_encoder *encoder;
 535
 536         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 537                 if (encoder->type == type)
 538                         return true;
 539
 540         return false;
 541 }
 542
 543 /**
 544  * Returns whether any output on the specified pipe will have the specified
 545  * type after a staged modeset is complete, i.e., the same as
 546  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
 547  * encoder->crtc.
 548  */
 549 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 550                                       int type)
 551 {
 552         struct drm_atomic_state *state = crtc_state->base.state;
 553         struct drm_connector *connector;
 554         struct drm_connector_state *connector_state;
 555         struct intel_encoder *encoder;
 556         int i, num_connectors = 0;
 557
 558         for_each_connector_in_state(state, connector, connector_state, i) {
 559                 if (connector_state->crtc != crtc_state->base.crtc)
 560                         continue;
 561
 562                 num_connectors++;
 563
 564                 encoder = to_intel_encoder(connector_state->best_encoder);
 565                 if (encoder->type == type)
 566                         return true;
 567         }
 568
 569         WARN_ON(num_connectors == 0);
 570
 571         return false;
 572 }
 573
 574 /*
 575  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 576  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 577  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 578  * The helpers' return value is the rate of the clock that is fed to the
 579  * display engine's pipe which can be the above fast dot clock rate or a
 580  * divided-down version of it.
 581  */
 582 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 583 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 584 {
 585         clock->m = clock->m2 + 2;
 586         clock->p = clock->p1 * clock->p2;
 587         if (WARN_ON(clock->n == 0 || clock->p == 0))
 588                 return 0;
 589         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 590         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 591
 592         return clock->dot;
 593 }
 594
 595 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 596 {
 597         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 598 }
 599
 600 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 601 {
 602         clock->m = i9xx_dpll_compute_m(clock);
 603         clock->p = clock->p1 * clock->p2;
 604         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 605                 return 0;
 606         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 607         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 608
 609         return clock->dot;
 610 }
 611
 612 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 613 {
 614         clock->m = clock->m1 * clock->m2;
 615         clock->p = clock->p1 * clock->p2;
 616         if (WARN_ON(clock->n == 0 || clock->p == 0))
 617                 return 0;
 618         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 619         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 620
 621         return clock->dot / 5;
 622 }
 623
 624 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 625 {
 626         clock->m = clock->m1 * clock->m2;
 627         clock->p = clock->p1 * clock->p2;
 628         if (WARN_ON(clock->n == 0 || clock->p == 0))
 629                 return 0;
 630         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 631                         clock->n << 22);
 632         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 633
 634         return clock->dot / 5;
 635 }
 636
 637 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 638 /**
 639  * Returns whether the given set of divisors are valid for a given refclk with
 640  * the given connectors.
 641  */
 642
 643 static bool intel_PLL_is_valid(struct drm_device *dev,
 644                                const struct intel_limit *limit,
 645                                const struct dpll *clock)
 646 {
 647         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 648                 INTELPllInvalid("n out of range\n");
 649         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 650                 INTELPllInvalid("p1 out of range\n");
 651         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 652                 INTELPllInvalid("m2 out of range\n");
 653         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 654                 INTELPllInvalid("m1 out of range\n");
 655
 656         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
 657             !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
 658                 if (clock->m1 <= clock->m2)
 659                         INTELPllInvalid("m1 <= m2\n");
 660
 661         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
 662                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 663                         INTELPllInvalid("p out of range\n");
 664                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 665                         INTELPllInvalid("m out of range\n");
 666         }
 667
 668         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 669                 INTELPllInvalid("vco out of range\n");
 670         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 671          * connector, etc., rather than just a single range.
 672          */
 673         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 674                 INTELPllInvalid("dot out of range\n");
 675
 676         return true;
 677 }
 678
 679 static int
 680 i9xx_select_p2_div(const struct intel_limit *limit,
 681                    const struct intel_crtc_state *crtc_state,
 682                    int target)
 683 {
 684         struct drm_device *dev = crtc_state->base.crtc->dev;
 685
 686         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 687                 /*
 688                  * For LVDS just rely on its current settings for dual-channel.
 689                  * We haven't figured out how to reliably set up different
 690                  * single/dual channel state, if we even can.
 691                  */
 692                 if (intel_is_dual_link_lvds(dev))
 693                         return limit->p2.p2_fast;
 694                 else
 695                         return limit->p2.p2_slow;
 696         } else {
 697                 if (target < limit->p2.dot_limit)
 698                         return limit->p2.p2_slow;
 699                 else
 700                         return limit->p2.p2_fast;
 701         }
 702 }
 703
 704 /*
 705  * Returns a set of divisors for the desired target clock with the given
 706  * refclk, or FALSE.  The returned values represent the clock equation:
 707  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 708  *
 709  * Target and reference clocks are specified in kHz.
 710  *
 711  * If match_clock is provided, then best_clock P divider must match the P
 712  * divider from @match_clock used for LVDS downclocking.
 713  */
 714 static bool
 715 i9xx_find_best_dpll(const struct intel_limit *limit,
 716                     struct intel_crtc_state *crtc_state,
 717                     int target, int refclk, struct dpll *match_clock,
 718                     struct dpll *best_clock)
 719 {
 720         struct drm_device *dev = crtc_state->base.crtc->dev;
 721         struct dpll clock;
 722         int err = target;
 723
 724         memset(best_clock, 0, sizeof(*best_clock));
 725
 726         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 727
 728         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 729              clock.m1++) {
 730                 for (clock.m2 = limit->m2.min;
 731                      clock.m2 <= limit->m2.max; clock.m2++) {
 732                         if (clock.m2 >= clock.m1)
 733                                 break;
 734                         for (clock.n = limit->n.min;
 735                              clock.n <= limit->n.max; clock.n++) {
 736                                 for (clock.p1 = limit->p1.min;
 737                                         clock.p1 <= limit->p1.max; clock.p1++) {
 738                                         int this_err;
 739
 740                                         i9xx_calc_dpll_params(refclk, &clock);
 741                                         if (!intel_PLL_is_valid(dev, limit,
 742                                                                 &clock))
 743                                                 continue;
 744                                         if (match_clock &&
 745                                             clock.p != match_clock->p)
 746                                                 continue;
 747
 748                                         this_err = abs(clock.dot - target);
 749                                         if (this_err < err) {
 750                                                 *best_clock = clock;
 751                                                 err = this_err;
 752                                         }
 753                                 }
 754                         }
 755                 }
 756         }
 757
 758         return (err != target);
 759 }
 760
 761 /*
 762  * Returns a set of divisors for the desired target clock with the given
 763  * refclk, or FALSE.  The returned values represent the clock equation:
 764  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 765  *
 766  * Target and reference clocks are specified in kHz.
 767  *
 768  * If match_clock is provided, then best_clock P divider must match the P
 769  * divider from @match_clock used for LVDS downclocking.
 770  */
 771 static bool
 772 pnv_find_best_dpll(const struct intel_limit *limit,
 773                    struct intel_crtc_state *crtc_state,
 774                    int target, int refclk, struct dpll *match_clock,
 775                    struct dpll *best_clock)
 776 {
 777         struct drm_device *dev = crtc_state->base.crtc->dev;
 778         struct dpll clock;
 779         int err = target;
 780
 781         memset(best_clock, 0, sizeof(*best_clock));
 782
 783         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 784
 785         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 786              clock.m1++) {
 787                 for (clock.m2 = limit->m2.min;
 788                      clock.m2 <= limit->m2.max; clock.m2++) {
 789                         for (clock.n = limit->n.min;
 790                              clock.n <= limit->n.max; clock.n++) {
 791                                 for (clock.p1 = limit->p1.min;
 792                                         clock.p1 <= limit->p1.max; clock.p1++) {
 793                                         int this_err;
 794
 795                                         pnv_calc_dpll_params(refclk, &clock);
 796                                         if (!intel_PLL_is_valid(dev, limit,
 797                                                                 &clock))
 798                                                 continue;
 799                                         if (match_clock &&
 800                                             clock.p != match_clock->p)
 801                                                 continue;
 802
 803                                         this_err = abs(clock.dot - target);
 804                                         if (this_err < err) {
 805                                                 *best_clock = clock;
 806                                                 err = this_err;
 807                                         }
 808                                 }
 809                         }
 810                 }
 811         }
 812
 813         return (err != target);
 814 }
 815
 816 /*
 817  * Returns a set of divisors for the desired target clock with the given
 818  * refclk, or FALSE.  The returned values represent the clock equation:
 819  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 820  *
 821  * Target and reference clocks are specified in kHz.
 822  *
 823  * If match_clock is provided, then best_clock P divider must match the P
 824  * divider from @match_clock used for LVDS downclocking.
 825  */
 826 static bool
 827 g4x_find_best_dpll(const struct intel_limit *limit,
 828                    struct intel_crtc_state *crtc_state,
 829                    int target, int refclk, struct dpll *match_clock,
 830                    struct dpll *best_clock)
 831 {
 832         struct drm_device *dev = crtc_state->base.crtc->dev;
 833         struct dpll clock;
 834         int max_n;
 835         bool found = false;
 836         /* approximately equals target * 0.00585 */
 837         int err_most = (target >> 8) + (target >> 9);
 838
 839         memset(best_clock, 0, sizeof(*best_clock));
 840
 841         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 842
 843         max_n = limit->n.max;
 844         /* based on hardware requirement, prefer smaller n to precision */
 845         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 846                 /* based on hardware requirement, prefere larger m1,m2 */
 847                 for (clock.m1 = limit->m1.max;
 848                      clock.m1 >= limit->m1.min; clock.m1--) {
 849                         for (clock.m2 = limit->m2.max;
 850                              clock.m2 >= limit->m2.min; clock.m2--) {
 851                                 for (clock.p1 = limit->p1.max;
 852                                      clock.p1 >= limit->p1.min; clock.p1--) {
 853                                         int this_err;
 854
 855                                         i9xx_calc_dpll_params(refclk, &clock);
 856                                         if (!intel_PLL_is_valid(dev, limit,
 857                                                                 &clock))
 858                                                 continue;
 859
 860                                         this_err = abs(clock.dot - target);
 861                                         if (this_err < err_most) {
 862                                                 *best_clock = clock;
 863                                                 err_most = this_err;
 864                                                 max_n = clock.n;
 865                                                 found = true;
 866                                         }
 867                                 }
 868                         }
 869                 }
 870         }
 871         return found;
 872 }
 873
 874 /*
 875  * Check if the calculated PLL configuration is more optimal compared to the
 876  * best configuration and error found so far. Return the calculated error.
 877  */
 878 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 879                                const struct dpll *calculated_clock,
 880                                const struct dpll *best_clock,
 881                                unsigned int best_error_ppm,
 882                                unsigned int *error_ppm)
 883 {
 884         /*
 885          * For CHV ignore the error and consider only the P value.
 886          * Prefer a bigger P value based on HW requirements.
 887          */
 888         if (IS_CHERRYVIEW(dev)) {
 889                 *error_ppm = 0;
 890
 891                 return calculated_clock->p > best_clock->p;
 892         }
 893
 894         if (WARN_ON_ONCE(!target_freq))
 895                 return false;
 896
 897         *error_ppm = div_u64(1000000ULL *
 898                                 abs(target_freq - calculated_clock->dot),
 899                              target_freq);
 900         /*
 901          * Prefer a better P value over a better (smaller) error if the error
 902          * is small. Ensure this preference for future configurations too by
 903          * setting the error to 0.
 904          */
 905         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 906                 *error_ppm = 0;
 907
 908                 return true;
 909         }
 910
 911         return *error_ppm + 10 < best_error_ppm;
 912 }
 913
 914 /*
 915  * Returns a set of divisors for the desired target clock with the given
 916  * refclk, or FALSE.  The returned values represent the clock equation:
 917  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 918  */
 919 static bool
 920 vlv_find_best_dpll(const struct intel_limit *limit,
 921                    struct intel_crtc_state *crtc_state,
 922                    int target, int refclk, struct dpll *match_clock,
 923                    struct dpll *best_clock)
 924 {
 925         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 926         struct drm_device *dev = crtc->base.dev;
 927         struct dpll clock;
 928         unsigned int bestppm = 1000000;
 929         /* min update 19.2 MHz */
 930         int max_n = min(limit->n.max, refclk / 19200);
 931         bool found = false;
 932
 933         target *= 5; /* fast clock */
 934
 935         memset(best_clock, 0, sizeof(*best_clock));
 936
 937         /* based on hardware requirement, prefer smaller n to precision */
 938         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 939                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 940                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 941                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 942                                 clock.p = clock.p1 * clock.p2;
 943                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 944                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 945                                         unsigned int ppm;
 946
 947                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 948                                                                      refclk * clock.m1);
 949
 950                                         vlv_calc_dpll_params(refclk, &clock);
 951
 952                                         if (!intel_PLL_is_valid(dev, limit,
 953                                                                 &clock))
 954                                                 continue;
 955
 956                                         if (!vlv_PLL_is_optimal(dev, target,
 957                                                                 &clock,
 958                                                                 best_clock,
 959                                                                 bestppm, &ppm))
 960                                                 continue;
 961
 962                                         *best_clock = clock;
 963                                         bestppm = ppm;
 964                                         found = true;
 965                                 }
 966                         }
 967                 }
 968         }
 969
 970         return found;
 971 }
 972
 973 /*
 974  * Returns a set of divisors for the desired target clock with the given
 975  * refclk, or FALSE.  The returned values represent the clock equation:
 976  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 977  */
 978 static bool
 979 chv_find_best_dpll(const struct intel_limit *limit,
 980                    struct intel_crtc_state *crtc_state,
 981                    int target, int refclk, struct dpll *match_clock,
 982                    struct dpll *best_clock)
 983 {
 984         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 985         struct drm_device *dev = crtc->base.dev;
 986         unsigned int best_error_ppm;
 987         struct dpll clock;
 988         uint64_t m2;
 989         int found = false;
 990
 991         memset(best_clock, 0, sizeof(*best_clock));
 992         best_error_ppm = 1000000;
 993
 994         /*
 995          * Based on hardware doc, the n always set to 1, and m1 always
 996          * set to 2.  If requires to support 200Mhz refclk, we need to
 997          * revisit this because n may not 1 anymore.
 998          */
 999         clock.n = 1, clock.m1 = 2;
1000         target *= 5;    /* fast clock */
1001
1002         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1003                 for (clock.p2 = limit->p2.p2_fast;
1004                                 clock.p2 >= limit->p2.p2_slow;
1005                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1006                         unsigned int error_ppm;
1007
1008                         clock.p = clock.p1 * clock.p2;
1009
1010                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1011                                         clock.n) << 22, refclk * clock.m1);
1012
1013                         if (m2 > INT_MAX/clock.m1)
1014                                 continue;
1015
1016                         clock.m2 = m2;
1017
1018                         chv_calc_dpll_params(refclk, &clock);
1019
1020                         if (!intel_PLL_is_valid(dev, limit, &clock))
1021                                 continue;
1022
1023                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1024                                                 best_error_ppm, &error_ppm))
1025                                 continue;
1026
1027                         *best_clock = clock;
1028                         best_error_ppm = error_ppm;
1029                         found = true;
1030                 }
1031         }
1032
1033         return found;
1034 }
1035
1036 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1037                         struct dpll *best_clock)
1038 {
1039         int refclk = 100000;
1040         const struct intel_limit *limit = &intel_limits_bxt;
1041
1042         return chv_find_best_dpll(limit, crtc_state,
1043                                   target_clock, refclk, NULL, best_clock);
1044 }
1045
1046 bool intel_crtc_active(struct drm_crtc *crtc)
1047 {
1048         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1049
1050         /* Be paranoid as we can arrive here with only partial
1051          * state retrieved from the hardware during setup.
1052          *
1053          * We can ditch the adjusted_mode.crtc_clock check as soon
1054          * as Haswell has gained clock readout/fastboot support.
1055          *
1056          * We can ditch the crtc->primary->fb check as soon as we can
1057          * properly reconstruct framebuffers.
1058          *
1059          * FIXME: The intel_crtc->active here should be switched to
1060          * crtc->state->active once we have proper CRTC states wired up
1061          * for atomic.
1062          */
1063         return intel_crtc->active && crtc->primary->state->fb &&
1064                 intel_crtc->config->base.adjusted_mode.crtc_clock;
1065 }
1066
1067 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1068                                              enum pipe pipe)
1069 {
1070         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1072
1073         return intel_crtc->config->cpu_transcoder;
1074 }
1075
1076 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1077 {
1078         struct drm_i915_private *dev_priv = dev->dev_private;
1079         i915_reg_t reg = PIPEDSL(pipe);
1080         u32 line1, line2;
1081         u32 line_mask;
1082
1083         if (IS_GEN2(dev))
1084                 line_mask = DSL_LINEMASK_GEN2;
1085         else
1086                 line_mask = DSL_LINEMASK_GEN3;
1087
1088         line1 = I915_READ(reg) & line_mask;
1089         msleep(5);
1090         line2 = I915_READ(reg) & line_mask;
1091
1092         return line1 == line2;
1093 }
1094
1095 /*
1096  * intel_wait_for_pipe_off - wait for pipe to turn off
1097  * @crtc: crtc whose pipe to wait for
1098  *
1099  * After disabling a pipe, we can't wait for vblank in the usual way,
1100  * spinning on the vblank interrupt status bit, since we won't actually
1101  * see an interrupt when the pipe is disabled.
1102  *
1103  * On Gen4 and above:
1104  *   wait for the pipe register state bit to turn off
1105  *
1106  * Otherwise:
1107  *   wait for the display line value to settle (it usually
1108  *   ends up stopping at the start of the next frame).
1109  *
1110  */
1111 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1112 {
1113         struct drm_device *dev = crtc->base.dev;
1114         struct drm_i915_private *dev_priv = dev->dev_private;
1115         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1116         enum pipe pipe = crtc->pipe;
1117
1118         if (INTEL_INFO(dev)->gen >= 4) {
1119                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1120
1121                 /* Wait for the Pipe State to go off */
1122                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1123                              100))
1124                         WARN(1, "pipe_off wait timed out\n");
1125         } else {
1126                 /* Wait for the display line to settle */
1127                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1128                         WARN(1, "pipe_off wait timed out\n");
1129         }
1130 }
1131
1132 /* Only for pre-ILK configs */
1133 void assert_pll(struct drm_i915_private *dev_priv,
1134                 enum pipe pipe, bool state)
1135 {
1136         u32 val;
1137         bool cur_state;
1138
1139         val = I915_READ(DPLL(pipe));
1140         cur_state = !!(val & DPLL_VCO_ENABLE);
1141         I915_STATE_WARN(cur_state != state,
1142              "PLL state assertion failure (expected %s, current %s)\n",
1143                         onoff(state), onoff(cur_state));
1144 }
1145
1146 /* XXX: the dsi pll is shared between MIPI DSI ports */
1147 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1148 {
1149         u32 val;
1150         bool cur_state;
1151
1152         mutex_lock(&dev_priv->sb_lock);
1153         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1154         mutex_unlock(&dev_priv->sb_lock);
1155
1156         cur_state = val & DSI_PLL_VCO_EN;
1157         I915_STATE_WARN(cur_state != state,
1158              "DSI PLL state assertion failure (expected %s, current %s)\n",
1159                         onoff(state), onoff(cur_state));
1160 }
1161
1162 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1163                           enum pipe pipe, bool state)
1164 {
1165         bool cur_state;
1166         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1167                                                                       pipe);
1168
1169         if (HAS_DDI(dev_priv)) {
1170                 /* DDI does not have a specific FDI_TX register */
1171                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1172                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1173         } else {
1174                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1175                 cur_state = !!(val & FDI_TX_ENABLE);
1176         }
1177         I915_STATE_WARN(cur_state != state,
1178              "FDI TX state assertion failure (expected %s, current %s)\n",
1179                         onoff(state), onoff(cur_state));
1180 }
1181 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1182 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1183
1184 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1185                           enum pipe pipe, bool state)
1186 {
1187         u32 val;
1188         bool cur_state;
1189
1190         val = I915_READ(FDI_RX_CTL(pipe));
1191         cur_state = !!(val & FDI_RX_ENABLE);
1192         I915_STATE_WARN(cur_state != state,
1193              "FDI RX state assertion failure (expected %s, current %s)\n",
1194                         onoff(state), onoff(cur_state));
1195 }
1196 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1197 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1198
1199 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1200                                       enum pipe pipe)
1201 {
1202         u32 val;
1203
1204         /* ILK FDI PLL is always enabled */
1205         if (IS_GEN5(dev_priv))
1206                 return;
1207
1208         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1209         if (HAS_DDI(dev_priv))
1210                 return;
1211
1212         val = I915_READ(FDI_TX_CTL(pipe));
1213         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1214 }
1215
1216 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1217                        enum pipe pipe, bool state)
1218 {
1219         u32 val;
1220         bool cur_state;
1221
1222         val = I915_READ(FDI_RX_CTL(pipe));
1223         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1224         I915_STATE_WARN(cur_state != state,
1225              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1226                         onoff(state), onoff(cur_state));
1227 }
1228
1229 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1230                            enum pipe pipe)
1231 {
1232         struct drm_device *dev = dev_priv->dev;
1233         i915_reg_t pp_reg;
1234         u32 val;
1235         enum pipe panel_pipe = PIPE_A;
1236         bool locked = true;
1237
1238         if (WARN_ON(HAS_DDI(dev)))
1239                 return;
1240
1241         if (HAS_PCH_SPLIT(dev)) {
1242                 u32 port_sel;
1243
1244                 pp_reg = PCH_PP_CONTROL;
1245                 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1246
1247                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1248                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1249                         panel_pipe = PIPE_B;
1250                 /* XXX: else fix for eDP */
1251         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1252                 /* presumably write lock depends on pipe, not port select */
1253                 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1254                 panel_pipe = pipe;
1255         } else {
1256                 pp_reg = PP_CONTROL;
1257                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1258                         panel_pipe = PIPE_B;
1259         }
1260
1261         val = I915_READ(pp_reg);
1262         if (!(val & PANEL_POWER_ON) ||
1263             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1264                 locked = false;
1265
1266         I915_STATE_WARN(panel_pipe == pipe && locked,
1267              "panel assertion failure, pipe %c regs locked\n",
1268              pipe_name(pipe));
1269 }
1270
1271 static void assert_cursor(struct drm_i915_private *dev_priv,
1272                           enum pipe pipe, bool state)
1273 {
1274         struct drm_device *dev = dev_priv->dev;
1275         bool cur_state;
1276
1277         if (IS_845G(dev) || IS_I865G(dev))
1278                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1279         else
1280                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1281
1282         I915_STATE_WARN(cur_state != state,
1283              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1284                         pipe_name(pipe), onoff(state), onoff(cur_state));
1285 }
1286 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1287 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1288
1289 void assert_pipe(struct drm_i915_private *dev_priv,
1290                  enum pipe pipe, bool state)
1291 {
1292         bool cur_state;
1293         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1294                                                                       pipe);
1295         enum intel_display_power_domain power_domain;
1296
1297         /* if we need the pipe quirk it must be always on */
1298         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1299             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1300                 state = true;
1301
1302         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1303         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1304                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1305                 cur_state = !!(val & PIPECONF_ENABLE);
1306
1307                 intel_display_power_put(dev_priv, power_domain);
1308         } else {
1309                 cur_state = false;
1310         }
1311
1312         I915_STATE_WARN(cur_state != state,
1313              "pipe %c assertion failure (expected %s, current %s)\n",
1314                         pipe_name(pipe), onoff(state), onoff(cur_state));
1315 }
1316
1317 static void assert_plane(struct drm_i915_private *dev_priv,
1318                          enum plane plane, bool state)
1319 {
1320         u32 val;
1321         bool cur_state;
1322
1323         val = I915_READ(DSPCNTR(plane));
1324         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1325         I915_STATE_WARN(cur_state != state,
1326              "plane %c assertion failure (expected %s, current %s)\n",
1327                         plane_name(plane), onoff(state), onoff(cur_state));
1328 }
1329
1330 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1331 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1332
1333 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1334                                    enum pipe pipe)
1335 {
1336         struct drm_device *dev = dev_priv->dev;
1337         int i;
1338
1339         /* Primary planes are fixed to pipes on gen4+ */
1340         if (INTEL_INFO(dev)->gen >= 4) {
1341                 u32 val = I915_READ(DSPCNTR(pipe));
1342                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1343                      "plane %c assertion failure, should be disabled but not\n",
1344                      plane_name(pipe));
1345                 return;
1346         }
1347
1348         /* Need to check both planes against the pipe */
1349         for_each_pipe(dev_priv, i) {
1350                 u32 val = I915_READ(DSPCNTR(i));
1351                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1352                         DISPPLANE_SEL_PIPE_SHIFT;
1353                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1354                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1355                      plane_name(i), pipe_name(pipe));
1356         }
1357 }
1358
1359 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1360                                     enum pipe pipe)
1361 {
1362         struct drm_device *dev = dev_priv->dev;
1363         int sprite;
1364
1365         if (INTEL_INFO(dev)->gen >= 9) {
1366                 for_each_sprite(dev_priv, pipe, sprite) {
1367                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1368                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1369                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1370                              sprite, pipe_name(pipe));
1371                 }
1372         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1373                 for_each_sprite(dev_priv, pipe, sprite) {
1374                         u32 val = I915_READ(SPCNTR(pipe, sprite));
1375                         I915_STATE_WARN(val & SP_ENABLE,
1376                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1377                              sprite_name(pipe, sprite), pipe_name(pipe));
1378                 }
1379         } else if (INTEL_INFO(dev)->gen >= 7) {
1380                 u32 val = I915_READ(SPRCTL(pipe));
1381                 I915_STATE_WARN(val & SPRITE_ENABLE,
1382                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1383                      plane_name(pipe), pipe_name(pipe));
1384         } else if (INTEL_INFO(dev)->gen >= 5) {
1385                 u32 val = I915_READ(DVSCNTR(pipe));
1386                 I915_STATE_WARN(val & DVS_ENABLE,
1387                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1388                      plane_name(pipe), pipe_name(pipe));
1389         }
1390 }
1391
1392 static void assert_vblank_disabled(struct drm_crtc *crtc)
1393 {
1394         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1395                 drm_crtc_vblank_put(crtc);
1396 }
1397
1398 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1399                                     enum pipe pipe)
1400 {
1401         u32 val;
1402         bool enabled;
1403
1404         val = I915_READ(PCH_TRANSCONF(pipe));
1405         enabled = !!(val & TRANS_ENABLE);
1406         I915_STATE_WARN(enabled,
1407              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1408              pipe_name(pipe));
1409 }
1410
1411 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1412                             enum pipe pipe, u32 port_sel, u32 val)
1413 {
1414         if ((val & DP_PORT_EN) == 0)
1415                 return false;
1416
1417         if (HAS_PCH_CPT(dev_priv)) {
1418                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1419                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1420                         return false;
1421         } else if (IS_CHERRYVIEW(dev_priv)) {
1422                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1423                         return false;
1424         } else {
1425                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1426                         return false;
1427         }
1428         return true;
1429 }
1430
1431 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1432                               enum pipe pipe, u32 val)
1433 {
1434         if ((val & SDVO_ENABLE) == 0)
1435                 return false;
1436
1437         if (HAS_PCH_CPT(dev_priv)) {
1438                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1439                         return false;
1440         } else if (IS_CHERRYVIEW(dev_priv)) {
1441                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1442                         return false;
1443         } else {
1444                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1445                         return false;
1446         }
1447         return true;
1448 }
1449
1450 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1451                               enum pipe pipe, u32 val)
1452 {
1453         if ((val & LVDS_PORT_EN) == 0)
1454                 return false;
1455
1456         if (HAS_PCH_CPT(dev_priv)) {
1457                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1458                         return false;
1459         } else {
1460                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1461                         return false;
1462         }
1463         return true;
1464 }
1465
1466 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1467                               enum pipe pipe, u32 val)
1468 {
1469         if ((val & ADPA_DAC_ENABLE) == 0)
1470                 return false;
1471         if (HAS_PCH_CPT(dev_priv)) {
1472                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1473                         return false;
1474         } else {
1475                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1476                         return false;
1477         }
1478         return true;
1479 }
1480
1481 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1482                                    enum pipe pipe, i915_reg_t reg,
1483                                    u32 port_sel)
1484 {
1485         u32 val = I915_READ(reg);
1486         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1487              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1488              i915_mmio_reg_offset(reg), pipe_name(pipe));
1489
1490         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1491              && (val & DP_PIPEB_SELECT),
1492              "IBX PCH dp port still using transcoder B\n");
1493 }
1494
1495 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1496                                      enum pipe pipe, i915_reg_t reg)
1497 {
1498         u32 val = I915_READ(reg);
1499         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1500              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1501              i915_mmio_reg_offset(reg), pipe_name(pipe));
1502
1503         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1504              && (val & SDVO_PIPE_B_SELECT),
1505              "IBX PCH hdmi port still using transcoder B\n");
1506 }
1507
1508 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1509                                       enum pipe pipe)
1510 {
1511         u32 val;
1512
1513         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1514         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1515         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1516
1517         val = I915_READ(PCH_ADPA);
1518         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1519              "PCH VGA enabled on transcoder %c, should be disabled\n",
1520              pipe_name(pipe));
1521
1522         val = I915_READ(PCH_LVDS);
1523         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1524              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1525              pipe_name(pipe));
1526
1527         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1528         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1529         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1530 }
1531
1532 static void _vlv_enable_pll(struct intel_crtc *crtc,
1533                             const struct intel_crtc_state *pipe_config)
1534 {
1535         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1536         enum pipe pipe = crtc->pipe;
1537
1538         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1539         POSTING_READ(DPLL(pipe));
1540         udelay(150);
1541
1542         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1543                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1544 }
1545
1546 static void vlv_enable_pll(struct intel_crtc *crtc,
1547                            const struct intel_crtc_state *pipe_config)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550         enum pipe pipe = crtc->pipe;
1551
1552         assert_pipe_disabled(dev_priv, pipe);
1553
1554         /* PLL is protected by panel, make sure we can write it */
1555         assert_panel_unlocked(dev_priv, pipe);
1556
1557         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1558                 _vlv_enable_pll(crtc, pipe_config);
1559
1560         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1561         POSTING_READ(DPLL_MD(pipe));
1562 }
1563
1564
1565 static void _chv_enable_pll(struct intel_crtc *crtc,
1566                             const struct intel_crtc_state *pipe_config)
1567 {
1568         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1569         enum pipe pipe = crtc->pipe;
1570         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1571         u32 tmp;
1572
1573         mutex_lock(&dev_priv->sb_lock);
1574
1575         /* Enable back the 10bit clock to display controller */
1576         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1577         tmp |= DPIO_DCLKP_EN;
1578         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1579
1580         mutex_unlock(&dev_priv->sb_lock);
1581
1582         /*
1583          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1584          */
1585         udelay(1);
1586
1587         /* Enable PLL */
1588         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1589
1590         /* Check PLL is locked */
1591         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1592                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1593 }
1594
1595 static void chv_enable_pll(struct intel_crtc *crtc,
1596                            const struct intel_crtc_state *pipe_config)
1597 {
1598         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1599         enum pipe pipe = crtc->pipe;
1600
1601         assert_pipe_disabled(dev_priv, pipe);
1602
1603         /* PLL is protected by panel, make sure we can write it */
1604         assert_panel_unlocked(dev_priv, pipe);
1605
1606         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1607                 _chv_enable_pll(crtc, pipe_config);
1608
1609         if (pipe != PIPE_A) {
1610                 /*
1611                  * WaPixelRepeatModeFixForC0:chv
1612                  *
1613                  * DPLLCMD is AWOL. Use chicken bits to propagate
1614                  * the value from DPLLBMD to either pipe B or C.
1615                  */
1616                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1617                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1618                 I915_WRITE(CBR4_VLV, 0);
1619                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1620
1621                 /*
1622                  * DPLLB VGA mode also seems to cause problems.
1623                  * We should always have it disabled.
1624                  */
1625                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1626         } else {
1627                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1628                 POSTING_READ(DPLL_MD(pipe));
1629         }
1630 }
1631
1632 static int intel_num_dvo_pipes(struct drm_device *dev)
1633 {
1634         struct intel_crtc *crtc;
1635         int count = 0;
1636
1637         for_each_intel_crtc(dev, crtc)
1638                 count += crtc->base.state->active &&
1639                         intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1640
1641         return count;
1642 }
1643
1644 static void i9xx_enable_pll(struct intel_crtc *crtc)
1645 {
1646         struct drm_device *dev = crtc->base.dev;
1647         struct drm_i915_private *dev_priv = dev->dev_private;
1648         i915_reg_t reg = DPLL(crtc->pipe);
1649         u32 dpll = crtc->config->dpll_hw_state.dpll;
1650
1651         assert_pipe_disabled(dev_priv, crtc->pipe);
1652
1653         /* PLL is protected by panel, make sure we can write it */
1654         if (IS_MOBILE(dev) && !IS_I830(dev))
1655                 assert_panel_unlocked(dev_priv, crtc->pipe);
1656
1657         /* Enable DVO 2x clock on both PLLs if necessary */
1658         if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1659                 /*
1660                  * It appears to be important that we don't enable this
1661                  * for the current pipe before otherwise configuring the
1662                  * PLL. No idea how this should be handled if multiple
1663                  * DVO outputs are enabled simultaneosly.
1664                  */
1665                 dpll |= DPLL_DVO_2X_MODE;
1666                 I915_WRITE(DPLL(!crtc->pipe),
1667                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1668         }
1669
1670         /*
1671          * Apparently we need to have VGA mode enabled prior to changing
1672          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1673          * dividers, even though the register value does change.
1674          */
1675         I915_WRITE(reg, 0);
1676
1677         I915_WRITE(reg, dpll);
1678
1679         /* Wait for the clocks to stabilize. */
1680         POSTING_READ(reg);
1681         udelay(150);
1682
1683         if (INTEL_INFO(dev)->gen >= 4) {
1684                 I915_WRITE(DPLL_MD(crtc->pipe),
1685                            crtc->config->dpll_hw_state.dpll_md);
1686         } else {
1687                 /* The pixel multiplier can only be updated once the
1688                  * DPLL is enabled and the clocks are stable.
1689                  *
1690                  * So write it again.
1691                  */
1692                 I915_WRITE(reg, dpll);
1693         }
1694
1695         /* We do this three times for luck */
1696         I915_WRITE(reg, dpll);
1697         POSTING_READ(reg);
1698         udelay(150); /* wait for warmup */
1699         I915_WRITE(reg, dpll);
1700         POSTING_READ(reg);
1701         udelay(150); /* wait for warmup */
1702         I915_WRITE(reg, dpll);
1703         POSTING_READ(reg);
1704         udelay(150); /* wait for warmup */
1705 }
1706
1707 /**
1708  * i9xx_disable_pll - disable a PLL
1709  * @dev_priv: i915 private structure
1710  * @pipe: pipe PLL to disable
1711  *
1712  * Disable the PLL for @pipe, making sure the pipe is off first.
1713  *
1714  * Note!  This is for pre-ILK only.
1715  */
1716 static void i9xx_disable_pll(struct intel_crtc *crtc)
1717 {
1718         struct drm_device *dev = crtc->base.dev;
1719         struct drm_i915_private *dev_priv = dev->dev_private;
1720         enum pipe pipe = crtc->pipe;
1721
1722         /* Disable DVO 2x clock on both PLLs if necessary */
1723         if (IS_I830(dev) &&
1724             intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1725             !intel_num_dvo_pipes(dev)) {
1726                 I915_WRITE(DPLL(PIPE_B),
1727                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1728                 I915_WRITE(DPLL(PIPE_A),
1729                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1730         }
1731
1732         /* Don't disable pipe or pipe PLLs if needed */
1733         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1734             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1735                 return;
1736
1737         /* Make sure the pipe isn't still relying on us */
1738         assert_pipe_disabled(dev_priv, pipe);
1739
1740         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1741         POSTING_READ(DPLL(pipe));
1742 }
1743
1744 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1745 {
1746         u32 val;
1747
1748         /* Make sure the pipe isn't still relying on us */
1749         assert_pipe_disabled(dev_priv, pipe);
1750
1751         val = DPLL_INTEGRATED_REF_CLK_VLV |
1752                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1753         if (pipe != PIPE_A)
1754                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1755
1756         I915_WRITE(DPLL(pipe), val);
1757         POSTING_READ(DPLL(pipe));
1758 }
1759
1760 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1761 {
1762         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1763         u32 val;
1764
1765         /* Make sure the pipe isn't still relying on us */
1766         assert_pipe_disabled(dev_priv, pipe);
1767
1768         val = DPLL_SSC_REF_CLK_CHV |
1769                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1770         if (pipe != PIPE_A)
1771                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1772
1773         I915_WRITE(DPLL(pipe), val);
1774         POSTING_READ(DPLL(pipe));
1775
1776         mutex_lock(&dev_priv->sb_lock);
1777
1778         /* Disable 10bit clock to display controller */
1779         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1780         val &= ~DPIO_DCLKP_EN;
1781         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1782
1783         mutex_unlock(&dev_priv->sb_lock);
1784 }
1785
1786 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1787                          struct intel_digital_port *dport,
1788                          unsigned int expected_mask)
1789 {
1790         u32 port_mask;
1791         i915_reg_t dpll_reg;
1792
1793         switch (dport->port) {
1794         case PORT_B:
1795                 port_mask = DPLL_PORTB_READY_MASK;
1796                 dpll_reg = DPLL(0);
1797                 break;
1798         case PORT_C:
1799                 port_mask = DPLL_PORTC_READY_MASK;
1800                 dpll_reg = DPLL(0);
1801                 expected_mask <<= 4;
1802                 break;
1803         case PORT_D:
1804                 port_mask = DPLL_PORTD_READY_MASK;
1805                 dpll_reg = DPIO_PHY_STATUS;
1806                 break;
1807         default:
1808                 BUG();
1809         }
1810
1811         if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1812                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1813                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1814 }
1815
1816 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1817                                            enum pipe pipe)
1818 {
1819         struct drm_device *dev = dev_priv->dev;
1820         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1821         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1822         i915_reg_t reg;
1823         uint32_t val, pipeconf_val;
1824
1825         /* Make sure PCH DPLL is enabled */
1826         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1827
1828         /* FDI must be feeding us bits for PCH ports */
1829         assert_fdi_tx_enabled(dev_priv, pipe);
1830         assert_fdi_rx_enabled(dev_priv, pipe);
1831
1832         if (HAS_PCH_CPT(dev)) {
1833                 /* Workaround: Set the timing override bit before enabling the
1834                  * pch transcoder. */
1835                 reg = TRANS_CHICKEN2(pipe);
1836                 val = I915_READ(reg);
1837                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1838                 I915_WRITE(reg, val);
1839         }
1840
1841         reg = PCH_TRANSCONF(pipe);
1842         val = I915_READ(reg);
1843         pipeconf_val = I915_READ(PIPECONF(pipe));
1844
1845         if (HAS_PCH_IBX(dev_priv)) {
1846                 /*
1847                  * Make the BPC in transcoder be consistent with
1848                  * that in pipeconf reg. For HDMI we must use 8bpc
1849                  * here for both 8bpc and 12bpc.
1850                  */
1851                 val &= ~PIPECONF_BPC_MASK;
1852                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1853                         val |= PIPECONF_8BPC;
1854                 else
1855                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1856         }
1857
1858         val &= ~TRANS_INTERLACE_MASK;
1859         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1860                 if (HAS_PCH_IBX(dev_priv) &&
1861                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1862                         val |= TRANS_LEGACY_INTERLACED_ILK;
1863                 else
1864                         val |= TRANS_INTERLACED;
1865         else
1866                 val |= TRANS_PROGRESSIVE;
1867
1868         I915_WRITE(reg, val | TRANS_ENABLE);
1869         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1870                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1871 }
1872
1873 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1874                                       enum transcoder cpu_transcoder)
1875 {
1876         u32 val, pipeconf_val;
1877
1878         /* FDI must be feeding us bits for PCH ports */
1879         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1880         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1881
1882         /* Workaround: set timing override bit. */
1883         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1884         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1885         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1886
1887         val = TRANS_ENABLE;
1888         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1889
1890         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1891             PIPECONF_INTERLACED_ILK)
1892                 val |= TRANS_INTERLACED;
1893         else
1894                 val |= TRANS_PROGRESSIVE;
1895
1896         I915_WRITE(LPT_TRANSCONF, val);
1897         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1898                 DRM_ERROR("Failed to enable PCH transcoder\n");
1899 }
1900
1901 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1902                                             enum pipe pipe)
1903 {
1904         struct drm_device *dev = dev_priv->dev;
1905         i915_reg_t reg;
1906         uint32_t val;
1907
1908         /* FDI relies on the transcoder */
1909         assert_fdi_tx_disabled(dev_priv, pipe);
1910         assert_fdi_rx_disabled(dev_priv, pipe);
1911
1912         /* Ports must be off as well */
1913         assert_pch_ports_disabled(dev_priv, pipe);
1914
1915         reg = PCH_TRANSCONF(pipe);
1916         val = I915_READ(reg);
1917         val &= ~TRANS_ENABLE;
1918         I915_WRITE(reg, val);
1919         /* wait for PCH transcoder off, transcoder state */
1920         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1921                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1922
1923         if (HAS_PCH_CPT(dev)) {
1924                 /* Workaround: Clear the timing override chicken bit again. */
1925                 reg = TRANS_CHICKEN2(pipe);
1926                 val = I915_READ(reg);
1927                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1928                 I915_WRITE(reg, val);
1929         }
1930 }
1931
1932 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1933 {
1934         u32 val;
1935
1936         val = I915_READ(LPT_TRANSCONF);
1937         val &= ~TRANS_ENABLE;
1938         I915_WRITE(LPT_TRANSCONF, val);
1939         /* wait for PCH transcoder off, transcoder state */
1940         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1941                 DRM_ERROR("Failed to disable PCH transcoder\n");
1942
1943         /* Workaround: clear timing override bit. */
1944         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1945         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1946         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1947 }
1948
1949 /**
1950  * intel_enable_pipe - enable a pipe, asserting requirements
1951  * @crtc: crtc responsible for the pipe
1952  *
1953  * Enable @crtc's pipe, making sure that various hardware specific requirements
1954  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1955  */
1956 static void intel_enable_pipe(struct intel_crtc *crtc)
1957 {
1958         struct drm_device *dev = crtc->base.dev;
1959         struct drm_i915_private *dev_priv = dev->dev_private;
1960         enum pipe pipe = crtc->pipe;
1961         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1962         enum pipe pch_transcoder;
1963         i915_reg_t reg;
1964         u32 val;
1965
1966         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1967
1968         assert_planes_disabled(dev_priv, pipe);
1969         assert_cursor_disabled(dev_priv, pipe);
1970         assert_sprites_disabled(dev_priv, pipe);
1971
1972         if (HAS_PCH_LPT(dev_priv))
1973                 pch_transcoder = TRANSCODER_A;
1974         else
1975                 pch_transcoder = pipe;
1976
1977         /*
1978          * A pipe without a PLL won't actually be able to drive bits from
1979          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1980          * need the check.
1981          */
1982         if (HAS_GMCH_DISPLAY(dev_priv))
1983                 if (crtc->config->has_dsi_encoder)
1984                         assert_dsi_pll_enabled(dev_priv);
1985                 else
1986                         assert_pll_enabled(dev_priv, pipe);
1987         else {
1988                 if (crtc->config->has_pch_encoder) {
1989                         /* if driving the PCH, we need FDI enabled */
1990                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1991                         assert_fdi_tx_pll_enabled(dev_priv,
1992                                                   (enum pipe) cpu_transcoder);
1993                 }
1994                 /* FIXME: assert CPU port conditions for SNB+ */
1995         }
1996
1997         reg = PIPECONF(cpu_transcoder);
1998         val = I915_READ(reg);
1999         if (val & PIPECONF_ENABLE) {
2000                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2001                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2002                 return;
2003         }
2004
2005         I915_WRITE(reg, val | PIPECONF_ENABLE);
2006         POSTING_READ(reg);
2007
2008         /*
2009          * Until the pipe starts DSL will read as 0, which would cause
2010          * an apparent vblank timestamp jump, which messes up also the
2011          * frame count when it's derived from the timestamps. So let's
2012          * wait for the pipe to start properly before we call
2013          * drm_crtc_vblank_on()
2014          */
2015         if (dev->max_vblank_count == 0 &&
2016             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2017                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2018 }
2019
2020 /**
2021  * intel_disable_pipe - disable a pipe, asserting requirements
2022  * @crtc: crtc whose pipes is to be disabled
2023  *
2024  * Disable the pipe of @crtc, making sure that various hardware
2025  * specific requirements are met, if applicable, e.g. plane
2026  * disabled, panel fitter off, etc.
2027  *
2028  * Will wait until the pipe has shut down before returning.
2029  */
2030 static void intel_disable_pipe(struct intel_crtc *crtc)
2031 {
2032         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2033         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2034         enum pipe pipe = crtc->pipe;
2035         i915_reg_t reg;
2036         u32 val;
2037
2038         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2039
2040         /*
2041          * Make sure planes won't keep trying to pump pixels to us,
2042          * or we might hang the display.
2043          */
2044         assert_planes_disabled(dev_priv, pipe);
2045         assert_cursor_disabled(dev_priv, pipe);
2046         assert_sprites_disabled(dev_priv, pipe);
2047
2048         reg = PIPECONF(cpu_transcoder);
2049         val = I915_READ(reg);
2050         if ((val & PIPECONF_ENABLE) == 0)
2051                 return;
2052
2053         /*
2054          * Double wide has implications for planes
2055          * so best keep it disabled when not needed.
2056          */
2057         if (crtc->config->double_wide)
2058                 val &= ~PIPECONF_DOUBLE_WIDE;
2059
2060         /* Don't disable pipe or pipe PLLs if needed */
2061         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2062             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2063                 val &= ~PIPECONF_ENABLE;
2064
2065         I915_WRITE(reg, val);
2066         if ((val & PIPECONF_ENABLE) == 0)
2067                 intel_wait_for_pipe_off(crtc);
2068 }
2069
2070 static bool need_vtd_wa(struct drm_device *dev)
2071 {
2072 #ifdef CONFIG_INTEL_IOMMU
2073         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2074                 return true;
2075 #endif
2076         return false;
2077 }
2078
2079 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2080 {
2081         return IS_GEN2(dev_priv) ? 2048 : 4096;
2082 }
2083
2084 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2085                                            uint64_t fb_modifier, unsigned int cpp)
2086 {
2087         switch (fb_modifier) {
2088         case DRM_FORMAT_MOD_NONE:
2089                 return cpp;
2090         case I915_FORMAT_MOD_X_TILED:
2091                 if (IS_GEN2(dev_priv))
2092                         return 128;
2093                 else
2094                         return 512;
2095         case I915_FORMAT_MOD_Y_TILED:
2096                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2097                         return 128;
2098                 else
2099                         return 512;
2100         case I915_FORMAT_MOD_Yf_TILED:
2101                 switch (cpp) {
2102                 case 1:
2103                         return 64;
2104                 case 2:
2105                 case 4:
2106                         return 128;
2107                 case 8:
2108                 case 16:
2109                         return 256;
2110                 default:
2111                         MISSING_CASE(cpp);
2112                         return cpp;
2113                 }
2114                 break;
2115         default:
2116                 MISSING_CASE(fb_modifier);
2117                 return cpp;
2118         }
2119 }
2120
2121 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2122                                uint64_t fb_modifier, unsigned int cpp)
2123 {
2124         if (fb_modifier == DRM_FORMAT_MOD_NONE)
2125                 return 1;
2126         else
2127                 return intel_tile_size(dev_priv) /
2128                         intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2129 }
2130
2131 /* Return the tile dimensions in pixel units */
2132 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2133                             unsigned int *tile_width,
2134                             unsigned int *tile_height,
2135                             uint64_t fb_modifier,
2136                             unsigned int cpp)
2137 {
2138         unsigned int tile_width_bytes =
2139                 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2140
2141         *tile_width = tile_width_bytes / cpp;
2142         *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2143 }
2144
2145 unsigned int
2146 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2147                       uint32_t pixel_format, uint64_t fb_modifier)
2148 {
2149         unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2150         unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2151
2152         return ALIGN(height, tile_height);
2153 }
2154
2155 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2156 {
2157         unsigned int size = 0;
2158         int i;
2159
2160         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2161                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2162
2163         return size;
2164 }
2165
2166 static void
2167 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2168                         const struct drm_framebuffer *fb,
2169                         unsigned int rotation)
2170 {
2171         if (intel_rotation_90_or_270(rotation)) {
2172                 *view = i915_ggtt_view_rotated;
2173                 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2174         } else {
2175                 *view = i915_ggtt_view_normal;
2176         }
2177 }
2178
2179 static void
2180 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2181                    struct drm_framebuffer *fb)
2182 {
2183         struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2184         unsigned int tile_size, tile_width, tile_height, cpp;
2185
2186         tile_size = intel_tile_size(dev_priv);
2187
2188         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2189         intel_tile_dims(dev_priv, &tile_width, &tile_height,
2190                         fb->modifier[0], cpp);
2191
2192         info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2193         info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2194
2195         if (info->pixel_format == DRM_FORMAT_NV12) {
2196                 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2197                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2198                                 fb->modifier[1], cpp);
2199
2200                 info->uv_offset = fb->offsets[1];
2201                 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2202                 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2203         }
2204 }
2205
2206 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2207 {
2208         if (INTEL_INFO(dev_priv)->gen >= 9)
2209                 return 256 * 1024;
2210         else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2211                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2212                 return 128 * 1024;
2213         else if (INTEL_INFO(dev_priv)->gen >= 4)
2214                 return 4 * 1024;
2215         else
2216                 return 0;
2217 }
2218
2219 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2220                                          uint64_t fb_modifier)
2221 {
2222         switch (fb_modifier) {
2223         case DRM_FORMAT_MOD_NONE:
2224                 return intel_linear_alignment(dev_priv);
2225         case I915_FORMAT_MOD_X_TILED:
2226                 if (INTEL_INFO(dev_priv)->gen >= 9)
2227                         return 256 * 1024;
2228                 return 0;
2229         case I915_FORMAT_MOD_Y_TILED:
2230         case I915_FORMAT_MOD_Yf_TILED:
2231                 return 1 * 1024 * 1024;
2232         default:
2233                 MISSING_CASE(fb_modifier);
2234                 return 0;
2235         }
2236 }
2237
2238 int
2239 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2240                            unsigned int rotation)
2241 {
2242         struct drm_device *dev = fb->dev;
2243         struct drm_i915_private *dev_priv = dev->dev_private;
2244         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2245         struct i915_ggtt_view view;
2246         u32 alignment;
2247         int ret;
2248
2249         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2250
2251         alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2252
2253         intel_fill_fb_ggtt_view(&view, fb, rotation);
2254
2255         /* Note that the w/a also requires 64 PTE of padding following the
2256          * bo. We currently fill all unused PTE with the shadow page and so
2257          * we should always have valid PTE following the scanout preventing
2258          * the VT-d warning.
2259          */
2260         if (need_vtd_wa(dev) && alignment < 256 * 1024)
2261                 alignment = 256 * 1024;
2262
2263         /*
2264          * Global gtt pte registers are special registers which actually forward
2265          * writes to a chunk of system memory. Which means that there is no risk
2266          * that the register values disappear as soon as we call
2267          * intel_runtime_pm_put(), so it is correct to wrap only the
2268          * pin/unpin/fence and not more.
2269          */
2270         intel_runtime_pm_get(dev_priv);
2271
2272         ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2273                                                    &view);
2274         if (ret)
2275                 goto err_pm;
2276
2277         /* Install a fence for tiled scan-out. Pre-i965 always needs a
2278          * fence, whereas 965+ only requires a fence if using
2279          * framebuffer compression.  For simplicity, we always install
2280          * a fence as the cost is not that onerous.
2281          */
2282         if (view.type == I915_GGTT_VIEW_NORMAL) {
2283                 ret = i915_gem_object_get_fence(obj);
2284                 if (ret == -EDEADLK) {
2285                         /*
2286                          * -EDEADLK means there are no free fences
2287                          * no pending flips.
2288                          *
2289                          * This is propagated to atomic, but it uses
2290                          * -EDEADLK to force a locking recovery, so
2291                          * change the returned error to -EBUSY.
2292                          */
2293                         ret = -EBUSY;
2294                         goto err_unpin;
2295                 } else if (ret)
2296                         goto err_unpin;
2297
2298                 i915_gem_object_pin_fence(obj);
2299         }
2300
2301         intel_runtime_pm_put(dev_priv);
2302         return 0;
2303
2304 err_unpin:
2305         i915_gem_object_unpin_from_display_plane(obj, &view);
2306 err_pm:
2307         intel_runtime_pm_put(dev_priv);
2308         return ret;
2309 }
2310
2311 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2312 {
2313         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2314         struct i915_ggtt_view view;
2315
2316         WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2317
2318         intel_fill_fb_ggtt_view(&view, fb, rotation);
2319
2320         if (view.type == I915_GGTT_VIEW_NORMAL)
2321                 i915_gem_object_unpin_fence(obj);
2322
2323         i915_gem_object_unpin_from_display_plane(obj, &view);
2324 }
2325
2326 /*
2327  * Adjust the tile offset by moving the difference into
2328  * the x/y offsets.
2329  *
2330  * Input tile dimensions and pitch must already be
2331  * rotated to match x and y, and in pixel units.
2332  */
2333 static u32 intel_adjust_tile_offset(int *x, int *y,
2334                                     unsigned int tile_width,
2335                                     unsigned int tile_height,
2336                                     unsigned int tile_size,
2337                                     unsigned int pitch_tiles,
2338                                     u32 old_offset,
2339                                     u32 new_offset)
2340 {
2341         unsigned int tiles;
2342
2343         WARN_ON(old_offset & (tile_size - 1));
2344         WARN_ON(new_offset & (tile_size - 1));
2345         WARN_ON(new_offset > old_offset);
2346
2347         tiles = (old_offset - new_offset) / tile_size;
2348
2349         *y += tiles / pitch_tiles * tile_height;
2350         *x += tiles % pitch_tiles * tile_width;
2351
2352         return new_offset;
2353 }
2354
2355 /*
2356  * Computes the linear offset to the base tile and adjusts
2357  * x, y. bytes per pixel is assumed to be a power-of-two.
2358  *
2359  * In the 90/270 rotated case, x and y are assumed
2360  * to be already rotated to match the rotated GTT view, and
2361  * pitch is the tile_height aligned framebuffer height.
2362  */
2363 u32 intel_compute_tile_offset(int *x, int *y,
2364                               const struct drm_framebuffer *fb, int plane,
2365                               unsigned int pitch,
2366                               unsigned int rotation)
2367 {
2368         const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2369         uint64_t fb_modifier = fb->modifier[plane];
2370         unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2371         u32 offset, offset_aligned, alignment;
2372
2373         alignment = intel_surf_alignment(dev_priv, fb_modifier);
2374         if (alignment)
2375                 alignment--;
2376
2377         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2378                 unsigned int tile_size, tile_width, tile_height;
2379                 unsigned int tile_rows, tiles, pitch_tiles;
2380
2381                 tile_size = intel_tile_size(dev_priv);
2382                 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2383                                 fb_modifier, cpp);
2384
2385                 if (intel_rotation_90_or_270(rotation)) {
2386                         pitch_tiles = pitch / tile_height;
2387                         swap(tile_width, tile_height);
2388                 } else {
2389                         pitch_tiles = pitch / (tile_width * cpp);
2390                 }
2391
2392                 tile_rows = *y / tile_height;
2393                 *y %= tile_height;
2394
2395                 tiles = *x / tile_width;
2396                 *x %= tile_width;
2397
2398                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2399                 offset_aligned = offset & ~alignment;
2400
2401                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2402                                          tile_size, pitch_tiles,
2403                                          offset, offset_aligned);
2404         } else {
2405                 offset = *y * pitch + *x * cpp;
2406                 offset_aligned = offset & ~alignment;
2407
2408                 *y = (offset & alignment) / pitch;
2409                 *x = ((offset & alignment) - *y * pitch) / cpp;
2410         }
2411
2412         return offset_aligned;
2413 }
2414
2415 static int i9xx_format_to_fourcc(int format)
2416 {
2417         switch (format) {
2418         case DISPPLANE_8BPP:
2419                 return DRM_FORMAT_C8;
2420         case DISPPLANE_BGRX555:
2421                 return DRM_FORMAT_XRGB1555;
2422         case DISPPLANE_BGRX565:
2423                 return DRM_FORMAT_RGB565;
2424         default:
2425         case DISPPLANE_BGRX888:
2426                 return DRM_FORMAT_XRGB8888;
2427         case DISPPLANE_RGBX888:
2428                 return DRM_FORMAT_XBGR8888;
2429         case DISPPLANE_BGRX101010:
2430                 return DRM_FORMAT_XRGB2101010;
2431         case DISPPLANE_RGBX101010:
2432                 return DRM_FORMAT_XBGR2101010;
2433         }
2434 }
2435
2436 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2437 {
2438         switch (format) {
2439         case PLANE_CTL_FORMAT_RGB_565:
2440                 return DRM_FORMAT_RGB565;
2441         default:
2442         case PLANE_CTL_FORMAT_XRGB_8888:
2443                 if (rgb_order) {
2444                         if (alpha)
2445                                 return DRM_FORMAT_ABGR8888;
2446                         else
2447                                 return DRM_FORMAT_XBGR8888;
2448                 } else {
2449                         if (alpha)
2450                                 return DRM_FORMAT_ARGB8888;
2451                         else
2452                                 return DRM_FORMAT_XRGB8888;
2453                 }
2454         case PLANE_CTL_FORMAT_XRGB_2101010:
2455                 if (rgb_order)
2456                         return DRM_FORMAT_XBGR2101010;
2457                 else
2458                         return DRM_FORMAT_XRGB2101010;
2459         }
2460 }
2461
2462 static bool
2463 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2464                               struct intel_initial_plane_config *plane_config)
2465 {
2466         struct drm_device *dev = crtc->base.dev;
2467         struct drm_i915_private *dev_priv = to_i915(dev);
2468         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2469         struct drm_i915_gem_object *obj = NULL;
2470         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2471         struct drm_framebuffer *fb = &plane_config->fb->base;
2472         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2473         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2474                                     PAGE_SIZE);
2475
2476         size_aligned -= base_aligned;
2477
2478         if (plane_config->size == 0)
2479                 return false;
2480
2481         /* If the FB is too big, just don't use it since fbdev is not very
2482          * important and we should probably use that space with FBC or other
2483          * features. */
2484         if (size_aligned * 2 > ggtt->stolen_usable_size)
2485                 return false;
2486
2487         mutex_lock(&dev->struct_mutex);
2488
2489         obj = i915_gem_object_create_stolen_for_preallocated(dev,
2490                                                              base_aligned,
2491                                                              base_aligned,
2492                                                              size_aligned);
2493         if (!obj) {
2494                 mutex_unlock(&dev->struct_mutex);
2495                 return false;
2496         }
2497
2498         obj->tiling_mode = plane_config->tiling;
2499         if (obj->tiling_mode == I915_TILING_X)
2500                 obj->stride = fb->pitches[0];
2501
2502         mode_cmd.pixel_format = fb->pixel_format;
2503         mode_cmd.width = fb->width;
2504         mode_cmd.height = fb->height;
2505         mode_cmd.pitches[0] = fb->pitches[0];
2506         mode_cmd.modifier[0] = fb->modifier[0];
2507         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2508
2509         if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2510                                    &mode_cmd, obj)) {
2511                 DRM_DEBUG_KMS("intel fb init failed\n");
2512                 goto out_unref_obj;
2513         }
2514
2515         mutex_unlock(&dev->struct_mutex);
2516
2517         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2518         return true;
2519
2520 out_unref_obj:
2521         drm_gem_object_unreference(&obj->base);
2522         mutex_unlock(&dev->struct_mutex);
2523         return false;
2524 }
2525
2526 static void
2527 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2528                              struct intel_initial_plane_config *plane_config)
2529 {
2530         struct drm_device *dev = intel_crtc->base.dev;
2531         struct drm_i915_private *dev_priv = dev->dev_private;
2532         struct drm_crtc *c;
2533         struct intel_crtc *i;
2534         struct drm_i915_gem_object *obj;
2535         struct drm_plane *primary = intel_crtc->base.primary;
2536         struct drm_plane_state *plane_state = primary->state;
2537         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2538         struct intel_plane *intel_plane = to_intel_plane(primary);
2539         struct intel_plane_state *intel_state =
2540                 to_intel_plane_state(plane_state);
2541         struct drm_framebuffer *fb;
2542
2543         if (!plane_config->fb)
2544                 return;
2545
2546         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2547                 fb = &plane_config->fb->base;
2548                 goto valid_fb;
2549         }
2550
2551         kfree(plane_config->fb);
2552
2553         /*
2554          * Failed to alloc the obj, check to see if we should share
2555          * an fb with another CRTC instead
2556          */
2557         for_each_crtc(dev, c) {
2558                 i = to_intel_crtc(c);
2559
2560                 if (c == &intel_crtc->base)
2561                         continue;
2562
2563                 if (!i->active)
2564                         continue;
2565
2566                 fb = c->primary->fb;
2567                 if (!fb)
2568                         continue;
2569
2570                 obj = intel_fb_obj(fb);
2571                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2572                         drm_framebuffer_reference(fb);
2573                         goto valid_fb;
2574                 }
2575         }
2576
2577         /*
2578          * We've failed to reconstruct the BIOS FB.  Current display state
2579          * indicates that the primary plane is visible, but has a NULL FB,
2580          * which will lead to problems later if we don't fix it up.  The
2581          * simplest solution is to just disable the primary plane now and
2582          * pretend the BIOS never had it enabled.
2583          */
2584         to_intel_plane_state(plane_state)->visible = false;
2585         crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2586         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2587         intel_plane->disable_plane(primary, &intel_crtc->base);
2588
2589         return;
2590
2591 valid_fb:
2592         plane_state->src_x = 0;
2593         plane_state->src_y = 0;
2594         plane_state->src_w = fb->width << 16;
2595         plane_state->src_h = fb->height << 16;
2596
2597         plane_state->crtc_x = 0;
2598         plane_state->crtc_y = 0;
2599         plane_state->crtc_w = fb->width;
2600         plane_state->crtc_h = fb->height;
2601
2602         intel_state->src.x1 = plane_state->src_x;
2603         intel_state->src.y1 = plane_state->src_y;
2604         intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2605         intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2606         intel_state->dst.x1 = plane_state->crtc_x;
2607         intel_state->dst.y1 = plane_state->crtc_y;
2608         intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2609         intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2610
2611         obj = intel_fb_obj(fb);
2612         if (obj->tiling_mode != I915_TILING_NONE)
2613                 dev_priv->preserve_bios_swizzle = true;
2614
2615         drm_framebuffer_reference(fb);
2616         primary->fb = primary->state->fb = fb;
2617         primary->crtc = primary->state->crtc = &intel_crtc->base;
2618         intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2619         obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2620 }
2621
2622 static void i9xx_update_primary_plane(struct drm_plane *primary,
2623                                       const struct intel_crtc_state *crtc_state,
2624                                       const struct intel_plane_state *plane_state)
2625 {
2626         struct drm_device *dev = primary->dev;
2627         struct drm_i915_private *dev_priv = dev->dev_private;
2628         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2629         struct drm_framebuffer *fb = plane_state->base.fb;
2630         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2631         int plane = intel_crtc->plane;
2632         u32 linear_offset;
2633         u32 dspcntr;
2634         i915_reg_t reg = DSPCNTR(plane);
2635         unsigned int rotation = plane_state->base.rotation;
2636         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2637         int x = plane_state->src.x1 >> 16;
2638         int y = plane_state->src.y1 >> 16;
2639
2640         dspcntr = DISPPLANE_GAMMA_ENABLE;
2641
2642         dspcntr |= DISPLAY_PLANE_ENABLE;
2643
2644         if (INTEL_INFO(dev)->gen < 4) {
2645                 if (intel_crtc->pipe == PIPE_B)
2646                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2647
2648                 /* pipesrc and dspsize control the size that is scaled from,
2649                  * which should always be the user's requested size.
2650                  */
2651                 I915_WRITE(DSPSIZE(plane),
2652                            ((crtc_state->pipe_src_h - 1) << 16) |
2653                            (crtc_state->pipe_src_w - 1));
2654                 I915_WRITE(DSPPOS(plane), 0);
2655         } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2656                 I915_WRITE(PRIMSIZE(plane),
2657                            ((crtc_state->pipe_src_h - 1) << 16) |
2658                            (crtc_state->pipe_src_w - 1));
2659                 I915_WRITE(PRIMPOS(plane), 0);
2660                 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2661         }
2662
2663         switch (fb->pixel_format) {
2664         case DRM_FORMAT_C8:
2665                 dspcntr |= DISPPLANE_8BPP;
2666                 break;
2667         case DRM_FORMAT_XRGB1555:
2668                 dspcntr |= DISPPLANE_BGRX555;
2669                 break;
2670         case DRM_FORMAT_RGB565:
2671                 dspcntr |= DISPPLANE_BGRX565;
2672                 break;
2673         case DRM_FORMAT_XRGB8888:
2674                 dspcntr |= DISPPLANE_BGRX888;
2675                 break;
2676         case DRM_FORMAT_XBGR8888:
2677                 dspcntr |= DISPPLANE_RGBX888;
2678                 break;
2679         case DRM_FORMAT_XRGB2101010:
2680                 dspcntr |= DISPPLANE_BGRX101010;
2681                 break;
2682         case DRM_FORMAT_XBGR2101010:
2683                 dspcntr |= DISPPLANE_RGBX101010;
2684                 break;
2685         default:
2686                 BUG();
2687         }
2688
2689         if (INTEL_INFO(dev)->gen >= 4 &&
2690             obj->tiling_mode != I915_TILING_NONE)
2691                 dspcntr |= DISPPLANE_TILED;
2692
2693         if (IS_G4X(dev))
2694                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2695
2696         linear_offset = y * fb->pitches[0] + x * cpp;
2697
2698         if (INTEL_INFO(dev)->gen >= 4) {
2699                 intel_crtc->dspaddr_offset =
2700                         intel_compute_tile_offset(&x, &y, fb, 0,
2701                                                   fb->pitches[0], rotation);
2702                 linear_offset -= intel_crtc->dspaddr_offset;
2703         } else {
2704                 intel_crtc->dspaddr_offset = linear_offset;
2705         }
2706
2707         if (rotation == BIT(DRM_ROTATE_180)) {
2708                 dspcntr |= DISPPLANE_ROTATE_180;
2709
2710                 x += (crtc_state->pipe_src_w - 1);
2711                 y += (crtc_state->pipe_src_h - 1);
2712
2713                 /* Finding the last pixel of the last line of the display
2714                 data and adding to linear_offset*/
2715                 linear_offset +=
2716                         (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2717                         (crtc_state->pipe_src_w - 1) * cpp;
2718         }
2719
2720         intel_crtc->adjusted_x = x;
2721         intel_crtc->adjusted_y = y;
2722
2723         I915_WRITE(reg, dspcntr);
2724
2725         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2726         if (INTEL_INFO(dev)->gen >= 4) {
2727                 I915_WRITE(DSPSURF(plane),
2728                            i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2729                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2730                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2731         } else
2732                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2733         POSTING_READ(reg);
2734 }
2735
2736 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2737                                        struct drm_crtc *crtc)
2738 {
2739         struct drm_device *dev = crtc->dev;
2740         struct drm_i915_private *dev_priv = dev->dev_private;
2741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2742         int plane = intel_crtc->plane;
2743
2744         I915_WRITE(DSPCNTR(plane), 0);
2745         if (INTEL_INFO(dev_priv)->gen >= 4)
2746                 I915_WRITE(DSPSURF(plane), 0);
2747         else
2748                 I915_WRITE(DSPADDR(plane), 0);
2749         POSTING_READ(DSPCNTR(plane));
2750 }
2751
2752 static void ironlake_update_primary_plane(struct drm_plane *primary,
2753                                           const struct intel_crtc_state *crtc_state,
2754                                           const struct intel_plane_state *plane_state)
2755 {
2756         struct drm_device *dev = primary->dev;
2757         struct drm_i915_private *dev_priv = dev->dev_private;
2758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2759         struct drm_framebuffer *fb = plane_state->base.fb;
2760         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2761         int plane = intel_crtc->plane;
2762         u32 linear_offset;
2763         u32 dspcntr;
2764         i915_reg_t reg = DSPCNTR(plane);
2765         unsigned int rotation = plane_state->base.rotation;
2766         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2767         int x = plane_state->src.x1 >> 16;
2768         int y = plane_state->src.y1 >> 16;
2769
2770         dspcntr = DISPPLANE_GAMMA_ENABLE;
2771         dspcntr |= DISPLAY_PLANE_ENABLE;
2772
2773         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2774                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2775
2776         switch (fb->pixel_format) {
2777         case DRM_FORMAT_C8:
2778                 dspcntr |= DISPPLANE_8BPP;
2779                 break;
2780         case DRM_FORMAT_RGB565:
2781                 dspcntr |= DISPPLANE_BGRX565;
2782                 break;
2783         case DRM_FORMAT_XRGB8888:
2784                 dspcntr |= DISPPLANE_BGRX888;
2785                 break;
2786         case DRM_FORMAT_XBGR8888:
2787                 dspcntr |= DISPPLANE_RGBX888;
2788                 break;
2789         case DRM_FORMAT_XRGB2101010:
2790                 dspcntr |= DISPPLANE_BGRX101010;
2791                 break;
2792         case DRM_FORMAT_XBGR2101010:
2793                 dspcntr |= DISPPLANE_RGBX101010;
2794                 break;
2795         default:
2796                 BUG();
2797         }
2798
2799         if (obj->tiling_mode != I915_TILING_NONE)
2800                 dspcntr |= DISPPLANE_TILED;
2801
2802         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2803                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2804
2805         linear_offset = y * fb->pitches[0] + x * cpp;
2806         intel_crtc->dspaddr_offset =
2807                 intel_compute_tile_offset(&x, &y, fb, 0,
2808                                           fb->pitches[0], rotation);
2809         linear_offset -= intel_crtc->dspaddr_offset;
2810         if (rotation == BIT(DRM_ROTATE_180)) {
2811                 dspcntr |= DISPPLANE_ROTATE_180;
2812
2813                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2814                         x += (crtc_state->pipe_src_w - 1);
2815                         y += (crtc_state->pipe_src_h - 1);
2816
2817                         /* Finding the last pixel of the last line of the display
2818                         data and adding to linear_offset*/
2819                         linear_offset +=
2820                                 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2821                                 (crtc_state->pipe_src_w - 1) * cpp;
2822                 }
2823         }
2824
2825         intel_crtc->adjusted_x = x;
2826         intel_crtc->adjusted_y = y;
2827
2828         I915_WRITE(reg, dspcntr);
2829
2830         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2831         I915_WRITE(DSPSURF(plane),
2832                    i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2833         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2834                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2835         } else {
2836                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2837                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2838         }
2839         POSTING_READ(reg);
2840 }
2841
2842 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2843                               uint64_t fb_modifier, uint32_t pixel_format)
2844 {
2845         if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2846                 return 64;
2847         } else {
2848                 int cpp = drm_format_plane_cpp(pixel_format, 0);
2849
2850                 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2851         }
2852 }
2853
2854 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2855                            struct drm_i915_gem_object *obj,
2856                            unsigned int plane)
2857 {
2858         struct i915_ggtt_view view;
2859         struct i915_vma *vma;
2860         u64 offset;
2861
2862         intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2863                                 intel_plane->base.state->rotation);
2864
2865         vma = i915_gem_obj_to_ggtt_view(obj, &view);
2866         if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2867                 view.type))
2868                 return -1;
2869
2870         offset = vma->node.start;
2871
2872         if (plane == 1) {
2873                 offset += vma->ggtt_view.params.rotated.uv_start_page *
2874                           PAGE_SIZE;
2875         }
2876
2877         WARN_ON(upper_32_bits(offset));
2878
2879         return lower_32_bits(offset);
2880 }
2881
2882 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2883 {
2884         struct drm_device *dev = intel_crtc->base.dev;
2885         struct drm_i915_private *dev_priv = dev->dev_private;
2886
2887         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2888         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2889         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2890 }
2891
2892 /*
2893  * This function detaches (aka. unbinds) unused scalers in hardware
2894  */
2895 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2896 {
2897         struct intel_crtc_scaler_state *scaler_state;
2898         int i;
2899
2900         scaler_state = &intel_crtc->config->scaler_state;
2901
2902         /* loop through and disable scalers that aren't in use */
2903         for (i = 0; i < intel_crtc->num_scalers; i++) {
2904                 if (!scaler_state->scalers[i].in_use)
2905                         skl_detach_scaler(intel_crtc, i);
2906         }
2907 }
2908
2909 u32 skl_plane_ctl_format(uint32_t pixel_format)
2910 {
2911         switch (pixel_format) {
2912         case DRM_FORMAT_C8:
2913                 return PLANE_CTL_FORMAT_INDEXED;
2914         case DRM_FORMAT_RGB565:
2915                 return PLANE_CTL_FORMAT_RGB_565;
2916         case DRM_FORMAT_XBGR8888:
2917                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2918         case DRM_FORMAT_XRGB8888:
2919                 return PLANE_CTL_FORMAT_XRGB_8888;
2920         /*
2921          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2922          * to be already pre-multiplied. We need to add a knob (or a different
2923          * DRM_FORMAT) for user-space to configure that.
2924          */
2925         case DRM_FORMAT_ABGR8888:
2926                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2927                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2928         case DRM_FORMAT_ARGB8888:
2929                 return PLANE_CTL_FORMAT_XRGB_8888 |
2930                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2931         case DRM_FORMAT_XRGB2101010:
2932                 return PLANE_CTL_FORMAT_XRGB_2101010;
2933         case DRM_FORMAT_XBGR2101010:
2934                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2935         case DRM_FORMAT_YUYV:
2936                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2937         case DRM_FORMAT_YVYU:
2938                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2939         case DRM_FORMAT_UYVY:
2940                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2941         case DRM_FORMAT_VYUY:
2942                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2943         default:
2944                 MISSING_CASE(pixel_format);
2945         }
2946
2947         return 0;
2948 }
2949
2950 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2951 {
2952         switch (fb_modifier) {
2953         case DRM_FORMAT_MOD_NONE:
2954                 break;
2955         case I915_FORMAT_MOD_X_TILED:
2956                 return PLANE_CTL_TILED_X;
2957         case I915_FORMAT_MOD_Y_TILED:
2958                 return PLANE_CTL_TILED_Y;
2959         case I915_FORMAT_MOD_Yf_TILED:
2960                 return PLANE_CTL_TILED_YF;
2961         default:
2962                 MISSING_CASE(fb_modifier);
2963         }
2964
2965         return 0;
2966 }
2967
2968 u32 skl_plane_ctl_rotation(unsigned int rotation)
2969 {
2970         switch (rotation) {
2971         case BIT(DRM_ROTATE_0):
2972                 break;
2973         /*
2974          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2975          * while i915 HW rotation is clockwise, thats why this swapping.
2976          */
2977         case BIT(DRM_ROTATE_90):
2978                 return PLANE_CTL_ROTATE_270;
2979         case BIT(DRM_ROTATE_180):
2980                 return PLANE_CTL_ROTATE_180;
2981         case BIT(DRM_ROTATE_270):
2982                 return PLANE_CTL_ROTATE_90;
2983         default:
2984                 MISSING_CASE(rotation);
2985         }
2986
2987         return 0;
2988 }
2989
2990 static void skylake_update_primary_plane(struct drm_plane *plane,
2991                                          const struct intel_crtc_state *crtc_state,
2992                                          const struct intel_plane_state *plane_state)
2993 {
2994         struct drm_device *dev = plane->dev;
2995         struct drm_i915_private *dev_priv = dev->dev_private;
2996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2997         struct drm_framebuffer *fb = plane_state->base.fb;
2998         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2999         int pipe = intel_crtc->pipe;
3000         u32 plane_ctl, stride_div, stride;
3001         u32 tile_height, plane_offset, plane_size;
3002         unsigned int rotation = plane_state->base.rotation;
3003         int x_offset, y_offset;
3004         u32 surf_addr;
3005         int scaler_id = plane_state->scaler_id;
3006         int src_x = plane_state->src.x1 >> 16;
3007         int src_y = plane_state->src.y1 >> 16;
3008         int src_w = drm_rect_width(&plane_state->src) >> 16;
3009         int src_h = drm_rect_height(&plane_state->src) >> 16;
3010         int dst_x = plane_state->dst.x1;
3011         int dst_y = plane_state->dst.y1;
3012         int dst_w = drm_rect_width(&plane_state->dst);
3013         int dst_h = drm_rect_height(&plane_state->dst);
3014
3015         plane_ctl = PLANE_CTL_ENABLE |
3016                     PLANE_CTL_PIPE_GAMMA_ENABLE |
3017                     PLANE_CTL_PIPE_CSC_ENABLE;
3018
3019         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3020         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3021         plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3022         plane_ctl |= skl_plane_ctl_rotation(rotation);
3023
3024         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3025                                                fb->pixel_format);
3026         surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3027
3028         WARN_ON(drm_rect_width(&plane_state->src) == 0);
3029
3030         if (intel_rotation_90_or_270(rotation)) {
3031                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3032
3033                 /* stride = Surface height in tiles */
3034                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3035                 stride = DIV_ROUND_UP(fb->height, tile_height);
3036                 x_offset = stride * tile_height - src_y - src_h;
3037                 y_offset = src_x;
3038                 plane_size = (src_w - 1) << 16 | (src_h - 1);
3039         } else {
3040                 stride = fb->pitches[0] / stride_div;
3041                 x_offset = src_x;
3042                 y_offset = src_y;
3043                 plane_size = (src_h - 1) << 16 | (src_w - 1);
3044         }
3045         plane_offset = y_offset << 16 | x_offset;
3046
3047         intel_crtc->adjusted_x = x_offset;
3048         intel_crtc->adjusted_y = y_offset;
3049
3050         I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3051         I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3052         I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3053         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3054
3055         if (scaler_id >= 0) {
3056                 uint32_t ps_ctrl = 0;
3057
3058                 WARN_ON(!dst_w || !dst_h);
3059                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3060                         crtc_state->scaler_state.scalers[scaler_id].mode;
3061                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3062                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3063                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3064                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3065                 I915_WRITE(PLANE_POS(pipe, 0), 0);
3066         } else {
3067                 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3068         }
3069
3070         I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3071
3072         POSTING_READ(PLANE_SURF(pipe, 0));
3073 }
3074
3075 static void skylake_disable_primary_plane(struct drm_plane *primary,
3076                                           struct drm_crtc *crtc)
3077 {
3078         struct drm_device *dev = crtc->dev;
3079         struct drm_i915_private *dev_priv = dev->dev_private;
3080         int pipe = to_intel_crtc(crtc)->pipe;
3081
3082         I915_WRITE(PLANE_CTL(pipe, 0), 0);
3083         I915_WRITE(PLANE_SURF(pipe, 0), 0);
3084         POSTING_READ(PLANE_SURF(pipe, 0));
3085 }
3086
3087 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3088 static int
3089 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3090                            int x, int y, enum mode_set_atomic state)
3091 {
3092         /* Support for kgdboc is disabled, this needs a major rework. */
3093         DRM_ERROR("legacy panic handler not supported any more.\n");
3094
3095         return -ENODEV;
3096 }
3097
3098 static void intel_update_primary_planes(struct drm_device *dev)
3099 {
3100         struct drm_crtc *crtc;
3101
3102         for_each_crtc(dev, crtc) {
3103                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3104                 struct intel_plane_state *plane_state;
3105
3106                 drm_modeset_lock_crtc(crtc, &plane->base);
3107                 plane_state = to_intel_plane_state(plane->base.state);
3108
3109                 if (plane_state->visible)
3110                         plane->update_plane(&plane->base,
3111                                             to_intel_crtc_state(crtc->state),
3112                                             plane_state);
3113
3114                 drm_modeset_unlock_crtc(crtc);
3115         }
3116 }
3117
3118 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3119 {
3120         /* no reset support for gen2 */
3121         if (IS_GEN2(dev_priv))
3122                 return;
3123
3124         /* reset doesn't touch the display */
3125         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
3126                 return;
3127
3128         drm_modeset_lock_all(dev_priv->dev);
3129         /*
3130          * Disabling the crtcs gracefully seems nicer. Also the
3131          * g33 docs say we should at least disable all the planes.
3132          */
3133         intel_display_suspend(dev_priv->dev);
3134 }
3135
3136 void intel_finish_reset(struct drm_i915_private *dev_priv)
3137 {
3138         /* no reset support for gen2 */
3139         if (IS_GEN2(dev_priv))
3140                 return;
3141
3142         /* reset doesn't touch the display */
3143         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
3144                 /*
3145                  * Flips in the rings have been nuked by the reset,
3146                  * so update the base address of all primary
3147                  * planes to the the last fb to make sure we're
3148                  * showing the correct fb after a reset.
3149                  *
3150                  * FIXME: Atomic will make this obsolete since we won't schedule
3151                  * CS-based flips (which might get lost in gpu resets) any more.
3152                  */
3153                 intel_update_primary_planes(dev_priv->dev);
3154                 return;
3155         }
3156
3157         /*
3158          * The display has been reset as well,
3159          * so need a full re-initialization.
3160          */
3161         intel_runtime_pm_disable_interrupts(dev_priv);
3162         intel_runtime_pm_enable_interrupts(dev_priv);
3163
3164         intel_modeset_init_hw(dev_priv->dev);
3165
3166         spin_lock_irq(&dev_priv->irq_lock);
3167         if (dev_priv->display.hpd_irq_setup)
3168                 dev_priv->display.hpd_irq_setup(dev_priv);
3169         spin_unlock_irq(&dev_priv->irq_lock);
3170
3171         intel_display_resume(dev_priv->dev);
3172
3173         intel_hpd_init(dev_priv);
3174
3175         drm_modeset_unlock_all(dev_priv->dev);
3176 }
3177
3178 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3179 {
3180         return !list_empty_careful(&to_intel_crtc(crtc)->flip_work);
3181 }
3182
3183 static void intel_update_pipe_config(struct intel_crtc *crtc,
3184                                      struct intel_crtc_state *old_crtc_state)
3185 {
3186         struct drm_device *dev = crtc->base.dev;
3187         struct drm_i915_private *dev_priv = dev->dev_private;
3188         struct intel_crtc_state *pipe_config =
3189                 to_intel_crtc_state(crtc->base.state);
3190
3191         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3192         crtc->base.mode = crtc->base.state->mode;
3193
3194         DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3195                       old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3196                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3197
3198         /*
3199          * Update pipe size and adjust fitter if needed: the reason for this is
3200          * that in compute_mode_changes we check the native mode (not the pfit
3201          * mode) to see if we can flip rather than do a full mode set. In the
3202          * fastboot case, we'll flip, but if we don't update the pipesrc and
3203          * pfit state, we'll end up with a big fb scanned out into the wrong
3204          * sized surface.
3205          */
3206
3207         I915_WRITE(PIPESRC(crtc->pipe),
3208                    ((pipe_config->pipe_src_w - 1) << 16) |
3209                    (pipe_config->pipe_src_h - 1));
3210
3211         /* on skylake this is done by detaching scalers */
3212         if (INTEL_INFO(dev)->gen >= 9) {
3213                 skl_detach_scalers(crtc);
3214
3215                 if (pipe_config->pch_pfit.enabled)
3216                         skylake_pfit_enable(crtc);
3217         } else if (HAS_PCH_SPLIT(dev)) {
3218                 if (pipe_config->pch_pfit.enabled)
3219                         ironlake_pfit_enable(crtc);
3220                 else if (old_crtc_state->pch_pfit.enabled)
3221                         ironlake_pfit_disable(crtc, true);
3222         }
3223 }
3224
3225 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3226 {
3227         struct drm_device *dev = crtc->dev;
3228         struct drm_i915_private *dev_priv = dev->dev_private;
3229         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3230         int pipe = intel_crtc->pipe;
3231         i915_reg_t reg;
3232         u32 temp;
3233
3234         /* enable normal train */
3235         reg = FDI_TX_CTL(pipe);
3236         temp = I915_READ(reg);
3237         if (IS_IVYBRIDGE(dev)) {
3238                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3239                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3240         } else {
3241                 temp &= ~FDI_LINK_TRAIN_NONE;
3242                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3243         }
3244         I915_WRITE(reg, temp);
3245
3246         reg = FDI_RX_CTL(pipe);
3247         temp = I915_READ(reg);
3248         if (HAS_PCH_CPT(dev)) {
3249                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3250                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3251         } else {
3252                 temp &= ~FDI_LINK_TRAIN_NONE;
3253                 temp |= FDI_LINK_TRAIN_NONE;
3254         }
3255         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3256
3257         /* wait one idle pattern time */
3258         POSTING_READ(reg);
3259         udelay(1000);
3260
3261         /* IVB wants error correction enabled */
3262         if (IS_IVYBRIDGE(dev))
3263                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3264                            FDI_FE_ERRC_ENABLE);
3265 }
3266
3267 /* The FDI link training functions for ILK/Ibexpeak. */
3268 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3269 {
3270         struct drm_device *dev = crtc->dev;
3271         struct drm_i915_private *dev_priv = dev->dev_private;
3272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3273         int pipe = intel_crtc->pipe;
3274         i915_reg_t reg;
3275         u32 temp, tries;
3276
3277         /* FDI needs bits from pipe first */
3278         assert_pipe_enabled(dev_priv, pipe);
3279
3280         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3281            for train result */
3282         reg = FDI_RX_IMR(pipe);
3283         temp = I915_READ(reg);
3284         temp &= ~FDI_RX_SYMBOL_LOCK;
3285         temp &= ~FDI_RX_BIT_LOCK;
3286         I915_WRITE(reg, temp);
3287         I915_READ(reg);
3288         udelay(150);
3289
3290         /* enable CPU FDI TX and PCH FDI RX */
3291         reg = FDI_TX_CTL(pipe);
3292         temp = I915_READ(reg);
3293         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3294         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3295         temp &= ~FDI_LINK_TRAIN_NONE;
3296         temp |= FDI_LINK_TRAIN_PATTERN_1;
3297         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3298
3299         reg = FDI_RX_CTL(pipe);
3300         temp = I915_READ(reg);
3301         temp &= ~FDI_LINK_TRAIN_NONE;
3302         temp |= FDI_LINK_TRAIN_PATTERN_1;
3303         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3304
3305         POSTING_READ(reg);
3306         udelay(150);
3307
3308         /* Ironlake workaround, enable clock pointer after FDI enable*/
3309         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3310         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3311                    FDI_RX_PHASE_SYNC_POINTER_EN);
3312
3313         reg = FDI_RX_IIR(pipe);
3314         for (tries = 0; tries < 5; tries++) {
3315                 temp = I915_READ(reg);
3316                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3317
3318                 if ((temp & FDI_RX_BIT_LOCK)) {
3319                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3320                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3321                         break;
3322                 }
3323         }
3324         if (tries == 5)
3325                 DRM_ERROR("FDI train 1 fail!\n");
3326
3327         /* Train 2 */
3328         reg = FDI_TX_CTL(pipe);
3329         temp = I915_READ(reg);
3330         temp &= ~FDI_LINK_TRAIN_NONE;
3331         temp |= FDI_LINK_TRAIN_PATTERN_2;
3332         I915_WRITE(reg, temp);
3333
3334         reg = FDI_RX_CTL(pipe);
3335         temp = I915_READ(reg);
3336         temp &= ~FDI_LINK_TRAIN_NONE;
3337         temp |= FDI_LINK_TRAIN_PATTERN_2;
3338         I915_WRITE(reg, temp);
3339
3340         POSTING_READ(reg);
3341         udelay(150);
3342
3343         reg = FDI_RX_IIR(pipe);
3344         for (tries = 0; tries < 5; tries++) {
3345                 temp = I915_READ(reg);
3346                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3347
3348                 if (temp & FDI_RX_SYMBOL_LOCK) {
3349                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3350                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3351                         break;
3352                 }
3353         }
3354         if (tries == 5)
3355                 DRM_ERROR("FDI train 2 fail!\n");
3356
3357         DRM_DEBUG_KMS("FDI train done\n");
3358
3359 }
3360
3361 static const int snb_b_fdi_train_param[] = {
3362         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3363         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3364         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3365         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3366 };
3367
3368 /* The FDI link training functions for SNB/Cougarpoint. */
3369 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3370 {
3371         struct drm_device *dev = crtc->dev;
3372         struct drm_i915_private *dev_priv = dev->dev_private;
3373         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3374         int pipe = intel_crtc->pipe;
3375         i915_reg_t reg;
3376         u32 temp, i, retry;
3377
3378         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3379            for train result */
3380         reg = FDI_RX_IMR(pipe);
3381         temp = I915_READ(reg);
3382         temp &= ~FDI_RX_SYMBOL_LOCK;
3383         temp &= ~FDI_RX_BIT_LOCK;
3384         I915_WRITE(reg, temp);
3385
3386         POSTING_READ(reg);
3387         udelay(150);
3388
3389         /* enable CPU FDI TX and PCH FDI RX */
3390         reg = FDI_TX_CTL(pipe);
3391         temp = I915_READ(reg);
3392         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3393         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3394         temp &= ~FDI_LINK_TRAIN_NONE;
3395         temp |= FDI_LINK_TRAIN_PATTERN_1;
3396         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3397         /* SNB-B */
3398         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3399         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3400
3401         I915_WRITE(FDI_RX_MISC(pipe),
3402                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3403
3404         reg = FDI_RX_CTL(pipe);
3405         temp = I915_READ(reg);
3406         if (HAS_PCH_CPT(dev)) {
3407                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3408                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3409         } else {
3410                 temp &= ~FDI_LINK_TRAIN_NONE;
3411                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3412         }
3413         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3414
3415         POSTING_READ(reg);
3416         udelay(150);
3417
3418         for (i = 0; i < 4; i++) {
3419                 reg = FDI_TX_CTL(pipe);
3420                 temp = I915_READ(reg);
3421                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3422                 temp |= snb_b_fdi_train_param[i];
3423                 I915_WRITE(reg, temp);
3424
3425                 POSTING_READ(reg);
3426                 udelay(500);
3427
3428                 for (retry = 0; retry < 5; retry++) {
3429                         reg = FDI_RX_IIR(pipe);
3430                         temp = I915_READ(reg);
3431                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3432                         if (temp & FDI_RX_BIT_LOCK) {
3433                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3434                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3435                                 break;
3436                         }
3437                         udelay(50);
3438                 }
3439                 if (retry < 5)
3440                         break;
3441         }
3442         if (i == 4)
3443                 DRM_ERROR("FDI train 1 fail!\n");
3444
3445         /* Train 2 */
3446         reg = FDI_TX_CTL(pipe);
3447         temp = I915_READ(reg);
3448         temp &= ~FDI_LINK_TRAIN_NONE;
3449         temp |= FDI_LINK_TRAIN_PATTERN_2;
3450         if (IS_GEN6(dev)) {
3451                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3452                 /* SNB-B */
3453                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3454         }
3455         I915_WRITE(reg, temp);
3456
3457         reg = FDI_RX_CTL(pipe);
3458         temp = I915_READ(reg);
3459         if (HAS_PCH_CPT(dev)) {
3460                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3461                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3462         } else {
3463                 temp &= ~FDI_LINK_TRAIN_NONE;
3464                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3465         }
3466         I915_WRITE(reg, temp);
3467
3468         POSTING_READ(reg);
3469         udelay(150);
3470
3471         for (i = 0; i < 4; i++) {
3472                 reg = FDI_TX_CTL(pipe);
3473                 temp = I915_READ(reg);
3474                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3475                 temp |= snb_b_fdi_train_param[i];
3476                 I915_WRITE(reg, temp);
3477
3478                 POSTING_READ(reg);
3479                 udelay(500);
3480
3481                 for (retry = 0; retry < 5; retry++) {
3482                         reg = FDI_RX_IIR(pipe);
3483                         temp = I915_READ(reg);
3484                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3485                         if (temp & FDI_RX_SYMBOL_LOCK) {
3486                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3487                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3488                                 break;
3489                         }
3490                         udelay(50);
3491                 }
3492                 if (retry < 5)
3493                         break;
3494         }
3495         if (i == 4)
3496                 DRM_ERROR("FDI train 2 fail!\n");
3497
3498         DRM_DEBUG_KMS("FDI train done.\n");
3499 }
3500
3501 /* Manual link training for Ivy Bridge A0 parts */
3502 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3503 {
3504         struct drm_device *dev = crtc->dev;
3505         struct drm_i915_private *dev_priv = dev->dev_private;
3506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507         int pipe = intel_crtc->pipe;
3508         i915_reg_t reg;
3509         u32 temp, i, j;
3510
3511         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3512            for train result */
3513         reg = FDI_RX_IMR(pipe);
3514         temp = I915_READ(reg);
3515         temp &= ~FDI_RX_SYMBOL_LOCK;
3516         temp &= ~FDI_RX_BIT_LOCK;
3517         I915_WRITE(reg, temp);
3518
3519         POSTING_READ(reg);
3520         udelay(150);
3521
3522         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3523                       I915_READ(FDI_RX_IIR(pipe)));
3524
3525         /* Try each vswing and preemphasis setting twice before moving on */
3526         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3527                 /* disable first in case we need to retry */
3528                 reg = FDI_TX_CTL(pipe);
3529                 temp = I915_READ(reg);
3530                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3531                 temp &= ~FDI_TX_ENABLE;
3532                 I915_WRITE(reg, temp);
3533
3534                 reg = FDI_RX_CTL(pipe);
3535                 temp = I915_READ(reg);
3536                 temp &= ~FDI_LINK_TRAIN_AUTO;
3537                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3538                 temp &= ~FDI_RX_ENABLE;
3539                 I915_WRITE(reg, temp);
3540
3541                 /* enable CPU FDI TX and PCH FDI RX */
3542                 reg = FDI_TX_CTL(pipe);
3543                 temp = I915_READ(reg);
3544                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3545                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3546                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3547                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3548                 temp |= snb_b_fdi_train_param[j/2];
3549                 temp |= FDI_COMPOSITE_SYNC;
3550                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3551
3552                 I915_WRITE(FDI_RX_MISC(pipe),
3553                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3554
3555                 reg = FDI_RX_CTL(pipe);
3556                 temp = I915_READ(reg);
3557                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3558                 temp |= FDI_COMPOSITE_SYNC;
3559                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3560
3561                 POSTING_READ(reg);
3562                 udelay(1); /* should be 0.5us */
3563
3564                 for (i = 0; i < 4; i++) {
3565                         reg = FDI_RX_IIR(pipe);
3566                         temp = I915_READ(reg);
3567                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3568
3569                         if (temp & FDI_RX_BIT_LOCK ||
3570                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3571                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3572                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3573                                               i);
3574                                 break;
3575                         }
3576                         udelay(1); /* should be 0.5us */
3577                 }
3578                 if (i == 4) {
3579                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3580                         continue;
3581                 }
3582
3583                 /* Train 2 */
3584                 reg = FDI_TX_CTL(pipe);
3585                 temp = I915_READ(reg);
3586                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3587                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3588                 I915_WRITE(reg, temp);
3589
3590                 reg = FDI_RX_CTL(pipe);
3591                 temp = I915_READ(reg);
3592                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3593                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3594                 I915_WRITE(reg, temp);
3595
3596                 POSTING_READ(reg);
3597                 udelay(2); /* should be 1.5us */
3598
3599                 for (i = 0; i < 4; i++) {
3600                         reg = FDI_RX_IIR(pipe);
3601                         temp = I915_READ(reg);
3602                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3603
3604                         if (temp & FDI_RX_SYMBOL_LOCK ||
3605                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3606                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3607                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3608                                               i);
3609                                 goto train_done;
3610                         }
3611                         udelay(2); /* should be 1.5us */
3612                 }
3613                 if (i == 4)
3614                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3615         }
3616
3617 train_done:
3618         DRM_DEBUG_KMS("FDI train done.\n");
3619 }
3620
3621 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3622 {
3623         struct drm_device *dev = intel_crtc->base.dev;
3624         struct drm_i915_private *dev_priv = dev->dev_private;
3625         int pipe = intel_crtc->pipe;
3626         i915_reg_t reg;
3627         u32 temp;
3628
3629         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3630         reg = FDI_RX_CTL(pipe);
3631         temp = I915_READ(reg);
3632         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3633         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3634         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3635         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3636
3637         POSTING_READ(reg);
3638         udelay(200);
3639
3640         /* Switch from Rawclk to PCDclk */
3641         temp = I915_READ(reg);
3642         I915_WRITE(reg, temp | FDI_PCDCLK);
3643
3644         POSTING_READ(reg);
3645         udelay(200);
3646
3647         /* Enable CPU FDI TX PLL, always on for Ironlake */
3648         reg = FDI_TX_CTL(pipe);
3649         temp = I915_READ(reg);
3650         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3651                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3652
3653                 POSTING_READ(reg);
3654                 udelay(100);
3655         }
3656 }
3657
3658 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3659 {
3660         struct drm_device *dev = intel_crtc->base.dev;
3661         struct drm_i915_private *dev_priv = dev->dev_private;
3662         int pipe = intel_crtc->pipe;
3663         i915_reg_t reg;
3664         u32 temp;
3665
3666         /* Switch from PCDclk to Rawclk */
3667         reg = FDI_RX_CTL(pipe);
3668         temp = I915_READ(reg);
3669         I915_WRITE(reg, temp & ~FDI_PCDCLK);
3670
3671         /* Disable CPU FDI TX PLL */
3672         reg = FDI_TX_CTL(pipe);
3673         temp = I915_READ(reg);
3674         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3675
3676         POSTING_READ(reg);
3677         udelay(100);
3678
3679         reg = FDI_RX_CTL(pipe);
3680         temp = I915_READ(reg);
3681         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3682
3683         /* Wait for the clocks to turn off. */
3684         POSTING_READ(reg);
3685         udelay(100);
3686 }
3687
3688 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3689 {
3690         struct drm_device *dev = crtc->dev;
3691         struct drm_i915_private *dev_priv = dev->dev_private;
3692         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3693         int pipe = intel_crtc->pipe;
3694         i915_reg_t reg;
3695         u32 temp;
3696
3697         /* disable CPU FDI tx and PCH FDI rx */
3698         reg = FDI_TX_CTL(pipe);
3699         temp = I915_READ(reg);
3700         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3701         POSTING_READ(reg);
3702
3703         reg = FDI_RX_CTL(pipe);
3704         temp = I915_READ(reg);
3705         temp &= ~(0x7 << 16);
3706         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3707         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3708
3709         POSTING_READ(reg);
3710         udelay(100);
3711
3712         /* Ironlake workaround, disable clock pointer after downing FDI */
3713         if (HAS_PCH_IBX(dev))
3714                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3715
3716         /* still set train pattern 1 */
3717         reg = FDI_TX_CTL(pipe);
3718         temp = I915_READ(reg);
3719         temp &= ~FDI_LINK_TRAIN_NONE;
3720         temp |= FDI_LINK_TRAIN_PATTERN_1;
3721         I915_WRITE(reg, temp);
3722
3723         reg = FDI_RX_CTL(pipe);
3724         temp = I915_READ(reg);
3725         if (HAS_PCH_CPT(dev)) {
3726                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3727                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3728         } else {
3729                 temp &= ~FDI_LINK_TRAIN_NONE;
3730                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3731         }
3732         /* BPC in FDI rx is consistent with that in PIPECONF */
3733         temp &= ~(0x07 << 16);
3734         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3735         I915_WRITE(reg, temp);
3736
3737         POSTING_READ(reg);
3738         udelay(100);
3739 }
3740
3741 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3742 {
3743         struct intel_crtc *crtc;
3744
3745         /* Note that we don't need to be called with mode_config.lock here
3746          * as our list of CRTC objects is static for the lifetime of the
3747          * device and so cannot disappear as we iterate. Similarly, we can
3748          * happily treat the predicates as racy, atomic checks as userspace
3749          * cannot claim and pin a new fb without at least acquring the
3750          * struct_mutex and so serialising with us.
3751          */
3752         for_each_intel_crtc(dev, crtc) {
3753                 if (atomic_read(&crtc->unpin_work_count) == 0)
3754                         continue;
3755
3756                 if (!list_empty_careful(&crtc->flip_work))
3757                         intel_wait_for_vblank(dev, crtc->pipe);
3758
3759                 return true;
3760         }
3761
3762         return false;
3763 }
3764
3765 static void page_flip_completed(struct intel_crtc *intel_crtc, struct intel_flip_work *work)
3766 {
3767         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3768         struct drm_plane_state *new_plane_state;
3769         struct drm_plane *primary = intel_crtc->base.primary;
3770
3771         if (work->event)
3772                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
3773
3774         drm_crtc_vblank_put(&intel_crtc->base);
3775
3776         new_plane_state = &work->old_plane_state[0]->base;
3777         if (work->num_planes >= 1 &&
3778             new_plane_state->plane == primary &&
3779             new_plane_state->fb)
3780                 trace_i915_flip_complete(intel_crtc->plane,
3781                                          intel_fb_obj(new_plane_state->fb));
3782
3783         if (work->can_async_unpin) {
3784                 list_del_init(&work->head);
3785                 wake_up_all(&dev_priv->pending_flip_queue);
3786         }
3787
3788         queue_work(dev_priv->wq, &work->unpin_work);
3789 }
3790
3791 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3792 {
3793         struct drm_device *dev = crtc->dev;
3794         struct drm_i915_private *dev_priv = dev->dev_private;
3795         long ret;
3796
3797         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3798
3799         ret = wait_event_interruptible_timeout(
3800                                         dev_priv->pending_flip_queue,
3801                                         !intel_crtc_has_pending_flip(crtc),
3802                                         60*HZ);
3803
3804         if (ret < 0)
3805                 return ret;
3806
3807         WARN(ret == 0, "Stuck page flip\n");
3808
3809         return 0;
3810 }
3811
3812 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3813 {
3814         u32 temp;
3815
3816         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3817
3818         mutex_lock(&dev_priv->sb_lock);
3819
3820         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3821         temp |= SBI_SSCCTL_DISABLE;
3822         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3823
3824         mutex_unlock(&dev_priv->sb_lock);
3825 }
3826
3827 /* Program iCLKIP clock to the desired frequency */
3828 static void lpt_program_iclkip(struct drm_crtc *crtc)
3829 {
3830         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3831         int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3832         u32 divsel, phaseinc, auxdiv, phasedir = 0;
3833         u32 temp;
3834
3835         lpt_disable_iclkip(dev_priv);
3836
3837         /* The iCLK virtual clock root frequency is in MHz,
3838          * but the adjusted_mode->crtc_clock in in KHz. To get the
3839          * divisors, it is necessary to divide one by another, so we
3840          * convert the virtual clock precision to KHz here for higher
3841          * precision.
3842          */
3843         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3844                 u32 iclk_virtual_root_freq = 172800 * 1000;
3845                 u32 iclk_pi_range = 64;
3846                 u32 desired_divisor;
3847
3848                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3849                                                     clock << auxdiv);
3850                 divsel = (desired_divisor / iclk_pi_range) - 2;
3851                 phaseinc = desired_divisor % iclk_pi_range;
3852
3853                 /*
3854                  * Near 20MHz is a corner case which is
3855                  * out of range for the 7-bit divisor
3856                  */
3857                 if (divsel <= 0x7f)
3858                         break;
3859         }
3860
3861         /* This should not happen with any sane values */
3862         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3863                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3864         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3865                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3866
3867         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3868                         clock,
3869                         auxdiv,
3870                         divsel,
3871                         phasedir,
3872                         phaseinc);
3873
3874         mutex_lock(&dev_priv->sb_lock);
3875
3876         /* Program SSCDIVINTPHASE6 */
3877         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3878         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3879         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3880         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3881         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3882         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3883         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3884         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3885
3886         /* Program SSCAUXDIV */
3887         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3888         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3889         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3890         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3891
3892         /* Enable modulator and associated divider */
3893         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3894         temp &= ~SBI_SSCCTL_DISABLE;
3895         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3896
3897         mutex_unlock(&dev_priv->sb_lock);
3898
3899         /* Wait for initialization time */
3900         udelay(24);
3901
3902         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3903 }
3904
3905 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3906 {
3907         u32 divsel, phaseinc, auxdiv;
3908         u32 iclk_virtual_root_freq = 172800 * 1000;
3909         u32 iclk_pi_range = 64;
3910         u32 desired_divisor;
3911         u32 temp;
3912
3913         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3914                 return 0;
3915
3916         mutex_lock(&dev_priv->sb_lock);
3917
3918         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3919         if (temp & SBI_SSCCTL_DISABLE) {
3920                 mutex_unlock(&dev_priv->sb_lock);
3921                 return 0;
3922         }
3923
3924         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3925         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3926                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3927         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3928                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3929
3930         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3931         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3932                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3933
3934         mutex_unlock(&dev_priv->sb_lock);
3935
3936         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3937
3938         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3939                                  desired_divisor << auxdiv);
3940 }
3941
3942 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3943                                                 enum pipe pch_transcoder)
3944 {
3945         struct drm_device *dev = crtc->base.dev;
3946         struct drm_i915_private *dev_priv = dev->dev_private;
3947         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3948
3949         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3950                    I915_READ(HTOTAL(cpu_transcoder)));
3951         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3952                    I915_READ(HBLANK(cpu_transcoder)));
3953         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3954                    I915_READ(HSYNC(cpu_transcoder)));
3955
3956         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3957                    I915_READ(VTOTAL(cpu_transcoder)));
3958         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3959                    I915_READ(VBLANK(cpu_transcoder)));
3960         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3961                    I915_READ(VSYNC(cpu_transcoder)));
3962         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3963                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3964 }
3965
3966 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3967 {
3968         struct drm_i915_private *dev_priv = dev->dev_private;
3969         uint32_t temp;
3970
3971         temp = I915_READ(SOUTH_CHICKEN1);
3972         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3973                 return;
3974
3975         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3976         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3977
3978         temp &= ~FDI_BC_BIFURCATION_SELECT;
3979         if (enable)
3980                 temp |= FDI_BC_BIFURCATION_SELECT;
3981
3982         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3983         I915_WRITE(SOUTH_CHICKEN1, temp);
3984         POSTING_READ(SOUTH_CHICKEN1);
3985 }
3986
3987 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3988 {
3989         struct drm_device *dev = intel_crtc->base.dev;
3990
3991         switch (intel_crtc->pipe) {
3992         case PIPE_A:
3993                 break;
3994         case PIPE_B:
3995                 if (intel_crtc->config->fdi_lanes > 2)
3996                         cpt_set_fdi_bc_bifurcation(dev, false);
3997                 else
3998                         cpt_set_fdi_bc_bifurcation(dev, true);
3999
4000                 break;
4001         case PIPE_C:
4002                 cpt_set_fdi_bc_bifurcation(dev, true);
4003
4004                 break;
4005         default:
4006                 BUG();
4007         }
4008 }
4009
4010 /* Return which DP Port should be selected for Transcoder DP control */
4011 static enum port
4012 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4013 {
4014         struct drm_device *dev = crtc->dev;
4015         struct intel_encoder *encoder;
4016
4017         for_each_encoder_on_crtc(dev, crtc, encoder) {
4018                 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4019                     encoder->type == INTEL_OUTPUT_EDP)
4020                         return enc_to_dig_port(&encoder->base)->port;
4021         }
4022
4023         return -1;
4024 }
4025
4026 /*
4027  * Enable PCH resources required for PCH ports:
4028  *   - PCH PLLs
4029  *   - FDI training & RX/TX
4030  *   - update transcoder timings
4031  *   - DP transcoding bits
4032  *   - transcoder
4033  */
4034 static void ironlake_pch_enable(struct drm_crtc *crtc)
4035 {
4036         struct drm_device *dev = crtc->dev;
4037         struct drm_i915_private *dev_priv = dev->dev_private;
4038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4039         int pipe = intel_crtc->pipe;
4040         u32 temp;
4041
4042         assert_pch_transcoder_disabled(dev_priv, pipe);
4043
4044         if (IS_IVYBRIDGE(dev))
4045                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4046
4047         /* Write the TU size bits before fdi link training, so that error
4048          * detection works. */
4049         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4050                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4051
4052         /* For PCH output, training FDI link */
4053         dev_priv->display.fdi_link_train(crtc);
4054
4055         /* We need to program the right clock selection before writing the pixel
4056          * mutliplier into the DPLL. */
4057         if (HAS_PCH_CPT(dev)) {
4058                 u32 sel;
4059
4060                 temp = I915_READ(PCH_DPLL_SEL);
4061                 temp |= TRANS_DPLL_ENABLE(pipe);
4062                 sel = TRANS_DPLLB_SEL(pipe);
4063                 if (intel_crtc->config->shared_dpll ==
4064                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4065                         temp |= sel;
4066                 else
4067                         temp &= ~sel;
4068                 I915_WRITE(PCH_DPLL_SEL, temp);
4069         }
4070
4071         /* XXX: pch pll's can be enabled any time before we enable the PCH
4072          * transcoder, and we actually should do this to not upset any PCH
4073          * transcoder that already use the clock when we share it.
4074          *
4075          * Note that enable_shared_dpll tries to do the right thing, but
4076          * get_shared_dpll unconditionally resets the pll - we need that to have
4077          * the right LVDS enable sequence. */
4078         intel_enable_shared_dpll(intel_crtc);
4079
4080         /* set transcoder timing, panel must allow it */
4081         assert_panel_unlocked(dev_priv, pipe);
4082         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4083
4084         intel_fdi_normal_train(crtc);
4085
4086         /* For PCH DP, enable TRANS_DP_CTL */
4087         if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4088                 const struct drm_display_mode *adjusted_mode =
4089                         &intel_crtc->config->base.adjusted_mode;
4090                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4091                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4092                 temp = I915_READ(reg);
4093                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4094                           TRANS_DP_SYNC_MASK |
4095                           TRANS_DP_BPC_MASK);
4096                 temp |= TRANS_DP_OUTPUT_ENABLE;
4097                 temp |= bpc << 9; /* same format but at 11:9 */
4098
4099                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4100                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4101                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4102                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4103
4104                 switch (intel_trans_dp_port_sel(crtc)) {
4105                 case PORT_B:
4106                         temp |= TRANS_DP_PORT_SEL_B;
4107                         break;
4108                 case PORT_C:
4109                         temp |= TRANS_DP_PORT_SEL_C;
4110                         break;
4111                 case PORT_D:
4112                         temp |= TRANS_DP_PORT_SEL_D;
4113                         break;
4114                 default:
4115                         BUG();
4116                 }
4117
4118                 I915_WRITE(reg, temp);
4119         }
4120
4121         ironlake_enable_pch_transcoder(dev_priv, pipe);
4122 }
4123
4124 static void lpt_pch_enable(struct drm_crtc *crtc)
4125 {
4126         struct drm_device *dev = crtc->dev;
4127         struct drm_i915_private *dev_priv = dev->dev_private;
4128         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4129         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4130
4131         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4132
4133         lpt_program_iclkip(crtc);
4134
4135         /* Set transcoder timing. */
4136         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4137
4138         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4139 }
4140
4141 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4142 {
4143         struct drm_i915_private *dev_priv = dev->dev_private;
4144         i915_reg_t dslreg = PIPEDSL(pipe);
4145         u32 temp;
4146
4147         temp = I915_READ(dslreg);
4148         udelay(500);
4149         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4150                 if (wait_for(I915_READ(dslreg) != temp, 5))
4151                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4152         }
4153 }
4154
4155 static int
4156 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4157                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4158                   int src_w, int src_h, int dst_w, int dst_h)
4159 {
4160         struct intel_crtc_scaler_state *scaler_state =
4161                 &crtc_state->scaler_state;
4162         struct intel_crtc *intel_crtc =
4163                 to_intel_crtc(crtc_state->base.crtc);
4164         int need_scaling;
4165
4166         need_scaling = intel_rotation_90_or_270(rotation) ?
4167                 (src_h != dst_w || src_w != dst_h):
4168                 (src_w != dst_w || src_h != dst_h);
4169
4170         /*
4171          * if plane is being disabled or scaler is no more required or force detach
4172          *  - free scaler binded to this plane/crtc
4173          *  - in order to do this, update crtc->scaler_usage
4174          *
4175          * Here scaler state in crtc_state is set free so that
4176          * scaler can be assigned to other user. Actual register
4177          * update to free the scaler is done in plane/panel-fit programming.
4178          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4179          */
4180         if (force_detach || !need_scaling) {
4181                 if (*scaler_id >= 0) {
4182                         scaler_state->scaler_users &= ~(1 << scaler_user);
4183                         scaler_state->scalers[*scaler_id].in_use = 0;
4184
4185                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4186                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4187                                 intel_crtc->pipe, scaler_user, *scaler_id,
4188                                 scaler_state->scaler_users);
4189                         *scaler_id = -1;
4190                 }
4191                 return 0;
4192         }
4193
4194         /* range checks */
4195         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4196                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4197
4198                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4199                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4200                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4201                         "size is out of scaler range\n",
4202                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4203                 return -EINVAL;
4204         }
4205
4206         /* mark this plane as a scaler user in crtc_state */
4207         scaler_state->scaler_users |= (1 << scaler_user);
4208         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4209                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4210                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4211                 scaler_state->scaler_users);
4212
4213         return 0;
4214 }
4215
4216 /**
4217  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4218  *
4219  * @state: crtc's scaler state
4220  *
4221  * Return
4222  *     0 - scaler_usage updated successfully
4223  *    error - requested scaling cannot be supported or other error condition
4224  */
4225 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4226 {
4227         struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4228         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4229
4230         DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4231                       intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4232
4233         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4234                 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4235                 state->pipe_src_w, state->pipe_src_h,
4236                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4237 }
4238
4239 /**
4240  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4241  *
4242  * @state: crtc's scaler state
4243  * @plane_state: atomic plane state to update
4244  *
4245  * Return
4246  *     0 - scaler_usage updated successfully
4247  *    error - requested scaling cannot be supported or other error condition
4248  */
4249 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4250                                    struct intel_plane_state *plane_state)
4251 {
4252
4253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4254         struct intel_plane *intel_plane =
4255                 to_intel_plane(plane_state->base.plane);
4256         struct drm_framebuffer *fb = plane_state->base.fb;
4257         int ret;
4258
4259         bool force_detach = !fb || !plane_state->visible;
4260
4261         DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4262                       intel_plane->base.base.id, intel_crtc->pipe,
4263                       drm_plane_index(&intel_plane->base));
4264
4265         ret = skl_update_scaler(crtc_state, force_detach,
4266                                 drm_plane_index(&intel_plane->base),
4267                                 &plane_state->scaler_id,
4268                                 plane_state->base.rotation,
4269                                 drm_rect_width(&plane_state->src) >> 16,
4270                                 drm_rect_height(&plane_state->src) >> 16,
4271                                 drm_rect_width(&plane_state->dst),
4272                                 drm_rect_height(&plane_state->dst));
4273
4274         if (ret || plane_state->scaler_id < 0)
4275                 return ret;
4276
4277         /* check colorkey */
4278         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4279                 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4280                               intel_plane->base.base.id);
4281                 return -EINVAL;
4282         }
4283
4284         /* Check src format */
4285         switch (fb->pixel_format) {
4286         case DRM_FORMAT_RGB565:
4287         case DRM_FORMAT_XBGR8888:
4288         case DRM_FORMAT_XRGB8888:
4289         case DRM_FORMAT_ABGR8888:
4290         case DRM_FORMAT_ARGB8888:
4291         case DRM_FORMAT_XRGB2101010:
4292         case DRM_FORMAT_XBGR2101010:
4293         case DRM_FORMAT_YUYV:
4294         case DRM_FORMAT_YVYU:
4295         case DRM_FORMAT_UYVY:
4296         case DRM_FORMAT_VYUY:
4297                 break;
4298         default:
4299                 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4300                         intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4301                 return -EINVAL;
4302         }
4303
4304         return 0;
4305 }
4306
4307 static void skylake_scaler_disable(struct intel_crtc *crtc)
4308 {
4309         int i;
4310
4311         for (i = 0; i < crtc->num_scalers; i++)
4312                 skl_detach_scaler(crtc, i);
4313 }
4314
4315 static void skylake_pfit_enable(struct intel_crtc *crtc)
4316 {
4317         struct drm_device *dev = crtc->base.dev;
4318         struct drm_i915_private *dev_priv = dev->dev_private;
4319         int pipe = crtc->pipe;
4320         struct intel_crtc_scaler_state *scaler_state =
4321                 &crtc->config->scaler_state;
4322
4323         DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4324
4325         if (crtc->config->pch_pfit.enabled) {
4326                 int id;
4327
4328                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4329                         DRM_ERROR("Requesting pfit without getting a scaler first\n");
4330                         return;
4331                 }
4332
4333                 id = scaler_state->scaler_id;
4334                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4335                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4336                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4337                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4338
4339                 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4340         }
4341 }
4342
4343 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4344 {
4345         struct drm_device *dev = crtc->base.dev;
4346         struct drm_i915_private *dev_priv = dev->dev_private;
4347         int pipe = crtc->pipe;
4348
4349         if (crtc->config->pch_pfit.enabled) {
4350                 /* Force use of hard-coded filter coefficients
4351                  * as some pre-programmed values are broken,
4352                  * e.g. x201.
4353                  */
4354                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4355                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4356                                                  PF_PIPE_SEL_IVB(pipe));
4357                 else
4358                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4359                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4360                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4361         }
4362 }
4363
4364 void hsw_enable_ips(struct intel_crtc *crtc)
4365 {
4366         struct drm_device *dev = crtc->base.dev;
4367         struct drm_i915_private *dev_priv = dev->dev_private;
4368
4369         if (!crtc->config->ips_enabled)
4370                 return;
4371
4372         /*
4373          * We can only enable IPS after we enable a plane and wait for a vblank
4374          * This function is called from post_plane_update, which is run after
4375          * a vblank wait.
4376          */
4377
4378         assert_plane_enabled(dev_priv, crtc->plane);
4379         if (IS_BROADWELL(dev)) {
4380                 mutex_lock(&dev_priv->rps.hw_lock);
4381                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4382                 mutex_unlock(&dev_priv->rps.hw_lock);
4383                 /* Quoting Art Runyan: "its not safe to expect any particular
4384                  * value in IPS_CTL bit 31 after enabling IPS through the
4385                  * mailbox." Moreover, the mailbox may return a bogus state,
4386                  * so we need to just enable it and continue on.
4387                  */
4388         } else {
4389                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4390                 /* The bit only becomes 1 in the next vblank, so this wait here
4391                  * is essentially intel_wait_for_vblank. If we don't have this
4392                  * and don't wait for vblanks until the end of crtc_enable, then
4393                  * the HW state readout code will complain that the expected
4394                  * IPS_CTL value is not the one we read. */
4395                 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4396                         DRM_ERROR("Timed out waiting for IPS enable\n");
4397         }
4398 }
4399
4400 void hsw_disable_ips(struct intel_crtc *crtc)
4401 {
4402         struct drm_device *dev = crtc->base.dev;
4403         struct drm_i915_private *dev_priv = dev->dev_private;
4404
4405         if (!crtc->config->ips_enabled)
4406                 return;
4407
4408         assert_plane_enabled(dev_priv, crtc->plane);
4409         if (IS_BROADWELL(dev)) {
4410                 mutex_lock(&dev_priv->rps.hw_lock);
4411                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4412                 mutex_unlock(&dev_priv->rps.hw_lock);
4413                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4414                 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4415                         DRM_ERROR("Timed out waiting for IPS disable\n");
4416         } else {
4417                 I915_WRITE(IPS_CTL, 0);
4418                 POSTING_READ(IPS_CTL);
4419         }
4420
4421         /* We need to wait for a vblank before we can disable the plane. */
4422         intel_wait_for_vblank(dev, crtc->pipe);
4423 }
4424
4425 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4426 {
4427         if (intel_crtc->overlay) {
4428                 struct drm_device *dev = intel_crtc->base.dev;
4429                 struct drm_i915_private *dev_priv = dev->dev_private;
4430
4431                 mutex_lock(&dev->struct_mutex);
4432                 dev_priv->mm.interruptible = false;
4433                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4434                 dev_priv->mm.interruptible = true;
4435                 mutex_unlock(&dev->struct_mutex);
4436         }
4437
4438         /* Let userspace switch the overlay on again. In most cases userspace
4439          * has to recompute where to put it anyway.
4440          */
4441 }
4442
4443 /**
4444  * intel_post_enable_primary - Perform operations after enabling primary plane
4445  * @crtc: the CRTC whose primary plane was just enabled
4446  *
4447  * Performs potentially sleeping operations that must be done after the primary
4448  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4449  * called due to an explicit primary plane update, or due to an implicit
4450  * re-enable that is caused when a sprite plane is updated to no longer
4451  * completely hide the primary plane.
4452  */
4453 static void
4454 intel_post_enable_primary(struct drm_crtc *crtc)
4455 {
4456         struct drm_device *dev = crtc->dev;
4457         struct drm_i915_private *dev_priv = dev->dev_private;
4458         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4459         int pipe = intel_crtc->pipe;
4460
4461         /*
4462          * FIXME IPS should be fine as long as one plane is
4463          * enabled, but in practice it seems to have problems
4464          * when going from primary only to sprite only and vice
4465          * versa.
4466          */
4467         hsw_enable_ips(intel_crtc);
4468
4469         /*
4470          * Gen2 reports pipe underruns whenever all planes are disabled.
4471          * So don't enable underrun reporting before at least some planes
4472          * are enabled.
4473          * FIXME: Need to fix the logic to work when we turn off all planes
4474          * but leave the pipe running.
4475          */
4476         if (IS_GEN2(dev))
4477                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4478
4479         /* Underruns don't always raise interrupts, so check manually. */
4480         intel_check_cpu_fifo_underruns(dev_priv);
4481         intel_check_pch_fifo_underruns(dev_priv);
4482 }
4483
4484 /* FIXME move all this to pre_plane_update() with proper state tracking */
4485 static void
4486 intel_pre_disable_primary(struct drm_crtc *crtc)
4487 {
4488         struct drm_device *dev = crtc->dev;
4489         struct drm_i915_private *dev_priv = dev->dev_private;
4490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4491         int pipe = intel_crtc->pipe;
4492
4493         /*
4494          * Gen2 reports pipe underruns whenever all planes are disabled.
4495          * So diasble underrun reporting before all the planes get disabled.
4496          * FIXME: Need to fix the logic to work when we turn off all planes
4497          * but leave the pipe running.
4498          */
4499         if (IS_GEN2(dev))
4500                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4501
4502         /*
4503          * FIXME IPS should be fine as long as one plane is
4504          * enabled, but in practice it seems to have problems
4505          * when going from primary only to sprite only and vice
4506          * versa.
4507          */
4508         hsw_disable_ips(intel_crtc);
4509 }
4510
4511 /* FIXME get rid of this and use pre_plane_update */
4512 static void
4513 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4514 {
4515         struct drm_device *dev = crtc->dev;
4516         struct drm_i915_private *dev_priv = dev->dev_private;
4517         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4518         int pipe = intel_crtc->pipe;
4519
4520         intel_pre_disable_primary(crtc);
4521
4522         /*
4523          * Vblank time updates from the shadow to live plane control register
4524          * are blocked if the memory self-refresh mode is active at that
4525          * moment. So to make sure the plane gets truly disabled, disable
4526          * first the self-refresh mode. The self-refresh enable bit in turn
4527          * will be checked/applied by the HW only at the next frame start
4528          * event which is after the vblank start event, so we need to have a
4529          * wait-for-vblank between disabling the plane and the pipe.
4530          */
4531         if (HAS_GMCH_DISPLAY(dev)) {
4532                 intel_set_memory_cxsr(dev_priv, false);
4533                 dev_priv->wm.vlv.cxsr = false;
4534                 intel_wait_for_vblank(dev, pipe);
4535         }
4536 }
4537
4538 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4539 {
4540         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4541         struct drm_device *dev = crtc->base.dev;
4542         struct drm_i915_private *dev_priv = dev->dev_private;
4543         struct intel_crtc_state *pipe_config =
4544                 to_intel_crtc_state(crtc->base.state);
4545         struct drm_atomic_state *old_state = old_crtc_state->base.state;
4546         struct drm_plane *primary = crtc->base.primary;
4547         struct drm_plane_state *old_pri_state =
4548                 drm_atomic_get_existing_plane_state(old_state, primary);
4549         bool modeset = needs_modeset(&pipe_config->base);
4550
4551         if (old_pri_state) {
4552                 struct intel_plane_state *primary_state =
4553                         to_intel_plane_state(primary->state);
4554                 struct intel_plane_state *old_primary_state =
4555                         to_intel_plane_state(old_pri_state);
4556
4557                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
4558
4559                 if (old_primary_state->visible &&
4560                     (modeset || !primary_state->visible))
4561                         intel_pre_disable_primary(&crtc->base);
4562         }
4563
4564         if (pipe_config->disable_cxsr) {
4565                 crtc->wm.cxsr_allowed = false;
4566
4567                 /*
4568                  * Vblank time updates from the shadow to live plane control register
4569                  * are blocked if the memory self-refresh mode is active at that
4570                  * moment. So to make sure the plane gets truly disabled, disable
4571                  * first the self-refresh mode. The self-refresh enable bit in turn
4572                  * will be checked/applied by the HW only at the next frame start
4573                  * event which is after the vblank start event, so we need to have a
4574                  * wait-for-vblank between disabling the plane and the pipe.
4575                  */
4576                 if (old_crtc_state->base.active) {
4577                         intel_set_memory_cxsr(dev_priv, false);
4578                         dev_priv->wm.vlv.cxsr = false;
4579                         intel_wait_for_vblank(dev, crtc->pipe);
4580                 }
4581         }
4582
4583         /*
4584          * IVB workaround: must disable low power watermarks for at least
4585          * one frame before enabling scaling.  LP watermarks can be re-enabled
4586          * when scaling is disabled.
4587          *
4588          * WaCxSRDisabledForSpriteScaling:ivb
4589          */
4590         if (pipe_config->disable_lp_wm) {
4591                 ilk_disable_lp_wm(dev);
4592                 intel_wait_for_vblank(dev, crtc->pipe);
4593         }
4594
4595         /*
4596          * If we're doing a modeset, we're done.  No need to do any pre-vblank
4597          * watermark programming here.
4598          */
4599         if (needs_modeset(&pipe_config->base))
4600                 return;
4601
4602         /*
4603          * For platforms that support atomic watermarks, program the
4604          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
4605          * will be the intermediate values that are safe for both pre- and
4606          * post- vblank; when vblank happens, the 'active' values will be set
4607          * to the final 'target' values and we'll do this again to get the
4608          * optimal watermarks.  For gen9+ platforms, the values we program here
4609          * will be the final target values which will get automatically latched
4610          * at vblank time; no further programming will be necessary.
4611          *
4612          * If a platform hasn't been transitioned to atomic watermarks yet,
4613          * we'll continue to update watermarks the old way, if flags tell
4614          * us to.
4615          */
4616         if (dev_priv->display.initial_watermarks != NULL)
4617                 dev_priv->display.initial_watermarks(pipe_config);
4618         else if (pipe_config->update_wm_pre)
4619                 intel_update_watermarks(&crtc->base);
4620 }
4621
4622 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4623 {
4624         struct drm_device *dev = crtc->dev;
4625         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4626         struct drm_plane *p;
4627         int pipe = intel_crtc->pipe;
4628
4629         intel_crtc_dpms_overlay_disable(intel_crtc);
4630
4631         drm_for_each_plane_mask(p, dev, plane_mask)
4632                 to_intel_plane(p)->disable_plane(p, crtc);
4633
4634         /*
4635          * FIXME: Once we grow proper nuclear flip support out of this we need
4636          * to compute the mask of flip planes precisely. For the time being
4637          * consider this a flip to a NULL plane.
4638          */
4639         intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4640 }
4641
4642 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4643 {
4644         struct drm_device *dev = crtc->dev;
4645         struct drm_i915_private *dev_priv = dev->dev_private;
4646         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4647         struct intel_encoder *encoder;
4648         int pipe = intel_crtc->pipe;
4649         struct intel_crtc_state *pipe_config =
4650                 to_intel_crtc_state(crtc->state);
4651
4652         if (WARN_ON(intel_crtc->active))
4653                 return;
4654
4655         /*
4656          * Sometimes spurious CPU pipe underruns happen during FDI
4657          * training, at least with VGA+HDMI cloning. Suppress them.
4658          *
4659          * On ILK we get an occasional spurious CPU pipe underruns
4660          * between eDP port A enable and vdd enable. Also PCH port
4661          * enable seems to result in the occasional CPU pipe underrun.
4662          *
4663          * Spurious PCH underruns also occur during PCH enabling.
4664          */
4665         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
4666                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4667         if (intel_crtc->config->has_pch_encoder)
4668                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4669
4670         if (intel_crtc->config->has_pch_encoder)
4671                 intel_prepare_shared_dpll(intel_crtc);
4672
4673         if (intel_crtc->config->has_dp_encoder)
4674                 intel_dp_set_m_n(intel_crtc, M1_N1);
4675
4676         intel_set_pipe_timings(intel_crtc);
4677         intel_set_pipe_src_size(intel_crtc);
4678
4679         if (intel_crtc->config->has_pch_encoder) {
4680                 intel_cpu_transcoder_set_m_n(intel_crtc,
4681                                      &intel_crtc->config->fdi_m_n, NULL);
4682         }
4683
4684         ironlake_set_pipeconf(crtc);
4685
4686         intel_crtc->active = true;
4687
4688         for_each_encoder_on_crtc(dev, crtc, encoder)
4689                 if (encoder->pre_enable)
4690                         encoder->pre_enable(encoder);
4691
4692         if (intel_crtc->config->has_pch_encoder) {
4693                 /* Note: FDI PLL enabling _must_ be done before we enable the
4694                  * cpu pipes, hence this is separate from all the other fdi/pch
4695                  * enabling. */
4696                 ironlake_fdi_pll_enable(intel_crtc);
4697         } else {
4698                 assert_fdi_tx_disabled(dev_priv, pipe);
4699                 assert_fdi_rx_disabled(dev_priv, pipe);
4700         }
4701
4702         ironlake_pfit_enable(intel_crtc);
4703
4704         /*
4705          * On ILK+ LUT must be loaded before the pipe is running but with
4706          * clocks enabled
4707          */
4708         intel_color_load_luts(&pipe_config->base);
4709
4710         if (dev_priv->display.initial_watermarks != NULL)
4711                 dev_priv->display.initial_watermarks(intel_crtc->config);
4712         intel_enable_pipe(intel_crtc);
4713
4714         if (intel_crtc->config->has_pch_encoder)
4715                 ironlake_pch_enable(crtc);
4716
4717         assert_vblank_disabled(crtc);
4718         drm_crtc_vblank_on(crtc);
4719
4720         for_each_encoder_on_crtc(dev, crtc, encoder)
4721                 encoder->enable(encoder);
4722
4723         if (HAS_PCH_CPT(dev))
4724                 cpt_verify_modeset(dev, intel_crtc->pipe);
4725
4726         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4727         if (intel_crtc->config->has_pch_encoder)
4728                 intel_wait_for_vblank(dev, pipe);
4729         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4730         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4731 }
4732
4733 /* IPS only exists on ULT machines and is tied to pipe A. */
4734 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4735 {
4736         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4737 }
4738
4739 static void haswell_crtc_enable(struct drm_crtc *crtc)
4740 {
4741         struct drm_device *dev = crtc->dev;
4742         struct drm_i915_private *dev_priv = dev->dev_private;
4743         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4744         struct intel_encoder *encoder;
4745         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4746         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4747         struct intel_crtc_state *pipe_config =
4748                 to_intel_crtc_state(crtc->state);
4749
4750         if (WARN_ON(intel_crtc->active))
4751                 return;
4752
4753         if (intel_crtc->config->has_pch_encoder)
4754                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4755                                                       false);
4756
4757         if (intel_crtc->config->shared_dpll)
4758                 intel_enable_shared_dpll(intel_crtc);
4759
4760         if (intel_crtc->config->has_dp_encoder)
4761                 intel_dp_set_m_n(intel_crtc, M1_N1);
4762
4763         if (!intel_crtc->config->has_dsi_encoder)
4764                 intel_set_pipe_timings(intel_crtc);
4765
4766         intel_set_pipe_src_size(intel_crtc);
4767
4768         if (cpu_transcoder != TRANSCODER_EDP &&
4769             !transcoder_is_dsi(cpu_transcoder)) {
4770                 I915_WRITE(PIPE_MULT(cpu_transcoder),
4771                            intel_crtc->config->pixel_multiplier - 1);
4772         }
4773
4774         if (intel_crtc->config->has_pch_encoder) {
4775                 intel_cpu_transcoder_set_m_n(intel_crtc,
4776                                      &intel_crtc->config->fdi_m_n, NULL);
4777         }
4778
4779         if (!intel_crtc->config->has_dsi_encoder)
4780                 haswell_set_pipeconf(crtc);
4781
4782         haswell_set_pipemisc(crtc);
4783
4784         intel_color_set_csc(&pipe_config->base);
4785
4786         intel_crtc->active = true;
4787
4788         if (intel_crtc->config->has_pch_encoder)
4789                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4790         else
4791                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4792
4793         for_each_encoder_on_crtc(dev, crtc, encoder) {
4794                 if (encoder->pre_enable)
4795                         encoder->pre_enable(encoder);
4796         }
4797
4798         if (intel_crtc->config->has_pch_encoder)
4799                 dev_priv->display.fdi_link_train(crtc);
4800
4801         if (!intel_crtc->config->has_dsi_encoder)
4802                 intel_ddi_enable_pipe_clock(intel_crtc);
4803
4804         if (INTEL_INFO(dev)->gen >= 9)
4805                 skylake_pfit_enable(intel_crtc);
4806         else
4807                 ironlake_pfit_enable(intel_crtc);
4808
4809         /*
4810          * On ILK+ LUT must be loaded before the pipe is running but with
4811          * clocks enabled
4812          */
4813         intel_color_load_luts(&pipe_config->base);
4814
4815         intel_ddi_set_pipe_settings(crtc);
4816         if (!intel_crtc->config->has_dsi_encoder)
4817                 intel_ddi_enable_transcoder_func(crtc);
4818
4819         if (dev_priv->display.initial_watermarks != NULL)
4820                 dev_priv->display.initial_watermarks(pipe_config);
4821         else
4822                 intel_update_watermarks(crtc);
4823
4824         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4825         if (!intel_crtc->config->has_dsi_encoder)
4826                 intel_enable_pipe(intel_crtc);
4827
4828         if (intel_crtc->config->has_pch_encoder)
4829                 lpt_pch_enable(crtc);
4830
4831         if (intel_crtc->config->dp_encoder_is_mst)
4832                 intel_ddi_set_vc_payload_alloc(crtc, true);
4833
4834         assert_vblank_disabled(crtc);
4835         drm_crtc_vblank_on(crtc);
4836
4837         for_each_encoder_on_crtc(dev, crtc, encoder) {
4838                 encoder->enable(encoder);
4839                 intel_opregion_notify_encoder(encoder, true);
4840         }
4841
4842         if (intel_crtc->config->has_pch_encoder) {
4843                 intel_wait_for_vblank(dev, pipe);
4844                 intel_wait_for_vblank(dev, pipe);
4845                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4846                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4847                                                       true);
4848         }
4849
4850         /* If we change the relative order between pipe/planes enabling, we need
4851          * to change the workaround. */
4852         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4853         if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4854                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4855                 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4856         }
4857 }
4858
4859 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4860 {
4861         struct drm_device *dev = crtc->base.dev;
4862         struct drm_i915_private *dev_priv = dev->dev_private;
4863         int pipe = crtc->pipe;
4864
4865         /* To avoid upsetting the power well on haswell only disable the pfit if
4866          * it's in use. The hw state code will make sure we get this right. */
4867         if (force || crtc->config->pch_pfit.enabled) {
4868                 I915_WRITE(PF_CTL(pipe), 0);
4869                 I915_WRITE(PF_WIN_POS(pipe), 0);
4870                 I915_WRITE(PF_WIN_SZ(pipe), 0);
4871         }
4872 }
4873
4874 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4875 {
4876         struct drm_device *dev = crtc->dev;
4877         struct drm_i915_private *dev_priv = dev->dev_private;
4878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4879         struct intel_encoder *encoder;
4880         int pipe = intel_crtc->pipe;
4881
4882         /*
4883          * Sometimes spurious CPU pipe underruns happen when the
4884          * pipe is already disabled, but FDI RX/TX is still enabled.
4885          * Happens at least with VGA+HDMI cloning. Suppress them.
4886          */
4887         if (intel_crtc->config->has_pch_encoder) {
4888                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4889                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4890         }
4891
4892         for_each_encoder_on_crtc(dev, crtc, encoder)
4893                 encoder->disable(encoder);
4894
4895         drm_crtc_vblank_off(crtc);
4896         assert_vblank_disabled(crtc);
4897
4898         intel_disable_pipe(intel_crtc);
4899
4900         ironlake_pfit_disable(intel_crtc, false);
4901
4902         if (intel_crtc->config->has_pch_encoder)
4903                 ironlake_fdi_disable(crtc);
4904
4905         for_each_encoder_on_crtc(dev, crtc, encoder)
4906                 if (encoder->post_disable)
4907                         encoder->post_disable(encoder);
4908
4909         if (intel_crtc->config->has_pch_encoder) {
4910                 ironlake_disable_pch_transcoder(dev_priv, pipe);
4911
4912                 if (HAS_PCH_CPT(dev)) {
4913                         i915_reg_t reg;
4914                         u32 temp;
4915
4916                         /* disable TRANS_DP_CTL */
4917                         reg = TRANS_DP_CTL(pipe);
4918                         temp = I915_READ(reg);
4919                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4920                                   TRANS_DP_PORT_SEL_MASK);
4921                         temp |= TRANS_DP_PORT_SEL_NONE;
4922                         I915_WRITE(reg, temp);
4923
4924                         /* disable DPLL_SEL */
4925                         temp = I915_READ(PCH_DPLL_SEL);
4926                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4927                         I915_WRITE(PCH_DPLL_SEL, temp);
4928                 }
4929
4930                 ironlake_fdi_pll_disable(intel_crtc);
4931         }
4932
4933         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4934         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4935 }
4936
4937 static void haswell_crtc_disable(struct drm_crtc *crtc)
4938 {
4939         struct drm_device *dev = crtc->dev;
4940         struct drm_i915_private *dev_priv = dev->dev_private;
4941         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4942         struct intel_encoder *encoder;
4943         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4944
4945         if (intel_crtc->config->has_pch_encoder)
4946                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4947                                                       false);
4948
4949         for_each_encoder_on_crtc(dev, crtc, encoder) {
4950                 intel_opregion_notify_encoder(encoder, false);
4951                 encoder->disable(encoder);
4952         }
4953
4954         drm_crtc_vblank_off(crtc);
4955         assert_vblank_disabled(crtc);
4956
4957         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4958         if (!intel_crtc->config->has_dsi_encoder)
4959                 intel_disable_pipe(intel_crtc);
4960
4961         if (intel_crtc->config->dp_encoder_is_mst)
4962                 intel_ddi_set_vc_payload_alloc(crtc, false);
4963
4964         if (!intel_crtc->config->has_dsi_encoder)
4965                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4966
4967         if (INTEL_INFO(dev)->gen >= 9)
4968                 skylake_scaler_disable(intel_crtc);
4969         else
4970                 ironlake_pfit_disable(intel_crtc, false);
4971
4972         if (!intel_crtc->config->has_dsi_encoder)
4973                 intel_ddi_disable_pipe_clock(intel_crtc);
4974
4975         for_each_encoder_on_crtc(dev, crtc, encoder)
4976                 if (encoder->post_disable)
4977                         encoder->post_disable(encoder);
4978
4979         if (intel_crtc->config->has_pch_encoder) {
4980                 lpt_disable_pch_transcoder(dev_priv);
4981                 lpt_disable_iclkip(dev_priv);
4982                 intel_ddi_fdi_disable(crtc);
4983
4984                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4985                                                       true);
4986         }
4987 }
4988
4989 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4990 {
4991         struct drm_device *dev = crtc->base.dev;
4992         struct drm_i915_private *dev_priv = dev->dev_private;
4993         struct intel_crtc_state *pipe_config = crtc->config;
4994
4995         if (!pipe_config->gmch_pfit.control)
4996                 return;
4997
4998         /*
4999          * The panel fitter should only be adjusted whilst the pipe is disabled,
5000          * according to register description and PRM.
5001          */
5002         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5003         assert_pipe_disabled(dev_priv, crtc->pipe);
5004
5005         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5006         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5007
5008         /* Border color in case we don't scale up to the full screen. Black by
5009          * default, change to something else for debugging. */
5010         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5011 }
5012
5013 static enum intel_display_power_domain port_to_power_domain(enum port port)
5014 {
5015         switch (port) {
5016         case PORT_A:
5017                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5018         case PORT_B:
5019                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5020         case PORT_C:
5021                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5022         case PORT_D:
5023                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5024         case PORT_E:
5025                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5026         default:
5027                 MISSING_CASE(port);
5028                 return POWER_DOMAIN_PORT_OTHER;
5029         }
5030 }
5031
5032 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5033 {
5034         switch (port) {
5035         case PORT_A:
5036                 return POWER_DOMAIN_AUX_A;
5037         case PORT_B:
5038                 return POWER_DOMAIN_AUX_B;
5039         case PORT_C:
5040                 return POWER_DOMAIN_AUX_C;
5041         case PORT_D:
5042                 return POWER_DOMAIN_AUX_D;
5043         case PORT_E:
5044                 /* FIXME: Check VBT for actual wiring of PORT E */
5045                 return POWER_DOMAIN_AUX_D;
5046         default:
5047                 MISSING_CASE(port);
5048                 return POWER_DOMAIN_AUX_A;
5049         }
5050 }
5051
5052 enum intel_display_power_domain
5053 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5054 {
5055         struct drm_device *dev = intel_encoder->base.dev;
5056         struct intel_digital_port *intel_dig_port;
5057
5058         switch (intel_encoder->type) {
5059         case INTEL_OUTPUT_UNKNOWN:
5060                 /* Only DDI platforms should ever use this output type */
5061                 WARN_ON_ONCE(!HAS_DDI(dev));
5062         case INTEL_OUTPUT_DISPLAYPORT:
5063         case INTEL_OUTPUT_HDMI:
5064         case INTEL_OUTPUT_EDP:
5065                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5066                 return port_to_power_domain(intel_dig_port->port);
5067         case INTEL_OUTPUT_DP_MST:
5068                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5069                 return port_to_power_domain(intel_dig_port->port);
5070         case INTEL_OUTPUT_ANALOG:
5071                 return POWER_DOMAIN_PORT_CRT;
5072         case INTEL_OUTPUT_DSI:
5073                 return POWER_DOMAIN_PORT_DSI;
5074         default:
5075                 return POWER_DOMAIN_PORT_OTHER;
5076         }
5077 }
5078
5079 enum intel_display_power_domain
5080 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5081 {
5082         struct drm_device *dev = intel_encoder->base.dev;
5083         struct intel_digital_port *intel_dig_port;
5084
5085         switch (intel_encoder->type) {
5086         case INTEL_OUTPUT_UNKNOWN:
5087         case INTEL_OUTPUT_HDMI:
5088                 /*
5089                  * Only DDI platforms should ever use these output types.
5090                  * We can get here after the HDMI detect code has already set
5091                  * the type of the shared encoder. Since we can't be sure
5092                  * what's the status of the given connectors, play safe and
5093                  * run the DP detection too.
5094                  */
5095                 WARN_ON_ONCE(!HAS_DDI(dev));
5096         case INTEL_OUTPUT_DISPLAYPORT:
5097         case INTEL_OUTPUT_EDP:
5098                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5099                 return port_to_aux_power_domain(intel_dig_port->port);
5100         case INTEL_OUTPUT_DP_MST:
5101                 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5102                 return port_to_aux_power_domain(intel_dig_port->port);
5103         default:
5104                 MISSING_CASE(intel_encoder->type);
5105                 return POWER_DOMAIN_AUX_A;
5106         }
5107 }
5108
5109 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5110                                             struct intel_crtc_state *crtc_state)
5111 {
5112         struct drm_device *dev = crtc->dev;
5113         struct drm_encoder *encoder;
5114         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5115         enum pipe pipe = intel_crtc->pipe;
5116         unsigned long mask;
5117         enum transcoder transcoder = crtc_state->cpu_transcoder;
5118
5119         if (!crtc_state->base.active)
5120                 return 0;
5121
5122         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5123         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5124         if (crtc_state->pch_pfit.enabled ||
5125             crtc_state->pch_pfit.force_thru)
5126                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5127
5128         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5129                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5130
5131                 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5132         }
5133
5134         if (crtc_state->shared_dpll)
5135                 mask |= BIT(POWER_DOMAIN_PLLS);
5136
5137         return mask;
5138 }
5139
5140 static unsigned long
5141 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5142                                struct intel_crtc_state *crtc_state)
5143 {
5144         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5145         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5146         enum intel_display_power_domain domain;
5147         unsigned long domains, new_domains, old_domains, ms_domain = 0;
5148
5149         old_domains = intel_crtc->enabled_power_domains;
5150         intel_crtc->enabled_power_domains = new_domains =
5151                 get_crtc_power_domains(crtc, crtc_state);
5152
5153         if (needs_modeset(&crtc_state->base))
5154                 ms_domain = BIT(POWER_DOMAIN_MODESET);
5155
5156         domains = (new_domains & ~old_domains) | ms_domain;
5157
5158         for_each_power_domain(domain, domains)
5159                 intel_display_power_get(dev_priv, domain);
5160
5161         return (old_domains & ~new_domains) | ms_domain;
5162 }
5163
5164 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5165                                       unsigned long domains)
5166 {
5167         enum intel_display_power_domain domain;
5168
5169         for_each_power_domain(domain, domains)
5170                 intel_display_power_put(dev_priv, domain);
5171 }
5172
5173 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5174 {
5175         int max_cdclk_freq = dev_priv->max_cdclk_freq;
5176
5177         if (INTEL_INFO(dev_priv)->gen >= 9 ||
5178             IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5179                 return max_cdclk_freq;
5180         else if (IS_CHERRYVIEW(dev_priv))
5181                 return max_cdclk_freq*95/100;
5182         else if (INTEL_INFO(dev_priv)->gen < 4)
5183                 return 2*max_cdclk_freq*90/100;
5184         else
5185                 return max_cdclk_freq*90/100;
5186 }
5187
5188 static int skl_calc_cdclk(int max_pixclk, int vco);
5189
5190 static void intel_update_max_cdclk(struct drm_device *dev)
5191 {
5192         struct drm_i915_private *dev_priv = dev->dev_private;
5193
5194         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5195                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5196                 int max_cdclk, vco;
5197
5198                 vco = dev_priv->skl_preferred_vco_freq;
5199                 WARN_ON(vco != 8100 && vco != 8640);
5200
5201                 /*
5202                  * Use the lower (vco 8640) cdclk values as a
5203                  * first guess. skl_calc_cdclk() will correct it
5204                  * if the preferred vco is 8100 instead.
5205                  */
5206                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5207                         max_cdclk = 617140;
5208                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5209                         max_cdclk = 540000;
5210                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5211                         max_cdclk = 432000;
5212                 else
5213                         max_cdclk = 308570;
5214
5215                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5216         } else if (IS_BROXTON(dev)) {
5217                 dev_priv->max_cdclk_freq = 624000;
5218         } else if (IS_BROADWELL(dev))  {
5219                 /*
5220                  * FIXME with extra cooling we can allow
5221                  * 540 MHz for ULX and 675 Mhz for ULT.
5222                  * How can we know if extra cooling is
5223                  * available? PCI ID, VTB, something else?
5224                  */
5225                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5226                         dev_priv->max_cdclk_freq = 450000;
5227                 else if (IS_BDW_ULX(dev))
5228                         dev_priv->max_cdclk_freq = 450000;
5229                 else if (IS_BDW_ULT(dev))
5230                         dev_priv->max_cdclk_freq = 540000;
5231                 else
5232                         dev_priv->max_cdclk_freq = 675000;
5233         } else if (IS_CHERRYVIEW(dev)) {
5234                 dev_priv->max_cdclk_freq = 320000;
5235         } else if (IS_VALLEYVIEW(dev)) {
5236                 dev_priv->max_cdclk_freq = 400000;
5237         } else {
5238                 /* otherwise assume cdclk is fixed */
5239                 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5240         }
5241
5242         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5243
5244         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5245                          dev_priv->max_cdclk_freq);
5246
5247         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5248                          dev_priv->max_dotclk_freq);
5249 }
5250
5251 static void intel_update_cdclk(struct drm_device *dev)
5252 {
5253         struct drm_i915_private *dev_priv = dev->dev_private;
5254
5255         dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5256
5257         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5258                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d MHz\n",
5259                                  dev_priv->cdclk_freq, dev_priv->skl_vco_freq);
5260         else
5261                 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5262                                  dev_priv->cdclk_freq);
5263
5264         /*
5265          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5266          * Programmng [sic] note: bit[9:2] should be programmed to the number
5267          * of cdclk that generates 4MHz reference clock freq which is used to
5268          * generate GMBus clock. This will vary with the cdclk freq.
5269          */
5270         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5271                 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5272 }
5273
5274 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5275 static int skl_cdclk_decimal(int cdclk)
5276 {
5277         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5278 }
5279
5280 static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5281 {
5282         uint32_t divider;
5283         uint32_t ratio;
5284         uint32_t current_cdclk;
5285         int ret;
5286
5287         /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5288         switch (cdclk) {
5289         case 144000:
5290                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5291                 ratio = BXT_DE_PLL_RATIO(60);
5292                 break;
5293         case 288000:
5294                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5295                 ratio = BXT_DE_PLL_RATIO(60);
5296                 break;
5297         case 384000:
5298                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5299                 ratio = BXT_DE_PLL_RATIO(60);
5300                 break;
5301         case 576000:
5302                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5303                 ratio = BXT_DE_PLL_RATIO(60);
5304                 break;
5305         case 624000:
5306                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5307                 ratio = BXT_DE_PLL_RATIO(65);
5308                 break;
5309         case 19200:
5310                 /*
5311                  * Bypass frequency with DE PLL disabled. Init ratio, divider
5312                  * to suppress GCC warning.
5313                  */
5314                 ratio = 0;
5315                 divider = 0;
5316                 break;
5317         default:
5318                 DRM_ERROR("unsupported CDCLK freq %d", cdclk);
5319
5320                 return;
5321         }
5322
5323         mutex_lock(&dev_priv->rps.hw_lock);
5324         /* Inform power controller of upcoming frequency change */
5325         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5326                                       0x80000000);
5327         mutex_unlock(&dev_priv->rps.hw_lock);
5328
5329         if (ret) {
5330                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5331                           ret, cdclk);
5332                 return;
5333         }
5334
5335         current_cdclk = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5336         /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5337         current_cdclk = current_cdclk * 500 + 1000;
5338
5339         /*
5340          * DE PLL has to be disabled when
5341          * - setting to 19.2MHz (bypass, PLL isn't used)
5342          * - before setting to 624MHz (PLL needs toggling)
5343          * - before setting to any frequency from 624MHz (PLL needs toggling)
5344          */
5345         if (cdclk == 19200 || cdclk == 624000 ||
5346             current_cdclk == 624000) {
5347                 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5348                 /* Timeout 200us */
5349                 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5350                              1))
5351                         DRM_ERROR("timout waiting for DE PLL unlock\n");
5352         }
5353
5354         if (cdclk != 19200) {
5355                 uint32_t val;
5356
5357                 val = I915_READ(BXT_DE_PLL_CTL);
5358                 val &= ~BXT_DE_PLL_RATIO_MASK;
5359                 val |= ratio;
5360                 I915_WRITE(BXT_DE_PLL_CTL, val);
5361
5362                 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5363                 /* Timeout 200us */
5364                 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5365                         DRM_ERROR("timeout waiting for DE PLL lock\n");
5366
5367                 val = divider | skl_cdclk_decimal(cdclk);
5368                 /*
5369                  * FIXME if only the cd2x divider needs changing, it could be done
5370                  * without shutting off the pipe (if only one pipe is active).
5371                  */
5372                 val |= BXT_CDCLK_CD2X_PIPE_NONE;
5373                 /*
5374                  * Disable SSA Precharge when CD clock frequency < 500 MHz,
5375                  * enable otherwise.
5376                  */
5377                 if (cdclk >= 500000)
5378                         val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5379                 I915_WRITE(CDCLK_CTL, val);
5380         }
5381
5382         mutex_lock(&dev_priv->rps.hw_lock);
5383         ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5384                                       DIV_ROUND_UP(cdclk, 25000));
5385         mutex_unlock(&dev_priv->rps.hw_lock);
5386
5387         if (ret) {
5388                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5389                           ret, cdclk);
5390                 return;
5391         }
5392
5393         intel_update_cdclk(dev_priv->dev);
5394 }
5395
5396 static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
5397 {
5398         if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
5399                 return false;
5400
5401         /* TODO: Check for a valid CDCLK rate */
5402
5403         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) {
5404                 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n");
5405
5406                 return false;
5407         }
5408
5409         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) {
5410                 DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n");
5411
5412                 return false;
5413         }
5414
5415         return true;
5416 }
5417
5418 bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
5419 {
5420         return broxton_cdclk_is_enabled(dev_priv);
5421 }
5422
5423 void broxton_init_cdclk(struct drm_i915_private *dev_priv)
5424 {
5425         /* check if cd clock is enabled */
5426         if (broxton_cdclk_is_enabled(dev_priv)) {
5427                 DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n");
5428                 return;
5429         }
5430
5431         DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n");
5432
5433         /*
5434          * FIXME:
5435          * - The initial CDCLK needs to be read from VBT.
5436          *   Need to make this change after VBT has changes for BXT.
5437          * - check if setting the max (or any) cdclk freq is really necessary
5438          *   here, it belongs to modeset time
5439          */
5440         broxton_set_cdclk(dev_priv, 624000);
5441
5442         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5443         POSTING_READ(DBUF_CTL);
5444
5445         udelay(10);
5446
5447         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5448                 DRM_ERROR("DBuf power enable timeout!\n");
5449 }
5450
5451 void broxton_uninit_cdclk(struct drm_i915_private *dev_priv)
5452 {
5453         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5454         POSTING_READ(DBUF_CTL);
5455
5456         udelay(10);
5457
5458         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5459                 DRM_ERROR("DBuf power disable timeout!\n");
5460
5461         /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5462         broxton_set_cdclk(dev_priv, 19200);
5463 }
5464
5465 static int skl_calc_cdclk(int max_pixclk, int vco)
5466 {
5467         if (vco == 8640) {
5468                 if (max_pixclk > 540000)
5469                         return 617140;
5470                 else if (max_pixclk > 432000)
5471                         return 540000;
5472                 else if (max_pixclk > 308570)
5473                         return 432000;
5474                 else
5475                         return 308570;
5476         } else {
5477                 /* VCO 8100 */
5478                 if (max_pixclk > 540000)
5479                         return 675000;
5480                 else if (max_pixclk > 450000)
5481                         return 540000;
5482                 else if (max_pixclk > 337500)
5483                         return 450000;
5484                 else
5485                         return 337500;
5486         }
5487 }
5488
5489 static void
5490 skl_dpll0_update(struct drm_i915_private *dev_priv)
5491 {
5492         u32 val;
5493
5494         val = I915_READ(LCPLL1_CTL);
5495         if ((val & LCPLL_PLL_ENABLE) == 0) {
5496                 dev_priv->skl_vco_freq = 0;
5497                 return;
5498         }
5499
5500         val = I915_READ(DPLL_CTRL1);
5501
5502         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
5503         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
5504         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
5505         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
5506         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
5507                 dev_priv->skl_vco_freq = 8100;
5508                 break;
5509         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
5510         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
5511                 dev_priv->skl_vco_freq = 8640;
5512                 break;
5513         default:
5514                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5515                 dev_priv->skl_vco_freq = 0;
5516                 break;
5517         }
5518 }
5519
5520 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
5521 {
5522         bool changed = dev_priv->skl_preferred_vco_freq != vco;
5523
5524         dev_priv->skl_preferred_vco_freq = vco;
5525
5526         if (changed)
5527                 intel_update_max_cdclk(dev_priv->dev);
5528 }
5529
5530 static void
5531 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
5532 {
5533         int min_cdclk = skl_calc_cdclk(0, vco);
5534         u32 val;
5535
5536         WARN_ON(vco != 8100 && vco != 8640);
5537
5538         /* select the minimum CDCLK before enabling DPLL 0 */
5539         val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
5540         I915_WRITE(CDCLK_CTL, val);
5541         POSTING_READ(CDCLK_CTL);
5542
5543         /*
5544          * We always enable DPLL0 with the lowest link rate possible, but still
5545          * taking into account the VCO required to operate the eDP panel at the
5546          * desired frequency. The usual DP link rates operate with a VCO of
5547          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5548          * The modeset code is responsible for the selection of the exact link
5549          * rate later on, with the constraint of choosing a frequency that
5550          * works with vco.
5551          */
5552         val = I915_READ(DPLL_CTRL1);
5553
5554         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5555                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5556         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5557         if (vco == 8640)
5558                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5559                                             SKL_DPLL0);
5560         else
5561                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5562                                             SKL_DPLL0);
5563
5564         I915_WRITE(DPLL_CTRL1, val);
5565         POSTING_READ(DPLL_CTRL1);
5566
5567         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5568
5569         if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5570                 DRM_ERROR("DPLL0 not locked\n");
5571
5572         dev_priv->skl_vco_freq = vco;
5573
5574         /* We'll want to keep using the current vco from now on. */
5575         skl_set_preferred_cdclk_vco(dev_priv, vco);
5576 }
5577
5578 static void
5579 skl_dpll0_disable(struct drm_i915_private *dev_priv)
5580 {
5581         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5582         if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5583                 DRM_ERROR("Couldn't disable DPLL0\n");
5584
5585         dev_priv->skl_vco_freq = 0;
5586 }
5587
5588 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5589 {
5590         int ret;
5591         u32 val;
5592
5593         /* inform PCU we want to change CDCLK */
5594         val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5595         mutex_lock(&dev_priv->rps.hw_lock);
5596         ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5597         mutex_unlock(&dev_priv->rps.hw_lock);
5598
5599         return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5600 }
5601
5602 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5603 {
5604         unsigned int i;
5605
5606         for (i = 0; i < 15; i++) {
5607                 if (skl_cdclk_pcu_ready(dev_priv))
5608                         return true;
5609                 udelay(10);
5610         }
5611
5612         return false;
5613 }
5614
5615 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
5616 {
5617         struct drm_device *dev = dev_priv->dev;
5618         u32 freq_select, pcu_ack;
5619
5620         WARN_ON((cdclk == 24000) != (vco == 0));
5621
5622         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d MHz)\n", cdclk, vco);
5623
5624         if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5625                 DRM_ERROR("failed to inform PCU about cdclk change\n");
5626                 return;
5627         }
5628
5629         /* set CDCLK_CTL */
5630         switch (cdclk) {
5631         case 450000:
5632         case 432000:
5633                 freq_select = CDCLK_FREQ_450_432;
5634                 pcu_ack = 1;
5635                 break;
5636         case 540000:
5637                 freq_select = CDCLK_FREQ_540;
5638                 pcu_ack = 2;
5639                 break;
5640         case 308570:
5641         case 337500:
5642         default:
5643                 freq_select = CDCLK_FREQ_337_308;
5644                 pcu_ack = 0;
5645                 break;
5646         case 617140:
5647         case 675000:
5648                 freq_select = CDCLK_FREQ_675_617;
5649                 pcu_ack = 3;
5650                 break;
5651         }
5652
5653         if (dev_priv->skl_vco_freq != 0 &&
5654             dev_priv->skl_vco_freq != vco)
5655                 skl_dpll0_disable(dev_priv);
5656
5657         if (dev_priv->skl_vco_freq != vco)
5658                 skl_dpll0_enable(dev_priv, vco);
5659
5660         I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
5661         POSTING_READ(CDCLK_CTL);
5662
5663         /* inform PCU of the change */
5664         mutex_lock(&dev_priv->rps.hw_lock);
5665         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5666         mutex_unlock(&dev_priv->rps.hw_lock);
5667
5668         intel_update_cdclk(dev);
5669 }
5670
5671 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5672 {
5673         /* disable DBUF power */
5674         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5675         POSTING_READ(DBUF_CTL);
5676
5677         udelay(10);
5678
5679         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5680                 DRM_ERROR("DBuf power disable timeout\n");
5681
5682         skl_set_cdclk(dev_priv, 24000, 0);
5683 }
5684
5685 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5686 {
5687         /* DPLL0 not enabled (happens on early BIOS versions) */
5688         if (dev_priv->skl_vco_freq == 0) {
5689                 int cdclk, vco;
5690
5691                 /* set CDCLK to the lowest frequency, Modeset follows */
5692                 vco = dev_priv->skl_preferred_vco_freq;
5693                 if (vco == 0)
5694                         vco = 8100;
5695                 cdclk = skl_calc_cdclk(0, vco);
5696
5697                 skl_set_cdclk(dev_priv, cdclk, vco);
5698         }
5699
5700         /* enable DBUF power */
5701         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5702         POSTING_READ(DBUF_CTL);
5703
5704         udelay(10);
5705
5706         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5707                 DRM_ERROR("DBuf power enable timeout\n");
5708 }
5709
5710 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5711 {
5712         uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5713         uint32_t cdctl = I915_READ(CDCLK_CTL);
5714         int freq = dev_priv->cdclk_freq;
5715
5716         /*
5717          * check if the pre-os intialized the display
5718          * There is SWF18 scratchpad register defined which is set by the
5719          * pre-os which can be used by the OS drivers to check the status
5720          */
5721         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5722                 goto sanitize;
5723
5724         /* Is PLL enabled and locked ? */
5725         if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5726                 goto sanitize;
5727
5728         /* DPLL okay; verify the cdclock
5729          *
5730          * Noticed in some instances that the freq selection is correct but
5731          * decimal part is programmed wrong from BIOS where pre-os does not
5732          * enable display. Verify the same as well.
5733          */
5734         if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5735                 /* All well; nothing to sanitize */
5736                 return false;
5737 sanitize:
5738
5739         skl_init_cdclk(dev_priv);
5740
5741         /* we did have to sanitize */
5742         return true;
5743 }
5744
5745 /* Adjust CDclk dividers to allow high res or save power if possible */
5746 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5747 {
5748         struct drm_i915_private *dev_priv = dev->dev_private;
5749         u32 val, cmd;
5750
5751         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5752                                         != dev_priv->cdclk_freq);
5753
5754         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5755                 cmd = 2;
5756         else if (cdclk == 266667)
5757                 cmd = 1;
5758         else
5759                 cmd = 0;
5760
5761         mutex_lock(&dev_priv->rps.hw_lock);
5762         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5763         val &= ~DSPFREQGUAR_MASK;
5764         val |= (cmd << DSPFREQGUAR_SHIFT);
5765         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5766         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5767                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5768                      50)) {
5769                 DRM_ERROR("timed out waiting for CDclk change\n");
5770         }
5771         mutex_unlock(&dev_priv->rps.hw_lock);
5772
5773         mutex_lock(&dev_priv->sb_lock);
5774
5775         if (cdclk == 400000) {
5776                 u32 divider;
5777
5778                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5779
5780                 /* adjust cdclk divider */
5781                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5782                 val &= ~CCK_FREQUENCY_VALUES;
5783                 val |= divider;
5784                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5785
5786                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5787                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5788                              50))
5789                         DRM_ERROR("timed out waiting for CDclk change\n");
5790         }
5791
5792         /* adjust self-refresh exit latency value */
5793         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5794         val &= ~0x7f;
5795
5796         /*
5797          * For high bandwidth configs, we set a higher latency in the bunit
5798          * so that the core display fetch happens in time to avoid underruns.
5799          */
5800         if (cdclk == 400000)
5801                 val |= 4500 / 250; /* 4.5 usec */
5802         else
5803                 val |= 3000 / 250; /* 3.0 usec */
5804         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5805
5806         mutex_unlock(&dev_priv->sb_lock);
5807
5808         intel_update_cdclk(dev);
5809 }
5810
5811 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5812 {
5813         struct drm_i915_private *dev_priv = dev->dev_private;
5814         u32 val, cmd;
5815
5816         WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5817                                                 != dev_priv->cdclk_freq);
5818
5819         switch (cdclk) {
5820         case 333333:
5821         case 320000:
5822         case 266667:
5823         case 200000:
5824                 break;
5825         default:
5826                 MISSING_CASE(cdclk);
5827                 return;
5828         }
5829
5830         /*
5831          * Specs are full of misinformation, but testing on actual
5832          * hardware has shown that we just need to write the desired
5833          * CCK divider into the Punit register.
5834          */
5835         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5836
5837         mutex_lock(&dev_priv->rps.hw_lock);
5838         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5839         val &= ~DSPFREQGUAR_MASK_CHV;
5840         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5841         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5842         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5843                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5844                      50)) {
5845                 DRM_ERROR("timed out waiting for CDclk change\n");
5846         }
5847         mutex_unlock(&dev_priv->rps.hw_lock);
5848
5849         intel_update_cdclk(dev);
5850 }
5851
5852 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5853                                  int max_pixclk)
5854 {
5855         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ? 333333 : 320000;
5856         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5857
5858         /*
5859          * Really only a few cases to deal with, as only 4 CDclks are supported:
5860          *   200MHz
5861          *   267MHz
5862          *   320/333MHz (depends on HPLL freq)
5863          *   400MHz (VLV only)
5864          * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5865          * of the lower bin and adjust if needed.
5866          *
5867          * We seem to get an unstable or solid color picture at 200MHz.
5868          * Not sure what's wrong. For now use 200MHz only when all pipes
5869          * are off.
5870          */
5871         if (!IS_CHERRYVIEW(dev_priv) &&
5872             max_pixclk > freq_320*limit/100)
5873                 return 400000;
5874         else if (max_pixclk > 266667*limit/100)
5875                 return freq_320;
5876         else if (max_pixclk > 0)
5877                 return 266667;
5878         else
5879                 return 200000;
5880 }
5881
5882 static int broxton_calc_cdclk(int max_pixclk)
5883 {
5884         /*
5885          * FIXME:
5886          * - set 19.2MHz bypass frequency if there are no active pipes
5887          */
5888         if (max_pixclk > 576000)
5889                 return 624000;
5890         else if (max_pixclk > 384000)
5891                 return 576000;
5892         else if (max_pixclk > 288000)
5893                 return 384000;
5894         else if (max_pixclk > 144000)
5895                 return 288000;
5896         else
5897                 return 144000;
5898 }
5899
5900 /* Compute the max pixel clock for new configuration. */
5901 static int intel_mode_max_pixclk(struct drm_device *dev,
5902                                  struct drm_atomic_state *state)
5903 {
5904         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5905         struct drm_i915_private *dev_priv = dev->dev_private;
5906         struct drm_crtc *crtc;
5907         struct drm_crtc_state *crtc_state;
5908         unsigned max_pixclk = 0, i;
5909         enum pipe pipe;
5910
5911         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5912                sizeof(intel_state->min_pixclk));
5913
5914         for_each_crtc_in_state(state, crtc, crtc_state, i) {
5915                 int pixclk = 0;
5916
5917                 if (crtc_state->enable)
5918                         pixclk = crtc_state->adjusted_mode.crtc_clock;
5919
5920                 intel_state->min_pixclk[i] = pixclk;
5921         }
5922
5923         for_each_pipe(dev_priv, pipe)
5924                 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5925
5926         return max_pixclk;
5927 }
5928
5929 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5930 {
5931         struct drm_device *dev = state->dev;
5932         struct drm_i915_private *dev_priv = dev->dev_private;
5933         int max_pixclk = intel_mode_max_pixclk(dev, state);
5934         struct intel_atomic_state *intel_state =
5935                 to_intel_atomic_state(state);
5936
5937         intel_state->cdclk = intel_state->dev_cdclk =
5938                 valleyview_calc_cdclk(dev_priv, max_pixclk);
5939
5940         if (!intel_state->active_crtcs)
5941                 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5942
5943         return 0;
5944 }
5945
5946 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5947 {
5948         int max_pixclk = ilk_max_pixel_rate(state);
5949         struct intel_atomic_state *intel_state =
5950                 to_intel_atomic_state(state);
5951
5952         intel_state->cdclk = intel_state->dev_cdclk =
5953                 broxton_calc_cdclk(max_pixclk);
5954
5955         if (!intel_state->active_crtcs)
5956                 intel_state->dev_cdclk = broxton_calc_cdclk(0);
5957
5958         return 0;
5959 }
5960
5961 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5962 {
5963         unsigned int credits, default_credits;
5964
5965         if (IS_CHERRYVIEW(dev_priv))
5966                 default_credits = PFI_CREDIT(12);
5967         else
5968                 default_credits = PFI_CREDIT(8);
5969
5970         if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5971                 /* CHV suggested value is 31 or 63 */
5972                 if (IS_CHERRYVIEW(dev_priv))
5973                         credits = PFI_CREDIT_63;
5974                 else
5975                         credits = PFI_CREDIT(15);
5976         } else {
5977                 credits = default_credits;
5978         }
5979
5980         /*
5981          * WA - write default credits before re-programming
5982          * FIXME: should we also set the resend bit here?
5983          */
5984         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5985                    default_credits);
5986
5987         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5988                    credits | PFI_CREDIT_RESEND);
5989
5990         /*
5991          * FIXME is this guaranteed to clear
5992          * immediately or should we poll for it?
5993          */
5994         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5995 }
5996
5997 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
5998 {
5999         struct drm_device *dev = old_state->dev;
6000         struct drm_i915_private *dev_priv = dev->dev_private;
6001         struct intel_atomic_state *old_intel_state =
6002                 to_intel_atomic_state(old_state);
6003         unsigned req_cdclk = old_intel_state->dev_cdclk;
6004
6005         /*
6006          * FIXME: We can end up here with all power domains off, yet
6007          * with a CDCLK frequency other than the minimum. To account
6008          * for this take the PIPE-A power domain, which covers the HW
6009          * blocks needed for the following programming. This can be
6010          * removed once it's guaranteed that we get here either with
6011          * the minimum CDCLK set, or the required power domains
6012          * enabled.
6013          */
6014         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6015
6016         if (IS_CHERRYVIEW(dev))
6017                 cherryview_set_cdclk(dev, req_cdclk);
6018         else
6019                 valleyview_set_cdclk(dev, req_cdclk);
6020
6021         vlv_program_pfi_credits(dev_priv);
6022
6023         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6024 }
6025
6026 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6027 {
6028         struct drm_device *dev = crtc->dev;
6029         struct drm_i915_private *dev_priv = to_i915(dev);
6030         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6031         struct intel_encoder *encoder;
6032         struct intel_crtc_state *pipe_config =
6033                 to_intel_crtc_state(crtc->state);
6034         int pipe = intel_crtc->pipe;
6035
6036         if (WARN_ON(intel_crtc->active))
6037                 return;
6038
6039         if (intel_crtc->config->has_dp_encoder)
6040                 intel_dp_set_m_n(intel_crtc, M1_N1);
6041
6042         intel_set_pipe_timings(intel_crtc);
6043         intel_set_pipe_src_size(intel_crtc);
6044
6045         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6046                 struct drm_i915_private *dev_priv = dev->dev_private;
6047
6048                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6049                 I915_WRITE(CHV_CANVAS(pipe), 0);
6050         }
6051
6052         i9xx_set_pipeconf(intel_crtc);
6053
6054         intel_crtc->active = true;
6055
6056         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6057
6058         for_each_encoder_on_crtc(dev, crtc, encoder)
6059                 if (encoder->pre_pll_enable)
6060                         encoder->pre_pll_enable(encoder);
6061
6062         if (IS_CHERRYVIEW(dev)) {
6063                 chv_prepare_pll(intel_crtc, intel_crtc->config);
6064                 chv_enable_pll(intel_crtc, intel_crtc->config);
6065         } else {
6066                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6067                 vlv_enable_pll(intel_crtc, intel_crtc->config);
6068         }
6069
6070         for_each_encoder_on_crtc(dev, crtc, encoder)
6071                 if (encoder->pre_enable)
6072                         encoder->pre_enable(encoder);
6073
6074         i9xx_pfit_enable(intel_crtc);
6075
6076         intel_color_load_luts(&pipe_config->base);
6077
6078         intel_update_watermarks(crtc);
6079         intel_enable_pipe(intel_crtc);
6080
6081         assert_vblank_disabled(crtc);
6082         drm_crtc_vblank_on(crtc);
6083
6084         for_each_encoder_on_crtc(dev, crtc, encoder)
6085                 encoder->enable(encoder);
6086 }
6087
6088 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6089 {
6090         struct drm_device *dev = crtc->base.dev;
6091         struct drm_i915_private *dev_priv = dev->dev_private;
6092
6093         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6094         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6095 }
6096
6097 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6098 {
6099         struct drm_device *dev = crtc->dev;
6100         struct drm_i915_private *dev_priv = to_i915(dev);
6101         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6102         struct intel_encoder *encoder;
6103         struct intel_crtc_state *pipe_config =
6104                 to_intel_crtc_state(crtc->state);
6105         enum pipe pipe = intel_crtc->pipe;
6106
6107         if (WARN_ON(intel_crtc->active))
6108                 return;
6109
6110         i9xx_set_pll_dividers(intel_crtc);
6111
6112         if (intel_crtc->config->has_dp_encoder)
6113                 intel_dp_set_m_n(intel_crtc, M1_N1);
6114
6115         intel_set_pipe_timings(intel_crtc);
6116         intel_set_pipe_src_size(intel_crtc);
6117
6118         i9xx_set_pipeconf(intel_crtc);
6119
6120         intel_crtc->active = true;
6121
6122         if (!IS_GEN2(dev))
6123                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6124
6125         for_each_encoder_on_crtc(dev, crtc, encoder)
6126                 if (encoder->pre_enable)
6127                         encoder->pre_enable(encoder);
6128
6129         i9xx_enable_pll(intel_crtc);
6130
6131         i9xx_pfit_enable(intel_crtc);
6132
6133         intel_color_load_luts(&pipe_config->base);
6134
6135         intel_update_watermarks(crtc);
6136         intel_enable_pipe(intel_crtc);
6137
6138         assert_vblank_disabled(crtc);
6139         drm_crtc_vblank_on(crtc);
6140
6141         for_each_encoder_on_crtc(dev, crtc, encoder)
6142                 encoder->enable(encoder);
6143 }
6144
6145 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6146 {
6147         struct drm_device *dev = crtc->base.dev;
6148         struct drm_i915_private *dev_priv = dev->dev_private;
6149
6150         if (!crtc->config->gmch_pfit.control)
6151                 return;
6152
6153         assert_pipe_disabled(dev_priv, crtc->pipe);
6154
6155         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6156                          I915_READ(PFIT_CONTROL));
6157         I915_WRITE(PFIT_CONTROL, 0);
6158 }
6159
6160 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6161 {
6162         struct drm_device *dev = crtc->dev;
6163         struct drm_i915_private *dev_priv = dev->dev_private;
6164         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6165         struct intel_encoder *encoder;
6166         int pipe = intel_crtc->pipe;
6167
6168         /*
6169          * On gen2 planes are double buffered but the pipe isn't, so we must
6170          * wait for planes to fully turn off before disabling the pipe.
6171          */
6172         if (IS_GEN2(dev))
6173                 intel_wait_for_vblank(dev, pipe);
6174
6175         for_each_encoder_on_crtc(dev, crtc, encoder)
6176                 encoder->disable(encoder);
6177
6178         drm_crtc_vblank_off(crtc);
6179         assert_vblank_disabled(crtc);
6180
6181         intel_disable_pipe(intel_crtc);
6182
6183         i9xx_pfit_disable(intel_crtc);
6184
6185         for_each_encoder_on_crtc(dev, crtc, encoder)
6186                 if (encoder->post_disable)
6187                         encoder->post_disable(encoder);
6188
6189         if (!intel_crtc->config->has_dsi_encoder) {
6190                 if (IS_CHERRYVIEW(dev))
6191                         chv_disable_pll(dev_priv, pipe);
6192                 else if (IS_VALLEYVIEW(dev))
6193                         vlv_disable_pll(dev_priv, pipe);
6194                 else
6195                         i9xx_disable_pll(intel_crtc);
6196         }
6197
6198         for_each_encoder_on_crtc(dev, crtc, encoder)
6199                 if (encoder->post_pll_disable)
6200                         encoder->post_pll_disable(encoder);
6201
6202         if (!IS_GEN2(dev))
6203                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6204 }
6205
6206 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6207 {
6208         struct intel_encoder *encoder;
6209         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6210         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6211         enum intel_display_power_domain domain;
6212         unsigned long domains;
6213
6214         if (!intel_crtc->active)
6215                 return;
6216
6217         if (to_intel_plane_state(crtc->primary->state)->visible) {
6218                 WARN_ON(list_empty(&intel_crtc->flip_work));
6219
6220                 intel_pre_disable_primary_noatomic(crtc);
6221
6222                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6223                 to_intel_plane_state(crtc->primary->state)->visible = false;
6224         }
6225
6226         dev_priv->display.crtc_disable(crtc);
6227
6228         DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6229                       crtc->base.id);
6230
6231         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6232         crtc->state->active = false;
6233         intel_crtc->active = false;
6234         crtc->enabled = false;
6235         crtc->state->connector_mask = 0;
6236         crtc->state->encoder_mask = 0;
6237
6238         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6239                 encoder->base.crtc = NULL;
6240
6241         intel_fbc_disable(intel_crtc);
6242         intel_update_watermarks(crtc);
6243         intel_disable_shared_dpll(intel_crtc);
6244
6245         domains = intel_crtc->enabled_power_domains;
6246         for_each_power_domain(domain, domains)
6247                 intel_display_power_put(dev_priv, domain);
6248         intel_crtc->enabled_power_domains = 0;
6249
6250         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6251         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6252 }
6253
6254 /*
6255  * turn all crtc's off, but do not adjust state
6256  * This has to be paired with a call to intel_modeset_setup_hw_state.
6257  */
6258 int intel_display_suspend(struct drm_device *dev)
6259 {
6260         struct drm_i915_private *dev_priv = to_i915(dev);
6261         struct drm_atomic_state *state;
6262         int ret;
6263
6264         state = drm_atomic_helper_suspend(dev);
6265         ret = PTR_ERR_OR_ZERO(state);
6266         if (ret)
6267                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6268         else
6269                 dev_priv->modeset_restore_state = state;
6270
6271         /*
6272          * Make sure all unpin_work completes before returning.
6273          */
6274         flush_workqueue(dev_priv->wq);
6275
6276         return ret;
6277 }
6278
6279 void intel_encoder_destroy(struct drm_encoder *encoder)
6280 {
6281         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6282
6283         drm_encoder_cleanup(encoder);
6284         kfree(intel_encoder);
6285 }
6286
6287 /* Cross check the actual hw state with our own modeset state tracking (and it's
6288  * internal consistency). */
6289 static void intel_connector_verify_state(struct intel_connector *connector,
6290                                          struct drm_connector_state *conn_state)
6291 {
6292         struct drm_crtc *crtc = conn_state->crtc;
6293
6294         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6295                       connector->base.base.id,
6296                       connector->base.name);
6297
6298         if (connector->get_hw_state(connector)) {
6299                 struct intel_encoder *encoder = connector->encoder;
6300
6301                 I915_STATE_WARN(!crtc,
6302                          "connector enabled without attached crtc\n");
6303
6304                 if (!crtc)
6305                         return;
6306
6307                 I915_STATE_WARN(!crtc->state->active,
6308                       "connector is active, but attached crtc isn't\n");
6309
6310                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6311                         return;
6312
6313                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6314                         "atomic encoder doesn't match attached encoder\n");
6315
6316                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6317                         "attached encoder crtc differs from connector crtc\n");
6318         } else {
6319                 I915_STATE_WARN(crtc && crtc->state->active,
6320                         "attached crtc is active, but connector isn't\n");
6321                 I915_STATE_WARN(!crtc && conn_state->best_encoder,
6322                         "best encoder set without crtc!\n");
6323         }
6324 }
6325
6326 int intel_connector_init(struct intel_connector *connector)
6327 {
6328         drm_atomic_helper_connector_reset(&connector->base);
6329
6330         if (!connector->base.state)
6331                 return -ENOMEM;
6332
6333         return 0;
6334 }
6335
6336 struct intel_connector *intel_connector_alloc(void)
6337 {
6338         struct intel_connector *connector;
6339
6340         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6341         if (!connector)
6342                 return NULL;
6343
6344         if (intel_connector_init(connector) < 0) {
6345                 kfree(connector);
6346                 return NULL;
6347         }
6348
6349         return connector;
6350 }
6351
6352 /* Simple connector->get_hw_state implementation for encoders that support only
6353  * one connector and no cloning and hence the encoder state determines the state
6354  * of the connector. */
6355 bool intel_connector_get_hw_state(struct intel_connector *connector)
6356 {
6357         enum pipe pipe = 0;
6358         struct intel_encoder *encoder = connector->encoder;
6359
6360         return encoder->get_hw_state(encoder, &pipe);
6361 }
6362
6363 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6364 {
6365         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6366                 return crtc_state->fdi_lanes;
6367
6368         return 0;
6369 }
6370
6371 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6372                                      struct intel_crtc_state *pipe_config)
6373 {
6374         struct drm_atomic_state *state = pipe_config->base.state;
6375         struct intel_crtc *other_crtc;
6376         struct intel_crtc_state *other_crtc_state;
6377
6378         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6379                       pipe_name(pipe), pipe_config->fdi_lanes);
6380         if (pipe_config->fdi_lanes > 4) {
6381                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6382                               pipe_name(pipe), pipe_config->fdi_lanes);
6383                 return -EINVAL;
6384         }
6385
6386         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6387                 if (pipe_config->fdi_lanes > 2) {
6388                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6389                                       pipe_config->fdi_lanes);
6390                         return -EINVAL;
6391                 } else {
6392                         return 0;
6393                 }
6394         }
6395
6396         if (INTEL_INFO(dev)->num_pipes == 2)
6397                 return 0;
6398
6399         /* Ivybridge 3 pipe is really complicated */
6400         switch (pipe) {
6401         case PIPE_A:
6402                 return 0;
6403         case PIPE_B:
6404                 if (pipe_config->fdi_lanes <= 2)
6405                         return 0;
6406
6407                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6408                 other_crtc_state =
6409                         intel_atomic_get_crtc_state(state, other_crtc);
6410                 if (IS_ERR(other_crtc_state))
6411                         return PTR_ERR(other_crtc_state);
6412
6413                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6414                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6415                                       pipe_name(pipe), pipe_config->fdi_lanes);
6416                         return -EINVAL;
6417                 }
6418                 return 0;
6419         case PIPE_C:
6420                 if (pipe_config->fdi_lanes > 2) {
6421                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6422                                       pipe_name(pipe), pipe_config->fdi_lanes);
6423                         return -EINVAL;
6424                 }
6425
6426                 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6427                 other_crtc_state =
6428                         intel_atomic_get_crtc_state(state, other_crtc);
6429                 if (IS_ERR(other_crtc_state))
6430                         return PTR_ERR(other_crtc_state);
6431
6432                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6433                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6434                         return -EINVAL;
6435                 }
6436                 return 0;
6437         default:
6438                 BUG();
6439         }
6440 }
6441
6442 #define RETRY 1
6443 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6444                                        struct intel_crtc_state *pipe_config)
6445 {
6446         struct drm_device *dev = intel_crtc->base.dev;
6447         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6448         int lane, link_bw, fdi_dotclock, ret;
6449         bool needs_recompute = false;
6450
6451 retry:
6452         /* FDI is a binary signal running at ~2.7GHz, encoding
6453          * each output octet as 10 bits. The actual frequency
6454          * is stored as a divider into a 100MHz clock, and the
6455          * mode pixel clock is stored in units of 1KHz.
6456          * Hence the bw of each lane in terms of the mode signal
6457          * is:
6458          */
6459         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6460
6461         fdi_dotclock = adjusted_mode->crtc_clock;
6462
6463         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6464                                            pipe_config->pipe_bpp);
6465
6466         pipe_config->fdi_lanes = lane;
6467
6468         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6469                                link_bw, &pipe_config->fdi_m_n);
6470
6471         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6472         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6473                 pipe_config->pipe_bpp -= 2*3;
6474                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6475                               pipe_config->pipe_bpp);
6476                 needs_recompute = true;
6477                 pipe_config->bw_constrained = true;
6478
6479                 goto retry;
6480         }
6481
6482         if (needs_recompute)
6483                 return RETRY;
6484
6485         return ret;
6486 }
6487
6488 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6489                                      struct intel_crtc_state *pipe_config)
6490 {
6491         if (pipe_config->pipe_bpp > 24)
6492                 return false;
6493
6494         /* HSW can handle pixel rate up to cdclk? */
6495         if (IS_HASWELL(dev_priv))
6496                 return true;
6497
6498         /*
6499          * We compare against max which means we must take
6500          * the increased cdclk requirement into account when
6501          * calculating the new cdclk.
6502          *
6503          * Should measure whether using a lower cdclk w/o IPS
6504          */
6505         return ilk_pipe_pixel_rate(pipe_config) <=
6506                 dev_priv->max_cdclk_freq * 95 / 100;
6507 }
6508
6509 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6510                                    struct intel_crtc_state *pipe_config)
6511 {
6512         struct drm_device *dev = crtc->base.dev;
6513         struct drm_i915_private *dev_priv = dev->dev_private;
6514
6515         pipe_config->ips_enabled = i915.enable_ips &&
6516                 hsw_crtc_supports_ips(crtc) &&
6517                 pipe_config_supports_ips(dev_priv, pipe_config);
6518 }
6519
6520 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6521 {
6522         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6523
6524         /* GDG double wide on either pipe, otherwise pipe A only */
6525         return INTEL_INFO(dev_priv)->gen < 4 &&
6526                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6527 }
6528
6529 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6530                                      struct intel_crtc_state *pipe_config)
6531 {
6532         struct drm_device *dev = crtc->base.dev;
6533         struct drm_i915_private *dev_priv = dev->dev_private;
6534         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6535
6536         /* FIXME should check pixel clock limits on all platforms */
6537         if (INTEL_INFO(dev)->gen < 4) {
6538                 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6539
6540                 /*
6541                  * Enable double wide mode when the dot clock
6542                  * is > 90% of the (display) core speed.
6543                  */
6544                 if (intel_crtc_supports_double_wide(crtc) &&
6545                     adjusted_mode->crtc_clock > clock_limit) {
6546                         clock_limit *= 2;
6547                         pipe_config->double_wide = true;
6548                 }
6549
6550                 if (adjusted_mode->crtc_clock > clock_limit) {
6551                         DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6552                                       adjusted_mode->crtc_clock, clock_limit,
6553                                       yesno(pipe_config->double_wide));
6554                         return -EINVAL;
6555                 }
6556         }
6557
6558         /*
6559          * Pipe horizontal size must be even in:
6560          * - DVO ganged mode
6561          * - LVDS dual channel mode
6562          * - Double wide pipe
6563          */
6564         if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6565              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6566                 pipe_config->pipe_src_w &= ~1;
6567
6568         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6569          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6570          */
6571         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6572                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6573                 return -EINVAL;
6574
6575         if (HAS_IPS(dev))
6576                 hsw_compute_ips_config(crtc, pipe_config);
6577
6578         if (pipe_config->has_pch_encoder)
6579                 return ironlake_fdi_compute_config(crtc, pipe_config);
6580
6581         return 0;
6582 }
6583
6584 static int skylake_get_display_clock_speed(struct drm_device *dev)
6585 {
6586         struct drm_i915_private *dev_priv = to_i915(dev);
6587         uint32_t cdctl;
6588
6589         skl_dpll0_update(dev_priv);
6590
6591         if (dev_priv->skl_vco_freq == 0)
6592                 return 24000; /* 24MHz is the cd freq with NSSC ref */
6593
6594         cdctl = I915_READ(CDCLK_CTL);
6595
6596         if (dev_priv->skl_vco_freq == 8640) {
6597                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6598                 case CDCLK_FREQ_450_432:
6599                         return 432000;
6600                 case CDCLK_FREQ_337_308:
6601                         return 308570;
6602                 case CDCLK_FREQ_540:
6603                         return 540000;
6604                 case CDCLK_FREQ_675_617:
6605                         return 617140;
6606                 default:
6607                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6608                 }
6609         } else {
6610                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6611                 case CDCLK_FREQ_450_432:
6612                         return 450000;
6613                 case CDCLK_FREQ_337_308:
6614                         return 337500;
6615                 case CDCLK_FREQ_540:
6616                         return 540000;
6617                 case CDCLK_FREQ_675_617:
6618                         return 675000;
6619                 default:
6620                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
6621                 }
6622         }
6623
6624         /* error case, do as if DPLL0 isn't enabled */
6625         return 24000;
6626 }
6627
6628 static int broxton_get_display_clock_speed(struct drm_device *dev)
6629 {
6630         struct drm_i915_private *dev_priv = to_i915(dev);
6631         uint32_t cdctl = I915_READ(CDCLK_CTL);
6632         uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6633         uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6634         int cdclk;
6635
6636         if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6637                 return 19200;
6638
6639         cdclk = 19200 * pll_ratio / 2;
6640
6641         switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6642         case BXT_CDCLK_CD2X_DIV_SEL_1:
6643                 return cdclk;  /* 576MHz or 624MHz */
6644         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6645                 return cdclk * 2 / 3; /* 384MHz */
6646         case BXT_CDCLK_CD2X_DIV_SEL_2:
6647                 return cdclk / 2; /* 288MHz */
6648         case BXT_CDCLK_CD2X_DIV_SEL_4:
6649                 return cdclk / 4; /* 144MHz */
6650         }
6651
6652         /* error case, do as if DE PLL isn't enabled */
6653         return 19200;
6654 }
6655
6656 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6657 {
6658         struct drm_i915_private *dev_priv = dev->dev_private;
6659         uint32_t lcpll = I915_READ(LCPLL_CTL);
6660         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6661
6662         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6663                 return 800000;
6664         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6665                 return 450000;
6666         else if (freq == LCPLL_CLK_FREQ_450)
6667                 return 450000;
6668         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6669                 return 540000;
6670         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6671                 return 337500;
6672         else
6673                 return 675000;
6674 }
6675
6676 static int haswell_get_display_clock_speed(struct drm_device *dev)
6677 {
6678         struct drm_i915_private *dev_priv = dev->dev_private;
6679         uint32_t lcpll = I915_READ(LCPLL_CTL);
6680         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6681
6682         if (lcpll & LCPLL_CD_SOURCE_FCLK)
6683                 return 800000;
6684         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6685                 return 450000;
6686         else if (freq == LCPLL_CLK_FREQ_450)
6687                 return 450000;
6688         else if (IS_HSW_ULT(dev))
6689                 return 337500;
6690         else
6691                 return 540000;
6692 }
6693
6694 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6695 {
6696         return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6697                                       CCK_DISPLAY_CLOCK_CONTROL);
6698 }
6699
6700 static int ilk_get_display_clock_speed(struct drm_device *dev)
6701 {
6702         return 450000;
6703 }
6704
6705 static int i945_get_display_clock_speed(struct drm_device *dev)
6706 {
6707         return 400000;
6708 }
6709
6710 static int i915_get_display_clock_speed(struct drm_device *dev)
6711 {
6712         return 333333;
6713 }
6714
6715 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6716 {
6717         return 200000;
6718 }
6719
6720 static int pnv_get_display_clock_speed(struct drm_device *dev)
6721 {
6722         u16 gcfgc = 0;
6723
6724         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6725
6726         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6727         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6728                 return 266667;
6729         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6730                 return 333333;
6731         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6732                 return 444444;
6733         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6734                 return 200000;
6735         default:
6736                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6737         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6738                 return 133333;
6739         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6740                 return 166667;
6741         }
6742 }
6743
6744 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6745 {
6746         u16 gcfgc = 0;
6747
6748         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6749
6750         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6751                 return 133333;
6752         else {
6753                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6754                 case GC_DISPLAY_CLOCK_333_MHZ:
6755                         return 333333;
6756                 default:
6757                 case GC_DISPLAY_CLOCK_190_200_MHZ:
6758                         return 190000;
6759                 }
6760         }
6761 }
6762
6763 static int i865_get_display_clock_speed(struct drm_device *dev)
6764 {
6765         return 266667;
6766 }
6767
6768 static int i85x_get_display_clock_speed(struct drm_device *dev)
6769 {
6770         u16 hpllcc = 0;
6771
6772         /*
6773          * 852GM/852GMV only supports 133 MHz and the HPLLCC
6774          * encoding is different :(
6775          * FIXME is this the right way to detect 852GM/852GMV?
6776          */
6777         if (dev->pdev->revision == 0x1)
6778                 return 133333;
6779
6780         pci_bus_read_config_word(dev->pdev->bus,
6781                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6782
6783         /* Assume that the hardware is in the high speed state.  This
6784          * should be the default.
6785          */
6786         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6787         case GC_CLOCK_133_200:
6788         case GC_CLOCK_133_200_2:
6789         case GC_CLOCK_100_200:
6790                 return 200000;
6791         case GC_CLOCK_166_250:
6792                 return 250000;
6793         case GC_CLOCK_100_133:
6794                 return 133333;
6795         case GC_CLOCK_133_266:
6796         case GC_CLOCK_133_266_2:
6797         case GC_CLOCK_166_266:
6798                 return 266667;
6799         }
6800
6801         /* Shouldn't happen */
6802         return 0;
6803 }
6804
6805 static int i830_get_display_clock_speed(struct drm_device *dev)
6806 {
6807         return 133333;
6808 }
6809
6810 static unsigned int intel_hpll_vco(struct drm_device *dev)
6811 {
6812         struct drm_i915_private *dev_priv = dev->dev_private;
6813         static const unsigned int blb_vco[8] = {
6814                 [0] = 3200000,
6815                 [1] = 4000000,
6816                 [2] = 5333333,
6817                 [3] = 4800000,
6818                 [4] = 6400000,
6819         };
6820         static const unsigned int pnv_vco[8] = {
6821                 [0] = 3200000,
6822                 [1] = 4000000,
6823                 [2] = 5333333,
6824                 [3] = 4800000,
6825                 [4] = 2666667,
6826         };
6827         static const unsigned int cl_vco[8] = {
6828                 [0] = 3200000,
6829                 [1] = 4000000,
6830                 [2] = 5333333,
6831                 [3] = 6400000,
6832                 [4] = 3333333,
6833                 [5] = 3566667,
6834                 [6] = 4266667,
6835         };
6836         static const unsigned int elk_vco[8] = {
6837                 [0] = 3200000,
6838                 [1] = 4000000,
6839                 [2] = 5333333,
6840                 [3] = 4800000,
6841         };
6842         static const unsigned int ctg_vco[8] = {
6843                 [0] = 3200000,
6844                 [1] = 4000000,
6845                 [2] = 5333333,
6846                 [3] = 6400000,
6847                 [4] = 2666667,
6848                 [5] = 4266667,
6849         };
6850         const unsigned int *vco_table;
6851         unsigned int vco;
6852         uint8_t tmp = 0;
6853
6854         /* FIXME other chipsets? */
6855         if (IS_GM45(dev))
6856                 vco_table = ctg_vco;
6857         else if (IS_G4X(dev))
6858                 vco_table = elk_vco;
6859         else if (IS_CRESTLINE(dev))
6860                 vco_table = cl_vco;
6861         else if (IS_PINEVIEW(dev))
6862                 vco_table = pnv_vco;
6863         else if (IS_G33(dev))
6864                 vco_table = blb_vco;
6865         else
6866                 return 0;
6867
6868         tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6869
6870         vco = vco_table[tmp & 0x7];
6871         if (vco == 0)
6872                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6873         else
6874                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6875
6876         return vco;
6877 }
6878
6879 static int gm45_get_display_clock_speed(struct drm_device *dev)
6880 {
6881         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6882         uint16_t tmp = 0;
6883
6884         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6885
6886         cdclk_sel = (tmp >> 12) & 0x1;
6887
6888         switch (vco) {
6889         case 2666667:
6890         case 4000000:
6891         case 5333333:
6892                 return cdclk_sel ? 333333 : 222222;
6893         case 3200000:
6894                 return cdclk_sel ? 320000 : 228571;
6895         default:
6896                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6897                 return 222222;
6898         }
6899 }
6900
6901 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6902 {
6903         static const uint8_t div_3200[] = { 16, 10,  8 };
6904         static const uint8_t div_4000[] = { 20, 12, 10 };
6905         static const uint8_t div_5333[] = { 24, 16, 14 };
6906         const uint8_t *div_table;
6907         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6908         uint16_t tmp = 0;
6909
6910         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6911
6912         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6913
6914         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6915                 goto fail;
6916
6917         switch (vco) {
6918         case 3200000:
6919                 div_table = div_3200;
6920                 break;
6921         case 4000000:
6922                 div_table = div_4000;
6923                 break;
6924         case 5333333:
6925                 div_table = div_5333;
6926                 break;
6927         default:
6928                 goto fail;
6929         }
6930
6931         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6932
6933 fail:
6934         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6935         return 200000;
6936 }
6937
6938 static int g33_get_display_clock_speed(struct drm_device *dev)
6939 {
6940         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
6941         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
6942         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6943         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6944         const uint8_t *div_table;
6945         unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6946         uint16_t tmp = 0;
6947
6948         pci_read_config_word(dev->pdev, GCFGC, &tmp);
6949
6950         cdclk_sel = (tmp >> 4) & 0x7;
6951
6952         if (cdclk_sel >= ARRAY_SIZE(div_3200))
6953                 goto fail;
6954
6955         switch (vco) {
6956         case 3200000:
6957                 div_table = div_3200;
6958                 break;
6959         case 4000000:
6960                 div_table = div_4000;
6961                 break;
6962         case 4800000:
6963                 div_table = div_4800;
6964                 break;
6965         case 5333333:
6966                 div_table = div_5333;
6967                 break;
6968         default:
6969                 goto fail;
6970         }
6971
6972         return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6973
6974 fail:
6975         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6976         return 190476;
6977 }
6978
6979 static void
6980 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6981 {
6982         while (*num > DATA_LINK_M_N_MASK ||
6983                *den > DATA_LINK_M_N_MASK) {
6984                 *num >>= 1;
6985                 *den >>= 1;
6986         }
6987 }
6988
6989 static void compute_m_n(unsigned int m, unsigned int n,
6990                         uint32_t *ret_m, uint32_t *ret_n)
6991 {
6992         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6993         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6994         intel_reduce_m_n_ratio(ret_m, ret_n);
6995 }
6996
6997 void
6998 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6999                        int pixel_clock, int link_clock,
7000                        struct intel_link_m_n *m_n)
7001 {
7002         m_n->tu = 64;
7003
7004         compute_m_n(bits_per_pixel * pixel_clock,
7005                     link_clock * nlanes * 8,
7006                     &m_n->gmch_m, &m_n->gmch_n);
7007
7008         compute_m_n(pixel_clock, link_clock,
7009                     &m_n->link_m, &m_n->link_n);
7010 }
7011
7012 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7013 {
7014         if (i915.panel_use_ssc >= 0)
7015                 return i915.panel_use_ssc != 0;
7016         return dev_priv->vbt.lvds_use_ssc
7017                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7018 }
7019
7020 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7021 {
7022         return (1 << dpll->n) << 16 | dpll->m2;
7023 }
7024
7025 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7026 {
7027         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7028 }
7029
7030 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7031                                      struct intel_crtc_state *crtc_state,
7032                                      struct dpll *reduced_clock)
7033 {
7034         struct drm_device *dev = crtc->base.dev;
7035         u32 fp, fp2 = 0;
7036
7037         if (IS_PINEVIEW(dev)) {
7038                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7039                 if (reduced_clock)
7040                         fp2 = pnv_dpll_compute_fp(reduced_clock);
7041         } else {
7042                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7043                 if (reduced_clock)
7044                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
7045         }
7046
7047         crtc_state->dpll_hw_state.fp0 = fp;
7048
7049         crtc->lowfreq_avail = false;
7050         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7051             reduced_clock) {
7052                 crtc_state->dpll_hw_state.fp1 = fp2;
7053                 crtc->lowfreq_avail = true;
7054         } else {
7055                 crtc_state->dpll_hw_state.fp1 = fp;
7056         }
7057 }
7058
7059 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7060                 pipe)
7061 {
7062         u32 reg_val;
7063
7064         /*
7065          * PLLB opamp always calibrates to max value of 0x3f, force enable it
7066          * and set it to a reasonable value instead.
7067          */
7068         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7069         reg_val &= 0xffffff00;
7070         reg_val |= 0x00000030;
7071         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7072
7073         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7074         reg_val &= 0x8cffffff;
7075         reg_val = 0x8c000000;
7076         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7077
7078         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7079         reg_val &= 0xffffff00;
7080         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7081
7082         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7083         reg_val &= 0x00ffffff;
7084         reg_val |= 0xb0000000;
7085         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7086 }
7087
7088 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7089                                          struct intel_link_m_n *m_n)
7090 {
7091         struct drm_device *dev = crtc->base.dev;
7092         struct drm_i915_private *dev_priv = dev->dev_private;
7093         int pipe = crtc->pipe;
7094
7095         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7096         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7097         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7098         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7099 }
7100
7101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7102                                          struct intel_link_m_n *m_n,
7103                                          struct intel_link_m_n *m2_n2)
7104 {
7105         struct drm_device *dev = crtc->base.dev;
7106         struct drm_i915_private *dev_priv = dev->dev_private;
7107         int pipe = crtc->pipe;
7108         enum transcoder transcoder = crtc->config->cpu_transcoder;
7109
7110         if (INTEL_INFO(dev)->gen >= 5) {
7111                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7112                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7113                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7114                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7115                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7116                  * for gen < 8) and if DRRS is supported (to make sure the
7117                  * registers are not unnecessarily accessed).
7118                  */
7119                 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7120                         crtc->config->has_drrs) {
7121                         I915_WRITE(PIPE_DATA_M2(transcoder),
7122                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7123                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7124                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7125                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7126                 }
7127         } else {
7128                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7129                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7130                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7131                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7132         }
7133 }
7134
7135 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7136 {
7137         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7138
7139         if (m_n == M1_N1) {
7140                 dp_m_n = &crtc->config->dp_m_n;
7141                 dp_m2_n2 = &crtc->config->dp_m2_n2;
7142         } else if (m_n == M2_N2) {
7143
7144                 /*
7145                  * M2_N2 registers are not supported. Hence m2_n2 divider value
7146                  * needs to be programmed into M1_N1.
7147                  */
7148                 dp_m_n = &crtc->config->dp_m2_n2;
7149         } else {
7150                 DRM_ERROR("Unsupported divider value\n");
7151                 return;
7152         }
7153
7154         if (crtc->config->has_pch_encoder)
7155                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7156         else
7157                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7158 }
7159
7160 static void vlv_compute_dpll(struct intel_crtc *crtc,
7161                              struct intel_crtc_state *pipe_config)
7162 {
7163         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7164                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7165         if (crtc->pipe != PIPE_A)
7166                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7167
7168         /* DPLL not used with DSI, but still need the rest set up */
7169         if (!pipe_config->has_dsi_encoder)
7170                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7171                         DPLL_EXT_BUFFER_ENABLE_VLV;
7172
7173         pipe_config->dpll_hw_state.dpll_md =
7174                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7175 }
7176
7177 static void chv_compute_dpll(struct intel_crtc *crtc,
7178                              struct intel_crtc_state *pipe_config)
7179 {
7180         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7181                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7182         if (crtc->pipe != PIPE_A)
7183                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7184
7185         /* DPLL not used with DSI, but still need the rest set up */
7186         if (!pipe_config->has_dsi_encoder)
7187                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7188
7189         pipe_config->dpll_hw_state.dpll_md =
7190                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7191 }
7192
7193 static void vlv_prepare_pll(struct intel_crtc *crtc,
7194                             const struct intel_crtc_state *pipe_config)
7195 {
7196         struct drm_device *dev = crtc->base.dev;
7197         struct drm_i915_private *dev_priv = dev->dev_private;
7198         enum pipe pipe = crtc->pipe;
7199         u32 mdiv;
7200         u32 bestn, bestm1, bestm2, bestp1, bestp2;
7201         u32 coreclk, reg_val;
7202
7203         /* Enable Refclk */
7204         I915_WRITE(DPLL(pipe),
7205                    pipe_config->dpll_hw_state.dpll &
7206                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7207
7208         /* No need to actually set up the DPLL with DSI */
7209         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7210                 return;
7211
7212         mutex_lock(&dev_priv->sb_lock);
7213
7214         bestn = pipe_config->dpll.n;
7215         bestm1 = pipe_config->dpll.m1;
7216         bestm2 = pipe_config->dpll.m2;
7217         bestp1 = pipe_config->dpll.p1;
7218         bestp2 = pipe_config->dpll.p2;
7219
7220         /* See eDP HDMI DPIO driver vbios notes doc */
7221
7222         /* PLL B needs special handling */
7223         if (pipe == PIPE_B)
7224                 vlv_pllb_recal_opamp(dev_priv, pipe);
7225
7226         /* Set up Tx target for periodic Rcomp update */
7227         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7228
7229         /* Disable target IRef on PLL */
7230         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7231         reg_val &= 0x00ffffff;
7232         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7233
7234         /* Disable fast lock */
7235         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7236
7237         /* Set idtafcrecal before PLL is enabled */
7238         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7239         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7240         mdiv |= ((bestn << DPIO_N_SHIFT));
7241         mdiv |= (1 << DPIO_K_SHIFT);
7242
7243         /*
7244          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7245          * but we don't support that).
7246          * Note: don't use the DAC post divider as it seems unstable.
7247          */
7248         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7249         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7250
7251         mdiv |= DPIO_ENABLE_CALIBRATION;
7252         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7253
7254         /* Set HBR and RBR LPF coefficients */
7255         if (pipe_config->port_clock == 162000 ||
7256             intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7257             intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7258                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7259                                  0x009f0003);
7260         else
7261                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7262                                  0x00d0000f);
7263
7264         if (pipe_config->has_dp_encoder) {
7265                 /* Use SSC source */
7266                 if (pipe == PIPE_A)
7267                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7268                                          0x0df40000);
7269                 else
7270                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7271                                          0x0df70000);
7272         } else { /* HDMI or VGA */
7273                 /* Use bend source */
7274                 if (pipe == PIPE_A)
7275                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7276                                          0x0df70000);
7277                 else
7278                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7279                                          0x0df40000);
7280         }
7281
7282         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7283         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7284         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7285             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7286                 coreclk |= 0x01000000;
7287         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7288
7289         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7290         mutex_unlock(&dev_priv->sb_lock);
7291 }
7292
7293 static void chv_prepare_pll(struct intel_crtc *crtc,
7294                             const struct intel_crtc_state *pipe_config)
7295 {
7296         struct drm_device *dev = crtc->base.dev;
7297         struct drm_i915_private *dev_priv = dev->dev_private;
7298         enum pipe pipe = crtc->pipe;
7299         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7300         u32 loopfilter, tribuf_calcntr;
7301         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7302         u32 dpio_val;
7303         int vco;
7304
7305         /* Enable Refclk and SSC */
7306         I915_WRITE(DPLL(pipe),
7307                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7308
7309         /* No need to actually set up the DPLL with DSI */
7310         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7311                 return;
7312
7313         bestn = pipe_config->dpll.n;
7314         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7315         bestm1 = pipe_config->dpll.m1;
7316         bestm2 = pipe_config->dpll.m2 >> 22;
7317         bestp1 = pipe_config->dpll.p1;
7318         bestp2 = pipe_config->dpll.p2;
7319         vco = pipe_config->dpll.vco;
7320         dpio_val = 0;
7321         loopfilter = 0;
7322
7323         mutex_lock(&dev_priv->sb_lock);
7324
7325         /* p1 and p2 divider */
7326         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7327                         5 << DPIO_CHV_S1_DIV_SHIFT |
7328                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7329                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7330                         1 << DPIO_CHV_K_DIV_SHIFT);
7331
7332         /* Feedback post-divider - m2 */
7333         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7334
7335         /* Feedback refclk divider - n and m1 */
7336         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7337                         DPIO_CHV_M1_DIV_BY_2 |
7338                         1 << DPIO_CHV_N_DIV_SHIFT);
7339
7340         /* M2 fraction division */
7341         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7342
7343         /* M2 fraction division enable */
7344         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7345         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7346         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7347         if (bestm2_frac)
7348                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7349         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7350
7351         /* Program digital lock detect threshold */
7352         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7353         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7354                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7355         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7356         if (!bestm2_frac)
7357                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7358         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7359
7360         /* Loop filter */
7361         if (vco == 5400000) {
7362                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7363                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7364                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7365                 tribuf_calcntr = 0x9;
7366         } else if (vco <= 6200000) {
7367                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7368                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7369                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7370                 tribuf_calcntr = 0x9;
7371         } else if (vco <= 6480000) {
7372                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7373                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7374                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7375                 tribuf_calcntr = 0x8;
7376         } else {
7377                 /* Not supported. Apply the same limits as in the max case */
7378                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7379                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7380                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7381                 tribuf_calcntr = 0;
7382         }
7383         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7384
7385         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7386         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7387         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7388         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7389
7390         /* AFC Recal */
7391         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7392                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7393                         DPIO_AFC_RECAL);
7394
7395         mutex_unlock(&dev_priv->sb_lock);
7396 }
7397
7398 /**
7399  * vlv_force_pll_on - forcibly enable just the PLL
7400  * @dev_priv: i915 private structure
7401  * @pipe: pipe PLL to enable
7402  * @dpll: PLL configuration
7403  *
7404  * Enable the PLL for @pipe using the supplied @dpll config. To be used
7405  * in cases where we need the PLL enabled even when @pipe is not going to
7406  * be enabled.
7407  */
7408 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7409                      const struct dpll *dpll)
7410 {
7411         struct intel_crtc *crtc =
7412                 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7413         struct intel_crtc_state *pipe_config;
7414
7415         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7416         if (!pipe_config)
7417                 return -ENOMEM;
7418
7419         pipe_config->base.crtc = &crtc->base;
7420         pipe_config->pixel_multiplier = 1;
7421         pipe_config->dpll = *dpll;
7422
7423         if (IS_CHERRYVIEW(dev)) {
7424                 chv_compute_dpll(crtc, pipe_config);
7425                 chv_prepare_pll(crtc, pipe_config);
7426                 chv_enable_pll(crtc, pipe_config);
7427         } else {
7428                 vlv_compute_dpll(crtc, pipe_config);
7429                 vlv_prepare_pll(crtc, pipe_config);
7430                 vlv_enable_pll(crtc, pipe_config);
7431         }
7432
7433         kfree(pipe_config);
7434
7435         return 0;
7436 }
7437
7438 /**
7439  * vlv_force_pll_off - forcibly disable just the PLL
7440  * @dev_priv: i915 private structure
7441  * @pipe: pipe PLL to disable
7442  *
7443  * Disable the PLL for @pipe. To be used in cases where we need
7444  * the PLL enabled even when @pipe is not going to be enabled.
7445  */
7446 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7447 {
7448         if (IS_CHERRYVIEW(dev))
7449                 chv_disable_pll(to_i915(dev), pipe);
7450         else
7451                 vlv_disable_pll(to_i915(dev), pipe);
7452 }
7453
7454 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7455                               struct intel_crtc_state *crtc_state,
7456                               struct dpll *reduced_clock)
7457 {
7458         struct drm_device *dev = crtc->base.dev;
7459         struct drm_i915_private *dev_priv = dev->dev_private;
7460         u32 dpll;
7461         bool is_sdvo;
7462         struct dpll *clock = &crtc_state->dpll;
7463
7464         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7465
7466         is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7467                 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7468
7469         dpll = DPLL_VGA_MODE_DIS;
7470
7471         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7472                 dpll |= DPLLB_MODE_LVDS;
7473         else
7474                 dpll |= DPLLB_MODE_DAC_SERIAL;
7475
7476         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7477                 dpll |= (crtc_state->pixel_multiplier - 1)
7478                         << SDVO_MULTIPLIER_SHIFT_HIRES;
7479         }
7480
7481         if (is_sdvo)
7482                 dpll |= DPLL_SDVO_HIGH_SPEED;
7483
7484         if (crtc_state->has_dp_encoder)
7485                 dpll |= DPLL_SDVO_HIGH_SPEED;
7486
7487         /* compute bitmask from p1 value */
7488         if (IS_PINEVIEW(dev))
7489                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7490         else {
7491                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7492                 if (IS_G4X(dev) && reduced_clock)
7493                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7494         }
7495         switch (clock->p2) {
7496         case 5:
7497                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7498                 break;
7499         case 7:
7500                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7501                 break;
7502         case 10:
7503                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7504                 break;
7505         case 14:
7506                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7507                 break;
7508         }
7509         if (INTEL_INFO(dev)->gen >= 4)
7510                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7511
7512         if (crtc_state->sdvo_tv_clock)
7513                 dpll |= PLL_REF_INPUT_TVCLKINBC;
7514         else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7515                  intel_panel_use_ssc(dev_priv))
7516                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7517         else
7518                 dpll |= PLL_REF_INPUT_DREFCLK;
7519
7520         dpll |= DPLL_VCO_ENABLE;
7521         crtc_state->dpll_hw_state.dpll = dpll;
7522
7523         if (INTEL_INFO(dev)->gen >= 4) {
7524                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7525                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7526                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7527         }
7528 }
7529
7530 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7531                               struct intel_crtc_state *crtc_state,
7532                               struct dpll *reduced_clock)
7533 {
7534         struct drm_device *dev = crtc->base.dev;
7535         struct drm_i915_private *dev_priv = dev->dev_private;
7536         u32 dpll;
7537         struct dpll *clock = &crtc_state->dpll;
7538
7539         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7540
7541         dpll = DPLL_VGA_MODE_DIS;
7542
7543         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7544                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7545         } else {
7546                 if (clock->p1 == 2)
7547                         dpll |= PLL_P1_DIVIDE_BY_TWO;
7548                 else
7549                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7550                 if (clock->p2 == 4)
7551                         dpll |= PLL_P2_DIVIDE_BY_4;
7552         }
7553
7554         if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7555                 dpll |= DPLL_DVO_2X_MODE;
7556
7557         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7558             intel_panel_use_ssc(dev_priv))
7559                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7560         else
7561                 dpll |= PLL_REF_INPUT_DREFCLK;
7562
7563         dpll |= DPLL_VCO_ENABLE;
7564         crtc_state->dpll_hw_state.dpll = dpll;
7565 }
7566
7567 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7568 {
7569         struct drm_device *dev = intel_crtc->base.dev;
7570         struct drm_i915_private *dev_priv = dev->dev_private;
7571         enum pipe pipe = intel_crtc->pipe;
7572         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7573         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7574         uint32_t crtc_vtotal, crtc_vblank_end;
7575         int vsyncshift = 0;
7576
7577         /* We need to be careful not to changed the adjusted mode, for otherwise
7578          * the hw state checker will get angry at the mismatch. */
7579         crtc_vtotal = adjusted_mode->crtc_vtotal;
7580         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7581
7582         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7583                 /* the chip adds 2 halflines automatically */
7584                 crtc_vtotal -= 1;
7585                 crtc_vblank_end -= 1;
7586
7587                 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7588                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7589                 else
7590                         vsyncshift = adjusted_mode->crtc_hsync_start -
7591                                 adjusted_mode->crtc_htotal / 2;
7592                 if (vsyncshift < 0)
7593                         vsyncshift += adjusted_mode->crtc_htotal;
7594         }
7595
7596         if (INTEL_INFO(dev)->gen > 3)
7597                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7598
7599         I915_WRITE(HTOTAL(cpu_transcoder),
7600                    (adjusted_mode->crtc_hdisplay - 1) |
7601                    ((adjusted_mode->crtc_htotal - 1) << 16));
7602         I915_WRITE(HBLANK(cpu_transcoder),
7603                    (adjusted_mode->crtc_hblank_start - 1) |
7604                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
7605         I915_WRITE(HSYNC(cpu_transcoder),
7606                    (adjusted_mode->crtc_hsync_start - 1) |
7607                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
7608
7609         I915_WRITE(VTOTAL(cpu_transcoder),
7610                    (adjusted_mode->crtc_vdisplay - 1) |
7611                    ((crtc_vtotal - 1) << 16));
7612         I915_WRITE(VBLANK(cpu_transcoder),
7613                    (adjusted_mode->crtc_vblank_start - 1) |
7614                    ((crtc_vblank_end - 1) << 16));
7615         I915_WRITE(VSYNC(cpu_transcoder),
7616                    (adjusted_mode->crtc_vsync_start - 1) |
7617                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
7618
7619         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7620          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7621          * documented on the DDI_FUNC_CTL register description, EDP Input Select
7622          * bits. */
7623         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7624             (pipe == PIPE_B || pipe == PIPE_C))
7625                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7626
7627 }
7628
7629 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7630 {
7631         struct drm_device *dev = intel_crtc->base.dev;
7632         struct drm_i915_private *dev_priv = dev->dev_private;
7633         enum pipe pipe = intel_crtc->pipe;
7634
7635         /* pipesrc controls the size that is scaled from, which should
7636          * always be the user's requested size.
7637          */
7638         I915_WRITE(PIPESRC(pipe),
7639                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
7640                    (intel_crtc->config->pipe_src_h - 1));
7641 }
7642
7643 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7644                                    struct intel_crtc_state *pipe_config)
7645 {
7646         struct drm_device *dev = crtc->base.dev;
7647         struct drm_i915_private *dev_priv = dev->dev_private;
7648         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7649         uint32_t tmp;
7650
7651         tmp = I915_READ(HTOTAL(cpu_transcoder));
7652         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7653         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7654         tmp = I915_READ(HBLANK(cpu_transcoder));
7655         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7656         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7657         tmp = I915_READ(HSYNC(cpu_transcoder));
7658         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7659         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7660
7661         tmp = I915_READ(VTOTAL(cpu_transcoder));
7662         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7663         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7664         tmp = I915_READ(VBLANK(cpu_transcoder));
7665         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7666         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7667         tmp = I915_READ(VSYNC(cpu_transcoder));
7668         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7669         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7670
7671         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7672                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7673                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7674                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7675         }
7676 }
7677
7678 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7679                                     struct intel_crtc_state *pipe_config)
7680 {
7681         struct drm_device *dev = crtc->base.dev;
7682         struct drm_i915_private *dev_priv = dev->dev_private;
7683         u32 tmp;
7684
7685         tmp = I915_READ(PIPESRC(crtc->pipe));
7686         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7687         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7688
7689         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7690         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7691 }
7692
7693 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7694                                  struct intel_crtc_state *pipe_config)
7695 {
7696         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7697         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7698         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7699         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7700
7701         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7702         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7703         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7704         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7705
7706         mode->flags = pipe_config->base.adjusted_mode.flags;
7707         mode->type = DRM_MODE_TYPE_DRIVER;
7708
7709         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7710         mode->flags |= pipe_config->base.adjusted_mode.flags;
7711
7712         mode->hsync = drm_mode_hsync(mode);
7713         mode->vrefresh = drm_mode_vrefresh(mode);
7714         drm_mode_set_name(mode);
7715 }
7716
7717 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7718 {
7719         struct drm_device *dev = intel_crtc->base.dev;
7720         struct drm_i915_private *dev_priv = dev->dev_private;
7721         uint32_t pipeconf;
7722
7723         pipeconf = 0;
7724
7725         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7726             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7727                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7728
7729         if (intel_crtc->config->double_wide)
7730                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7731
7732         /* only g4x and later have fancy bpc/dither controls */
7733         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7734                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7735                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7736                         pipeconf |= PIPECONF_DITHER_EN |
7737                                     PIPECONF_DITHER_TYPE_SP;
7738
7739                 switch (intel_crtc->config->pipe_bpp) {
7740                 case 18:
7741                         pipeconf |= PIPECONF_6BPC;
7742                         break;
7743                 case 24:
7744                         pipeconf |= PIPECONF_8BPC;
7745                         break;
7746                 case 30:
7747                         pipeconf |= PIPECONF_10BPC;
7748                         break;
7749                 default:
7750                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7751                         BUG();
7752                 }
7753         }
7754
7755         if (HAS_PIPE_CXSR(dev)) {
7756                 if (intel_crtc->lowfreq_avail) {
7757                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7758                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7759                 } else {
7760                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7761                 }
7762         }
7763
7764         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7765                 if (INTEL_INFO(dev)->gen < 4 ||
7766                     intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7767                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7768                 else
7769                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7770         } else
7771                 pipeconf |= PIPECONF_PROGRESSIVE;
7772
7773         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7774              intel_crtc->config->limited_color_range)
7775                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7776
7777         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7778         POSTING_READ(PIPECONF(intel_crtc->pipe));
7779 }
7780
7781 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7782                                    struct intel_crtc_state *crtc_state)
7783 {
7784         struct drm_device *dev = crtc->base.dev;
7785         struct drm_i915_private *dev_priv = dev->dev_private;
7786         const struct intel_limit *limit;
7787         int refclk = 48000;
7788
7789         memset(&crtc_state->dpll_hw_state, 0,
7790                sizeof(crtc_state->dpll_hw_state));
7791
7792         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7793                 if (intel_panel_use_ssc(dev_priv)) {
7794                         refclk = dev_priv->vbt.lvds_ssc_freq;
7795                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7796                 }
7797
7798                 limit = &intel_limits_i8xx_lvds;
7799         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7800                 limit = &intel_limits_i8xx_dvo;
7801         } else {
7802                 limit = &intel_limits_i8xx_dac;
7803         }
7804
7805         if (!crtc_state->clock_set &&
7806             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7807                                  refclk, NULL, &crtc_state->dpll)) {
7808                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7809                 return -EINVAL;
7810         }
7811
7812         i8xx_compute_dpll(crtc, crtc_state, NULL);
7813
7814         return 0;
7815 }
7816
7817 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7818                                   struct intel_crtc_state *crtc_state)
7819 {
7820         struct drm_device *dev = crtc->base.dev;
7821         struct drm_i915_private *dev_priv = dev->dev_private;
7822         const struct intel_limit *limit;
7823         int refclk = 96000;
7824
7825         memset(&crtc_state->dpll_hw_state, 0,
7826                sizeof(crtc_state->dpll_hw_state));
7827
7828         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7829                 if (intel_panel_use_ssc(dev_priv)) {
7830                         refclk = dev_priv->vbt.lvds_ssc_freq;
7831                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7832                 }
7833
7834                 if (intel_is_dual_link_lvds(dev))
7835                         limit = &intel_limits_g4x_dual_channel_lvds;
7836                 else
7837                         limit = &intel_limits_g4x_single_channel_lvds;
7838         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7839                    intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7840                 limit = &intel_limits_g4x_hdmi;
7841         } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7842                 limit = &intel_limits_g4x_sdvo;
7843         } else {
7844                 /* The option is for other outputs */
7845                 limit = &intel_limits_i9xx_sdvo;
7846         }
7847
7848         if (!crtc_state->clock_set &&
7849             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7850                                 refclk, NULL, &crtc_state->dpll)) {
7851                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7852                 return -EINVAL;
7853         }
7854
7855         i9xx_compute_dpll(crtc, crtc_state, NULL);
7856
7857         return 0;
7858 }
7859
7860 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7861                                   struct intel_crtc_state *crtc_state)
7862 {
7863         struct drm_device *dev = crtc->base.dev;
7864         struct drm_i915_private *dev_priv = dev->dev_private;
7865         const struct intel_limit *limit;
7866         int refclk = 96000;
7867
7868         memset(&crtc_state->dpll_hw_state, 0,
7869                sizeof(crtc_state->dpll_hw_state));
7870
7871         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7872                 if (intel_panel_use_ssc(dev_priv)) {
7873                         refclk = dev_priv->vbt.lvds_ssc_freq;
7874                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7875                 }
7876
7877                 limit = &intel_limits_pineview_lvds;
7878         } else {
7879                 limit = &intel_limits_pineview_sdvo;
7880         }
7881
7882         if (!crtc_state->clock_set &&
7883             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7884                                 refclk, NULL, &crtc_state->dpll)) {
7885                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7886                 return -EINVAL;
7887         }
7888
7889         i9xx_compute_dpll(crtc, crtc_state, NULL);
7890
7891         return 0;
7892 }
7893
7894 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7895                                    struct intel_crtc_state *crtc_state)
7896 {
7897         struct drm_device *dev = crtc->base.dev;
7898         struct drm_i915_private *dev_priv = dev->dev_private;
7899         const struct intel_limit *limit;
7900         int refclk = 96000;
7901
7902         memset(&crtc_state->dpll_hw_state, 0,
7903                sizeof(crtc_state->dpll_hw_state));
7904
7905         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7906                 if (intel_panel_use_ssc(dev_priv)) {
7907                         refclk = dev_priv->vbt.lvds_ssc_freq;
7908                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7909                 }
7910
7911                 limit = &intel_limits_i9xx_lvds;
7912         } else {
7913                 limit = &intel_limits_i9xx_sdvo;
7914         }
7915
7916         if (!crtc_state->clock_set &&
7917             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7918                                  refclk, NULL, &crtc_state->dpll)) {
7919                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7920                 return -EINVAL;
7921         }
7922
7923         i9xx_compute_dpll(crtc, crtc_state, NULL);
7924
7925         return 0;
7926 }
7927
7928 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7929                                   struct intel_crtc_state *crtc_state)
7930 {
7931         int refclk = 100000;
7932         const struct intel_limit *limit = &intel_limits_chv;
7933
7934         memset(&crtc_state->dpll_hw_state, 0,
7935                sizeof(crtc_state->dpll_hw_state));
7936
7937         if (!crtc_state->clock_set &&
7938             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7939                                 refclk, NULL, &crtc_state->dpll)) {
7940                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7941                 return -EINVAL;
7942         }
7943
7944         chv_compute_dpll(crtc, crtc_state);
7945
7946         return 0;
7947 }
7948
7949 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7950                                   struct intel_crtc_state *crtc_state)
7951 {
7952         int refclk = 100000;
7953         const struct intel_limit *limit = &intel_limits_vlv;
7954
7955         memset(&crtc_state->dpll_hw_state, 0,
7956                sizeof(crtc_state->dpll_hw_state));
7957
7958         if (!crtc_state->clock_set &&
7959             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7960                                 refclk, NULL, &crtc_state->dpll)) {
7961                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7962                 return -EINVAL;
7963         }
7964
7965         vlv_compute_dpll(crtc, crtc_state);
7966
7967         return 0;
7968 }
7969
7970 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7971                                  struct intel_crtc_state *pipe_config)
7972 {
7973         struct drm_device *dev = crtc->base.dev;
7974         struct drm_i915_private *dev_priv = dev->dev_private;
7975         uint32_t tmp;
7976
7977         if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7978                 return;
7979
7980         tmp = I915_READ(PFIT_CONTROL);
7981         if (!(tmp & PFIT_ENABLE))
7982                 return;
7983
7984         /* Check whether the pfit is attached to our pipe. */
7985         if (INTEL_INFO(dev)->gen < 4) {
7986                 if (crtc->pipe != PIPE_B)
7987                         return;
7988         } else {
7989                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7990                         return;
7991         }
7992
7993         pipe_config->gmch_pfit.control = tmp;
7994         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7995 }
7996
7997 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7998                                struct intel_crtc_state *pipe_config)
7999 {
8000         struct drm_device *dev = crtc->base.dev;
8001         struct drm_i915_private *dev_priv = dev->dev_private;
8002         int pipe = pipe_config->cpu_transcoder;
8003         struct dpll clock;
8004         u32 mdiv;
8005         int refclk = 100000;
8006
8007         /* In case of DSI, DPLL will not be used */
8008         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8009                 return;
8010
8011         mutex_lock(&dev_priv->sb_lock);
8012         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8013         mutex_unlock(&dev_priv->sb_lock);
8014
8015         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8016         clock.m2 = mdiv & DPIO_M2DIV_MASK;
8017         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8018         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8019         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8020
8021         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8022 }
8023
8024 static void
8025 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8026                               struct intel_initial_plane_config *plane_config)
8027 {
8028         struct drm_device *dev = crtc->base.dev;
8029         struct drm_i915_private *dev_priv = dev->dev_private;
8030         u32 val, base, offset;
8031         int pipe = crtc->pipe, plane = crtc->plane;
8032         int fourcc, pixel_format;
8033         unsigned int aligned_height;
8034         struct drm_framebuffer *fb;
8035         struct intel_framebuffer *intel_fb;
8036
8037         val = I915_READ(DSPCNTR(plane));
8038         if (!(val & DISPLAY_PLANE_ENABLE))
8039                 return;
8040
8041         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8042         if (!intel_fb) {
8043                 DRM_DEBUG_KMS("failed to alloc fb\n");
8044                 return;
8045         }
8046
8047         fb = &intel_fb->base;
8048
8049         if (INTEL_INFO(dev)->gen >= 4) {
8050                 if (val & DISPPLANE_TILED) {
8051                         plane_config->tiling = I915_TILING_X;
8052                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8053                 }
8054         }
8055
8056         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8057         fourcc = i9xx_format_to_fourcc(pixel_format);
8058         fb->pixel_format = fourcc;
8059         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8060
8061         if (INTEL_INFO(dev)->gen >= 4) {
8062                 if (plane_config->tiling)
8063                         offset = I915_READ(DSPTILEOFF(plane));
8064                 else
8065                         offset = I915_READ(DSPLINOFF(plane));
8066                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8067         } else {
8068                 base = I915_READ(DSPADDR(plane));
8069         }
8070         plane_config->base = base;
8071
8072         val = I915_READ(PIPESRC(pipe));
8073         fb->width = ((val >> 16) & 0xfff) + 1;
8074         fb->height = ((val >> 0) & 0xfff) + 1;
8075
8076         val = I915_READ(DSPSTRIDE(pipe));
8077         fb->pitches[0] = val & 0xffffffc0;
8078
8079         aligned_height = intel_fb_align_height(dev, fb->height,
8080                                                fb->pixel_format,
8081                                                fb->modifier[0]);
8082
8083         plane_config->size = fb->pitches[0] * aligned_height;
8084
8085         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8086                       pipe_name(pipe), plane, fb->width, fb->height,
8087                       fb->bits_per_pixel, base, fb->pitches[0],
8088                       plane_config->size);
8089
8090         plane_config->fb = intel_fb;
8091 }
8092
8093 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8094                                struct intel_crtc_state *pipe_config)
8095 {
8096         struct drm_device *dev = crtc->base.dev;
8097         struct drm_i915_private *dev_priv = dev->dev_private;
8098         int pipe = pipe_config->cpu_transcoder;
8099         enum dpio_channel port = vlv_pipe_to_channel(pipe);
8100         struct dpll clock;
8101         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8102         int refclk = 100000;
8103
8104         /* In case of DSI, DPLL will not be used */
8105         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8106                 return;
8107
8108         mutex_lock(&dev_priv->sb_lock);
8109         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8110         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8111         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8112         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8113         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8114         mutex_unlock(&dev_priv->sb_lock);
8115
8116         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8117         clock.m2 = (pll_dw0 & 0xff) << 22;
8118         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8119                 clock.m2 |= pll_dw2 & 0x3fffff;
8120         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8121         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8122         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8123
8124         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8125 }
8126
8127 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8128                                  struct intel_crtc_state *pipe_config)
8129 {
8130         struct drm_device *dev = crtc->base.dev;
8131         struct drm_i915_private *dev_priv = dev->dev_private;
8132         enum intel_display_power_domain power_domain;
8133         uint32_t tmp;
8134         bool ret;
8135
8136         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8137         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8138                 return false;
8139
8140         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8141         pipe_config->shared_dpll = NULL;
8142
8143         ret = false;
8144
8145         tmp = I915_READ(PIPECONF(crtc->pipe));
8146         if (!(tmp & PIPECONF_ENABLE))
8147                 goto out;
8148
8149         if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8150                 switch (tmp & PIPECONF_BPC_MASK) {
8151                 case PIPECONF_6BPC:
8152                         pipe_config->pipe_bpp = 18;
8153                         break;
8154                 case PIPECONF_8BPC:
8155                         pipe_config->pipe_bpp = 24;
8156                         break;
8157                 case PIPECONF_10BPC:
8158                         pipe_config->pipe_bpp = 30;
8159                         break;
8160                 default:
8161                         break;
8162                 }
8163         }
8164
8165         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8166             (tmp & PIPECONF_COLOR_RANGE_SELECT))
8167                 pipe_config->limited_color_range = true;
8168
8169         if (INTEL_INFO(dev)->gen < 4)
8170                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8171
8172         intel_get_pipe_timings(crtc, pipe_config);
8173         intel_get_pipe_src_size(crtc, pipe_config);
8174
8175         i9xx_get_pfit_config(crtc, pipe_config);
8176
8177         if (INTEL_INFO(dev)->gen >= 4) {
8178                 /* No way to read it out on pipes B and C */
8179                 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8180                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
8181                 else
8182                         tmp = I915_READ(DPLL_MD(crtc->pipe));
8183                 pipe_config->pixel_multiplier =
8184                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8185                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8186                 pipe_config->dpll_hw_state.dpll_md = tmp;
8187         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8188                 tmp = I915_READ(DPLL(crtc->pipe));
8189                 pipe_config->pixel_multiplier =
8190                         ((tmp & SDVO_MULTIPLIER_MASK)
8191                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8192         } else {
8193                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8194                  * port and will be fixed up in the encoder->get_config
8195                  * function. */
8196                 pipe_config->pixel_multiplier = 1;
8197         }
8198         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8199         if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8200                 /*
8201                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8202                  * on 830. Filter it out here so that we don't
8203                  * report errors due to that.
8204                  */
8205                 if (IS_I830(dev))
8206                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8207
8208                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8209                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8210         } else {
8211                 /* Mask out read-only status bits. */
8212                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8213                                                      DPLL_PORTC_READY_MASK |
8214                                                      DPLL_PORTB_READY_MASK);
8215         }
8216
8217         if (IS_CHERRYVIEW(dev))
8218                 chv_crtc_clock_get(crtc, pipe_config);
8219         else if (IS_VALLEYVIEW(dev))
8220                 vlv_crtc_clock_get(crtc, pipe_config);
8221         else
8222                 i9xx_crtc_clock_get(crtc, pipe_config);
8223
8224         /*
8225          * Normally the dotclock is filled in by the encoder .get_config()
8226          * but in case the pipe is enabled w/o any ports we need a sane
8227          * default.
8228          */
8229         pipe_config->base.adjusted_mode.crtc_clock =
8230                 pipe_config->port_clock / pipe_config->pixel_multiplier;
8231
8232         ret = true;
8233
8234 out:
8235         intel_display_power_put(dev_priv, power_domain);
8236
8237         return ret;
8238 }
8239
8240 static void ironlake_init_pch_refclk(struct drm_device *dev)
8241 {
8242         struct drm_i915_private *dev_priv = dev->dev_private;
8243         struct intel_encoder *encoder;
8244         u32 val, final;
8245         bool has_lvds = false;
8246         bool has_cpu_edp = false;
8247         bool has_panel = false;
8248         bool has_ck505 = false;
8249         bool can_ssc = false;
8250
8251         /* We need to take the global config into account */
8252         for_each_intel_encoder(dev, encoder) {
8253                 switch (encoder->type) {
8254                 case INTEL_OUTPUT_LVDS:
8255                         has_panel = true;
8256                         has_lvds = true;
8257                         break;
8258                 case INTEL_OUTPUT_EDP:
8259                         has_panel = true;
8260                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8261                                 has_cpu_edp = true;
8262                         break;
8263                 default:
8264                         break;
8265                 }
8266         }
8267
8268         if (HAS_PCH_IBX(dev)) {
8269                 has_ck505 = dev_priv->vbt.display_clock_mode;
8270                 can_ssc = has_ck505;
8271         } else {
8272                 has_ck505 = false;
8273                 can_ssc = true;
8274         }
8275
8276         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8277                       has_panel, has_lvds, has_ck505);
8278
8279         /* Ironlake: try to setup display ref clock before DPLL
8280          * enabling. This is only under driver's control after
8281          * PCH B stepping, previous chipset stepping should be
8282          * ignoring this setting.
8283          */
8284         val = I915_READ(PCH_DREF_CONTROL);
8285
8286         /* As we must carefully and slowly disable/enable each source in turn,
8287          * compute the final state we want first and check if we need to
8288          * make any changes at all.
8289          */
8290         final = val;
8291         final &= ~DREF_NONSPREAD_SOURCE_MASK;
8292         if (has_ck505)
8293                 final |= DREF_NONSPREAD_CK505_ENABLE;
8294         else
8295                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8296
8297         final &= ~DREF_SSC_SOURCE_MASK;
8298         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8299         final &= ~DREF_SSC1_ENABLE;
8300
8301         if (has_panel) {
8302                 final |= DREF_SSC_SOURCE_ENABLE;
8303
8304                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8305                         final |= DREF_SSC1_ENABLE;
8306
8307                 if (has_cpu_edp) {
8308                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
8309                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8310                         else
8311                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8312                 } else
8313                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8314         } else {
8315                 final |= DREF_SSC_SOURCE_DISABLE;
8316                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8317         }
8318
8319         if (final == val)
8320                 return;
8321
8322         /* Always enable nonspread source */
8323         val &= ~DREF_NONSPREAD_SOURCE_MASK;
8324
8325         if (has_ck505)
8326                 val |= DREF_NONSPREAD_CK505_ENABLE;
8327         else
8328                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8329
8330         if (has_panel) {
8331                 val &= ~DREF_SSC_SOURCE_MASK;
8332                 val |= DREF_SSC_SOURCE_ENABLE;
8333
8334                 /* SSC must be turned on before enabling the CPU output  */
8335                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8336                         DRM_DEBUG_KMS("Using SSC on panel\n");
8337                         val |= DREF_SSC1_ENABLE;
8338                 } else
8339                         val &= ~DREF_SSC1_ENABLE;
8340
8341                 /* Get SSC going before enabling the outputs */
8342                 I915_WRITE(PCH_DREF_CONTROL, val);
8343                 POSTING_READ(PCH_DREF_CONTROL);
8344                 udelay(200);
8345
8346                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8347
8348                 /* Enable CPU source on CPU attached eDP */
8349                 if (has_cpu_edp) {
8350                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8351                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
8352                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8353                         } else
8354                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8355                 } else
8356                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8357
8358                 I915_WRITE(PCH_DREF_CONTROL, val);
8359                 POSTING_READ(PCH_DREF_CONTROL);
8360                 udelay(200);
8361         } else {
8362                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8363
8364                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8365
8366                 /* Turn off CPU output */
8367                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8368
8369                 I915_WRITE(PCH_DREF_CONTROL, val);
8370                 POSTING_READ(PCH_DREF_CONTROL);
8371                 udelay(200);
8372
8373                 /* Turn off the SSC source */
8374                 val &= ~DREF_SSC_SOURCE_MASK;
8375                 val |= DREF_SSC_SOURCE_DISABLE;
8376
8377                 /* Turn off SSC1 */
8378                 val &= ~DREF_SSC1_ENABLE;
8379
8380                 I915_WRITE(PCH_DREF_CONTROL, val);
8381                 POSTING_READ(PCH_DREF_CONTROL);
8382                 udelay(200);
8383         }
8384
8385         BUG_ON(val != final);
8386 }
8387
8388 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8389 {
8390         uint32_t tmp;
8391
8392         tmp = I915_READ(SOUTH_CHICKEN2);
8393         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8394         I915_WRITE(SOUTH_CHICKEN2, tmp);
8395
8396         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8397                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8398                 DRM_ERROR("FDI mPHY reset assert timeout\n");
8399
8400         tmp = I915_READ(SOUTH_CHICKEN2);
8401         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8402         I915_WRITE(SOUTH_CHICKEN2, tmp);
8403
8404         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8405                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8406                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8407 }
8408
8409 /* WaMPhyProgramming:hsw */
8410 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8411 {
8412         uint32_t tmp;
8413
8414         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8415         tmp &= ~(0xFF << 24);
8416         tmp |= (0x12 << 24);
8417         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8418
8419         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8420         tmp |= (1 << 11);
8421         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8422
8423         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8424         tmp |= (1 << 11);
8425         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8426
8427         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8428         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8429         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8430
8431         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8432         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8433         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8434
8435         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8436         tmp &= ~(7 << 13);
8437         tmp |= (5 << 13);
8438         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8439
8440         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8441         tmp &= ~(7 << 13);
8442         tmp |= (5 << 13);
8443         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8444
8445         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8446         tmp &= ~0xFF;
8447         tmp |= 0x1C;
8448         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8449
8450         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8451         tmp &= ~0xFF;
8452         tmp |= 0x1C;
8453         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8454
8455         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8456         tmp &= ~(0xFF << 16);
8457         tmp |= (0x1C << 16);
8458         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8459
8460         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8461         tmp &= ~(0xFF << 16);
8462         tmp |= (0x1C << 16);
8463         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8464
8465         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8466         tmp |= (1 << 27);
8467         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8468
8469         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8470         tmp |= (1 << 27);
8471         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8472
8473         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8474         tmp &= ~(0xF << 28);
8475         tmp |= (4 << 28);
8476         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8477
8478         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8479         tmp &= ~(0xF << 28);
8480         tmp |= (4 << 28);
8481         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8482 }
8483
8484 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8485  * Programming" based on the parameters passed:
8486  * - Sequence to enable CLKOUT_DP
8487  * - Sequence to enable CLKOUT_DP without spread
8488  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8489  */
8490 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8491                                  bool with_fdi)
8492 {
8493         struct drm_i915_private *dev_priv = dev->dev_private;
8494         uint32_t reg, tmp;
8495
8496         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8497                 with_spread = true;
8498         if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8499                 with_fdi = false;
8500
8501         mutex_lock(&dev_priv->sb_lock);
8502
8503         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8504         tmp &= ~SBI_SSCCTL_DISABLE;
8505         tmp |= SBI_SSCCTL_PATHALT;
8506         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8507
8508         udelay(24);
8509
8510         if (with_spread) {
8511                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8512                 tmp &= ~SBI_SSCCTL_PATHALT;
8513                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8514
8515                 if (with_fdi) {
8516                         lpt_reset_fdi_mphy(dev_priv);
8517                         lpt_program_fdi_mphy(dev_priv);
8518                 }
8519         }
8520
8521         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8522         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8523         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8524         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8525
8526         mutex_unlock(&dev_priv->sb_lock);
8527 }
8528
8529 /* Sequence to disable CLKOUT_DP */
8530 static void lpt_disable_clkout_dp(struct drm_device *dev)
8531 {
8532         struct drm_i915_private *dev_priv = dev->dev_private;
8533         uint32_t reg, tmp;
8534
8535         mutex_lock(&dev_priv->sb_lock);
8536
8537         reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8538         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8539         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8540         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8541
8542         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8543         if (!(tmp & SBI_SSCCTL_DISABLE)) {
8544                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8545                         tmp |= SBI_SSCCTL_PATHALT;
8546                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8547                         udelay(32);
8548                 }
8549                 tmp |= SBI_SSCCTL_DISABLE;
8550                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8551         }
8552
8553         mutex_unlock(&dev_priv->sb_lock);
8554 }
8555
8556 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8557
8558 static const uint16_t sscdivintphase[] = {
8559         [BEND_IDX( 50)] = 0x3B23,
8560         [BEND_IDX( 45)] = 0x3B23,
8561         [BEND_IDX( 40)] = 0x3C23,
8562         [BEND_IDX( 35)] = 0x3C23,
8563         [BEND_IDX( 30)] = 0x3D23,
8564         [BEND_IDX( 25)] = 0x3D23,
8565         [BEND_IDX( 20)] = 0x3E23,
8566         [BEND_IDX( 15)] = 0x3E23,
8567         [BEND_IDX( 10)] = 0x3F23,
8568         [BEND_IDX(  5)] = 0x3F23,
8569         [BEND_IDX(  0)] = 0x0025,
8570         [BEND_IDX( -5)] = 0x0025,
8571         [BEND_IDX(-10)] = 0x0125,
8572         [BEND_IDX(-15)] = 0x0125,
8573         [BEND_IDX(-20)] = 0x0225,
8574         [BEND_IDX(-25)] = 0x0225,
8575         [BEND_IDX(-30)] = 0x0325,
8576         [BEND_IDX(-35)] = 0x0325,
8577         [BEND_IDX(-40)] = 0x0425,
8578         [BEND_IDX(-45)] = 0x0425,
8579         [BEND_IDX(-50)] = 0x0525,
8580 };
8581
8582 /*
8583  * Bend CLKOUT_DP
8584  * steps -50 to 50 inclusive, in steps of 5
8585  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8586  * change in clock period = -(steps / 10) * 5.787 ps
8587  */
8588 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8589 {
8590         uint32_t tmp;
8591         int idx = BEND_IDX(steps);
8592
8593         if (WARN_ON(steps % 5 != 0))
8594                 return;
8595
8596         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8597                 return;
8598
8599         mutex_lock(&dev_priv->sb_lock);
8600
8601         if (steps % 10 != 0)
8602                 tmp = 0xAAAAAAAB;
8603         else
8604                 tmp = 0x00000000;
8605         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8606
8607         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8608         tmp &= 0xffff0000;
8609         tmp |= sscdivintphase[idx];
8610         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8611
8612         mutex_unlock(&dev_priv->sb_lock);
8613 }
8614
8615 #undef BEND_IDX
8616
8617 static void lpt_init_pch_refclk(struct drm_device *dev)
8618 {
8619         struct intel_encoder *encoder;
8620         bool has_vga = false;
8621
8622         for_each_intel_encoder(dev, encoder) {
8623                 switch (encoder->type) {
8624                 case INTEL_OUTPUT_ANALOG:
8625                         has_vga = true;
8626                         break;
8627                 default:
8628                         break;
8629                 }
8630         }
8631
8632         if (has_vga) {
8633                 lpt_bend_clkout_dp(to_i915(dev), 0);
8634                 lpt_enable_clkout_dp(dev, true, true);
8635         } else {
8636                 lpt_disable_clkout_dp(dev);
8637         }
8638 }
8639
8640 /*
8641  * Initialize reference clocks when the driver loads
8642  */
8643 void intel_init_pch_refclk(struct drm_device *dev)
8644 {
8645         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8646                 ironlake_init_pch_refclk(dev);
8647         else if (HAS_PCH_LPT(dev))
8648                 lpt_init_pch_refclk(dev);
8649 }
8650
8651 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8652 {
8653         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8654         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8655         int pipe = intel_crtc->pipe;
8656         uint32_t val;
8657
8658         val = 0;
8659
8660         switch (intel_crtc->config->pipe_bpp) {
8661         case 18:
8662                 val |= PIPECONF_6BPC;
8663                 break;
8664         case 24:
8665                 val |= PIPECONF_8BPC;
8666                 break;
8667         case 30:
8668                 val |= PIPECONF_10BPC;
8669                 break;
8670         case 36:
8671                 val |= PIPECONF_12BPC;
8672                 break;
8673         default:
8674                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8675                 BUG();
8676         }
8677
8678         if (intel_crtc->config->dither)
8679                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8680
8681         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8682                 val |= PIPECONF_INTERLACED_ILK;
8683         else
8684                 val |= PIPECONF_PROGRESSIVE;
8685
8686         if (intel_crtc->config->limited_color_range)
8687                 val |= PIPECONF_COLOR_RANGE_SELECT;
8688
8689         I915_WRITE(PIPECONF(pipe), val);
8690         POSTING_READ(PIPECONF(pipe));
8691 }
8692
8693 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8694 {
8695         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8696         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8697         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8698         u32 val = 0;
8699
8700         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8701                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8702
8703         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8704                 val |= PIPECONF_INTERLACED_ILK;
8705         else
8706                 val |= PIPECONF_PROGRESSIVE;
8707
8708         I915_WRITE(PIPECONF(cpu_transcoder), val);
8709         POSTING_READ(PIPECONF(cpu_transcoder));
8710 }
8711
8712 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8713 {
8714         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8715         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8716
8717         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8718                 u32 val = 0;
8719
8720                 switch (intel_crtc->config->pipe_bpp) {
8721                 case 18:
8722                         val |= PIPEMISC_DITHER_6_BPC;
8723                         break;
8724                 case 24:
8725                         val |= PIPEMISC_DITHER_8_BPC;
8726                         break;
8727                 case 30:
8728                         val |= PIPEMISC_DITHER_10_BPC;
8729                         break;
8730                 case 36:
8731                         val |= PIPEMISC_DITHER_12_BPC;
8732                         break;
8733                 default:
8734                         /* Case prevented by pipe_config_set_bpp. */
8735                         BUG();
8736                 }
8737
8738                 if (intel_crtc->config->dither)
8739                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8740
8741                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8742         }
8743 }
8744
8745 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8746 {
8747         /*
8748          * Account for spread spectrum to avoid
8749          * oversubscribing the link. Max center spread
8750          * is 2.5%; use 5% for safety's sake.
8751          */
8752         u32 bps = target_clock * bpp * 21 / 20;
8753         return DIV_ROUND_UP(bps, link_bw * 8);
8754 }
8755
8756 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8757 {
8758         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8759 }
8760
8761 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8762                                   struct intel_crtc_state *crtc_state,
8763                                   struct dpll *reduced_clock)
8764 {
8765         struct drm_crtc *crtc = &intel_crtc->base;
8766         struct drm_device *dev = crtc->dev;
8767         struct drm_i915_private *dev_priv = dev->dev_private;
8768         struct drm_atomic_state *state = crtc_state->base.state;
8769         struct drm_connector *connector;
8770         struct drm_connector_state *connector_state;
8771         struct intel_encoder *encoder;
8772         u32 dpll, fp, fp2;
8773         int factor, i;
8774         bool is_lvds = false, is_sdvo = false;
8775
8776         for_each_connector_in_state(state, connector, connector_state, i) {
8777                 if (connector_state->crtc != crtc_state->base.crtc)
8778                         continue;
8779
8780                 encoder = to_intel_encoder(connector_state->best_encoder);
8781
8782                 switch (encoder->type) {
8783                 case INTEL_OUTPUT_LVDS:
8784                         is_lvds = true;
8785                         break;
8786                 case INTEL_OUTPUT_SDVO:
8787                 case INTEL_OUTPUT_HDMI:
8788                         is_sdvo = true;
8789                         break;
8790                 default:
8791                         break;
8792                 }
8793         }
8794
8795         /* Enable autotuning of the PLL clock (if permissible) */
8796         factor = 21;
8797         if (is_lvds) {
8798                 if ((intel_panel_use_ssc(dev_priv) &&
8799                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8800                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8801                         factor = 25;
8802         } else if (crtc_state->sdvo_tv_clock)
8803                 factor = 20;
8804
8805         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8806
8807         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8808                 fp |= FP_CB_TUNE;
8809
8810         if (reduced_clock) {
8811                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8812
8813                 if (reduced_clock->m < factor * reduced_clock->n)
8814                         fp2 |= FP_CB_TUNE;
8815         } else {
8816                 fp2 = fp;
8817         }
8818
8819         dpll = 0;
8820
8821         if (is_lvds)
8822                 dpll |= DPLLB_MODE_LVDS;
8823         else
8824                 dpll |= DPLLB_MODE_DAC_SERIAL;
8825
8826         dpll |= (crtc_state->pixel_multiplier - 1)
8827                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8828
8829         if (is_sdvo)
8830                 dpll |= DPLL_SDVO_HIGH_SPEED;
8831         if (crtc_state->has_dp_encoder)
8832                 dpll |= DPLL_SDVO_HIGH_SPEED;
8833
8834         /* compute bitmask from p1 value */
8835         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8836         /* also FPA1 */
8837         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8838
8839         switch (crtc_state->dpll.p2) {
8840         case 5:
8841                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8842                 break;
8843         case 7:
8844                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8845                 break;
8846         case 10:
8847                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8848                 break;
8849         case 14:
8850                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8851                 break;
8852         }
8853
8854         if (is_lvds && intel_panel_use_ssc(dev_priv))
8855                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8856         else
8857                 dpll |= PLL_REF_INPUT_DREFCLK;
8858
8859         dpll |= DPLL_VCO_ENABLE;
8860
8861         crtc_state->dpll_hw_state.dpll = dpll;
8862         crtc_state->dpll_hw_state.fp0 = fp;
8863         crtc_state->dpll_hw_state.fp1 = fp2;
8864 }
8865
8866 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8867                                        struct intel_crtc_state *crtc_state)
8868 {
8869         struct drm_device *dev = crtc->base.dev;
8870         struct drm_i915_private *dev_priv = dev->dev_private;
8871         struct dpll reduced_clock;
8872         bool has_reduced_clock = false;
8873         struct intel_shared_dpll *pll;
8874         const struct intel_limit *limit;
8875         int refclk = 120000;
8876
8877         memset(&crtc_state->dpll_hw_state, 0,
8878                sizeof(crtc_state->dpll_hw_state));
8879
8880         crtc->lowfreq_avail = false;
8881
8882         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8883         if (!crtc_state->has_pch_encoder)
8884                 return 0;
8885
8886         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8887                 if (intel_panel_use_ssc(dev_priv)) {
8888                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8889                                       dev_priv->vbt.lvds_ssc_freq);
8890                         refclk = dev_priv->vbt.lvds_ssc_freq;
8891                 }
8892
8893                 if (intel_is_dual_link_lvds(dev)) {
8894                         if (refclk == 100000)
8895                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8896                         else
8897                                 limit = &intel_limits_ironlake_dual_lvds;
8898                 } else {
8899                         if (refclk == 100000)
8900                                 limit = &intel_limits_ironlake_single_lvds_100m;
8901                         else
8902                                 limit = &intel_limits_ironlake_single_lvds;
8903                 }
8904         } else {
8905                 limit = &intel_limits_ironlake_dac;
8906         }
8907
8908         if (!crtc_state->clock_set &&
8909             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8910                                 refclk, NULL, &crtc_state->dpll)) {
8911                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8912                 return -EINVAL;
8913         }
8914
8915         ironlake_compute_dpll(crtc, crtc_state,
8916                               has_reduced_clock ? &reduced_clock : NULL);
8917
8918         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8919         if (pll == NULL) {
8920                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8921                                  pipe_name(crtc->pipe));
8922                 return -EINVAL;
8923         }
8924
8925         if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8926             has_reduced_clock)
8927                 crtc->lowfreq_avail = true;
8928
8929         return 0;
8930 }
8931
8932 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8933                                          struct intel_link_m_n *m_n)
8934 {
8935         struct drm_device *dev = crtc->base.dev;
8936         struct drm_i915_private *dev_priv = dev->dev_private;
8937         enum pipe pipe = crtc->pipe;
8938
8939         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8940         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8941         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8942                 & ~TU_SIZE_MASK;
8943         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8944         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8945                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8946 }
8947
8948 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8949                                          enum transcoder transcoder,
8950                                          struct intel_link_m_n *m_n,
8951                                          struct intel_link_m_n *m2_n2)
8952 {
8953         struct drm_device *dev = crtc->base.dev;
8954         struct drm_i915_private *dev_priv = dev->dev_private;
8955         enum pipe pipe = crtc->pipe;
8956
8957         if (INTEL_INFO(dev)->gen >= 5) {
8958                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8959                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8960                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8961                         & ~TU_SIZE_MASK;
8962                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8963                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8964                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8965                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8966                  * gen < 8) and if DRRS is supported (to make sure the
8967                  * registers are not unnecessarily read).
8968                  */
8969                 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8970                         crtc->config->has_drrs) {
8971                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8972                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8973                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8974                                         & ~TU_SIZE_MASK;
8975                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8976                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8977                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8978                 }
8979         } else {
8980                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8981                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8982                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8983                         & ~TU_SIZE_MASK;
8984                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8985                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8986                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8987         }
8988 }
8989
8990 void intel_dp_get_m_n(struct intel_crtc *crtc,
8991                       struct intel_crtc_state *pipe_config)
8992 {
8993         if (pipe_config->has_pch_encoder)
8994                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8995         else
8996                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8997                                              &pipe_config->dp_m_n,
8998                                              &pipe_config->dp_m2_n2);
8999 }
9000
9001 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9002                                         struct intel_crtc_state *pipe_config)
9003 {
9004         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9005                                      &pipe_config->fdi_m_n, NULL);
9006 }
9007
9008 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9009                                     struct intel_crtc_state *pipe_config)
9010 {
9011         struct drm_device *dev = crtc->base.dev;
9012         struct drm_i915_private *dev_priv = dev->dev_private;
9013         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9014         uint32_t ps_ctrl = 0;
9015         int id = -1;
9016         int i;
9017
9018         /* find scaler attached to this pipe */
9019         for (i = 0; i < crtc->num_scalers; i++) {
9020                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9021                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9022                         id = i;
9023                         pipe_config->pch_pfit.enabled = true;
9024                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9025                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9026                         break;
9027                 }
9028         }
9029
9030         scaler_state->scaler_id = id;
9031         if (id >= 0) {
9032                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9033         } else {
9034                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9035         }
9036 }
9037
9038 static void
9039 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9040                                  struct intel_initial_plane_config *plane_config)
9041 {
9042         struct drm_device *dev = crtc->base.dev;
9043         struct drm_i915_private *dev_priv = dev->dev_private;
9044         u32 val, base, offset, stride_mult, tiling;
9045         int pipe = crtc->pipe;
9046         int fourcc, pixel_format;
9047         unsigned int aligned_height;
9048         struct drm_framebuffer *fb;
9049         struct intel_framebuffer *intel_fb;
9050
9051         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9052         if (!intel_fb) {
9053                 DRM_DEBUG_KMS("failed to alloc fb\n");
9054                 return;
9055         }
9056
9057         fb = &intel_fb->base;
9058
9059         val = I915_READ(PLANE_CTL(pipe, 0));
9060         if (!(val & PLANE_CTL_ENABLE))
9061                 goto error;
9062
9063         pixel_format = val & PLANE_CTL_FORMAT_MASK;
9064         fourcc = skl_format_to_fourcc(pixel_format,
9065                                       val & PLANE_CTL_ORDER_RGBX,
9066                                       val & PLANE_CTL_ALPHA_MASK);
9067         fb->pixel_format = fourcc;
9068         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9069
9070         tiling = val & PLANE_CTL_TILED_MASK;
9071         switch (tiling) {
9072         case PLANE_CTL_TILED_LINEAR:
9073                 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9074                 break;
9075         case PLANE_CTL_TILED_X:
9076                 plane_config->tiling = I915_TILING_X;
9077                 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9078                 break;
9079         case PLANE_CTL_TILED_Y:
9080                 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9081                 break;
9082         case PLANE_CTL_TILED_YF:
9083                 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9084                 break;
9085         default:
9086                 MISSING_CASE(tiling);
9087                 goto error;
9088         }
9089
9090         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9091         plane_config->base = base;
9092
9093         offset = I915_READ(PLANE_OFFSET(pipe, 0));
9094
9095         val = I915_READ(PLANE_SIZE(pipe, 0));
9096         fb->height = ((val >> 16) & 0xfff) + 1;
9097         fb->width = ((val >> 0) & 0x1fff) + 1;
9098
9099         val = I915_READ(PLANE_STRIDE(pipe, 0));
9100         stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9101                                                 fb->pixel_format);
9102         fb->pitches[0] = (val & 0x3ff) * stride_mult;
9103
9104         aligned_height = intel_fb_align_height(dev, fb->height,
9105                                                fb->pixel_format,
9106                                                fb->modifier[0]);
9107
9108         plane_config->size = fb->pitches[0] * aligned_height;
9109
9110         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9111                       pipe_name(pipe), fb->width, fb->height,
9112                       fb->bits_per_pixel, base, fb->pitches[0],
9113                       plane_config->size);
9114
9115         plane_config->fb = intel_fb;
9116         return;
9117
9118 error:
9119         kfree(fb);
9120 }
9121
9122 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9123                                      struct intel_crtc_state *pipe_config)
9124 {
9125         struct drm_device *dev = crtc->base.dev;
9126         struct drm_i915_private *dev_priv = dev->dev_private;
9127         uint32_t tmp;
9128
9129         tmp = I915_READ(PF_CTL(crtc->pipe));
9130
9131         if (tmp & PF_ENABLE) {
9132                 pipe_config->pch_pfit.enabled = true;
9133                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9134                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9135
9136                 /* We currently do not free assignements of panel fitters on
9137                  * ivb/hsw (since we don't use the higher upscaling modes which
9138                  * differentiates them) so just WARN about this case for now. */
9139                 if (IS_GEN7(dev)) {
9140                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9141                                 PF_PIPE_SEL_IVB(crtc->pipe));
9142                 }
9143         }
9144 }
9145
9146 static void
9147 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9148                                   struct intel_initial_plane_config *plane_config)
9149 {
9150         struct drm_device *dev = crtc->base.dev;
9151         struct drm_i915_private *dev_priv = dev->dev_private;
9152         u32 val, base, offset;
9153         int pipe = crtc->pipe;
9154         int fourcc, pixel_format;
9155         unsigned int aligned_height;
9156         struct drm_framebuffer *fb;
9157         struct intel_framebuffer *intel_fb;
9158
9159         val = I915_READ(DSPCNTR(pipe));
9160         if (!(val & DISPLAY_PLANE_ENABLE))
9161                 return;
9162
9163         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9164         if (!intel_fb) {
9165                 DRM_DEBUG_KMS("failed to alloc fb\n");
9166                 return;
9167         }
9168
9169         fb = &intel_fb->base;
9170
9171         if (INTEL_INFO(dev)->gen >= 4) {
9172                 if (val & DISPPLANE_TILED) {
9173                         plane_config->tiling = I915_TILING_X;
9174                         fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9175                 }
9176         }
9177
9178         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9179         fourcc = i9xx_format_to_fourcc(pixel_format);
9180         fb->pixel_format = fourcc;
9181         fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9182
9183         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9184         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9185                 offset = I915_READ(DSPOFFSET(pipe));
9186         } else {
9187                 if (plane_config->tiling)
9188                         offset = I915_READ(DSPTILEOFF(pipe));
9189                 else
9190                         offset = I915_READ(DSPLINOFF(pipe));
9191         }
9192         plane_config->base = base;
9193
9194         val = I915_READ(PIPESRC(pipe));
9195         fb->width = ((val >> 16) & 0xfff) + 1;
9196         fb->height = ((val >> 0) & 0xfff) + 1;
9197
9198         val = I915_READ(DSPSTRIDE(pipe));
9199         fb->pitches[0] = val & 0xffffffc0;
9200
9201         aligned_height = intel_fb_align_height(dev, fb->height,
9202                                                fb->pixel_format,
9203                                                fb->modifier[0]);
9204
9205         plane_config->size = fb->pitches[0] * aligned_height;
9206
9207         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9208                       pipe_name(pipe), fb->width, fb->height,
9209                       fb->bits_per_pixel, base, fb->pitches[0],
9210                       plane_config->size);
9211
9212         plane_config->fb = intel_fb;
9213 }
9214
9215 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9216                                      struct intel_crtc_state *pipe_config)
9217 {
9218         struct drm_device *dev = crtc->base.dev;
9219         struct drm_i915_private *dev_priv = dev->dev_private;
9220         enum intel_display_power_domain power_domain;
9221         uint32_t tmp;
9222         bool ret;
9223
9224         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9225         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9226                 return false;
9227
9228         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9229         pipe_config->shared_dpll = NULL;
9230
9231         ret = false;
9232         tmp = I915_READ(PIPECONF(crtc->pipe));
9233         if (!(tmp & PIPECONF_ENABLE))
9234                 goto out;
9235
9236         switch (tmp & PIPECONF_BPC_MASK) {
9237         case PIPECONF_6BPC:
9238                 pipe_config->pipe_bpp = 18;
9239                 break;
9240         case PIPECONF_8BPC:
9241                 pipe_config->pipe_bpp = 24;
9242                 break;
9243         case PIPECONF_10BPC:
9244                 pipe_config->pipe_bpp = 30;
9245                 break;
9246         case PIPECONF_12BPC:
9247                 pipe_config->pipe_bpp = 36;
9248                 break;
9249         default:
9250                 break;
9251         }
9252
9253         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9254                 pipe_config->limited_color_range = true;
9255
9256         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9257                 struct intel_shared_dpll *pll;
9258                 enum intel_dpll_id pll_id;
9259
9260                 pipe_config->has_pch_encoder = true;
9261
9262                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9263                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9264                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9265
9266                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9267
9268                 if (HAS_PCH_IBX(dev_priv)) {
9269                         /*
9270                          * The pipe->pch transcoder and pch transcoder->pll
9271                          * mapping is fixed.
9272                          */
9273                         pll_id = (enum intel_dpll_id) crtc->pipe;
9274                 } else {
9275                         tmp = I915_READ(PCH_DPLL_SEL);
9276                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9277                                 pll_id = DPLL_ID_PCH_PLL_B;
9278                         else
9279                                 pll_id= DPLL_ID_PCH_PLL_A;
9280                 }
9281
9282                 pipe_config->shared_dpll =
9283                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
9284                 pll = pipe_config->shared_dpll;
9285
9286                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9287                                                  &pipe_config->dpll_hw_state));
9288
9289                 tmp = pipe_config->dpll_hw_state.dpll;
9290                 pipe_config->pixel_multiplier =
9291                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9292                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9293
9294                 ironlake_pch_clock_get(crtc, pipe_config);
9295         } else {
9296                 pipe_config->pixel_multiplier = 1;
9297         }
9298
9299         intel_get_pipe_timings(crtc, pipe_config);
9300         intel_get_pipe_src_size(crtc, pipe_config);
9301
9302         ironlake_get_pfit_config(crtc, pipe_config);
9303
9304         ret = true;
9305
9306 out:
9307         intel_display_power_put(dev_priv, power_domain);
9308
9309         return ret;
9310 }
9311
9312 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9313 {
9314         struct drm_device *dev = dev_priv->dev;
9315         struct intel_crtc *crtc;
9316
9317         for_each_intel_crtc(dev, crtc)
9318                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9319                      pipe_name(crtc->pipe));
9320
9321         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9322         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9323         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9324         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9325         I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9326         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9327              "CPU PWM1 enabled\n");
9328         if (IS_HASWELL(dev))
9329                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9330                      "CPU PWM2 enabled\n");
9331         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9332              "PCH PWM1 enabled\n");
9333         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9334              "Utility pin enabled\n");
9335         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9336
9337         /*
9338          * In theory we can still leave IRQs enabled, as long as only the HPD
9339          * interrupts remain enabled. We used to check for that, but since it's
9340          * gen-specific and since we only disable LCPLL after we fully disable
9341          * the interrupts, the check below should be enough.
9342          */
9343         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9344 }
9345
9346 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9347 {
9348         struct drm_device *dev = dev_priv->dev;
9349
9350         if (IS_HASWELL(dev))
9351                 return I915_READ(D_COMP_HSW);
9352         else
9353                 return I915_READ(D_COMP_BDW);
9354 }
9355
9356 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9357 {
9358         struct drm_device *dev = dev_priv->dev;
9359
9360         if (IS_HASWELL(dev)) {
9361                 mutex_lock(&dev_priv->rps.hw_lock);
9362                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9363                                             val))
9364                         DRM_ERROR("Failed to write to D_COMP\n");
9365                 mutex_unlock(&dev_priv->rps.hw_lock);
9366         } else {
9367                 I915_WRITE(D_COMP_BDW, val);
9368                 POSTING_READ(D_COMP_BDW);
9369         }
9370 }
9371
9372 /*
9373  * This function implements pieces of two sequences from BSpec:
9374  * - Sequence for display software to disable LCPLL
9375  * - Sequence for display software to allow package C8+
9376  * The steps implemented here are just the steps that actually touch the LCPLL
9377  * register. Callers should take care of disabling all the display engine
9378  * functions, doing the mode unset, fixing interrupts, etc.
9379  */
9380 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9381                               bool switch_to_fclk, bool allow_power_down)
9382 {
9383         uint32_t val;
9384
9385         assert_can_disable_lcpll(dev_priv);
9386
9387         val = I915_READ(LCPLL_CTL);
9388
9389         if (switch_to_fclk) {
9390                 val |= LCPLL_CD_SOURCE_FCLK;
9391                 I915_WRITE(LCPLL_CTL, val);
9392
9393                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9394                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
9395                         DRM_ERROR("Switching to FCLK failed\n");
9396
9397                 val = I915_READ(LCPLL_CTL);
9398         }
9399
9400         val |= LCPLL_PLL_DISABLE;
9401         I915_WRITE(LCPLL_CTL, val);
9402         POSTING_READ(LCPLL_CTL);
9403
9404         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9405                 DRM_ERROR("LCPLL still locked\n");
9406
9407         val = hsw_read_dcomp(dev_priv);
9408         val |= D_COMP_COMP_DISABLE;
9409         hsw_write_dcomp(dev_priv, val);
9410         ndelay(100);
9411
9412         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9413                      1))
9414                 DRM_ERROR("D_COMP RCOMP still in progress\n");
9415
9416         if (allow_power_down) {
9417                 val = I915_READ(LCPLL_CTL);
9418                 val |= LCPLL_POWER_DOWN_ALLOW;
9419                 I915_WRITE(LCPLL_CTL, val);
9420                 POSTING_READ(LCPLL_CTL);
9421         }
9422 }
9423
9424 /*
9425  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9426  * source.
9427  */
9428 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9429 {
9430         uint32_t val;
9431
9432         val = I915_READ(LCPLL_CTL);
9433
9434         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9435                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9436                 return;
9437
9438         /*
9439          * Make sure we're not on PC8 state before disabling PC8, otherwise
9440          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9441          */
9442         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9443
9444         if (val & LCPLL_POWER_DOWN_ALLOW) {
9445                 val &= ~LCPLL_POWER_DOWN_ALLOW;
9446                 I915_WRITE(LCPLL_CTL, val);
9447                 POSTING_READ(LCPLL_CTL);
9448         }
9449
9450         val = hsw_read_dcomp(dev_priv);
9451         val |= D_COMP_COMP_FORCE;
9452         val &= ~D_COMP_COMP_DISABLE;
9453         hsw_write_dcomp(dev_priv, val);
9454
9455         val = I915_READ(LCPLL_CTL);
9456         val &= ~LCPLL_PLL_DISABLE;
9457         I915_WRITE(LCPLL_CTL, val);
9458
9459         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9460                 DRM_ERROR("LCPLL not locked yet\n");
9461
9462         if (val & LCPLL_CD_SOURCE_FCLK) {
9463                 val = I915_READ(LCPLL_CTL);
9464                 val &= ~LCPLL_CD_SOURCE_FCLK;
9465                 I915_WRITE(LCPLL_CTL, val);
9466
9467                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9468                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9469                         DRM_ERROR("Switching back to LCPLL failed\n");
9470         }
9471
9472         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9473         intel_update_cdclk(dev_priv->dev);
9474 }
9475
9476 /*
9477  * Package states C8 and deeper are really deep PC states that can only be
9478  * reached when all the devices on the system allow it, so even if the graphics
9479  * device allows PC8+, it doesn't mean the system will actually get to these
9480  * states. Our driver only allows PC8+ when going into runtime PM.
9481  *
9482  * The requirements for PC8+ are that all the outputs are disabled, the power
9483  * well is disabled and most interrupts are disabled, and these are also
9484  * requirements for runtime PM. When these conditions are met, we manually do
9485  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9486  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9487  * hang the machine.
9488  *
9489  * When we really reach PC8 or deeper states (not just when we allow it) we lose
9490  * the state of some registers, so when we come back from PC8+ we need to
9491  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9492  * need to take care of the registers kept by RC6. Notice that this happens even
9493  * if we don't put the device in PCI D3 state (which is what currently happens
9494  * because of the runtime PM support).
9495  *
9496  * For more, read "Display Sequences for Package C8" on the hardware
9497  * documentation.
9498  */
9499 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9500 {
9501         struct drm_device *dev = dev_priv->dev;
9502         uint32_t val;
9503
9504         DRM_DEBUG_KMS("Enabling package C8+\n");
9505
9506         if (HAS_PCH_LPT_LP(dev)) {
9507                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9508                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9509                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9510         }
9511
9512         lpt_disable_clkout_dp(dev);
9513         hsw_disable_lcpll(dev_priv, true, true);
9514 }
9515
9516 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9517 {
9518         struct drm_device *dev = dev_priv->dev;
9519         uint32_t val;
9520
9521         DRM_DEBUG_KMS("Disabling package C8+\n");
9522
9523         hsw_restore_lcpll(dev_priv);
9524         lpt_init_pch_refclk(dev);
9525
9526         if (HAS_PCH_LPT_LP(dev)) {
9527                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9528                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9529                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9530         }
9531 }
9532
9533 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9534 {
9535         struct drm_device *dev = old_state->dev;
9536         struct intel_atomic_state *old_intel_state =
9537                 to_intel_atomic_state(old_state);
9538         unsigned int req_cdclk = old_intel_state->dev_cdclk;
9539
9540         broxton_set_cdclk(to_i915(dev), req_cdclk);
9541 }
9542
9543 /* compute the max rate for new configuration */
9544 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9545 {
9546         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9547         struct drm_i915_private *dev_priv = state->dev->dev_private;
9548         struct drm_crtc *crtc;
9549         struct drm_crtc_state *cstate;
9550         struct intel_crtc_state *crtc_state;
9551         unsigned max_pixel_rate = 0, i;
9552         enum pipe pipe;
9553
9554         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9555                sizeof(intel_state->min_pixclk));
9556
9557         for_each_crtc_in_state(state, crtc, cstate, i) {
9558                 int pixel_rate;
9559
9560                 crtc_state = to_intel_crtc_state(cstate);
9561                 if (!crtc_state->base.enable) {
9562                         intel_state->min_pixclk[i] = 0;
9563                         continue;
9564                 }
9565
9566                 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9567
9568                 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9569                 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9570                         pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9571
9572                 intel_state->min_pixclk[i] = pixel_rate;
9573         }
9574
9575         for_each_pipe(dev_priv, pipe)
9576                 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9577
9578         return max_pixel_rate;
9579 }
9580
9581 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9582 {
9583         struct drm_i915_private *dev_priv = dev->dev_private;
9584         uint32_t val, data;
9585         int ret;
9586
9587         if (WARN((I915_READ(LCPLL_CTL) &
9588                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9589                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9590                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9591                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9592                  "trying to change cdclk frequency with cdclk not enabled\n"))
9593                 return;
9594
9595         mutex_lock(&dev_priv->rps.hw_lock);
9596         ret = sandybridge_pcode_write(dev_priv,
9597                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9598         mutex_unlock(&dev_priv->rps.hw_lock);
9599         if (ret) {
9600                 DRM_ERROR("failed to inform pcode about cdclk change\n");
9601                 return;
9602         }
9603
9604         val = I915_READ(LCPLL_CTL);
9605         val |= LCPLL_CD_SOURCE_FCLK;
9606         I915_WRITE(LCPLL_CTL, val);
9607
9608         if (wait_for_us(I915_READ(LCPLL_CTL) &
9609                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
9610                 DRM_ERROR("Switching to FCLK failed\n");
9611
9612         val = I915_READ(LCPLL_CTL);
9613         val &= ~LCPLL_CLK_FREQ_MASK;
9614
9615         switch (cdclk) {
9616         case 450000:
9617                 val |= LCPLL_CLK_FREQ_450;
9618                 data = 0;
9619                 break;
9620         case 540000:
9621                 val |= LCPLL_CLK_FREQ_54O_BDW;
9622                 data = 1;
9623                 break;
9624         case 337500:
9625                 val |= LCPLL_CLK_FREQ_337_5_BDW;
9626                 data = 2;
9627                 break;
9628         case 675000:
9629                 val |= LCPLL_CLK_FREQ_675_BDW;
9630                 data = 3;
9631                 break;
9632         default:
9633                 WARN(1, "invalid cdclk frequency\n");
9634                 return;
9635         }
9636
9637         I915_WRITE(LCPLL_CTL, val);
9638
9639         val = I915_READ(LCPLL_CTL);
9640         val &= ~LCPLL_CD_SOURCE_FCLK;
9641         I915_WRITE(LCPLL_CTL, val);
9642
9643         if (wait_for_us((I915_READ(LCPLL_CTL) &
9644                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9645                 DRM_ERROR("Switching back to LCPLL failed\n");
9646
9647         mutex_lock(&dev_priv->rps.hw_lock);
9648         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9649         mutex_unlock(&dev_priv->rps.hw_lock);
9650
9651         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9652
9653         intel_update_cdclk(dev);
9654
9655         WARN(cdclk != dev_priv->cdclk_freq,
9656              "cdclk requested %d kHz but got %d kHz\n",
9657              cdclk, dev_priv->cdclk_freq);
9658 }
9659
9660 static int broadwell_calc_cdclk(int max_pixclk)
9661 {
9662         if (max_pixclk > 540000)
9663                 return 675000;
9664         else if (max_pixclk > 450000)
9665                 return 540000;
9666         else if (max_pixclk > 337500)
9667                 return 450000;
9668         else
9669                 return 337500;
9670 }
9671
9672 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9673 {
9674         struct drm_i915_private *dev_priv = to_i915(state->dev);
9675         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9676         int max_pixclk = ilk_max_pixel_rate(state);
9677         int cdclk;
9678
9679         /*
9680          * FIXME should also account for plane ratio
9681          * once 64bpp pixel formats are supported.
9682          */
9683         cdclk = broadwell_calc_cdclk(max_pixclk);
9684
9685         if (cdclk > dev_priv->max_cdclk_freq) {
9686                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9687                               cdclk, dev_priv->max_cdclk_freq);
9688                 return -EINVAL;
9689         }
9690
9691         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9692         if (!intel_state->active_crtcs)
9693                 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
9694
9695         return 0;
9696 }
9697
9698 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9699 {
9700         struct drm_device *dev = old_state->dev;
9701         struct intel_atomic_state *old_intel_state =
9702                 to_intel_atomic_state(old_state);
9703         unsigned req_cdclk = old_intel_state->dev_cdclk;
9704
9705         broadwell_set_cdclk(dev, req_cdclk);
9706 }
9707
9708 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
9709 {
9710         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9711         struct drm_i915_private *dev_priv = to_i915(state->dev);
9712         const int max_pixclk = ilk_max_pixel_rate(state);
9713         int vco = intel_state->cdclk_pll_vco;
9714         int cdclk;
9715
9716         /*
9717          * FIXME should also account for plane ratio
9718          * once 64bpp pixel formats are supported.
9719          */
9720         cdclk = skl_calc_cdclk(max_pixclk, vco);
9721
9722         /*
9723          * FIXME move the cdclk caclulation to
9724          * compute_config() so we can fail gracegully.
9725          */
9726         if (cdclk > dev_priv->max_cdclk_freq) {
9727                 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9728                           cdclk, dev_priv->max_cdclk_freq);
9729                 cdclk = dev_priv->max_cdclk_freq;
9730         }
9731
9732         intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9733         if (!intel_state->active_crtcs)
9734                 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
9735
9736         return 0;
9737 }
9738
9739 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9740 {
9741         struct drm_i915_private *dev_priv = to_i915(old_state->dev);
9742         struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
9743         unsigned int req_cdclk = intel_state->dev_cdclk;
9744         unsigned int req_vco = intel_state->cdclk_pll_vco;
9745
9746         skl_set_cdclk(dev_priv, req_cdclk, req_vco);
9747 }
9748
9749 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9750                                       struct intel_crtc_state *crtc_state)
9751 {
9752         struct intel_encoder *intel_encoder =
9753                 intel_ddi_get_crtc_new_encoder(crtc_state);
9754
9755         if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9756                 if (!intel_ddi_pll_select(crtc, crtc_state))
9757                         return -EINVAL;
9758         }
9759
9760         crtc->lowfreq_avail = false;
9761
9762         return 0;
9763 }
9764
9765 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9766                                 enum port port,
9767                                 struct intel_crtc_state *pipe_config)
9768 {
9769         enum intel_dpll_id id;
9770
9771         switch (port) {
9772         case PORT_A:
9773                 pipe_config->ddi_pll_sel = SKL_DPLL0;
9774                 id = DPLL_ID_SKL_DPLL0;
9775                 break;
9776         case PORT_B:
9777                 pipe_config->ddi_pll_sel = SKL_DPLL1;
9778                 id = DPLL_ID_SKL_DPLL1;
9779                 break;
9780         case PORT_C:
9781                 pipe_config->ddi_pll_sel = SKL_DPLL2;
9782                 id = DPLL_ID_SKL_DPLL2;
9783                 break;
9784         default:
9785                 DRM_ERROR("Incorrect port type\n");
9786                 return;
9787         }
9788
9789         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9790 }
9791
9792 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9793                                 enum port port,
9794                                 struct intel_crtc_state *pipe_config)
9795 {
9796         enum intel_dpll_id id;
9797         u32 temp;
9798
9799         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9800         pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9801
9802         switch (pipe_config->ddi_pll_sel) {
9803         case SKL_DPLL0:
9804                 id = DPLL_ID_SKL_DPLL0;
9805                 break;
9806         case SKL_DPLL1:
9807                 id = DPLL_ID_SKL_DPLL1;
9808                 break;
9809         case SKL_DPLL2:
9810                 id = DPLL_ID_SKL_DPLL2;
9811                 break;
9812         case SKL_DPLL3:
9813                 id = DPLL_ID_SKL_DPLL3;
9814                 break;
9815         default:
9816                 MISSING_CASE(pipe_config->ddi_pll_sel);
9817                 return;
9818         }
9819
9820         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9821 }
9822
9823 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9824                                 enum port port,
9825                                 struct intel_crtc_state *pipe_config)
9826 {
9827         enum intel_dpll_id id;
9828
9829         pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9830
9831         switch (pipe_config->ddi_pll_sel) {
9832         case PORT_CLK_SEL_WRPLL1:
9833                 id = DPLL_ID_WRPLL1;
9834                 break;
9835         case PORT_CLK_SEL_WRPLL2:
9836                 id = DPLL_ID_WRPLL2;
9837                 break;
9838         case PORT_CLK_SEL_SPLL:
9839                 id = DPLL_ID_SPLL;
9840                 break;
9841         case PORT_CLK_SEL_LCPLL_810:
9842                 id = DPLL_ID_LCPLL_810;
9843                 break;
9844         case PORT_CLK_SEL_LCPLL_1350:
9845                 id = DPLL_ID_LCPLL_1350;
9846                 break;
9847         case PORT_CLK_SEL_LCPLL_2700:
9848                 id = DPLL_ID_LCPLL_2700;
9849                 break;
9850         default:
9851                 MISSING_CASE(pipe_config->ddi_pll_sel);
9852                 /* fall through */
9853         case PORT_CLK_SEL_NONE:
9854                 return;
9855         }
9856
9857         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9858 }
9859
9860 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9861                                      struct intel_crtc_state *pipe_config,
9862                                      unsigned long *power_domain_mask)
9863 {
9864         struct drm_device *dev = crtc->base.dev;
9865         struct drm_i915_private *dev_priv = dev->dev_private;
9866         enum intel_display_power_domain power_domain;
9867         u32 tmp;
9868
9869         /*
9870          * The pipe->transcoder mapping is fixed with the exception of the eDP
9871          * transcoder handled below.
9872          */
9873         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9874
9875         /*
9876          * XXX: Do intel_display_power_get_if_enabled before reading this (for
9877          * consistency and less surprising code; it's in always on power).
9878          */
9879         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9880         if (tmp & TRANS_DDI_FUNC_ENABLE) {
9881                 enum pipe trans_edp_pipe;
9882                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9883                 default:
9884                         WARN(1, "unknown pipe linked to edp transcoder\n");
9885                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9886                 case TRANS_DDI_EDP_INPUT_A_ON:
9887                         trans_edp_pipe = PIPE_A;
9888                         break;
9889                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9890                         trans_edp_pipe = PIPE_B;
9891                         break;
9892                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9893                         trans_edp_pipe = PIPE_C;
9894                         break;
9895                 }
9896
9897                 if (trans_edp_pipe == crtc->pipe)
9898                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
9899         }
9900
9901         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9902         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9903                 return false;
9904         *power_domain_mask |= BIT(power_domain);
9905
9906         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9907
9908         return tmp & PIPECONF_ENABLE;
9909 }
9910
9911 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9912                                          struct intel_crtc_state *pipe_config,
9913                                          unsigned long *power_domain_mask)
9914 {
9915         struct drm_device *dev = crtc->base.dev;
9916         struct drm_i915_private *dev_priv = dev->dev_private;
9917         enum intel_display_power_domain power_domain;
9918         enum port port;
9919         enum transcoder cpu_transcoder;
9920         u32 tmp;
9921
9922         pipe_config->has_dsi_encoder = false;
9923
9924         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9925                 if (port == PORT_A)
9926                         cpu_transcoder = TRANSCODER_DSI_A;
9927                 else
9928                         cpu_transcoder = TRANSCODER_DSI_C;
9929
9930                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9931                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9932                         continue;
9933                 *power_domain_mask |= BIT(power_domain);
9934
9935                 /*
9936                  * The PLL needs to be enabled with a valid divider
9937                  * configuration, otherwise accessing DSI registers will hang
9938                  * the machine. See BSpec North Display Engine
9939                  * registers/MIPI[BXT]. We can break out here early, since we
9940                  * need the same DSI PLL to be enabled for both DSI ports.
9941                  */
9942                 if (!intel_dsi_pll_is_enabled(dev_priv))
9943                         break;
9944
9945                 /* XXX: this works for video mode only */
9946                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9947                 if (!(tmp & DPI_ENABLE))
9948                         continue;
9949
9950                 tmp = I915_READ(MIPI_CTRL(port));
9951                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9952                         continue;
9953
9954                 pipe_config->cpu_transcoder = cpu_transcoder;
9955                 pipe_config->has_dsi_encoder = true;
9956                 break;
9957         }
9958
9959         return pipe_config->has_dsi_encoder;
9960 }
9961
9962 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9963                                        struct intel_crtc_state *pipe_config)
9964 {
9965         struct drm_device *dev = crtc->base.dev;
9966         struct drm_i915_private *dev_priv = dev->dev_private;
9967         struct intel_shared_dpll *pll;
9968         enum port port;
9969         uint32_t tmp;
9970
9971         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9972
9973         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9974
9975         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9976                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9977         else if (IS_BROXTON(dev))
9978                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9979         else
9980                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9981
9982         pll = pipe_config->shared_dpll;
9983         if (pll) {
9984                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9985                                                  &pipe_config->dpll_hw_state));
9986         }
9987
9988         /*
9989          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9990          * DDI E. So just check whether this pipe is wired to DDI E and whether
9991          * the PCH transcoder is on.
9992          */
9993         if (INTEL_INFO(dev)->gen < 9 &&
9994             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9995                 pipe_config->has_pch_encoder = true;
9996
9997                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9998                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9999                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
10000
10001                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10002         }
10003 }
10004
10005 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10006                                     struct intel_crtc_state *pipe_config)
10007 {
10008         struct drm_device *dev = crtc->base.dev;
10009         struct drm_i915_private *dev_priv = dev->dev_private;
10010         enum intel_display_power_domain power_domain;
10011         unsigned long power_domain_mask;
10012         bool active;
10013
10014         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10015         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10016                 return false;
10017         power_domain_mask = BIT(power_domain);
10018
10019         pipe_config->shared_dpll = NULL;
10020
10021         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10022
10023         if (IS_BROXTON(dev_priv)) {
10024                 bxt_get_dsi_transcoder_state(crtc, pipe_config,
10025                                              &power_domain_mask);
10026                 WARN_ON(active && pipe_config->has_dsi_encoder);
10027                 if (pipe_config->has_dsi_encoder)
10028                         active = true;
10029         }
10030
10031         if (!active)
10032                 goto out;
10033
10034         if (!pipe_config->has_dsi_encoder) {
10035                 haswell_get_ddi_port_state(crtc, pipe_config);
10036                 intel_get_pipe_timings(crtc, pipe_config);
10037         }
10038
10039         intel_get_pipe_src_size(crtc, pipe_config);
10040
10041         pipe_config->gamma_mode =
10042                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10043
10044         if (INTEL_INFO(dev)->gen >= 9) {
10045                 skl_init_scalers(dev, crtc, pipe_config);
10046         }
10047
10048         if (INTEL_INFO(dev)->gen >= 9) {
10049                 pipe_config->scaler_state.scaler_id = -1;
10050                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10051         }
10052
10053         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10054         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10055                 power_domain_mask |= BIT(power_domain);
10056                 if (INTEL_INFO(dev)->gen >= 9)
10057                         skylake_get_pfit_config(crtc, pipe_config);
10058                 else
10059                         ironlake_get_pfit_config(crtc, pipe_config);
10060         }
10061
10062         if (IS_HASWELL(dev))
10063                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10064                         (I915_READ(IPS_CTL) & IPS_ENABLE);
10065
10066         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10067             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10068                 pipe_config->pixel_multiplier =
10069                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10070         } else {
10071                 pipe_config->pixel_multiplier = 1;
10072         }
10073
10074 out:
10075         for_each_power_domain(power_domain, power_domain_mask)
10076                 intel_display_power_put(dev_priv, power_domain);
10077
10078         return active;
10079 }
10080
10081 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10082                                const struct intel_plane_state *plane_state)
10083 {
10084         struct drm_device *dev = crtc->dev;
10085         struct drm_i915_private *dev_priv = dev->dev_private;
10086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10087         uint32_t cntl = 0, size = 0;
10088
10089         if (plane_state && plane_state->visible) {
10090                 unsigned int width = plane_state->base.crtc_w;
10091                 unsigned int height = plane_state->base.crtc_h;
10092                 unsigned int stride = roundup_pow_of_two(width) * 4;
10093
10094                 switch (stride) {
10095                 default:
10096                         WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10097                                   width, stride);
10098                         stride = 256;
10099                         /* fallthrough */
10100                 case 256:
10101                 case 512:
10102                 case 1024:
10103                 case 2048:
10104                         break;
10105                 }
10106
10107                 cntl |= CURSOR_ENABLE |
10108                         CURSOR_GAMMA_ENABLE |
10109                         CURSOR_FORMAT_ARGB |
10110                         CURSOR_STRIDE(stride);
10111
10112                 size = (height << 12) | width;
10113         }
10114
10115         if (intel_crtc->cursor_cntl != 0 &&
10116             (intel_crtc->cursor_base != base ||
10117              intel_crtc->cursor_size != size ||
10118              intel_crtc->cursor_cntl != cntl)) {
10119                 /* On these chipsets we can only modify the base/size/stride
10120                  * whilst the cursor is disabled.
10121                  */
10122                 I915_WRITE(CURCNTR(PIPE_A), 0);
10123                 POSTING_READ(CURCNTR(PIPE_A));
10124                 intel_crtc->cursor_cntl = 0;
10125         }
10126
10127         if (intel_crtc->cursor_base != base) {
10128                 I915_WRITE(CURBASE(PIPE_A), base);
10129                 intel_crtc->cursor_base = base;
10130         }
10131
10132         if (intel_crtc->cursor_size != size) {
10133                 I915_WRITE(CURSIZE, size);
10134                 intel_crtc->cursor_size = size;
10135         }
10136
10137         if (intel_crtc->cursor_cntl != cntl) {
10138                 I915_WRITE(CURCNTR(PIPE_A), cntl);
10139                 POSTING_READ(CURCNTR(PIPE_A));
10140                 intel_crtc->cursor_cntl = cntl;
10141         }
10142 }
10143
10144 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10145                                const struct intel_plane_state *plane_state)
10146 {
10147         struct drm_device *dev = crtc->dev;
10148         struct drm_i915_private *dev_priv = dev->dev_private;
10149         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10150         int pipe = intel_crtc->pipe;
10151         uint32_t cntl = 0;
10152
10153         if (plane_state && plane_state->visible) {
10154                 cntl = MCURSOR_GAMMA_ENABLE;
10155                 switch (plane_state->base.crtc_w) {
10156                         case 64:
10157                                 cntl |= CURSOR_MODE_64_ARGB_AX;
10158                                 break;
10159                         case 128:
10160                                 cntl |= CURSOR_MODE_128_ARGB_AX;
10161                                 break;
10162                         case 256:
10163                                 cntl |= CURSOR_MODE_256_ARGB_AX;
10164                                 break;
10165                         default:
10166                                 MISSING_CASE(plane_state->base.crtc_w);
10167                                 return;
10168                 }
10169                 cntl |= pipe << 28; /* Connect to correct pipe */
10170
10171                 if (HAS_DDI(dev))
10172                         cntl |= CURSOR_PIPE_CSC_ENABLE;
10173
10174                 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10175                         cntl |= CURSOR_ROTATE_180;
10176         }
10177
10178         if (intel_crtc->cursor_cntl != cntl) {
10179                 I915_WRITE(CURCNTR(pipe), cntl);
10180                 POSTING_READ(CURCNTR(pipe));
10181                 intel_crtc->cursor_cntl = cntl;
10182         }
10183
10184         /* and commit changes on next vblank */
10185         I915_WRITE(CURBASE(pipe), base);
10186         POSTING_READ(CURBASE(pipe));
10187
10188         intel_crtc->cursor_base = base;
10189 }
10190
10191 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10192 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10193                                      const struct intel_plane_state *plane_state)
10194 {
10195         struct drm_device *dev = crtc->dev;
10196         struct drm_i915_private *dev_priv = dev->dev_private;
10197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10198         int pipe = intel_crtc->pipe;
10199         u32 base = intel_crtc->cursor_addr;
10200         u32 pos = 0;
10201
10202         if (plane_state) {
10203                 int x = plane_state->base.crtc_x;
10204                 int y = plane_state->base.crtc_y;
10205
10206                 if (x < 0) {
10207                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10208                         x = -x;
10209                 }
10210                 pos |= x << CURSOR_X_SHIFT;
10211
10212                 if (y < 0) {
10213                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10214                         y = -y;
10215                 }
10216                 pos |= y << CURSOR_Y_SHIFT;
10217
10218                 /* ILK+ do this automagically */
10219                 if (HAS_GMCH_DISPLAY(dev) &&
10220                     plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10221                         base += (plane_state->base.crtc_h *
10222                                  plane_state->base.crtc_w - 1) * 4;
10223                 }
10224         }
10225
10226         I915_WRITE(CURPOS(pipe), pos);
10227
10228         if (IS_845G(dev) || IS_I865G(dev))
10229                 i845_update_cursor(crtc, base, plane_state);
10230         else
10231                 i9xx_update_cursor(crtc, base, plane_state);
10232 }
10233
10234 static bool cursor_size_ok(struct drm_device *dev,
10235                            uint32_t width, uint32_t height)
10236 {
10237         if (width == 0 || height == 0)
10238                 return false;
10239
10240         /*
10241          * 845g/865g are special in that they are only limited by
10242          * the width of their cursors, the height is arbitrary up to
10243          * the precision of the register. Everything else requires
10244          * square cursors, limited to a few power-of-two sizes.
10245          */
10246         if (IS_845G(dev) || IS_I865G(dev)) {
10247                 if ((width & 63) != 0)
10248                         return false;
10249
10250                 if (width > (IS_845G(dev) ? 64 : 512))
10251                         return false;
10252
10253                 if (height > 1023)
10254                         return false;
10255         } else {
10256                 switch (width | height) {
10257                 case 256:
10258                 case 128:
10259                         if (IS_GEN2(dev))
10260                                 return false;
10261                 case 64:
10262                         break;
10263                 default:
10264                         return false;
10265                 }
10266         }
10267
10268         return true;
10269 }
10270
10271 /* VESA 640x480x72Hz mode to set on the pipe */
10272 static struct drm_display_mode load_detect_mode = {
10273         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10274                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10275 };
10276
10277 struct drm_framebuffer *
10278 __intel_framebuffer_create(struct drm_device *dev,
10279                            struct drm_mode_fb_cmd2 *mode_cmd,
10280                            struct drm_i915_gem_object *obj)
10281 {
10282         struct intel_framebuffer *intel_fb;
10283         int ret;
10284
10285         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10286         if (!intel_fb)
10287                 return ERR_PTR(-ENOMEM);
10288
10289         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10290         if (ret)
10291                 goto err;
10292
10293         return &intel_fb->base;
10294
10295 err:
10296         kfree(intel_fb);
10297         return ERR_PTR(ret);
10298 }
10299
10300 static struct drm_framebuffer *
10301 intel_framebuffer_create(struct drm_device *dev,
10302                          struct drm_mode_fb_cmd2 *mode_cmd,
10303                          struct drm_i915_gem_object *obj)
10304 {
10305         struct drm_framebuffer *fb;
10306         int ret;
10307
10308         ret = i915_mutex_lock_interruptible(dev);
10309         if (ret)
10310                 return ERR_PTR(ret);
10311         fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10312         mutex_unlock(&dev->struct_mutex);
10313
10314         return fb;
10315 }
10316
10317 static u32
10318 intel_framebuffer_pitch_for_width(int width, int bpp)
10319 {
10320         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10321         return ALIGN(pitch, 64);
10322 }
10323
10324 static u32
10325 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10326 {
10327         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10328         return PAGE_ALIGN(pitch * mode->vdisplay);
10329 }
10330
10331 static struct drm_framebuffer *
10332 intel_framebuffer_create_for_mode(struct drm_device *dev,
10333                                   struct drm_display_mode *mode,
10334                                   int depth, int bpp)
10335 {
10336         struct drm_framebuffer *fb;
10337         struct drm_i915_gem_object *obj;
10338         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10339
10340         obj = i915_gem_object_create(dev,
10341                                     intel_framebuffer_size_for_mode(mode, bpp));
10342         if (IS_ERR(obj))
10343                 return ERR_CAST(obj);
10344
10345         mode_cmd.width = mode->hdisplay;
10346         mode_cmd.height = mode->vdisplay;
10347         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10348                                                                 bpp);
10349         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10350
10351         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10352         if (IS_ERR(fb))
10353                 drm_gem_object_unreference_unlocked(&obj->base);
10354
10355         return fb;
10356 }
10357
10358 static struct drm_framebuffer *
10359 mode_fits_in_fbdev(struct drm_device *dev,
10360                    struct drm_display_mode *mode)
10361 {
10362 #ifdef CONFIG_DRM_FBDEV_EMULATION
10363         struct drm_i915_private *dev_priv = dev->dev_private;
10364         struct drm_i915_gem_object *obj;
10365         struct drm_framebuffer *fb;
10366
10367         if (!dev_priv->fbdev)
10368                 return NULL;
10369
10370         if (!dev_priv->fbdev->fb)
10371                 return NULL;
10372
10373         obj = dev_priv->fbdev->fb->obj;
10374         BUG_ON(!obj);
10375
10376         fb = &dev_priv->fbdev->fb->base;
10377         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10378                                                                fb->bits_per_pixel))
10379                 return NULL;
10380
10381         if (obj->base.size < mode->vdisplay * fb->pitches[0])
10382                 return NULL;
10383
10384         drm_framebuffer_reference(fb);
10385         return fb;
10386 #else
10387         return NULL;
10388 #endif
10389 }
10390
10391 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10392                                            struct drm_crtc *crtc,
10393                                            struct drm_display_mode *mode,
10394                                            struct drm_framebuffer *fb,
10395                                            int x, int y)
10396 {
10397         struct drm_plane_state *plane_state;
10398         int hdisplay, vdisplay;
10399         int ret;
10400
10401         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10402         if (IS_ERR(plane_state))
10403                 return PTR_ERR(plane_state);
10404
10405         if (mode)
10406                 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10407         else
10408                 hdisplay = vdisplay = 0;
10409
10410         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10411         if (ret)
10412                 return ret;
10413         drm_atomic_set_fb_for_plane(plane_state, fb);
10414         plane_state->crtc_x = 0;
10415         plane_state->crtc_y = 0;
10416         plane_state->crtc_w = hdisplay;
10417         plane_state->crtc_h = vdisplay;
10418         plane_state->src_x = x << 16;
10419         plane_state->src_y = y << 16;
10420         plane_state->src_w = hdisplay << 16;
10421         plane_state->src_h = vdisplay << 16;
10422
10423         return 0;
10424 }
10425
10426 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10427                                 struct drm_display_mode *mode,
10428                                 struct intel_load_detect_pipe *old,
10429                                 struct drm_modeset_acquire_ctx *ctx)
10430 {
10431         struct intel_crtc *intel_crtc;
10432         struct intel_encoder *intel_encoder =
10433                 intel_attached_encoder(connector);
10434         struct drm_crtc *possible_crtc;
10435         struct drm_encoder *encoder = &intel_encoder->base;
10436         struct drm_crtc *crtc = NULL;
10437         struct drm_device *dev = encoder->dev;
10438         struct drm_framebuffer *fb;
10439         struct drm_mode_config *config = &dev->mode_config;
10440         struct drm_atomic_state *state = NULL, *restore_state = NULL;
10441         struct drm_connector_state *connector_state;
10442         struct intel_crtc_state *crtc_state;
10443         int ret, i = -1;
10444
10445         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10446                       connector->base.id, connector->name,
10447                       encoder->base.id, encoder->name);
10448
10449         old->restore_state = NULL;
10450
10451 retry:
10452         ret = drm_modeset_lock(&config->connection_mutex, ctx);
10453         if (ret)
10454                 goto fail;
10455
10456         /*
10457          * Algorithm gets a little messy:
10458          *
10459          *   - if the connector already has an assigned crtc, use it (but make
10460          *     sure it's on first)
10461          *
10462          *   - try to find the first unused crtc that can drive this connector,
10463          *     and use that if we find one
10464          */
10465
10466         /* See if we already have a CRTC for this connector */
10467         if (connector->state->crtc) {
10468                 crtc = connector->state->crtc;
10469
10470                 ret = drm_modeset_lock(&crtc->mutex, ctx);
10471                 if (ret)
10472                         goto fail;
10473
10474                 /* Make sure the crtc and connector are running */
10475                 goto found;
10476         }
10477
10478         /* Find an unused one (if possible) */
10479         for_each_crtc(dev, possible_crtc) {
10480                 i++;
10481                 if (!(encoder->possible_crtcs & (1 << i)))
10482                         continue;
10483
10484                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10485                 if (ret)
10486                         goto fail;
10487
10488                 if (possible_crtc->state->enable) {
10489                         drm_modeset_unlock(&possible_crtc->mutex);
10490                         continue;
10491                 }
10492
10493                 crtc = possible_crtc;
10494                 break;
10495         }
10496
10497         /*
10498          * If we didn't find an unused CRTC, don't use any.
10499          */
10500         if (!crtc) {
10501                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10502                 goto fail;
10503         }
10504
10505 found:
10506         intel_crtc = to_intel_crtc(crtc);
10507
10508         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10509         if (ret)
10510                 goto fail;
10511
10512         state = drm_atomic_state_alloc(dev);
10513         restore_state = drm_atomic_state_alloc(dev);
10514         if (!state || !restore_state) {
10515                 ret = -ENOMEM;
10516                 goto fail;
10517         }
10518
10519         state->acquire_ctx = ctx;
10520         restore_state->acquire_ctx = ctx;
10521
10522         connector_state = drm_atomic_get_connector_state(state, connector);
10523         if (IS_ERR(connector_state)) {
10524                 ret = PTR_ERR(connector_state);
10525                 goto fail;
10526         }
10527
10528         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10529         if (ret)
10530                 goto fail;
10531
10532         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10533         if (IS_ERR(crtc_state)) {
10534                 ret = PTR_ERR(crtc_state);
10535                 goto fail;
10536         }
10537
10538         crtc_state->base.active = crtc_state->base.enable = true;
10539
10540         if (!mode)
10541                 mode = &load_detect_mode;
10542
10543         /* We need a framebuffer large enough to accommodate all accesses
10544          * that the plane may generate whilst we perform load detection.
10545          * We can not rely on the fbcon either being present (we get called
10546          * during its initialisation to detect all boot displays, or it may
10547          * not even exist) or that it is large enough to satisfy the
10548          * requested mode.
10549          */
10550         fb = mode_fits_in_fbdev(dev, mode);
10551         if (fb == NULL) {
10552                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10553                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10554         } else
10555                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10556         if (IS_ERR(fb)) {
10557                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10558                 goto fail;
10559         }
10560
10561         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10562         if (ret)
10563                 goto fail;
10564
10565         drm_framebuffer_unreference(fb);
10566
10567         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10568         if (ret)
10569                 goto fail;
10570
10571         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10572         if (!ret)
10573                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10574         if (!ret)
10575                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10576         if (ret) {
10577                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10578                 goto fail;
10579         }
10580
10581         ret = drm_atomic_commit(state);
10582         if (ret) {
10583                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10584                 goto fail;
10585         }
10586
10587         old->restore_state = restore_state;
10588
10589         /* let the connector get through one full cycle before testing */
10590         intel_wait_for_vblank(dev, intel_crtc->pipe);
10591         return true;
10592
10593 fail:
10594         drm_atomic_state_free(state);
10595         drm_atomic_state_free(restore_state);
10596         restore_state = state = NULL;
10597
10598         if (ret == -EDEADLK) {
10599                 drm_modeset_backoff(ctx);
10600                 goto retry;
10601         }
10602
10603         return false;
10604 }
10605
10606 void intel_release_load_detect_pipe(struct drm_connector *connector,
10607                                     struct intel_load_detect_pipe *old,
10608                                     struct drm_modeset_acquire_ctx *ctx)
10609 {
10610         struct intel_encoder *intel_encoder =
10611                 intel_attached_encoder(connector);
10612         struct drm_encoder *encoder = &intel_encoder->base;
10613         struct drm_atomic_state *state = old->restore_state;
10614         int ret;
10615
10616         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10617                       connector->base.id, connector->name,
10618                       encoder->base.id, encoder->name);
10619
10620         if (!state)
10621                 return;
10622
10623         ret = drm_atomic_commit(state);
10624         if (ret) {
10625                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10626                 drm_atomic_state_free(state);
10627         }
10628 }
10629
10630 static int i9xx_pll_refclk(struct drm_device *dev,
10631                            const struct intel_crtc_state *pipe_config)
10632 {
10633         struct drm_i915_private *dev_priv = dev->dev_private;
10634         u32 dpll = pipe_config->dpll_hw_state.dpll;
10635
10636         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10637                 return dev_priv->vbt.lvds_ssc_freq;
10638         else if (HAS_PCH_SPLIT(dev))
10639                 return 120000;
10640         else if (!IS_GEN2(dev))
10641                 return 96000;
10642         else
10643                 return 48000;
10644 }
10645
10646 /* Returns the clock of the currently programmed mode of the given pipe. */
10647 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10648                                 struct intel_crtc_state *pipe_config)
10649 {
10650         struct drm_device *dev = crtc->base.dev;
10651         struct drm_i915_private *dev_priv = dev->dev_private;
10652         int pipe = pipe_config->cpu_transcoder;
10653         u32 dpll = pipe_config->dpll_hw_state.dpll;
10654         u32 fp;
10655         struct dpll clock;
10656         int port_clock;
10657         int refclk = i9xx_pll_refclk(dev, pipe_config);
10658
10659         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10660                 fp = pipe_config->dpll_hw_state.fp0;
10661         else
10662                 fp = pipe_config->dpll_hw_state.fp1;
10663
10664         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10665         if (IS_PINEVIEW(dev)) {
10666                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10667                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10668         } else {
10669                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10670                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10671         }
10672
10673         if (!IS_GEN2(dev)) {
10674                 if (IS_PINEVIEW(dev))
10675                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10676                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10677                 else
10678                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10679                                DPLL_FPA01_P1_POST_DIV_SHIFT);
10680
10681                 switch (dpll & DPLL_MODE_MASK) {
10682                 case DPLLB_MODE_DAC_SERIAL:
10683                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10684                                 5 : 10;
10685                         break;
10686                 case DPLLB_MODE_LVDS:
10687                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10688                                 7 : 14;
10689                         break;
10690                 default:
10691                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10692                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
10693                         return;
10694                 }
10695
10696                 if (IS_PINEVIEW(dev))
10697                         port_clock = pnv_calc_dpll_params(refclk, &clock);
10698                 else
10699                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
10700         } else {
10701                 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10702                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10703
10704                 if (is_lvds) {
10705                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10706                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
10707
10708                         if (lvds & LVDS_CLKB_POWER_UP)
10709                                 clock.p2 = 7;
10710                         else
10711                                 clock.p2 = 14;
10712                 } else {
10713                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
10714                                 clock.p1 = 2;
10715                         else {
10716                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10717                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10718                         }
10719                         if (dpll & PLL_P2_DIVIDE_BY_4)
10720                                 clock.p2 = 4;
10721                         else
10722                                 clock.p2 = 2;
10723                 }
10724
10725                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10726         }
10727
10728         /*
10729          * This value includes pixel_multiplier. We will use
10730          * port_clock to compute adjusted_mode.crtc_clock in the
10731          * encoder's get_config() function.
10732          */
10733         pipe_config->port_clock = port_clock;
10734 }
10735
10736 int intel_dotclock_calculate(int link_freq,
10737                              const struct intel_link_m_n *m_n)
10738 {
10739         /*
10740          * The calculation for the data clock is:
10741          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10742          * But we want to avoid losing precison if possible, so:
10743          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10744          *
10745          * and the link clock is simpler:
10746          * link_clock = (m * link_clock) / n
10747          */
10748
10749         if (!m_n->link_n)
10750                 return 0;
10751
10752         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10753 }
10754
10755 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10756                                    struct intel_crtc_state *pipe_config)
10757 {
10758         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10759
10760         /* read out port_clock from the DPLL */
10761         i9xx_crtc_clock_get(crtc, pipe_config);
10762
10763         /*
10764          * In case there is an active pipe without active ports,
10765          * we may need some idea for the dotclock anyway.
10766          * Calculate one based on the FDI configuration.
10767          */
10768         pipe_config->base.adjusted_mode.crtc_clock =
10769                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10770                                          &pipe_config->fdi_m_n);
10771 }
10772
10773 /** Returns the currently programmed mode of the given pipe. */
10774 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10775                                              struct drm_crtc *crtc)
10776 {
10777         struct drm_i915_private *dev_priv = dev->dev_private;
10778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10779         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10780         struct drm_display_mode *mode;
10781         struct intel_crtc_state *pipe_config;
10782         int htot = I915_READ(HTOTAL(cpu_transcoder));
10783         int hsync = I915_READ(HSYNC(cpu_transcoder));
10784         int vtot = I915_READ(VTOTAL(cpu_transcoder));
10785         int vsync = I915_READ(VSYNC(cpu_transcoder));
10786         enum pipe pipe = intel_crtc->pipe;
10787
10788         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10789         if (!mode)
10790                 return NULL;
10791
10792         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10793         if (!pipe_config) {
10794                 kfree(mode);
10795                 return NULL;
10796         }
10797
10798         /*
10799          * Construct a pipe_config sufficient for getting the clock info
10800          * back out of crtc_clock_get.
10801          *
10802          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10803          * to use a real value here instead.
10804          */
10805         pipe_config->cpu_transcoder = (enum transcoder) pipe;
10806         pipe_config->pixel_multiplier = 1;
10807         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10808         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10809         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10810         i9xx_crtc_clock_get(intel_crtc, pipe_config);
10811
10812         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10813         mode->hdisplay = (htot & 0xffff) + 1;
10814         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10815         mode->hsync_start = (hsync & 0xffff) + 1;
10816         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10817         mode->vdisplay = (vtot & 0xffff) + 1;
10818         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10819         mode->vsync_start = (vsync & 0xffff) + 1;
10820         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10821
10822         drm_mode_set_name(mode);
10823
10824         kfree(pipe_config);
10825
10826         return mode;
10827 }
10828
10829 void intel_mark_busy(struct drm_i915_private *dev_priv)
10830 {
10831         if (dev_priv->mm.busy)
10832                 return;
10833
10834         intel_runtime_pm_get(dev_priv);
10835         i915_update_gfx_val(dev_priv);
10836         if (INTEL_GEN(dev_priv) >= 6)
10837                 gen6_rps_busy(dev_priv);
10838         dev_priv->mm.busy = true;
10839 }
10840
10841 void intel_mark_idle(struct drm_i915_private *dev_priv)
10842 {
10843         if (!dev_priv->mm.busy)
10844                 return;
10845
10846         dev_priv->mm.busy = false;
10847
10848         if (INTEL_GEN(dev_priv) >= 6)
10849                 gen6_rps_idle(dev_priv);
10850
10851         intel_runtime_pm_put(dev_priv);
10852 }
10853
10854 void intel_free_flip_work(struct intel_flip_work *work)
10855 {
10856         kfree(work->old_connector_state);
10857         kfree(work->new_connector_state);
10858         kfree(work);
10859 }
10860
10861 static void intel_crtc_destroy(struct drm_crtc *crtc)
10862 {
10863         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10864         struct drm_device *dev = crtc->dev;
10865         struct intel_flip_work *work;
10866
10867         spin_lock_irq(&dev->event_lock);
10868         while (!list_empty(&intel_crtc->flip_work)) {
10869                 work = list_first_entry(&intel_crtc->flip_work,
10870                                         struct intel_flip_work, head);
10871                 list_del_init(&work->head);
10872                 spin_unlock_irq(&dev->event_lock);
10873
10874                 cancel_work_sync(&work->mmio_work);
10875                 cancel_work_sync(&work->unpin_work);
10876                 intel_free_flip_work(work);
10877
10878                 spin_lock_irq(&dev->event_lock);
10879         }
10880         spin_unlock_irq(&dev->event_lock);
10881
10882         drm_crtc_cleanup(crtc);
10883
10884         kfree(intel_crtc);
10885 }
10886
10887 static void intel_crtc_post_flip_update(struct intel_flip_work *work,
10888                                         struct drm_crtc *crtc)
10889 {
10890         struct intel_crtc_state *crtc_state = work->new_crtc_state;
10891         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10892
10893         if (crtc_state->disable_cxsr)
10894                 intel_crtc->wm.cxsr_allowed = true;
10895
10896         if (crtc_state->update_wm_post && crtc_state->base.active)
10897                 intel_update_watermarks(crtc);
10898
10899         if (work->num_planes > 0 &&
10900             work->old_plane_state[0]->base.plane == crtc->primary) {
10901                 struct intel_plane_state *plane_state =
10902                         work->new_plane_state[0];
10903
10904                 if (plane_state->visible &&
10905                     (needs_modeset(&crtc_state->base) ||
10906                      !work->old_plane_state[0]->visible))
10907                         intel_post_enable_primary(crtc);
10908         }
10909 }
10910
10911 static void intel_unpin_work_fn(struct work_struct *__work)
10912 {
10913         struct intel_flip_work *work =
10914                 container_of(__work, struct intel_flip_work, unpin_work);
10915         struct drm_crtc *crtc = work->old_crtc_state->base.crtc;
10916         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10917         struct drm_device *dev = crtc->dev;
10918         struct drm_i915_private *dev_priv = dev->dev_private;
10919         int i;
10920
10921         if (work->fb_bits)
10922                 intel_frontbuffer_flip_complete(dev, work->fb_bits);
10923
10924         /*
10925          * Unless work->can_async_unpin is false, there's no way to ensure
10926          * that work->new_crtc_state contains valid memory during unpin
10927          * because intel_atomic_commit may free it before this runs.
10928          */
10929         if (!work->can_async_unpin) {
10930                 intel_crtc_post_flip_update(work, crtc);
10931
10932                 if (dev_priv->display.optimize_watermarks)
10933                         dev_priv->display.optimize_watermarks(work->new_crtc_state);
10934         }
10935
10936         if (work->fb_bits & to_intel_plane(crtc->primary)->frontbuffer_bit)
10937                 intel_fbc_post_update(intel_crtc);
10938
10939         if (work->put_power_domains)
10940                 modeset_put_power_domains(dev_priv, work->put_power_domains);
10941
10942         /* Make sure mmio work is completely finished before freeing all state here. */
10943         flush_work(&work->mmio_work);
10944
10945         if (!work->can_async_unpin &&
10946             (work->new_crtc_state->update_pipe ||
10947              needs_modeset(&work->new_crtc_state->base))) {
10948                 /* This must be called before work is unpinned for serialization. */
10949                 intel_modeset_verify_crtc(crtc, &work->old_crtc_state->base,
10950                                           &work->new_crtc_state->base);
10951
10952                 for (i = 0; i < work->num_new_connectors; i++) {
10953                         struct drm_connector_state *conn_state =
10954                                 work->new_connector_state[i];
10955                         struct drm_connector *con = conn_state->connector;
10956
10957                         WARN_ON(!con);
10958
10959                         intel_connector_verify_state(to_intel_connector(con),
10960                                                      conn_state);
10961                 }
10962         }
10963
10964         for (i = 0; i < work->num_old_connectors; i++) {
10965                 struct drm_connector_state *old_con_state =
10966                         work->old_connector_state[i];
10967                 struct drm_connector *con =
10968                         old_con_state->connector;
10969
10970                 con->funcs->atomic_destroy_state(con, old_con_state);
10971         }
10972
10973         if (!work->can_async_unpin || !list_empty(&work->head)) {
10974                 spin_lock_irq(&dev->event_lock);
10975                 WARN(list_empty(&work->head) != work->can_async_unpin,
10976                      "[CRTC:%i] Pin work %p async %i with %i planes, active %i -> %i ms %i\n",
10977                      crtc->base.id, work, work->can_async_unpin, work->num_planes,
10978                      work->old_crtc_state->base.active, work->new_crtc_state->base.active,
10979                      needs_modeset(&work->new_crtc_state->base));
10980
10981                 if (!list_empty(&work->head))
10982                         list_del(&work->head);
10983
10984                 wake_up_all(&dev_priv->pending_flip_queue);
10985                 spin_unlock_irq(&dev->event_lock);
10986         }
10987
10988         /* New crtc_state freed? */
10989         if (work->free_new_crtc_state)
10990                 intel_crtc_destroy_state(crtc, &work->new_crtc_state->base);
10991
10992         intel_crtc_destroy_state(crtc, &work->old_crtc_state->base);
10993
10994         for (i = 0; i < work->num_planes; i++) {
10995                 struct intel_plane_state *old_plane_state =
10996                         work->old_plane_state[i];
10997                 struct drm_framebuffer *old_fb = old_plane_state->base.fb;
10998                 struct drm_plane *plane = old_plane_state->base.plane;
10999                 struct drm_i915_gem_request *req;
11000
11001                 req = old_plane_state->wait_req;
11002                 old_plane_state->wait_req = NULL;
11003                 if (req)
11004                         i915_gem_request_unreference(req);
11005
11006                 fence_put(old_plane_state->base.fence);
11007                 old_plane_state->base.fence = NULL;
11008
11009                 if (old_fb &&
11010                     (plane->type != DRM_PLANE_TYPE_CURSOR ||
11011                      !INTEL_INFO(dev_priv)->cursor_needs_physical)) {
11012                         mutex_lock(&dev->struct_mutex);
11013                         intel_unpin_fb_obj(old_fb, old_plane_state->base.rotation);
11014                         mutex_unlock(&dev->struct_mutex);
11015                 }
11016
11017                 intel_plane_destroy_state(plane, &old_plane_state->base);
11018         }
11019
11020         if (!WARN_ON(atomic_read(&intel_crtc->unpin_work_count) == 0))
11021                 atomic_dec(&intel_crtc->unpin_work_count);
11022
11023         intel_free_flip_work(work);
11024 }
11025
11026
11027 static bool pageflip_finished(struct intel_crtc *crtc,
11028                               struct intel_flip_work *work)
11029 {
11030         if (!atomic_read(&work->pending))
11031                 return false;
11032
11033         smp_rmb();
11034
11035         /*
11036          * MMIO work completes when vblank is different from
11037          * flip_queued_vblank.
11038          */
11039         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11040 }
11041
11042 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11043 {
11044         struct drm_device *dev = dev_priv->dev;
11045         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11046         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11047         struct intel_flip_work *work;
11048         unsigned long flags;
11049
11050         /* Ignore early vblank irqs */
11051         if (!crtc)
11052                 return;
11053
11054         /*
11055          * This is called both by irq handlers and the reset code (to complete
11056          * lost pageflips) so needs the full irqsave spinlocks.
11057          */
11058         spin_lock_irqsave(&dev->event_lock, flags);
11059         while (!list_empty(&intel_crtc->flip_work)) {
11060                 work = list_first_entry(&intel_crtc->flip_work,
11061                                         struct intel_flip_work,
11062                                         head);
11063
11064                 if (!pageflip_finished(intel_crtc, work) ||
11065                     work_busy(&work->unpin_work))
11066                         break;
11067
11068                 page_flip_completed(intel_crtc, work);
11069         }
11070         spin_unlock_irqrestore(&dev->event_lock, flags);
11071 }
11072
11073 static void intel_mmio_flip_work_func(struct work_struct *w)
11074 {
11075         struct intel_flip_work *work =
11076                 container_of(w, struct intel_flip_work, mmio_work);
11077         struct drm_crtc *crtc = work->old_crtc_state->base.crtc;
11078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11079         struct intel_crtc_state *crtc_state = work->new_crtc_state;
11080         struct drm_device *dev = crtc->dev;
11081         struct drm_i915_private *dev_priv = dev->dev_private;
11082         struct drm_i915_gem_request *req;
11083         int i, ret;
11084
11085         if (!needs_modeset(&crtc_state->base) && crtc_state->update_pipe) {
11086                 work->put_power_domains =
11087                         modeset_get_crtc_power_domains(crtc, crtc_state);
11088         }
11089
11090         for (i = 0; i < work->num_planes; i++) {
11091                 struct intel_plane_state *old_plane_state = work->old_plane_state[i];
11092
11093                 /* For framebuffer backed by dmabuf, wait for fence */
11094                 if (old_plane_state->base.fence)
11095                         WARN_ON(fence_wait(old_plane_state->base.fence, false) < 0);
11096
11097                 req = old_plane_state->wait_req;
11098                 if (!req)
11099                         continue;
11100
11101                 WARN_ON(__i915_wait_request(req, false, NULL,
11102                                             &dev_priv->rps.mmioflips));
11103         }
11104
11105         ret = drm_crtc_vblank_get(crtc);
11106         I915_STATE_WARN(ret < 0, "enabling vblank failed with %i\n", ret);
11107
11108         if (work->num_planes &&
11109             work->old_plane_state[0]->base.plane == crtc->primary)
11110                 intel_fbc_enable(intel_crtc, work->new_crtc_state, work->new_plane_state[0]);
11111
11112         intel_frontbuffer_flip_prepare(dev, work->fb_bits);
11113
11114         intel_pipe_update_start(intel_crtc);
11115         if (!needs_modeset(&crtc_state->base)) {
11116                 if (crtc_state->base.color_mgmt_changed || crtc_state->update_pipe) {
11117                         intel_color_set_csc(&crtc_state->base);
11118                         intel_color_load_luts(&crtc_state->base);
11119                 }
11120
11121                 if (crtc_state->update_pipe)
11122                         intel_update_pipe_config(intel_crtc, work->old_crtc_state);
11123                 else if (INTEL_INFO(dev)->gen >= 9)
11124                         skl_detach_scalers(intel_crtc);
11125         }
11126
11127         for (i = 0; i < work->num_planes; i++) {
11128                 struct intel_plane_state *new_plane_state = work->new_plane_state[i];
11129                 struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
11130
11131                 if (new_plane_state->visible)
11132                         plane->update_plane(&plane->base, crtc_state, new_plane_state);
11133                 else
11134                         plane->disable_plane(&plane->base, crtc);
11135         }
11136
11137         intel_pipe_update_end(intel_crtc, work);
11138 }
11139
11140 /**
11141  * intel_wm_need_update - Check whether watermarks need updating
11142  * @plane: drm plane
11143  * @state: new plane state
11144  *
11145  * Check current plane state versus the new one to determine whether
11146  * watermarks need to be recalculated.
11147  *
11148  * Returns true or false.
11149  */
11150 static bool intel_wm_need_update(struct drm_plane *plane,
11151                                  struct drm_plane_state *state)
11152 {
11153         struct intel_plane_state *new = to_intel_plane_state(state);
11154         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11155
11156         /* Update watermarks on tiling or size changes. */
11157         if (new->visible != cur->visible)
11158                 return true;
11159
11160         if (!cur->base.fb || !new->base.fb)
11161                 return false;
11162
11163         if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11164             cur->base.rotation != new->base.rotation ||
11165             drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11166             drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11167             drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11168             drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11169                 return true;
11170
11171         return false;
11172 }
11173
11174 static bool needs_scaling(struct intel_plane_state *state)
11175 {
11176         int src_w = drm_rect_width(&state->src) >> 16;
11177         int src_h = drm_rect_height(&state->src) >> 16;
11178         int dst_w = drm_rect_width(&state->dst);
11179         int dst_h = drm_rect_height(&state->dst);
11180
11181         return (src_w != dst_w || src_h != dst_h);
11182 }
11183
11184 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11185                                     struct drm_plane_state *plane_state)
11186 {
11187         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11188         struct drm_crtc *crtc = crtc_state->crtc;
11189         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11190         struct drm_plane *plane = plane_state->plane;
11191         struct drm_device *dev = crtc->dev;
11192         struct drm_i915_private *dev_priv = to_i915(dev);
11193         struct intel_plane_state *old_plane_state =
11194                 to_intel_plane_state(plane->state);
11195         int idx = intel_crtc->base.base.id, ret;
11196         bool mode_changed = needs_modeset(crtc_state);
11197         bool was_crtc_enabled = crtc->state->active;
11198         bool is_crtc_enabled = crtc_state->active;
11199         bool turn_off, turn_on, visible, was_visible;
11200         struct drm_framebuffer *fb = plane_state->fb;
11201
11202         if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11203             plane->type != DRM_PLANE_TYPE_CURSOR) {
11204                 ret = skl_update_scaler_plane(
11205                         to_intel_crtc_state(crtc_state),
11206                         to_intel_plane_state(plane_state));
11207                 if (ret)
11208                         return ret;
11209         }
11210
11211         was_visible = old_plane_state->visible;
11212         visible = to_intel_plane_state(plane_state)->visible;
11213
11214         if (!was_crtc_enabled && WARN_ON(was_visible))
11215                 was_visible = false;
11216
11217         /*
11218          * Visibility is calculated as if the crtc was on, but
11219          * after scaler setup everything depends on it being off
11220          * when the crtc isn't active.
11221          *
11222          * FIXME this is wrong for watermarks. Watermarks should also
11223          * be computed as if the pipe would be active. Perhaps move
11224          * per-plane wm computation to the .check_plane() hook, and
11225          * only combine the results from all planes in the current place?
11226          */
11227         if (!is_crtc_enabled)
11228                 to_intel_plane_state(plane_state)->visible = visible = false;
11229
11230         if (!was_visible && !visible)
11231                 return 0;
11232
11233         if (fb != old_plane_state->base.fb)
11234                 pipe_config->fb_changed = true;
11235
11236         turn_off = was_visible && (!visible || mode_changed);
11237         turn_on = visible && (!was_visible || mode_changed);
11238
11239         DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11240                          plane->base.id, fb ? fb->base.id : -1);
11241
11242         DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11243                          plane->base.id, was_visible, visible,
11244                          turn_off, turn_on, mode_changed);
11245
11246         if (turn_on) {
11247                 pipe_config->update_wm_pre = true;
11248
11249                 /* must disable cxsr around plane enable/disable */
11250                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11251                         pipe_config->disable_cxsr = true;
11252         } else if (turn_off) {
11253                 pipe_config->update_wm_post = true;
11254
11255                 /* must disable cxsr around plane enable/disable */
11256                 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11257                         pipe_config->disable_cxsr = true;
11258         } else if (intel_wm_need_update(plane, plane_state)) {
11259                 /* FIXME bollocks */
11260                 pipe_config->update_wm_pre = true;
11261                 pipe_config->update_wm_post = true;
11262         }
11263
11264         /* Pre-gen9 platforms need two-step watermark updates */
11265         if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11266             INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11267                 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11268
11269         if (visible || was_visible)
11270                 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11271
11272         /*
11273          * WaCxSRDisabledForSpriteScaling:ivb
11274          *
11275          * cstate->update_wm was already set above, so this flag will
11276          * take effect when we commit and program watermarks.
11277          */
11278         if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11279             needs_scaling(to_intel_plane_state(plane_state)) &&
11280             !needs_scaling(old_plane_state))
11281                 pipe_config->disable_lp_wm = true;
11282
11283         return 0;
11284 }
11285
11286 static bool encoders_cloneable(const struct intel_encoder *a,
11287                                const struct intel_encoder *b)
11288 {
11289         /* masks could be asymmetric, so check both ways */
11290         return a == b || (a->cloneable & (1 << b->type) &&
11291                           b->cloneable & (1 << a->type));
11292 }
11293
11294 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11295                                          struct intel_crtc *crtc,
11296                                          struct intel_encoder *encoder)
11297 {
11298         struct intel_encoder *source_encoder;
11299         struct drm_connector *connector;
11300         struct drm_connector_state *connector_state;
11301         int i;
11302
11303         for_each_connector_in_state(state, connector, connector_state, i) {
11304                 if (connector_state->crtc != &crtc->base)
11305                         continue;
11306
11307                 source_encoder =
11308                         to_intel_encoder(connector_state->best_encoder);
11309                 if (!encoders_cloneable(encoder, source_encoder))
11310                         return false;
11311         }
11312
11313         return true;
11314 }
11315
11316 static bool check_encoder_cloning(struct drm_atomic_state *state,
11317                                   struct intel_crtc *crtc)
11318 {
11319         struct intel_encoder *encoder;
11320         struct drm_connector *connector;
11321         struct drm_connector_state *connector_state;
11322         int i;
11323
11324         for_each_connector_in_state(state, connector, connector_state, i) {
11325                 if (connector_state->crtc != &crtc->base)
11326                         continue;
11327
11328                 encoder = to_intel_encoder(connector_state->best_encoder);
11329                 if (!check_single_encoder_cloning(state, crtc, encoder))
11330                         return false;
11331         }
11332
11333         return true;
11334 }
11335
11336 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11337                                    struct drm_crtc_state *crtc_state)
11338 {
11339         struct drm_device *dev = crtc->dev;
11340         struct drm_i915_private *dev_priv = dev->dev_private;
11341         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11342         struct intel_crtc_state *pipe_config =
11343                 to_intel_crtc_state(crtc_state);
11344         struct drm_atomic_state *state = crtc_state->state;
11345         int ret;
11346         bool mode_changed = needs_modeset(crtc_state);
11347
11348         if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11349                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11350                 return -EINVAL;
11351         }
11352
11353         if (mode_changed && !crtc_state->active)
11354                 pipe_config->update_wm_post = true;
11355
11356         if (mode_changed && crtc_state->enable &&
11357             dev_priv->display.crtc_compute_clock &&
11358             !WARN_ON(pipe_config->shared_dpll)) {
11359                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11360                                                            pipe_config);
11361                 if (ret)
11362                         return ret;
11363         }
11364
11365         if (crtc_state->color_mgmt_changed) {
11366                 ret = intel_color_check(crtc, crtc_state);
11367                 if (ret)
11368                         return ret;
11369         }
11370
11371         ret = 0;
11372         if (dev_priv->display.compute_pipe_wm) {
11373                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11374                 if (ret) {
11375                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11376                         return ret;
11377                 }
11378         }
11379
11380         if (dev_priv->display.compute_intermediate_wm &&
11381             !to_intel_atomic_state(state)->skip_intermediate_wm) {
11382                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11383                         return 0;
11384
11385                 /*
11386                  * Calculate 'intermediate' watermarks that satisfy both the
11387                  * old state and the new state.  We can program these
11388                  * immediately.
11389                  */
11390                 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11391                                                                 intel_crtc,
11392                                                                 pipe_config);
11393                 if (ret) {
11394                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11395                         return ret;
11396                 }
11397         } else if (dev_priv->display.compute_intermediate_wm) {
11398                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11399                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11400         }
11401
11402         if (INTEL_INFO(dev)->gen >= 9) {
11403                 if (mode_changed)
11404                         ret = skl_update_scaler_crtc(pipe_config);
11405
11406                 if (!ret)
11407                         ret = intel_atomic_setup_scalers(dev, intel_crtc,
11408                                                          pipe_config);
11409         }
11410
11411         return ret;
11412 }
11413
11414 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11415         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11416         .atomic_check = intel_crtc_atomic_check,
11417 };
11418
11419 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11420 {
11421         struct intel_connector *connector;
11422
11423         for_each_intel_connector(dev, connector) {
11424                 if (connector->base.state->crtc)
11425                         drm_connector_unreference(&connector->base);
11426
11427                 if (connector->base.encoder) {
11428                         connector->base.state->best_encoder =
11429                                 connector->base.encoder;
11430                         connector->base.state->crtc =
11431                                 connector->base.encoder->crtc;
11432
11433                         drm_connector_reference(&connector->base);
11434                 } else {
11435                         connector->base.state->best_encoder = NULL;
11436                         connector->base.state->crtc = NULL;
11437                 }
11438         }
11439 }
11440
11441 static void
11442 connected_sink_compute_bpp(struct intel_connector *connector,
11443                            struct intel_crtc_state *pipe_config)
11444 {
11445         int bpp = pipe_config->pipe_bpp;
11446
11447         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11448                 connector->base.base.id,
11449                 connector->base.name);
11450
11451         /* Don't use an invalid EDID bpc value */
11452         if (connector->base.display_info.bpc &&
11453             connector->base.display_info.bpc * 3 < bpp) {
11454                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11455                               bpp, connector->base.display_info.bpc*3);
11456                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11457         }
11458
11459         /* Clamp bpp to default limit on screens without EDID 1.4 */
11460         if (connector->base.display_info.bpc == 0) {
11461                 int type = connector->base.connector_type;
11462                 int clamp_bpp = 24;
11463
11464                 /* Fall back to 18 bpp when DP sink capability is unknown. */
11465                 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
11466                     type == DRM_MODE_CONNECTOR_eDP)
11467                         clamp_bpp = 18;
11468
11469                 if (bpp > clamp_bpp) {
11470                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
11471                                       bpp, clamp_bpp);
11472                         pipe_config->pipe_bpp = clamp_bpp;
11473                 }
11474         }
11475 }
11476
11477 static int
11478 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11479                           struct intel_crtc_state *pipe_config)
11480 {
11481         struct drm_device *dev = crtc->base.dev;
11482         struct drm_atomic_state *state;
11483         struct drm_connector *connector;
11484         struct drm_connector_state *connector_state;
11485         int bpp, i;
11486
11487         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
11488                 bpp = 10*3;
11489         else if (INTEL_INFO(dev)->gen >= 5)
11490                 bpp = 12*3;
11491         else
11492                 bpp = 8*3;
11493
11494
11495         pipe_config->pipe_bpp = bpp;
11496
11497         state = pipe_config->base.state;
11498
11499         /* Clamp display bpp to EDID value */
11500         for_each_connector_in_state(state, connector, connector_state, i) {
11501                 if (connector_state->crtc != &crtc->base)
11502                         continue;
11503
11504                 connected_sink_compute_bpp(to_intel_connector(connector),
11505                                            pipe_config);
11506         }
11507
11508         return bpp;
11509 }
11510
11511 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11512 {
11513         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11514                         "type: 0x%x flags: 0x%x\n",
11515                 mode->crtc_clock,
11516                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11517                 mode->crtc_hsync_end, mode->crtc_htotal,
11518                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11519                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11520 }
11521
11522 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11523                                    struct intel_crtc_state *pipe_config,
11524                                    const char *context)
11525 {
11526         struct drm_device *dev = crtc->base.dev;
11527         struct drm_plane *plane;
11528         struct intel_plane *intel_plane;
11529         struct intel_plane_state *state;
11530         struct drm_framebuffer *fb;
11531
11532         DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11533                       context, pipe_config, pipe_name(crtc->pipe));
11534
11535         DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
11536         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11537                       pipe_config->pipe_bpp, pipe_config->dither);
11538         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11539                       pipe_config->has_pch_encoder,
11540                       pipe_config->fdi_lanes,
11541                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11542                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11543                       pipe_config->fdi_m_n.tu);
11544         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11545                       pipe_config->has_dp_encoder,
11546                       pipe_config->lane_count,
11547                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11548                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11549                       pipe_config->dp_m_n.tu);
11550
11551         DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11552                       pipe_config->has_dp_encoder,
11553                       pipe_config->lane_count,
11554                       pipe_config->dp_m2_n2.gmch_m,
11555                       pipe_config->dp_m2_n2.gmch_n,
11556                       pipe_config->dp_m2_n2.link_m,
11557                       pipe_config->dp_m2_n2.link_n,
11558                       pipe_config->dp_m2_n2.tu);
11559
11560         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11561                       pipe_config->has_audio,
11562                       pipe_config->has_infoframe);
11563
11564         DRM_DEBUG_KMS("requested mode:\n");
11565         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11566         DRM_DEBUG_KMS("adjusted mode:\n");
11567         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11568         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11569         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11570         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11571                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11572         DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11573                       crtc->num_scalers,
11574                       pipe_config->scaler_state.scaler_users,
11575                       pipe_config->scaler_state.scaler_id);
11576         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11577                       pipe_config->gmch_pfit.control,
11578                       pipe_config->gmch_pfit.pgm_ratios,
11579                       pipe_config->gmch_pfit.lvds_border_bits);
11580         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11581                       pipe_config->pch_pfit.pos,
11582                       pipe_config->pch_pfit.size,
11583                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11584         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11585         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11586
11587         if (IS_BROXTON(dev)) {
11588                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11589                               "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11590                               "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11591                               pipe_config->ddi_pll_sel,
11592                               pipe_config->dpll_hw_state.ebb0,
11593                               pipe_config->dpll_hw_state.ebb4,
11594                               pipe_config->dpll_hw_state.pll0,
11595                               pipe_config->dpll_hw_state.pll1,
11596                               pipe_config->dpll_hw_state.pll2,
11597                               pipe_config->dpll_hw_state.pll3,
11598                               pipe_config->dpll_hw_state.pll6,
11599                               pipe_config->dpll_hw_state.pll8,
11600                               pipe_config->dpll_hw_state.pll9,
11601                               pipe_config->dpll_hw_state.pll10,
11602                               pipe_config->dpll_hw_state.pcsdw12);
11603         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
11604                 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11605                               "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11606                               pipe_config->ddi_pll_sel,
11607                               pipe_config->dpll_hw_state.ctrl1,
11608                               pipe_config->dpll_hw_state.cfgcr1,
11609                               pipe_config->dpll_hw_state.cfgcr2);
11610         } else if (HAS_DDI(dev)) {
11611                 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
11612                               pipe_config->ddi_pll_sel,
11613                               pipe_config->dpll_hw_state.wrpll,
11614                               pipe_config->dpll_hw_state.spll);
11615         } else {
11616                 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11617                               "fp0: 0x%x, fp1: 0x%x\n",
11618                               pipe_config->dpll_hw_state.dpll,
11619                               pipe_config->dpll_hw_state.dpll_md,
11620                               pipe_config->dpll_hw_state.fp0,
11621                               pipe_config->dpll_hw_state.fp1);
11622         }
11623
11624         DRM_DEBUG_KMS("planes on this crtc\n");
11625         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11626                 intel_plane = to_intel_plane(plane);
11627                 if (intel_plane->pipe != crtc->pipe)
11628                         continue;
11629
11630                 state = to_intel_plane_state(plane->state);
11631                 fb = state->base.fb;
11632                 if (!fb) {
11633                         DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11634                                 "disabled, scaler_id = %d\n",
11635                                 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11636                                 plane->base.id, intel_plane->pipe,
11637                                 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11638                                 drm_plane_index(plane), state->scaler_id);
11639                         continue;
11640                 }
11641
11642                 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11643                         plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11644                         plane->base.id, intel_plane->pipe,
11645                         crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11646                         drm_plane_index(plane));
11647                 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11648                         fb->base.id, fb->width, fb->height, fb->pixel_format);
11649                 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11650                         state->scaler_id,
11651                         state->src.x1 >> 16, state->src.y1 >> 16,
11652                         drm_rect_width(&state->src) >> 16,
11653                         drm_rect_height(&state->src) >> 16,
11654                         state->dst.x1, state->dst.y1,
11655                         drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11656         }
11657 }
11658
11659 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11660 {
11661         struct drm_device *dev = state->dev;
11662         struct drm_connector *connector;
11663         unsigned int used_ports = 0;
11664
11665         /*
11666          * Walk the connector list instead of the encoder
11667          * list to detect the problem on ddi platforms
11668          * where there's just one encoder per digital port.
11669          */
11670         drm_for_each_connector(connector, dev) {
11671                 struct drm_connector_state *connector_state;
11672                 struct intel_encoder *encoder;
11673
11674                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11675                 if (!connector_state)
11676                         connector_state = connector->state;
11677
11678                 if (!connector_state->best_encoder)
11679                         continue;
11680
11681                 encoder = to_intel_encoder(connector_state->best_encoder);
11682
11683                 WARN_ON(!connector_state->crtc);
11684
11685                 switch (encoder->type) {
11686                         unsigned int port_mask;
11687                 case INTEL_OUTPUT_UNKNOWN:
11688                         if (WARN_ON(!HAS_DDI(dev)))
11689                                 break;
11690                 case INTEL_OUTPUT_DISPLAYPORT:
11691                 case INTEL_OUTPUT_HDMI:
11692                 case INTEL_OUTPUT_EDP:
11693                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11694
11695                         /* the same port mustn't appear more than once */
11696                         if (used_ports & port_mask)
11697                                 return false;
11698
11699                         used_ports |= port_mask;
11700                 default:
11701                         break;
11702                 }
11703         }
11704
11705         return true;
11706 }
11707
11708 static void
11709 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11710 {
11711         struct drm_crtc_state tmp_state;
11712         struct intel_crtc_scaler_state scaler_state;
11713         struct intel_dpll_hw_state dpll_hw_state;
11714         struct intel_shared_dpll *shared_dpll;
11715         uint32_t ddi_pll_sel;
11716         bool force_thru;
11717
11718         /* FIXME: before the switch to atomic started, a new pipe_config was
11719          * kzalloc'd. Code that depends on any field being zero should be
11720          * fixed, so that the crtc_state can be safely duplicated. For now,
11721          * only fields that are know to not cause problems are preserved. */
11722
11723         tmp_state = crtc_state->base;
11724         scaler_state = crtc_state->scaler_state;
11725         shared_dpll = crtc_state->shared_dpll;
11726         dpll_hw_state = crtc_state->dpll_hw_state;
11727         ddi_pll_sel = crtc_state->ddi_pll_sel;
11728         force_thru = crtc_state->pch_pfit.force_thru;
11729
11730         memset(crtc_state, 0, sizeof *crtc_state);
11731
11732         crtc_state->base = tmp_state;
11733         crtc_state->scaler_state = scaler_state;
11734         crtc_state->shared_dpll = shared_dpll;
11735         crtc_state->dpll_hw_state = dpll_hw_state;
11736         crtc_state->ddi_pll_sel = ddi_pll_sel;
11737         crtc_state->pch_pfit.force_thru = force_thru;
11738 }
11739
11740 static int
11741 intel_modeset_pipe_config(struct drm_crtc *crtc,
11742                           struct intel_crtc_state *pipe_config)
11743 {
11744         struct drm_atomic_state *state = pipe_config->base.state;
11745         struct intel_encoder *encoder;
11746         struct drm_connector *connector;
11747         struct drm_connector_state *connector_state;
11748         int base_bpp, ret = -EINVAL;
11749         int i;
11750         bool retry = true;
11751
11752         clear_intel_crtc_state(pipe_config);
11753
11754         pipe_config->cpu_transcoder =
11755                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11756
11757         /*
11758          * Sanitize sync polarity flags based on requested ones. If neither
11759          * positive or negative polarity is requested, treat this as meaning
11760          * negative polarity.
11761          */
11762         if (!(pipe_config->base.adjusted_mode.flags &
11763               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11764                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11765
11766         if (!(pipe_config->base.adjusted_mode.flags &
11767               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11768                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11769
11770         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11771                                              pipe_config);
11772         if (base_bpp < 0)
11773                 goto fail;
11774
11775         /*
11776          * Determine the real pipe dimensions. Note that stereo modes can
11777          * increase the actual pipe size due to the frame doubling and
11778          * insertion of additional space for blanks between the frame. This
11779          * is stored in the crtc timings. We use the requested mode to do this
11780          * computation to clearly distinguish it from the adjusted mode, which
11781          * can be changed by the connectors in the below retry loop.
11782          */
11783         drm_crtc_get_hv_timing(&pipe_config->base.mode,
11784                                &pipe_config->pipe_src_w,
11785                                &pipe_config->pipe_src_h);
11786
11787 encoder_retry:
11788         /* Ensure the port clock defaults are reset when retrying. */
11789         pipe_config->port_clock = 0;
11790         pipe_config->pixel_multiplier = 1;
11791
11792         /* Fill in default crtc timings, allow encoders to overwrite them. */
11793         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11794                               CRTC_STEREO_DOUBLE);
11795
11796         /* Pass our mode to the connectors and the CRTC to give them a chance to
11797          * adjust it according to limitations or connector properties, and also
11798          * a chance to reject the mode entirely.
11799          */
11800         for_each_connector_in_state(state, connector, connector_state, i) {
11801                 if (connector_state->crtc != crtc)
11802                         continue;
11803
11804                 encoder = to_intel_encoder(connector_state->best_encoder);
11805
11806                 if (!(encoder->compute_config(encoder, pipe_config))) {
11807                         DRM_DEBUG_KMS("Encoder config failure\n");
11808                         goto fail;
11809                 }
11810         }
11811
11812         /* Set default port clock if not overwritten by the encoder. Needs to be
11813          * done afterwards in case the encoder adjusts the mode. */
11814         if (!pipe_config->port_clock)
11815                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11816                         * pipe_config->pixel_multiplier;
11817
11818         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11819         if (ret < 0) {
11820                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11821                 goto fail;
11822         }
11823
11824         if (ret == RETRY) {
11825                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11826                         ret = -EINVAL;
11827                         goto fail;
11828                 }
11829
11830                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11831                 retry = false;
11832                 goto encoder_retry;
11833         }
11834
11835         /* Dithering seems to not pass-through bits correctly when it should, so
11836          * only enable it on 6bpc panels. */
11837         pipe_config->dither = pipe_config->pipe_bpp == 6*3;
11838         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11839                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11840
11841 fail:
11842         return ret;
11843 }
11844
11845 static void
11846 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11847 {
11848         struct drm_crtc *crtc;
11849         struct drm_crtc_state *crtc_state;
11850         int i;
11851
11852         /* Double check state. */
11853         for_each_crtc_in_state(state, crtc, crtc_state, i) {
11854                 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
11855
11856                 /* Update hwmode for vblank functions */
11857                 if (crtc->state->active)
11858                         crtc->hwmode = crtc->state->adjusted_mode;
11859                 else
11860                         crtc->hwmode.crtc_clock = 0;
11861
11862                 /*
11863                  * Update legacy state to satisfy fbc code. This can
11864                  * be removed when fbc uses the atomic state.
11865                  */
11866                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11867                         struct drm_plane_state *plane_state = crtc->primary->state;
11868
11869                         crtc->primary->fb = plane_state->fb;
11870                         crtc->x = plane_state->src_x >> 16;
11871                         crtc->y = plane_state->src_y >> 16;
11872                 }
11873         }
11874 }
11875
11876 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11877 {
11878         int diff;
11879
11880         if (clock1 == clock2)
11881                 return true;
11882
11883         if (!clock1 || !clock2)
11884                 return false;
11885
11886         diff = abs(clock1 - clock2);
11887
11888         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11889                 return true;
11890
11891         return false;
11892 }
11893
11894 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11895         list_for_each_entry((intel_crtc), \
11896                             &(dev)->mode_config.crtc_list, \
11897                             base.head) \
11898                 for_each_if (mask & (1 <<(intel_crtc)->pipe))
11899
11900 static bool
11901 intel_compare_m_n(unsigned int m, unsigned int n,
11902                   unsigned int m2, unsigned int n2,
11903                   bool exact)
11904 {
11905         if (m == m2 && n == n2)
11906                 return true;
11907
11908         if (exact || !m || !n || !m2 || !n2)
11909                 return false;
11910
11911         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11912
11913         if (n > n2) {
11914                 while (n > n2) {
11915                         m2 <<= 1;
11916                         n2 <<= 1;
11917                 }
11918         } else if (n < n2) {
11919                 while (n < n2) {
11920                         m <<= 1;
11921                         n <<= 1;
11922                 }
11923         }
11924
11925         if (n != n2)
11926                 return false;
11927
11928         return intel_fuzzy_clock_check(m, m2);
11929 }
11930
11931 static bool
11932 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11933                        struct intel_link_m_n *m2_n2,
11934                        bool adjust)
11935 {
11936         if (m_n->tu == m2_n2->tu &&
11937             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11938                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11939             intel_compare_m_n(m_n->link_m, m_n->link_n,
11940                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11941                 if (adjust)
11942                         *m2_n2 = *m_n;
11943
11944                 return true;
11945         }
11946
11947         return false;
11948 }
11949
11950 static bool
11951 intel_pipe_config_compare(struct drm_device *dev,
11952                           struct intel_crtc_state *current_config,
11953                           struct intel_crtc_state *pipe_config,
11954                           bool adjust)
11955 {
11956         bool ret = true;
11957
11958 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
11959         do { \
11960                 if (!adjust) \
11961                         DRM_ERROR(fmt, ##__VA_ARGS__); \
11962                 else \
11963                         DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
11964         } while (0)
11965
11966 #define PIPE_CONF_CHECK_X(name) \
11967         if (current_config->name != pipe_config->name) { \
11968                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
11969                           "(expected 0x%08x, found 0x%08x)\n", \
11970                           current_config->name, \
11971                           pipe_config->name); \
11972                 ret = false; \
11973         }
11974
11975 #define PIPE_CONF_CHECK_I(name) \
11976         if (current_config->name != pipe_config->name) { \
11977                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
11978                           "(expected %i, found %i)\n", \
11979                           current_config->name, \
11980                           pipe_config->name); \
11981                 ret = false; \
11982         }
11983
11984 #define PIPE_CONF_CHECK_P(name) \
11985         if (current_config->name != pipe_config->name) { \
11986                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
11987                           "(expected %p, found %p)\n", \
11988                           current_config->name, \
11989                           pipe_config->name); \
11990                 ret = false; \
11991         }
11992
11993 #define PIPE_CONF_CHECK_M_N(name) \
11994         if (!intel_compare_link_m_n(&current_config->name, \
11995                                     &pipe_config->name,\
11996                                     adjust)) { \
11997                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
11998                           "(expected tu %i gmch %i/%i link %i/%i, " \
11999                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12000                           current_config->name.tu, \
12001                           current_config->name.gmch_m, \
12002                           current_config->name.gmch_n, \
12003                           current_config->name.link_m, \
12004                           current_config->name.link_n, \
12005                           pipe_config->name.tu, \
12006                           pipe_config->name.gmch_m, \
12007                           pipe_config->name.gmch_n, \
12008                           pipe_config->name.link_m, \
12009                           pipe_config->name.link_n); \
12010                 ret = false; \
12011         }
12012
12013 /* This is required for BDW+ where there is only one set of registers for
12014  * switching between high and low RR.
12015  * This macro can be used whenever a comparison has to be made between one
12016  * hw state and multiple sw state variables.
12017  */
12018 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12019         if (!intel_compare_link_m_n(&current_config->name, \
12020                                     &pipe_config->name, adjust) && \
12021             !intel_compare_link_m_n(&current_config->alt_name, \
12022                                     &pipe_config->name, adjust)) { \
12023                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12024                           "(expected tu %i gmch %i/%i link %i/%i, " \
12025                           "or tu %i gmch %i/%i link %i/%i, " \
12026                           "found tu %i, gmch %i/%i link %i/%i)\n", \
12027                           current_config->name.tu, \
12028                           current_config->name.gmch_m, \
12029                           current_config->name.gmch_n, \
12030                           current_config->name.link_m, \
12031                           current_config->name.link_n, \
12032                           current_config->alt_name.tu, \
12033                           current_config->alt_name.gmch_m, \
12034                           current_config->alt_name.gmch_n, \
12035                           current_config->alt_name.link_m, \
12036                           current_config->alt_name.link_n, \
12037                           pipe_config->name.tu, \
12038                           pipe_config->name.gmch_m, \
12039                           pipe_config->name.gmch_n, \
12040                           pipe_config->name.link_m, \
12041                           pipe_config->name.link_n); \
12042                 ret = false; \
12043         }
12044
12045 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
12046         if ((current_config->name ^ pipe_config->name) & (mask)) { \
12047                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12048                           "(expected %i, found %i)\n", \
12049                           current_config->name & (mask), \
12050                           pipe_config->name & (mask)); \
12051                 ret = false; \
12052         }
12053
12054 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12055         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12056                 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12057                           "(expected %i, found %i)\n", \
12058                           current_config->name, \
12059                           pipe_config->name); \
12060                 ret = false; \
12061         }
12062
12063 #define PIPE_CONF_QUIRK(quirk)  \
12064         ((current_config->quirks | pipe_config->quirks) & (quirk))
12065
12066         PIPE_CONF_CHECK_I(cpu_transcoder);
12067
12068         PIPE_CONF_CHECK_I(has_pch_encoder);
12069         PIPE_CONF_CHECK_I(fdi_lanes);
12070         PIPE_CONF_CHECK_M_N(fdi_m_n);
12071
12072         PIPE_CONF_CHECK_I(has_dp_encoder);
12073         PIPE_CONF_CHECK_I(lane_count);
12074
12075         if (INTEL_INFO(dev)->gen < 8) {
12076                 PIPE_CONF_CHECK_M_N(dp_m_n);
12077
12078                 if (current_config->has_drrs)
12079                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
12080         } else
12081                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12082
12083         PIPE_CONF_CHECK_I(has_dsi_encoder);
12084
12085         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12086         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12087         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12088         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12089         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12090         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12091
12092         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12093         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12094         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12095         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12096         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12097         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12098
12099         PIPE_CONF_CHECK_I(pixel_multiplier);
12100         PIPE_CONF_CHECK_I(has_hdmi_sink);
12101         if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12102             IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12103                 PIPE_CONF_CHECK_I(limited_color_range);
12104         PIPE_CONF_CHECK_I(has_infoframe);
12105
12106         PIPE_CONF_CHECK_I(has_audio);
12107
12108         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12109                               DRM_MODE_FLAG_INTERLACE);
12110
12111         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12112                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12113                                       DRM_MODE_FLAG_PHSYNC);
12114                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12115                                       DRM_MODE_FLAG_NHSYNC);
12116                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12117                                       DRM_MODE_FLAG_PVSYNC);
12118                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12119                                       DRM_MODE_FLAG_NVSYNC);
12120         }
12121
12122         PIPE_CONF_CHECK_X(gmch_pfit.control);
12123         /* pfit ratios are autocomputed by the hw on gen4+ */
12124         if (INTEL_INFO(dev)->gen < 4)
12125                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
12126         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12127
12128         if (!adjust) {
12129                 PIPE_CONF_CHECK_I(pipe_src_w);
12130                 PIPE_CONF_CHECK_I(pipe_src_h);
12131
12132                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12133                 if (current_config->pch_pfit.enabled) {
12134                         PIPE_CONF_CHECK_X(pch_pfit.pos);
12135                         PIPE_CONF_CHECK_X(pch_pfit.size);
12136                 }
12137
12138                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12139         }
12140
12141         /* BDW+ don't expose a synchronous way to read the state */
12142         if (IS_HASWELL(dev))
12143                 PIPE_CONF_CHECK_I(ips_enabled);
12144
12145         PIPE_CONF_CHECK_I(double_wide);
12146
12147         PIPE_CONF_CHECK_X(ddi_pll_sel);
12148
12149         PIPE_CONF_CHECK_P(shared_dpll);
12150         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12151         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12152         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12153         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12154         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12155         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12156         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12157         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12158         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12159
12160         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
12161         PIPE_CONF_CHECK_X(dsi_pll.div);
12162
12163         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12164                 PIPE_CONF_CHECK_I(pipe_bpp);
12165
12166         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12167         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12168
12169 #undef PIPE_CONF_CHECK_X
12170 #undef PIPE_CONF_CHECK_I
12171 #undef PIPE_CONF_CHECK_P
12172 #undef PIPE_CONF_CHECK_FLAGS
12173 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12174 #undef PIPE_CONF_QUIRK
12175 #undef INTEL_ERR_OR_DBG_KMS
12176
12177         return ret;
12178 }
12179
12180 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12181                                            const struct intel_crtc_state *pipe_config)
12182 {
12183         if (pipe_config->has_pch_encoder) {
12184                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12185                                                             &pipe_config->fdi_m_n);
12186                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12187
12188                 /*
12189                  * FDI already provided one idea for the dotclock.
12190                  * Yell if the encoder disagrees.
12191                  */
12192                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12193                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12194                      fdi_dotclock, dotclock);
12195         }
12196 }
12197
12198 static void verify_wm_state(struct drm_crtc *crtc,
12199                             struct drm_crtc_state *new_state)
12200 {
12201         struct drm_device *dev = crtc->dev;
12202         struct drm_i915_private *dev_priv = dev->dev_private;
12203         struct skl_ddb_allocation hw_ddb, *sw_ddb;
12204         struct skl_ddb_entry *hw_entry, *sw_entry;
12205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12206         const enum pipe pipe = intel_crtc->pipe;
12207         int plane;
12208
12209         if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
12210                 return;
12211
12212         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12213         sw_ddb = &dev_priv->wm.skl_hw.ddb;
12214
12215         /* planes */
12216         for_each_plane(dev_priv, pipe, plane) {
12217                 hw_entry = &hw_ddb.plane[pipe][plane];
12218                 sw_entry = &sw_ddb->plane[pipe][plane];
12219
12220                 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12221                         continue;
12222
12223                 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12224                           "(expected (%u,%u), found (%u,%u))\n",
12225                           pipe_name(pipe), plane + 1,
12226                           sw_entry->start, sw_entry->end,
12227                           hw_entry->start, hw_entry->end);
12228         }
12229
12230         /* cursor */
12231         hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12232         sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12233
12234         if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
12235                 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12236                           "(expected (%u,%u), found (%u,%u))\n",
12237                           pipe_name(pipe),
12238                           sw_entry->start, sw_entry->end,
12239                           hw_entry->start, hw_entry->end);
12240         }
12241 }
12242
12243 static void
12244 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
12245 {
12246         struct drm_connector *connector;
12247
12248         drm_for_each_connector(connector, dev) {
12249                 struct drm_encoder *encoder = connector->encoder;
12250                 struct drm_connector_state *state = connector->state;
12251
12252                 if (state->crtc != crtc)
12253                         continue;
12254
12255                 intel_connector_verify_state(to_intel_connector(connector),
12256                                              connector->state);
12257
12258                 I915_STATE_WARN(state->best_encoder != encoder,
12259                      "connector's atomic encoder doesn't match legacy encoder\n");
12260         }
12261 }
12262
12263 static void
12264 verify_encoder_state(struct drm_device *dev)
12265 {
12266         struct intel_encoder *encoder;
12267         struct intel_connector *connector;
12268
12269         for_each_intel_encoder(dev, encoder) {
12270                 bool enabled = false;
12271                 enum pipe pipe;
12272
12273                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12274                               encoder->base.base.id,
12275                               encoder->base.name);
12276
12277                 for_each_intel_connector(dev, connector) {
12278                         if (connector->base.state->best_encoder != &encoder->base)
12279                                 continue;
12280                         enabled = true;
12281
12282                         I915_STATE_WARN(connector->base.state->crtc !=
12283                                         encoder->base.crtc,
12284                              "connector's crtc doesn't match encoder crtc\n");
12285                 }
12286
12287                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12288                      "encoder's enabled state mismatch "
12289                      "(expected %i, found %i)\n",
12290                      !!encoder->base.crtc, enabled);
12291
12292                 if (!encoder->base.crtc) {
12293                         bool active;
12294
12295                         active = encoder->get_hw_state(encoder, &pipe);
12296                         I915_STATE_WARN(active,
12297                              "encoder detached but still enabled on pipe %c.\n",
12298                              pipe_name(pipe));
12299                 }
12300         }
12301 }
12302
12303 static void
12304 verify_crtc_state(struct drm_crtc *crtc,
12305                   struct drm_crtc_state *old_crtc_state,
12306                   struct drm_crtc_state *new_crtc_state)
12307 {
12308         struct drm_device *dev = crtc->dev;
12309         struct drm_i915_private *dev_priv = dev->dev_private;
12310         struct intel_encoder *encoder;
12311         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12312         struct intel_crtc_state *pipe_config, *sw_config;
12313         struct drm_atomic_state *old_state;
12314         bool active;
12315
12316         old_state = old_crtc_state->state;
12317         __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12318         pipe_config = to_intel_crtc_state(old_crtc_state);
12319         memset(pipe_config, 0, sizeof(*pipe_config));
12320         pipe_config->base.crtc = crtc;
12321         pipe_config->base.state = old_state;
12322
12323         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
12324
12325         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12326
12327         /* hw state is inconsistent with the pipe quirk */
12328         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12329             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12330                 active = new_crtc_state->active;
12331
12332         I915_STATE_WARN(new_crtc_state->active != active,
12333              "crtc active state doesn't match with hw state "
12334              "(expected %i, found %i)\n", new_crtc_state->active, active);
12335
12336         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12337              "transitional active state does not match atomic hw state "
12338              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12339
12340         for_each_encoder_on_crtc(dev, crtc, encoder) {
12341                 enum pipe pipe;
12342
12343                 active = encoder->get_hw_state(encoder, &pipe);
12344                 I915_STATE_WARN(active != new_crtc_state->active,
12345                         "[ENCODER:%i] active %i with crtc active %i\n",
12346                         encoder->base.base.id, active, new_crtc_state->active);
12347
12348                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12349                                 "Encoder connected to wrong pipe %c\n",
12350                                 pipe_name(pipe));
12351
12352                 if (active)
12353                         encoder->get_config(encoder, pipe_config);
12354         }
12355
12356         if (!new_crtc_state->active)
12357                 return;
12358
12359         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12360
12361         sw_config = to_intel_crtc_state(crtc->state);
12362         if (!intel_pipe_config_compare(dev, sw_config,
12363                                        pipe_config, false)) {
12364                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12365                 intel_dump_pipe_config(intel_crtc, pipe_config,
12366                                        "[hw state]");
12367                 intel_dump_pipe_config(intel_crtc, sw_config,
12368                                        "[sw state]");
12369         }
12370 }
12371
12372 static void
12373 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12374                          struct intel_shared_dpll *pll,
12375                          struct drm_crtc *crtc,
12376                          struct drm_crtc_state *new_state)
12377 {
12378         struct intel_dpll_hw_state dpll_hw_state;
12379         unsigned crtc_mask;
12380         bool active;
12381
12382         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12383
12384         DRM_DEBUG_KMS("%s\n", pll->name);
12385
12386         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12387
12388         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12389                 I915_STATE_WARN(!pll->on && pll->active_mask,
12390                      "pll in active use but not on in sw tracking\n");
12391                 I915_STATE_WARN(pll->on && !pll->active_mask,
12392                      "pll is on but not used by any active crtc\n");
12393                 I915_STATE_WARN(pll->on != active,
12394                      "pll on state mismatch (expected %i, found %i)\n",
12395                      pll->on, active);
12396         }
12397
12398         if (!crtc) {
12399                 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12400                                 "more active pll users than references: %x vs %x\n",
12401                                 pll->active_mask, pll->config.crtc_mask);
12402
12403                 return;
12404         }
12405
12406         crtc_mask = 1 << drm_crtc_index(crtc);
12407
12408         if (new_state->active)
12409                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12410                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12411                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12412         else
12413                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12414                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12415                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12416
12417         I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
12418                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12419                         crtc_mask, pll->config.crtc_mask);
12420
12421         I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
12422                                           &dpll_hw_state,
12423                                           sizeof(dpll_hw_state)),
12424                         "pll hw state mismatch\n");
12425 }
12426
12427 static void
12428 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12429                          struct drm_crtc_state *old_crtc_state,
12430                          struct drm_crtc_state *new_crtc_state)
12431 {
12432         struct drm_i915_private *dev_priv = dev->dev_private;
12433         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12434         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12435
12436         if (new_state->shared_dpll)
12437                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12438
12439         if (old_state->shared_dpll &&
12440             old_state->shared_dpll != new_state->shared_dpll) {
12441                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12442                 struct intel_shared_dpll *pll = old_state->shared_dpll;
12443
12444                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12445                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12446                                 pipe_name(drm_crtc_index(crtc)));
12447                 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
12448                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12449                                 pipe_name(drm_crtc_index(crtc)));
12450         }
12451 }
12452
12453 static void
12454 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12455                          struct drm_crtc_state *old_state,
12456                          struct drm_crtc_state *new_state)
12457 {
12458         verify_wm_state(crtc, new_state);
12459         verify_crtc_state(crtc, old_state, new_state);
12460         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12461 }
12462
12463 static void
12464 verify_disabled_dpll_state(struct drm_device *dev)
12465 {
12466         struct drm_i915_private *dev_priv = dev->dev_private;
12467         int i;
12468
12469         for (i = 0; i < dev_priv->num_shared_dpll; i++)
12470                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12471 }
12472
12473 static void
12474 intel_modeset_verify_disabled(struct drm_device *dev)
12475 {
12476         verify_encoder_state(dev);
12477         verify_connector_state(dev, NULL);
12478         verify_disabled_dpll_state(dev);
12479 }
12480
12481 static void update_scanline_offset(struct intel_crtc *crtc)
12482 {
12483         struct drm_device *dev = crtc->base.dev;
12484
12485         /*
12486          * The scanline counter increments at the leading edge of hsync.
12487          *
12488          * On most platforms it starts counting from vtotal-1 on the
12489          * first active line. That means the scanline counter value is
12490          * always one less than what we would expect. Ie. just after
12491          * start of vblank, which also occurs at start of hsync (on the
12492          * last active line), the scanline counter will read vblank_start-1.
12493          *
12494          * On gen2 the scanline counter starts counting from 1 instead
12495          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12496          * to keep the value positive), instead of adding one.
12497          *
12498          * On HSW+ the behaviour of the scanline counter depends on the output
12499          * type. For DP ports it behaves like most other platforms, but on HDMI
12500          * there's an extra 1 line difference. So we need to add two instead of
12501          * one to the value.
12502          */
12503         if (IS_GEN2(dev)) {
12504                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12505                 int vtotal;
12506
12507                 vtotal = adjusted_mode->crtc_vtotal;
12508                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12509                         vtotal /= 2;
12510
12511                 crtc->scanline_offset = vtotal - 1;
12512         } else if (HAS_DDI(dev) &&
12513                    intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12514                 crtc->scanline_offset = 2;
12515         } else
12516                 crtc->scanline_offset = 1;
12517 }
12518
12519 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12520 {
12521         struct drm_device *dev = state->dev;
12522         struct drm_i915_private *dev_priv = to_i915(dev);
12523         struct intel_shared_dpll_config *shared_dpll = NULL;
12524         struct drm_crtc *crtc;
12525         struct drm_crtc_state *crtc_state;
12526         int i;
12527
12528         if (!dev_priv->display.crtc_compute_clock)
12529                 return;
12530
12531         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12532                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12533                 struct intel_shared_dpll *old_dpll =
12534                         to_intel_crtc_state(crtc->state)->shared_dpll;
12535
12536                 if (!needs_modeset(crtc_state))
12537                         continue;
12538
12539                 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
12540
12541                 if (!old_dpll)
12542                         continue;
12543
12544                 if (!shared_dpll)
12545                         shared_dpll = intel_atomic_get_shared_dpll_state(state);
12546
12547                 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
12548         }
12549 }
12550
12551 /*
12552  * This implements the workaround described in the "notes" section of the mode
12553  * set sequence documentation. When going from no pipes or single pipe to
12554  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12555  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12556  */
12557 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12558 {
12559         struct drm_crtc_state *crtc_state;
12560         struct intel_crtc *intel_crtc;
12561         struct drm_crtc *crtc;
12562         struct intel_crtc_state *first_crtc_state = NULL;
12563         struct intel_crtc_state *other_crtc_state = NULL;
12564         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12565         int i;
12566
12567         /* look at all crtc's that are going to be enabled in during modeset */
12568         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12569                 intel_crtc = to_intel_crtc(crtc);
12570
12571                 if (!crtc_state->active || !needs_modeset(crtc_state))
12572                         continue;
12573
12574                 if (first_crtc_state) {
12575                         other_crtc_state = to_intel_crtc_state(crtc_state);
12576                         break;
12577                 } else {
12578                         first_crtc_state = to_intel_crtc_state(crtc_state);
12579                         first_pipe = intel_crtc->pipe;
12580                 }
12581         }
12582
12583         /* No workaround needed? */
12584         if (!first_crtc_state)
12585                 return 0;
12586
12587         /* w/a possibly needed, check how many crtc's are already enabled. */
12588         for_each_intel_crtc(state->dev, intel_crtc) {
12589                 struct intel_crtc_state *pipe_config;
12590
12591                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12592                 if (IS_ERR(pipe_config))
12593                         return PTR_ERR(pipe_config);
12594
12595                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12596
12597                 if (!pipe_config->base.active ||
12598                     needs_modeset(&pipe_config->base))
12599                         continue;
12600
12601                 /* 2 or more enabled crtcs means no need for w/a */
12602                 if (enabled_pipe != INVALID_PIPE)
12603                         return 0;
12604
12605                 enabled_pipe = intel_crtc->pipe;
12606         }
12607
12608         if (enabled_pipe != INVALID_PIPE)
12609                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12610         else if (other_crtc_state)
12611                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12612
12613         return 0;
12614 }
12615
12616 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12617 {
12618         struct drm_crtc *crtc;
12619         struct drm_crtc_state *crtc_state;
12620         int ret = 0;
12621
12622         /* add all active pipes to the state */
12623         for_each_crtc(state->dev, crtc) {
12624                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12625                 if (IS_ERR(crtc_state))
12626                         return PTR_ERR(crtc_state);
12627
12628                 if (!crtc_state->active || needs_modeset(crtc_state))
12629                         continue;
12630
12631                 crtc_state->mode_changed = true;
12632
12633                 ret = drm_atomic_add_affected_connectors(state, crtc);
12634                 if (ret)
12635                         break;
12636
12637                 ret = drm_atomic_add_affected_planes(state, crtc);
12638                 if (ret)
12639                         break;
12640         }
12641
12642         return ret;
12643 }
12644
12645 static int intel_modeset_checks(struct drm_atomic_state *state)
12646 {
12647         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12648         struct drm_i915_private *dev_priv = state->dev->dev_private;
12649         struct drm_crtc *crtc;
12650         struct drm_crtc_state *crtc_state;
12651         int ret = 0, i;
12652
12653         if (!check_digital_port_conflicts(state)) {
12654                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12655                 return -EINVAL;
12656         }
12657
12658         intel_state->modeset = true;
12659         intel_state->active_crtcs = dev_priv->active_crtcs;
12660
12661         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12662                 if (crtc_state->active)
12663                         intel_state->active_crtcs |= 1 << i;
12664                 else
12665                         intel_state->active_crtcs &= ~(1 << i);
12666
12667                 if (crtc_state->active != crtc->state->active)
12668                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12669         }
12670
12671         /*
12672          * See if the config requires any additional preparation, e.g.
12673          * to adjust global state with pipes off.  We need to do this
12674          * here so we can get the modeset_pipe updated config for the new
12675          * mode set on this crtc.  For other crtcs we need to use the
12676          * adjusted_mode bits in the crtc directly.
12677          */
12678         if (dev_priv->display.modeset_calc_cdclk) {
12679                 if (!intel_state->cdclk_pll_vco)
12680                         intel_state->cdclk_pll_vco = dev_priv->skl_vco_freq;
12681                 if (!intel_state->cdclk_pll_vco)
12682                         intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
12683
12684                 ret = dev_priv->display.modeset_calc_cdclk(state);
12685                 if (ret < 0)
12686                         return ret;
12687
12688                 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
12689                     intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq)
12690                         ret = intel_modeset_all_pipes(state);
12691
12692                 if (ret < 0)
12693                         return ret;
12694
12695                 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
12696                               intel_state->cdclk, intel_state->dev_cdclk);
12697         } else
12698                 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
12699
12700         intel_modeset_clear_plls(state);
12701
12702         if (IS_HASWELL(dev_priv))
12703                 return haswell_mode_set_planes_workaround(state);
12704
12705         return 0;
12706 }
12707
12708 /*
12709  * Handle calculation of various watermark data at the end of the atomic check
12710  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12711  * handlers to ensure that all derived state has been updated.
12712  */
12713 static int calc_watermark_data(struct drm_atomic_state *state)
12714 {
12715         struct drm_device *dev = state->dev;
12716         struct drm_i915_private *dev_priv = to_i915(dev);
12717
12718         /* Is there platform-specific watermark information to calculate? */
12719         if (dev_priv->display.compute_global_watermarks)
12720                 return dev_priv->display.compute_global_watermarks(state);
12721
12722         return 0;
12723 }
12724
12725 /**
12726  * intel_atomic_check - validate state object
12727  * @dev: drm device
12728  * @state: state to validate
12729  */
12730 static int intel_atomic_check(struct drm_device *dev,
12731                               struct drm_atomic_state *state)
12732 {
12733         struct drm_i915_private *dev_priv = to_i915(dev);
12734         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12735         struct drm_crtc *crtc;
12736         struct drm_crtc_state *crtc_state;
12737         int ret, i;
12738         bool any_ms = false;
12739
12740         ret = drm_atomic_helper_check_modeset(dev, state);
12741         if (ret)
12742                 return ret;
12743
12744         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12745                 struct intel_crtc_state *pipe_config =
12746                         to_intel_crtc_state(crtc_state);
12747
12748                 /* Catch I915_MODE_FLAG_INHERITED */
12749                 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
12750                         crtc_state->mode_changed = true;
12751
12752                 if (!needs_modeset(crtc_state))
12753                         continue;
12754
12755                 if (!crtc_state->enable) {
12756                         any_ms = true;
12757                         continue;
12758                 }
12759
12760                 /* FIXME: For only active_changed we shouldn't need to do any
12761                  * state recomputation at all. */
12762
12763                 ret = drm_atomic_add_affected_connectors(state, crtc);
12764                 if (ret)
12765                         return ret;
12766
12767                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12768                 if (ret) {
12769                         intel_dump_pipe_config(to_intel_crtc(crtc),
12770                                                pipe_config, "[failed]");
12771                         return ret;
12772                 }
12773
12774                 if (i915.fastboot &&
12775                     intel_pipe_config_compare(dev,
12776                                         to_intel_crtc_state(crtc->state),
12777                                         pipe_config, true)) {
12778                         crtc_state->mode_changed = false;
12779                         to_intel_crtc_state(crtc_state)->update_pipe = true;
12780                 }
12781
12782                 if (needs_modeset(crtc_state))
12783                         any_ms = true;
12784
12785                 ret = drm_atomic_add_affected_planes(state, crtc);
12786                 if (ret)
12787                         return ret;
12788
12789                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12790                                        needs_modeset(crtc_state) ?
12791                                        "[modeset]" : "[fastset]");
12792         }
12793
12794         if (any_ms) {
12795                 ret = intel_modeset_checks(state);
12796
12797                 if (ret)
12798                         return ret;
12799         } else
12800                 intel_state->cdclk = dev_priv->cdclk_freq;
12801
12802         ret = drm_atomic_helper_check_planes(dev, state);
12803         if (ret)
12804                 return ret;
12805
12806         intel_fbc_choose_crtc(dev_priv, state);
12807         return calc_watermark_data(state);
12808 }
12809
12810 static bool needs_work(struct drm_crtc_state *crtc_state)
12811 {
12812         /* hw state checker needs to run */
12813         if (needs_modeset(crtc_state))
12814                 return true;
12815
12816         /* unpin old fb's, possibly vblank update */
12817         if (crtc_state->planes_changed)
12818                 return true;
12819
12820         /* pipe parameters need to be updated, and hw state checker */
12821         if (to_intel_crtc_state(crtc_state)->update_pipe)
12822                 return true;
12823
12824         /* vblank event requested? */
12825         if (crtc_state->event)
12826                 return true;
12827
12828         return false;
12829 }
12830
12831 static int intel_atomic_prepare_commit(struct drm_device *dev,
12832                                        struct drm_atomic_state *state,
12833                                        bool nonblock)
12834 {
12835         struct drm_i915_private *dev_priv = dev->dev_private;
12836         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12837         struct drm_plane_state *plane_state;
12838         struct drm_crtc_state *crtc_state;
12839         struct drm_plane *plane;
12840         struct drm_crtc *crtc;
12841         int i, ret;
12842
12843         for_each_crtc_in_state(state, crtc, crtc_state, i) {
12844                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12845                 struct intel_flip_work *work;
12846
12847                 if (!state->legacy_cursor_update) {
12848                         ret = intel_crtc_wait_for_pending_flips(crtc);
12849                         if (ret)
12850                                 return ret;
12851
12852                         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12853                                 flush_workqueue(dev_priv->wq);
12854                 }
12855
12856                 /* test if we need to update something */
12857                 if (!needs_work(crtc_state))
12858                         continue;
12859
12860                 intel_state->work[i] = work =
12861                         kzalloc(sizeof(**intel_state->work), GFP_KERNEL);
12862
12863                 if (!work)
12864                         return -ENOMEM;
12865
12866                 if (needs_modeset(crtc_state) ||
12867                     to_intel_crtc_state(crtc_state)->update_pipe) {
12868                         work->num_old_connectors = hweight32(crtc->state->connector_mask);
12869
12870                         work->old_connector_state = kcalloc(work->num_old_connectors,
12871                                                             sizeof(*work->old_connector_state),
12872                                                             GFP_KERNEL);
12873
12874                         work->num_new_connectors = hweight32(crtc_state->connector_mask);
12875                         work->new_connector_state = kcalloc(work->num_new_connectors,
12876                                                             sizeof(*work->new_connector_state),
12877                                                             GFP_KERNEL);
12878
12879                         if (!work->old_connector_state || !work->new_connector_state)
12880                                 return -ENOMEM;
12881                 }
12882         }
12883
12884         if (intel_state->modeset && nonblock) {
12885                 DRM_DEBUG_ATOMIC("Nonblock modesets are not yet supported!\n");
12886                 return -EINVAL;
12887         }
12888
12889         ret = mutex_lock_interruptible(&dev->struct_mutex);
12890         if (ret)
12891                 return ret;
12892
12893         ret = drm_atomic_helper_prepare_planes(dev, state);
12894         mutex_unlock(&dev->struct_mutex);
12895
12896         if (!ret && !nonblock) {
12897                 for_each_plane_in_state(state, plane, plane_state, i) {
12898                         struct intel_plane_state *intel_plane_state =
12899                                 to_intel_plane_state(plane_state);
12900
12901                         if (plane_state->fence) {
12902                                 long lret = fence_wait(plane_state->fence, true);
12903
12904                                 if (lret < 0) {
12905                                         ret = lret;
12906                                         break;
12907                                 }
12908                         }
12909
12910                         if (!intel_plane_state->wait_req)
12911                                 continue;
12912
12913                         ret = __i915_wait_request(intel_plane_state->wait_req,
12914                                                   true, NULL, NULL);
12915                         if (ret) {
12916                                 /* Any hang should be swallowed by the wait */
12917                                 WARN_ON(ret == -EIO);
12918                                 mutex_lock(&dev->struct_mutex);
12919                                 drm_atomic_helper_cleanup_planes(dev, state);
12920                                 mutex_unlock(&dev->struct_mutex);
12921                                 break;
12922                         }
12923                 }
12924         }
12925
12926         return ret;
12927 }
12928
12929 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12930 {
12931         struct drm_device *dev = crtc->base.dev;
12932
12933         if (!dev->max_vblank_count)
12934                 return drm_accurate_vblank_count(&crtc->base);
12935
12936         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12937 }
12938
12939 static void intel_prepare_work(struct drm_crtc *crtc,
12940                                struct intel_flip_work *work,
12941                                struct drm_atomic_state *state,
12942                                struct drm_crtc_state *old_crtc_state)
12943 {
12944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12945         struct drm_plane_state *old_plane_state;
12946         struct drm_plane *plane;
12947         int i, j = 0;
12948
12949         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12950         INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12951         atomic_inc(&intel_crtc->unpin_work_count);
12952
12953         for_each_plane_in_state(state, plane, old_plane_state, i) {
12954                 struct intel_plane_state *old_state = to_intel_plane_state(old_plane_state);
12955                 struct intel_plane_state *new_state = to_intel_plane_state(plane->state);
12956
12957                 if (old_state->base.crtc != crtc &&
12958                     new_state->base.crtc != crtc)
12959                         continue;
12960
12961                 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
12962                         plane->fb = new_state->base.fb;
12963                         crtc->x = new_state->base.src_x >> 16;
12964                         crtc->y = new_state->base.src_y >> 16;
12965                 }
12966
12967                 old_state->wait_req = new_state->wait_req;
12968                 new_state->wait_req = NULL;
12969
12970                 old_state->base.fence = new_state->base.fence;
12971                 new_state->base.fence = NULL;
12972
12973                 /* remove plane state from the atomic state and move it to work */
12974                 old_plane_state->state = NULL;
12975                 state->planes[i] = NULL;
12976                 state->plane_states[i] = NULL;
12977
12978                 work->old_plane_state[j] = old_state;
12979                 work->new_plane_state[j++] = new_state;
12980         }
12981
12982         old_crtc_state->state = NULL;
12983         state->crtcs[drm_crtc_index(crtc)] = NULL;
12984         state->crtc_states[drm_crtc_index(crtc)] = NULL;
12985
12986         work->old_crtc_state = to_intel_crtc_state(old_crtc_state);
12987         work->new_crtc_state = to_intel_crtc_state(crtc->state);
12988         work->num_planes = j;
12989
12990         work->event = crtc->state->event;
12991         crtc->state->event = NULL;
12992
12993         if (needs_modeset(crtc->state) || work->new_crtc_state->update_pipe) {
12994                 struct drm_connector *conn;
12995                 struct drm_connector_state *old_conn_state;
12996                 int k = 0;
12997
12998                 j = 0;
12999
13000                 /*
13001                  * intel_unpin_work_fn cannot depend on the connector list
13002                  * because it may be freed from underneath it, so add
13003                  * them all to the work struct while we're holding locks.
13004                  */
13005                 for_each_connector_in_state(state, conn, old_conn_state, i) {
13006                         if (old_conn_state->crtc == crtc) {
13007                                 work->old_connector_state[j++] = old_conn_state;
13008
13009                                 state->connectors[i] = NULL;
13010                                 state->connector_states[i] = NULL;
13011                         }
13012                 }
13013
13014                 /* If another crtc has stolen the connector from state,
13015                  * then for_each_connector_in_state is no longer reliable,
13016                  * so use drm_for_each_connector here.
13017                  */
13018                 drm_for_each_connector(conn, state->dev)
13019                         if (conn->state->crtc == crtc)
13020                                 work->new_connector_state[k++] = conn->state;
13021
13022                 WARN(j != work->num_old_connectors, "j = %i, expected %i\n", j, work->num_old_connectors);
13023                 WARN(k != work->num_new_connectors, "k = %i, expected %i\n", k, work->num_new_connectors);
13024         } else if (!work->new_crtc_state->update_wm_post)
13025                 work->can_async_unpin = true;
13026
13027         work->fb_bits = work->new_crtc_state->fb_bits;
13028 }
13029
13030 static void intel_schedule_unpin(struct drm_crtc *crtc,
13031                                  struct intel_atomic_state *state,
13032                                  struct intel_flip_work *work)
13033 {
13034         struct drm_device *dev = crtc->dev;
13035         struct drm_i915_private *dev_priv = dev->dev_private;
13036
13037         to_intel_crtc(crtc)->config = work->new_crtc_state;
13038
13039         queue_work(dev_priv->wq, &work->unpin_work);
13040 }
13041
13042 static void intel_schedule_flip(struct drm_crtc *crtc,
13043                                 struct intel_atomic_state *state,
13044                                 struct intel_flip_work *work,
13045                                 bool nonblock)
13046 {
13047         struct intel_crtc_state *crtc_state = work->new_crtc_state;
13048
13049         if (crtc_state->base.planes_changed ||
13050             needs_modeset(&crtc_state->base) ||
13051             crtc_state->update_pipe) {
13052                 if (nonblock)
13053                         schedule_work(&work->mmio_work);
13054                 else
13055                         intel_mmio_flip_work_func(&work->mmio_work);
13056         } else {
13057                 int ret;
13058
13059                 ret = drm_crtc_vblank_get(crtc);
13060                 I915_STATE_WARN(ret < 0, "enabling vblank failed with %i\n", ret);
13061
13062                 work->flip_queued_vblank = intel_crtc_get_vblank_counter(to_intel_crtc(crtc));
13063                 smp_mb__before_atomic();
13064                 atomic_set(&work->pending, 1);
13065         }
13066 }
13067
13068 static void intel_schedule_update(struct drm_crtc *crtc,
13069                                   struct intel_atomic_state *state,
13070                                   struct intel_flip_work *work,
13071                                   bool nonblock)
13072 {
13073         struct drm_device *dev = crtc->dev;
13074         struct intel_crtc_state *pipe_config = work->new_crtc_state;
13075
13076         if (!pipe_config->base.active && work->can_async_unpin) {
13077                 INIT_LIST_HEAD(&work->head);
13078                 intel_schedule_unpin(crtc, state, work);
13079                 return;
13080         }
13081
13082         spin_lock_irq(&dev->event_lock);
13083         list_add_tail(&work->head, &to_intel_crtc(crtc)->flip_work);
13084         spin_unlock_irq(&dev->event_lock);
13085
13086         if (!pipe_config->base.active)
13087                 intel_schedule_unpin(crtc, state, work);
13088         else
13089                 intel_schedule_flip(crtc, state, work, nonblock);
13090 }
13091
13092 /**
13093  * intel_atomic_commit - commit validated state object
13094  * @dev: DRM device
13095  * @state: the top-level driver state object
13096  * @nonblock: nonblocking commit
13097  *
13098  * This function commits a top-level state object that has been validated
13099  * with drm_atomic_helper_check().
13100  *
13101  * FIXME:  Atomic modeset support for i915 is not yet complete.  At the moment
13102  * we can only handle plane-related operations and do not yet support
13103  * nonblocking commit.
13104  *
13105  * RETURNS
13106  * Zero for success or -errno.
13107  */
13108 static int intel_atomic_commit(struct drm_device *dev,
13109                                struct drm_atomic_state *state,
13110                                bool nonblock)
13111 {
13112         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13113         struct drm_i915_private *dev_priv = dev->dev_private;
13114         struct drm_crtc_state *old_crtc_state;
13115         struct drm_crtc *crtc;
13116         int ret = 0, i;
13117
13118         ret = intel_atomic_prepare_commit(dev, state, nonblock);
13119         if (ret) {
13120                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13121                 return ret;
13122         }
13123
13124         drm_atomic_helper_swap_state(dev, state);
13125         dev_priv->wm.distrust_bios_wm = false;
13126         dev_priv->wm.skl_results = intel_state->wm_results;
13127         intel_shared_dpll_commit(state);
13128
13129         if (intel_state->modeset) {
13130                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13131                        sizeof(intel_state->min_pixclk));
13132                 dev_priv->active_crtcs = intel_state->active_crtcs;
13133                 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13134         }
13135
13136         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13137                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13138
13139                 if (!needs_modeset(crtc->state))
13140                         continue;
13141
13142                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13143
13144                 intel_state->work[i]->put_power_domains =
13145                         modeset_get_crtc_power_domains(crtc,
13146                                 to_intel_crtc_state(crtc->state));
13147
13148                 if (old_crtc_state->active) {
13149                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13150                         dev_priv->display.crtc_disable(crtc);
13151                         intel_crtc->active = false;
13152                         intel_fbc_disable(intel_crtc);
13153                         intel_disable_shared_dpll(intel_crtc);
13154
13155                         /*
13156                          * Underruns don't always raise
13157                          * interrupts, so check manually.
13158                          */
13159                         intel_check_cpu_fifo_underruns(dev_priv);
13160                         intel_check_pch_fifo_underruns(dev_priv);
13161
13162                         if (!crtc->state->active)
13163                                 intel_update_watermarks(crtc);
13164                 }
13165         }
13166
13167         /* Only after disabling all output pipelines that will be changed can we
13168          * update the the output configuration. */
13169         intel_modeset_update_crtc_state(state);
13170
13171         if (intel_state->modeset) {
13172                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13173
13174                 if (dev_priv->display.modeset_commit_cdclk &&
13175                     (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13176                      intel_state->cdclk_pll_vco != dev_priv->skl_vco_freq))
13177                         dev_priv->display.modeset_commit_cdclk(state);
13178
13179                 intel_modeset_verify_disabled(dev);
13180         }
13181
13182         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13183         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13184                 struct intel_flip_work *work = intel_state->work[i];
13185                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13186                 bool modeset = needs_modeset(crtc->state);
13187
13188                 if (modeset && crtc->state->active) {
13189                         update_scanline_offset(to_intel_crtc(crtc));
13190                         dev_priv->display.crtc_enable(crtc);
13191                 }
13192
13193                 if (!modeset)
13194                         intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13195
13196                 if (!work) {
13197                         if (!list_empty_careful(&intel_crtc->flip_work)) {
13198                                 spin_lock_irq(&dev->event_lock);
13199                                 if (!list_empty(&intel_crtc->flip_work))
13200                                         work = list_last_entry(&intel_crtc->flip_work,
13201                                                                struct intel_flip_work, head);
13202
13203                                 if (work && work->new_crtc_state == to_intel_crtc_state(old_crtc_state)) {
13204                                         work->free_new_crtc_state = true;
13205                                         state->crtc_states[i] = NULL;
13206                                         state->crtcs[i] = NULL;
13207                                 }
13208                                 spin_unlock_irq(&dev->event_lock);
13209                         }
13210                         continue;
13211                 }
13212
13213                 intel_state->work[i] = NULL;
13214                 intel_prepare_work(crtc, work, state, old_crtc_state);
13215                 intel_schedule_update(crtc, intel_state, work, nonblock);
13216         }
13217
13218         /* FIXME: add subpixel order */
13219
13220         drm_atomic_state_free(state);
13221
13222         /* As one of the primary mmio accessors, KMS has a high likelihood
13223          * of triggering bugs in unclaimed access. After we finish
13224          * modesetting, see if an error has been flagged, and if so
13225          * enable debugging for the next modeset - and hope we catch
13226          * the culprit.
13227          *
13228          * XXX note that we assume display power is on at this point.
13229          * This might hold true now but we need to add pm helper to check
13230          * unclaimed only when the hardware is on, as atomic commits
13231          * can happen also when the device is completely off.
13232          */
13233         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13234
13235         return 0;
13236 }
13237
13238 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13239 {
13240         struct drm_device *dev = crtc->dev;
13241         struct drm_atomic_state *state;
13242         struct drm_crtc_state *crtc_state;
13243         int ret;
13244
13245         state = drm_atomic_state_alloc(dev);
13246         if (!state) {
13247                 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13248                               crtc->base.id);
13249                 return;
13250         }
13251
13252         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13253
13254 retry:
13255         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13256         ret = PTR_ERR_OR_ZERO(crtc_state);
13257         if (!ret) {
13258                 if (!crtc_state->active)
13259                         goto out;
13260
13261                 crtc_state->mode_changed = true;
13262                 ret = drm_atomic_commit(state);
13263         }
13264
13265         if (ret == -EDEADLK) {
13266                 drm_atomic_state_clear(state);
13267                 drm_modeset_backoff(state->acquire_ctx);
13268                 goto retry;
13269         }
13270
13271         if (ret)
13272 out:
13273                 drm_atomic_state_free(state);
13274 }
13275
13276 #undef for_each_intel_crtc_masked
13277
13278 static const struct drm_crtc_funcs intel_crtc_funcs = {
13279         .gamma_set = drm_atomic_helper_legacy_gamma_set,
13280         .set_config = drm_atomic_helper_set_config,
13281         .set_property = drm_atomic_helper_crtc_set_property,
13282         .destroy = intel_crtc_destroy,
13283         .page_flip = drm_atomic_helper_page_flip,
13284         .atomic_duplicate_state = intel_crtc_duplicate_state,
13285         .atomic_destroy_state = intel_crtc_destroy_state,
13286 };
13287
13288 static struct fence *intel_get_excl_fence(struct drm_i915_gem_object *obj)
13289 {
13290         struct reservation_object *resv;
13291
13292
13293         if (!obj->base.dma_buf)
13294                 return NULL;
13295
13296         resv = obj->base.dma_buf->resv;
13297
13298         /* For framebuffer backed by dmabuf, wait for fence */
13299         while (1) {
13300                 struct fence *fence_excl, *ret = NULL;
13301
13302                 rcu_read_lock();
13303
13304                 fence_excl = rcu_dereference(resv->fence_excl);
13305                 if (fence_excl)
13306                         ret = fence_get_rcu(fence_excl);
13307
13308                 rcu_read_unlock();
13309
13310                 if (ret == fence_excl)
13311                         return ret;
13312         }
13313 }
13314
13315 /**
13316  * intel_prepare_plane_fb - Prepare fb for usage on plane
13317  * @plane: drm plane to prepare for
13318  * @fb: framebuffer to prepare for presentation
13319  *
13320  * Prepares a framebuffer for usage on a display plane.  Generally this
13321  * involves pinning the underlying object and updating the frontbuffer tracking
13322  * bits.  Some older platforms need special physical address handling for
13323  * cursor planes.
13324  *
13325  * Must be called with struct_mutex held.
13326  *
13327  * Returns 0 on success, negative error code on failure.
13328  */
13329 int
13330 intel_prepare_plane_fb(struct drm_plane *plane,
13331                        const struct drm_plane_state *new_state)
13332 {
13333         struct drm_device *dev = plane->dev;
13334         struct drm_framebuffer *fb = new_state->fb;
13335         struct intel_plane *intel_plane = to_intel_plane(plane);
13336         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13337         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13338         struct drm_crtc *crtc = new_state->crtc ?: plane->state->crtc;
13339         int ret = 0;
13340
13341         if (!obj && !old_obj)
13342                 return 0;
13343
13344         if (WARN_ON(!new_state->state) || WARN_ON(!crtc) ||
13345             WARN_ON(!to_intel_atomic_state(new_state->state)->work[to_intel_crtc(crtc)->pipe])) {
13346                 if (WARN_ON(old_obj != obj))
13347                         return -EINVAL;
13348
13349                 return 0;
13350         }
13351
13352         if (old_obj) {
13353                 struct drm_crtc_state *crtc_state =
13354                         drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13355
13356                 /* Big Hammer, we also need to ensure that any pending
13357                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13358                  * current scanout is retired before unpinning the old
13359                  * framebuffer. Note that we rely on userspace rendering
13360                  * into the buffer attached to the pipe they are waiting
13361                  * on. If not, userspace generates a GPU hang with IPEHR
13362                  * point to the MI_WAIT_FOR_EVENT.
13363                  *
13364                  * This should only fail upon a hung GPU, in which case we
13365                  * can safely continue.
13366                  */
13367                 if (needs_modeset(crtc_state))
13368                         ret = i915_gem_object_wait_rendering(old_obj, true);
13369                 if (ret) {
13370                         /* GPU hangs should have been swallowed by the wait */
13371                         WARN_ON(ret == -EIO);
13372                         return ret;
13373                 }
13374         }
13375
13376         if (!obj) {
13377                 ret = 0;
13378         } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13379             INTEL_INFO(dev)->cursor_needs_physical) {
13380                 int align = IS_I830(dev) ? 16 * 1024 : 256;
13381                 ret = i915_gem_object_attach_phys(obj, align);
13382                 if (ret)
13383                         DRM_DEBUG_KMS("failed to attach phys object\n");
13384         } else {
13385                 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13386         }
13387
13388         if (ret == 0) {
13389                 if (obj) {
13390                         struct intel_plane_state *plane_state =
13391                                 to_intel_plane_state(new_state);
13392
13393                         i915_gem_request_assign(&plane_state->wait_req,
13394                                                 obj->last_write_req);
13395
13396                         plane_state->base.fence = intel_get_excl_fence(obj);
13397                 }
13398
13399                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13400         }
13401
13402         return ret;
13403 }
13404
13405 /**
13406  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13407  * @plane: drm plane to clean up for
13408  * @fb: old framebuffer that was on plane
13409  *
13410  * Cleans up a framebuffer that has just been removed from a plane.
13411  *
13412  * Must be called with struct_mutex held.
13413  */
13414 void
13415 intel_cleanup_plane_fb(struct drm_plane *plane,
13416                        const struct drm_plane_state *old_state)
13417 {
13418         struct drm_device *dev = plane->dev;
13419         struct intel_plane *intel_plane = to_intel_plane(plane);
13420         struct intel_plane_state *old_intel_state;
13421         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13422         struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13423
13424         old_intel_state = to_intel_plane_state(old_state);
13425
13426         if (!obj && !old_obj)
13427                 return;
13428
13429         if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13430             !INTEL_INFO(dev)->cursor_needs_physical))
13431                 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13432
13433         /* prepare_fb aborted? */
13434         if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13435             (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13436                 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13437
13438         i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13439
13440         fence_put(old_intel_state->base.fence);
13441         old_intel_state->base.fence = NULL;
13442 }
13443
13444 int
13445 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13446 {
13447         int max_scale;
13448         struct drm_device *dev;
13449         struct drm_i915_private *dev_priv;
13450         int crtc_clock, cdclk;
13451
13452         if (!intel_crtc || !crtc_state->base.enable)
13453                 return DRM_PLANE_HELPER_NO_SCALING;
13454
13455         dev = intel_crtc->base.dev;
13456         dev_priv = dev->dev_private;
13457         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13458         cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13459
13460         if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13461                 return DRM_PLANE_HELPER_NO_SCALING;
13462
13463         /*
13464          * skl max scale is lower of:
13465          *    close to 3 but not 3, -1 is for that purpose
13466          *            or
13467          *    cdclk/crtc_clock
13468          */
13469         max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13470
13471         return max_scale;
13472 }
13473
13474 static int
13475 intel_check_primary_plane(struct drm_plane *plane,
13476                           struct intel_crtc_state *crtc_state,
13477                           struct intel_plane_state *state)
13478 {
13479         struct drm_crtc *crtc = state->base.crtc;
13480         struct drm_framebuffer *fb = state->base.fb;
13481         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13482         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13483         bool can_position = false;
13484
13485         if (INTEL_INFO(plane->dev)->gen >= 9) {
13486                 /* use scaler when colorkey is not required */
13487                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13488                         min_scale = 1;
13489                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13490                 }
13491                 can_position = true;
13492         }
13493
13494         return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13495                                              &state->dst, &state->clip,
13496                                              min_scale, max_scale,
13497                                              can_position, true,
13498                                              &state->visible);
13499 }
13500
13501 /**
13502  * intel_plane_destroy - destroy a plane
13503  * @plane: plane to destroy
13504  *
13505  * Common destruction function for all types of planes (primary, cursor,
13506  * sprite).
13507  */
13508 void intel_plane_destroy(struct drm_plane *plane)
13509 {
13510         struct intel_plane *intel_plane = to_intel_plane(plane);
13511         drm_plane_cleanup(plane);
13512         kfree(intel_plane);
13513 }
13514
13515 const struct drm_plane_funcs intel_plane_funcs = {
13516         .update_plane = drm_atomic_helper_update_plane,
13517         .disable_plane = drm_atomic_helper_disable_plane,
13518         .destroy = intel_plane_destroy,
13519         .set_property = drm_atomic_helper_plane_set_property,
13520         .atomic_get_property = intel_plane_atomic_get_property,
13521         .atomic_set_property = intel_plane_atomic_set_property,
13522         .atomic_duplicate_state = intel_plane_duplicate_state,
13523         .atomic_destroy_state = intel_plane_destroy_state,
13524
13525 };
13526
13527 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13528                                                     int pipe)
13529 {
13530         struct intel_plane *primary = NULL;
13531         struct intel_plane_state *state = NULL;
13532         const uint32_t *intel_primary_formats;
13533         unsigned int num_formats;
13534         int ret;
13535
13536         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13537         if (!primary)
13538                 goto fail;
13539
13540         state = intel_create_plane_state(&primary->base);
13541         if (!state)
13542                 goto fail;
13543         primary->base.state = &state->base;
13544
13545         primary->can_scale = false;
13546         primary->max_downscale = 1;
13547         if (INTEL_INFO(dev)->gen >= 9) {
13548                 primary->can_scale = true;
13549                 state->scaler_id = -1;
13550         }
13551         primary->pipe = pipe;
13552         primary->plane = pipe;
13553         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13554         primary->check_plane = intel_check_primary_plane;
13555         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13556                 primary->plane = !pipe;
13557
13558         if (INTEL_INFO(dev)->gen >= 9) {
13559                 intel_primary_formats = skl_primary_formats;
13560                 num_formats = ARRAY_SIZE(skl_primary_formats);
13561
13562                 primary->update_plane = skylake_update_primary_plane;
13563                 primary->disable_plane = skylake_disable_primary_plane;
13564         } else if (HAS_PCH_SPLIT(dev)) {
13565                 intel_primary_formats = i965_primary_formats;
13566                 num_formats = ARRAY_SIZE(i965_primary_formats);
13567
13568                 primary->update_plane = ironlake_update_primary_plane;
13569                 primary->disable_plane = i9xx_disable_primary_plane;
13570         } else if (INTEL_INFO(dev)->gen >= 4) {
13571                 intel_primary_formats = i965_primary_formats;
13572                 num_formats = ARRAY_SIZE(i965_primary_formats);
13573
13574                 primary->update_plane = i9xx_update_primary_plane;
13575                 primary->disable_plane = i9xx_disable_primary_plane;
13576         } else {
13577                 intel_primary_formats = i8xx_primary_formats;
13578                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13579
13580                 primary->update_plane = i9xx_update_primary_plane;
13581                 primary->disable_plane = i9xx_disable_primary_plane;
13582         }
13583
13584         ret = drm_universal_plane_init(dev, &primary->base, 0,
13585                                        &intel_plane_funcs,
13586                                        intel_primary_formats, num_formats,
13587                                        DRM_PLANE_TYPE_PRIMARY, NULL);
13588         if (ret)
13589                 goto fail;
13590
13591         if (INTEL_INFO(dev)->gen >= 4)
13592                 intel_create_rotation_property(dev, primary);
13593
13594         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13595
13596         return &primary->base;
13597
13598 fail:
13599         kfree(state);
13600         kfree(primary);
13601
13602         return NULL;
13603 }
13604
13605 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13606 {
13607         if (!dev->mode_config.rotation_property) {
13608                 unsigned long flags = BIT(DRM_ROTATE_0) |
13609                         BIT(DRM_ROTATE_180);
13610
13611                 if (INTEL_INFO(dev)->gen >= 9)
13612                         flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13613
13614                 dev->mode_config.rotation_property =
13615                         drm_mode_create_rotation_property(dev, flags);
13616         }
13617         if (dev->mode_config.rotation_property)
13618                 drm_object_attach_property(&plane->base.base,
13619                                 dev->mode_config.rotation_property,
13620                                 plane->base.state->rotation);
13621 }
13622
13623 static int
13624 intel_check_cursor_plane(struct drm_plane *plane,
13625                          struct intel_crtc_state *crtc_state,
13626                          struct intel_plane_state *state)
13627 {
13628         struct drm_crtc *crtc = crtc_state->base.crtc;
13629         struct drm_framebuffer *fb = state->base.fb;
13630         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13631         enum pipe pipe = to_intel_plane(plane)->pipe;
13632         unsigned stride;
13633         int ret;
13634
13635         ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13636                                             &state->dst, &state->clip,
13637                                             DRM_PLANE_HELPER_NO_SCALING,
13638                                             DRM_PLANE_HELPER_NO_SCALING,
13639                                             true, true, &state->visible);
13640         if (ret)
13641                 return ret;
13642
13643         /* if we want to turn off the cursor ignore width and height */
13644         if (!obj)
13645                 return 0;
13646
13647         /* Check for which cursor types we support */
13648         if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13649                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13650                           state->base.crtc_w, state->base.crtc_h);
13651                 return -EINVAL;
13652         }
13653
13654         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13655         if (obj->base.size < stride * state->base.crtc_h) {
13656                 DRM_DEBUG_KMS("buffer is too small\n");
13657                 return -ENOMEM;
13658         }
13659
13660         if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13661                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13662                 return -EINVAL;
13663         }
13664
13665         /*
13666          * There's something wrong with the cursor on CHV pipe C.
13667          * If it straddles the left edge of the screen then
13668          * moving it away from the edge or disabling it often
13669          * results in a pipe underrun, and often that can lead to
13670          * dead pipe (constant underrun reported, and it scans
13671          * out just a solid color). To recover from that, the
13672          * display power well must be turned off and on again.
13673          * Refuse the put the cursor into that compromised position.
13674          */
13675         if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
13676             state->visible && state->base.crtc_x < 0) {
13677                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13678                 return -EINVAL;
13679         }
13680
13681         return 0;
13682 }
13683
13684 static void
13685 intel_disable_cursor_plane(struct drm_plane *plane,
13686                            struct drm_crtc *crtc)
13687 {
13688         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13689
13690         intel_crtc->cursor_addr = 0;
13691         intel_crtc_update_cursor(crtc, NULL);
13692 }
13693
13694 static void
13695 intel_update_cursor_plane(struct drm_plane *plane,
13696                           const struct intel_crtc_state *crtc_state,
13697                           const struct intel_plane_state *state)
13698 {
13699         struct drm_crtc *crtc = crtc_state->base.crtc;
13700         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13701         struct drm_device *dev = plane->dev;
13702         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13703         uint32_t addr;
13704
13705         if (!obj)
13706                 addr = 0;
13707         else if (!INTEL_INFO(dev)->cursor_needs_physical)
13708                 addr = i915_gem_obj_ggtt_offset(obj);
13709         else
13710                 addr = obj->phys_handle->busaddr;
13711
13712         intel_crtc->cursor_addr = addr;
13713         intel_crtc_update_cursor(crtc, state);
13714 }
13715
13716 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13717                                                    int pipe)
13718 {
13719         struct intel_plane *cursor = NULL;
13720         struct intel_plane_state *state = NULL;
13721         int ret;
13722
13723         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13724         if (!cursor)
13725                 goto fail;
13726
13727         state = intel_create_plane_state(&cursor->base);
13728         if (!state)
13729                 goto fail;
13730         cursor->base.state = &state->base;
13731
13732         cursor->can_scale = false;
13733         cursor->max_downscale = 1;
13734         cursor->pipe = pipe;
13735         cursor->plane = pipe;
13736         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13737         cursor->check_plane = intel_check_cursor_plane;
13738         cursor->update_plane = intel_update_cursor_plane;
13739         cursor->disable_plane = intel_disable_cursor_plane;
13740
13741         ret = drm_universal_plane_init(dev, &cursor->base, 0,
13742                                        &intel_plane_funcs,
13743                                        intel_cursor_formats,
13744                                        ARRAY_SIZE(intel_cursor_formats),
13745                                        DRM_PLANE_TYPE_CURSOR, NULL);
13746         if (ret)
13747                 goto fail;
13748
13749         if (INTEL_INFO(dev)->gen >= 4) {
13750                 if (!dev->mode_config.rotation_property)
13751                         dev->mode_config.rotation_property =
13752                                 drm_mode_create_rotation_property(dev,
13753                                                         BIT(DRM_ROTATE_0) |
13754                                                         BIT(DRM_ROTATE_180));
13755                 if (dev->mode_config.rotation_property)
13756                         drm_object_attach_property(&cursor->base.base,
13757                                 dev->mode_config.rotation_property,
13758                                 state->base.rotation);
13759         }
13760
13761         if (INTEL_INFO(dev)->gen >=9)
13762                 state->scaler_id = -1;
13763
13764         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13765
13766         return &cursor->base;
13767
13768 fail:
13769         kfree(state);
13770         kfree(cursor);
13771
13772         return NULL;
13773 }
13774
13775 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13776         struct intel_crtc_state *crtc_state)
13777 {
13778         int i;
13779         struct intel_scaler *intel_scaler;
13780         struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13781
13782         for (i = 0; i < intel_crtc->num_scalers; i++) {
13783                 intel_scaler = &scaler_state->scalers[i];
13784                 intel_scaler->in_use = 0;
13785                 intel_scaler->mode = PS_SCALER_MODE_DYN;
13786         }
13787
13788         scaler_state->scaler_id = -1;
13789 }
13790
13791 static void intel_crtc_init(struct drm_device *dev, int pipe)
13792 {
13793         struct drm_i915_private *dev_priv = dev->dev_private;
13794         struct intel_crtc *intel_crtc;
13795         struct intel_crtc_state *crtc_state = NULL;
13796         struct drm_plane *primary = NULL;
13797         struct drm_plane *cursor = NULL;
13798         int ret;
13799
13800         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13801         if (intel_crtc == NULL)
13802                 return;
13803
13804         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13805         if (!crtc_state)
13806                 goto fail;
13807         intel_crtc->config = crtc_state;
13808         intel_crtc->base.state = &crtc_state->base;
13809         crtc_state->base.crtc = &intel_crtc->base;
13810
13811         INIT_LIST_HEAD(&intel_crtc->flip_work);
13812
13813         /* initialize shared scalers */
13814         if (INTEL_INFO(dev)->gen >= 9) {
13815                 if (pipe == PIPE_C)
13816                         intel_crtc->num_scalers = 1;
13817                 else
13818                         intel_crtc->num_scalers = SKL_NUM_SCALERS;
13819
13820                 skl_init_scalers(dev, intel_crtc, crtc_state);
13821         }
13822
13823         primary = intel_primary_plane_create(dev, pipe);
13824         if (!primary)
13825                 goto fail;
13826
13827         cursor = intel_cursor_plane_create(dev, pipe);
13828         if (!cursor)
13829                 goto fail;
13830
13831         ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13832                                         cursor, &intel_crtc_funcs, NULL);
13833         if (ret)
13834                 goto fail;
13835
13836         /*
13837          * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13838          * is hooked to pipe B. Hence we want plane A feeding pipe B.
13839          */
13840         intel_crtc->pipe = pipe;
13841         intel_crtc->plane = pipe;
13842         if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13843                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13844                 intel_crtc->plane = !pipe;
13845         }
13846
13847         intel_crtc->cursor_base = ~0;
13848         intel_crtc->cursor_cntl = ~0;
13849         intel_crtc->cursor_size = ~0;
13850
13851         intel_crtc->wm.cxsr_allowed = true;
13852
13853         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13854                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13855         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13856         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13857
13858         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13859
13860         intel_color_init(&intel_crtc->base);
13861
13862         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13863         return;
13864
13865 fail:
13866         if (primary)
13867                 drm_plane_cleanup(primary);
13868         if (cursor)
13869                 drm_plane_cleanup(cursor);
13870         kfree(crtc_state);
13871         kfree(intel_crtc);
13872 }
13873
13874 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13875 {
13876         struct drm_encoder *encoder = connector->base.encoder;
13877         struct drm_device *dev = connector->base.dev;
13878
13879         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13880
13881         if (!encoder || WARN_ON(!encoder->crtc))
13882                 return INVALID_PIPE;
13883
13884         return to_intel_crtc(encoder->crtc)->pipe;
13885 }
13886
13887 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13888                                 struct drm_file *file)
13889 {
13890         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13891         struct drm_crtc *drmmode_crtc;
13892         struct intel_crtc *crtc;
13893
13894         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13895
13896         if (!drmmode_crtc) {
13897                 DRM_ERROR("no such CRTC id\n");
13898                 return -ENOENT;
13899         }
13900
13901         crtc = to_intel_crtc(drmmode_crtc);
13902         pipe_from_crtc_id->pipe = crtc->pipe;
13903
13904         return 0;
13905 }
13906
13907 static int intel_encoder_clones(struct intel_encoder *encoder)
13908 {
13909         struct drm_device *dev = encoder->base.dev;
13910         struct intel_encoder *source_encoder;
13911         int index_mask = 0;
13912         int entry = 0;
13913
13914         for_each_intel_encoder(dev, source_encoder) {
13915                 if (encoders_cloneable(encoder, source_encoder))
13916                         index_mask |= (1 << entry);
13917
13918                 entry++;
13919         }
13920
13921         return index_mask;
13922 }
13923
13924 static bool has_edp_a(struct drm_device *dev)
13925 {
13926         struct drm_i915_private *dev_priv = dev->dev_private;
13927
13928         if (!IS_MOBILE(dev))
13929                 return false;
13930
13931         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13932                 return false;
13933
13934         if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13935                 return false;
13936
13937         return true;
13938 }
13939
13940 static bool intel_crt_present(struct drm_device *dev)
13941 {
13942         struct drm_i915_private *dev_priv = dev->dev_private;
13943
13944         if (INTEL_INFO(dev)->gen >= 9)
13945                 return false;
13946
13947         if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13948                 return false;
13949
13950         if (IS_CHERRYVIEW(dev))
13951                 return false;
13952
13953         if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
13954                 return false;
13955
13956         /* DDI E can't be used if DDI A requires 4 lanes */
13957         if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
13958                 return false;
13959
13960         if (!dev_priv->vbt.int_crt_support)
13961                 return false;
13962
13963         return true;
13964 }
13965
13966 static void intel_setup_outputs(struct drm_device *dev)
13967 {
13968         struct drm_i915_private *dev_priv = dev->dev_private;
13969         struct intel_encoder *encoder;
13970         bool dpd_is_edp = false;
13971
13972         intel_lvds_init(dev);
13973
13974         if (intel_crt_present(dev))
13975                 intel_crt_init(dev);
13976
13977         if (IS_BROXTON(dev)) {
13978                 /*
13979                  * FIXME: Broxton doesn't support port detection via the
13980                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13981                  * detect the ports.
13982                  */
13983                 intel_ddi_init(dev, PORT_A);
13984                 intel_ddi_init(dev, PORT_B);
13985                 intel_ddi_init(dev, PORT_C);
13986
13987                 intel_dsi_init(dev);
13988         } else if (HAS_DDI(dev)) {
13989                 int found;
13990
13991                 /*
13992                  * Haswell uses DDI functions to detect digital outputs.
13993                  * On SKL pre-D0 the strap isn't connected, so we assume
13994                  * it's there.
13995                  */
13996                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13997                 /* WaIgnoreDDIAStrap: skl */
13998                 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
13999                         intel_ddi_init(dev, PORT_A);
14000
14001                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14002                  * register */
14003                 found = I915_READ(SFUSE_STRAP);
14004
14005                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14006                         intel_ddi_init(dev, PORT_B);
14007                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14008                         intel_ddi_init(dev, PORT_C);
14009                 if (found & SFUSE_STRAP_DDID_DETECTED)
14010                         intel_ddi_init(dev, PORT_D);
14011                 /*
14012                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14013                  */
14014                 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14015                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14016                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14017                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14018                         intel_ddi_init(dev, PORT_E);
14019
14020         } else if (HAS_PCH_SPLIT(dev)) {
14021                 int found;
14022                 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14023
14024                 if (has_edp_a(dev))
14025                         intel_dp_init(dev, DP_A, PORT_A);
14026
14027                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14028                         /* PCH SDVOB multiplex with HDMIB */
14029                         found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14030                         if (!found)
14031                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14032                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14033                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
14034                 }
14035
14036                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14037                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14038
14039                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14040                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14041
14042                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14043                         intel_dp_init(dev, PCH_DP_C, PORT_C);
14044
14045                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14046                         intel_dp_init(dev, PCH_DP_D, PORT_D);
14047         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14048                 /*
14049                  * The DP_DETECTED bit is the latched state of the DDC
14050                  * SDA pin at boot. However since eDP doesn't require DDC
14051                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14052                  * eDP ports may have been muxed to an alternate function.
14053                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14054                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14055                  * detect eDP ports.
14056                  */
14057                 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14058                     !intel_dp_is_edp(dev, PORT_B))
14059                         intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14060                 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14061                     intel_dp_is_edp(dev, PORT_B))
14062                         intel_dp_init(dev, VLV_DP_B, PORT_B);
14063
14064                 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14065                     !intel_dp_is_edp(dev, PORT_C))
14066                         intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14067                 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14068                     intel_dp_is_edp(dev, PORT_C))
14069                         intel_dp_init(dev, VLV_DP_C, PORT_C);
14070
14071                 if (IS_CHERRYVIEW(dev)) {
14072                         /* eDP not supported on port D, so don't check VBT */
14073                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14074                                 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14075                         if (I915_READ(CHV_DP_D) & DP_DETECTED)
14076                                 intel_dp_init(dev, CHV_DP_D, PORT_D);
14077                 }
14078
14079                 intel_dsi_init(dev);
14080         } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14081                 bool found = false;
14082
14083                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14084                         DRM_DEBUG_KMS("probing SDVOB\n");
14085                         found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14086                         if (!found && IS_G4X(dev)) {
14087                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14088                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14089                         }
14090
14091                         if (!found && IS_G4X(dev))
14092                                 intel_dp_init(dev, DP_B, PORT_B);
14093                 }
14094
14095                 /* Before G4X SDVOC doesn't have its own detect register */
14096
14097                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14098                         DRM_DEBUG_KMS("probing SDVOC\n");
14099                         found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14100                 }
14101
14102                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14103
14104                         if (IS_G4X(dev)) {
14105                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14106                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14107                         }
14108                         if (IS_G4X(dev))
14109                                 intel_dp_init(dev, DP_C, PORT_C);
14110                 }
14111
14112                 if (IS_G4X(dev) &&
14113                     (I915_READ(DP_D) & DP_DETECTED))
14114                         intel_dp_init(dev, DP_D, PORT_D);
14115         } else if (IS_GEN2(dev))
14116                 intel_dvo_init(dev);
14117
14118         if (SUPPORTS_TV(dev))
14119                 intel_tv_init(dev);
14120
14121         intel_psr_init(dev);
14122
14123         for_each_intel_encoder(dev, encoder) {
14124                 encoder->base.possible_crtcs = encoder->crtc_mask;
14125                 encoder->base.possible_clones =
14126                         intel_encoder_clones(encoder);
14127         }
14128
14129         intel_init_pch_refclk(dev);
14130
14131         drm_helper_move_panel_connectors_to_head(dev);
14132 }
14133
14134 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14135 {
14136         struct drm_device *dev = fb->dev;
14137         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14138
14139         drm_framebuffer_cleanup(fb);
14140         mutex_lock(&dev->struct_mutex);
14141         WARN_ON(!intel_fb->obj->framebuffer_references--);
14142         drm_gem_object_unreference(&intel_fb->obj->base);
14143         mutex_unlock(&dev->struct_mutex);
14144         kfree(intel_fb);
14145 }
14146
14147 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14148                                                 struct drm_file *file,
14149                                                 unsigned int *handle)
14150 {
14151         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14152         struct drm_i915_gem_object *obj = intel_fb->obj;
14153
14154         if (obj->userptr.mm) {
14155                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14156                 return -EINVAL;
14157         }
14158
14159         return drm_gem_handle_create(file, &obj->base, handle);
14160 }
14161
14162 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14163                                         struct drm_file *file,
14164                                         unsigned flags, unsigned color,
14165                                         struct drm_clip_rect *clips,
14166                                         unsigned num_clips)
14167 {
14168         struct drm_device *dev = fb->dev;
14169         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14170         struct drm_i915_gem_object *obj = intel_fb->obj;
14171
14172         mutex_lock(&dev->struct_mutex);
14173         intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14174         mutex_unlock(&dev->struct_mutex);
14175
14176         return 0;
14177 }
14178
14179 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14180         .destroy = intel_user_framebuffer_destroy,
14181         .create_handle = intel_user_framebuffer_create_handle,
14182         .dirty = intel_user_framebuffer_dirty,
14183 };
14184
14185 static
14186 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14187                          uint32_t pixel_format)
14188 {
14189         u32 gen = INTEL_INFO(dev)->gen;
14190
14191         if (gen >= 9) {
14192                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14193
14194                 /* "The stride in bytes must not exceed the of the size of 8K
14195                  *  pixels and 32K bytes."
14196                  */
14197                 return min(8192 * cpp, 32768);
14198         } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14199                 return 32*1024;
14200         } else if (gen >= 4) {
14201                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14202                         return 16*1024;
14203                 else
14204                         return 32*1024;
14205         } else if (gen >= 3) {
14206                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14207                         return 8*1024;
14208                 else
14209                         return 16*1024;
14210         } else {
14211                 /* XXX DSPC is limited to 4k tiled */
14212                 return 8*1024;
14213         }
14214 }
14215
14216 static int intel_framebuffer_init(struct drm_device *dev,
14217                                   struct intel_framebuffer *intel_fb,
14218                                   struct drm_mode_fb_cmd2 *mode_cmd,
14219                                   struct drm_i915_gem_object *obj)
14220 {
14221         struct drm_i915_private *dev_priv = to_i915(dev);
14222         unsigned int aligned_height;
14223         int ret;
14224         u32 pitch_limit, stride_alignment;
14225
14226         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14227
14228         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14229                 /* Enforce that fb modifier and tiling mode match, but only for
14230                  * X-tiled. This is needed for FBC. */
14231                 if (!!(obj->tiling_mode == I915_TILING_X) !=
14232                     !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14233                         DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14234                         return -EINVAL;
14235                 }
14236         } else {
14237                 if (obj->tiling_mode == I915_TILING_X)
14238                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14239                 else if (obj->tiling_mode == I915_TILING_Y) {
14240                         DRM_DEBUG("No Y tiling for legacy addfb\n");
14241                         return -EINVAL;
14242                 }
14243         }
14244
14245         /* Passed in modifier sanity checking. */
14246         switch (mode_cmd->modifier[0]) {
14247         case I915_FORMAT_MOD_Y_TILED:
14248         case I915_FORMAT_MOD_Yf_TILED:
14249                 if (INTEL_INFO(dev)->gen < 9) {
14250                         DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14251                                   mode_cmd->modifier[0]);
14252                         return -EINVAL;
14253                 }
14254         case DRM_FORMAT_MOD_NONE:
14255         case I915_FORMAT_MOD_X_TILED:
14256                 break;
14257         default:
14258                 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14259                           mode_cmd->modifier[0]);
14260                 return -EINVAL;
14261         }
14262
14263         stride_alignment = intel_fb_stride_alignment(dev_priv,
14264                                                      mode_cmd->modifier[0],
14265                                                      mode_cmd->pixel_format);
14266         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14267                 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14268                           mode_cmd->pitches[0], stride_alignment);
14269                 return -EINVAL;
14270         }
14271
14272         pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14273                                            mode_cmd->pixel_format);
14274         if (mode_cmd->pitches[0] > pitch_limit) {
14275                 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14276                           mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14277                           "tiled" : "linear",
14278                           mode_cmd->pitches[0], pitch_limit);
14279                 return -EINVAL;
14280         }
14281
14282         if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14283             mode_cmd->pitches[0] != obj->stride) {
14284                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14285                           mode_cmd->pitches[0], obj->stride);
14286                 return -EINVAL;
14287         }
14288
14289         /* Reject formats not supported by any plane early. */
14290         switch (mode_cmd->pixel_format) {
14291         case DRM_FORMAT_C8:
14292         case DRM_FORMAT_RGB565:
14293         case DRM_FORMAT_XRGB8888:
14294         case DRM_FORMAT_ARGB8888:
14295                 break;
14296         case DRM_FORMAT_XRGB1555:
14297                 if (INTEL_INFO(dev)->gen > 3) {
14298                         DRM_DEBUG("unsupported pixel format: %s\n",
14299                                   drm_get_format_name(mode_cmd->pixel_format));
14300                         return -EINVAL;
14301                 }
14302                 break;
14303         case DRM_FORMAT_ABGR8888:
14304                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14305                     INTEL_INFO(dev)->gen < 9) {
14306                         DRM_DEBUG("unsupported pixel format: %s\n",
14307                                   drm_get_format_name(mode_cmd->pixel_format));
14308                         return -EINVAL;
14309                 }
14310                 break;
14311         case DRM_FORMAT_XBGR8888:
14312         case DRM_FORMAT_XRGB2101010:
14313         case DRM_FORMAT_XBGR2101010:
14314                 if (INTEL_INFO(dev)->gen < 4) {
14315                         DRM_DEBUG("unsupported pixel format: %s\n",
14316                                   drm_get_format_name(mode_cmd->pixel_format));
14317                         return -EINVAL;
14318                 }
14319                 break;
14320         case DRM_FORMAT_ABGR2101010:
14321                 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14322                         DRM_DEBUG("unsupported pixel format: %s\n",
14323                                   drm_get_format_name(mode_cmd->pixel_format));
14324                         return -EINVAL;
14325                 }
14326                 break;
14327         case DRM_FORMAT_YUYV:
14328         case DRM_FORMAT_UYVY:
14329         case DRM_FORMAT_YVYU:
14330         case DRM_FORMAT_VYUY:
14331                 if (INTEL_INFO(dev)->gen < 5) {
14332                         DRM_DEBUG("unsupported pixel format: %s\n",
14333                                   drm_get_format_name(mode_cmd->pixel_format));
14334                         return -EINVAL;
14335                 }
14336                 break;
14337         default:
14338                 DRM_DEBUG("unsupported pixel format: %s\n",
14339                           drm_get_format_name(mode_cmd->pixel_format));
14340                 return -EINVAL;
14341         }
14342
14343         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14344         if (mode_cmd->offsets[0] != 0)
14345                 return -EINVAL;
14346
14347         aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14348                                                mode_cmd->pixel_format,
14349                                                mode_cmd->modifier[0]);
14350         /* FIXME drm helper for size checks (especially planar formats)? */
14351         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14352                 return -EINVAL;
14353
14354         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14355         intel_fb->obj = obj;
14356
14357         intel_fill_fb_info(dev_priv, &intel_fb->base);
14358
14359         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14360         if (ret) {
14361                 DRM_ERROR("framebuffer init failed %d\n", ret);
14362                 return ret;
14363         }
14364
14365         intel_fb->obj->framebuffer_references++;
14366
14367         return 0;
14368 }
14369
14370 static struct drm_framebuffer *
14371 intel_user_framebuffer_create(struct drm_device *dev,
14372                               struct drm_file *filp,
14373                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14374 {
14375         struct drm_framebuffer *fb;
14376         struct drm_i915_gem_object *obj;
14377         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14378
14379         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14380                                                 mode_cmd.handles[0]));
14381         if (&obj->base == NULL)
14382                 return ERR_PTR(-ENOENT);
14383
14384         fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14385         if (IS_ERR(fb))
14386                 drm_gem_object_unreference_unlocked(&obj->base);
14387
14388         return fb;
14389 }
14390
14391 #ifndef CONFIG_DRM_FBDEV_EMULATION
14392 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14393 {
14394 }
14395 #endif
14396
14397 static const struct drm_mode_config_funcs intel_mode_funcs = {
14398         .fb_create = intel_user_framebuffer_create,
14399         .output_poll_changed = intel_fbdev_output_poll_changed,
14400         .atomic_check = intel_atomic_check,
14401         .atomic_commit = intel_atomic_commit,
14402         .atomic_state_alloc = intel_atomic_state_alloc,
14403         .atomic_state_clear = intel_atomic_state_clear,
14404 };
14405
14406 /**
14407  * intel_init_display_hooks - initialize the display modesetting hooks
14408  * @dev_priv: device private
14409  */
14410 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14411 {
14412         if (INTEL_INFO(dev_priv)->gen >= 9) {
14413                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14414                 dev_priv->display.get_initial_plane_config =
14415                         skylake_get_initial_plane_config;
14416                 dev_priv->display.crtc_compute_clock =
14417                         haswell_crtc_compute_clock;
14418                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14419                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14420         } else if (HAS_DDI(dev_priv)) {
14421                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14422                 dev_priv->display.get_initial_plane_config =
14423                         ironlake_get_initial_plane_config;
14424                 dev_priv->display.crtc_compute_clock =
14425                         haswell_crtc_compute_clock;
14426                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14427                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14428         } else if (HAS_PCH_SPLIT(dev_priv)) {
14429                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14430                 dev_priv->display.get_initial_plane_config =
14431                         ironlake_get_initial_plane_config;
14432                 dev_priv->display.crtc_compute_clock =
14433                         ironlake_crtc_compute_clock;
14434                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14435                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14436         } else if (IS_CHERRYVIEW(dev_priv)) {
14437                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14438                 dev_priv->display.get_initial_plane_config =
14439                         i9xx_get_initial_plane_config;
14440                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14441                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14442                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14443         } else if (IS_VALLEYVIEW(dev_priv)) {
14444                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14445                 dev_priv->display.get_initial_plane_config =
14446                         i9xx_get_initial_plane_config;
14447                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14448                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14449                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14450         } else if (IS_G4X(dev_priv)) {
14451                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14452                 dev_priv->display.get_initial_plane_config =
14453                         i9xx_get_initial_plane_config;
14454                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14455                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14456                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14457         } else if (IS_PINEVIEW(dev_priv)) {
14458                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14459                 dev_priv->display.get_initial_plane_config =
14460                         i9xx_get_initial_plane_config;
14461                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14462                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14463                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14464         } else if (!IS_GEN2(dev_priv)) {
14465                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14466                 dev_priv->display.get_initial_plane_config =
14467                         i9xx_get_initial_plane_config;
14468                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14469                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14470                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14471         } else {
14472                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14473                 dev_priv->display.get_initial_plane_config =
14474                         i9xx_get_initial_plane_config;
14475                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14476                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14477                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14478         }
14479
14480         /* Returns the core display clock speed */
14481         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14482                 dev_priv->display.get_display_clock_speed =
14483                         skylake_get_display_clock_speed;
14484         else if (IS_BROXTON(dev_priv))
14485                 dev_priv->display.get_display_clock_speed =
14486                         broxton_get_display_clock_speed;
14487         else if (IS_BROADWELL(dev_priv))
14488                 dev_priv->display.get_display_clock_speed =
14489                         broadwell_get_display_clock_speed;
14490         else if (IS_HASWELL(dev_priv))
14491                 dev_priv->display.get_display_clock_speed =
14492                         haswell_get_display_clock_speed;
14493         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14494                 dev_priv->display.get_display_clock_speed =
14495                         valleyview_get_display_clock_speed;
14496         else if (IS_GEN5(dev_priv))
14497                 dev_priv->display.get_display_clock_speed =
14498                         ilk_get_display_clock_speed;
14499         else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14500                  IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14501                 dev_priv->display.get_display_clock_speed =
14502                         i945_get_display_clock_speed;
14503         else if (IS_GM45(dev_priv))
14504                 dev_priv->display.get_display_clock_speed =
14505                         gm45_get_display_clock_speed;
14506         else if (IS_CRESTLINE(dev_priv))
14507                 dev_priv->display.get_display_clock_speed =
14508                         i965gm_get_display_clock_speed;
14509         else if (IS_PINEVIEW(dev_priv))
14510                 dev_priv->display.get_display_clock_speed =
14511                         pnv_get_display_clock_speed;
14512         else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
14513                 dev_priv->display.get_display_clock_speed =
14514                         g33_get_display_clock_speed;
14515         else if (IS_I915G(dev_priv))
14516                 dev_priv->display.get_display_clock_speed =
14517                         i915_get_display_clock_speed;
14518         else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
14519                 dev_priv->display.get_display_clock_speed =
14520                         i9xx_misc_get_display_clock_speed;
14521         else if (IS_I915GM(dev_priv))
14522                 dev_priv->display.get_display_clock_speed =
14523                         i915gm_get_display_clock_speed;
14524         else if (IS_I865G(dev_priv))
14525                 dev_priv->display.get_display_clock_speed =
14526                         i865_get_display_clock_speed;
14527         else if (IS_I85X(dev_priv))
14528                 dev_priv->display.get_display_clock_speed =
14529                         i85x_get_display_clock_speed;
14530         else { /* 830 */
14531                 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
14532                 dev_priv->display.get_display_clock_speed =
14533                         i830_get_display_clock_speed;
14534         }
14535
14536         if (IS_GEN5(dev_priv)) {
14537                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14538         } else if (IS_GEN6(dev_priv)) {
14539                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14540         } else if (IS_IVYBRIDGE(dev_priv)) {
14541                 /* FIXME: detect B0+ stepping and use auto training */
14542                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14543         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14544                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14545         }
14546
14547         if (IS_BROADWELL(dev_priv)) {
14548                 dev_priv->display.modeset_commit_cdclk =
14549                         broadwell_modeset_commit_cdclk;
14550                 dev_priv->display.modeset_calc_cdclk =
14551                         broadwell_modeset_calc_cdclk;
14552         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14553                 dev_priv->display.modeset_commit_cdclk =
14554                         valleyview_modeset_commit_cdclk;
14555                 dev_priv->display.modeset_calc_cdclk =
14556                         valleyview_modeset_calc_cdclk;
14557         } else if (IS_BROXTON(dev_priv)) {
14558                 dev_priv->display.modeset_commit_cdclk =
14559                         broxton_modeset_commit_cdclk;
14560                 dev_priv->display.modeset_calc_cdclk =
14561                         broxton_modeset_calc_cdclk;
14562         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
14563                 dev_priv->display.modeset_commit_cdclk =
14564                         skl_modeset_commit_cdclk;
14565                 dev_priv->display.modeset_calc_cdclk =
14566                         skl_modeset_calc_cdclk;
14567         }
14568 }
14569
14570 /*
14571  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14572  * resume, or other times.  This quirk makes sure that's the case for
14573  * affected systems.
14574  */
14575 static void quirk_pipea_force(struct drm_device *dev)
14576 {
14577         struct drm_i915_private *dev_priv = dev->dev_private;
14578
14579         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14580         DRM_INFO("applying pipe a force quirk\n");
14581 }
14582
14583 static void quirk_pipeb_force(struct drm_device *dev)
14584 {
14585         struct drm_i915_private *dev_priv = dev->dev_private;
14586
14587         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14588         DRM_INFO("applying pipe b force quirk\n");
14589 }
14590
14591 /*
14592  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14593  */
14594 static void quirk_ssc_force_disable(struct drm_device *dev)
14595 {
14596         struct drm_i915_private *dev_priv = dev->dev_private;
14597         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14598         DRM_INFO("applying lvds SSC disable quirk\n");
14599 }
14600
14601 /*
14602  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14603  * brightness value
14604  */
14605 static void quirk_invert_brightness(struct drm_device *dev)
14606 {
14607         struct drm_i915_private *dev_priv = dev->dev_private;
14608         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14609         DRM_INFO("applying inverted panel brightness quirk\n");
14610 }
14611
14612 /* Some VBT's incorrectly indicate no backlight is present */
14613 static void quirk_backlight_present(struct drm_device *dev)
14614 {
14615         struct drm_i915_private *dev_priv = dev->dev_private;
14616         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14617         DRM_INFO("applying backlight present quirk\n");
14618 }
14619
14620 struct intel_quirk {
14621         int device;
14622         int subsystem_vendor;
14623         int subsystem_device;
14624         void (*hook)(struct drm_device *dev);
14625 };
14626
14627 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14628 struct intel_dmi_quirk {
14629         void (*hook)(struct drm_device *dev);
14630         const struct dmi_system_id (*dmi_id_list)[];
14631 };
14632
14633 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14634 {
14635         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14636         return 1;
14637 }
14638
14639 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14640         {
14641                 .dmi_id_list = &(const struct dmi_system_id[]) {
14642                         {
14643                                 .callback = intel_dmi_reverse_brightness,
14644                                 .ident = "NCR Corporation",
14645                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14646                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14647                                 },
14648                         },
14649                         { }  /* terminating entry */
14650                 },
14651                 .hook = quirk_invert_brightness,
14652         },
14653 };
14654
14655 static struct intel_quirk intel_quirks[] = {
14656         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14657         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14658
14659         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14660         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14661
14662         /* 830 needs to leave pipe A & dpll A up */
14663         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14664
14665         /* 830 needs to leave pipe B & dpll B up */
14666         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14667
14668         /* Lenovo U160 cannot use SSC on LVDS */
14669         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14670
14671         /* Sony Vaio Y cannot use SSC on LVDS */
14672         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14673
14674         /* Acer Aspire 5734Z must invert backlight brightness */
14675         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14676
14677         /* Acer/eMachines G725 */
14678         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14679
14680         /* Acer/eMachines e725 */
14681         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14682
14683         /* Acer/Packard Bell NCL20 */
14684         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14685
14686         /* Acer Aspire 4736Z */
14687         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14688
14689         /* Acer Aspire 5336 */
14690         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14691
14692         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14693         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14694
14695         /* Acer C720 Chromebook (Core i3 4005U) */
14696         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14697
14698         /* Apple Macbook 2,1 (Core 2 T7400) */
14699         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14700
14701         /* Apple Macbook 4,1 */
14702         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14703
14704         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14705         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14706
14707         /* HP Chromebook 14 (Celeron 2955U) */
14708         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14709
14710         /* Dell Chromebook 11 */
14711         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14712
14713         /* Dell Chromebook 11 (2015 version) */
14714         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14715 };
14716
14717 static void intel_init_quirks(struct drm_device *dev)
14718 {
14719         struct pci_dev *d = dev->pdev;
14720         int i;
14721
14722         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14723                 struct intel_quirk *q = &intel_quirks[i];
14724
14725                 if (d->device == q->device &&
14726                     (d->subsystem_vendor == q->subsystem_vendor ||
14727                      q->subsystem_vendor == PCI_ANY_ID) &&
14728                     (d->subsystem_device == q->subsystem_device ||
14729                      q->subsystem_device == PCI_ANY_ID))
14730                         q->hook(dev);
14731         }
14732         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14733                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14734                         intel_dmi_quirks[i].hook(dev);
14735         }
14736 }
14737
14738 /* Disable the VGA plane that we never use */
14739 static void i915_disable_vga(struct drm_device *dev)
14740 {
14741         struct drm_i915_private *dev_priv = dev->dev_private;
14742         u8 sr1;
14743         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
14744
14745         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14746         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14747         outb(SR01, VGA_SR_INDEX);
14748         sr1 = inb(VGA_SR_DATA);
14749         outb(sr1 | 1<<5, VGA_SR_DATA);
14750         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14751         udelay(300);
14752
14753         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14754         POSTING_READ(vga_reg);
14755 }
14756
14757 void intel_modeset_init_hw(struct drm_device *dev)
14758 {
14759         struct drm_i915_private *dev_priv = dev->dev_private;
14760
14761         intel_update_cdclk(dev);
14762
14763         dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
14764
14765         intel_init_clock_gating(dev);
14766         intel_enable_gt_powersave(dev_priv);
14767 }
14768
14769 /*
14770  * Calculate what we think the watermarks should be for the state we've read
14771  * out of the hardware and then immediately program those watermarks so that
14772  * we ensure the hardware settings match our internal state.
14773  *
14774  * We can calculate what we think WM's should be by creating a duplicate of the
14775  * current state (which was constructed during hardware readout) and running it
14776  * through the atomic check code to calculate new watermark values in the
14777  * state object.
14778  */
14779 static void sanitize_watermarks(struct drm_device *dev)
14780 {
14781         struct drm_i915_private *dev_priv = to_i915(dev);
14782         struct drm_atomic_state *state;
14783         struct drm_crtc *crtc;
14784         struct drm_crtc_state *cstate;
14785         struct drm_modeset_acquire_ctx ctx;
14786         int ret;
14787         int i;
14788
14789         /* Only supported on platforms that use atomic watermark design */
14790         if (!dev_priv->display.optimize_watermarks)
14791                 return;
14792
14793         /*
14794          * We need to hold connection_mutex before calling duplicate_state so
14795          * that the connector loop is protected.
14796          */
14797         drm_modeset_acquire_init(&ctx, 0);
14798 retry:
14799         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14800         if (ret == -EDEADLK) {
14801                 drm_modeset_backoff(&ctx);
14802                 goto retry;
14803         } else if (WARN_ON(ret)) {
14804                 goto fail;
14805         }
14806
14807         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14808         if (WARN_ON(IS_ERR(state)))
14809                 goto fail;
14810
14811         /*
14812          * Hardware readout is the only time we don't want to calculate
14813          * intermediate watermarks (since we don't trust the current
14814          * watermarks).
14815          */
14816         to_intel_atomic_state(state)->skip_intermediate_wm = true;
14817
14818         ret = intel_atomic_check(dev, state);
14819         if (ret) {
14820                 /*
14821                  * If we fail here, it means that the hardware appears to be
14822                  * programmed in a way that shouldn't be possible, given our
14823                  * understanding of watermark requirements.  This might mean a
14824                  * mistake in the hardware readout code or a mistake in the
14825                  * watermark calculations for a given platform.  Raise a WARN
14826                  * so that this is noticeable.
14827                  *
14828                  * If this actually happens, we'll have to just leave the
14829                  * BIOS-programmed watermarks untouched and hope for the best.
14830                  */
14831                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14832                 goto fail;
14833         }
14834
14835         /* Write calculated watermark values back */
14836         for_each_crtc_in_state(state, crtc, cstate, i) {
14837                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14838
14839                 cs->wm.need_postvbl_update = true;
14840                 dev_priv->display.optimize_watermarks(cs);
14841         }
14842
14843         drm_atomic_state_free(state);
14844 fail:
14845         drm_modeset_drop_locks(&ctx);
14846         drm_modeset_acquire_fini(&ctx);
14847 }
14848
14849 void intel_modeset_init(struct drm_device *dev)
14850 {
14851         struct drm_i915_private *dev_priv = to_i915(dev);
14852         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14853         int sprite, ret;
14854         enum pipe pipe;
14855         struct intel_crtc *crtc;
14856
14857         drm_mode_config_init(dev);
14858
14859         dev->mode_config.min_width = 0;
14860         dev->mode_config.min_height = 0;
14861
14862         dev->mode_config.preferred_depth = 24;
14863         dev->mode_config.prefer_shadow = 1;
14864
14865         dev->mode_config.allow_fb_modifiers = true;
14866
14867         dev->mode_config.funcs = &intel_mode_funcs;
14868
14869         intel_init_quirks(dev);
14870
14871         intel_init_pm(dev);
14872
14873         if (INTEL_INFO(dev)->num_pipes == 0)
14874                 return;
14875
14876         /*
14877          * There may be no VBT; and if the BIOS enabled SSC we can
14878          * just keep using it to avoid unnecessary flicker.  Whereas if the
14879          * BIOS isn't using it, don't assume it will work even if the VBT
14880          * indicates as much.
14881          */
14882         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14883                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14884                                             DREF_SSC1_ENABLE);
14885
14886                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14887                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14888                                      bios_lvds_use_ssc ? "en" : "dis",
14889                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14890                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14891                 }
14892         }
14893
14894         if (IS_GEN2(dev)) {
14895                 dev->mode_config.max_width = 2048;
14896                 dev->mode_config.max_height = 2048;
14897         } else if (IS_GEN3(dev)) {
14898                 dev->mode_config.max_width = 4096;
14899                 dev->mode_config.max_height = 4096;
14900         } else {
14901                 dev->mode_config.max_width = 8192;
14902                 dev->mode_config.max_height = 8192;
14903         }
14904
14905         if (IS_845G(dev) || IS_I865G(dev)) {
14906                 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14907                 dev->mode_config.cursor_height = 1023;
14908         } else if (IS_GEN2(dev)) {
14909                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14910                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14911         } else {
14912                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14913                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14914         }
14915
14916         dev->mode_config.fb_base = ggtt->mappable_base;
14917
14918         DRM_DEBUG_KMS("%d display pipe%s available.\n",
14919                       INTEL_INFO(dev)->num_pipes,
14920                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14921
14922         for_each_pipe(dev_priv, pipe) {
14923                 intel_crtc_init(dev, pipe);
14924                 for_each_sprite(dev_priv, pipe, sprite) {
14925                         ret = intel_plane_init(dev, pipe, sprite);
14926                         if (ret)
14927                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14928                                               pipe_name(pipe), sprite_name(pipe, sprite), ret);
14929                 }
14930         }
14931
14932         intel_update_czclk(dev_priv);
14933         intel_update_cdclk(dev);
14934
14935         intel_shared_dpll_init(dev);
14936
14937         if (dev_priv->max_cdclk_freq == 0)
14938                 intel_update_max_cdclk(dev);
14939
14940         /* Just disable it once at startup */
14941         i915_disable_vga(dev);
14942         intel_setup_outputs(dev);
14943
14944         drm_modeset_lock_all(dev);
14945         intel_modeset_setup_hw_state(dev);
14946         drm_modeset_unlock_all(dev);
14947
14948         for_each_intel_crtc(dev, crtc) {
14949                 struct intel_initial_plane_config plane_config = {};
14950
14951                 if (!crtc->active)
14952                         continue;
14953
14954                 /*
14955                  * Note that reserving the BIOS fb up front prevents us
14956                  * from stuffing other stolen allocations like the ring
14957                  * on top.  This prevents some ugliness at boot time, and
14958                  * can even allow for smooth boot transitions if the BIOS
14959                  * fb is large enough for the active pipe configuration.
14960                  */
14961                 dev_priv->display.get_initial_plane_config(crtc,
14962                                                            &plane_config);
14963
14964                 /*
14965                  * If the fb is shared between multiple heads, we'll
14966                  * just get the first one.
14967                  */
14968                 intel_find_initial_plane_obj(crtc, &plane_config);
14969         }
14970
14971         /*
14972          * Make sure hardware watermarks really match the state we read out.
14973          * Note that we need to do this after reconstructing the BIOS fb's
14974          * since the watermark calculation done here will use pstate->fb.
14975          */
14976         sanitize_watermarks(dev);
14977 }
14978
14979 static void intel_enable_pipe_a(struct drm_device *dev)
14980 {
14981         struct intel_connector *connector;
14982         struct drm_connector *crt = NULL;
14983         struct intel_load_detect_pipe load_detect_temp;
14984         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14985
14986         /* We can't just switch on the pipe A, we need to set things up with a
14987          * proper mode and output configuration. As a gross hack, enable pipe A
14988          * by enabling the load detect pipe once. */
14989         for_each_intel_connector(dev, connector) {
14990                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14991                         crt = &connector->base;
14992                         break;
14993                 }
14994         }
14995
14996         if (!crt)
14997                 return;
14998
14999         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15000                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15001 }
15002
15003 static bool
15004 intel_check_plane_mapping(struct intel_crtc *crtc)
15005 {
15006         struct drm_device *dev = crtc->base.dev;
15007         struct drm_i915_private *dev_priv = dev->dev_private;
15008         u32 val;
15009
15010         if (INTEL_INFO(dev)->num_pipes == 1)
15011                 return true;
15012
15013         val = I915_READ(DSPCNTR(!crtc->plane));
15014
15015         if ((val & DISPLAY_PLANE_ENABLE) &&
15016             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15017                 return false;
15018
15019         return true;
15020 }
15021
15022 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15023 {
15024         struct drm_device *dev = crtc->base.dev;
15025         struct intel_encoder *encoder;
15026
15027         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15028                 return true;
15029
15030         return false;
15031 }
15032
15033 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15034 {
15035         struct drm_device *dev = encoder->base.dev;
15036         struct intel_connector *connector;
15037
15038         for_each_connector_on_encoder(dev, &encoder->base, connector)
15039                 return true;
15040
15041         return false;
15042 }
15043
15044 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15045 {
15046         struct drm_device *dev = crtc->base.dev;
15047         struct drm_i915_private *dev_priv = dev->dev_private;
15048         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15049
15050         /* Clear any frame start delays used for debugging left by the BIOS */
15051         if (!transcoder_is_dsi(cpu_transcoder)) {
15052                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15053
15054                 I915_WRITE(reg,
15055                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15056         }
15057
15058         /* restore vblank interrupts to correct state */
15059         drm_crtc_vblank_reset(&crtc->base);
15060         if (crtc->active) {
15061                 struct intel_plane *plane;
15062
15063                 drm_crtc_vblank_on(&crtc->base);
15064
15065                 /* Disable everything but the primary plane */
15066                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15067                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15068                                 continue;
15069
15070                         plane->disable_plane(&plane->base, &crtc->base);
15071                 }
15072         }
15073
15074         /* We need to sanitize the plane -> pipe mapping first because this will
15075          * disable the crtc (and hence change the state) if it is wrong. Note
15076          * that gen4+ has a fixed plane -> pipe mapping.  */
15077         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15078                 bool plane;
15079
15080                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15081                               crtc->base.base.id);
15082
15083                 /* Pipe has the wrong plane attached and the plane is active.
15084                  * Temporarily change the plane mapping and disable everything
15085                  * ...  */
15086                 plane = crtc->plane;
15087                 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15088                 crtc->plane = !plane;
15089                 intel_crtc_disable_noatomic(&crtc->base);
15090                 crtc->plane = plane;
15091         }
15092
15093         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15094             crtc->pipe == PIPE_A && !crtc->active) {
15095                 /* BIOS forgot to enable pipe A, this mostly happens after
15096                  * resume. Force-enable the pipe to fix this, the update_dpms
15097                  * call below we restore the pipe to the right state, but leave
15098                  * the required bits on. */
15099                 intel_enable_pipe_a(dev);
15100         }
15101
15102         /* Adjust the state of the output pipe according to whether we
15103          * have active connectors/encoders. */
15104         if (crtc->active && !intel_crtc_has_encoders(crtc))
15105                 intel_crtc_disable_noatomic(&crtc->base);
15106
15107         if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15108                 /*
15109                  * We start out with underrun reporting disabled to avoid races.
15110                  * For correct bookkeeping mark this on active crtcs.
15111                  *
15112                  * Also on gmch platforms we dont have any hardware bits to
15113                  * disable the underrun reporting. Which means we need to start
15114                  * out with underrun reporting disabled also on inactive pipes,
15115                  * since otherwise we'll complain about the garbage we read when
15116                  * e.g. coming up after runtime pm.
15117                  *
15118                  * No protection against concurrent access is required - at
15119                  * worst a fifo underrun happens which also sets this to false.
15120                  */
15121                 crtc->cpu_fifo_underrun_disabled = true;
15122                 crtc->pch_fifo_underrun_disabled = true;
15123         }
15124 }
15125
15126 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15127 {
15128         struct intel_connector *connector;
15129         struct drm_device *dev = encoder->base.dev;
15130
15131         /* We need to check both for a crtc link (meaning that the
15132          * encoder is active and trying to read from a pipe) and the
15133          * pipe itself being active. */
15134         bool has_active_crtc = encoder->base.crtc &&
15135                 to_intel_crtc(encoder->base.crtc)->active;
15136
15137         if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15138                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15139                               encoder->base.base.id,
15140                               encoder->base.name);
15141
15142                 /* Connector is active, but has no active pipe. This is
15143                  * fallout from our resume register restoring. Disable
15144                  * the encoder manually again. */
15145                 if (encoder->base.crtc) {
15146                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15147                                       encoder->base.base.id,
15148                                       encoder->base.name);
15149                         encoder->disable(encoder);
15150                         if (encoder->post_disable)
15151                                 encoder->post_disable(encoder);
15152                 }
15153                 encoder->base.crtc = NULL;
15154
15155                 /* Inconsistent output/port/pipe state happens presumably due to
15156                  * a bug in one of the get_hw_state functions. Or someplace else
15157                  * in our code, like the register restore mess on resume. Clamp
15158                  * things to off as a safer default. */
15159                 for_each_intel_connector(dev, connector) {
15160                         if (connector->encoder != encoder)
15161                                 continue;
15162                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15163                         connector->base.encoder = NULL;
15164                 }
15165         }
15166         /* Enabled encoders without active connectors will be fixed in
15167          * the crtc fixup. */
15168 }
15169
15170 void i915_redisable_vga_power_on(struct drm_device *dev)
15171 {
15172         struct drm_i915_private *dev_priv = dev->dev_private;
15173         i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15174
15175         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15176                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15177                 i915_disable_vga(dev);
15178         }
15179 }
15180
15181 void i915_redisable_vga(struct drm_device *dev)
15182 {
15183         struct drm_i915_private *dev_priv = dev->dev_private;
15184
15185         /* This function can be called both from intel_modeset_setup_hw_state or
15186          * at a very early point in our resume sequence, where the power well
15187          * structures are not yet restored. Since this function is at a very
15188          * paranoid "someone might have enabled VGA while we were not looking"
15189          * level, just check if the power well is enabled instead of trying to
15190          * follow the "don't touch the power well if we don't need it" policy
15191          * the rest of the driver uses. */
15192         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15193                 return;
15194
15195         i915_redisable_vga_power_on(dev);
15196
15197         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15198 }
15199
15200 static bool primary_get_hw_state(struct intel_plane *plane)
15201 {
15202         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15203
15204         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15205 }
15206
15207 /* FIXME read out full plane state for all planes */
15208 static void readout_plane_state(struct intel_crtc *crtc)
15209 {
15210         struct drm_plane *primary = crtc->base.primary;
15211         struct intel_plane_state *plane_state =
15212                 to_intel_plane_state(primary->state);
15213
15214         plane_state->visible = crtc->active &&
15215                 primary_get_hw_state(to_intel_plane(primary));
15216
15217         if (plane_state->visible)
15218                 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15219 }
15220
15221 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15222 {
15223         struct drm_i915_private *dev_priv = dev->dev_private;
15224         enum pipe pipe;
15225         struct intel_crtc *crtc;
15226         struct intel_encoder *encoder;
15227         struct intel_connector *connector;
15228         int i;
15229
15230         dev_priv->active_crtcs = 0;
15231
15232         for_each_intel_crtc(dev, crtc) {
15233                 struct intel_crtc_state *crtc_state = crtc->config;
15234                 int pixclk = 0;
15235
15236                 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15237                 memset(crtc_state, 0, sizeof(*crtc_state));
15238                 crtc_state->base.crtc = &crtc->base;
15239
15240                 crtc_state->base.active = crtc_state->base.enable =
15241                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15242
15243                 crtc->base.enabled = crtc_state->base.enable;
15244                 crtc->active = crtc_state->base.active;
15245
15246                 if (crtc_state->base.active) {
15247                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15248
15249                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
15250                                 pixclk = ilk_pipe_pixel_rate(crtc_state);
15251                         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15252                                 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15253                         else
15254                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15255
15256                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15257                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15258                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15259                 }
15260
15261                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15262
15263                 readout_plane_state(crtc);
15264
15265                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15266                               crtc->base.base.id,
15267                               crtc->active ? "enabled" : "disabled");
15268         }
15269
15270         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15271                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15272
15273                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15274                                                   &pll->config.hw_state);
15275                 pll->config.crtc_mask = 0;
15276                 for_each_intel_crtc(dev, crtc) {
15277                         if (crtc->active && crtc->config->shared_dpll == pll)
15278                                 pll->config.crtc_mask |= 1 << crtc->pipe;
15279                 }
15280                 pll->active_mask = pll->config.crtc_mask;
15281
15282                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15283                               pll->name, pll->config.crtc_mask, pll->on);
15284         }
15285
15286         for_each_intel_encoder(dev, encoder) {
15287                 pipe = 0;
15288
15289                 if (encoder->get_hw_state(encoder, &pipe)) {
15290                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15291                         encoder->base.crtc = &crtc->base;
15292                         encoder->get_config(encoder, crtc->config);
15293                 } else {
15294                         encoder->base.crtc = NULL;
15295                 }
15296
15297                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15298                               encoder->base.base.id,
15299                               encoder->base.name,
15300                               encoder->base.crtc ? "enabled" : "disabled",
15301                               pipe_name(pipe));
15302         }
15303
15304         for_each_intel_connector(dev, connector) {
15305                 if (connector->get_hw_state(connector)) {
15306                         connector->base.dpms = DRM_MODE_DPMS_ON;
15307
15308                         encoder = connector->encoder;
15309                         connector->base.encoder = &encoder->base;
15310
15311                         if (encoder->base.crtc &&
15312                             encoder->base.crtc->state->active) {
15313                                 /*
15314                                  * This has to be done during hardware readout
15315                                  * because anything calling .crtc_disable may
15316                                  * rely on the connector_mask being accurate.
15317                                  */
15318                                 encoder->base.crtc->state->connector_mask |=
15319                                         1 << drm_connector_index(&connector->base);
15320                                 encoder->base.crtc->state->encoder_mask |=
15321                                         1 << drm_encoder_index(&encoder->base);
15322                         }
15323
15324                 } else {
15325                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15326                         connector->base.encoder = NULL;
15327                 }
15328                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15329                               connector->base.base.id,
15330                               connector->base.name,
15331                               connector->base.encoder ? "enabled" : "disabled");
15332         }
15333
15334         for_each_intel_crtc(dev, crtc) {
15335                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15336
15337                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15338                 if (crtc->base.state->active) {
15339                         intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15340                         intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15341                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15342
15343                         /*
15344                          * The initial mode needs to be set in order to keep
15345                          * the atomic core happy. It wants a valid mode if the
15346                          * crtc's enabled, so we do the above call.
15347                          *
15348                          * At this point some state updated by the connectors
15349                          * in their ->detect() callback has not run yet, so
15350                          * no recalculation can be done yet.
15351                          *
15352                          * Even if we could do a recalculation and modeset
15353                          * right now it would cause a double modeset if
15354                          * fbdev or userspace chooses a different initial mode.
15355                          *
15356                          * If that happens, someone indicated they wanted a
15357                          * mode change, which means it's safe to do a full
15358                          * recalculation.
15359                          */
15360                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15361
15362                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15363                         update_scanline_offset(crtc);
15364                 }
15365
15366                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15367         }
15368 }
15369
15370 /* Scan out the current hw modeset state,
15371  * and sanitizes it to the current state
15372  */
15373 static void
15374 intel_modeset_setup_hw_state(struct drm_device *dev)
15375 {
15376         struct drm_i915_private *dev_priv = dev->dev_private;
15377         enum pipe pipe;
15378         struct intel_crtc *crtc;
15379         struct intel_encoder *encoder;
15380         int i;
15381
15382         intel_modeset_readout_hw_state(dev);
15383
15384         /* HW state is read out, now we need to sanitize this mess. */
15385         for_each_intel_encoder(dev, encoder) {
15386                 intel_sanitize_encoder(encoder);
15387         }
15388
15389         for_each_pipe(dev_priv, pipe) {
15390                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15391                 intel_sanitize_crtc(crtc);
15392                 intel_dump_pipe_config(crtc, crtc->config,
15393                                        "[setup_hw_state]");
15394         }
15395
15396         intel_modeset_update_connector_atomic_state(dev);
15397
15398         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15399                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15400
15401                 if (!pll->on || pll->active_mask)
15402                         continue;
15403
15404                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15405
15406                 pll->funcs.disable(dev_priv, pll);
15407                 pll->on = false;
15408         }
15409
15410         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15411                 vlv_wm_get_hw_state(dev);
15412         else if (IS_GEN9(dev))
15413                 skl_wm_get_hw_state(dev);
15414         else if (HAS_PCH_SPLIT(dev))
15415                 ilk_wm_get_hw_state(dev);
15416
15417         for_each_intel_crtc(dev, crtc) {
15418                 unsigned long put_domains;
15419
15420                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15421                 if (WARN_ON(put_domains))
15422                         modeset_put_power_domains(dev_priv, put_domains);
15423         }
15424         intel_display_set_init_power(dev_priv, false);
15425
15426         intel_fbc_init_pipe_state(dev_priv);
15427 }
15428
15429 void intel_display_resume(struct drm_device *dev)
15430 {
15431         struct drm_i915_private *dev_priv = to_i915(dev);
15432         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15433         struct drm_modeset_acquire_ctx ctx;
15434         int ret;
15435         bool setup = false;
15436
15437         dev_priv->modeset_restore_state = NULL;
15438
15439         /*
15440          * This is a cludge because with real atomic modeset mode_config.mutex
15441          * won't be taken. Unfortunately some probed state like
15442          * audio_codec_enable is still protected by mode_config.mutex, so lock
15443          * it here for now.
15444          */
15445         mutex_lock(&dev->mode_config.mutex);
15446         drm_modeset_acquire_init(&ctx, 0);
15447
15448 retry:
15449         ret = drm_modeset_lock_all_ctx(dev, &ctx);
15450
15451         if (ret == 0 && !setup) {
15452                 setup = true;
15453
15454                 intel_modeset_setup_hw_state(dev);
15455                 i915_redisable_vga(dev);
15456         }
15457
15458         if (ret == 0 && state) {
15459                 struct drm_crtc_state *crtc_state;
15460                 struct drm_crtc *crtc;
15461                 int i;
15462
15463                 state->acquire_ctx = &ctx;
15464
15465                 /* ignore any reset values/BIOS leftovers in the WM registers */
15466                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15467
15468                 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15469                         /*
15470                          * Force recalculation even if we restore
15471                          * current state. With fast modeset this may not result
15472                          * in a modeset when the state is compatible.
15473                          */
15474                         crtc_state->mode_changed = true;
15475                 }
15476
15477                 ret = drm_atomic_commit(state);
15478         }
15479
15480         if (ret == -EDEADLK) {
15481                 drm_modeset_backoff(&ctx);
15482                 goto retry;
15483         }
15484
15485         drm_modeset_drop_locks(&ctx);
15486         drm_modeset_acquire_fini(&ctx);
15487         mutex_unlock(&dev->mode_config.mutex);
15488
15489         if (ret) {
15490                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15491                 drm_atomic_state_free(state);
15492         }
15493 }
15494
15495 void intel_modeset_gem_init(struct drm_device *dev)
15496 {
15497         struct drm_i915_private *dev_priv = to_i915(dev);
15498         struct drm_crtc *c;
15499         struct drm_i915_gem_object *obj;
15500         int ret;
15501
15502         intel_init_gt_powersave(dev_priv);
15503
15504         intel_modeset_init_hw(dev);
15505
15506         intel_setup_overlay(dev_priv);
15507
15508         /*
15509          * Make sure any fbs we allocated at startup are properly
15510          * pinned & fenced.  When we do the allocation it's too early
15511          * for this.
15512          */
15513         for_each_crtc(dev, c) {
15514                 obj = intel_fb_obj(c->primary->fb);
15515                 if (obj == NULL)
15516                         continue;
15517
15518                 mutex_lock(&dev->struct_mutex);
15519                 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
15520                                                  c->primary->state->rotation);
15521                 mutex_unlock(&dev->struct_mutex);
15522                 if (ret) {
15523                         DRM_ERROR("failed to pin boot fb on pipe %d\n",
15524                                   to_intel_crtc(c)->pipe);
15525                         drm_framebuffer_unreference(c->primary->fb);
15526                         drm_framebuffer_unreference(c->primary->state->fb);
15527                         c->primary->fb = c->primary->state->fb = NULL;
15528                         c->primary->crtc = c->primary->state->crtc = NULL;
15529                         c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15530                 }
15531         }
15532
15533         intel_backlight_register(dev);
15534 }
15535
15536 void intel_connector_unregister(struct intel_connector *intel_connector)
15537 {
15538         struct drm_connector *connector = &intel_connector->base;
15539
15540         intel_panel_destroy_backlight(connector);
15541         drm_connector_unregister(connector);
15542 }
15543
15544 void intel_modeset_cleanup(struct drm_device *dev)
15545 {
15546         struct drm_i915_private *dev_priv = dev->dev_private;
15547         struct intel_connector *connector;
15548
15549         intel_disable_gt_powersave(dev_priv);
15550
15551         intel_backlight_unregister(dev);
15552
15553         /*
15554          * Interrupts and polling as the first thing to avoid creating havoc.
15555          * Too much stuff here (turning of connectors, ...) would
15556          * experience fancy races otherwise.
15557          */
15558         intel_irq_uninstall(dev_priv);
15559
15560         /*
15561          * Due to the hpd irq storm handling the hotplug work can re-arm the
15562          * poll handlers. Hence disable polling after hpd handling is shut down.
15563          */
15564         drm_kms_helper_poll_fini(dev);
15565
15566         intel_unregister_dsm_handler();
15567
15568         intel_fbc_global_disable(dev_priv);
15569
15570         /* flush any delayed tasks or pending work */
15571         flush_scheduled_work();
15572
15573         /* destroy the backlight and sysfs files before encoders/connectors */
15574         for_each_intel_connector(dev, connector)
15575                 connector->unregister(connector);
15576
15577         drm_mode_config_cleanup(dev);
15578
15579         intel_cleanup_overlay(dev_priv);
15580
15581         intel_cleanup_gt_powersave(dev_priv);
15582
15583         intel_teardown_gmbus(dev);
15584 }
15585
15586 /*
15587  * Return which encoder is currently attached for connector.
15588  */
15589 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15590 {
15591         return &intel_attached_encoder(connector)->base;
15592 }
15593
15594 void intel_connector_attach_encoder(struct intel_connector *connector,
15595                                     struct intel_encoder *encoder)
15596 {
15597         connector->encoder = encoder;
15598         drm_mode_connector_attach_encoder(&connector->base,
15599                                           &encoder->base);
15600 }
15601
15602 /*
15603  * set vga decode state - true == enable VGA decode
15604  */
15605 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15606 {
15607         struct drm_i915_private *dev_priv = dev->dev_private;
15608         unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15609         u16 gmch_ctrl;
15610
15611         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15612                 DRM_ERROR("failed to read control word\n");
15613                 return -EIO;
15614         }
15615
15616         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15617                 return 0;
15618
15619         if (state)
15620                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15621         else
15622                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15623
15624         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15625                 DRM_ERROR("failed to write control word\n");
15626                 return -EIO;
15627         }
15628
15629         return 0;
15630 }
15631
15632 struct intel_display_error_state {
15633
15634         u32 power_well_driver;
15635
15636         int num_transcoders;
15637
15638         struct intel_cursor_error_state {
15639                 u32 control;
15640                 u32 position;
15641                 u32 base;
15642                 u32 size;
15643         } cursor[I915_MAX_PIPES];
15644
15645         struct intel_pipe_error_state {
15646                 bool power_domain_on;
15647                 u32 source;
15648                 u32 stat;
15649         } pipe[I915_MAX_PIPES];
15650
15651         struct intel_plane_error_state {
15652                 u32 control;
15653                 u32 stride;
15654                 u32 size;
15655                 u32 pos;
15656                 u32 addr;
15657                 u32 surface;
15658                 u32 tile_offset;
15659         } plane[I915_MAX_PIPES];
15660
15661         struct intel_transcoder_error_state {
15662                 bool power_domain_on;
15663                 enum transcoder cpu_transcoder;
15664
15665                 u32 conf;
15666
15667                 u32 htotal;
15668                 u32 hblank;
15669                 u32 hsync;
15670                 u32 vtotal;
15671                 u32 vblank;
15672                 u32 vsync;
15673         } transcoder[4];
15674 };
15675
15676 struct intel_display_error_state *
15677 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15678 {
15679         struct intel_display_error_state *error;
15680         int transcoders[] = {
15681                 TRANSCODER_A,
15682                 TRANSCODER_B,
15683                 TRANSCODER_C,
15684                 TRANSCODER_EDP,
15685         };
15686         int i;
15687
15688         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15689                 return NULL;
15690
15691         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15692         if (error == NULL)
15693                 return NULL;
15694
15695         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15696                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15697
15698         for_each_pipe(dev_priv, i) {
15699                 error->pipe[i].power_domain_on =
15700                         __intel_display_power_is_enabled(dev_priv,
15701                                                          POWER_DOMAIN_PIPE(i));
15702                 if (!error->pipe[i].power_domain_on)
15703                         continue;
15704
15705                 error->cursor[i].control = I915_READ(CURCNTR(i));
15706                 error->cursor[i].position = I915_READ(CURPOS(i));
15707                 error->cursor[i].base = I915_READ(CURBASE(i));
15708
15709                 error->plane[i].control = I915_READ(DSPCNTR(i));
15710                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15711                 if (INTEL_GEN(dev_priv) <= 3) {
15712                         error->plane[i].size = I915_READ(DSPSIZE(i));
15713                         error->plane[i].pos = I915_READ(DSPPOS(i));
15714                 }
15715                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15716                         error->plane[i].addr = I915_READ(DSPADDR(i));
15717                 if (INTEL_GEN(dev_priv) >= 4) {
15718                         error->plane[i].surface = I915_READ(DSPSURF(i));
15719                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15720                 }
15721
15722                 error->pipe[i].source = I915_READ(PIPESRC(i));
15723
15724                 if (HAS_GMCH_DISPLAY(dev_priv))
15725                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15726         }
15727
15728         /* Note: this does not include DSI transcoders. */
15729         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15730         if (HAS_DDI(dev_priv))
15731                 error->num_transcoders++; /* Account for eDP. */
15732
15733         for (i = 0; i < error->num_transcoders; i++) {
15734                 enum transcoder cpu_transcoder = transcoders[i];
15735
15736                 error->transcoder[i].power_domain_on =
15737                         __intel_display_power_is_enabled(dev_priv,
15738                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15739                 if (!error->transcoder[i].power_domain_on)
15740                         continue;
15741
15742                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15743
15744                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15745                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15746                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15747                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15748                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15749                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15750                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15751         }
15752
15753         return error;
15754 }
15755
15756 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15757
15758 void
15759 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15760                                 struct drm_device *dev,
15761                                 struct intel_display_error_state *error)
15762 {
15763         struct drm_i915_private *dev_priv = dev->dev_private;
15764         int i;
15765
15766         if (!error)
15767                 return;
15768
15769         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15770         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15771                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15772                            error->power_well_driver);
15773         for_each_pipe(dev_priv, i) {
15774                 err_printf(m, "Pipe [%d]:\n", i);
15775                 err_printf(m, "  Power: %s\n",
15776                            onoff(error->pipe[i].power_domain_on));
15777                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15778                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15779
15780                 err_printf(m, "Plane [%d]:\n", i);
15781                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15782                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15783                 if (INTEL_INFO(dev)->gen <= 3) {
15784                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15785                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15786                 }
15787                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15788                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15789                 if (INTEL_INFO(dev)->gen >= 4) {
15790                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15791                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15792                 }
15793
15794                 err_printf(m, "Cursor [%d]:\n", i);
15795                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15796                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15797                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15798         }
15799
15800         for (i = 0; i < error->num_transcoders; i++) {
15801                 err_printf(m, "CPU transcoder: %s\n",
15802                            transcoder_name(error->transcoder[i].cpu_transcoder));
15803                 err_printf(m, "  Power: %s\n",
15804                            onoff(error->transcoder[i].power_domain_on));
15805                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15806                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15807                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15808                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15809                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15810                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15811                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15812         }
15813 }