drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  32  * them for both DP and FDI transports, allowing those ports to
  33  * automatically adapt to HDMI connections as well
  34  */
  35 static const u32 hsw_ddi_translations_dp[] = {
  36         0x00FFFFFF, 0x0006000E,
  37         0x00D75FFF, 0x0005000A,
  38         0x00C30FFF, 0x00040006,
  39         0x80AAAFFF, 0x000B0000,
  40         0x00FFFFFF, 0x0005000A,
  41         0x00D75FFF, 0x000C0004,
  42         0x80C30FFF, 0x000B0000,
  43         0x00FFFFFF, 0x00040006,
  44         0x80D75FFF, 0x000B0000,
  45 };
  46
  47 static const u32 hsw_ddi_translations_fdi[] = {
  48         0x00FFFFFF, 0x0007000E,
  49         0x00D75FFF, 0x000F000A,
  50         0x00C30FFF, 0x00060006,
  51         0x00AAAFFF, 0x001E0000,
  52         0x00FFFFFF, 0x000F000A,
  53         0x00D75FFF, 0x00160004,
  54         0x00C30FFF, 0x001E0000,
  55         0x00FFFFFF, 0x00060006,
  56         0x00D75FFF, 0x001E0000,
  57 };
  58
  59 static const u32 hsw_ddi_translations_hdmi[] = {
  60                                 /* Idx  NT mV diff      T mV diff       db  */
  61         0x00FFFFFF, 0x0006000E, /* 0:   400             400             0   */
  62         0x00E79FFF, 0x000E000C, /* 1:   400             500             2   */
  63         0x00D75FFF, 0x0005000A, /* 2:   400             600             3.5 */
  64         0x00FFFFFF, 0x0005000A, /* 3:   600             600             0   */
  65         0x00E79FFF, 0x001D0007, /* 4:   600             750             2   */
  66         0x00D75FFF, 0x000C0004, /* 5:   600             900             3.5 */
  67         0x00FFFFFF, 0x00040006, /* 6:   800             800             0   */
  68         0x80E79FFF, 0x00030002, /* 7:   800             1000            2   */
  69         0x00FFFFFF, 0x00140005, /* 8:   850             850             0   */
  70         0x00FFFFFF, 0x000C0004, /* 9:   900             900             0   */
  71         0x00FFFFFF, 0x001C0003, /* 10:  950             950             0   */
  72         0x80FFFFFF, 0x00030002, /* 11:  1000            1000            0   */
  73 };
  74
  75 static const u32 bdw_ddi_translations_edp[] = {
  76         0x00FFFFFF, 0x00000012,
  77         0x00EBAFFF, 0x00020011,
  78         0x00C71FFF, 0x0006000F,
  79         0x00AAAFFF, 0x000E000A,
  80         0x00FFFFFF, 0x00020011,
  81         0x00DB6FFF, 0x0005000F,
  82         0x00BEEFFF, 0x000A000C,
  83         0x00FFFFFF, 0x0005000F,
  84         0x00DB6FFF, 0x000A000C,
  85 };
  86
  87 static const u32 bdw_ddi_translations_dp[] = {
  88         0x00FFFFFF, 0x0007000E,
  89         0x00D75FFF, 0x000E000A,
  90         0x00BEFFFF, 0x00140006,
  91         0x80B2CFFF, 0x001B0002,
  92         0x00FFFFFF, 0x000E000A,
  93         0x00D75FFF, 0x00180004,
  94         0x80CB2FFF, 0x001B0002,
  95         0x00F7DFFF, 0x00180004,
  96         0x80D75FFF, 0x001B0002,
  97 };
  98
  99 static const u32 bdw_ddi_translations_fdi[] = {
 100         0x00FFFFFF, 0x0001000E,
 101         0x00D75FFF, 0x0004000A,
 102         0x00C30FFF, 0x00070006,
 103         0x00AAAFFF, 0x000C0000,
 104         0x00FFFFFF, 0x0004000A,
 105         0x00D75FFF, 0x00090004,
 106         0x00C30FFF, 0x000C0000,
 107         0x00FFFFFF, 0x00070006,
 108         0x00D75FFF, 0x000C0000,
 109 };
 110
 111 static const u32 bdw_ddi_translations_hdmi[] = {
 112                                 /* Idx  NT mV diff      T mV diff       db  */
 113         0x00FFFFFF, 0x0007000E, /* 0:   400             400             0   */
 114         0x00D75FFF, 0x000E000A, /* 1:   400             600             3.5 */
 115         0x00BEFFFF, 0x00140006, /* 2:   400             800             6   */
 116         0x00FFFFFF, 0x0009000D, /* 3:   450             450             0   */
 117         0x00FFFFFF, 0x000E000A, /* 4:   600             600             0   */
 118         0x00D7FFFF, 0x00140006, /* 5:   600             800             2.5 */
 119         0x80CB2FFF, 0x001B0002, /* 6:   600             1000            4.5 */
 120         0x00FFFFFF, 0x00140006, /* 7:   800             800             0   */
 121         0x80E79FFF, 0x001B0002, /* 8:   800             1000            2   */
 122         0x80FFFFFF, 0x001B0002, /* 9:   1000            1000            0   */
 123 };
 124
 125 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 126 {
 127         struct drm_encoder *encoder = &intel_encoder->base;
 128         int type = intel_encoder->type;
 129
 130         if (type == INTEL_OUTPUT_DP_MST) {
 131                 struct intel_digital_port *intel_dig_port = enc_to_mst(encoder)->primary;
 132                 return intel_dig_port->port;
 133         } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
 134             type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
 135                 struct intel_digital_port *intel_dig_port =
 136                         enc_to_dig_port(encoder);
 137                 return intel_dig_port->port;
 138
 139         } else if (type == INTEL_OUTPUT_ANALOG) {
 140                 return PORT_E;
 141
 142         } else {
 143                 DRM_ERROR("Invalid DDI encoder type %d\n", type);
 144                 BUG();
 145         }
 146 }
 147
 148 /*
 149  * Starting with Haswell, DDI port buffers must be programmed with correct
 150  * values in advance. The buffer values are different for FDI and DP modes,
 151  * but the HDMI/DVI fields are shared among those. So we program the DDI
 152  * in either FDI or DP modes only, as HDMI connections will work with both
 153  * of those
 154  */
 155 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 156 {
 157         struct drm_i915_private *dev_priv = dev->dev_private;
 158         u32 reg;
 159         int i, n_hdmi_entries, hdmi_800mV_0dB;
 160         int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 161         const u32 *ddi_translations_fdi;
 162         const u32 *ddi_translations_dp;
 163         const u32 *ddi_translations_edp;
 164         const u32 *ddi_translations_hdmi;
 165         const u32 *ddi_translations;
 166
 167         if (IS_BROADWELL(dev)) {
 168                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 169                 ddi_translations_dp = bdw_ddi_translations_dp;
 170                 ddi_translations_edp = bdw_ddi_translations_edp;
 171                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 172                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi) / 2;
 173                 hdmi_800mV_0dB = 7;
 174         } else if (IS_HASWELL(dev)) {
 175                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 176                 ddi_translations_dp = hsw_ddi_translations_dp;
 177                 ddi_translations_edp = hsw_ddi_translations_dp;
 178                 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
 179                 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi) / 2;
 180                 hdmi_800mV_0dB = 6;
 181         } else {
 182                 WARN(1, "ddi translation table missing\n");
 183                 ddi_translations_edp = bdw_ddi_translations_dp;
 184                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 185                 ddi_translations_dp = bdw_ddi_translations_dp;
 186                 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
 187                 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi) / 2;
 188                 hdmi_800mV_0dB = 7;
 189         }
 190
 191         switch (port) {
 192         case PORT_A:
 193                 ddi_translations = ddi_translations_edp;
 194                 break;
 195         case PORT_B:
 196         case PORT_C:
 197                 ddi_translations = ddi_translations_dp;
 198                 break;
 199         case PORT_D:
 200                 if (intel_dp_is_edp(dev, PORT_D))
 201                         ddi_translations = ddi_translations_edp;
 202                 else
 203                         ddi_translations = ddi_translations_dp;
 204                 break;
 205         case PORT_E:
 206                 ddi_translations = ddi_translations_fdi;
 207                 break;
 208         default:
 209                 BUG();
 210         }
 211
 212         for (i = 0, reg = DDI_BUF_TRANS(port);
 213              i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
 214                 I915_WRITE(reg, ddi_translations[i]);
 215                 reg += 4;
 216         }
 217
 218         /* Choose a good default if VBT is badly populated */
 219         if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
 220             hdmi_level >= n_hdmi_entries)
 221                 hdmi_level = hdmi_800mV_0dB;
 222
 223         /* Entry 9 is for HDMI: */
 224         for (i = 0; i < 2; i++) {
 225                 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level * 2 + i]);
 226                 reg += 4;
 227         }
 228 }
 229
 230 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
 231  * mode and port E for FDI.
 232  */
 233 void intel_prepare_ddi(struct drm_device *dev)
 234 {
 235         int port;
 236
 237         if (!HAS_DDI(dev))
 238                 return;
 239
 240         for (port = PORT_A; port <= PORT_E; port++)
 241                 intel_prepare_ddi_buffers(dev, port);
 242 }
 243
 244 static const long hsw_ddi_buf_ctl_values[] = {
 245         DDI_BUF_EMP_400MV_0DB_HSW,
 246         DDI_BUF_EMP_400MV_3_5DB_HSW,
 247         DDI_BUF_EMP_400MV_6DB_HSW,
 248         DDI_BUF_EMP_400MV_9_5DB_HSW,
 249         DDI_BUF_EMP_600MV_0DB_HSW,
 250         DDI_BUF_EMP_600MV_3_5DB_HSW,
 251         DDI_BUF_EMP_600MV_6DB_HSW,
 252         DDI_BUF_EMP_800MV_0DB_HSW,
 253         DDI_BUF_EMP_800MV_3_5DB_HSW
 254 };
 255
 256 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 257                                     enum port port)
 258 {
 259         uint32_t reg = DDI_BUF_CTL(port);
 260         int i;
 261
 262         for (i = 0; i < 8; i++) {
 263                 udelay(1);
 264                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 265                         return;
 266         }
 267         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 268 }
 269
 270 /* Starting with Haswell, different DDI ports can work in FDI mode for
 271  * connection to the PCH-located connectors. For this, it is necessary to train
 272  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 273  *
 274  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 275  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 276  * DDI A (which is used for eDP)
 277  */
 278
 279 void hsw_fdi_link_train(struct drm_crtc *crtc)
 280 {
 281         struct drm_device *dev = crtc->dev;
 282         struct drm_i915_private *dev_priv = dev->dev_private;
 283         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 284         u32 temp, i, rx_ctl_val;
 285
 286         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 287          * mode set "sequence for CRT port" document:
 288          * - TP1 to TP2 time with the default value
 289          * - FDI delay to 90h
 290          *
 291          * WaFDIAutoLinkSetTimingOverrride:hsw
 292          */
 293         I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
 294                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 295                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 296
 297         /* Enable the PCH Receiver FDI PLL */
 298         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 299                      FDI_RX_PLL_ENABLE |
 300                      FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
 301         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 302         POSTING_READ(_FDI_RXA_CTL);
 303         udelay(220);
 304
 305         /* Switch from Rawclk to PCDclk */
 306         rx_ctl_val |= FDI_PCDCLK;
 307         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 308
 309         /* Configure Port Clock Select */
 310         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel);
 311         WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL);
 312
 313         /* Start the training iterating through available voltages and emphasis,
 314          * testing each value twice. */
 315         for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
 316                 /* Configure DP_TP_CTL with auto-training */
 317                 I915_WRITE(DP_TP_CTL(PORT_E),
 318                                         DP_TP_CTL_FDI_AUTOTRAIN |
 319                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 320                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 321                                         DP_TP_CTL_ENABLE);
 322
 323                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 324                  * DDI E does not support port reversal, the functionality is
 325                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 326                  * port reversal bit */
 327                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 328                            DDI_BUF_CTL_ENABLE |
 329                            ((intel_crtc->config.fdi_lanes - 1) << 1) |
 330                            hsw_ddi_buf_ctl_values[i / 2]);
 331                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 332
 333                 udelay(600);
 334
 335                 /* Program PCH FDI Receiver TU */
 336                 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
 337
 338                 /* Enable PCH FDI Receiver with auto-training */
 339                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 340                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 341                 POSTING_READ(_FDI_RXA_CTL);
 342
 343                 /* Wait for FDI receiver lane calibration */
 344                 udelay(30);
 345
 346                 /* Unset FDI_RX_MISC pwrdn lanes */
 347                 temp = I915_READ(_FDI_RXA_MISC);
 348                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 349                 I915_WRITE(_FDI_RXA_MISC, temp);
 350                 POSTING_READ(_FDI_RXA_MISC);
 351
 352                 /* Wait for FDI auto training time */
 353                 udelay(5);
 354
 355                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 356                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 357                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 358
 359                         /* Enable normal pixel sending for FDI */
 360                         I915_WRITE(DP_TP_CTL(PORT_E),
 361                                    DP_TP_CTL_FDI_AUTOTRAIN |
 362                                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 363                                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 364                                    DP_TP_CTL_ENABLE);
 365
 366                         return;
 367                 }
 368
 369                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 370                 temp &= ~DDI_BUF_CTL_ENABLE;
 371                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 372                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 373
 374                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 375                 temp = I915_READ(DP_TP_CTL(PORT_E));
 376                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 377                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 378                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 379                 POSTING_READ(DP_TP_CTL(PORT_E));
 380
 381                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 382
 383                 rx_ctl_val &= ~FDI_RX_ENABLE;
 384                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 385                 POSTING_READ(_FDI_RXA_CTL);
 386
 387                 /* Reset FDI_RX_MISC pwrdn lanes */
 388                 temp = I915_READ(_FDI_RXA_MISC);
 389                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 390                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 391                 I915_WRITE(_FDI_RXA_MISC, temp);
 392                 POSTING_READ(_FDI_RXA_MISC);
 393         }
 394
 395         DRM_ERROR("FDI link training failed!\n");
 396 }
 397
 398 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
 399 {
 400         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 401         struct intel_digital_port *intel_dig_port =
 402                 enc_to_dig_port(&encoder->base);
 403
 404         intel_dp->DP = intel_dig_port->saved_port_bits |
 405                 DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
 406         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 407
 408 }
 409
 410 static struct intel_encoder *
 411 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 412 {
 413         struct drm_device *dev = crtc->dev;
 414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 415         struct intel_encoder *intel_encoder, *ret = NULL;
 416         int num_encoders = 0;
 417
 418         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 419                 ret = intel_encoder;
 420                 num_encoders++;
 421         }
 422
 423         if (num_encoders != 1)
 424                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 425                      pipe_name(intel_crtc->pipe));
 426
 427         BUG_ON(ret == NULL);
 428         return ret;
 429 }
 430
 431 #define LC_FREQ 2700
 432 #define LC_FREQ_2K (LC_FREQ * 2000)
 433
 434 #define P_MIN 2
 435 #define P_MAX 64
 436 #define P_INC 2
 437
 438 /* Constraints for PLL good behavior */
 439 #define REF_MIN 48
 440 #define REF_MAX 400
 441 #define VCO_MIN 2400
 442 #define VCO_MAX 4800
 443
 444 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
 445
 446 struct wrpll_rnp {
 447         unsigned p, n2, r2;
 448 };
 449
 450 static unsigned wrpll_get_budget_for_freq(int clock)
 451 {
 452         unsigned budget;
 453
 454         switch (clock) {
 455         case 25175000:
 456         case 25200000:
 457         case 27000000:
 458         case 27027000:
 459         case 37762500:
 460         case 37800000:
 461         case 40500000:
 462         case 40541000:
 463         case 54000000:
 464         case 54054000:
 465         case 59341000:
 466         case 59400000:
 467         case 72000000:
 468         case 74176000:
 469         case 74250000:
 470         case 81000000:
 471         case 81081000:
 472         case 89012000:
 473         case 89100000:
 474         case 108000000:
 475         case 108108000:
 476         case 111264000:
 477         case 111375000:
 478         case 148352000:
 479         case 148500000:
 480         case 162000000:
 481         case 162162000:
 482         case 222525000:
 483         case 222750000:
 484         case 296703000:
 485         case 297000000:
 486                 budget = 0;
 487                 break;
 488         case 233500000:
 489         case 245250000:
 490         case 247750000:
 491         case 253250000:
 492         case 298000000:
 493                 budget = 1500;
 494                 break;
 495         case 169128000:
 496         case 169500000:
 497         case 179500000:
 498         case 202000000:
 499                 budget = 2000;
 500                 break;
 501         case 256250000:
 502         case 262500000:
 503         case 270000000:
 504         case 272500000:
 505         case 273750000:
 506         case 280750000:
 507         case 281250000:
 508         case 286000000:
 509         case 291750000:
 510                 budget = 4000;
 511                 break;
 512         case 267250000:
 513         case 268500000:
 514                 budget = 5000;
 515                 break;
 516         default:
 517                 budget = 1000;
 518                 break;
 519         }
 520
 521         return budget;
 522 }
 523
 524 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 525                              unsigned r2, unsigned n2, unsigned p,
 526                              struct wrpll_rnp *best)
 527 {
 528         uint64_t a, b, c, d, diff, diff_best;
 529
 530         /* No best (r,n,p) yet */
 531         if (best->p == 0) {
 532                 best->p = p;
 533                 best->n2 = n2;
 534                 best->r2 = r2;
 535                 return;
 536         }
 537
 538         /*
 539          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 540          * freq2k.
 541          *
 542          * delta = 1e6 *
 543          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 544          *         freq2k;
 545          *
 546          * and we would like delta <= budget.
 547          *
 548          * If the discrepancy is above the PPM-based budget, always prefer to
 549          * improve upon the previous solution.  However, if you're within the
 550          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 551          */
 552         a = freq2k * budget * p * r2;
 553         b = freq2k * budget * best->p * best->r2;
 554         diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
 555         diff_best = ABS_DIFF((freq2k * best->p * best->r2),
 556                              (LC_FREQ_2K * best->n2));
 557         c = 1000000 * diff;
 558         d = 1000000 * diff_best;
 559
 560         if (a < c && b < d) {
 561                 /* If both are above the budget, pick the closer */
 562                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 563                         best->p = p;
 564                         best->n2 = n2;
 565                         best->r2 = r2;
 566                 }
 567         } else if (a >= c && b < d) {
 568                 /* If A is below the threshold but B is above it?  Update. */
 569                 best->p = p;
 570                 best->n2 = n2;
 571                 best->r2 = r2;
 572         } else if (a >= c && b >= d) {
 573                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 574                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 575                         best->p = p;
 576                         best->n2 = n2;
 577                         best->r2 = r2;
 578                 }
 579         }
 580         /* Otherwise a < c && b >= d, do nothing */
 581 }
 582
 583 static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
 584                                      int reg)
 585 {
 586         int refclk = LC_FREQ;
 587         int n, p, r;
 588         u32 wrpll;
 589
 590         wrpll = I915_READ(reg);
 591         switch (wrpll & WRPLL_PLL_REF_MASK) {
 592         case WRPLL_PLL_SSC:
 593         case WRPLL_PLL_NON_SSC:
 594                 /*
 595                  * We could calculate spread here, but our checking
 596                  * code only cares about 5% accuracy, and spread is a max of
 597                  * 0.5% downspread.
 598                  */
 599                 refclk = 135;
 600                 break;
 601         case WRPLL_PLL_LCPLL:
 602                 refclk = LC_FREQ;
 603                 break;
 604         default:
 605                 WARN(1, "bad wrpll refclk\n");
 606                 return 0;
 607         }
 608
 609         r = wrpll & WRPLL_DIVIDER_REF_MASK;
 610         p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 611         n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 612
 613         /* Convert to KHz, p & r have a fixed point portion */
 614         return (refclk * n * 100) / (p * r);
 615 }
 616
 617 static void hsw_ddi_clock_get(struct intel_encoder *encoder,
 618                               struct intel_crtc_config *pipe_config)
 619 {
 620         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 621         int link_clock = 0;
 622         u32 val, pll;
 623
 624         val = pipe_config->ddi_pll_sel;
 625         switch (val & PORT_CLK_SEL_MASK) {
 626         case PORT_CLK_SEL_LCPLL_810:
 627                 link_clock = 81000;
 628                 break;
 629         case PORT_CLK_SEL_LCPLL_1350:
 630                 link_clock = 135000;
 631                 break;
 632         case PORT_CLK_SEL_LCPLL_2700:
 633                 link_clock = 270000;
 634                 break;
 635         case PORT_CLK_SEL_WRPLL1:
 636                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
 637                 break;
 638         case PORT_CLK_SEL_WRPLL2:
 639                 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
 640                 break;
 641         case PORT_CLK_SEL_SPLL:
 642                 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
 643                 if (pll == SPLL_PLL_FREQ_810MHz)
 644                         link_clock = 81000;
 645                 else if (pll == SPLL_PLL_FREQ_1350MHz)
 646                         link_clock = 135000;
 647                 else if (pll == SPLL_PLL_FREQ_2700MHz)
 648                         link_clock = 270000;
 649                 else {
 650                         WARN(1, "bad spll freq\n");
 651                         return;
 652                 }
 653                 break;
 654         default:
 655                 WARN(1, "bad port clock sel\n");
 656                 return;
 657         }
 658
 659         pipe_config->port_clock = link_clock * 2;
 660
 661         if (pipe_config->has_pch_encoder)
 662                 pipe_config->adjusted_mode.crtc_clock =
 663                         intel_dotclock_calculate(pipe_config->port_clock,
 664                                                  &pipe_config->fdi_m_n);
 665         else if (pipe_config->has_dp_encoder)
 666                 pipe_config->adjusted_mode.crtc_clock =
 667                         intel_dotclock_calculate(pipe_config->port_clock,
 668                                                  &pipe_config->dp_m_n);
 669         else
 670                 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock;
 671 }
 672
 673 void intel_ddi_clock_get(struct intel_encoder *encoder,
 674                          struct intel_crtc_config *pipe_config)
 675 {
 676         hsw_ddi_clock_get(encoder, pipe_config);
 677 }
 678
 679 static void
 680 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 681                         unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
 682 {
 683         uint64_t freq2k;
 684         unsigned p, n2, r2;
 685         struct wrpll_rnp best = { 0, 0, 0 };
 686         unsigned budget;
 687
 688         freq2k = clock / 100;
 689
 690         budget = wrpll_get_budget_for_freq(clock);
 691
 692         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
 693          * and directly pass the LC PLL to it. */
 694         if (freq2k == 5400000) {
 695                 *n2_out = 2;
 696                 *p_out = 1;
 697                 *r2_out = 2;
 698                 return;
 699         }
 700
 701         /*
 702          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
 703          * the WR PLL.
 704          *
 705          * We want R so that REF_MIN <= Ref <= REF_MAX.
 706          * Injecting R2 = 2 * R gives:
 707          *   REF_MAX * r2 > LC_FREQ * 2 and
 708          *   REF_MIN * r2 < LC_FREQ * 2
 709          *
 710          * Which means the desired boundaries for r2 are:
 711          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
 712          *
 713          */
 714         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
 715              r2 <= LC_FREQ * 2 / REF_MIN;
 716              r2++) {
 717
 718                 /*
 719                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
 720                  *
 721                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
 722                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
 723                  *   VCO_MAX * r2 > n2 * LC_FREQ and
 724                  *   VCO_MIN * r2 < n2 * LC_FREQ)
 725                  *
 726                  * Which means the desired boundaries for n2 are:
 727                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
 728                  */
 729                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
 730                      n2 <= VCO_MAX * r2 / LC_FREQ;
 731                      n2++) {
 732
 733                         for (p = P_MIN; p <= P_MAX; p += P_INC)
 734                                 wrpll_update_rnp(freq2k, budget,
 735                                                  r2, n2, p, &best);
 736                 }
 737         }
 738
 739         *n2_out = best.n2;
 740         *p_out = best.p;
 741         *r2_out = best.r2;
 742 }
 743
 744 static bool
 745 hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 746                    struct intel_encoder *intel_encoder,
 747                    int clock)
 748 {
 749         if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
 750                 struct intel_shared_dpll *pll;
 751                 uint32_t val;
 752                 unsigned p, n2, r2;
 753
 754                 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 755
 756                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
 757                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 758                       WRPLL_DIVIDER_POST(p);
 759
 760                 intel_crtc->config.dpll_hw_state.wrpll = val;
 761
 762                 pll = intel_get_shared_dpll(intel_crtc);
 763                 if (pll == NULL) {
 764                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
 765                                          pipe_name(intel_crtc->pipe));
 766                         return false;
 767                 }
 768
 769                 intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
 770         }
 771
 772         return true;
 773 }
 774
 775
 776 /*
 777  * Tries to find a *shared* PLL for the CRTC and store it in
 778  * intel_crtc->ddi_pll_sel.
 779  *
 780  * For private DPLLs, compute_config() should do the selection for us. This
 781  * function should be folded into compute_config() eventually.
 782  */
 783 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
 784 {
 785         struct drm_crtc *crtc = &intel_crtc->base;
 786         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 787         int clock = intel_crtc->config.port_clock;
 788
 789         intel_put_shared_dpll(intel_crtc);
 790
 791         return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock);
 792 }
 793
 794 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
 795 {
 796         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 797         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 798         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 799         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 800         int type = intel_encoder->type;
 801         uint32_t temp;
 802
 803         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
 804                 temp = TRANS_MSA_SYNC_CLK;
 805                 switch (intel_crtc->config.pipe_bpp) {
 806                 case 18:
 807                         temp |= TRANS_MSA_6_BPC;
 808                         break;
 809                 case 24:
 810                         temp |= TRANS_MSA_8_BPC;
 811                         break;
 812                 case 30:
 813                         temp |= TRANS_MSA_10_BPC;
 814                         break;
 815                 case 36:
 816                         temp |= TRANS_MSA_12_BPC;
 817                         break;
 818                 default:
 819                         BUG();
 820                 }
 821                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 822         }
 823 }
 824
 825 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
 826 {
 827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 828         struct drm_device *dev = crtc->dev;
 829         struct drm_i915_private *dev_priv = dev->dev_private;
 830         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 831         uint32_t temp;
 832         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
 833         if (state == true)
 834                 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
 835         else
 836                 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
 837         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 838 }
 839
 840 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 841 {
 842         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 843         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 844         struct drm_encoder *encoder = &intel_encoder->base;
 845         struct drm_device *dev = crtc->dev;
 846         struct drm_i915_private *dev_priv = dev->dev_private;
 847         enum pipe pipe = intel_crtc->pipe;
 848         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 849         enum port port = intel_ddi_get_encoder_port(intel_encoder);
 850         int type = intel_encoder->type;
 851         uint32_t temp;
 852
 853         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 854         temp = TRANS_DDI_FUNC_ENABLE;
 855         temp |= TRANS_DDI_SELECT_PORT(port);
 856
 857         switch (intel_crtc->config.pipe_bpp) {
 858         case 18:
 859                 temp |= TRANS_DDI_BPC_6;
 860                 break;
 861         case 24:
 862                 temp |= TRANS_DDI_BPC_8;
 863                 break;
 864         case 30:
 865                 temp |= TRANS_DDI_BPC_10;
 866                 break;
 867         case 36:
 868                 temp |= TRANS_DDI_BPC_12;
 869                 break;
 870         default:
 871                 BUG();
 872         }
 873
 874         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 875                 temp |= TRANS_DDI_PVSYNC;
 876         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 877                 temp |= TRANS_DDI_PHSYNC;
 878
 879         if (cpu_transcoder == TRANSCODER_EDP) {
 880                 switch (pipe) {
 881                 case PIPE_A:
 882                         /* On Haswell, can only use the always-on power well for
 883                          * eDP when not using the panel fitter, and when not
 884                          * using motion blur mitigation (which we don't
 885                          * support). */
 886                         if (IS_HASWELL(dev) &&
 887                             (intel_crtc->config.pch_pfit.enabled ||
 888                              intel_crtc->config.pch_pfit.force_thru))
 889                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 890                         else
 891                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 892                         break;
 893                 case PIPE_B:
 894                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 895                         break;
 896                 case PIPE_C:
 897                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 898                         break;
 899                 default:
 900                         BUG();
 901                         break;
 902                 }
 903         }
 904
 905         if (type == INTEL_OUTPUT_HDMI) {
 906                 if (intel_crtc->config.has_hdmi_sink)
 907                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
 908                 else
 909                         temp |= TRANS_DDI_MODE_SELECT_DVI;
 910
 911         } else if (type == INTEL_OUTPUT_ANALOG) {
 912                 temp |= TRANS_DDI_MODE_SELECT_FDI;
 913                 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
 914
 915         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
 916                    type == INTEL_OUTPUT_EDP) {
 917                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 918
 919                 if (intel_dp->is_mst) {
 920                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 921                 } else
 922                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 923
 924                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
 925         } else if (type == INTEL_OUTPUT_DP_MST) {
 926                 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
 927
 928                 if (intel_dp->is_mst) {
 929                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 930                 } else
 931                         temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 932
 933                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
 934         } else {
 935                 WARN(1, "Invalid encoder type %d for pipe %c\n",
 936                      intel_encoder->type, pipe_name(pipe));
 937         }
 938
 939         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 940 }
 941
 942 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 943                                        enum transcoder cpu_transcoder)
 944 {
 945         uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 946         uint32_t val = I915_READ(reg);
 947
 948         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
 949         val |= TRANS_DDI_PORT_NONE;
 950         I915_WRITE(reg, val);
 951 }
 952
 953 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 954 {
 955         struct drm_device *dev = intel_connector->base.dev;
 956         struct drm_i915_private *dev_priv = dev->dev_private;
 957         struct intel_encoder *intel_encoder = intel_connector->encoder;
 958         int type = intel_connector->base.connector_type;
 959         enum port port = intel_ddi_get_encoder_port(intel_encoder);
 960         enum pipe pipe = 0;
 961         enum transcoder cpu_transcoder;
 962         enum intel_display_power_domain power_domain;
 963         uint32_t tmp;
 964
 965         power_domain = intel_display_port_power_domain(intel_encoder);
 966         if (!intel_display_power_enabled(dev_priv, power_domain))
 967                 return false;
 968
 969         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
 970                 return false;
 971
 972         if (port == PORT_A)
 973                 cpu_transcoder = TRANSCODER_EDP;
 974         else
 975                 cpu_transcoder = (enum transcoder) pipe;
 976
 977         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
 978
 979         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
 980         case TRANS_DDI_MODE_SELECT_HDMI:
 981         case TRANS_DDI_MODE_SELECT_DVI:
 982                 return (type == DRM_MODE_CONNECTOR_HDMIA);
 983
 984         case TRANS_DDI_MODE_SELECT_DP_SST:
 985                 if (type == DRM_MODE_CONNECTOR_eDP)
 986                         return true;
 987                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
 988         case TRANS_DDI_MODE_SELECT_DP_MST:
 989                 /* if the transcoder is in MST state then
 990                  * connector isn't connected */
 991                 return false;
 992
 993         case TRANS_DDI_MODE_SELECT_FDI:
 994                 return (type == DRM_MODE_CONNECTOR_VGA);
 995
 996         default:
 997                 return false;
 998         }
 999 }
1000
1001 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1002                             enum pipe *pipe)
1003 {
1004         struct drm_device *dev = encoder->base.dev;
1005         struct drm_i915_private *dev_priv = dev->dev_private;
1006         enum port port = intel_ddi_get_encoder_port(encoder);
1007         enum intel_display_power_domain power_domain;
1008         u32 tmp;
1009         int i;
1010
1011         power_domain = intel_display_port_power_domain(encoder);
1012         if (!intel_display_power_enabled(dev_priv, power_domain))
1013                 return false;
1014
1015         tmp = I915_READ(DDI_BUF_CTL(port));
1016
1017         if (!(tmp & DDI_BUF_CTL_ENABLE))
1018                 return false;
1019
1020         if (port == PORT_A) {
1021                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1022
1023                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1024                 case TRANS_DDI_EDP_INPUT_A_ON:
1025                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1026                         *pipe = PIPE_A;
1027                         break;
1028                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1029                         *pipe = PIPE_B;
1030                         break;
1031                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1032                         *pipe = PIPE_C;
1033                         break;
1034                 }
1035
1036                 return true;
1037         } else {
1038                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1039                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1040
1041                         if ((tmp & TRANS_DDI_PORT_MASK)
1042                             == TRANS_DDI_SELECT_PORT(port)) {
1043                                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1044                                         return false;
1045
1046                                 *pipe = i;
1047                                 return true;
1048                         }
1049                 }
1050         }
1051
1052         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1053
1054         return false;
1055 }
1056
1057 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1058 {
1059         struct drm_crtc *crtc = &intel_crtc->base;
1060         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1061         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1062         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1063         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1064
1065         if (cpu_transcoder != TRANSCODER_EDP)
1066                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1067                            TRANS_CLK_SEL_PORT(port));
1068 }
1069
1070 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1071 {
1072         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1073         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1074
1075         if (cpu_transcoder != TRANSCODER_EDP)
1076                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1077                            TRANS_CLK_SEL_DISABLED);
1078 }
1079
1080 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1081 {
1082         struct drm_encoder *encoder = &intel_encoder->base;
1083         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1084         struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1085         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1086         int type = intel_encoder->type;
1087
1088         if (crtc->config.has_audio) {
1089                 DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n",
1090                                  pipe_name(crtc->pipe));
1091
1092                 /* write eld */
1093                 DRM_DEBUG_DRIVER("DDI audio: write eld information\n");
1094                 intel_write_eld(encoder, &crtc->config.adjusted_mode);
1095         }
1096
1097         if (type == INTEL_OUTPUT_EDP) {
1098                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1099                 intel_edp_panel_on(intel_dp);
1100         }
1101
1102         WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
1103         I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
1104
1105         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1106                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1107
1108                 intel_ddi_init_dp_buf_reg(intel_encoder);
1109
1110                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1111                 intel_dp_start_link_train(intel_dp);
1112                 intel_dp_complete_link_train(intel_dp);
1113                 if (port != PORT_A)
1114                         intel_dp_stop_link_train(intel_dp);
1115         } else if (type == INTEL_OUTPUT_HDMI) {
1116                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1117
1118                 intel_hdmi->set_infoframes(encoder,
1119                                            crtc->config.has_hdmi_sink,
1120                                            &crtc->config.adjusted_mode);
1121         }
1122 }
1123
1124 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1125 {
1126         struct drm_encoder *encoder = &intel_encoder->base;
1127         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1128         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1129         int type = intel_encoder->type;
1130         uint32_t val;
1131         bool wait = false;
1132
1133         val = I915_READ(DDI_BUF_CTL(port));
1134         if (val & DDI_BUF_CTL_ENABLE) {
1135                 val &= ~DDI_BUF_CTL_ENABLE;
1136                 I915_WRITE(DDI_BUF_CTL(port), val);
1137                 wait = true;
1138         }
1139
1140         val = I915_READ(DP_TP_CTL(port));
1141         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1142         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1143         I915_WRITE(DP_TP_CTL(port), val);
1144
1145         if (wait)
1146                 intel_wait_ddi_buf_idle(dev_priv, port);
1147
1148         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1149                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1150                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1151                 intel_edp_panel_vdd_on(intel_dp);
1152                 intel_edp_panel_off(intel_dp);
1153         }
1154
1155         I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1156 }
1157
1158 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1159 {
1160         struct drm_encoder *encoder = &intel_encoder->base;
1161         struct drm_crtc *crtc = encoder->crtc;
1162         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1163         int pipe = intel_crtc->pipe;
1164         struct drm_device *dev = encoder->dev;
1165         struct drm_i915_private *dev_priv = dev->dev_private;
1166         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1167         int type = intel_encoder->type;
1168         uint32_t tmp;
1169
1170         if (type == INTEL_OUTPUT_HDMI) {
1171                 struct intel_digital_port *intel_dig_port =
1172                         enc_to_dig_port(encoder);
1173
1174                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1175                  * are ignored so nothing special needs to be done besides
1176                  * enabling the port.
1177                  */
1178                 I915_WRITE(DDI_BUF_CTL(port),
1179                            intel_dig_port->saved_port_bits |
1180                            DDI_BUF_CTL_ENABLE);
1181         } else if (type == INTEL_OUTPUT_EDP) {
1182                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1183
1184                 if (port == PORT_A)
1185                         intel_dp_stop_link_train(intel_dp);
1186
1187                 intel_edp_backlight_on(intel_dp);
1188                 intel_edp_psr_enable(intel_dp);
1189         }
1190
1191         if (intel_crtc->config.has_audio) {
1192                 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1193                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1194                 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1195                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1196         }
1197 }
1198
1199 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1200 {
1201         struct drm_encoder *encoder = &intel_encoder->base;
1202         struct drm_crtc *crtc = encoder->crtc;
1203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1204         int pipe = intel_crtc->pipe;
1205         int type = intel_encoder->type;
1206         struct drm_device *dev = encoder->dev;
1207         struct drm_i915_private *dev_priv = dev->dev_private;
1208         uint32_t tmp;
1209
1210         /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this
1211          * register is part of the power well on Haswell. */
1212         if (intel_crtc->config.has_audio) {
1213                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1214                 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1215                          (pipe * 4));
1216                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1217                 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1218         }
1219
1220         if (type == INTEL_OUTPUT_EDP) {
1221                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1222
1223                 intel_edp_psr_disable(intel_dp);
1224                 intel_edp_backlight_off(intel_dp);
1225         }
1226 }
1227
1228 static int bdw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1229 {
1230         uint32_t lcpll = I915_READ(LCPLL_CTL);
1231         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1232
1233         if (lcpll & LCPLL_CD_SOURCE_FCLK)
1234                 return 800000;
1235         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1236                 return 450000;
1237         else if (freq == LCPLL_CLK_FREQ_450)
1238                 return 450000;
1239         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
1240                 return 540000;
1241         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1242                 return 337500;
1243         else
1244                 return 675000;
1245 }
1246
1247 static int hsw_get_cdclk_freq(struct drm_i915_private *dev_priv)
1248 {
1249         struct drm_device *dev = dev_priv->dev;
1250         uint32_t lcpll = I915_READ(LCPLL_CTL);
1251         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1252
1253         if (lcpll & LCPLL_CD_SOURCE_FCLK)
1254                 return 800000;
1255         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
1256                 return 450000;
1257         else if (freq == LCPLL_CLK_FREQ_450)
1258                 return 450000;
1259         else if (IS_ULT(dev))
1260                 return 337500;
1261         else
1262                 return 540000;
1263 }
1264
1265 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1266 {
1267         struct drm_device *dev = dev_priv->dev;
1268
1269         if (IS_BROADWELL(dev))
1270                 return bdw_get_cdclk_freq(dev_priv);
1271
1272         /* Haswell */
1273         return hsw_get_cdclk_freq(dev_priv);
1274 }
1275
1276 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
1277                                struct intel_shared_dpll *pll)
1278 {
1279         I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll);
1280         POSTING_READ(WRPLL_CTL(pll->id));
1281         udelay(20);
1282 }
1283
1284 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
1285                                 struct intel_shared_dpll *pll)
1286 {
1287         uint32_t val;
1288
1289         val = I915_READ(WRPLL_CTL(pll->id));
1290         I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
1291         POSTING_READ(WRPLL_CTL(pll->id));
1292 }
1293
1294 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1295                                      struct intel_shared_dpll *pll,
1296                                      struct intel_dpll_hw_state *hw_state)
1297 {
1298         uint32_t val;
1299
1300         if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
1301                 return false;
1302
1303         val = I915_READ(WRPLL_CTL(pll->id));
1304         hw_state->wrpll = val;
1305
1306         return val & WRPLL_PLL_ENABLE;
1307 }
1308
1309 static const char * const hsw_ddi_pll_names[] = {
1310         "WRPLL 1",
1311         "WRPLL 2",
1312 };
1313
1314 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
1315 {
1316         int i;
1317
1318         dev_priv->num_shared_dpll = 2;
1319
1320         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
1321                 dev_priv->shared_dplls[i].id = i;
1322                 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
1323                 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
1324                 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
1325                 dev_priv->shared_dplls[i].get_hw_state =
1326                         hsw_ddi_pll_get_hw_state;
1327         }
1328 }
1329
1330 void intel_ddi_pll_init(struct drm_device *dev)
1331 {
1332         struct drm_i915_private *dev_priv = dev->dev_private;
1333         uint32_t val = I915_READ(LCPLL_CTL);
1334
1335         hsw_shared_dplls_init(dev_priv);
1336
1337         /* The LCPLL register should be turned on by the BIOS. For now let's
1338          * just check its state and print errors in case something is wrong.
1339          * Don't even try to turn it on.
1340          */
1341
1342         DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1343                       intel_ddi_get_cdclk_freq(dev_priv));
1344
1345         if (val & LCPLL_CD_SOURCE_FCLK)
1346                 DRM_ERROR("CDCLK source is not LCPLL\n");
1347
1348         if (val & LCPLL_PLL_DISABLE)
1349                 DRM_ERROR("LCPLL is disabled\n");
1350 }
1351
1352 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1353 {
1354         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1355         struct intel_dp *intel_dp = &intel_dig_port->dp;
1356         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1357         enum port port = intel_dig_port->port;
1358         uint32_t val;
1359         bool wait = false;
1360
1361         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1362                 val = I915_READ(DDI_BUF_CTL(port));
1363                 if (val & DDI_BUF_CTL_ENABLE) {
1364                         val &= ~DDI_BUF_CTL_ENABLE;
1365                         I915_WRITE(DDI_BUF_CTL(port), val);
1366                         wait = true;
1367                 }
1368
1369                 val = I915_READ(DP_TP_CTL(port));
1370                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1371                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1372                 I915_WRITE(DP_TP_CTL(port), val);
1373                 POSTING_READ(DP_TP_CTL(port));
1374
1375                 if (wait)
1376                         intel_wait_ddi_buf_idle(dev_priv, port);
1377         }
1378
1379         val = DP_TP_CTL_ENABLE |
1380               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1381         if (intel_dp->is_mst)
1382                 val |= DP_TP_CTL_MODE_MST;
1383         else {
1384                 val |= DP_TP_CTL_MODE_SST;
1385                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1386                         val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1387         }
1388         I915_WRITE(DP_TP_CTL(port), val);
1389         POSTING_READ(DP_TP_CTL(port));
1390
1391         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1392         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1393         POSTING_READ(DDI_BUF_CTL(port));
1394
1395         udelay(600);
1396 }
1397
1398 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1399 {
1400         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1401         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1402         uint32_t val;
1403
1404         intel_ddi_post_disable(intel_encoder);
1405
1406         val = I915_READ(_FDI_RXA_CTL);
1407         val &= ~FDI_RX_ENABLE;
1408         I915_WRITE(_FDI_RXA_CTL, val);
1409
1410         val = I915_READ(_FDI_RXA_MISC);
1411         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1412         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1413         I915_WRITE(_FDI_RXA_MISC, val);
1414
1415         val = I915_READ(_FDI_RXA_CTL);
1416         val &= ~FDI_PCDCLK;
1417         I915_WRITE(_FDI_RXA_CTL, val);
1418
1419         val = I915_READ(_FDI_RXA_CTL);
1420         val &= ~FDI_RX_PLL_ENABLE;
1421         I915_WRITE(_FDI_RXA_CTL, val);
1422 }
1423
1424 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1425 {
1426         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base);
1427         int type = intel_dig_port->base.type;
1428
1429         if (type != INTEL_OUTPUT_DISPLAYPORT &&
1430             type != INTEL_OUTPUT_EDP &&
1431             type != INTEL_OUTPUT_UNKNOWN) {
1432                 return;
1433         }
1434
1435         intel_dp_hot_plug(intel_encoder);
1436 }
1437
1438 void intel_ddi_get_config(struct intel_encoder *encoder,
1439                           struct intel_crtc_config *pipe_config)
1440 {
1441         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1442         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1443         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1444         u32 temp, flags = 0;
1445
1446         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1447         if (temp & TRANS_DDI_PHSYNC)
1448                 flags |= DRM_MODE_FLAG_PHSYNC;
1449         else
1450                 flags |= DRM_MODE_FLAG_NHSYNC;
1451         if (temp & TRANS_DDI_PVSYNC)
1452                 flags |= DRM_MODE_FLAG_PVSYNC;
1453         else
1454                 flags |= DRM_MODE_FLAG_NVSYNC;
1455
1456         pipe_config->adjusted_mode.flags |= flags;
1457
1458         switch (temp & TRANS_DDI_BPC_MASK) {
1459         case TRANS_DDI_BPC_6:
1460                 pipe_config->pipe_bpp = 18;
1461                 break;
1462         case TRANS_DDI_BPC_8:
1463                 pipe_config->pipe_bpp = 24;
1464                 break;
1465         case TRANS_DDI_BPC_10:
1466                 pipe_config->pipe_bpp = 30;
1467                 break;
1468         case TRANS_DDI_BPC_12:
1469                 pipe_config->pipe_bpp = 36;
1470                 break;
1471         default:
1472                 break;
1473         }
1474
1475         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1476         case TRANS_DDI_MODE_SELECT_HDMI:
1477                 pipe_config->has_hdmi_sink = true;
1478         case TRANS_DDI_MODE_SELECT_DVI:
1479         case TRANS_DDI_MODE_SELECT_FDI:
1480                 break;
1481         case TRANS_DDI_MODE_SELECT_DP_SST:
1482         case TRANS_DDI_MODE_SELECT_DP_MST:
1483                 pipe_config->has_dp_encoder = true;
1484                 intel_dp_get_m_n(intel_crtc, pipe_config);
1485                 break;
1486         default:
1487                 break;
1488         }
1489
1490         if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
1491                 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1492                 if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4)))
1493                         pipe_config->has_audio = true;
1494         }
1495
1496         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1497             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1498                 /*
1499                  * This is a big fat ugly hack.
1500                  *
1501                  * Some machines in UEFI boot mode provide us a VBT that has 18
1502                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1503                  * unknown we fail to light up. Yet the same BIOS boots up with
1504                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1505                  * max, not what it tells us to use.
1506                  *
1507                  * Note: This will still be broken if the eDP panel is not lit
1508                  * up by the BIOS, and thus we can't get the mode at module
1509                  * load.
1510                  */
1511                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1512                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1513                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1514         }
1515
1516         hsw_ddi_clock_get(encoder, pipe_config);
1517 }
1518
1519 static void intel_ddi_destroy(struct drm_encoder *encoder)
1520 {
1521         /* HDMI has nothing special to destroy, so we can go with this. */
1522         intel_dp_encoder_destroy(encoder);
1523 }
1524
1525 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1526                                      struct intel_crtc_config *pipe_config)
1527 {
1528         int type = encoder->type;
1529         int port = intel_ddi_get_encoder_port(encoder);
1530
1531         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1532
1533         if (port == PORT_A)
1534                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1535
1536         if (type == INTEL_OUTPUT_HDMI)
1537                 return intel_hdmi_compute_config(encoder, pipe_config);
1538         else
1539                 return intel_dp_compute_config(encoder, pipe_config);
1540 }
1541
1542 static const struct drm_encoder_funcs intel_ddi_funcs = {
1543         .destroy = intel_ddi_destroy,
1544 };
1545
1546 static struct intel_connector *
1547 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1548 {
1549         struct intel_connector *connector;
1550         enum port port = intel_dig_port->port;
1551
1552         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1553         if (!connector)
1554                 return NULL;
1555
1556         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1557         if (!intel_dp_init_connector(intel_dig_port, connector)) {
1558                 kfree(connector);
1559                 return NULL;
1560         }
1561
1562         return connector;
1563 }
1564
1565 static struct intel_connector *
1566 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1567 {
1568         struct intel_connector *connector;
1569         enum port port = intel_dig_port->port;
1570
1571         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1572         if (!connector)
1573                 return NULL;
1574
1575         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1576         intel_hdmi_init_connector(intel_dig_port, connector);
1577
1578         return connector;
1579 }
1580
1581 void intel_ddi_init(struct drm_device *dev, enum port port)
1582 {
1583         struct drm_i915_private *dev_priv = dev->dev_private;
1584         struct intel_digital_port *intel_dig_port;
1585         struct intel_encoder *intel_encoder;
1586         struct drm_encoder *encoder;
1587         bool init_hdmi, init_dp;
1588
1589         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1590                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1591         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1592         if (!init_dp && !init_hdmi) {
1593                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
1594                               port_name(port));
1595                 init_hdmi = true;
1596                 init_dp = true;
1597         }
1598
1599         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1600         if (!intel_dig_port)
1601                 return;
1602
1603         intel_encoder = &intel_dig_port->base;
1604         encoder = &intel_encoder->base;
1605
1606         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1607                          DRM_MODE_ENCODER_TMDS);
1608
1609         intel_encoder->compute_config = intel_ddi_compute_config;
1610         intel_encoder->enable = intel_enable_ddi;
1611         intel_encoder->pre_enable = intel_ddi_pre_enable;
1612         intel_encoder->disable = intel_disable_ddi;
1613         intel_encoder->post_disable = intel_ddi_post_disable;
1614         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1615         intel_encoder->get_config = intel_ddi_get_config;
1616
1617         intel_dig_port->port = port;
1618         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1619                                           (DDI_BUF_PORT_REVERSAL |
1620                                            DDI_A_4_LANES);
1621
1622         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1623         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1624         intel_encoder->cloneable = 0;
1625         intel_encoder->hot_plug = intel_ddi_hot_plug;
1626
1627         if (init_dp) {
1628                 if (!intel_ddi_init_dp_connector(intel_dig_port))
1629                         goto err;
1630
1631                 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
1632                 dev_priv->hpd_irq_port[port] = intel_dig_port;
1633         }
1634
1635         /* In theory we don't need the encoder->type check, but leave it just in
1636          * case we have some really bad VBTs... */
1637         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
1638                 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
1639                         goto err;
1640         }
1641
1642         return;
1643
1644 err:
1645         drm_encoder_cleanup(encoder);
1646         kfree(intel_dig_port);
1647 }