drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 static const u32 hpd_ibx[] = {
  41         [HPD_CRT] = SDE_CRT_HOTPLUG,
  42         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  43         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  44         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  45         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  46 };
  47
  48 static const u32 hpd_cpt[] = {
  49         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  50         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  51         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  52         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  53         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  54 };
  55
  56 static const u32 hpd_mask_i915[] = {
  57         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  58         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  59         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  60         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  61         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  62         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  63 };
  64
  65 static const u32 hpd_status_g4x[] = {
  66         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  67         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  69         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  71         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  72 };
  73
  74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  75         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  76         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  77         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  78         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  80         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  81 };
  82
  83 /* For display hotplug interrupt */
  84 static void
  85 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  86 {
  87         assert_spin_locked(&dev_priv->irq_lock);
  88
  89         if (dev_priv->pc8.irqs_disabled) {
  90                 WARN(1, "IRQs disabled\n");
  91                 dev_priv->pc8.regsave.deimr &= ~mask;
  92                 return;
  93         }
  94
  95         if ((dev_priv->irq_mask & mask) != 0) {
  96                 dev_priv->irq_mask &= ~mask;
  97                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  98                 POSTING_READ(DEIMR);
  99         }
 100 }
 101
 102 static void
 103 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 104 {
 105         assert_spin_locked(&dev_priv->irq_lock);
 106
 107         if (dev_priv->pc8.irqs_disabled) {
 108                 WARN(1, "IRQs disabled\n");
 109                 dev_priv->pc8.regsave.deimr |= mask;
 110                 return;
 111         }
 112
 113         if ((dev_priv->irq_mask & mask) != mask) {
 114                 dev_priv->irq_mask |= mask;
 115                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 116                 POSTING_READ(DEIMR);
 117         }
 118 }
 119
 120 /**
 121  * ilk_update_gt_irq - update GTIMR
 122  * @dev_priv: driver private
 123  * @interrupt_mask: mask of interrupt bits to update
 124  * @enabled_irq_mask: mask of interrupt bits to enable
 125  */
 126 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 127                               uint32_t interrupt_mask,
 128                               uint32_t enabled_irq_mask)
 129 {
 130         assert_spin_locked(&dev_priv->irq_lock);
 131
 132         if (dev_priv->pc8.irqs_disabled) {
 133                 WARN(1, "IRQs disabled\n");
 134                 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
 135                 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
 136                                                 interrupt_mask);
 137                 return;
 138         }
 139
 140         dev_priv->gt_irq_mask &= ~interrupt_mask;
 141         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 142         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 143         POSTING_READ(GTIMR);
 144 }
 145
 146 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 147 {
 148         ilk_update_gt_irq(dev_priv, mask, mask);
 149 }
 150
 151 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 152 {
 153         ilk_update_gt_irq(dev_priv, mask, 0);
 154 }
 155
 156 /**
 157   * snb_update_pm_irq - update GEN6_PMIMR
 158   * @dev_priv: driver private
 159   * @interrupt_mask: mask of interrupt bits to update
 160   * @enabled_irq_mask: mask of interrupt bits to enable
 161   */
 162 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 163                               uint32_t interrupt_mask,
 164                               uint32_t enabled_irq_mask)
 165 {
 166         uint32_t new_val;
 167
 168         assert_spin_locked(&dev_priv->irq_lock);
 169
 170         if (dev_priv->pc8.irqs_disabled) {
 171                 WARN(1, "IRQs disabled\n");
 172                 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
 173                 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
 174                                                      interrupt_mask);
 175                 return;
 176         }
 177
 178         new_val = dev_priv->pm_irq_mask;
 179         new_val &= ~interrupt_mask;
 180         new_val |= (~enabled_irq_mask & interrupt_mask);
 181
 182         if (new_val != dev_priv->pm_irq_mask) {
 183                 dev_priv->pm_irq_mask = new_val;
 184                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
 185                 POSTING_READ(GEN6_PMIMR);
 186         }
 187 }
 188
 189 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 190 {
 191         snb_update_pm_irq(dev_priv, mask, mask);
 192 }
 193
 194 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 195 {
 196         snb_update_pm_irq(dev_priv, mask, 0);
 197 }
 198
 199 static bool ivb_can_enable_err_int(struct drm_device *dev)
 200 {
 201         struct drm_i915_private *dev_priv = dev->dev_private;
 202         struct intel_crtc *crtc;
 203         enum pipe pipe;
 204
 205         assert_spin_locked(&dev_priv->irq_lock);
 206
 207         for_each_pipe(pipe) {
 208                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 209
 210                 if (crtc->cpu_fifo_underrun_disabled)
 211                         return false;
 212         }
 213
 214         return true;
 215 }
 216
 217 static bool cpt_can_enable_serr_int(struct drm_device *dev)
 218 {
 219         struct drm_i915_private *dev_priv = dev->dev_private;
 220         enum pipe pipe;
 221         struct intel_crtc *crtc;
 222
 223         assert_spin_locked(&dev_priv->irq_lock);
 224
 225         for_each_pipe(pipe) {
 226                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 227
 228                 if (crtc->pch_fifo_underrun_disabled)
 229                         return false;
 230         }
 231
 232         return true;
 233 }
 234
 235 static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
 236 {
 237         struct drm_i915_private *dev_priv = dev->dev_private;
 238         u32 reg = PIPESTAT(pipe);
 239         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 240
 241         assert_spin_locked(&dev_priv->irq_lock);
 242
 243         I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
 244         POSTING_READ(reg);
 245 }
 246
 247 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 248                                                  enum pipe pipe, bool enable)
 249 {
 250         struct drm_i915_private *dev_priv = dev->dev_private;
 251         uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
 252                                           DE_PIPEB_FIFO_UNDERRUN;
 253
 254         if (enable)
 255                 ironlake_enable_display_irq(dev_priv, bit);
 256         else
 257                 ironlake_disable_display_irq(dev_priv, bit);
 258 }
 259
 260 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 261                                                   enum pipe pipe, bool enable)
 262 {
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         if (enable) {
 265                 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
 266
 267                 if (!ivb_can_enable_err_int(dev))
 268                         return;
 269
 270                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
 271         } else {
 272                 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
 273
 274                 /* Change the state _after_ we've read out the current one. */
 275                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 276
 277                 if (!was_enabled &&
 278                     (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
 279                         DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
 280                                       pipe_name(pipe));
 281                 }
 282         }
 283 }
 284
 285 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
 286                                                   enum pipe pipe, bool enable)
 287 {
 288         struct drm_i915_private *dev_priv = dev->dev_private;
 289
 290         assert_spin_locked(&dev_priv->irq_lock);
 291
 292         if (enable)
 293                 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
 294         else
 295                 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
 296         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 297         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 298 }
 299
 300 /**
 301  * ibx_display_interrupt_update - update SDEIMR
 302  * @dev_priv: driver private
 303  * @interrupt_mask: mask of interrupt bits to update
 304  * @enabled_irq_mask: mask of interrupt bits to enable
 305  */
 306 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 307                                          uint32_t interrupt_mask,
 308                                          uint32_t enabled_irq_mask)
 309 {
 310         uint32_t sdeimr = I915_READ(SDEIMR);
 311         sdeimr &= ~interrupt_mask;
 312         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 313
 314         assert_spin_locked(&dev_priv->irq_lock);
 315
 316         if (dev_priv->pc8.irqs_disabled &&
 317             (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
 318                 WARN(1, "IRQs disabled\n");
 319                 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
 320                 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
 321                                                  interrupt_mask);
 322                 return;
 323         }
 324
 325         I915_WRITE(SDEIMR, sdeimr);
 326         POSTING_READ(SDEIMR);
 327 }
 328 #define ibx_enable_display_interrupt(dev_priv, bits) \
 329         ibx_display_interrupt_update((dev_priv), (bits), (bits))
 330 #define ibx_disable_display_interrupt(dev_priv, bits) \
 331         ibx_display_interrupt_update((dev_priv), (bits), 0)
 332
 333 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
 334                                             enum transcoder pch_transcoder,
 335                                             bool enable)
 336 {
 337         struct drm_i915_private *dev_priv = dev->dev_private;
 338         uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
 339                        SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
 340
 341         if (enable)
 342                 ibx_enable_display_interrupt(dev_priv, bit);
 343         else
 344                 ibx_disable_display_interrupt(dev_priv, bit);
 345 }
 346
 347 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 348                                             enum transcoder pch_transcoder,
 349                                             bool enable)
 350 {
 351         struct drm_i915_private *dev_priv = dev->dev_private;
 352
 353         if (enable) {
 354                 I915_WRITE(SERR_INT,
 355                            SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 356
 357                 if (!cpt_can_enable_serr_int(dev))
 358                         return;
 359
 360                 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 361         } else {
 362                 uint32_t tmp = I915_READ(SERR_INT);
 363                 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
 364
 365                 /* Change the state _after_ we've read out the current one. */
 366                 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 367
 368                 if (!was_enabled &&
 369                     (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
 370                         DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
 371                                       transcoder_name(pch_transcoder));
 372                 }
 373         }
 374 }
 375
 376 /**
 377  * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 378  * @dev: drm device
 379  * @pipe: pipe
 380  * @enable: true if we want to report FIFO underrun errors, false otherwise
 381  *
 382  * This function makes us disable or enable CPU fifo underruns for a specific
 383  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 384  * reporting for one pipe may also disable all the other CPU error interruts for
 385  * the other pipes, due to the fact that there's just one interrupt mask/enable
 386  * bit for all the pipes.
 387  *
 388  * Returns the previous state of underrun reporting.
 389  */
 390 bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 391                                              enum pipe pipe, bool enable)
 392 {
 393         struct drm_i915_private *dev_priv = dev->dev_private;
 394         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 396         bool ret;
 397
 398         assert_spin_locked(&dev_priv->irq_lock);
 399
 400         ret = !intel_crtc->cpu_fifo_underrun_disabled;
 401
 402         if (enable == ret)
 403                 goto done;
 404
 405         intel_crtc->cpu_fifo_underrun_disabled = !enable;
 406
 407         if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
 408                 i9xx_clear_fifo_underrun(dev, pipe);
 409         else if (IS_GEN5(dev) || IS_GEN6(dev))
 410                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 411         else if (IS_GEN7(dev))
 412                 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
 413         else if (IS_GEN8(dev))
 414                 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 415
 416 done:
 417         return ret;
 418 }
 419
 420 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 421                                            enum pipe pipe, bool enable)
 422 {
 423         struct drm_i915_private *dev_priv = dev->dev_private;
 424         unsigned long flags;
 425         bool ret;
 426
 427         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 428         ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
 429         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 430
 431         return ret;
 432 }
 433
 434 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
 435                                                   enum pipe pipe)
 436 {
 437         struct drm_i915_private *dev_priv = dev->dev_private;
 438         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 439         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 440
 441         return !intel_crtc->cpu_fifo_underrun_disabled;
 442 }
 443
 444 /**
 445  * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 446  * @dev: drm device
 447  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 448  * @enable: true if we want to report FIFO underrun errors, false otherwise
 449  *
 450  * This function makes us disable or enable PCH fifo underruns for a specific
 451  * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 452  * underrun reporting for one transcoder may also disable all the other PCH
 453  * error interruts for the other transcoders, due to the fact that there's just
 454  * one interrupt mask/enable bit for all the transcoders.
 455  *
 456  * Returns the previous state of underrun reporting.
 457  */
 458 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 459                                            enum transcoder pch_transcoder,
 460                                            bool enable)
 461 {
 462         struct drm_i915_private *dev_priv = dev->dev_private;
 463         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
 464         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 465         unsigned long flags;
 466         bool ret;
 467
 468         /*
 469          * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
 470          * has only one pch transcoder A that all pipes can use. To avoid racy
 471          * pch transcoder -> pipe lookups from interrupt code simply store the
 472          * underrun statistics in crtc A. Since we never expose this anywhere
 473          * nor use it outside of the fifo underrun code here using the "wrong"
 474          * crtc on LPT won't cause issues.
 475          */
 476
 477         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 478
 479         ret = !intel_crtc->pch_fifo_underrun_disabled;
 480
 481         if (enable == ret)
 482                 goto done;
 483
 484         intel_crtc->pch_fifo_underrun_disabled = !enable;
 485
 486         if (HAS_PCH_IBX(dev))
 487                 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 488         else
 489                 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 490
 491 done:
 492         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 493         return ret;
 494 }
 495
 496
 497 static void
 498 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 499                        u32 enable_mask, u32 status_mask)
 500 {
 501         u32 reg = PIPESTAT(pipe);
 502         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 503
 504         assert_spin_locked(&dev_priv->irq_lock);
 505
 506         if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 507                          status_mask & ~PIPESTAT_INT_STATUS_MASK))
 508                 return;
 509
 510         if ((pipestat & enable_mask) == enable_mask)
 511                 return;
 512
 513         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 514
 515         /* Enable the interrupt, clear any pending status */
 516         pipestat |= enable_mask | status_mask;
 517         I915_WRITE(reg, pipestat);
 518         POSTING_READ(reg);
 519 }
 520
 521 static void
 522 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 523                         u32 enable_mask, u32 status_mask)
 524 {
 525         u32 reg = PIPESTAT(pipe);
 526         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 527
 528         assert_spin_locked(&dev_priv->irq_lock);
 529
 530         if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 531                          status_mask & ~PIPESTAT_INT_STATUS_MASK))
 532                 return;
 533
 534         if ((pipestat & enable_mask) == 0)
 535                 return;
 536
 537         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 538
 539         pipestat &= ~enable_mask;
 540         I915_WRITE(reg, pipestat);
 541         POSTING_READ(reg);
 542 }
 543
 544 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 545 {
 546         u32 enable_mask = status_mask << 16;
 547
 548         /*
 549          * On pipe A we don't support the PSR interrupt yet, on pipe B the
 550          * same bit MBZ.
 551          */
 552         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 553                 return 0;
 554
 555         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 556                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 557                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 558         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 559                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 560         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 561                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 562
 563         return enable_mask;
 564 }
 565
 566 void
 567 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 568                      u32 status_mask)
 569 {
 570         u32 enable_mask;
 571
 572         if (IS_VALLEYVIEW(dev_priv->dev))
 573                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 574                                                            status_mask);
 575         else
 576                 enable_mask = status_mask << 16;
 577         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 578 }
 579
 580 void
 581 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 582                       u32 status_mask)
 583 {
 584         u32 enable_mask;
 585
 586         if (IS_VALLEYVIEW(dev_priv->dev))
 587                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 588                                                            status_mask);
 589         else
 590                 enable_mask = status_mask << 16;
 591         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 592 }
 593
 594 /**
 595  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 596  */
 597 static void i915_enable_asle_pipestat(struct drm_device *dev)
 598 {
 599         drm_i915_private_t *dev_priv = dev->dev_private;
 600         unsigned long irqflags;
 601
 602         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 603                 return;
 604
 605         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 606
 607         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 608         if (INTEL_INFO(dev)->gen >= 4)
 609                 i915_enable_pipestat(dev_priv, PIPE_A,
 610                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 611
 612         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 613 }
 614
 615 /**
 616  * i915_pipe_enabled - check if a pipe is enabled
 617  * @dev: DRM device
 618  * @pipe: pipe to check
 619  *
 620  * Reading certain registers when the pipe is disabled can hang the chip.
 621  * Use this routine to make sure the PLL is running and the pipe is active
 622  * before reading such registers if unsure.
 623  */
 624 static int
 625 i915_pipe_enabled(struct drm_device *dev, int pipe)
 626 {
 627         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 628
 629         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 630                 /* Locking is horribly broken here, but whatever. */
 631                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 632                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 633
 634                 return intel_crtc->active;
 635         } else {
 636                 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 637         }
 638 }
 639
 640 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
 641 {
 642         /* Gen2 doesn't have a hardware frame counter */
 643         return 0;
 644 }
 645
 646 /* Called from drm generic code, passed a 'crtc', which
 647  * we use as a pipe index
 648  */
 649 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 650 {
 651         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 652         unsigned long high_frame;
 653         unsigned long low_frame;
 654         u32 high1, high2, low, pixel, vbl_start;
 655
 656         if (!i915_pipe_enabled(dev, pipe)) {
 657                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 658                                 "pipe %c\n", pipe_name(pipe));
 659                 return 0;
 660         }
 661
 662         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 663                 struct intel_crtc *intel_crtc =
 664                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 665                 const struct drm_display_mode *mode =
 666                         &intel_crtc->config.adjusted_mode;
 667
 668                 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
 669         } else {
 670                 enum transcoder cpu_transcoder = (enum transcoder) pipe;
 671                 u32 htotal;
 672
 673                 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
 674                 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
 675
 676                 vbl_start *= htotal;
 677         }
 678
 679         high_frame = PIPEFRAME(pipe);
 680         low_frame = PIPEFRAMEPIXEL(pipe);
 681
 682         /*
 683          * High & low register fields aren't synchronized, so make sure
 684          * we get a low value that's stable across two reads of the high
 685          * register.
 686          */
 687         do {
 688                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 689                 low   = I915_READ(low_frame);
 690                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 691         } while (high1 != high2);
 692
 693         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 694         pixel = low & PIPE_PIXEL_MASK;
 695         low >>= PIPE_FRAME_LOW_SHIFT;
 696
 697         /*
 698          * The frame counter increments at beginning of active.
 699          * Cook up a vblank counter by also checking the pixel
 700          * counter against vblank start.
 701          */
 702         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 703 }
 704
 705 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 706 {
 707         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 708         int reg = PIPE_FRMCOUNT_GM45(pipe);
 709
 710         if (!i915_pipe_enabled(dev, pipe)) {
 711                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 712                                  "pipe %c\n", pipe_name(pipe));
 713                 return 0;
 714         }
 715
 716         return I915_READ(reg);
 717 }
 718
 719 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
 720 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 721 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
 722
 723 static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
 724 {
 725         struct drm_i915_private *dev_priv = dev->dev_private;
 726         uint32_t status;
 727
 728         if (INTEL_INFO(dev)->gen < 7) {
 729                 status = pipe == PIPE_A ?
 730                         DE_PIPEA_VBLANK :
 731                         DE_PIPEB_VBLANK;
 732         } else {
 733                 switch (pipe) {
 734                 default:
 735                 case PIPE_A:
 736                         status = DE_PIPEA_VBLANK_IVB;
 737                         break;
 738                 case PIPE_B:
 739                         status = DE_PIPEB_VBLANK_IVB;
 740                         break;
 741                 case PIPE_C:
 742                         status = DE_PIPEC_VBLANK_IVB;
 743                         break;
 744                 }
 745         }
 746
 747         return __raw_i915_read32(dev_priv, DEISR) & status;
 748 }
 749
 750 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 751                                     unsigned int flags, int *vpos, int *hpos,
 752                                     ktime_t *stime, ktime_t *etime)
 753 {
 754         struct drm_i915_private *dev_priv = dev->dev_private;
 755         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 757         const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
 758         int position;
 759         int vbl_start, vbl_end, htotal, vtotal;
 760         bool in_vbl = true;
 761         int ret = 0;
 762         unsigned long irqflags;
 763
 764         if (!intel_crtc->active) {
 765                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 766                                  "pipe %c\n", pipe_name(pipe));
 767                 return 0;
 768         }
 769
 770         htotal = mode->crtc_htotal;
 771         vtotal = mode->crtc_vtotal;
 772         vbl_start = mode->crtc_vblank_start;
 773         vbl_end = mode->crtc_vblank_end;
 774
 775         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 776                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 777                 vbl_end /= 2;
 778                 vtotal /= 2;
 779         }
 780
 781         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 782
 783         /*
 784          * Lock uncore.lock, as we will do multiple timing critical raw
 785          * register reads, potentially with preemption disabled, so the
 786          * following code must not block on uncore.lock.
 787          */
 788         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 789
 790         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 791
 792         /* Get optional system timestamp before query. */
 793         if (stime)
 794                 *stime = ktime_get();
 795
 796         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 797                 /* No obvious pixelcount register. Only query vertical
 798                  * scanout position from Display scan line register.
 799                  */
 800                 if (IS_GEN2(dev))
 801                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 802                 else
 803                         position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 804
 805                 if (HAS_PCH_SPLIT(dev)) {
 806                         /*
 807                          * The scanline counter increments at the leading edge
 808                          * of hsync, ie. it completely misses the active portion
 809                          * of the line. Fix up the counter at both edges of vblank
 810                          * to get a more accurate picture whether we're in vblank
 811                          * or not.
 812                          */
 813                         in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
 814                         if ((in_vbl && position == vbl_start - 1) ||
 815                             (!in_vbl && position == vbl_end - 1))
 816                                 position = (position + 1) % vtotal;
 817                 } else {
 818                         /*
 819                          * ISR vblank status bits don't work the way we'd want
 820                          * them to work on non-PCH platforms (for
 821                          * ilk_pipe_in_vblank_locked()), and there doesn't
 822                          * appear any other way to determine if we're currently
 823                          * in vblank.
 824                          *
 825                          * Instead let's assume that we're already in vblank if
 826                          * we got called from the vblank interrupt and the
 827                          * scanline counter value indicates that we're on the
 828                          * line just prior to vblank start. This should result
 829                          * in the correct answer, unless the vblank interrupt
 830                          * delivery really got delayed for almost exactly one
 831                          * full frame/field.
 832                          */
 833                         if (flags & DRM_CALLED_FROM_VBLIRQ &&
 834                             position == vbl_start - 1) {
 835                                 position = (position + 1) % vtotal;
 836
 837                                 /* Signal this correction as "applied". */
 838                                 ret |= 0x8;
 839                         }
 840                 }
 841         } else {
 842                 /* Have access to pixelcount since start of frame.
 843                  * We can split this into vertical and horizontal
 844                  * scanout position.
 845                  */
 846                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 847
 848                 /* convert to pixel counts */
 849                 vbl_start *= htotal;
 850                 vbl_end *= htotal;
 851                 vtotal *= htotal;
 852         }
 853
 854         /* Get optional system timestamp after query. */
 855         if (etime)
 856                 *etime = ktime_get();
 857
 858         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 859
 860         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 861
 862         in_vbl = position >= vbl_start && position < vbl_end;
 863
 864         /*
 865          * While in vblank, position will be negative
 866          * counting up towards 0 at vbl_end. And outside
 867          * vblank, position will be positive counting
 868          * up since vbl_end.
 869          */
 870         if (position >= vbl_start)
 871                 position -= vbl_end;
 872         else
 873                 position += vtotal - vbl_end;
 874
 875         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 876                 *vpos = position;
 877                 *hpos = 0;
 878         } else {
 879                 *vpos = position / htotal;
 880                 *hpos = position - (*vpos * htotal);
 881         }
 882
 883         /* In vblank? */
 884         if (in_vbl)
 885                 ret |= DRM_SCANOUTPOS_INVBL;
 886
 887         return ret;
 888 }
 889
 890 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 891                               int *max_error,
 892                               struct timeval *vblank_time,
 893                               unsigned flags)
 894 {
 895         struct drm_crtc *crtc;
 896
 897         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 898                 DRM_ERROR("Invalid crtc %d\n", pipe);
 899                 return -EINVAL;
 900         }
 901
 902         /* Get drm_crtc to timestamp: */
 903         crtc = intel_get_crtc_for_pipe(dev, pipe);
 904         if (crtc == NULL) {
 905                 DRM_ERROR("Invalid crtc %d\n", pipe);
 906                 return -EINVAL;
 907         }
 908
 909         if (!crtc->enabled) {
 910                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 911                 return -EBUSY;
 912         }
 913
 914         /* Helper routine in DRM core does all the work: */
 915         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 916                                                      vblank_time, flags,
 917                                                      crtc,
 918                                                      &to_intel_crtc(crtc)->config.adjusted_mode);
 919 }
 920
 921 static bool intel_hpd_irq_event(struct drm_device *dev,
 922                                 struct drm_connector *connector)
 923 {
 924         enum drm_connector_status old_status;
 925
 926         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 927         old_status = connector->status;
 928
 929         connector->status = connector->funcs->detect(connector, false);
 930         if (old_status == connector->status)
 931                 return false;
 932
 933         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
 934                       connector->base.id,
 935                       drm_get_connector_name(connector),
 936                       drm_get_connector_status_name(old_status),
 937                       drm_get_connector_status_name(connector->status));
 938
 939         return true;
 940 }
 941
 942 /*
 943  * Handle hotplug events outside the interrupt handler proper.
 944  */
 945 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 946
 947 static void i915_hotplug_work_func(struct work_struct *work)
 948 {
 949         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 950                                                     hotplug_work);
 951         struct drm_device *dev = dev_priv->dev;
 952         struct drm_mode_config *mode_config = &dev->mode_config;
 953         struct intel_connector *intel_connector;
 954         struct intel_encoder *intel_encoder;
 955         struct drm_connector *connector;
 956         unsigned long irqflags;
 957         bool hpd_disabled = false;
 958         bool changed = false;
 959         u32 hpd_event_bits;
 960
 961         /* HPD irq before everything is fully set up. */
 962         if (!dev_priv->enable_hotplug_processing)
 963                 return;
 964
 965         mutex_lock(&mode_config->mutex);
 966         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 967
 968         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 969
 970         hpd_event_bits = dev_priv->hpd_event_bits;
 971         dev_priv->hpd_event_bits = 0;
 972         list_for_each_entry(connector, &mode_config->connector_list, head) {
 973                 intel_connector = to_intel_connector(connector);
 974                 intel_encoder = intel_connector->encoder;
 975                 if (intel_encoder->hpd_pin > HPD_NONE &&
 976                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 977                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 978                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 979                                  "switching from hotplug detection to polling\n",
 980                                 drm_get_connector_name(connector));
 981                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 982                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 983                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 984                         hpd_disabled = true;
 985                 }
 986                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 987                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
 988                                       drm_get_connector_name(connector), intel_encoder->hpd_pin);
 989                 }
 990         }
 991          /* if there were no outputs to poll, poll was disabled,
 992           * therefore make sure it's enabled when disabling HPD on
 993           * some connectors */
 994         if (hpd_disabled) {
 995                 drm_kms_helper_poll_enable(dev);
 996                 mod_timer(&dev_priv->hotplug_reenable_timer,
 997                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 998         }
 999
1000         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1001
1002         list_for_each_entry(connector, &mode_config->connector_list, head) {
1003                 intel_connector = to_intel_connector(connector);
1004                 intel_encoder = intel_connector->encoder;
1005                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1006                         if (intel_encoder->hot_plug)
1007                                 intel_encoder->hot_plug(intel_encoder);
1008                         if (intel_hpd_irq_event(dev, connector))
1009                                 changed = true;
1010                 }
1011         }
1012         mutex_unlock(&mode_config->mutex);
1013
1014         if (changed)
1015                 drm_kms_helper_hotplug_event(dev);
1016 }
1017
1018 static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1019 {
1020         del_timer_sync(&dev_priv->hotplug_reenable_timer);
1021 }
1022
1023 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1024 {
1025         drm_i915_private_t *dev_priv = dev->dev_private;
1026         u32 busy_up, busy_down, max_avg, min_avg;
1027         u8 new_delay;
1028
1029         spin_lock(&mchdev_lock);
1030
1031         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1032
1033         new_delay = dev_priv->ips.cur_delay;
1034
1035         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1036         busy_up = I915_READ(RCPREVBSYTUPAVG);
1037         busy_down = I915_READ(RCPREVBSYTDNAVG);
1038         max_avg = I915_READ(RCBMAXAVG);
1039         min_avg = I915_READ(RCBMINAVG);
1040
1041         /* Handle RCS change request from hw */
1042         if (busy_up > max_avg) {
1043                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1044                         new_delay = dev_priv->ips.cur_delay - 1;
1045                 if (new_delay < dev_priv->ips.max_delay)
1046                         new_delay = dev_priv->ips.max_delay;
1047         } else if (busy_down < min_avg) {
1048                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1049                         new_delay = dev_priv->ips.cur_delay + 1;
1050                 if (new_delay > dev_priv->ips.min_delay)
1051                         new_delay = dev_priv->ips.min_delay;
1052         }
1053
1054         if (ironlake_set_drps(dev, new_delay))
1055                 dev_priv->ips.cur_delay = new_delay;
1056
1057         spin_unlock(&mchdev_lock);
1058
1059         return;
1060 }
1061
1062 static void notify_ring(struct drm_device *dev,
1063                         struct intel_ring_buffer *ring)
1064 {
1065         if (ring->obj == NULL)
1066                 return;
1067
1068         trace_i915_gem_request_complete(ring);
1069
1070         wake_up_all(&ring->irq_queue);
1071         i915_queue_hangcheck(dev);
1072 }
1073
1074 void gen6_set_pm_mask(struct drm_i915_private *dev_priv,
1075                              u32 pm_iir, int new_delay)
1076 {
1077         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1078                 if (new_delay >= dev_priv->rps.max_delay) {
1079                         /* Mask UP THRESHOLD Interrupts */
1080                         I915_WRITE(GEN6_PMINTRMSK,
1081                                    I915_READ(GEN6_PMINTRMSK) |
1082                                    GEN6_PM_RP_UP_THRESHOLD);
1083                         dev_priv->rps.rp_up_masked = true;
1084                 }
1085                 if (dev_priv->rps.rp_down_masked) {
1086                         /* UnMask DOWN THRESHOLD Interrupts */
1087                         I915_WRITE(GEN6_PMINTRMSK,
1088                                    I915_READ(GEN6_PMINTRMSK) &
1089                                    ~GEN6_PM_RP_DOWN_THRESHOLD);
1090                         dev_priv->rps.rp_down_masked = false;
1091                 }
1092         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1093                 if (new_delay <= dev_priv->rps.min_delay) {
1094                         /* Mask DOWN THRESHOLD Interrupts */
1095                         I915_WRITE(GEN6_PMINTRMSK,
1096                                    I915_READ(GEN6_PMINTRMSK) |
1097                                    GEN6_PM_RP_DOWN_THRESHOLD);
1098                         dev_priv->rps.rp_down_masked = true;
1099                 }
1100
1101                 if (dev_priv->rps.rp_up_masked) {
1102                         /* UnMask UP THRESHOLD Interrupts */
1103                         I915_WRITE(GEN6_PMINTRMSK,
1104                                    I915_READ(GEN6_PMINTRMSK) &
1105                                    ~GEN6_PM_RP_UP_THRESHOLD);
1106                         dev_priv->rps.rp_up_masked = false;
1107                 }
1108         }
1109 }
1110
1111 static void gen6_pm_rps_work(struct work_struct *work)
1112 {
1113         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1114                                                     rps.work);
1115         u32 pm_iir;
1116         int new_delay, adj;
1117
1118         spin_lock_irq(&dev_priv->irq_lock);
1119         pm_iir = dev_priv->rps.pm_iir;
1120         dev_priv->rps.pm_iir = 0;
1121         /* Make sure not to corrupt PMIMR state used by ringbuffer code */
1122         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
1123         spin_unlock_irq(&dev_priv->irq_lock);
1124
1125         /* Make sure we didn't queue anything we're not going to process. */
1126         WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
1127
1128         if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
1129                 return;
1130
1131         mutex_lock(&dev_priv->rps.hw_lock);
1132
1133         adj = dev_priv->rps.last_adj;
1134         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1135                 if (adj > 0)
1136                         adj *= 2;
1137                 else
1138                         adj = 1;
1139                 new_delay = dev_priv->rps.cur_delay + adj;
1140
1141                 /*
1142                  * For better performance, jump directly
1143                  * to RPe if we're below it.
1144                  */
1145                 if (new_delay < dev_priv->rps.rpe_delay)
1146                         new_delay = dev_priv->rps.rpe_delay;
1147         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1148                 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
1149                         new_delay = dev_priv->rps.rpe_delay;
1150                 else
1151                         new_delay = dev_priv->rps.min_delay;
1152                 adj = 0;
1153         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1154                 if (adj < 0)
1155                         adj *= 2;
1156                 else
1157                         adj = -1;
1158                 new_delay = dev_priv->rps.cur_delay + adj;
1159         } else { /* unknown event */
1160                 new_delay = dev_priv->rps.cur_delay;
1161         }
1162
1163         /* sysfs frequency interfaces may have snuck in while servicing the
1164          * interrupt
1165          */
1166         new_delay = clamp_t(int, new_delay,
1167                             dev_priv->rps.min_delay, dev_priv->rps.max_delay);
1168
1169         gen6_set_pm_mask(dev_priv, pm_iir, new_delay);
1170         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
1171
1172         if (IS_VALLEYVIEW(dev_priv->dev))
1173                 valleyview_set_rps(dev_priv->dev, new_delay);
1174         else
1175                 gen6_set_rps(dev_priv->dev, new_delay);
1176
1177         mutex_unlock(&dev_priv->rps.hw_lock);
1178 }
1179
1180
1181 /**
1182  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1183  * occurred.
1184  * @work: workqueue struct
1185  *
1186  * Doesn't actually do anything except notify userspace. As a consequence of
1187  * this event, userspace should try to remap the bad rows since statistically
1188  * it is likely the same row is more likely to go bad again.
1189  */
1190 static void ivybridge_parity_work(struct work_struct *work)
1191 {
1192         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
1193                                                     l3_parity.error_work);
1194         u32 error_status, row, bank, subbank;
1195         char *parity_event[6];
1196         uint32_t misccpctl;
1197         unsigned long flags;
1198         uint8_t slice = 0;
1199
1200         /* We must turn off DOP level clock gating to access the L3 registers.
1201          * In order to prevent a get/put style interface, acquire struct mutex
1202          * any time we access those registers.
1203          */
1204         mutex_lock(&dev_priv->dev->struct_mutex);
1205
1206         /* If we've screwed up tracking, just let the interrupt fire again */
1207         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1208                 goto out;
1209
1210         misccpctl = I915_READ(GEN7_MISCCPCTL);
1211         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1212         POSTING_READ(GEN7_MISCCPCTL);
1213
1214         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1215                 u32 reg;
1216
1217                 slice--;
1218                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1219                         break;
1220
1221                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1222
1223                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1224
1225                 error_status = I915_READ(reg);
1226                 row = GEN7_PARITY_ERROR_ROW(error_status);
1227                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1228                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1229
1230                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1231                 POSTING_READ(reg);
1232
1233                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1234                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1235                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1236                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1237                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1238                 parity_event[5] = NULL;
1239
1240                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1241                                    KOBJ_CHANGE, parity_event);
1242
1243                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1244                           slice, row, bank, subbank);
1245
1246                 kfree(parity_event[4]);
1247                 kfree(parity_event[3]);
1248                 kfree(parity_event[2]);
1249                 kfree(parity_event[1]);
1250         }
1251
1252         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1253
1254 out:
1255         WARN_ON(dev_priv->l3_parity.which_slice);
1256         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1257         ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1258         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1259
1260         mutex_unlock(&dev_priv->dev->struct_mutex);
1261 }
1262
1263 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1264 {
1265         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1266
1267         if (!HAS_L3_DPF(dev))
1268                 return;
1269
1270         spin_lock(&dev_priv->irq_lock);
1271         ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1272         spin_unlock(&dev_priv->irq_lock);
1273
1274         iir &= GT_PARITY_ERROR(dev);
1275         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1276                 dev_priv->l3_parity.which_slice |= 1 << 1;
1277
1278         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1279                 dev_priv->l3_parity.which_slice |= 1 << 0;
1280
1281         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1282 }
1283
1284 static void ilk_gt_irq_handler(struct drm_device *dev,
1285                                struct drm_i915_private *dev_priv,
1286                                u32 gt_iir)
1287 {
1288         if (gt_iir &
1289             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1290                 notify_ring(dev, &dev_priv->ring[RCS]);
1291         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1292                 notify_ring(dev, &dev_priv->ring[VCS]);
1293 }
1294
1295 static void snb_gt_irq_handler(struct drm_device *dev,
1296                                struct drm_i915_private *dev_priv,
1297                                u32 gt_iir)
1298 {
1299
1300         if (gt_iir &
1301             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1302                 notify_ring(dev, &dev_priv->ring[RCS]);
1303         if (gt_iir & GT_BSD_USER_INTERRUPT)
1304                 notify_ring(dev, &dev_priv->ring[VCS]);
1305         if (gt_iir & GT_BLT_USER_INTERRUPT)
1306                 notify_ring(dev, &dev_priv->ring[BCS]);
1307
1308         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1309                       GT_BSD_CS_ERROR_INTERRUPT |
1310                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1311                 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1312                                   gt_iir);
1313         }
1314
1315         if (gt_iir & GT_PARITY_ERROR(dev))
1316                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1317 }
1318
1319 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1320                                        struct drm_i915_private *dev_priv,
1321                                        u32 master_ctl)
1322 {
1323         u32 rcs, bcs, vcs;
1324         uint32_t tmp = 0;
1325         irqreturn_t ret = IRQ_NONE;
1326
1327         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1328                 tmp = I915_READ(GEN8_GT_IIR(0));
1329                 if (tmp) {
1330                         ret = IRQ_HANDLED;
1331                         rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1332                         bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1333                         if (rcs & GT_RENDER_USER_INTERRUPT)
1334                                 notify_ring(dev, &dev_priv->ring[RCS]);
1335                         if (bcs & GT_RENDER_USER_INTERRUPT)
1336                                 notify_ring(dev, &dev_priv->ring[BCS]);
1337                         I915_WRITE(GEN8_GT_IIR(0), tmp);
1338                 } else
1339                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1340         }
1341
1342         if (master_ctl & GEN8_GT_VCS1_IRQ) {
1343                 tmp = I915_READ(GEN8_GT_IIR(1));
1344                 if (tmp) {
1345                         ret = IRQ_HANDLED;
1346                         vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1347                         if (vcs & GT_RENDER_USER_INTERRUPT)
1348                                 notify_ring(dev, &dev_priv->ring[VCS]);
1349                         I915_WRITE(GEN8_GT_IIR(1), tmp);
1350                 } else
1351                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1352         }
1353
1354         if (master_ctl & GEN8_GT_VECS_IRQ) {
1355                 tmp = I915_READ(GEN8_GT_IIR(3));
1356                 if (tmp) {
1357                         ret = IRQ_HANDLED;
1358                         vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1359                         if (vcs & GT_RENDER_USER_INTERRUPT)
1360                                 notify_ring(dev, &dev_priv->ring[VECS]);
1361                         I915_WRITE(GEN8_GT_IIR(3), tmp);
1362                 } else
1363                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1364         }
1365
1366         return ret;
1367 }
1368
1369 #define HPD_STORM_DETECT_PERIOD 1000
1370 #define HPD_STORM_THRESHOLD 5
1371
1372 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1373                                          u32 hotplug_trigger,
1374                                          const u32 *hpd)
1375 {
1376         drm_i915_private_t *dev_priv = dev->dev_private;
1377         int i;
1378         bool storm_detected = false;
1379
1380         if (!hotplug_trigger)
1381                 return;
1382
1383         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1384                           hotplug_trigger);
1385
1386         spin_lock(&dev_priv->irq_lock);
1387         for (i = 1; i < HPD_NUM_PINS; i++) {
1388
1389                 WARN_ONCE(hpd[i] & hotplug_trigger &&
1390                           dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
1391                           "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1392                           hotplug_trigger, i, hpd[i]);
1393
1394                 if (!(hpd[i] & hotplug_trigger) ||
1395                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1396                         continue;
1397
1398                 dev_priv->hpd_event_bits |= (1 << i);
1399                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1400                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1401                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1402                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1403                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1404                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1405                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1406                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1407                         dev_priv->hpd_event_bits &= ~(1 << i);
1408                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1409                         storm_detected = true;
1410                 } else {
1411                         dev_priv->hpd_stats[i].hpd_cnt++;
1412                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1413                                       dev_priv->hpd_stats[i].hpd_cnt);
1414                 }
1415         }
1416
1417         if (storm_detected)
1418                 dev_priv->display.hpd_irq_setup(dev);
1419         spin_unlock(&dev_priv->irq_lock);
1420
1421         /*
1422          * Our hotplug handler can grab modeset locks (by calling down into the
1423          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1424          * queue for otherwise the flush_work in the pageflip code will
1425          * deadlock.
1426          */
1427         schedule_work(&dev_priv->hotplug_work);
1428 }
1429
1430 static void gmbus_irq_handler(struct drm_device *dev)
1431 {
1432         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1433
1434         wake_up_all(&dev_priv->gmbus_wait_queue);
1435 }
1436
1437 static void dp_aux_irq_handler(struct drm_device *dev)
1438 {
1439         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1440
1441         wake_up_all(&dev_priv->gmbus_wait_queue);
1442 }
1443
1444 #if defined(CONFIG_DEBUG_FS)
1445 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1446                                          uint32_t crc0, uint32_t crc1,
1447                                          uint32_t crc2, uint32_t crc3,
1448                                          uint32_t crc4)
1449 {
1450         struct drm_i915_private *dev_priv = dev->dev_private;
1451         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1452         struct intel_pipe_crc_entry *entry;
1453         int head, tail;
1454
1455         spin_lock(&pipe_crc->lock);
1456
1457         if (!pipe_crc->entries) {
1458                 spin_unlock(&pipe_crc->lock);
1459                 DRM_ERROR("spurious interrupt\n");
1460                 return;
1461         }
1462
1463         head = pipe_crc->head;
1464         tail = pipe_crc->tail;
1465
1466         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1467                 spin_unlock(&pipe_crc->lock);
1468                 DRM_ERROR("CRC buffer overflowing\n");
1469                 return;
1470         }
1471
1472         entry = &pipe_crc->entries[head];
1473
1474         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1475         entry->crc[0] = crc0;
1476         entry->crc[1] = crc1;
1477         entry->crc[2] = crc2;
1478         entry->crc[3] = crc3;
1479         entry->crc[4] = crc4;
1480
1481         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1482         pipe_crc->head = head;
1483
1484         spin_unlock(&pipe_crc->lock);
1485
1486         wake_up_interruptible(&pipe_crc->wq);
1487 }
1488 #else
1489 static inline void
1490 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1491                              uint32_t crc0, uint32_t crc1,
1492                              uint32_t crc2, uint32_t crc3,
1493                              uint32_t crc4) {}
1494 #endif
1495
1496
1497 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1498 {
1499         struct drm_i915_private *dev_priv = dev->dev_private;
1500
1501         display_pipe_crc_irq_handler(dev, pipe,
1502                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1503                                      0, 0, 0, 0);
1504 }
1505
1506 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1507 {
1508         struct drm_i915_private *dev_priv = dev->dev_private;
1509
1510         display_pipe_crc_irq_handler(dev, pipe,
1511                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1512                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1513                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1514                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1515                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1516 }
1517
1518 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1519 {
1520         struct drm_i915_private *dev_priv = dev->dev_private;
1521         uint32_t res1, res2;
1522
1523         if (INTEL_INFO(dev)->gen >= 3)
1524                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1525         else
1526                 res1 = 0;
1527
1528         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1529                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1530         else
1531                 res2 = 0;
1532
1533         display_pipe_crc_irq_handler(dev, pipe,
1534                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1535                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1536                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1537                                      res1, res2);
1538 }
1539
1540 /* The RPS events need forcewake, so we add them to a work queue and mask their
1541  * IMR bits until the work is done. Other interrupts can be processed without
1542  * the work queue. */
1543 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1544 {
1545         if (pm_iir & GEN6_PM_RPS_EVENTS) {
1546                 spin_lock(&dev_priv->irq_lock);
1547                 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1548                 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1549                 spin_unlock(&dev_priv->irq_lock);
1550
1551                 queue_work(dev_priv->wq, &dev_priv->rps.work);
1552         }
1553
1554         if (HAS_VEBOX(dev_priv->dev)) {
1555                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1556                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1557
1558                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1559                         i915_handle_error(dev_priv->dev, false,
1560                                           "VEBOX CS error interrupt 0x%08x",
1561                                           pm_iir);
1562                 }
1563         }
1564 }
1565
1566 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1567 {
1568         struct drm_i915_private *dev_priv = dev->dev_private;
1569         u32 pipe_stats[I915_MAX_PIPES] = { };
1570         int pipe;
1571
1572         spin_lock(&dev_priv->irq_lock);
1573         for_each_pipe(pipe) {
1574                 int reg;
1575                 u32 mask, iir_bit = 0;
1576
1577                 /*
1578                  * PIPESTAT bits get signalled even when the interrupt is
1579                  * disabled with the mask bits, and some of the status bits do
1580                  * not generate interrupts at all (like the underrun bit). Hence
1581                  * we need to be careful that we only handle what we want to
1582                  * handle.
1583                  */
1584                 mask = 0;
1585                 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1586                         mask |= PIPE_FIFO_UNDERRUN_STATUS;
1587
1588                 switch (pipe) {
1589                 case PIPE_A:
1590                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1591                         break;
1592                 case PIPE_B:
1593                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1594                         break;
1595                 }
1596                 if (iir & iir_bit)
1597                         mask |= dev_priv->pipestat_irq_mask[pipe];
1598
1599                 if (!mask)
1600                         continue;
1601
1602                 reg = PIPESTAT(pipe);
1603                 mask |= PIPESTAT_INT_ENABLE_MASK;
1604                 pipe_stats[pipe] = I915_READ(reg) & mask;
1605
1606                 /*
1607                  * Clear the PIPE*STAT regs before the IIR
1608                  */
1609                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1610                                         PIPESTAT_INT_STATUS_MASK))
1611                         I915_WRITE(reg, pipe_stats[pipe]);
1612         }
1613         spin_unlock(&dev_priv->irq_lock);
1614
1615         for_each_pipe(pipe) {
1616                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1617                         drm_handle_vblank(dev, pipe);
1618
1619                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
1620                         intel_prepare_page_flip(dev, pipe);
1621                         intel_finish_page_flip(dev, pipe);
1622                 }
1623
1624                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1625                         i9xx_pipe_crc_irq_handler(dev, pipe);
1626
1627                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1628                     intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1629                         DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1630         }
1631
1632         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1633                 gmbus_irq_handler(dev);
1634 }
1635
1636 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1637 {
1638         struct drm_device *dev = (struct drm_device *) arg;
1639         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1640         u32 iir, gt_iir, pm_iir;
1641         irqreturn_t ret = IRQ_NONE;
1642
1643         while (true) {
1644                 iir = I915_READ(VLV_IIR);
1645                 gt_iir = I915_READ(GTIIR);
1646                 pm_iir = I915_READ(GEN6_PMIIR);
1647
1648                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1649                         goto out;
1650
1651                 ret = IRQ_HANDLED;
1652
1653                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1654
1655                 valleyview_pipestat_irq_handler(dev, iir);
1656
1657                 /* Consume port.  Then clear IIR or we'll miss events */
1658                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1659                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1660                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1661
1662                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1663
1664                         if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1665                                 dp_aux_irq_handler(dev);
1666
1667                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1668                         I915_READ(PORT_HOTPLUG_STAT);
1669                 }
1670
1671
1672                 if (pm_iir)
1673                         gen6_rps_irq_handler(dev_priv, pm_iir);
1674
1675                 I915_WRITE(GTIIR, gt_iir);
1676                 I915_WRITE(GEN6_PMIIR, pm_iir);
1677                 I915_WRITE(VLV_IIR, iir);
1678         }
1679
1680 out:
1681         return ret;
1682 }
1683
1684 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1685 {
1686         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1687         int pipe;
1688         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1689
1690         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1691
1692         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1693                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1694                                SDE_AUDIO_POWER_SHIFT);
1695                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1696                                  port_name(port));
1697         }
1698
1699         if (pch_iir & SDE_AUX_MASK)
1700                 dp_aux_irq_handler(dev);
1701
1702         if (pch_iir & SDE_GMBUS)
1703                 gmbus_irq_handler(dev);
1704
1705         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1706                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1707
1708         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1709                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1710
1711         if (pch_iir & SDE_POISON)
1712                 DRM_ERROR("PCH poison interrupt\n");
1713
1714         if (pch_iir & SDE_FDI_MASK)
1715                 for_each_pipe(pipe)
1716                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1717                                          pipe_name(pipe),
1718                                          I915_READ(FDI_RX_IIR(pipe)));
1719
1720         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1721                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1722
1723         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1724                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1725
1726         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1727                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1728                                                           false))
1729                         DRM_ERROR("PCH transcoder A FIFO underrun\n");
1730
1731         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1732                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1733                                                           false))
1734                         DRM_ERROR("PCH transcoder B FIFO underrun\n");
1735 }
1736
1737 static void ivb_err_int_handler(struct drm_device *dev)
1738 {
1739         struct drm_i915_private *dev_priv = dev->dev_private;
1740         u32 err_int = I915_READ(GEN7_ERR_INT);
1741         enum pipe pipe;
1742
1743         if (err_int & ERR_INT_POISON)
1744                 DRM_ERROR("Poison interrupt\n");
1745
1746         for_each_pipe(pipe) {
1747                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1748                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1749                                                                   false))
1750                                 DRM_ERROR("Pipe %c FIFO underrun\n",
1751                                           pipe_name(pipe));
1752                 }
1753
1754                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1755                         if (IS_IVYBRIDGE(dev))
1756                                 ivb_pipe_crc_irq_handler(dev, pipe);
1757                         else
1758                                 hsw_pipe_crc_irq_handler(dev, pipe);
1759                 }
1760         }
1761
1762         I915_WRITE(GEN7_ERR_INT, err_int);
1763 }
1764
1765 static void cpt_serr_int_handler(struct drm_device *dev)
1766 {
1767         struct drm_i915_private *dev_priv = dev->dev_private;
1768         u32 serr_int = I915_READ(SERR_INT);
1769
1770         if (serr_int & SERR_INT_POISON)
1771                 DRM_ERROR("PCH poison interrupt\n");
1772
1773         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1774                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1775                                                           false))
1776                         DRM_ERROR("PCH transcoder A FIFO underrun\n");
1777
1778         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1779                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1780                                                           false))
1781                         DRM_ERROR("PCH transcoder B FIFO underrun\n");
1782
1783         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1784                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1785                                                           false))
1786                         DRM_ERROR("PCH transcoder C FIFO underrun\n");
1787
1788         I915_WRITE(SERR_INT, serr_int);
1789 }
1790
1791 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1792 {
1793         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1794         int pipe;
1795         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1796
1797         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1798
1799         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1800                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1801                                SDE_AUDIO_POWER_SHIFT_CPT);
1802                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1803                                  port_name(port));
1804         }
1805
1806         if (pch_iir & SDE_AUX_MASK_CPT)
1807                 dp_aux_irq_handler(dev);
1808
1809         if (pch_iir & SDE_GMBUS_CPT)
1810                 gmbus_irq_handler(dev);
1811
1812         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1813                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1814
1815         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1816                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1817
1818         if (pch_iir & SDE_FDI_MASK_CPT)
1819                 for_each_pipe(pipe)
1820                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1821                                          pipe_name(pipe),
1822                                          I915_READ(FDI_RX_IIR(pipe)));
1823
1824         if (pch_iir & SDE_ERROR_CPT)
1825                 cpt_serr_int_handler(dev);
1826 }
1827
1828 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1829 {
1830         struct drm_i915_private *dev_priv = dev->dev_private;
1831         enum pipe pipe;
1832
1833         if (de_iir & DE_AUX_CHANNEL_A)
1834                 dp_aux_irq_handler(dev);
1835
1836         if (de_iir & DE_GSE)
1837                 intel_opregion_asle_intr(dev);
1838
1839         if (de_iir & DE_POISON)
1840                 DRM_ERROR("Poison interrupt\n");
1841
1842         for_each_pipe(pipe) {
1843                 if (de_iir & DE_PIPE_VBLANK(pipe))
1844                         drm_handle_vblank(dev, pipe);
1845
1846                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1847                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1848                                 DRM_ERROR("Pipe %c FIFO underrun\n",
1849                                           pipe_name(pipe));
1850
1851                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1852                         i9xx_pipe_crc_irq_handler(dev, pipe);
1853
1854                 /* plane/pipes map 1:1 on ilk+ */
1855                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1856                         intel_prepare_page_flip(dev, pipe);
1857                         intel_finish_page_flip_plane(dev, pipe);
1858                 }
1859         }
1860
1861         /* check event from PCH */
1862         if (de_iir & DE_PCH_EVENT) {
1863                 u32 pch_iir = I915_READ(SDEIIR);
1864
1865                 if (HAS_PCH_CPT(dev))
1866                         cpt_irq_handler(dev, pch_iir);
1867                 else
1868                         ibx_irq_handler(dev, pch_iir);
1869
1870                 /* should clear PCH hotplug event before clear CPU irq */
1871                 I915_WRITE(SDEIIR, pch_iir);
1872         }
1873
1874         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1875                 ironlake_rps_change_irq_handler(dev);
1876 }
1877
1878 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1879 {
1880         struct drm_i915_private *dev_priv = dev->dev_private;
1881         enum pipe pipe;
1882
1883         if (de_iir & DE_ERR_INT_IVB)
1884                 ivb_err_int_handler(dev);
1885
1886         if (de_iir & DE_AUX_CHANNEL_A_IVB)
1887                 dp_aux_irq_handler(dev);
1888
1889         if (de_iir & DE_GSE_IVB)
1890                 intel_opregion_asle_intr(dev);
1891
1892         for_each_pipe(pipe) {
1893                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
1894                         drm_handle_vblank(dev, pipe);
1895
1896                 /* plane/pipes map 1:1 on ilk+ */
1897                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
1898                         intel_prepare_page_flip(dev, pipe);
1899                         intel_finish_page_flip_plane(dev, pipe);
1900                 }
1901         }
1902
1903         /* check event from PCH */
1904         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1905                 u32 pch_iir = I915_READ(SDEIIR);
1906
1907                 cpt_irq_handler(dev, pch_iir);
1908
1909                 /* clear PCH hotplug event before clear CPU irq */
1910                 I915_WRITE(SDEIIR, pch_iir);
1911         }
1912 }
1913
1914 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1915 {
1916         struct drm_device *dev = (struct drm_device *) arg;
1917         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1918         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1919         irqreturn_t ret = IRQ_NONE;
1920
1921         /* We get interrupts on unclaimed registers, so check for this before we
1922          * do any I915_{READ,WRITE}. */
1923         intel_uncore_check_errors(dev);
1924
1925         /* disable master interrupt before clearing iir  */
1926         de_ier = I915_READ(DEIER);
1927         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1928         POSTING_READ(DEIER);
1929
1930         /* Disable south interrupts. We'll only write to SDEIIR once, so further
1931          * interrupts will will be stored on its back queue, and then we'll be
1932          * able to process them after we restore SDEIER (as soon as we restore
1933          * it, we'll get an interrupt if SDEIIR still has something to process
1934          * due to its back queue). */
1935         if (!HAS_PCH_NOP(dev)) {
1936                 sde_ier = I915_READ(SDEIER);
1937                 I915_WRITE(SDEIER, 0);
1938                 POSTING_READ(SDEIER);
1939         }
1940
1941         gt_iir = I915_READ(GTIIR);
1942         if (gt_iir) {
1943                 if (INTEL_INFO(dev)->gen >= 6)
1944                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1945                 else
1946                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1947                 I915_WRITE(GTIIR, gt_iir);
1948                 ret = IRQ_HANDLED;
1949         }
1950
1951         de_iir = I915_READ(DEIIR);
1952         if (de_iir) {
1953                 if (INTEL_INFO(dev)->gen >= 7)
1954                         ivb_display_irq_handler(dev, de_iir);
1955                 else
1956                         ilk_display_irq_handler(dev, de_iir);
1957                 I915_WRITE(DEIIR, de_iir);
1958                 ret = IRQ_HANDLED;
1959         }
1960
1961         if (INTEL_INFO(dev)->gen >= 6) {
1962                 u32 pm_iir = I915_READ(GEN6_PMIIR);
1963                 if (pm_iir) {
1964                         gen6_rps_irq_handler(dev_priv, pm_iir);
1965                         I915_WRITE(GEN6_PMIIR, pm_iir);
1966                         ret = IRQ_HANDLED;
1967                 }
1968         }
1969
1970         I915_WRITE(DEIER, de_ier);
1971         POSTING_READ(DEIER);
1972         if (!HAS_PCH_NOP(dev)) {
1973                 I915_WRITE(SDEIER, sde_ier);
1974                 POSTING_READ(SDEIER);
1975         }
1976
1977         return ret;
1978 }
1979
1980 static irqreturn_t gen8_irq_handler(int irq, void *arg)
1981 {
1982         struct drm_device *dev = arg;
1983         struct drm_i915_private *dev_priv = dev->dev_private;
1984         u32 master_ctl;
1985         irqreturn_t ret = IRQ_NONE;
1986         uint32_t tmp = 0;
1987         enum pipe pipe;
1988
1989         master_ctl = I915_READ(GEN8_MASTER_IRQ);
1990         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
1991         if (!master_ctl)
1992                 return IRQ_NONE;
1993
1994         I915_WRITE(GEN8_MASTER_IRQ, 0);
1995         POSTING_READ(GEN8_MASTER_IRQ);
1996
1997         ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
1998
1999         if (master_ctl & GEN8_DE_MISC_IRQ) {
2000                 tmp = I915_READ(GEN8_DE_MISC_IIR);
2001                 if (tmp & GEN8_DE_MISC_GSE)
2002                         intel_opregion_asle_intr(dev);
2003                 else if (tmp)
2004                         DRM_ERROR("Unexpected DE Misc interrupt\n");
2005                 else
2006                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2007
2008                 if (tmp) {
2009                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2010                         ret = IRQ_HANDLED;
2011                 }
2012         }
2013
2014         if (master_ctl & GEN8_DE_PORT_IRQ) {
2015                 tmp = I915_READ(GEN8_DE_PORT_IIR);
2016                 if (tmp & GEN8_AUX_CHANNEL_A)
2017                         dp_aux_irq_handler(dev);
2018                 else if (tmp)
2019                         DRM_ERROR("Unexpected DE Port interrupt\n");
2020                 else
2021                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2022
2023                 if (tmp) {
2024                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2025                         ret = IRQ_HANDLED;
2026                 }
2027         }
2028
2029         for_each_pipe(pipe) {
2030                 uint32_t pipe_iir;
2031
2032                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2033                         continue;
2034
2035                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2036                 if (pipe_iir & GEN8_PIPE_VBLANK)
2037                         drm_handle_vblank(dev, pipe);
2038
2039                 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
2040                         intel_prepare_page_flip(dev, pipe);
2041                         intel_finish_page_flip_plane(dev, pipe);
2042                 }
2043
2044                 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2045                         hsw_pipe_crc_irq_handler(dev, pipe);
2046
2047                 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2048                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2049                                                                   false))
2050                                 DRM_ERROR("Pipe %c FIFO underrun\n",
2051                                           pipe_name(pipe));
2052                 }
2053
2054                 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2055                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2056                                   pipe_name(pipe),
2057                                   pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2058                 }
2059
2060                 if (pipe_iir) {
2061                         ret = IRQ_HANDLED;
2062                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2063                 } else
2064                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2065         }
2066
2067         if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2068                 /*
2069                  * FIXME(BDW): Assume for now that the new interrupt handling
2070                  * scheme also closed the SDE interrupt handling race we've seen
2071                  * on older pch-split platforms. But this needs testing.
2072                  */
2073                 u32 pch_iir = I915_READ(SDEIIR);
2074
2075                 cpt_irq_handler(dev, pch_iir);
2076
2077                 if (pch_iir) {
2078                         I915_WRITE(SDEIIR, pch_iir);
2079                         ret = IRQ_HANDLED;
2080                 }
2081         }
2082
2083         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2084         POSTING_READ(GEN8_MASTER_IRQ);
2085
2086         return ret;
2087 }
2088
2089 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2090                                bool reset_completed)
2091 {
2092         struct intel_ring_buffer *ring;
2093         int i;
2094
2095         /*
2096          * Notify all waiters for GPU completion events that reset state has
2097          * been changed, and that they need to restart their wait after
2098          * checking for potential errors (and bail out to drop locks if there is
2099          * a gpu reset pending so that i915_error_work_func can acquire them).
2100          */
2101
2102         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2103         for_each_ring(ring, dev_priv, i)
2104                 wake_up_all(&ring->irq_queue);
2105
2106         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2107         wake_up_all(&dev_priv->pending_flip_queue);
2108
2109         /*
2110          * Signal tasks blocked in i915_gem_wait_for_error that the pending
2111          * reset state is cleared.
2112          */
2113         if (reset_completed)
2114                 wake_up_all(&dev_priv->gpu_error.reset_queue);
2115 }
2116
2117 /**
2118  * i915_error_work_func - do process context error handling work
2119  * @work: work struct
2120  *
2121  * Fire an error uevent so userspace can see that a hang or error
2122  * was detected.
2123  */
2124 static void i915_error_work_func(struct work_struct *work)
2125 {
2126         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2127                                                     work);
2128         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
2129                                                     gpu_error);
2130         struct drm_device *dev = dev_priv->dev;
2131         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2132         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2133         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2134         int ret;
2135
2136         kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2137
2138         /*
2139          * Note that there's only one work item which does gpu resets, so we
2140          * need not worry about concurrent gpu resets potentially incrementing
2141          * error->reset_counter twice. We only need to take care of another
2142          * racing irq/hangcheck declaring the gpu dead for a second time. A
2143          * quick check for that is good enough: schedule_work ensures the
2144          * correct ordering between hang detection and this work item, and since
2145          * the reset in-progress bit is only ever set by code outside of this
2146          * work we don't need to worry about any other races.
2147          */
2148         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2149                 DRM_DEBUG_DRIVER("resetting chip\n");
2150                 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2151                                    reset_event);
2152
2153                 /*
2154                  * All state reset _must_ be completed before we update the
2155                  * reset counter, for otherwise waiters might miss the reset
2156                  * pending state and not properly drop locks, resulting in
2157                  * deadlocks with the reset work.
2158                  */
2159                 ret = i915_reset(dev);
2160
2161                 intel_display_handle_reset(dev);
2162
2163                 if (ret == 0) {
2164                         /*
2165                          * After all the gem state is reset, increment the reset
2166                          * counter and wake up everyone waiting for the reset to
2167                          * complete.
2168                          *
2169                          * Since unlock operations are a one-sided barrier only,
2170                          * we need to insert a barrier here to order any seqno
2171                          * updates before
2172                          * the counter increment.
2173                          */
2174                         smp_mb__before_atomic_inc();
2175                         atomic_inc(&dev_priv->gpu_error.reset_counter);
2176
2177                         kobject_uevent_env(&dev->primary->kdev->kobj,
2178                                            KOBJ_CHANGE, reset_done_event);
2179                 } else {
2180                         atomic_set_mask(I915_WEDGED, &error->reset_counter);
2181                 }
2182
2183                 /*
2184                  * Note: The wake_up also serves as a memory barrier so that
2185                  * waiters see the update value of the reset counter atomic_t.
2186                  */
2187                 i915_error_wake_up(dev_priv, true);
2188         }
2189 }
2190
2191 static void i915_report_and_clear_eir(struct drm_device *dev)
2192 {
2193         struct drm_i915_private *dev_priv = dev->dev_private;
2194         uint32_t instdone[I915_NUM_INSTDONE_REG];
2195         u32 eir = I915_READ(EIR);
2196         int pipe, i;
2197
2198         if (!eir)
2199                 return;
2200
2201         pr_err("render error detected, EIR: 0x%08x\n", eir);
2202
2203         i915_get_extra_instdone(dev, instdone);
2204
2205         if (IS_G4X(dev)) {
2206                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2207                         u32 ipeir = I915_READ(IPEIR_I965);
2208
2209                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2210                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2211                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2212                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2213                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2214                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2215                         I915_WRITE(IPEIR_I965, ipeir);
2216                         POSTING_READ(IPEIR_I965);
2217                 }
2218                 if (eir & GM45_ERROR_PAGE_TABLE) {
2219                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2220                         pr_err("page table error\n");
2221                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2222                         I915_WRITE(PGTBL_ER, pgtbl_err);
2223                         POSTING_READ(PGTBL_ER);
2224                 }
2225         }
2226
2227         if (!IS_GEN2(dev)) {
2228                 if (eir & I915_ERROR_PAGE_TABLE) {
2229                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2230                         pr_err("page table error\n");
2231                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2232                         I915_WRITE(PGTBL_ER, pgtbl_err);
2233                         POSTING_READ(PGTBL_ER);
2234                 }
2235         }
2236
2237         if (eir & I915_ERROR_MEMORY_REFRESH) {
2238                 pr_err("memory refresh error:\n");
2239                 for_each_pipe(pipe)
2240                         pr_err("pipe %c stat: 0x%08x\n",
2241                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2242                 /* pipestat has already been acked */
2243         }
2244         if (eir & I915_ERROR_INSTRUCTION) {
2245                 pr_err("instruction error\n");
2246                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2247                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2248                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2249                 if (INTEL_INFO(dev)->gen < 4) {
2250                         u32 ipeir = I915_READ(IPEIR);
2251
2252                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2253                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2254                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2255                         I915_WRITE(IPEIR, ipeir);
2256                         POSTING_READ(IPEIR);
2257                 } else {
2258                         u32 ipeir = I915_READ(IPEIR_I965);
2259
2260                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2261                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2262                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2263                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2264                         I915_WRITE(IPEIR_I965, ipeir);
2265                         POSTING_READ(IPEIR_I965);
2266                 }
2267         }
2268
2269         I915_WRITE(EIR, eir);
2270         POSTING_READ(EIR);
2271         eir = I915_READ(EIR);
2272         if (eir) {
2273                 /*
2274                  * some errors might have become stuck,
2275                  * mask them.
2276                  */
2277                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2278                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2279                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2280         }
2281 }
2282
2283 /**
2284  * i915_handle_error - handle an error interrupt
2285  * @dev: drm device
2286  *
2287  * Do some basic checking of regsiter state at error interrupt time and
2288  * dump it to the syslog.  Also call i915_capture_error_state() to make
2289  * sure we get a record and make it available in debugfs.  Fire a uevent
2290  * so userspace knows something bad happened (should trigger collection
2291  * of a ring dump etc.).
2292  */
2293 void i915_handle_error(struct drm_device *dev, bool wedged,
2294                        const char *fmt, ...)
2295 {
2296         struct drm_i915_private *dev_priv = dev->dev_private;
2297         va_list args;
2298         char error_msg[80];
2299
2300         va_start(args, fmt);
2301         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2302         va_end(args);
2303
2304         i915_capture_error_state(dev, wedged, error_msg);
2305         i915_report_and_clear_eir(dev);
2306
2307         if (wedged) {
2308                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2309                                 &dev_priv->gpu_error.reset_counter);
2310
2311                 /*
2312                  * Wakeup waiting processes so that the reset work function
2313                  * i915_error_work_func doesn't deadlock trying to grab various
2314                  * locks. By bumping the reset counter first, the woken
2315                  * processes will see a reset in progress and back off,
2316                  * releasing their locks and then wait for the reset completion.
2317                  * We must do this for _all_ gpu waiters that might hold locks
2318                  * that the reset work needs to acquire.
2319                  *
2320                  * Note: The wake_up serves as the required memory barrier to
2321                  * ensure that the waiters see the updated value of the reset
2322                  * counter atomic_t.
2323                  */
2324                 i915_error_wake_up(dev_priv, false);
2325         }
2326
2327         /*
2328          * Our reset work can grab modeset locks (since it needs to reset the
2329          * state of outstanding pagelips). Hence it must not be run on our own
2330          * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2331          * code will deadlock.
2332          */
2333         schedule_work(&dev_priv->gpu_error.work);
2334 }
2335
2336 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2337 {
2338         drm_i915_private_t *dev_priv = dev->dev_private;
2339         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2340         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2341         struct drm_i915_gem_object *obj;
2342         struct intel_unpin_work *work;
2343         unsigned long flags;
2344         bool stall_detected;
2345
2346         /* Ignore early vblank irqs */
2347         if (intel_crtc == NULL)
2348                 return;
2349
2350         spin_lock_irqsave(&dev->event_lock, flags);
2351         work = intel_crtc->unpin_work;
2352
2353         if (work == NULL ||
2354             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2355             !work->enable_stall_check) {
2356                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2357                 spin_unlock_irqrestore(&dev->event_lock, flags);
2358                 return;
2359         }
2360
2361         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2362         obj = work->pending_flip_obj;
2363         if (INTEL_INFO(dev)->gen >= 4) {
2364                 int dspsurf = DSPSURF(intel_crtc->plane);
2365                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2366                                         i915_gem_obj_ggtt_offset(obj);
2367         } else {
2368                 int dspaddr = DSPADDR(intel_crtc->plane);
2369                 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2370                                                         crtc->y * crtc->fb->pitches[0] +
2371                                                         crtc->x * crtc->fb->bits_per_pixel/8);
2372         }
2373
2374         spin_unlock_irqrestore(&dev->event_lock, flags);
2375
2376         if (stall_detected) {
2377                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2378                 intel_prepare_page_flip(dev, intel_crtc->plane);
2379         }
2380 }
2381
2382 /* Called from drm generic code, passed 'crtc' which
2383  * we use as a pipe index
2384  */
2385 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2386 {
2387         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2388         unsigned long irqflags;
2389
2390         if (!i915_pipe_enabled(dev, pipe))
2391                 return -EINVAL;
2392
2393         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2394         if (INTEL_INFO(dev)->gen >= 4)
2395                 i915_enable_pipestat(dev_priv, pipe,
2396                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2397         else
2398                 i915_enable_pipestat(dev_priv, pipe,
2399                                      PIPE_VBLANK_INTERRUPT_STATUS);
2400
2401         /* maintain vblank delivery even in deep C-states */
2402         if (INTEL_INFO(dev)->gen == 3)
2403                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2404         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2405
2406         return 0;
2407 }
2408
2409 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2410 {
2411         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2412         unsigned long irqflags;
2413         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2414                                                      DE_PIPE_VBLANK(pipe);
2415
2416         if (!i915_pipe_enabled(dev, pipe))
2417                 return -EINVAL;
2418
2419         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2420         ironlake_enable_display_irq(dev_priv, bit);
2421         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2422
2423         return 0;
2424 }
2425
2426 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2427 {
2428         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2429         unsigned long irqflags;
2430
2431         if (!i915_pipe_enabled(dev, pipe))
2432                 return -EINVAL;
2433
2434         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2435         i915_enable_pipestat(dev_priv, pipe,
2436                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2437         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2438
2439         return 0;
2440 }
2441
2442 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2443 {
2444         struct drm_i915_private *dev_priv = dev->dev_private;
2445         unsigned long irqflags;
2446
2447         if (!i915_pipe_enabled(dev, pipe))
2448                 return -EINVAL;
2449
2450         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2451         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2452         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2453         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2454         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2455         return 0;
2456 }
2457
2458 /* Called from drm generic code, passed 'crtc' which
2459  * we use as a pipe index
2460  */
2461 static void i915_disable_vblank(struct drm_device *dev, int pipe)
2462 {
2463         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2464         unsigned long irqflags;
2465
2466         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2467         if (INTEL_INFO(dev)->gen == 3)
2468                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2469
2470         i915_disable_pipestat(dev_priv, pipe,
2471                               PIPE_VBLANK_INTERRUPT_STATUS |
2472                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2473         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2474 }
2475
2476 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
2477 {
2478         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2479         unsigned long irqflags;
2480         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2481                                                      DE_PIPE_VBLANK(pipe);
2482
2483         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2484         ironlake_disable_display_irq(dev_priv, bit);
2485         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2486 }
2487
2488 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2489 {
2490         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2491         unsigned long irqflags;
2492
2493         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2494         i915_disable_pipestat(dev_priv, pipe,
2495                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2496         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2497 }
2498
2499 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2500 {
2501         struct drm_i915_private *dev_priv = dev->dev_private;
2502         unsigned long irqflags;
2503
2504         if (!i915_pipe_enabled(dev, pipe))
2505                 return;
2506
2507         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2508         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2509         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2510         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2511         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2512 }
2513
2514 static u32
2515 ring_last_seqno(struct intel_ring_buffer *ring)
2516 {
2517         return list_entry(ring->request_list.prev,
2518                           struct drm_i915_gem_request, list)->seqno;
2519 }
2520
2521 static bool
2522 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2523 {
2524         return (list_empty(&ring->request_list) ||
2525                 i915_seqno_passed(seqno, ring_last_seqno(ring)));
2526 }
2527
2528 static struct intel_ring_buffer *
2529 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
2530 {
2531         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2532         u32 cmd, ipehr, acthd, acthd_min;
2533
2534         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2535         if ((ipehr & ~(0x3 << 16)) !=
2536             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
2537                 return NULL;
2538
2539         /* ACTHD is likely pointing to the dword after the actual command,
2540          * so scan backwards until we find the MBOX.
2541          */
2542         acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
2543         acthd_min = max((int)acthd - 3 * 4, 0);
2544         do {
2545                 cmd = ioread32(ring->virtual_start + acthd);
2546                 if (cmd == ipehr)
2547                         break;
2548
2549                 acthd -= 4;
2550                 if (acthd < acthd_min)
2551                         return NULL;
2552         } while (1);
2553
2554         *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2555         return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
2556 }
2557
2558 static int semaphore_passed(struct intel_ring_buffer *ring)
2559 {
2560         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2561         struct intel_ring_buffer *signaller;
2562         u32 seqno, ctl;
2563
2564         ring->hangcheck.deadlock = true;
2565
2566         signaller = semaphore_waits_for(ring, &seqno);
2567         if (signaller == NULL || signaller->hangcheck.deadlock)
2568                 return -1;
2569
2570         /* cursory check for an unkickable deadlock */
2571         ctl = I915_READ_CTL(signaller);
2572         if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2573                 return -1;
2574
2575         return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2576 }
2577
2578 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2579 {
2580         struct intel_ring_buffer *ring;
2581         int i;
2582
2583         for_each_ring(ring, dev_priv, i)
2584                 ring->hangcheck.deadlock = false;
2585 }
2586
2587 static enum intel_ring_hangcheck_action
2588 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
2589 {
2590         struct drm_device *dev = ring->dev;
2591         struct drm_i915_private *dev_priv = dev->dev_private;
2592         u32 tmp;
2593
2594         if (ring->hangcheck.acthd != acthd)
2595                 return HANGCHECK_ACTIVE;
2596
2597         if (IS_GEN2(dev))
2598                 return HANGCHECK_HUNG;
2599
2600         /* Is the chip hanging on a WAIT_FOR_EVENT?
2601          * If so we can simply poke the RB_WAIT bit
2602          * and break the hang. This should work on
2603          * all but the second generation chipsets.
2604          */
2605         tmp = I915_READ_CTL(ring);
2606         if (tmp & RING_WAIT) {
2607                 i915_handle_error(dev, false,
2608                                   "Kicking stuck wait on %s",
2609                                   ring->name);
2610                 I915_WRITE_CTL(ring, tmp);
2611                 return HANGCHECK_KICK;
2612         }
2613
2614         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2615                 switch (semaphore_passed(ring)) {
2616                 default:
2617                         return HANGCHECK_HUNG;
2618                 case 1:
2619                         i915_handle_error(dev, false,
2620                                           "Kicking stuck semaphore on %s",
2621                                           ring->name);
2622                         I915_WRITE_CTL(ring, tmp);
2623                         return HANGCHECK_KICK;
2624                 case 0:
2625                         return HANGCHECK_WAIT;
2626                 }
2627         }
2628
2629         return HANGCHECK_HUNG;
2630 }
2631
2632 /**
2633  * This is called when the chip hasn't reported back with completed
2634  * batchbuffers in a long time. We keep track per ring seqno progress and
2635  * if there are no progress, hangcheck score for that ring is increased.
2636  * Further, acthd is inspected to see if the ring is stuck. On stuck case
2637  * we kick the ring. If we see no progress on three subsequent calls
2638  * we assume chip is wedged and try to fix it by resetting the chip.
2639  */
2640 static void i915_hangcheck_elapsed(unsigned long data)
2641 {
2642         struct drm_device *dev = (struct drm_device *)data;
2643         drm_i915_private_t *dev_priv = dev->dev_private;
2644         struct intel_ring_buffer *ring;
2645         int i;
2646         int busy_count = 0, rings_hung = 0;
2647         bool stuck[I915_NUM_RINGS] = { 0 };
2648 #define BUSY 1
2649 #define KICK 5
2650 #define HUNG 20
2651
2652         if (!i915.enable_hangcheck)
2653                 return;
2654
2655         for_each_ring(ring, dev_priv, i) {
2656                 u32 seqno, acthd;
2657                 bool busy = true;
2658
2659                 semaphore_clear_deadlocks(dev_priv);
2660
2661                 seqno = ring->get_seqno(ring, false);
2662                 acthd = intel_ring_get_active_head(ring);
2663
2664                 if (ring->hangcheck.seqno == seqno) {
2665                         if (ring_idle(ring, seqno)) {
2666                                 ring->hangcheck.action = HANGCHECK_IDLE;
2667
2668                                 if (waitqueue_active(&ring->irq_queue)) {
2669                                         /* Issue a wake-up to catch stuck h/w. */
2670                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2671                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2672                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2673                                                                   ring->name);
2674                                                 else
2675                                                         DRM_INFO("Fake missed irq on %s\n",
2676                                                                  ring->name);
2677                                                 wake_up_all(&ring->irq_queue);
2678                                         }
2679                                         /* Safeguard against driver failure */
2680                                         ring->hangcheck.score += BUSY;
2681                                 } else
2682                                         busy = false;
2683                         } else {
2684                                 /* We always increment the hangcheck score
2685                                  * if the ring is busy and still processing
2686                                  * the same request, so that no single request
2687                                  * can run indefinitely (such as a chain of
2688                                  * batches). The only time we do not increment
2689                                  * the hangcheck score on this ring, if this
2690                                  * ring is in a legitimate wait for another
2691                                  * ring. In that case the waiting ring is a
2692                                  * victim and we want to be sure we catch the
2693                                  * right culprit. Then every time we do kick
2694                                  * the ring, add a small increment to the
2695                                  * score so that we can catch a batch that is
2696                                  * being repeatedly kicked and so responsible
2697                                  * for stalling the machine.
2698                                  */
2699                                 ring->hangcheck.action = ring_stuck(ring,
2700                                                                     acthd);
2701
2702                                 switch (ring->hangcheck.action) {
2703                                 case HANGCHECK_IDLE:
2704                                 case HANGCHECK_WAIT:
2705                                         break;
2706                                 case HANGCHECK_ACTIVE:
2707                                         ring->hangcheck.score += BUSY;
2708                                         break;
2709                                 case HANGCHECK_KICK:
2710                                         ring->hangcheck.score += KICK;
2711                                         break;
2712                                 case HANGCHECK_HUNG:
2713                                         ring->hangcheck.score += HUNG;
2714                                         stuck[i] = true;
2715                                         break;
2716                                 }
2717                         }
2718                 } else {
2719                         ring->hangcheck.action = HANGCHECK_ACTIVE;
2720
2721                         /* Gradually reduce the count so that we catch DoS
2722                          * attempts across multiple batches.
2723                          */
2724                         if (ring->hangcheck.score > 0)
2725                                 ring->hangcheck.score--;
2726                 }
2727
2728                 ring->hangcheck.seqno = seqno;
2729                 ring->hangcheck.acthd = acthd;
2730                 busy_count += busy;
2731         }
2732
2733         for_each_ring(ring, dev_priv, i) {
2734                 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
2735                         DRM_INFO("%s on %s\n",
2736                                  stuck[i] ? "stuck" : "no progress",
2737                                  ring->name);
2738                         rings_hung++;
2739                 }
2740         }
2741
2742         if (rings_hung)
2743                 return i915_handle_error(dev, true, "Ring hung");
2744
2745         if (busy_count)
2746                 /* Reset timer case chip hangs without another request
2747                  * being added */
2748                 i915_queue_hangcheck(dev);
2749 }
2750
2751 void i915_queue_hangcheck(struct drm_device *dev)
2752 {
2753         struct drm_i915_private *dev_priv = dev->dev_private;
2754         if (!i915.enable_hangcheck)
2755                 return;
2756
2757         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2758                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2759 }
2760
2761 static void ibx_irq_preinstall(struct drm_device *dev)
2762 {
2763         struct drm_i915_private *dev_priv = dev->dev_private;
2764
2765         if (HAS_PCH_NOP(dev))
2766                 return;
2767
2768         /* south display irq */
2769         I915_WRITE(SDEIMR, 0xffffffff);
2770         /*
2771          * SDEIER is also touched by the interrupt handler to work around missed
2772          * PCH interrupts. Hence we can't update it after the interrupt handler
2773          * is enabled - instead we unconditionally enable all PCH interrupt
2774          * sources here, but then only unmask them as needed with SDEIMR.
2775          */
2776         I915_WRITE(SDEIER, 0xffffffff);
2777         POSTING_READ(SDEIER);
2778 }
2779
2780 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2781 {
2782         struct drm_i915_private *dev_priv = dev->dev_private;
2783
2784         /* and GT */
2785         I915_WRITE(GTIMR, 0xffffffff);
2786         I915_WRITE(GTIER, 0x0);
2787         POSTING_READ(GTIER);
2788
2789         if (INTEL_INFO(dev)->gen >= 6) {
2790                 /* and PM */
2791                 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2792                 I915_WRITE(GEN6_PMIER, 0x0);
2793                 POSTING_READ(GEN6_PMIER);
2794         }
2795 }
2796
2797 /* drm_dma.h hooks
2798 */
2799 static void ironlake_irq_preinstall(struct drm_device *dev)
2800 {
2801         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2802
2803         I915_WRITE(HWSTAM, 0xeffe);
2804
2805         I915_WRITE(DEIMR, 0xffffffff);
2806         I915_WRITE(DEIER, 0x0);
2807         POSTING_READ(DEIER);
2808
2809         gen5_gt_irq_preinstall(dev);
2810
2811         ibx_irq_preinstall(dev);
2812 }
2813
2814 static void valleyview_irq_preinstall(struct drm_device *dev)
2815 {
2816         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2817         int pipe;
2818
2819         /* VLV magic */
2820         I915_WRITE(VLV_IMR, 0);
2821         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2822         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2823         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2824
2825         /* and GT */
2826         I915_WRITE(GTIIR, I915_READ(GTIIR));
2827         I915_WRITE(GTIIR, I915_READ(GTIIR));
2828
2829         gen5_gt_irq_preinstall(dev);
2830
2831         I915_WRITE(DPINVGTT, 0xff);
2832
2833         I915_WRITE(PORT_HOTPLUG_EN, 0);
2834         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2835         for_each_pipe(pipe)
2836                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2837         I915_WRITE(VLV_IIR, 0xffffffff);
2838         I915_WRITE(VLV_IMR, 0xffffffff);
2839         I915_WRITE(VLV_IER, 0x0);
2840         POSTING_READ(VLV_IER);
2841 }
2842
2843 static void gen8_irq_preinstall(struct drm_device *dev)
2844 {
2845         struct drm_i915_private *dev_priv = dev->dev_private;
2846         int pipe;
2847
2848         I915_WRITE(GEN8_MASTER_IRQ, 0);
2849         POSTING_READ(GEN8_MASTER_IRQ);
2850
2851         /* IIR can theoretically queue up two events. Be paranoid */
2852 #define GEN8_IRQ_INIT_NDX(type, which) do { \
2853                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
2854                 POSTING_READ(GEN8_##type##_IMR(which)); \
2855                 I915_WRITE(GEN8_##type##_IER(which), 0); \
2856                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2857                 POSTING_READ(GEN8_##type##_IIR(which)); \
2858                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
2859         } while (0)
2860
2861 #define GEN8_IRQ_INIT(type) do { \
2862                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
2863                 POSTING_READ(GEN8_##type##_IMR); \
2864                 I915_WRITE(GEN8_##type##_IER, 0); \
2865                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2866                 POSTING_READ(GEN8_##type##_IIR); \
2867                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
2868         } while (0)
2869
2870         GEN8_IRQ_INIT_NDX(GT, 0);
2871         GEN8_IRQ_INIT_NDX(GT, 1);
2872         GEN8_IRQ_INIT_NDX(GT, 2);
2873         GEN8_IRQ_INIT_NDX(GT, 3);
2874
2875         for_each_pipe(pipe) {
2876                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe);
2877         }
2878
2879         GEN8_IRQ_INIT(DE_PORT);
2880         GEN8_IRQ_INIT(DE_MISC);
2881         GEN8_IRQ_INIT(PCU);
2882 #undef GEN8_IRQ_INIT
2883 #undef GEN8_IRQ_INIT_NDX
2884
2885         POSTING_READ(GEN8_PCU_IIR);
2886
2887         ibx_irq_preinstall(dev);
2888 }
2889
2890 static void ibx_hpd_irq_setup(struct drm_device *dev)
2891 {
2892         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2893         struct drm_mode_config *mode_config = &dev->mode_config;
2894         struct intel_encoder *intel_encoder;
2895         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2896
2897         if (HAS_PCH_IBX(dev)) {
2898                 hotplug_irqs = SDE_HOTPLUG_MASK;
2899                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2900                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2901                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2902         } else {
2903                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2904                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2905                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2906                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2907         }
2908
2909         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2910
2911         /*
2912          * Enable digital hotplug on the PCH, and configure the DP short pulse
2913          * duration to 2ms (which is the minimum in the Display Port spec)
2914          *
2915          * This register is the same on all known PCH chips.
2916          */
2917         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2918         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2919         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2920         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2921         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2922         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2923 }
2924
2925 static void ibx_irq_postinstall(struct drm_device *dev)
2926 {
2927         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2928         u32 mask;
2929
2930         if (HAS_PCH_NOP(dev))
2931                 return;
2932
2933         if (HAS_PCH_IBX(dev)) {
2934                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2935                        SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2936         } else {
2937                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2938
2939                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2940         }
2941
2942         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2943         I915_WRITE(SDEIMR, ~mask);
2944 }
2945
2946 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2947 {
2948         struct drm_i915_private *dev_priv = dev->dev_private;
2949         u32 pm_irqs, gt_irqs;
2950
2951         pm_irqs = gt_irqs = 0;
2952
2953         dev_priv->gt_irq_mask = ~0;
2954         if (HAS_L3_DPF(dev)) {
2955                 /* L3 parity interrupt is always unmasked. */
2956                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2957                 gt_irqs |= GT_PARITY_ERROR(dev);
2958         }
2959
2960         gt_irqs |= GT_RENDER_USER_INTERRUPT;
2961         if (IS_GEN5(dev)) {
2962                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2963                            ILK_BSD_USER_INTERRUPT;
2964         } else {
2965                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2966         }
2967
2968         I915_WRITE(GTIIR, I915_READ(GTIIR));
2969         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2970         I915_WRITE(GTIER, gt_irqs);
2971         POSTING_READ(GTIER);
2972
2973         if (INTEL_INFO(dev)->gen >= 6) {
2974                 pm_irqs |= GEN6_PM_RPS_EVENTS;
2975
2976                 if (HAS_VEBOX(dev))
2977                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2978
2979                 dev_priv->pm_irq_mask = 0xffffffff;
2980                 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2981                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2982                 I915_WRITE(GEN6_PMIER, pm_irqs);
2983                 POSTING_READ(GEN6_PMIER);
2984         }
2985 }
2986
2987 static int ironlake_irq_postinstall(struct drm_device *dev)
2988 {
2989         unsigned long irqflags;
2990         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2991         u32 display_mask, extra_mask;
2992
2993         if (INTEL_INFO(dev)->gen >= 7) {
2994                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2995                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2996                                 DE_PLANEB_FLIP_DONE_IVB |
2997                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2998                                 DE_ERR_INT_IVB);
2999                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3000                               DE_PIPEA_VBLANK_IVB);
3001
3002                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3003         } else {
3004                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3005                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3006                                 DE_AUX_CHANNEL_A |
3007                                 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3008                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3009                                 DE_POISON);
3010                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
3011         }
3012
3013         dev_priv->irq_mask = ~display_mask;
3014
3015         /* should always can generate irq */
3016         I915_WRITE(DEIIR, I915_READ(DEIIR));
3017         I915_WRITE(DEIMR, dev_priv->irq_mask);
3018         I915_WRITE(DEIER, display_mask | extra_mask);
3019         POSTING_READ(DEIER);
3020
3021         gen5_gt_irq_postinstall(dev);
3022
3023         ibx_irq_postinstall(dev);
3024
3025         if (IS_IRONLAKE_M(dev)) {
3026                 /* Enable PCU event interrupts
3027                  *
3028                  * spinlocking not required here for correctness since interrupt
3029                  * setup is guaranteed to run in single-threaded context. But we
3030                  * need it to make the assert_spin_locked happy. */
3031                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3032                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3033                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3034         }
3035
3036         return 0;
3037 }
3038
3039 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3040 {
3041         u32 pipestat_mask;
3042         u32 iir_mask;
3043
3044         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3045                         PIPE_FIFO_UNDERRUN_STATUS;
3046
3047         I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3048         I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3049         POSTING_READ(PIPESTAT(PIPE_A));
3050
3051         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3052                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3053
3054         i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3055                                                PIPE_GMBUS_INTERRUPT_STATUS);
3056         i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3057
3058         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3059                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3060                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3061         dev_priv->irq_mask &= ~iir_mask;
3062
3063         I915_WRITE(VLV_IIR, iir_mask);
3064         I915_WRITE(VLV_IIR, iir_mask);
3065         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3066         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3067         POSTING_READ(VLV_IER);
3068 }
3069
3070 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3071 {
3072         u32 pipestat_mask;
3073         u32 iir_mask;
3074
3075         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3076                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3077                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
3078
3079         dev_priv->irq_mask |= iir_mask;
3080         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3081         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3082         I915_WRITE(VLV_IIR, iir_mask);
3083         I915_WRITE(VLV_IIR, iir_mask);
3084         POSTING_READ(VLV_IIR);
3085
3086         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3087                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3088
3089         i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3090                                                 PIPE_GMBUS_INTERRUPT_STATUS);
3091         i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3092
3093         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3094                         PIPE_FIFO_UNDERRUN_STATUS;
3095         I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3096         I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3097         POSTING_READ(PIPESTAT(PIPE_A));
3098 }
3099
3100 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3101 {
3102         assert_spin_locked(&dev_priv->irq_lock);
3103
3104         if (dev_priv->display_irqs_enabled)
3105                 return;
3106
3107         dev_priv->display_irqs_enabled = true;
3108
3109         if (dev_priv->dev->irq_enabled)
3110                 valleyview_display_irqs_install(dev_priv);
3111 }
3112
3113 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3114 {
3115         assert_spin_locked(&dev_priv->irq_lock);
3116
3117         if (!dev_priv->display_irqs_enabled)
3118                 return;
3119
3120         dev_priv->display_irqs_enabled = false;
3121
3122         if (dev_priv->dev->irq_enabled)
3123                 valleyview_display_irqs_uninstall(dev_priv);
3124 }
3125
3126 static int valleyview_irq_postinstall(struct drm_device *dev)
3127 {
3128         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3129         unsigned long irqflags;
3130
3131         dev_priv->irq_mask = ~0;
3132
3133         I915_WRITE(PORT_HOTPLUG_EN, 0);
3134         POSTING_READ(PORT_HOTPLUG_EN);
3135
3136         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3137         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3138         I915_WRITE(VLV_IIR, 0xffffffff);
3139         POSTING_READ(VLV_IER);
3140
3141         /* Interrupt setup is already guaranteed to be single-threaded, this is
3142          * just to make the assert_spin_locked check happy. */
3143         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3144         if (dev_priv->display_irqs_enabled)
3145                 valleyview_display_irqs_install(dev_priv);
3146         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3147
3148         I915_WRITE(VLV_IIR, 0xffffffff);
3149         I915_WRITE(VLV_IIR, 0xffffffff);
3150
3151         gen5_gt_irq_postinstall(dev);
3152
3153         /* ack & enable invalid PTE error interrupts */
3154 #if 0 /* FIXME: add support to irq handler for checking these bits */
3155         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3156         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3157 #endif
3158
3159         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3160
3161         return 0;
3162 }
3163
3164 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3165 {
3166         int i;
3167
3168         /* These are interrupts we'll toggle with the ring mask register */
3169         uint32_t gt_interrupts[] = {
3170                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3171                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3172                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3173                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3174                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3175                 0,
3176                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3177                 };
3178
3179         for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) {
3180                 u32 tmp = I915_READ(GEN8_GT_IIR(i));
3181                 if (tmp)
3182                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
3183                                   i, tmp);
3184                 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]);
3185                 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]);
3186         }
3187         POSTING_READ(GEN8_GT_IER(0));
3188 }
3189
3190 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3191 {
3192         struct drm_device *dev = dev_priv->dev;
3193         uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
3194                 GEN8_PIPE_CDCLK_CRC_DONE |
3195                 GEN8_PIPE_FIFO_UNDERRUN |
3196                 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3197         uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK;
3198         int pipe;
3199         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3200         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3201         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3202
3203         for_each_pipe(pipe) {
3204                 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe));
3205                 if (tmp)
3206                         DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n",
3207                                   pipe, tmp);
3208                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
3209                 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables);
3210         }
3211         POSTING_READ(GEN8_DE_PIPE_ISR(0));
3212
3213         I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A);
3214         I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A);
3215         POSTING_READ(GEN8_DE_PORT_IER);
3216 }
3217
3218 static int gen8_irq_postinstall(struct drm_device *dev)
3219 {
3220         struct drm_i915_private *dev_priv = dev->dev_private;
3221
3222         gen8_gt_irq_postinstall(dev_priv);
3223         gen8_de_irq_postinstall(dev_priv);
3224
3225         ibx_irq_postinstall(dev);
3226
3227         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3228         POSTING_READ(GEN8_MASTER_IRQ);
3229
3230         return 0;
3231 }
3232
3233 static void gen8_irq_uninstall(struct drm_device *dev)
3234 {
3235         struct drm_i915_private *dev_priv = dev->dev_private;
3236         int pipe;
3237
3238         if (!dev_priv)
3239                 return;
3240
3241         I915_WRITE(GEN8_MASTER_IRQ, 0);
3242
3243 #define GEN8_IRQ_FINI_NDX(type, which) do { \
3244                 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
3245                 I915_WRITE(GEN8_##type##_IER(which), 0); \
3246                 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
3247         } while (0)
3248
3249 #define GEN8_IRQ_FINI(type) do { \
3250                 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \
3251                 I915_WRITE(GEN8_##type##_IER, 0); \
3252                 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \
3253         } while (0)
3254
3255         GEN8_IRQ_FINI_NDX(GT, 0);
3256         GEN8_IRQ_FINI_NDX(GT, 1);
3257         GEN8_IRQ_FINI_NDX(GT, 2);
3258         GEN8_IRQ_FINI_NDX(GT, 3);
3259
3260         for_each_pipe(pipe) {
3261                 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe);
3262         }
3263
3264         GEN8_IRQ_FINI(DE_PORT);
3265         GEN8_IRQ_FINI(DE_MISC);
3266         GEN8_IRQ_FINI(PCU);
3267 #undef GEN8_IRQ_FINI
3268 #undef GEN8_IRQ_FINI_NDX
3269
3270         POSTING_READ(GEN8_PCU_IIR);
3271 }
3272
3273 static void valleyview_irq_uninstall(struct drm_device *dev)
3274 {
3275         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3276         unsigned long irqflags;
3277         int pipe;
3278
3279         if (!dev_priv)
3280                 return;
3281
3282         intel_hpd_irq_uninstall(dev_priv);
3283
3284         for_each_pipe(pipe)
3285                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3286
3287         I915_WRITE(HWSTAM, 0xffffffff);
3288         I915_WRITE(PORT_HOTPLUG_EN, 0);
3289         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3290
3291         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3292         if (dev_priv->display_irqs_enabled)
3293                 valleyview_display_irqs_uninstall(dev_priv);
3294         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3295
3296         dev_priv->irq_mask = 0;
3297
3298         I915_WRITE(VLV_IIR, 0xffffffff);
3299         I915_WRITE(VLV_IMR, 0xffffffff);
3300         I915_WRITE(VLV_IER, 0x0);
3301         POSTING_READ(VLV_IER);
3302 }
3303
3304 static void ironlake_irq_uninstall(struct drm_device *dev)
3305 {
3306         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3307
3308         if (!dev_priv)
3309                 return;
3310
3311         intel_hpd_irq_uninstall(dev_priv);
3312
3313         I915_WRITE(HWSTAM, 0xffffffff);
3314
3315         I915_WRITE(DEIMR, 0xffffffff);
3316         I915_WRITE(DEIER, 0x0);
3317         I915_WRITE(DEIIR, I915_READ(DEIIR));
3318         if (IS_GEN7(dev))
3319                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
3320
3321         I915_WRITE(GTIMR, 0xffffffff);
3322         I915_WRITE(GTIER, 0x0);
3323         I915_WRITE(GTIIR, I915_READ(GTIIR));
3324
3325         if (HAS_PCH_NOP(dev))
3326                 return;
3327
3328         I915_WRITE(SDEIMR, 0xffffffff);
3329         I915_WRITE(SDEIER, 0x0);
3330         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
3331         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3332                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
3333 }
3334
3335 static void i8xx_irq_preinstall(struct drm_device * dev)
3336 {
3337         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3338         int pipe;
3339
3340         for_each_pipe(pipe)
3341                 I915_WRITE(PIPESTAT(pipe), 0);
3342         I915_WRITE16(IMR, 0xffff);
3343         I915_WRITE16(IER, 0x0);
3344         POSTING_READ16(IER);
3345 }
3346
3347 static int i8xx_irq_postinstall(struct drm_device *dev)
3348 {
3349         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3350         unsigned long irqflags;
3351
3352         I915_WRITE16(EMR,
3353                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3354
3355         /* Unmask the interrupts that we always want on. */
3356         dev_priv->irq_mask =
3357                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3358                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3359                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3360                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3361                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3362         I915_WRITE16(IMR, dev_priv->irq_mask);
3363
3364         I915_WRITE16(IER,
3365                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3366                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3367                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3368                      I915_USER_INTERRUPT);
3369         POSTING_READ16(IER);
3370
3371         /* Interrupt setup is already guaranteed to be single-threaded, this is
3372          * just to make the assert_spin_locked check happy. */
3373         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3374         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3375         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3376         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3377
3378         return 0;
3379 }
3380
3381 /*
3382  * Returns true when a page flip has completed.
3383  */
3384 static bool i8xx_handle_vblank(struct drm_device *dev,
3385                                int plane, int pipe, u32 iir)
3386 {
3387         drm_i915_private_t *dev_priv = dev->dev_private;
3388         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3389
3390         if (!drm_handle_vblank(dev, pipe))
3391                 return false;
3392
3393         if ((iir & flip_pending) == 0)
3394                 return false;
3395
3396         intel_prepare_page_flip(dev, plane);
3397
3398         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3399          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3400          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3401          * the flip is completed (no longer pending). Since this doesn't raise
3402          * an interrupt per se, we watch for the change at vblank.
3403          */
3404         if (I915_READ16(ISR) & flip_pending)
3405                 return false;
3406
3407         intel_finish_page_flip(dev, pipe);
3408
3409         return true;
3410 }
3411
3412 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3413 {
3414         struct drm_device *dev = (struct drm_device *) arg;
3415         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3416         u16 iir, new_iir;
3417         u32 pipe_stats[2];
3418         unsigned long irqflags;
3419         int pipe;
3420         u16 flip_mask =
3421                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3422                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3423
3424         iir = I915_READ16(IIR);
3425         if (iir == 0)
3426                 return IRQ_NONE;
3427
3428         while (iir & ~flip_mask) {
3429                 /* Can't rely on pipestat interrupt bit in iir as it might
3430                  * have been cleared after the pipestat interrupt was received.
3431                  * It doesn't set the bit in iir again, but it still produces
3432                  * interrupts (for non-MSI).
3433                  */
3434                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3435                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3436                         i915_handle_error(dev, false,
3437                                           "Command parser error, iir 0x%08x",
3438                                           iir);
3439
3440                 for_each_pipe(pipe) {
3441                         int reg = PIPESTAT(pipe);
3442                         pipe_stats[pipe] = I915_READ(reg);
3443
3444                         /*
3445                          * Clear the PIPE*STAT regs before the IIR
3446                          */
3447                         if (pipe_stats[pipe] & 0x8000ffff)
3448                                 I915_WRITE(reg, pipe_stats[pipe]);
3449                 }
3450                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3451
3452                 I915_WRITE16(IIR, iir & ~flip_mask);
3453                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3454
3455                 i915_update_dri1_breadcrumb(dev);
3456
3457                 if (iir & I915_USER_INTERRUPT)
3458                         notify_ring(dev, &dev_priv->ring[RCS]);
3459
3460                 for_each_pipe(pipe) {
3461                         int plane = pipe;
3462                         if (HAS_FBC(dev))
3463                                 plane = !plane;
3464
3465                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3466                             i8xx_handle_vblank(dev, plane, pipe, iir))
3467                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3468
3469                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3470                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3471
3472                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3473                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3474                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3475                 }
3476
3477                 iir = new_iir;
3478         }
3479
3480         return IRQ_HANDLED;
3481 }
3482
3483 static void i8xx_irq_uninstall(struct drm_device * dev)
3484 {
3485         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3486         int pipe;
3487
3488         for_each_pipe(pipe) {
3489                 /* Clear enable bits; then clear status bits */
3490                 I915_WRITE(PIPESTAT(pipe), 0);
3491                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3492         }
3493         I915_WRITE16(IMR, 0xffff);
3494         I915_WRITE16(IER, 0x0);
3495         I915_WRITE16(IIR, I915_READ16(IIR));
3496 }
3497
3498 static void i915_irq_preinstall(struct drm_device * dev)
3499 {
3500         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3501         int pipe;
3502
3503         if (I915_HAS_HOTPLUG(dev)) {
3504                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3505                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3506         }
3507
3508         I915_WRITE16(HWSTAM, 0xeffe);
3509         for_each_pipe(pipe)
3510                 I915_WRITE(PIPESTAT(pipe), 0);
3511         I915_WRITE(IMR, 0xffffffff);
3512         I915_WRITE(IER, 0x0);
3513         POSTING_READ(IER);
3514 }
3515
3516 static int i915_irq_postinstall(struct drm_device *dev)
3517 {
3518         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3519         u32 enable_mask;
3520         unsigned long irqflags;
3521
3522         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3523
3524         /* Unmask the interrupts that we always want on. */
3525         dev_priv->irq_mask =
3526                 ~(I915_ASLE_INTERRUPT |
3527                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3528                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3529                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3530                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3531                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3532
3533         enable_mask =
3534                 I915_ASLE_INTERRUPT |
3535                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3536                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3537                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3538                 I915_USER_INTERRUPT;
3539
3540         if (I915_HAS_HOTPLUG(dev)) {
3541                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3542                 POSTING_READ(PORT_HOTPLUG_EN);
3543
3544                 /* Enable in IER... */
3545                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3546                 /* and unmask in IMR */
3547                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3548         }
3549
3550         I915_WRITE(IMR, dev_priv->irq_mask);
3551         I915_WRITE(IER, enable_mask);
3552         POSTING_READ(IER);
3553
3554         i915_enable_asle_pipestat(dev);
3555
3556         /* Interrupt setup is already guaranteed to be single-threaded, this is
3557          * just to make the assert_spin_locked check happy. */
3558         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3559         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3560         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3561         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3562
3563         return 0;
3564 }
3565
3566 /*
3567  * Returns true when a page flip has completed.
3568  */
3569 static bool i915_handle_vblank(struct drm_device *dev,
3570                                int plane, int pipe, u32 iir)
3571 {
3572         drm_i915_private_t *dev_priv = dev->dev_private;
3573         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3574
3575         if (!drm_handle_vblank(dev, pipe))
3576                 return false;
3577
3578         if ((iir & flip_pending) == 0)
3579                 return false;
3580
3581         intel_prepare_page_flip(dev, plane);
3582
3583         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3584          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3585          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3586          * the flip is completed (no longer pending). Since this doesn't raise
3587          * an interrupt per se, we watch for the change at vblank.
3588          */
3589         if (I915_READ(ISR) & flip_pending)
3590                 return false;
3591
3592         intel_finish_page_flip(dev, pipe);
3593
3594         return true;
3595 }
3596
3597 static irqreturn_t i915_irq_handler(int irq, void *arg)
3598 {
3599         struct drm_device *dev = (struct drm_device *) arg;
3600         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3601         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3602         unsigned long irqflags;
3603         u32 flip_mask =
3604                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3605                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3606         int pipe, ret = IRQ_NONE;
3607
3608         iir = I915_READ(IIR);
3609         do {
3610                 bool irq_received = (iir & ~flip_mask) != 0;
3611                 bool blc_event = false;
3612
3613                 /* Can't rely on pipestat interrupt bit in iir as it might
3614                  * have been cleared after the pipestat interrupt was received.
3615                  * It doesn't set the bit in iir again, but it still produces
3616                  * interrupts (for non-MSI).
3617                  */
3618                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3619                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3620                         i915_handle_error(dev, false,
3621                                           "Command parser error, iir 0x%08x",
3622                                           iir);
3623
3624                 for_each_pipe(pipe) {
3625                         int reg = PIPESTAT(pipe);
3626                         pipe_stats[pipe] = I915_READ(reg);
3627
3628                         /* Clear the PIPE*STAT regs before the IIR */
3629                         if (pipe_stats[pipe] & 0x8000ffff) {
3630                                 I915_WRITE(reg, pipe_stats[pipe]);
3631                                 irq_received = true;
3632                         }
3633                 }
3634                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3635
3636                 if (!irq_received)
3637                         break;
3638
3639                 /* Consume port.  Then clear IIR or we'll miss events */
3640                 if ((I915_HAS_HOTPLUG(dev)) &&
3641                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3642                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3643                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
3644
3645                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3646
3647                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3648                         POSTING_READ(PORT_HOTPLUG_STAT);
3649                 }
3650
3651                 I915_WRITE(IIR, iir & ~flip_mask);
3652                 new_iir = I915_READ(IIR); /* Flush posted writes */
3653
3654                 if (iir & I915_USER_INTERRUPT)
3655                         notify_ring(dev, &dev_priv->ring[RCS]);
3656
3657                 for_each_pipe(pipe) {
3658                         int plane = pipe;
3659                         if (HAS_FBC(dev))
3660                                 plane = !plane;
3661
3662                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3663                             i915_handle_vblank(dev, plane, pipe, iir))
3664                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3665
3666                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3667                                 blc_event = true;
3668
3669                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3670                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3671
3672                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3673                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3674                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3675                 }
3676
3677                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3678                         intel_opregion_asle_intr(dev);
3679
3680                 /* With MSI, interrupts are only generated when iir
3681                  * transitions from zero to nonzero.  If another bit got
3682                  * set while we were handling the existing iir bits, then
3683                  * we would never get another interrupt.
3684                  *
3685                  * This is fine on non-MSI as well, as if we hit this path
3686                  * we avoid exiting the interrupt handler only to generate
3687                  * another one.
3688                  *
3689                  * Note that for MSI this could cause a stray interrupt report
3690                  * if an interrupt landed in the time between writing IIR and
3691                  * the posting read.  This should be rare enough to never
3692                  * trigger the 99% of 100,000 interrupts test for disabling
3693                  * stray interrupts.
3694                  */
3695                 ret = IRQ_HANDLED;
3696                 iir = new_iir;
3697         } while (iir & ~flip_mask);
3698
3699         i915_update_dri1_breadcrumb(dev);
3700
3701         return ret;
3702 }
3703
3704 static void i915_irq_uninstall(struct drm_device * dev)
3705 {
3706         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3707         int pipe;
3708
3709         intel_hpd_irq_uninstall(dev_priv);
3710
3711         if (I915_HAS_HOTPLUG(dev)) {
3712                 I915_WRITE(PORT_HOTPLUG_EN, 0);
3713                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3714         }
3715
3716         I915_WRITE16(HWSTAM, 0xffff);
3717         for_each_pipe(pipe) {
3718                 /* Clear enable bits; then clear status bits */
3719                 I915_WRITE(PIPESTAT(pipe), 0);
3720                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3721         }
3722         I915_WRITE(IMR, 0xffffffff);
3723         I915_WRITE(IER, 0x0);
3724
3725         I915_WRITE(IIR, I915_READ(IIR));
3726 }
3727
3728 static void i965_irq_preinstall(struct drm_device * dev)
3729 {
3730         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3731         int pipe;
3732
3733         I915_WRITE(PORT_HOTPLUG_EN, 0);
3734         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3735
3736         I915_WRITE(HWSTAM, 0xeffe);
3737         for_each_pipe(pipe)
3738                 I915_WRITE(PIPESTAT(pipe), 0);
3739         I915_WRITE(IMR, 0xffffffff);
3740         I915_WRITE(IER, 0x0);
3741         POSTING_READ(IER);
3742 }
3743
3744 static int i965_irq_postinstall(struct drm_device *dev)
3745 {
3746         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3747         u32 enable_mask;
3748         u32 error_mask;
3749         unsigned long irqflags;
3750
3751         /* Unmask the interrupts that we always want on. */
3752         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
3753                                I915_DISPLAY_PORT_INTERRUPT |
3754                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3755                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3756                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3757                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3758                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3759
3760         enable_mask = ~dev_priv->irq_mask;
3761         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3762                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3763         enable_mask |= I915_USER_INTERRUPT;
3764
3765         if (IS_G4X(dev))
3766                 enable_mask |= I915_BSD_USER_INTERRUPT;
3767
3768         /* Interrupt setup is already guaranteed to be single-threaded, this is
3769          * just to make the assert_spin_locked check happy. */
3770         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3771         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3772         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3773         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3774         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3775
3776         /*
3777          * Enable some error detection, note the instruction error mask
3778          * bit is reserved, so we leave it masked.
3779          */
3780         if (IS_G4X(dev)) {
3781                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3782                                GM45_ERROR_MEM_PRIV |
3783                                GM45_ERROR_CP_PRIV |
3784                                I915_ERROR_MEMORY_REFRESH);
3785         } else {
3786                 error_mask = ~(I915_ERROR_PAGE_TABLE |
3787                                I915_ERROR_MEMORY_REFRESH);
3788         }
3789         I915_WRITE(EMR, error_mask);
3790
3791         I915_WRITE(IMR, dev_priv->irq_mask);
3792         I915_WRITE(IER, enable_mask);
3793         POSTING_READ(IER);
3794
3795         I915_WRITE(PORT_HOTPLUG_EN, 0);
3796         POSTING_READ(PORT_HOTPLUG_EN);
3797
3798         i915_enable_asle_pipestat(dev);
3799
3800         return 0;
3801 }
3802
3803 static void i915_hpd_irq_setup(struct drm_device *dev)
3804 {
3805         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3806         struct drm_mode_config *mode_config = &dev->mode_config;
3807         struct intel_encoder *intel_encoder;
3808         u32 hotplug_en;
3809
3810         assert_spin_locked(&dev_priv->irq_lock);
3811
3812         if (I915_HAS_HOTPLUG(dev)) {
3813                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3814                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3815                 /* Note HDMI and DP share hotplug bits */
3816                 /* enable bits are the same for all generations */
3817                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3818                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3819                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
3820                 /* Programming the CRT detection parameters tends
3821                    to generate a spurious hotplug event about three
3822                    seconds later.  So just do it once.
3823                 */
3824                 if (IS_G4X(dev))
3825                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3826                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
3827                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3828
3829                 /* Ignore TV since it's buggy */
3830                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3831         }
3832 }
3833
3834 static irqreturn_t i965_irq_handler(int irq, void *arg)
3835 {
3836         struct drm_device *dev = (struct drm_device *) arg;
3837         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3838         u32 iir, new_iir;
3839         u32 pipe_stats[I915_MAX_PIPES];
3840         unsigned long irqflags;
3841         int ret = IRQ_NONE, pipe;
3842         u32 flip_mask =
3843                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3844                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3845
3846         iir = I915_READ(IIR);
3847
3848         for (;;) {
3849                 bool irq_received = (iir & ~flip_mask) != 0;
3850                 bool blc_event = false;
3851
3852                 /* Can't rely on pipestat interrupt bit in iir as it might
3853                  * have been cleared after the pipestat interrupt was received.
3854                  * It doesn't set the bit in iir again, but it still produces
3855                  * interrupts (for non-MSI).
3856                  */
3857                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3858                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3859                         i915_handle_error(dev, false,
3860                                           "Command parser error, iir 0x%08x",
3861                                           iir);
3862
3863                 for_each_pipe(pipe) {
3864                         int reg = PIPESTAT(pipe);
3865                         pipe_stats[pipe] = I915_READ(reg);
3866
3867                         /*
3868                          * Clear the PIPE*STAT regs before the IIR
3869                          */
3870                         if (pipe_stats[pipe] & 0x8000ffff) {
3871                                 I915_WRITE(reg, pipe_stats[pipe]);
3872                                 irq_received = true;
3873                         }
3874                 }
3875                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3876
3877                 if (!irq_received)
3878                         break;
3879
3880                 ret = IRQ_HANDLED;
3881
3882                 /* Consume port.  Then clear IIR or we'll miss events */
3883                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3884                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3885                         u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3886                                                                   HOTPLUG_INT_STATUS_G4X :
3887                                                                   HOTPLUG_INT_STATUS_I915);
3888
3889                         intel_hpd_irq_handler(dev, hotplug_trigger,
3890                                               IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915);
3891
3892                         if (IS_G4X(dev) &&
3893                             (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3894                                 dp_aux_irq_handler(dev);
3895
3896                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3897                         I915_READ(PORT_HOTPLUG_STAT);
3898                 }
3899
3900                 I915_WRITE(IIR, iir & ~flip_mask);
3901                 new_iir = I915_READ(IIR); /* Flush posted writes */
3902
3903                 if (iir & I915_USER_INTERRUPT)
3904                         notify_ring(dev, &dev_priv->ring[RCS]);
3905                 if (iir & I915_BSD_USER_INTERRUPT)
3906                         notify_ring(dev, &dev_priv->ring[VCS]);
3907
3908                 for_each_pipe(pipe) {
3909                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3910                             i915_handle_vblank(dev, pipe, pipe, iir))
3911                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3912
3913                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3914                                 blc_event = true;
3915
3916                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3917                                 i9xx_pipe_crc_irq_handler(dev, pipe);
3918
3919                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3920                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
3921                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
3922                 }
3923
3924                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3925                         intel_opregion_asle_intr(dev);
3926
3927                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3928                         gmbus_irq_handler(dev);
3929
3930                 /* With MSI, interrupts are only generated when iir
3931                  * transitions from zero to nonzero.  If another bit got
3932                  * set while we were handling the existing iir bits, then
3933                  * we would never get another interrupt.
3934                  *
3935                  * This is fine on non-MSI as well, as if we hit this path
3936                  * we avoid exiting the interrupt handler only to generate
3937                  * another one.
3938                  *
3939                  * Note that for MSI this could cause a stray interrupt report
3940                  * if an interrupt landed in the time between writing IIR and
3941                  * the posting read.  This should be rare enough to never
3942                  * trigger the 99% of 100,000 interrupts test for disabling
3943                  * stray interrupts.
3944                  */
3945                 iir = new_iir;
3946         }
3947
3948         i915_update_dri1_breadcrumb(dev);
3949
3950         return ret;
3951 }
3952
3953 static void i965_irq_uninstall(struct drm_device * dev)
3954 {
3955         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3956         int pipe;
3957
3958         if (!dev_priv)
3959                 return;
3960
3961         intel_hpd_irq_uninstall(dev_priv);
3962
3963         I915_WRITE(PORT_HOTPLUG_EN, 0);
3964         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3965
3966         I915_WRITE(HWSTAM, 0xffffffff);
3967         for_each_pipe(pipe)
3968                 I915_WRITE(PIPESTAT(pipe), 0);
3969         I915_WRITE(IMR, 0xffffffff);
3970         I915_WRITE(IER, 0x0);
3971
3972         for_each_pipe(pipe)
3973                 I915_WRITE(PIPESTAT(pipe),
3974                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3975         I915_WRITE(IIR, I915_READ(IIR));
3976 }
3977
3978 static void intel_hpd_irq_reenable(unsigned long data)
3979 {
3980         drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3981         struct drm_device *dev = dev_priv->dev;
3982         struct drm_mode_config *mode_config = &dev->mode_config;
3983         unsigned long irqflags;
3984         int i;
3985
3986         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3987         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3988                 struct drm_connector *connector;
3989
3990                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3991                         continue;
3992
3993                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3994
3995                 list_for_each_entry(connector, &mode_config->connector_list, head) {
3996                         struct intel_connector *intel_connector = to_intel_connector(connector);
3997
3998                         if (intel_connector->encoder->hpd_pin == i) {
3999                                 if (connector->polled != intel_connector->polled)
4000                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4001                                                          drm_get_connector_name(connector));
4002                                 connector->polled = intel_connector->polled;
4003                                 if (!connector->polled)
4004                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4005                         }
4006                 }
4007         }
4008         if (dev_priv->display.hpd_irq_setup)
4009                 dev_priv->display.hpd_irq_setup(dev);
4010         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4011 }
4012
4013 void intel_irq_init(struct drm_device *dev)
4014 {
4015         struct drm_i915_private *dev_priv = dev->dev_private;
4016
4017         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4018         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4019         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4020         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4021
4022         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4023                     i915_hangcheck_elapsed,
4024                     (unsigned long) dev);
4025         setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
4026                     (unsigned long) dev_priv);
4027
4028         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4029
4030         if (IS_GEN2(dev)) {
4031                 dev->max_vblank_count = 0;
4032                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4033         } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4034                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4035                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4036         } else {
4037                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4038                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4039         }
4040
4041         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4042                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4043                 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4044         }
4045
4046         if (IS_VALLEYVIEW(dev)) {
4047                 dev->driver->irq_handler = valleyview_irq_handler;
4048                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4049                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4050                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4051                 dev->driver->enable_vblank = valleyview_enable_vblank;
4052                 dev->driver->disable_vblank = valleyview_disable_vblank;
4053                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4054         } else if (IS_GEN8(dev)) {
4055                 dev->driver->irq_handler = gen8_irq_handler;
4056                 dev->driver->irq_preinstall = gen8_irq_preinstall;
4057                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4058                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4059                 dev->driver->enable_vblank = gen8_enable_vblank;
4060                 dev->driver->disable_vblank = gen8_disable_vblank;
4061                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4062         } else if (HAS_PCH_SPLIT(dev)) {
4063                 dev->driver->irq_handler = ironlake_irq_handler;
4064                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
4065                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4066                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4067                 dev->driver->enable_vblank = ironlake_enable_vblank;
4068                 dev->driver->disable_vblank = ironlake_disable_vblank;
4069                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4070         } else {
4071                 if (INTEL_INFO(dev)->gen == 2) {
4072                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4073                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4074                         dev->driver->irq_handler = i8xx_irq_handler;
4075                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4076                 } else if (INTEL_INFO(dev)->gen == 3) {
4077                         dev->driver->irq_preinstall = i915_irq_preinstall;
4078                         dev->driver->irq_postinstall = i915_irq_postinstall;
4079                         dev->driver->irq_uninstall = i915_irq_uninstall;
4080                         dev->driver->irq_handler = i915_irq_handler;
4081                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4082                 } else {
4083                         dev->driver->irq_preinstall = i965_irq_preinstall;
4084                         dev->driver->irq_postinstall = i965_irq_postinstall;
4085                         dev->driver->irq_uninstall = i965_irq_uninstall;
4086                         dev->driver->irq_handler = i965_irq_handler;
4087                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4088                 }
4089                 dev->driver->enable_vblank = i915_enable_vblank;
4090                 dev->driver->disable_vblank = i915_disable_vblank;
4091         }
4092 }
4093
4094 void intel_hpd_init(struct drm_device *dev)
4095 {
4096         struct drm_i915_private *dev_priv = dev->dev_private;
4097         struct drm_mode_config *mode_config = &dev->mode_config;
4098         struct drm_connector *connector;
4099         unsigned long irqflags;
4100         int i;
4101
4102         for (i = 1; i < HPD_NUM_PINS; i++) {
4103                 dev_priv->hpd_stats[i].hpd_cnt = 0;
4104                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4105         }
4106         list_for_each_entry(connector, &mode_config->connector_list, head) {
4107                 struct intel_connector *intel_connector = to_intel_connector(connector);
4108                 connector->polled = intel_connector->polled;
4109                 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4110                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4111         }
4112
4113         /* Interrupt setup is already guaranteed to be single-threaded, this is
4114          * just to make the assert_spin_locked checks happy. */
4115         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4116         if (dev_priv->display.hpd_irq_setup)
4117                 dev_priv->display.hpd_irq_setup(dev);
4118         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4119 }
4120
4121 /* Disable interrupts so we can allow Package C8+. */
4122 void hsw_pc8_disable_interrupts(struct drm_device *dev)
4123 {
4124         struct drm_i915_private *dev_priv = dev->dev_private;
4125         unsigned long irqflags;
4126
4127         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4128
4129         dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
4130         dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
4131         dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
4132         dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
4133         dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
4134
4135         ironlake_disable_display_irq(dev_priv, 0xffffffff);
4136         ibx_disable_display_interrupt(dev_priv, 0xffffffff);
4137         ilk_disable_gt_irq(dev_priv, 0xffffffff);
4138         snb_disable_pm_irq(dev_priv, 0xffffffff);
4139
4140         dev_priv->pc8.irqs_disabled = true;
4141
4142         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4143 }
4144
4145 /* Restore interrupts so we can recover from Package C8+. */
4146 void hsw_pc8_restore_interrupts(struct drm_device *dev)
4147 {
4148         struct drm_i915_private *dev_priv = dev->dev_private;
4149         unsigned long irqflags;
4150         uint32_t val;
4151
4152         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4153
4154         val = I915_READ(DEIMR);
4155         WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
4156
4157         val = I915_READ(SDEIMR);
4158         WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
4159
4160         val = I915_READ(GTIMR);
4161         WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
4162
4163         val = I915_READ(GEN6_PMIMR);
4164         WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
4165
4166         dev_priv->pc8.irqs_disabled = false;
4167
4168         ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
4169         ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr);
4170         ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
4171         snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
4172         I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
4173
4174         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4175 }