1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <drm/drm_auth.h>
52 #include "i915_params.h"
55 #include "intel_bios.h"
56 #include "intel_dpll_mgr.h"
57 #include "intel_guc.h"
58 #include "intel_lrc.h"
59 #include "intel_ringbuffer.h"
62 #include "i915_gem_gtt.h"
63 #include "i915_gem_render_state.h"
65 #include "intel_gvt.h"
67 /* General customization:
70 #define DRIVER_NAME "i915"
71 #define DRIVER_DESC "Intel Graphics"
72 #define DRIVER_DATE "20160711"
75 /* Many gcc seem to no see through this and fall over :( */
77 #define WARN_ON(x) ({ \
78 bool __i915_warn_cond = (x); \
79 if (__builtin_constant_p(__i915_warn_cond)) \
80 BUILD_BUG_ON(__i915_warn_cond); \
81 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
83 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
87 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
89 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
90 (long) (x), __func__);
92 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
93 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
94 * which may not necessarily be a user visible problem. This will either
95 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
96 * enable distros and users to tailor their preferred amount of i915 abrt
99 #define I915_STATE_WARN(condition, format...) ({ \
100 int __ret_warn_on = !!(condition); \
101 if (unlikely(__ret_warn_on)) \
102 if (!WARN(i915.verbose_state_checks, format)) \
104 unlikely(__ret_warn_on); \
107 #define I915_STATE_WARN_ON(x) \
108 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
110 bool __i915_inject_load_failure(const char *func, int line);
111 #define i915_inject_load_failure() \
112 __i915_inject_load_failure(__func__, __LINE__)
114 static inline const char *yesno(bool v)
116 return v ? "yes" : "no";
119 static inline const char *onoff(bool v)
121 return v ? "on" : "off";
130 I915_MAX_PIPES = _PIPE_EDP
132 #define pipe_name(p) ((p) + 'A')
144 static inline const char *transcoder_name(enum transcoder transcoder)
146 switch (transcoder) {
155 case TRANSCODER_DSI_A:
157 case TRANSCODER_DSI_C:
164 static inline bool transcoder_is_dsi(enum transcoder transcoder)
166 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
170 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
171 * number of planes per CRTC. Not all platforms really have this many planes,
172 * which means some arrays of size I915_MAX_PLANES may have unused entries
173 * between the topmost sprite plane and the cursor plane.
182 #define plane_name(p) ((p) + 'A')
184 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
194 #define port_name(p) ((p) + 'A')
196 #define I915_NUM_PHYS_VLV 2
208 enum intel_display_power_domain {
212 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
213 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
214 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
215 POWER_DOMAIN_TRANSCODER_A,
216 POWER_DOMAIN_TRANSCODER_B,
217 POWER_DOMAIN_TRANSCODER_C,
218 POWER_DOMAIN_TRANSCODER_EDP,
219 POWER_DOMAIN_TRANSCODER_DSI_A,
220 POWER_DOMAIN_TRANSCODER_DSI_C,
221 POWER_DOMAIN_PORT_DDI_A_LANES,
222 POWER_DOMAIN_PORT_DDI_B_LANES,
223 POWER_DOMAIN_PORT_DDI_C_LANES,
224 POWER_DOMAIN_PORT_DDI_D_LANES,
225 POWER_DOMAIN_PORT_DDI_E_LANES,
226 POWER_DOMAIN_PORT_DSI,
227 POWER_DOMAIN_PORT_CRT,
228 POWER_DOMAIN_PORT_OTHER,
237 POWER_DOMAIN_MODESET,
243 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
244 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
245 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
246 #define POWER_DOMAIN_TRANSCODER(tran) \
247 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
248 (tran) + POWER_DOMAIN_TRANSCODER_A)
252 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
264 #define for_each_hpd_pin(__pin) \
265 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
267 struct i915_hotplug {
268 struct work_struct hotplug_work;
271 unsigned long last_jiffies;
276 HPD_MARK_DISABLED = 2
278 } stats[HPD_NUM_PINS];
280 struct delayed_work reenable_work;
282 struct intel_digital_port *irq_port[I915_MAX_PORTS];
285 struct work_struct dig_port_work;
287 struct work_struct poll_init_work;
291 * if we get a HPD irq from DP and a HPD irq from non-DP
292 * the non-DP HPD could block the workqueue on a mode config
293 * mutex getting, that userspace may have taken. However
294 * userspace is waiting on the DP workqueue to run which is
295 * blocked behind the non-DP one.
297 struct workqueue_struct *dp_wq;
300 #define I915_GEM_GPU_DOMAINS \
301 (I915_GEM_DOMAIN_RENDER | \
302 I915_GEM_DOMAIN_SAMPLER | \
303 I915_GEM_DOMAIN_COMMAND | \
304 I915_GEM_DOMAIN_INSTRUCTION | \
305 I915_GEM_DOMAIN_VERTEX)
307 #define for_each_pipe(__dev_priv, __p) \
308 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
309 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
310 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
311 for_each_if ((__mask) & (1 << (__p)))
312 #define for_each_plane(__dev_priv, __pipe, __p) \
314 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
316 #define for_each_sprite(__dev_priv, __p, __s) \
318 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
321 #define for_each_port_masked(__port, __ports_mask) \
322 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
323 for_each_if ((__ports_mask) & (1 << (__port)))
325 #define for_each_crtc(dev, crtc) \
326 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
328 #define for_each_intel_plane(dev, intel_plane) \
329 list_for_each_entry(intel_plane, \
330 &(dev)->mode_config.plane_list, \
333 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
334 list_for_each_entry(intel_plane, \
335 &(dev)->mode_config.plane_list, \
337 for_each_if ((plane_mask) & \
338 (1 << drm_plane_index(&intel_plane->base)))
340 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
341 list_for_each_entry(intel_plane, \
342 &(dev)->mode_config.plane_list, \
344 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
346 #define for_each_intel_crtc(dev, intel_crtc) \
347 list_for_each_entry(intel_crtc, \
348 &(dev)->mode_config.crtc_list, \
351 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
352 list_for_each_entry(intel_crtc, \
353 &(dev)->mode_config.crtc_list, \
355 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
357 #define for_each_intel_encoder(dev, intel_encoder) \
358 list_for_each_entry(intel_encoder, \
359 &(dev)->mode_config.encoder_list, \
362 #define for_each_intel_connector(dev, intel_connector) \
363 list_for_each_entry(intel_connector, \
364 &(dev)->mode_config.connector_list, \
367 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
368 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
369 for_each_if ((intel_encoder)->base.crtc == (__crtc))
371 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
372 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
373 for_each_if ((intel_connector)->base.encoder == (__encoder))
375 #define for_each_power_domain(domain, mask) \
376 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
377 for_each_if ((1 << (domain)) & (mask))
379 struct drm_i915_private;
380 struct i915_mm_struct;
381 struct i915_mmu_object;
383 struct drm_i915_file_private {
384 struct drm_i915_private *dev_priv;
385 struct drm_file *file;
389 struct list_head request_list;
390 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
391 * chosen to prevent the CPU getting more than a frame ahead of the GPU
392 * (when using lax throttling for the frontbuffer). We also use it to
393 * offer free GPU waitboosts for severely congested workloads.
395 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
397 struct idr context_idr;
399 struct intel_rps_client {
400 struct list_head link;
404 unsigned int bsd_ring;
407 /* Used by dp and fdi links */
408 struct intel_link_m_n {
416 void intel_link_compute_m_n(int bpp, int nlanes,
417 int pixel_clock, int link_clock,
418 struct intel_link_m_n *m_n);
420 /* Interface history:
423 * 1.2: Add Power Management
424 * 1.3: Add vblank support
425 * 1.4: Fix cmdbuffer path, add heap destroy
426 * 1.5: Add vblank pipe configuration
427 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
428 * - Support vertical blank on secondary display pipe
430 #define DRIVER_MAJOR 1
431 #define DRIVER_MINOR 6
432 #define DRIVER_PATCHLEVEL 0
434 #define WATCH_LISTS 0
436 struct opregion_header;
437 struct opregion_acpi;
438 struct opregion_swsci;
439 struct opregion_asle;
441 struct intel_opregion {
442 struct opregion_header *header;
443 struct opregion_acpi *acpi;
444 struct opregion_swsci *swsci;
445 u32 swsci_gbda_sub_functions;
446 u32 swsci_sbcb_sub_functions;
447 struct opregion_asle *asle;
452 struct work_struct asle_work;
454 #define OPREGION_SIZE (8*1024)
456 struct intel_overlay;
457 struct intel_overlay_error_state;
459 #define I915_FENCE_REG_NONE -1
460 #define I915_MAX_NUM_FENCES 32
461 /* 32 fences + sign bit for FENCE_REG_NONE */
462 #define I915_MAX_NUM_FENCE_BITS 6
464 struct drm_i915_fence_reg {
465 struct list_head lru_list;
466 struct drm_i915_gem_object *obj;
470 struct sdvo_device_mapping {
479 struct intel_display_error_state;
481 struct drm_i915_error_state {
491 /* Generic register state */
499 u32 error; /* gen6+ */
500 u32 err_int; /* gen7 */
501 u32 fault_data0; /* gen8, gen9 */
502 u32 fault_data1; /* gen8, gen9 */
508 u32 extra_instdone[I915_NUM_INSTDONE_REG];
509 u64 fence[I915_MAX_NUM_FENCES];
510 struct intel_overlay_error_state *overlay;
511 struct intel_display_error_state *display;
512 struct drm_i915_error_object *semaphore_obj;
514 struct drm_i915_error_ring {
516 /* Software tracked state */
520 enum intel_ring_hangcheck_action hangcheck_action;
523 /* our own tracking of ring head and tail */
528 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
547 u32 rc_psmi; /* sleep state */
548 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
550 struct drm_i915_error_object {
554 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
556 struct drm_i915_error_object *wa_ctx;
558 struct drm_i915_error_request {
564 struct drm_i915_error_waiter {
565 char comm[TASK_COMM_LEN];
579 char comm[TASK_COMM_LEN];
580 } ring[I915_NUM_ENGINES];
582 struct drm_i915_error_buffer {
585 u32 rseqno[I915_NUM_ENGINES], wseqno;
589 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
597 } **active_bo, **pinned_bo;
599 u32 *active_bo_count, *pinned_bo_count;
603 struct intel_connector;
604 struct intel_encoder;
605 struct intel_crtc_state;
606 struct intel_initial_plane_config;
611 struct drm_i915_display_funcs {
612 int (*get_display_clock_speed)(struct drm_device *dev);
613 int (*get_fifo_size)(struct drm_device *dev, int plane);
614 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
615 int (*compute_intermediate_wm)(struct drm_device *dev,
616 struct intel_crtc *intel_crtc,
617 struct intel_crtc_state *newstate);
618 void (*initial_watermarks)(struct intel_crtc_state *cstate);
619 void (*optimize_watermarks)(struct intel_crtc_state *cstate);
620 int (*compute_global_watermarks)(struct drm_atomic_state *state);
621 void (*update_wm)(struct drm_crtc *crtc);
622 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
623 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
624 /* Returns the active state of the crtc, and if the crtc is active,
625 * fills out the pipe-config with the hw state. */
626 bool (*get_pipe_config)(struct intel_crtc *,
627 struct intel_crtc_state *);
628 void (*get_initial_plane_config)(struct intel_crtc *,
629 struct intel_initial_plane_config *);
630 int (*crtc_compute_clock)(struct intel_crtc *crtc,
631 struct intel_crtc_state *crtc_state);
632 void (*crtc_enable)(struct drm_crtc *crtc);
633 void (*crtc_disable)(struct drm_crtc *crtc);
634 void (*audio_codec_enable)(struct drm_connector *connector,
635 struct intel_encoder *encoder,
636 const struct drm_display_mode *adjusted_mode);
637 void (*audio_codec_disable)(struct intel_encoder *encoder);
638 void (*fdi_link_train)(struct drm_crtc *crtc);
639 void (*init_clock_gating)(struct drm_device *dev);
640 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
641 struct drm_framebuffer *fb,
642 struct drm_i915_gem_object *obj,
643 struct drm_i915_gem_request *req,
645 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
646 /* clock updates for mode set */
648 /* render clock increase/decrease */
649 /* display clock increase/decrease */
650 /* pll clock increase/decrease */
652 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
653 void (*load_luts)(struct drm_crtc_state *crtc_state);
656 enum forcewake_domain_id {
657 FW_DOMAIN_ID_RENDER = 0,
658 FW_DOMAIN_ID_BLITTER,
664 enum forcewake_domains {
665 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
666 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
667 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
668 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
673 #define FW_REG_READ (1)
674 #define FW_REG_WRITE (2)
676 enum forcewake_domains
677 intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
678 i915_reg_t reg, unsigned int op);
680 struct intel_uncore_funcs {
681 void (*force_wake_get)(struct drm_i915_private *dev_priv,
682 enum forcewake_domains domains);
683 void (*force_wake_put)(struct drm_i915_private *dev_priv,
684 enum forcewake_domains domains);
686 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
687 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
688 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
689 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
691 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
692 uint8_t val, bool trace);
693 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
694 uint16_t val, bool trace);
695 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
696 uint32_t val, bool trace);
697 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
698 uint64_t val, bool trace);
701 struct intel_uncore {
702 spinlock_t lock; /** lock is also taken in irq contexts. */
704 struct intel_uncore_funcs funcs;
707 enum forcewake_domains fw_domains;
709 struct intel_uncore_forcewake_domain {
710 struct drm_i915_private *i915;
711 enum forcewake_domain_id id;
712 enum forcewake_domains mask;
714 struct hrtimer timer;
721 } fw_domain[FW_DOMAIN_ID_COUNT];
723 int unclaimed_mmio_check;
726 /* Iterate over initialised fw domains */
727 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
728 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
729 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
731 for_each_if ((mask__) & (domain__)->mask)
733 #define for_each_fw_domain(domain__, dev_priv__) \
734 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
736 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
737 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
738 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
741 struct work_struct work;
743 uint32_t *dmc_payload;
744 uint32_t dmc_fw_size;
747 i915_reg_t mmioaddr[8];
748 uint32_t mmiodata[8];
750 uint32_t allowed_dc_mask;
753 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
754 func(is_mobile) sep \
757 func(is_i945gm) sep \
759 func(need_gfx_hws) sep \
761 func(is_pineview) sep \
762 func(is_broadwater) sep \
763 func(is_crestline) sep \
764 func(is_ivybridge) sep \
765 func(is_valleyview) sep \
766 func(is_cherryview) sep \
767 func(is_haswell) sep \
768 func(is_broadwell) sep \
769 func(is_skylake) sep \
770 func(is_broxton) sep \
771 func(is_kabylake) sep \
772 func(is_preliminary) sep \
774 func(has_pipe_cxsr) sep \
775 func(has_hotplug) sep \
776 func(cursor_needs_physical) sep \
777 func(has_overlay) sep \
778 func(overlay_needs_physical) sep \
779 func(supports_tv) sep \
781 func(has_snoop) sep \
783 func(has_fpga_dbg) sep \
786 #define DEFINE_FLAG(name) u8 name:1
787 #define SEP_SEMICOLON ;
789 struct intel_device_info {
790 u32 display_mmio_offset;
793 u8 num_sprites[I915_MAX_PIPES];
796 u8 ring_mask; /* Rings supported by the HW */
797 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
798 /* Register offsets for the various display pipes and transcoders */
799 int pipe_offsets[I915_MAX_TRANSCODERS];
800 int trans_offsets[I915_MAX_TRANSCODERS];
801 int palette_offsets[I915_MAX_PIPES];
802 int cursor_offsets[I915_MAX_PIPES];
804 /* Slice/subslice/EU info */
807 u8 subslice_per_slice;
811 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
814 u8 has_subslice_pg:1;
818 u16 degamma_lut_size;
826 enum i915_cache_level {
828 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
829 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
830 caches, eg sampler/render caches, and the
831 large Last-Level-Cache. LLC is coherent with
832 the CPU, but L3 is only visible to the GPU. */
833 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
836 struct i915_ctx_hang_stats {
837 /* This context had batch pending when hang was declared */
838 unsigned batch_pending;
840 /* This context had batch active when hang was declared */
841 unsigned batch_active;
843 /* Time when this context was last blamed for a GPU reset */
844 unsigned long guilty_ts;
846 /* If the contexts causes a second GPU hang within this time,
847 * it is permanently banned from submitting any more work.
849 unsigned long ban_period_seconds;
851 /* This context is banned to submit more work */
855 /* This must match up with the value previously used for execbuf2.rsvd1. */
856 #define DEFAULT_CONTEXT_HANDLE 0
859 * struct i915_gem_context - as the name implies, represents a context.
860 * @ref: reference count.
861 * @user_handle: userspace tracking identity for this context.
862 * @remap_slice: l3 row remapping information.
863 * @flags: context specific flags:
864 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
865 * @file_priv: filp associated with this context (NULL for global default
867 * @hang_stats: information about the role of this context in possible GPU
869 * @ppgtt: virtual memory space used by this context.
870 * @legacy_hw_ctx: render context backing object and whether it is correctly
871 * initialized (legacy ring submission mechanism only).
872 * @link: link in the global list of contexts.
874 * Contexts are memory images used by the hardware to store copies of their
877 struct i915_gem_context {
879 struct drm_i915_private *i915;
880 struct drm_i915_file_private *file_priv;
881 struct i915_hw_ppgtt *ppgtt;
883 struct i915_ctx_hang_stats hang_stats;
886 #define CONTEXT_NO_ZEROMAP BIT(0)
887 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
889 /* Unique identifier for this context, used by the hw for tracking */
895 struct intel_context {
896 struct drm_i915_gem_object *state;
897 struct intel_ringbuffer *ringbuf;
898 struct i915_vma *lrc_vma;
899 uint32_t *lrc_reg_state;
903 } engine[I915_NUM_ENGINES];
906 struct atomic_notifier_head status_notifier;
907 bool execlists_force_single_submission;
909 struct list_head link;
923 /* This is always the inner lock when overlapping with struct_mutex and
924 * it's the outer lock when overlapping with stolen_lock. */
927 unsigned int possible_framebuffer_bits;
928 unsigned int busy_bits;
929 unsigned int visible_pipes_mask;
930 struct intel_crtc *crtc;
932 struct drm_mm_node compressed_fb;
933 struct drm_mm_node *compressed_llb;
940 struct intel_fbc_state_cache {
942 unsigned int mode_flags;
943 uint32_t hsw_bdw_pixel_rate;
947 unsigned int rotation;
955 uint32_t pixel_format;
958 unsigned int tiling_mode;
962 struct intel_fbc_reg_params {
966 unsigned int fence_y_offset;
971 uint32_t pixel_format;
979 struct intel_fbc_work {
981 u32 scheduled_vblank;
982 struct work_struct work;
985 const char *no_fbc_reason;
989 * HIGH_RR is the highest eDP panel refresh rate read from EDID
990 * LOW_RR is the lowest eDP panel refresh rate found from EDID
991 * parsing for same resolution.
993 enum drrs_refresh_rate_type {
996 DRRS_MAX_RR, /* RR count */
999 enum drrs_support_type {
1000 DRRS_NOT_SUPPORTED = 0,
1001 STATIC_DRRS_SUPPORT = 1,
1002 SEAMLESS_DRRS_SUPPORT = 2
1008 struct delayed_work work;
1009 struct intel_dp *dp;
1010 unsigned busy_frontbuffer_bits;
1011 enum drrs_refresh_rate_type refresh_rate_type;
1012 enum drrs_support_type type;
1019 struct intel_dp *enabled;
1021 struct delayed_work work;
1022 unsigned busy_frontbuffer_bits;
1024 bool aux_frame_sync;
1029 PCH_NONE = 0, /* No PCH present */
1030 PCH_IBX, /* Ibexpeak PCH */
1031 PCH_CPT, /* Cougarpoint PCH */
1032 PCH_LPT, /* Lynxpoint PCH */
1033 PCH_SPT, /* Sunrisepoint PCH */
1034 PCH_KBP, /* Kabypoint PCH */
1038 enum intel_sbi_destination {
1043 #define QUIRK_PIPEA_FORCE (1<<0)
1044 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1045 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1046 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1047 #define QUIRK_PIPEB_FORCE (1<<4)
1048 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1051 struct intel_fbc_work;
1053 struct intel_gmbus {
1054 struct i2c_adapter adapter;
1055 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1058 i915_reg_t gpio_reg;
1059 struct i2c_algo_bit_data bit_algo;
1060 struct drm_i915_private *dev_priv;
1063 struct i915_suspend_saved_registers {
1066 u32 savePP_ON_DELAYS;
1067 u32 savePP_OFF_DELAYS;
1072 u32 saveFBC_CONTROL;
1073 u32 saveCACHE_MODE_0;
1074 u32 saveMI_ARB_STATE;
1078 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1079 u32 savePCH_PORT_HOTPLUG;
1083 struct vlv_s0ix_state {
1090 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1091 u32 media_max_req_count;
1092 u32 gfx_max_req_count;
1118 u32 rp_down_timeout;
1124 /* Display 1 CZ domain */
1129 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1131 /* GT SA CZ domain */
1138 /* Display 2 CZ domain */
1142 u32 clock_gate_dis2;
1145 struct intel_rps_ei {
1151 struct intel_gen6_power_mgmt {
1153 * work, interrupts_enabled and pm_iir are protected by
1154 * dev_priv->irq_lock
1156 struct work_struct work;
1157 bool interrupts_enabled;
1162 /* Frequencies are stored in potentially platform dependent multiples.
1163 * In other words, *_freq needs to be multiplied by X to be interesting.
1164 * Soft limits are those which are used for the dynamic reclocking done
1165 * by the driver (raise frequencies under heavy loads, and lower for
1166 * lighter loads). Hard limits are those imposed by the hardware.
1168 * A distinction is made for overclocking, which is never enabled by
1169 * default, and is considered to be above the hard limit if it's
1172 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1173 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1174 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1175 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1176 u8 min_freq; /* AKA RPn. Minimum frequency */
1177 u8 idle_freq; /* Frequency to request when we are idle */
1178 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1179 u8 rp1_freq; /* "less than" RP0 power/freqency */
1180 u8 rp0_freq; /* Non-overclocked max frequency. */
1181 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
1183 u8 up_threshold; /* Current %busy required to uplock */
1184 u8 down_threshold; /* Current %busy required to downclock */
1187 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1189 spinlock_t client_lock;
1190 struct list_head clients;
1194 struct delayed_work delayed_resume_work;
1197 struct intel_rps_client semaphores, mmioflips;
1199 /* manual wa residency calculations */
1200 struct intel_rps_ei up_ei, down_ei;
1203 * Protects RPS/RC6 register access and PCU communication.
1204 * Must be taken after struct_mutex if nested. Note that
1205 * this lock may be held for long periods of time when
1206 * talking to hw - so only take it when talking to hw!
1208 struct mutex hw_lock;
1211 /* defined intel_pm.c */
1212 extern spinlock_t mchdev_lock;
1214 struct intel_ilk_power_mgmt {
1222 unsigned long last_time1;
1223 unsigned long chipset_power;
1226 unsigned long gfx_power;
1233 struct drm_i915_private;
1234 struct i915_power_well;
1236 struct i915_power_well_ops {
1238 * Synchronize the well's hw state to match the current sw state, for
1239 * example enable/disable it based on the current refcount. Called
1240 * during driver init and resume time, possibly after first calling
1241 * the enable/disable handlers.
1243 void (*sync_hw)(struct drm_i915_private *dev_priv,
1244 struct i915_power_well *power_well);
1246 * Enable the well and resources that depend on it (for example
1247 * interrupts located on the well). Called after the 0->1 refcount
1250 void (*enable)(struct drm_i915_private *dev_priv,
1251 struct i915_power_well *power_well);
1253 * Disable the well and resources that depend on it. Called after
1254 * the 1->0 refcount transition.
1256 void (*disable)(struct drm_i915_private *dev_priv,
1257 struct i915_power_well *power_well);
1258 /* Returns the hw enabled state. */
1259 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1260 struct i915_power_well *power_well);
1263 /* Power well structure for haswell */
1264 struct i915_power_well {
1267 /* power well enable/disable usage count */
1269 /* cached hw enabled state */
1271 unsigned long domains;
1273 const struct i915_power_well_ops *ops;
1276 struct i915_power_domains {
1278 * Power wells needed for initialization at driver init and suspend
1279 * time are on. They are kept on until after the first modeset.
1283 int power_well_count;
1286 int domain_use_count[POWER_DOMAIN_NUM];
1287 struct i915_power_well *power_wells;
1290 #define MAX_L3_SLICES 2
1291 struct intel_l3_parity {
1292 u32 *remap_info[MAX_L3_SLICES];
1293 struct work_struct error_work;
1297 struct i915_gem_mm {
1298 /** Memory allocator for GTT stolen memory */
1299 struct drm_mm stolen;
1300 /** Protects the usage of the GTT stolen memory allocator. This is
1301 * always the inner lock when overlapping with struct_mutex. */
1302 struct mutex stolen_lock;
1304 /** List of all objects in gtt_space. Used to restore gtt
1305 * mappings on resume */
1306 struct list_head bound_list;
1308 * List of objects which are not bound to the GTT (thus
1309 * are idle and not used by the GPU) but still have
1310 * (presumably uncached) pages still attached.
1312 struct list_head unbound_list;
1314 /** Usable portion of the GTT for GEM */
1315 unsigned long stolen_base; /* limited to low memory (32-bit) */
1317 /** PPGTT used for aliasing the PPGTT with the GTT */
1318 struct i915_hw_ppgtt *aliasing_ppgtt;
1320 struct notifier_block oom_notifier;
1321 struct notifier_block vmap_notifier;
1322 struct shrinker shrinker;
1323 bool shrinker_no_lock_stealing;
1325 /** LRU list of objects with fence regs on them. */
1326 struct list_head fence_list;
1329 * Are we in a non-interruptible section of code like
1334 /* the indicator for dispatch video commands on two BSD rings */
1335 unsigned int bsd_ring_dispatch_index;
1337 /** Bit 6 swizzling required for X tiling */
1338 uint32_t bit_6_swizzle_x;
1339 /** Bit 6 swizzling required for Y tiling */
1340 uint32_t bit_6_swizzle_y;
1342 /* accounting, useful for userland debugging */
1343 spinlock_t object_stat_lock;
1344 size_t object_memory;
1348 struct drm_i915_error_state_buf {
1349 struct drm_i915_private *i915;
1358 struct i915_error_state_file_priv {
1359 struct drm_device *dev;
1360 struct drm_i915_error_state *error;
1363 struct i915_gpu_error {
1364 /* For hangcheck timer */
1365 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1366 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1367 /* Hang gpu twice in this window and your context gets banned */
1368 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1370 struct delayed_work hangcheck_work;
1372 /* For reset and error_state handling. */
1374 /* Protected by the above dev->gpu_error.lock. */
1375 struct drm_i915_error_state *first_error;
1377 unsigned long missed_irq_rings;
1380 * State variable controlling the reset flow and count
1382 * This is a counter which gets incremented when reset is triggered,
1383 * and again when reset has been handled. So odd values (lowest bit set)
1384 * means that reset is in progress and even values that
1385 * (reset_counter >> 1):th reset was successfully completed.
1387 * If reset is not completed succesfully, the I915_WEDGE bit is
1388 * set meaning that hardware is terminally sour and there is no
1389 * recovery. All waiters on the reset_queue will be woken when
1392 * This counter is used by the wait_seqno code to notice that reset
1393 * event happened and it needs to restart the entire ioctl (since most
1394 * likely the seqno it waited for won't ever signal anytime soon).
1396 * This is important for lock-free wait paths, where no contended lock
1397 * naturally enforces the correct ordering between the bail-out of the
1398 * waiter and the gpu reset work code.
1400 atomic_t reset_counter;
1402 #define I915_RESET_IN_PROGRESS_FLAG 1
1403 #define I915_WEDGED (1 << 31)
1406 * Waitqueue to signal when a hang is detected. Used to for waiters
1407 * to release the struct_mutex for the reset to procede.
1409 wait_queue_head_t wait_queue;
1412 * Waitqueue to signal when the reset has completed. Used by clients
1413 * that wait for dev_priv->mm.wedged to settle.
1415 wait_queue_head_t reset_queue;
1417 /* For missed irq/seqno simulation. */
1418 unsigned long test_irq_rings;
1421 enum modeset_restore {
1422 MODESET_ON_LID_OPEN,
1427 #define DP_AUX_A 0x40
1428 #define DP_AUX_B 0x10
1429 #define DP_AUX_C 0x20
1430 #define DP_AUX_D 0x30
1432 #define DDC_PIN_B 0x05
1433 #define DDC_PIN_C 0x04
1434 #define DDC_PIN_D 0x06
1436 struct ddi_vbt_port_info {
1438 * This is an index in the HDMI/DVI DDI buffer translation table.
1439 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1440 * populate this field.
1442 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1443 uint8_t hdmi_level_shift;
1445 uint8_t supports_dvi:1;
1446 uint8_t supports_hdmi:1;
1447 uint8_t supports_dp:1;
1449 uint8_t alternate_aux_channel;
1450 uint8_t alternate_ddc_pin;
1452 uint8_t dp_boost_level;
1453 uint8_t hdmi_boost_level;
1456 enum psr_lines_to_wait {
1457 PSR_0_LINES_TO_WAIT = 0,
1459 PSR_4_LINES_TO_WAIT,
1463 struct intel_vbt_data {
1464 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1465 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1468 unsigned int int_tv_support:1;
1469 unsigned int lvds_dither:1;
1470 unsigned int lvds_vbt:1;
1471 unsigned int int_crt_support:1;
1472 unsigned int lvds_use_ssc:1;
1473 unsigned int display_clock_mode:1;
1474 unsigned int fdi_rx_polarity_inverted:1;
1475 unsigned int panel_type:4;
1477 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1479 enum drrs_support_type drrs_type;
1490 struct edp_power_seq pps;
1495 bool require_aux_wakeup;
1497 enum psr_lines_to_wait lines_to_wait;
1498 int tp1_wakeup_time;
1499 int tp2_tp3_wakeup_time;
1505 bool active_low_pwm;
1506 u8 min_brightness; /* min_brightness/255 of max */
1507 enum intel_backlight_type type;
1513 struct mipi_config *config;
1514 struct mipi_pps_data *pps;
1518 const u8 *sequence[MIPI_SEQ_MAX];
1524 union child_device_config *child_dev;
1526 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1527 struct sdvo_device_mapping sdvo_mappings[2];
1530 enum intel_ddb_partitioning {
1532 INTEL_DDB_PART_5_6, /* IVB+ */
1535 struct intel_wm_level {
1543 struct ilk_wm_values {
1544 uint32_t wm_pipe[3];
1546 uint32_t wm_lp_spr[3];
1547 uint32_t wm_linetime[3];
1549 enum intel_ddb_partitioning partitioning;
1552 struct vlv_pipe_wm {
1563 struct vlv_wm_values {
1564 struct vlv_pipe_wm pipe[3];
1565 struct vlv_sr_wm sr;
1575 struct skl_ddb_entry {
1576 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1579 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1581 return entry->end - entry->start;
1584 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1585 const struct skl_ddb_entry *e2)
1587 if (e1->start == e2->start && e1->end == e2->end)
1593 struct skl_ddb_allocation {
1594 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1595 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1596 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1599 struct skl_wm_values {
1600 unsigned dirty_pipes;
1601 struct skl_ddb_allocation ddb;
1602 uint32_t wm_linetime[I915_MAX_PIPES];
1603 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1604 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1607 struct skl_wm_level {
1608 bool plane_en[I915_MAX_PLANES];
1609 uint16_t plane_res_b[I915_MAX_PLANES];
1610 uint8_t plane_res_l[I915_MAX_PLANES];
1614 * This struct helps tracking the state needed for runtime PM, which puts the
1615 * device in PCI D3 state. Notice that when this happens, nothing on the
1616 * graphics device works, even register access, so we don't get interrupts nor
1619 * Every piece of our code that needs to actually touch the hardware needs to
1620 * either call intel_runtime_pm_get or call intel_display_power_get with the
1621 * appropriate power domain.
1623 * Our driver uses the autosuspend delay feature, which means we'll only really
1624 * suspend if we stay with zero refcount for a certain amount of time. The
1625 * default value is currently very conservative (see intel_runtime_pm_enable), but
1626 * it can be changed with the standard runtime PM files from sysfs.
1628 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1629 * goes back to false exactly before we reenable the IRQs. We use this variable
1630 * to check if someone is trying to enable/disable IRQs while they're supposed
1631 * to be disabled. This shouldn't happen and we'll print some error messages in
1634 * For more, read the Documentation/power/runtime_pm.txt.
1636 struct i915_runtime_pm {
1637 atomic_t wakeref_count;
1638 atomic_t atomic_seq;
1643 enum intel_pipe_crc_source {
1644 INTEL_PIPE_CRC_SOURCE_NONE,
1645 INTEL_PIPE_CRC_SOURCE_PLANE1,
1646 INTEL_PIPE_CRC_SOURCE_PLANE2,
1647 INTEL_PIPE_CRC_SOURCE_PF,
1648 INTEL_PIPE_CRC_SOURCE_PIPE,
1649 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1650 INTEL_PIPE_CRC_SOURCE_TV,
1651 INTEL_PIPE_CRC_SOURCE_DP_B,
1652 INTEL_PIPE_CRC_SOURCE_DP_C,
1653 INTEL_PIPE_CRC_SOURCE_DP_D,
1654 INTEL_PIPE_CRC_SOURCE_AUTO,
1655 INTEL_PIPE_CRC_SOURCE_MAX,
1658 struct intel_pipe_crc_entry {
1663 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1664 struct intel_pipe_crc {
1666 bool opened; /* exclusive access to the result file */
1667 struct intel_pipe_crc_entry *entries;
1668 enum intel_pipe_crc_source source;
1670 wait_queue_head_t wq;
1673 struct i915_frontbuffer_tracking {
1677 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1684 struct i915_wa_reg {
1687 /* bitmask representing WA bits */
1692 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1693 * allowing it for RCS as we don't foresee any requirement of having
1694 * a whitelist for other engines. When it is really required for
1695 * other engines then the limit need to be increased.
1697 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1699 struct i915_workarounds {
1700 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1702 u32 hw_whitelist_count[I915_NUM_ENGINES];
1705 struct i915_virtual_gpu {
1709 struct i915_execbuffer_params {
1710 struct drm_device *dev;
1711 struct drm_file *file;
1712 uint32_t dispatch_flags;
1713 uint32_t args_batch_start_offset;
1714 uint64_t batch_obj_vm_offset;
1715 struct intel_engine_cs *engine;
1716 struct drm_i915_gem_object *batch_obj;
1717 struct i915_gem_context *ctx;
1718 struct drm_i915_gem_request *request;
1721 /* used in computing the new watermarks state */
1722 struct intel_wm_config {
1723 unsigned int num_pipes_active;
1724 bool sprites_enabled;
1725 bool sprites_scaled;
1728 struct drm_i915_private {
1729 struct drm_device drm;
1731 struct kmem_cache *objects;
1732 struct kmem_cache *vmas;
1733 struct kmem_cache *requests;
1735 const struct intel_device_info info;
1737 int relative_constants_mode;
1741 struct intel_uncore uncore;
1743 struct i915_virtual_gpu vgpu;
1745 struct intel_gvt gvt;
1747 struct intel_guc guc;
1749 struct intel_csr csr;
1751 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1753 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1754 * controller on different i2c buses. */
1755 struct mutex gmbus_mutex;
1758 * Base address of the gmbus and gpio block.
1760 uint32_t gpio_mmio_base;
1762 /* MMIO base address for MIPI regs */
1763 uint32_t mipi_mmio_base;
1765 uint32_t psr_mmio_base;
1767 wait_queue_head_t gmbus_wait_queue;
1769 struct pci_dev *bridge_dev;
1770 struct i915_gem_context *kernel_context;
1771 struct intel_engine_cs engine[I915_NUM_ENGINES];
1772 struct drm_i915_gem_object *semaphore_obj;
1773 uint32_t last_seqno, next_seqno;
1775 struct drm_dma_handle *status_page_dmah;
1776 struct resource mch_res;
1778 /* protects the irq masks */
1779 spinlock_t irq_lock;
1781 /* protects the mmio flip data */
1782 spinlock_t mmio_flip_lock;
1784 bool display_irqs_enabled;
1786 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1787 struct pm_qos_request pm_qos;
1789 /* Sideband mailbox protection */
1790 struct mutex sb_lock;
1792 /** Cached value of IMR to avoid reads in updating the bitfield */
1795 u32 de_irq_mask[I915_MAX_PIPES];
1800 u32 pipestat_irq_mask[I915_MAX_PIPES];
1802 struct i915_hotplug hotplug;
1803 struct intel_fbc fbc;
1804 struct i915_drrs drrs;
1805 struct intel_opregion opregion;
1806 struct intel_vbt_data vbt;
1808 bool preserve_bios_swizzle;
1811 struct intel_overlay *overlay;
1813 /* backlight registers and fields in struct intel_panel */
1814 struct mutex backlight_lock;
1817 bool no_aux_handshake;
1819 /* protects panel power sequencer state */
1820 struct mutex pps_mutex;
1822 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1823 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1825 unsigned int fsb_freq, mem_freq, is_ddr3;
1826 unsigned int skl_preferred_vco_freq;
1827 unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
1828 unsigned int max_dotclk_freq;
1829 unsigned int rawclk_freq;
1830 unsigned int hpll_freq;
1831 unsigned int czclk_freq;
1834 unsigned int vco, ref;
1838 * wq - Driver workqueue for GEM.
1840 * NOTE: Work items scheduled here are not allowed to grab any modeset
1841 * locks, for otherwise the flushing done in the pageflip code will
1842 * result in deadlocks.
1844 struct workqueue_struct *wq;
1846 /* Display functions */
1847 struct drm_i915_display_funcs display;
1849 /* PCH chipset type */
1850 enum intel_pch pch_type;
1851 unsigned short pch_id;
1853 unsigned long quirks;
1855 enum modeset_restore modeset_restore;
1856 struct mutex modeset_restore_lock;
1857 struct drm_atomic_state *modeset_restore_state;
1858 struct drm_modeset_acquire_ctx reset_ctx;
1860 struct list_head vm_list; /* Global list of all address spaces */
1861 struct i915_ggtt ggtt; /* VM representing the global address space */
1863 struct i915_gem_mm mm;
1864 DECLARE_HASHTABLE(mm_structs, 7);
1865 struct mutex mm_lock;
1867 /* The hw wants to have a stable context identifier for the lifetime
1868 * of the context (for OA, PASID, faults, etc). This is limited
1869 * in execlists to 21 bits.
1871 struct ida context_hw_ida;
1872 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1874 /* Kernel Modesetting */
1876 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1877 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1878 wait_queue_head_t pending_flip_queue;
1880 #ifdef CONFIG_DEBUG_FS
1881 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1884 /* dpll and cdclk state is protected by connection_mutex */
1885 int num_shared_dpll;
1886 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1887 const struct intel_dpll_mgr *dpll_mgr;
1890 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1891 * Must be global rather than per dpll, because on some platforms
1892 * plls share registers.
1894 struct mutex dpll_lock;
1896 unsigned int active_crtcs;
1897 unsigned int min_pixclk[I915_MAX_PIPES];
1899 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1901 struct i915_workarounds workarounds;
1903 struct i915_frontbuffer_tracking fb_tracking;
1907 bool mchbar_need_disable;
1909 struct intel_l3_parity l3_parity;
1911 /* Cannot be determined by PCIID. You must always read a register. */
1914 /* gen6+ rps state */
1915 struct intel_gen6_power_mgmt rps;
1917 /* ilk-only ips/rps state. Everything in here is protected by the global
1918 * mchdev_lock in intel_pm.c */
1919 struct intel_ilk_power_mgmt ips;
1921 struct i915_power_domains power_domains;
1923 struct i915_psr psr;
1925 struct i915_gpu_error gpu_error;
1927 struct drm_i915_gem_object *vlv_pctx;
1929 #ifdef CONFIG_DRM_FBDEV_EMULATION
1930 /* list of fbdev register on this device */
1931 struct intel_fbdev *fbdev;
1932 struct work_struct fbdev_suspend_work;
1935 struct drm_property *broadcast_rgb_property;
1936 struct drm_property *force_audio_property;
1938 /* hda/i915 audio component */
1939 struct i915_audio_component *audio_component;
1940 bool audio_component_registered;
1942 * av_mutex - mutex for audio/video sync
1945 struct mutex av_mutex;
1947 uint32_t hw_context_size;
1948 struct list_head context_list;
1952 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1953 u32 chv_phy_control;
1955 * Shadows for CHV DPLL_MD regs to keep the state
1956 * checker somewhat working in the presence hardware
1957 * crappiness (can't read out DPLL_MD for pipes B & C).
1959 u32 chv_dpll_md[I915_MAX_PIPES];
1963 bool suspended_to_idle;
1964 struct i915_suspend_saved_registers regfile;
1965 struct vlv_s0ix_state vlv_s0ix_state;
1969 * Raw watermark latency values:
1970 * in 0.1us units for WM0,
1971 * in 0.5us units for WM1+.
1974 uint16_t pri_latency[5];
1976 uint16_t spr_latency[5];
1978 uint16_t cur_latency[5];
1980 * Raw watermark memory latency values
1981 * for SKL for all 8 levels
1984 uint16_t skl_latency[8];
1987 * The skl_wm_values structure is a bit too big for stack
1988 * allocation, so we keep the staging struct where we store
1989 * intermediate results here instead.
1991 struct skl_wm_values skl_results;
1993 /* current hardware state */
1995 struct ilk_wm_values hw;
1996 struct skl_wm_values skl_hw;
1997 struct vlv_wm_values vlv;
2003 * Should be held around atomic WM register writing; also
2004 * protects * intel_crtc->wm.active and
2005 * cstate->wm.need_postvbl_update.
2007 struct mutex wm_mutex;
2010 * Set during HW readout of watermarks/DDB. Some platforms
2011 * need to know when we're still using BIOS-provided values
2012 * (which we don't fully trust).
2014 bool distrust_bios_wm;
2017 struct i915_runtime_pm pm;
2019 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2021 int (*execbuf_submit)(struct i915_execbuffer_params *params,
2022 struct drm_i915_gem_execbuffer2 *args,
2023 struct list_head *vmas);
2024 int (*init_engines)(struct drm_device *dev);
2025 void (*cleanup_engine)(struct intel_engine_cs *engine);
2026 void (*stop_engine)(struct intel_engine_cs *engine);
2029 * Is the GPU currently considered idle, or busy executing
2030 * userspace requests? Whilst idle, we allow runtime power
2031 * management to power down the hardware and display clocks.
2032 * In order to reduce the effect on performance, there
2033 * is a slight delay before we do so.
2035 unsigned int active_engines;
2039 * We leave the user IRQ off as much as possible,
2040 * but this means that requests will finish and never
2041 * be retired once the system goes idle. Set a timer to
2042 * fire periodically while the ring is running. When it
2043 * fires, go retire requests.
2045 struct delayed_work retire_work;
2048 * When we detect an idle GPU, we want to turn on
2049 * powersaving features. So once we see that there
2050 * are no more requests outstanding and no more
2051 * arrive within a small period of time, we fire
2052 * off the idle_work.
2054 struct delayed_work idle_work;
2057 /* perform PHY state sanity checks? */
2058 bool chv_phy_assert[2];
2060 struct intel_encoder *dig_port_map[I915_MAX_PORTS];
2063 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2064 * will be rejected. Instead look for a better place.
2068 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2070 return container_of(dev, struct drm_i915_private, drm);
2073 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
2075 return to_i915(dev_get_drvdata(dev));
2078 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2080 return container_of(guc, struct drm_i915_private, guc);
2083 /* Simple iterator over all initialised engines */
2084 #define for_each_engine(engine__, dev_priv__) \
2085 for ((engine__) = &(dev_priv__)->engine[0]; \
2086 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2088 for_each_if (intel_engine_initialized(engine__))
2090 /* Iterator with engine_id */
2091 #define for_each_engine_id(engine__, dev_priv__, id__) \
2092 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2093 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2095 for_each_if (((id__) = (engine__)->id, \
2096 intel_engine_initialized(engine__)))
2098 /* Iterator over subset of engines selected by mask */
2099 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2100 for ((engine__) = &(dev_priv__)->engine[0]; \
2101 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2103 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2104 intel_engine_initialized(engine__))
2106 enum hdmi_force_audio {
2107 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2108 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2109 HDMI_AUDIO_AUTO, /* trust EDID */
2110 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2113 #define I915_GTT_OFFSET_NONE ((u32)-1)
2115 struct drm_i915_gem_object_ops {
2117 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2119 /* Interface between the GEM object and its backing storage.
2120 * get_pages() is called once prior to the use of the associated set
2121 * of pages before to binding them into the GTT, and put_pages() is
2122 * called after we no longer need them. As we expect there to be
2123 * associated cost with migrating pages between the backing storage
2124 * and making them available for the GPU (e.g. clflush), we may hold
2125 * onto the pages after they are no longer referenced by the GPU
2126 * in case they may be used again shortly (for example migrating the
2127 * pages to a different memory domain within the GTT). put_pages()
2128 * will therefore most likely be called when the object itself is
2129 * being released or under memory pressure (where we attempt to
2130 * reap pages for the shrinker).
2132 int (*get_pages)(struct drm_i915_gem_object *);
2133 void (*put_pages)(struct drm_i915_gem_object *);
2135 int (*dmabuf_export)(struct drm_i915_gem_object *);
2136 void (*release)(struct drm_i915_gem_object *);
2140 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2141 * considered to be the frontbuffer for the given plane interface-wise. This
2142 * doesn't mean that the hw necessarily already scans it out, but that any
2143 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2145 * We have one bit per pipe and per scanout plane type.
2147 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2148 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2149 #define INTEL_FRONTBUFFER_BITS \
2150 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2151 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2152 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2153 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2154 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2155 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2156 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2157 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2158 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2159 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2160 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2162 struct drm_i915_gem_object {
2163 struct drm_gem_object base;
2165 const struct drm_i915_gem_object_ops *ops;
2167 /** List of VMAs backed by this object */
2168 struct list_head vma_list;
2170 /** Stolen memory for this object, instead of being backed by shmem. */
2171 struct drm_mm_node *stolen;
2172 struct list_head global_list;
2174 struct list_head engine_list[I915_NUM_ENGINES];
2175 /** Used in execbuf to temporarily hold a ref */
2176 struct list_head obj_exec_link;
2178 struct list_head batch_pool_link;
2181 * This is set if the object is on the active lists (has pending
2182 * rendering and so a non-zero seqno), and is not set if it i s on
2183 * inactive (ready to be unbound) list.
2185 unsigned int active:I915_NUM_ENGINES;
2188 * This is set if the object has been written to since last bound
2191 unsigned int dirty:1;
2194 * Fence register bits (if any) for this object. Will be set
2195 * as needed when mapped into the GTT.
2196 * Protected by dev->struct_mutex.
2198 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2201 * Advice: are the backing pages purgeable?
2203 unsigned int madv:2;
2206 * Current tiling mode for the object.
2208 unsigned int tiling_mode:2;
2210 * Whether the tiling parameters for the currently associated fence
2211 * register have changed. Note that for the purposes of tracking
2212 * tiling changes we also treat the unfenced register, the register
2213 * slot that the object occupies whilst it executes a fenced
2214 * command (such as BLT on gen2/3), as a "fence".
2216 unsigned int fence_dirty:1;
2219 * Is the object at the current location in the gtt mappable and
2220 * fenceable? Used to avoid costly recalculations.
2222 unsigned int map_and_fenceable:1;
2225 * Whether the current gtt mapping needs to be mappable (and isn't just
2226 * mappable by accident). Track pin and fault separate for a more
2227 * accurate mappable working set.
2229 unsigned int fault_mappable:1;
2232 * Is the object to be mapped as read-only to the GPU
2233 * Only honoured if hardware has relevant pte bit
2235 unsigned long gt_ro:1;
2236 unsigned int cache_level:3;
2237 unsigned int cache_dirty:1;
2239 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2241 unsigned int has_wc_mmap;
2242 unsigned int pin_display;
2244 struct sg_table *pages;
2245 int pages_pin_count;
2247 struct scatterlist *sg;
2252 /** Breadcrumb of last rendering to the buffer.
2253 * There can only be one writer, but we allow for multiple readers.
2254 * If there is a writer that necessarily implies that all other
2255 * read requests are complete - but we may only be lazily clearing
2256 * the read requests. A read request is naturally the most recent
2257 * request on a ring, so we may have two different write and read
2258 * requests on one ring where the write request is older than the
2259 * read request. This allows for the CPU to read from an active
2260 * buffer by only waiting for the write to complete.
2262 struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES];
2263 struct drm_i915_gem_request *last_write_req;
2264 /** Breadcrumb of last fenced GPU access to the buffer. */
2265 struct drm_i915_gem_request *last_fenced_req;
2267 /** Current tiling stride for the object, if it's tiled. */
2270 /** References from framebuffers, locks out tiling changes. */
2271 unsigned long framebuffer_references;
2273 /** Record of address bit 17 of each page at last unbind. */
2274 unsigned long *bit_17;
2277 /** for phy allocated objects */
2278 struct drm_dma_handle *phys_handle;
2280 struct i915_gem_userptr {
2282 unsigned read_only :1;
2283 unsigned workers :4;
2284 #define I915_GEM_USERPTR_MAX_WORKERS 15
2286 struct i915_mm_struct *mm;
2287 struct i915_mmu_object *mmu_object;
2288 struct work_struct *work;
2292 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2295 i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
2297 return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
2301 * Optimised SGL iterator for GEM objects
2303 static __always_inline struct sgt_iter {
2304 struct scatterlist *sgp;
2311 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2312 struct sgt_iter s = { .sgp = sgl };
2315 s.max = s.curr = s.sgp->offset;
2316 s.max += s.sgp->length;
2318 s.dma = sg_dma_address(s.sgp);
2320 s.pfn = page_to_pfn(sg_page(s.sgp));
2327 * __sg_next - return the next scatterlist entry in a list
2328 * @sg: The current sg entry
2331 * If the entry is the last, return NULL; otherwise, step to the next
2332 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2333 * otherwise just return the pointer to the current element.
2335 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2337 #ifdef CONFIG_DEBUG_SG
2338 BUG_ON(sg->sg_magic != SG_MAGIC);
2340 return sg_is_last(sg) ? NULL :
2341 likely(!sg_is_chain(++sg)) ? sg :
2346 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2347 * @__dmap: DMA address (output)
2348 * @__iter: 'struct sgt_iter' (iterator state, internal)
2349 * @__sgt: sg_table to iterate over (input)
2351 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2352 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2353 ((__dmap) = (__iter).dma + (__iter).curr); \
2354 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2355 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2358 * for_each_sgt_page - iterate over the pages of the given sg_table
2359 * @__pp: page pointer (output)
2360 * @__iter: 'struct sgt_iter' (iterator state, internal)
2361 * @__sgt: sg_table to iterate over (input)
2363 #define for_each_sgt_page(__pp, __iter, __sgt) \
2364 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2365 ((__pp) = (__iter).pfn == 0 ? NULL : \
2366 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2367 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2368 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2371 * Request queue structure.
2373 * The request queue allows us to note sequence numbers that have been emitted
2374 * and may be associated with active buffers to be retired.
2376 * By keeping this list, we can avoid having to do questionable sequence
2377 * number comparisons on buffer last_read|write_seqno. It also allows an
2378 * emission time to be associated with the request for tracking how far ahead
2379 * of the GPU the submission is.
2381 * The requests are reference counted, so upon creation they should have an
2382 * initial reference taken using kref_init
2384 struct drm_i915_gem_request {
2387 /** On Which ring this request was generated */
2388 struct drm_i915_private *i915;
2389 struct intel_engine_cs *engine;
2390 struct intel_signal_node signaling;
2392 /** GEM sequence number associated with the previous request,
2393 * when the HWS breadcrumb is equal to this the GPU is processing
2398 /** GEM sequence number associated with this request,
2399 * when the HWS breadcrumb is equal or greater than this the GPU
2400 * has finished processing this request.
2404 /** Position in the ringbuffer of the start of the request */
2408 * Position in the ringbuffer of the start of the postfix.
2409 * This is required to calculate the maximum available ringbuffer
2410 * space without overwriting the postfix.
2414 /** Position in the ringbuffer of the end of the whole request */
2417 /** Preallocate space in the ringbuffer for the emitting the request */
2421 * Context and ring buffer related to this request
2422 * Contexts are refcounted, so when this request is associated with a
2423 * context, we must increment the context's refcount, to guarantee that
2424 * it persists while any request is linked to it. Requests themselves
2425 * are also refcounted, so the request will only be freed when the last
2426 * reference to it is dismissed, and the code in
2427 * i915_gem_request_free() will then decrement the refcount on the
2430 struct i915_gem_context *ctx;
2431 struct intel_ringbuffer *ringbuf;
2434 * Context related to the previous request.
2435 * As the contexts are accessed by the hardware until the switch is
2436 * completed to a new context, the hardware may still be writing
2437 * to the context object after the breadcrumb is visible. We must
2438 * not unpin/unbind/prune that object whilst still active and so
2439 * we keep the previous context pinned until the following (this)
2440 * request is retired.
2442 struct i915_gem_context *previous_context;
2444 /** Batch buffer related to this request if any (used for
2445 error state dump only) */
2446 struct drm_i915_gem_object *batch_obj;
2448 /** Time at which this request was emitted, in jiffies. */
2449 unsigned long emitted_jiffies;
2451 /** global list entry for this request */
2452 struct list_head list;
2454 struct drm_i915_file_private *file_priv;
2455 /** file_priv list entry for this request */
2456 struct list_head client_list;
2458 /** process identifier submitting this request */
2462 * The ELSP only accepts two elements at a time, so we queue
2463 * context/tail pairs on a given queue (ring->execlist_queue) until the
2464 * hardware is available. The queue serves a double purpose: we also use
2465 * it to keep track of the up to 2 contexts currently in the hardware
2466 * (usually one in execution and the other queued up by the GPU): We
2467 * only remove elements from the head of the queue when the hardware
2468 * informs us that an element has been completed.
2470 * All accesses to the queue are mediated by a spinlock
2471 * (ring->execlist_lock).
2474 /** Execlist link in the submission queue.*/
2475 struct list_head execlist_link;
2477 /** Execlists no. of times this request has been sent to the ELSP */
2480 /** Execlists context hardware id. */
2484 struct drm_i915_gem_request * __must_check
2485 i915_gem_request_alloc(struct intel_engine_cs *engine,
2486 struct i915_gem_context *ctx);
2487 void i915_gem_request_free(struct kref *req_ref);
2488 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2489 struct drm_file *file);
2491 static inline uint32_t
2492 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2494 return req ? req->seqno : 0;
2497 static inline struct intel_engine_cs *
2498 i915_gem_request_get_engine(struct drm_i915_gem_request *req)
2500 return req ? req->engine : NULL;
2503 static inline struct drm_i915_gem_request *
2504 i915_gem_request_reference(struct drm_i915_gem_request *req)
2507 kref_get(&req->ref);
2512 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2514 kref_put(&req->ref, i915_gem_request_free);
2517 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2518 struct drm_i915_gem_request *src)
2521 i915_gem_request_reference(src);
2524 i915_gem_request_unreference(*pdst);
2530 * XXX: i915_gem_request_completed should be here but currently needs the
2531 * definition of i915_seqno_passed() which is below. It will be moved in
2532 * a later patch when the call to i915_seqno_passed() is obsoleted...
2536 * A command that requires special handling by the command parser.
2538 struct drm_i915_cmd_descriptor {
2540 * Flags describing how the command parser processes the command.
2542 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2543 * a length mask if not set
2544 * CMD_DESC_SKIP: The command is allowed but does not follow the
2545 * standard length encoding for the opcode range in
2547 * CMD_DESC_REJECT: The command is never allowed
2548 * CMD_DESC_REGISTER: The command should be checked against the
2549 * register whitelist for the appropriate ring
2550 * CMD_DESC_MASTER: The command is allowed if the submitting process
2554 #define CMD_DESC_FIXED (1<<0)
2555 #define CMD_DESC_SKIP (1<<1)
2556 #define CMD_DESC_REJECT (1<<2)
2557 #define CMD_DESC_REGISTER (1<<3)
2558 #define CMD_DESC_BITMASK (1<<4)
2559 #define CMD_DESC_MASTER (1<<5)
2562 * The command's unique identification bits and the bitmask to get them.
2563 * This isn't strictly the opcode field as defined in the spec and may
2564 * also include type, subtype, and/or subop fields.
2572 * The command's length. The command is either fixed length (i.e. does
2573 * not include a length field) or has a length field mask. The flag
2574 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2575 * a length mask. All command entries in a command table must include
2576 * length information.
2584 * Describes where to find a register address in the command to check
2585 * against the ring's register whitelist. Only valid if flags has the
2586 * CMD_DESC_REGISTER bit set.
2588 * A non-zero step value implies that the command may access multiple
2589 * registers in sequence (e.g. LRI), in that case step gives the
2590 * distance in dwords between individual offset fields.
2598 #define MAX_CMD_DESC_BITMASKS 3
2600 * Describes command checks where a particular dword is masked and
2601 * compared against an expected value. If the command does not match
2602 * the expected value, the parser rejects it. Only valid if flags has
2603 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2606 * If the check specifies a non-zero condition_mask then the parser
2607 * only performs the check when the bits specified by condition_mask
2614 u32 condition_offset;
2616 } bits[MAX_CMD_DESC_BITMASKS];
2620 * A table of commands requiring special handling by the command parser.
2622 * Each ring has an array of tables. Each table consists of an array of command
2623 * descriptors, which must be sorted with command opcodes in ascending order.
2625 struct drm_i915_cmd_table {
2626 const struct drm_i915_cmd_descriptor *table;
2630 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2631 #define __I915__(p) ({ \
2632 struct drm_i915_private *__p; \
2633 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2634 __p = (struct drm_i915_private *)p; \
2635 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2636 __p = to_i915((struct drm_device *)p); \
2641 #define INTEL_INFO(p) (&__I915__(p)->info)
2642 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2643 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2645 #define REVID_FOREVER 0xff
2646 #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
2648 #define GEN_FOREVER (0)
2650 * Returns true if Gen is in inclusive range [Start, End].
2652 * Use GEN_FOREVER for unbound start and or end.
2654 #define IS_GEN(p, s, e) ({ \
2655 unsigned int __s = (s), __e = (e); \
2656 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2657 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2658 if ((__s) != GEN_FOREVER) \
2660 if ((__e) == GEN_FOREVER) \
2661 __e = BITS_PER_LONG - 1; \
2664 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2668 * Return true if revision is in range [since,until] inclusive.
2670 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2672 #define IS_REVID(p, since, until) \
2673 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2675 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2676 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2677 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2678 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2679 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2680 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2681 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2682 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2683 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2684 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2685 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2686 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2687 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2688 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2689 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2690 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2691 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2692 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2693 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2694 INTEL_DEVID(dev) == 0x0152 || \
2695 INTEL_DEVID(dev) == 0x015a)
2696 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2697 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2698 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2699 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
2700 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2701 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2702 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2703 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2704 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2705 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2706 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2707 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2708 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2709 (INTEL_DEVID(dev) & 0xf) == 0xe))
2710 /* ULX machines are also considered ULT. */
2711 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2712 (INTEL_DEVID(dev) & 0xf) == 0xe)
2713 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2714 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2715 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2716 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2717 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2718 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2719 /* ULX machines are also considered ULT. */
2720 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2721 INTEL_DEVID(dev) == 0x0A1E)
2722 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2723 INTEL_DEVID(dev) == 0x1913 || \
2724 INTEL_DEVID(dev) == 0x1916 || \
2725 INTEL_DEVID(dev) == 0x1921 || \
2726 INTEL_DEVID(dev) == 0x1926)
2727 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2728 INTEL_DEVID(dev) == 0x1915 || \
2729 INTEL_DEVID(dev) == 0x191E)
2730 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2731 INTEL_DEVID(dev) == 0x5913 || \
2732 INTEL_DEVID(dev) == 0x5916 || \
2733 INTEL_DEVID(dev) == 0x5921 || \
2734 INTEL_DEVID(dev) == 0x5926)
2735 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2736 INTEL_DEVID(dev) == 0x5915 || \
2737 INTEL_DEVID(dev) == 0x591E)
2738 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2739 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2740 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2741 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2743 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2745 #define SKL_REVID_A0 0x0
2746 #define SKL_REVID_B0 0x1
2747 #define SKL_REVID_C0 0x2
2748 #define SKL_REVID_D0 0x3
2749 #define SKL_REVID_E0 0x4
2750 #define SKL_REVID_F0 0x5
2751 #define SKL_REVID_G0 0x6
2752 #define SKL_REVID_H0 0x7
2754 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2756 #define BXT_REVID_A0 0x0
2757 #define BXT_REVID_A1 0x1
2758 #define BXT_REVID_B0 0x3
2759 #define BXT_REVID_C0 0x9
2761 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2763 #define KBL_REVID_A0 0x0
2764 #define KBL_REVID_B0 0x1
2765 #define KBL_REVID_C0 0x2
2766 #define KBL_REVID_D0 0x3
2767 #define KBL_REVID_E0 0x4
2769 #define IS_KBL_REVID(p, since, until) \
2770 (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2773 * The genX designation typically refers to the render engine, so render
2774 * capability related checks should use IS_GEN, while display and other checks
2775 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2778 #define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
2779 #define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
2780 #define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
2781 #define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
2782 #define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
2783 #define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
2784 #define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
2785 #define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
2787 #define ENGINE_MASK(id) BIT(id)
2788 #define RENDER_RING ENGINE_MASK(RCS)
2789 #define BSD_RING ENGINE_MASK(VCS)
2790 #define BLT_RING ENGINE_MASK(BCS)
2791 #define VEBOX_RING ENGINE_MASK(VECS)
2792 #define BSD2_RING ENGINE_MASK(VCS2)
2793 #define ALL_ENGINES (~0)
2795 #define HAS_ENGINE(dev_priv, id) \
2796 (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2798 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2799 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2800 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2801 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2803 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2804 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2805 #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2806 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2808 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2810 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2811 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2812 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2813 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2814 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2816 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2817 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2819 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2820 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2822 /* WaRsDisableCoarsePowerGating:skl,bxt */
2823 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2824 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2825 IS_SKL_GT3(dev_priv) || \
2826 IS_SKL_GT4(dev_priv))
2829 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2830 * even when in MSI mode. This results in spurious interrupt warnings if the
2831 * legacy irq no. is shared with another device. The kernel then disables that
2832 * interrupt source and so prevents the other device from working properly.
2834 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2835 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2837 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2838 * rows, which changed the alignment requirements and fence programming.
2840 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2842 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2843 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2845 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2846 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2847 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2849 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2851 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2852 INTEL_INFO(dev)->gen >= 9)
2854 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2855 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2856 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2857 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2858 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2859 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2860 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2861 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2862 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2863 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2864 #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
2866 #define HAS_CSR(dev) (IS_GEN9(dev))
2869 * For now, anything with a GuC requires uCode loading, and then supports
2870 * command submission once loaded. But these are logically independent
2871 * properties, so we have separate macros to test them.
2873 #define HAS_GUC(dev) (IS_GEN9(dev))
2874 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2875 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2877 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2878 INTEL_INFO(dev)->gen >= 8)
2880 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2881 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2884 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2886 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2887 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2888 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2889 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2890 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2891 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2892 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2893 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2894 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2895 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2896 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2897 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2899 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2900 #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2901 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2902 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2903 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2904 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2905 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2906 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2907 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2908 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2910 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2911 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2913 /* DPF == dynamic parity feature */
2914 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2915 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2917 #define GT_FREQUENCY_MULTIPLIER 50
2918 #define GEN9_FREQ_SCALER 3
2920 #include "i915_trace.h"
2922 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2924 #ifdef CONFIG_INTEL_IOMMU
2925 if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
2931 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2932 extern int i915_resume_switcheroo(struct drm_device *dev);
2934 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2939 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2940 const char *fmt, ...);
2942 #define i915_report_error(dev_priv, fmt, ...) \
2943 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2945 #ifdef CONFIG_COMPAT
2946 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2949 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2950 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2951 extern int i915_reset(struct drm_i915_private *dev_priv);
2952 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2953 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2954 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2955 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2956 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2957 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2958 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2960 /* intel_hotplug.c */
2961 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2962 u32 pin_mask, u32 long_mask);
2963 void intel_hpd_init(struct drm_i915_private *dev_priv);
2964 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2965 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2966 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2967 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2968 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2971 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2973 unsigned long delay;
2975 if (unlikely(!i915.enable_hangcheck))
2978 /* Don't continually defer the hangcheck so that it is always run at
2979 * least once after work has been scheduled on any ring. Otherwise,
2980 * we will ignore a hung ring if a second ring is kept busy.
2983 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2984 queue_delayed_work(system_long_wq,
2985 &dev_priv->gpu_error.hangcheck_work, delay);
2989 void i915_handle_error(struct drm_i915_private *dev_priv,
2991 const char *fmt, ...);
2993 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2994 int intel_irq_install(struct drm_i915_private *dev_priv);
2995 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2997 extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
2998 extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2999 bool restore_forcewake);
3000 extern void intel_uncore_init(struct drm_i915_private *dev_priv);
3001 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
3002 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
3003 extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
3004 extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
3006 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
3007 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
3008 enum forcewake_domains domains);
3009 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
3010 enum forcewake_domains domains);
3011 /* Like above but the caller must manage the uncore.lock itself.
3012 * Must be used with I915_READ_FW and friends.
3014 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
3015 enum forcewake_domains domains);
3016 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
3017 enum forcewake_domains domains);
3018 u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);
3020 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
3022 int intel_wait_for_register(struct drm_i915_private *dev_priv,
3026 const unsigned long timeout_ms);
3027 int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
3031 const unsigned long timeout_ms);
3033 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
3035 return dev_priv->gvt.initialized;
3038 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3040 return dev_priv->vgpu.active;
3044 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3048 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3051 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
3052 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3053 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
3056 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
3057 uint32_t interrupt_mask,
3058 uint32_t enabled_irq_mask);
3060 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3062 ilk_update_display_irq(dev_priv, bits, bits);
3065 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
3067 ilk_update_display_irq(dev_priv, bits, 0);
3069 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
3071 uint32_t interrupt_mask,
3072 uint32_t enabled_irq_mask);
3073 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
3074 enum pipe pipe, uint32_t bits)
3076 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
3078 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
3079 enum pipe pipe, uint32_t bits)
3081 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
3083 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
3084 uint32_t interrupt_mask,
3085 uint32_t enabled_irq_mask);
3087 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3089 ibx_display_interrupt_update(dev_priv, bits, bits);
3092 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
3094 ibx_display_interrupt_update(dev_priv, bits, 0);
3098 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
3099 struct drm_file *file_priv);
3100 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
3101 struct drm_file *file_priv);
3102 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
3103 struct drm_file *file_priv);
3104 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
3105 struct drm_file *file_priv);
3106 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
3107 struct drm_file *file_priv);
3108 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
3109 struct drm_file *file_priv);
3110 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
3111 struct drm_file *file_priv);
3112 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
3113 struct drm_i915_gem_request *req);
3114 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
3115 struct drm_i915_gem_execbuffer2 *args,
3116 struct list_head *vmas);
3117 int i915_gem_execbuffer(struct drm_device *dev, void *data,
3118 struct drm_file *file_priv);
3119 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
3120 struct drm_file *file_priv);
3121 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3122 struct drm_file *file_priv);
3123 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3124 struct drm_file *file);
3125 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3126 struct drm_file *file);
3127 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3128 struct drm_file *file_priv);
3129 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3130 struct drm_file *file_priv);
3131 int i915_gem_set_tiling(struct drm_device *dev, void *data,
3132 struct drm_file *file_priv);
3133 int i915_gem_get_tiling(struct drm_device *dev, void *data,
3134 struct drm_file *file_priv);
3135 void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3136 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
3137 struct drm_file *file);
3138 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
3139 struct drm_file *file_priv);
3140 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
3141 struct drm_file *file_priv);
3142 void i915_gem_load_init(struct drm_device *dev);
3143 void i915_gem_load_cleanup(struct drm_device *dev);
3144 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3145 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
3147 void *i915_gem_object_alloc(struct drm_device *dev);
3148 void i915_gem_object_free(struct drm_i915_gem_object *obj);
3149 void i915_gem_object_init(struct drm_i915_gem_object *obj,
3150 const struct drm_i915_gem_object_ops *ops);
3151 struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
3153 struct drm_i915_gem_object *i915_gem_object_create_from_data(
3154 struct drm_device *dev, const void *data, size_t size);
3155 void i915_gem_free_object(struct drm_gem_object *obj);
3156 void i915_gem_vma_destroy(struct i915_vma *vma);
3158 /* Flags used by pin/bind&friends. */
3159 #define PIN_MAPPABLE (1<<0)
3160 #define PIN_NONBLOCK (1<<1)
3161 #define PIN_GLOBAL (1<<2)
3162 #define PIN_OFFSET_BIAS (1<<3)
3163 #define PIN_USER (1<<4)
3164 #define PIN_UPDATE (1<<5)
3165 #define PIN_ZONE_4G (1<<6)
3166 #define PIN_HIGH (1<<7)
3167 #define PIN_OFFSET_FIXED (1<<8)
3168 #define PIN_OFFSET_MASK (~4095)
3170 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3171 struct i915_address_space *vm,
3175 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
3176 const struct i915_ggtt_view *view,
3180 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3182 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
3183 int __must_check i915_vma_unbind(struct i915_vma *vma);
3185 * BEWARE: Do not use the function below unless you can _absolutely_
3186 * _guarantee_ VMA in question is _not in use_ anywhere.
3188 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
3189 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
3190 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
3191 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3193 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3194 int *needs_clflush);
3196 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3198 static inline int __sg_page_count(struct scatterlist *sg)
3200 return sg->length >> PAGE_SHIFT;
3204 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);
3206 static inline dma_addr_t
3207 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n)
3209 if (n < obj->get_page.last) {
3210 obj->get_page.sg = obj->pages->sgl;
3211 obj->get_page.last = 0;
3214 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3215 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3216 if (unlikely(sg_is_chain(obj->get_page.sg)))
3217 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3220 return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT);
3223 static inline struct page *
3224 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3226 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
3229 if (n < obj->get_page.last) {
3230 obj->get_page.sg = obj->pages->sgl;
3231 obj->get_page.last = 0;
3234 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
3235 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
3236 if (unlikely(sg_is_chain(obj->get_page.sg)))
3237 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
3240 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3243 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3245 BUG_ON(obj->pages == NULL);
3246 obj->pages_pin_count++;
3249 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3251 BUG_ON(obj->pages_pin_count == 0);
3252 obj->pages_pin_count--;
3256 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3257 * @obj - the object to map into kernel address space
3259 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3260 * pages and then returns a contiguous mapping of the backing storage into
3261 * the kernel address space.
3263 * The caller must hold the struct_mutex, and is responsible for calling
3264 * i915_gem_object_unpin_map() when the mapping is no longer required.
3266 * Returns the pointer through which to access the mapped object, or an
3267 * ERR_PTR() on error.
3269 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj);
3272 * i915_gem_object_unpin_map - releases an earlier mapping
3273 * @obj - the object to unmap
3275 * After pinning the object and mapping its pages, once you are finished
3276 * with your access, call i915_gem_object_unpin_map() to release the pin
3277 * upon the mapping. Once the pin count reaches zero, that mapping may be
3280 * The caller must hold the struct_mutex.
3282 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3284 lockdep_assert_held(&obj->base.dev->struct_mutex);
3285 i915_gem_object_unpin_pages(obj);
3288 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3289 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3290 struct intel_engine_cs *to,
3291 struct drm_i915_gem_request **to_req);
3292 void i915_vma_move_to_active(struct i915_vma *vma,
3293 struct drm_i915_gem_request *req);
3294 int i915_gem_dumb_create(struct drm_file *file_priv,
3295 struct drm_device *dev,
3296 struct drm_mode_create_dumb *args);
3297 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3298 uint32_t handle, uint64_t *offset);
3300 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3301 struct drm_i915_gem_object *new,
3302 unsigned frontbuffer_bits);
3305 * Returns true if seq1 is later than seq2.
3308 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
3310 return (int32_t)(seq1 - seq2) >= 0;
3313 static inline bool i915_gem_request_started(const struct drm_i915_gem_request *req)
3315 return i915_seqno_passed(intel_engine_get_seqno(req->engine),
3316 req->previous_seqno);
3319 static inline bool i915_gem_request_completed(const struct drm_i915_gem_request *req)
3321 return i915_seqno_passed(intel_engine_get_seqno(req->engine),
3325 bool __i915_spin_request(const struct drm_i915_gem_request *request,
3326 int state, unsigned long timeout_us);
3327 static inline bool i915_spin_request(const struct drm_i915_gem_request *request,
3328 int state, unsigned long timeout_us)
3330 return (i915_gem_request_started(request) &&
3331 __i915_spin_request(request, state, timeout_us));
3334 int __must_check i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno);
3335 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3337 struct drm_i915_gem_request *
3338 i915_gem_find_active_request(struct intel_engine_cs *engine);
3340 void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3341 void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
3343 static inline u32 i915_reset_counter(struct i915_gpu_error *error)
3345 return atomic_read(&error->reset_counter);
3348 static inline bool __i915_reset_in_progress(u32 reset)
3350 return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
3353 static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
3355 return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3358 static inline bool __i915_terminally_wedged(u32 reset)
3360 return unlikely(reset & I915_WEDGED);
3363 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
3365 return __i915_reset_in_progress(i915_reset_counter(error));
3368 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3370 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
3373 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3375 return __i915_terminally_wedged(i915_reset_counter(error));
3378 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3380 return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
3383 void i915_gem_reset(struct drm_device *dev);
3384 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3385 int __must_check i915_gem_init(struct drm_device *dev);
3386 int i915_gem_init_engines(struct drm_device *dev);
3387 int __must_check i915_gem_init_hw(struct drm_device *dev);
3388 void i915_gem_init_swizzling(struct drm_device *dev);
3389 void i915_gem_cleanup_engines(struct drm_device *dev);
3390 int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv);
3391 int __must_check i915_gem_suspend(struct drm_device *dev);
3392 void __i915_add_request(struct drm_i915_gem_request *req,
3393 struct drm_i915_gem_object *batch_obj,
3395 #define i915_add_request(req) \
3396 __i915_add_request(req, NULL, true)
3397 #define i915_add_request_no_flush(req) \
3398 __i915_add_request(req, NULL, false)
3399 int __i915_wait_request(struct drm_i915_gem_request *req,
3402 struct intel_rps_client *rps);
3403 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3404 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3406 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3409 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3412 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3414 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3416 const struct i915_ggtt_view *view);
3417 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3418 const struct i915_ggtt_view *view);
3419 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3421 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3422 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3425 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3427 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3428 int tiling_mode, bool fenced);
3430 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3431 enum i915_cache_level cache_level);
3433 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3434 struct dma_buf *dma_buf);
3436 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3437 struct drm_gem_object *gem_obj, int flags);
3439 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3440 const struct i915_ggtt_view *view);
3441 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3442 struct i915_address_space *vm);
3444 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3446 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3449 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3450 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3451 const struct i915_ggtt_view *view);
3452 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3453 struct i915_address_space *vm);
3456 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3457 struct i915_address_space *vm);
3459 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3460 const struct i915_ggtt_view *view);
3463 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3464 struct i915_address_space *vm);
3466 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3467 const struct i915_ggtt_view *view);
3469 static inline struct i915_vma *
3470 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3472 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3474 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3476 /* Some GGTT VM helpers */
3477 static inline struct i915_hw_ppgtt *
3478 i915_vm_to_ppgtt(struct i915_address_space *vm)
3480 return container_of(vm, struct i915_hw_ppgtt, base);
3484 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3486 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3490 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj);
3492 static inline int __must_check
3493 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3497 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3498 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3500 return i915_gem_object_pin(obj, &ggtt->base,
3501 alignment, flags | PIN_GLOBAL);
3504 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3505 const struct i915_ggtt_view *view);
3507 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3509 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3512 /* i915_gem_fence.c */
3513 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3514 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3516 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3517 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3519 void i915_gem_restore_fences(struct drm_device *dev);
3521 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3522 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3523 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3525 /* i915_gem_context.c */
3526 int __must_check i915_gem_context_init(struct drm_device *dev);
3527 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3528 void i915_gem_context_fini(struct drm_device *dev);
3529 void i915_gem_context_reset(struct drm_device *dev);
3530 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3531 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3532 int i915_switch_context(struct drm_i915_gem_request *req);
3533 void i915_gem_context_free(struct kref *ctx_ref);
3534 struct drm_i915_gem_object *
3535 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3536 struct i915_gem_context *
3537 i915_gem_context_create_gvt(struct drm_device *dev);
3539 static inline struct i915_gem_context *
3540 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3542 struct i915_gem_context *ctx;
3544 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3546 ctx = idr_find(&file_priv->context_idr, id);
3548 return ERR_PTR(-ENOENT);
3553 static inline void i915_gem_context_reference(struct i915_gem_context *ctx)
3555 kref_get(&ctx->ref);
3558 static inline void i915_gem_context_unreference(struct i915_gem_context *ctx)
3560 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3561 kref_put(&ctx->ref, i915_gem_context_free);
3564 static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3566 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3569 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3570 struct drm_file *file);
3571 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3572 struct drm_file *file);
3573 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3574 struct drm_file *file_priv);
3575 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3576 struct drm_file *file_priv);
3577 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
3578 struct drm_file *file);
3580 /* i915_gem_evict.c */
3581 int __must_check i915_gem_evict_something(struct drm_device *dev,
3582 struct i915_address_space *vm,
3585 unsigned cache_level,
3586 unsigned long start,
3589 int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3590 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3592 /* belongs in i915_gem_gtt.h */
3593 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3596 if (INTEL_GEN(dev_priv) < 6)
3597 intel_gtt_chipset_flush();
3600 /* i915_gem_stolen.c */
3601 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3602 struct drm_mm_node *node, u64 size,
3603 unsigned alignment);
3604 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3605 struct drm_mm_node *node, u64 size,
3606 unsigned alignment, u64 start,
3608 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3609 struct drm_mm_node *node);
3610 int i915_gem_init_stolen(struct drm_device *dev);
3611 void i915_gem_cleanup_stolen(struct drm_device *dev);
3612 struct drm_i915_gem_object *
3613 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3614 struct drm_i915_gem_object *
3615 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3620 /* i915_gem_shrinker.c */
3621 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3622 unsigned long target,
3624 #define I915_SHRINK_PURGEABLE 0x1
3625 #define I915_SHRINK_UNBOUND 0x2
3626 #define I915_SHRINK_BOUND 0x4
3627 #define I915_SHRINK_ACTIVE 0x8
3628 #define I915_SHRINK_VMAPS 0x10
3629 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3630 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3631 void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3634 /* i915_gem_tiling.c */
3635 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3637 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3639 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3640 obj->tiling_mode != I915_TILING_NONE;
3643 /* i915_gem_debug.c */
3645 int i915_verify_lists(struct drm_device *dev);
3647 #define i915_verify_lists(dev) 0
3650 /* i915_debugfs.c */
3651 #ifdef CONFIG_DEBUG_FS
3652 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3653 void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
3654 int i915_debugfs_connector_add(struct drm_connector *connector);
3655 void intel_display_crc_init(struct drm_device *dev);
3657 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3658 static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3659 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3661 static inline void intel_display_crc_init(struct drm_device *dev) {}
3664 /* i915_gpu_error.c */
3666 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3667 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3668 const struct i915_error_state_file_priv *error);
3669 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3670 struct drm_i915_private *i915,
3671 size_t count, loff_t pos);
3672 static inline void i915_error_state_buf_release(
3673 struct drm_i915_error_state_buf *eb)
3677 void i915_capture_error_state(struct drm_i915_private *dev_priv,
3679 const char *error_msg);
3680 void i915_error_state_get(struct drm_device *dev,
3681 struct i915_error_state_file_priv *error_priv);
3682 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3683 void i915_destroy_error_state(struct drm_device *dev);
3685 void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
3686 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3688 /* i915_cmd_parser.c */
3689 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3690 int i915_cmd_parser_init_ring(struct intel_engine_cs *engine);
3691 void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine);
3692 bool i915_needs_cmd_parser(struct intel_engine_cs *engine);
3693 int i915_parse_cmds(struct intel_engine_cs *engine,
3694 struct drm_i915_gem_object *batch_obj,
3695 struct drm_i915_gem_object *shadow_batch_obj,
3696 u32 batch_start_offset,
3700 /* i915_suspend.c */
3701 extern int i915_save_state(struct drm_device *dev);
3702 extern int i915_restore_state(struct drm_device *dev);
3705 void i915_setup_sysfs(struct drm_device *dev_priv);
3706 void i915_teardown_sysfs(struct drm_device *dev_priv);
3709 extern int intel_setup_gmbus(struct drm_device *dev);
3710 extern void intel_teardown_gmbus(struct drm_device *dev);
3711 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3714 extern struct i2c_adapter *
3715 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3716 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3717 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3718 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3720 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3722 extern void intel_i2c_reset(struct drm_device *dev);
3725 int intel_bios_init(struct drm_i915_private *dev_priv);
3726 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3727 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3728 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3729 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3730 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3731 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3732 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3733 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3736 /* intel_opregion.c */
3738 extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3739 extern void intel_opregion_register(struct drm_i915_private *dev_priv);
3740 extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3741 extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3742 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3744 extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3746 extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3748 static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3749 static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
3750 static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3751 static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
3755 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3760 intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3764 static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3772 extern void intel_register_dsm_handler(void);
3773 extern void intel_unregister_dsm_handler(void);
3775 static inline void intel_register_dsm_handler(void) { return; }
3776 static inline void intel_unregister_dsm_handler(void) { return; }
3777 #endif /* CONFIG_ACPI */
3779 /* intel_device_info.c */
3780 static inline struct intel_device_info *
3781 mkwrite_device_info(struct drm_i915_private *dev_priv)
3783 return (struct intel_device_info *)&dev_priv->info;
3786 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
3787 void intel_device_info_dump(struct drm_i915_private *dev_priv);
3790 extern void intel_modeset_init_hw(struct drm_device *dev);
3791 extern void intel_modeset_init(struct drm_device *dev);
3792 extern void intel_modeset_gem_init(struct drm_device *dev);
3793 extern void intel_modeset_cleanup(struct drm_device *dev);
3794 extern int intel_connector_register(struct drm_connector *);
3795 extern void intel_connector_unregister(struct drm_connector *);
3796 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3797 extern void intel_display_resume(struct drm_device *dev);
3798 extern void i915_redisable_vga(struct drm_device *dev);
3799 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3800 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3801 extern void intel_init_pch_refclk(struct drm_device *dev);
3802 extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3803 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3806 extern bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv);
3807 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3808 struct drm_file *file);
3811 extern struct intel_overlay_error_state *
3812 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3813 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3814 struct intel_overlay_error_state *error);
3816 extern struct intel_display_error_state *
3817 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3818 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3819 struct drm_device *dev,
3820 struct intel_display_error_state *error);
3822 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3823 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3825 /* intel_sideband.c */
3826 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3827 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3828 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3829 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3830 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3831 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3832 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3833 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3834 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3835 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3836 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3837 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3838 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3839 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3840 enum intel_sbi_destination destination);
3841 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3842 enum intel_sbi_destination destination);
3843 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3844 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3846 /* intel_dpio_phy.c */
3847 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3848 u32 deemph_reg_value, u32 margin_reg_value,
3849 bool uniq_trans_scale);
3850 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3852 void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3853 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3854 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3855 void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3857 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3858 u32 demph_reg_value, u32 preemph_reg_value,
3859 u32 uniqtranscale_reg_value, u32 tx3_demph);
3860 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3861 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3862 void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3864 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3865 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3867 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3868 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3870 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3871 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3872 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3873 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3875 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3876 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3877 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3878 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3880 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3881 * will be implemented using 2 32-bit writes in an arbitrary order with
3882 * an arbitrary delay between them. This can cause the hardware to
3883 * act upon the intermediate value, possibly leading to corruption and
3884 * machine death. You have been warned.
3886 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3887 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3889 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3890 u32 upper, lower, old_upper, loop = 0; \
3891 upper = I915_READ(upper_reg); \
3893 old_upper = upper; \
3894 lower = I915_READ(lower_reg); \
3895 upper = I915_READ(upper_reg); \
3896 } while (upper != old_upper && loop++ < 2); \
3897 (u64)upper << 32 | lower; })
3899 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3900 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3902 #define __raw_read(x, s) \
3903 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3906 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3909 #define __raw_write(x, s) \
3910 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3911 i915_reg_t reg, uint##x##_t val) \
3913 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3928 /* These are untraced mmio-accessors that are only valid to be used inside
3929 * criticial sections inside IRQ handlers where forcewake is explicitly
3931 * Think twice, and think again, before using these.
3932 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3933 * intel_uncore_forcewake_irqunlock().
3935 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3936 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3937 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3938 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3940 /* "Broadcast RGB" property */
3941 #define INTEL_BROADCAST_RGB_AUTO 0
3942 #define INTEL_BROADCAST_RGB_FULL 1
3943 #define INTEL_BROADCAST_RGB_LIMITED 2
3945 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3947 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3948 return VLV_VGACNTRL;
3949 else if (INTEL_INFO(dev)->gen >= 5)
3950 return CPU_VGACNTRL;
3955 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3957 unsigned long j = msecs_to_jiffies(m);
3959 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3962 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3964 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3967 static inline unsigned long
3968 timespec_to_jiffies_timeout(const struct timespec *value)
3970 unsigned long j = timespec_to_jiffies(value);
3972 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3976 * If you need to wait X milliseconds between events A and B, but event B
3977 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3978 * when event A happened, then just before event B you call this function and
3979 * pass the timestamp as the first argument, and X as the second argument.
3982 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3984 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3987 * Don't re-read the value of "jiffies" every time since it may change
3988 * behind our back and break the math.
3990 tmp_jiffies = jiffies;
3991 target_jiffies = timestamp_jiffies +
3992 msecs_to_jiffies_timeout(to_wait_ms);
3994 if (time_after(target_jiffies, tmp_jiffies)) {
3995 remaining_jiffies = target_jiffies - tmp_jiffies;
3996 while (remaining_jiffies)
3998 schedule_timeout_uninterruptible(remaining_jiffies);
4001 static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
4003 struct intel_engine_cs *engine = req->engine;
4005 /* Before we do the heavier coherent read of the seqno,
4006 * check the value (hopefully) in the CPU cacheline.
4008 if (i915_gem_request_completed(req))
4011 /* Ensure our read of the seqno is coherent so that we
4012 * do not "miss an interrupt" (i.e. if this is the last
4013 * request and the seqno write from the GPU is not visible
4014 * by the time the interrupt fires, we will see that the
4015 * request is incomplete and go back to sleep awaiting
4016 * another interrupt that will never come.)
4018 * Strictly, we only need to do this once after an interrupt,
4019 * but it is easier and safer to do it every time the waiter
4022 if (engine->irq_seqno_barrier &&
4023 READ_ONCE(engine->breadcrumbs.irq_seqno_bh) == current &&
4024 cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
4025 struct task_struct *tsk;
4027 /* The ordering of irq_posted versus applying the barrier
4028 * is crucial. The clearing of the current irq_posted must
4029 * be visible before we perform the barrier operation,
4030 * such that if a subsequent interrupt arrives, irq_posted
4031 * is reasserted and our task rewoken (which causes us to
4032 * do another __i915_request_irq_complete() immediately
4033 * and reapply the barrier). Conversely, if the clear
4034 * occurs after the barrier, then an interrupt that arrived
4035 * whilst we waited on the barrier would not trigger a
4036 * barrier on the next pass, and the read may not see the
4039 engine->irq_seqno_barrier(engine);
4041 /* If we consume the irq, but we are no longer the bottom-half,
4042 * the real bottom-half may not have serialised their own
4043 * seqno check with the irq-barrier (i.e. may have inspected
4044 * the seqno before we believe it coherent since they see
4045 * irq_posted == false but we are still running).
4048 tsk = READ_ONCE(engine->breadcrumbs.irq_seqno_bh);
4049 if (tsk && tsk != current)
4050 /* Note that if the bottom-half is changed as we
4051 * are sending the wake-up, the new bottom-half will
4052 * be woken by whomever made the change. We only have
4053 * to worry about when we steal the irq-posted for
4056 wake_up_process(tsk);
4059 if (i915_gem_request_completed(req))
4063 /* We need to check whether any gpu reset happened in between
4064 * the request being submitted and now. If a reset has occurred,
4065 * the seqno will have been advance past ours and our request
4066 * is complete. If we are in the process of handling a reset,
4067 * the request is effectively complete as the rendering will
4068 * be discarded, but we need to return in order to drop the
4071 if (i915_reset_in_progress(&req->i915->gpu_error))