drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_ioctl.h>
  46 #include <drm/drm_irq.h>
  47 #include <drm/drm_probe_helper.h>
  48 #include <drm/i915_drm.h>
  49
  50 #include "i915_drv.h"
  51 #include "i915_trace.h"
  52 #include "i915_pmu.h"
  53 #include "i915_reset.h"
  54 #include "i915_query.h"
  55 #include "i915_vgpu.h"
  56 #include "intel_drv.h"
  57 #include "intel_uc.h"
  58 #include "intel_workarounds.h"
  59
  60 static struct drm_driver driver;
  61
  62 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
  63 static unsigned int i915_load_fail_count;
  64
  65 bool __i915_inject_load_failure(const char *func, int line)
  66 {
  67         if (i915_load_fail_count >= i915_modparams.inject_load_failure)
  68                 return false;
  69
  70         if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
  71                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  72                          i915_modparams.inject_load_failure, func, line);
  73                 i915_modparams.inject_load_failure = 0;
  74                 return true;
  75         }
  76
  77         return false;
  78 }
  79
  80 bool i915_error_injected(void)
  81 {
  82         return i915_load_fail_count && !i915_modparams.inject_load_failure;
  83 }
  84
  85 #endif
  86
  87 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  88 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  89                     "providing the dmesg log by booting with drm.debug=0xf"
  90
  91 void
  92 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  93               const char *fmt, ...)
  94 {
  95         static bool shown_bug_once;
  96         struct device *kdev = dev_priv->drm.dev;
  97         bool is_error = level[1] <= KERN_ERR[1];
  98         bool is_debug = level[1] == KERN_DEBUG[1];
  99         struct va_format vaf;
 100         va_list args;
 101
 102         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
 103                 return;
 104
 105         va_start(args, fmt);
 106
 107         vaf.fmt = fmt;
 108         vaf.va = &args;
 109
 110         if (is_error)
 111                 dev_printk(level, kdev, "%pV", &vaf);
 112         else
 113                 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
 114                            __builtin_return_address(0), &vaf);
 115
 116         va_end(args);
 117
 118         if (is_error && !shown_bug_once) {
 119                 /*
 120                  * Ask the user to file a bug report for the error, except
 121                  * if they may have caused the bug by fiddling with unsafe
 122                  * module parameters.
 123                  */
 124                 if (!test_taint(TAINT_USER))
 125                         dev_notice(kdev, "%s", FDO_BUG_MSG);
 126                 shown_bug_once = true;
 127         }
 128 }
 129
 130 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
 131 static enum intel_pch
 132 intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
 133 {
 134         switch (id) {
 135         case INTEL_PCH_IBX_DEVICE_ID_TYPE:
 136                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 137                 WARN_ON(!IS_GEN(dev_priv, 5));
 138                 return PCH_IBX;
 139         case INTEL_PCH_CPT_DEVICE_ID_TYPE:
 140                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 141                 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
 142                 return PCH_CPT;
 143         case INTEL_PCH_PPT_DEVICE_ID_TYPE:
 144                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 145                 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
 146                 /* PantherPoint is CPT compatible */
 147                 return PCH_CPT;
 148         case INTEL_PCH_LPT_DEVICE_ID_TYPE:
 149                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 150                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 151                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 152                 return PCH_LPT;
 153         case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
 154                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 155                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 156                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 157                 return PCH_LPT;
 158         case INTEL_PCH_WPT_DEVICE_ID_TYPE:
 159                 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
 160                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 161                 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
 162                 /* WildcatPoint is LPT compatible */
 163                 return PCH_LPT;
 164         case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
 165                 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
 166                 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
 167                 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
 168                 /* WildcatPoint is LPT compatible */
 169                 return PCH_LPT;
 170         case INTEL_PCH_SPT_DEVICE_ID_TYPE:
 171                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 172                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 173                 return PCH_SPT;
 174         case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
 175                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 176                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
 177                 return PCH_SPT;
 178         case INTEL_PCH_KBP_DEVICE_ID_TYPE:
 179                 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
 180                 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
 181                         !IS_COFFEELAKE(dev_priv));
 182                 return PCH_KBP;
 183         case INTEL_PCH_CNP_DEVICE_ID_TYPE:
 184                 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
 185                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 186                 return PCH_CNP;
 187         case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
 188                 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
 189                 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
 190                 return PCH_CNP;
 191         case INTEL_PCH_CMP_DEVICE_ID_TYPE:
 192                 DRM_DEBUG_KMS("Found Comet Lake PCH (CMP)\n");
 193                 WARN_ON(!IS_COFFEELAKE(dev_priv));
 194                 /* CometPoint is CNP Compatible */
 195                 return PCH_CNP;
 196         case INTEL_PCH_ICP_DEVICE_ID_TYPE:
 197                 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
 198                 WARN_ON(!IS_ICELAKE(dev_priv));
 199                 return PCH_ICP;
 200         default:
 201                 return PCH_NONE;
 202         }
 203 }
 204
 205 static bool intel_is_virt_pch(unsigned short id,
 206                               unsigned short svendor, unsigned short sdevice)
 207 {
 208         return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
 209                 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
 210                 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
 211                  svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 212                  sdevice == PCI_SUBDEVICE_ID_QEMU));
 213 }
 214
 215 static unsigned short
 216 intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
 217 {
 218         unsigned short id = 0;
 219
 220         /*
 221          * In a virtualized passthrough environment we can be in a
 222          * setup where the ISA bridge is not able to be passed through.
 223          * In this case, a south bridge can be emulated and we have to
 224          * make an educated guess as to which PCH is really there.
 225          */
 226
 227         if (IS_ICELAKE(dev_priv))
 228                 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
 229         else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 230                 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
 231         else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
 232                 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
 233         else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
 234                 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
 235         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 236                 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
 237         else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
 238                 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
 239         else if (IS_GEN(dev_priv, 5))
 240                 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
 241
 242         if (id)
 243                 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
 244         else
 245                 DRM_DEBUG_KMS("Assuming no PCH\n");
 246
 247         return id;
 248 }
 249
 250 static void intel_detect_pch(struct drm_i915_private *dev_priv)
 251 {
 252         struct pci_dev *pch = NULL;
 253
 254         /*
 255          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 256          * make graphics device passthrough work easy for VMM, that only
 257          * need to expose ISA bridge to let driver know the real hardware
 258          * underneath. This is a requirement from virtualization team.
 259          *
 260          * In some virtualized environments (e.g. XEN), there is irrelevant
 261          * ISA bridge in the system. To work reliably, we should scan trhough
 262          * all the ISA bridge devices and check for the first match, instead
 263          * of only checking the first one.
 264          */
 265         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 266                 unsigned short id;
 267                 enum intel_pch pch_type;
 268
 269                 if (pch->vendor != PCI_VENDOR_ID_INTEL)
 270                         continue;
 271
 272                 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 273
 274                 pch_type = intel_pch_type(dev_priv, id);
 275                 if (pch_type != PCH_NONE) {
 276                         dev_priv->pch_type = pch_type;
 277                         dev_priv->pch_id = id;
 278                         break;
 279                 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
 280                                          pch->subsystem_device)) {
 281                         id = intel_virt_detect_pch(dev_priv);
 282                         pch_type = intel_pch_type(dev_priv, id);
 283
 284                         /* Sanity check virtual PCH id */
 285                         if (WARN_ON(id && pch_type == PCH_NONE))
 286                                 id = 0;
 287
 288                         dev_priv->pch_type = pch_type;
 289                         dev_priv->pch_id = id;
 290                         break;
 291                 }
 292         }
 293
 294         /*
 295          * Use PCH_NOP (PCH but no South Display) for PCH platforms without
 296          * display.
 297          */
 298         if (pch && !HAS_DISPLAY(dev_priv)) {
 299                 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
 300                 dev_priv->pch_type = PCH_NOP;
 301                 dev_priv->pch_id = 0;
 302         }
 303
 304         if (!pch)
 305                 DRM_DEBUG_KMS("No PCH found.\n");
 306
 307         pci_dev_put(pch);
 308 }
 309
 310 static int i915_getparam_ioctl(struct drm_device *dev, void *data,
 311                                struct drm_file *file_priv)
 312 {
 313         struct drm_i915_private *dev_priv = to_i915(dev);
 314         struct pci_dev *pdev = dev_priv->drm.pdev;
 315         drm_i915_getparam_t *param = data;
 316         int value;
 317
 318         switch (param->param) {
 319         case I915_PARAM_IRQ_ACTIVE:
 320         case I915_PARAM_ALLOW_BATCHBUFFER:
 321         case I915_PARAM_LAST_DISPATCH:
 322         case I915_PARAM_HAS_EXEC_CONSTANTS:
 323                 /* Reject all old ums/dri params. */
 324                 return -ENODEV;
 325         case I915_PARAM_CHIPSET_ID:
 326                 value = pdev->device;
 327                 break;
 328         case I915_PARAM_REVISION:
 329                 value = pdev->revision;
 330                 break;
 331         case I915_PARAM_NUM_FENCES_AVAIL:
 332                 value = dev_priv->num_fence_regs;
 333                 break;
 334         case I915_PARAM_HAS_OVERLAY:
 335                 value = dev_priv->overlay ? 1 : 0;
 336                 break;
 337         case I915_PARAM_HAS_BSD:
 338                 value = !!dev_priv->engine[VCS0];
 339                 break;
 340         case I915_PARAM_HAS_BLT:
 341                 value = !!dev_priv->engine[BCS0];
 342                 break;
 343         case I915_PARAM_HAS_VEBOX:
 344                 value = !!dev_priv->engine[VECS0];
 345                 break;
 346         case I915_PARAM_HAS_BSD2:
 347                 value = !!dev_priv->engine[VCS1];
 348                 break;
 349         case I915_PARAM_HAS_LLC:
 350                 value = HAS_LLC(dev_priv);
 351                 break;
 352         case I915_PARAM_HAS_WT:
 353                 value = HAS_WT(dev_priv);
 354                 break;
 355         case I915_PARAM_HAS_ALIASING_PPGTT:
 356                 value = INTEL_PPGTT(dev_priv);
 357                 break;
 358         case I915_PARAM_HAS_SEMAPHORES:
 359                 value = !!(dev_priv->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
 360                 break;
 361         case I915_PARAM_HAS_SECURE_BATCHES:
 362                 value = capable(CAP_SYS_ADMIN);
 363                 break;
 364         case I915_PARAM_CMD_PARSER_VERSION:
 365                 value = i915_cmd_parser_get_version(dev_priv);
 366                 break;
 367         case I915_PARAM_SUBSLICE_TOTAL:
 368                 value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu);
 369                 if (!value)
 370                         return -ENODEV;
 371                 break;
 372         case I915_PARAM_EU_TOTAL:
 373                 value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
 374                 if (!value)
 375                         return -ENODEV;
 376                 break;
 377         case I915_PARAM_HAS_GPU_RESET:
 378                 value = i915_modparams.enable_hangcheck &&
 379                         intel_has_gpu_reset(dev_priv);
 380                 if (value && intel_has_reset_engine(dev_priv))
 381                         value = 2;
 382                 break;
 383         case I915_PARAM_HAS_RESOURCE_STREAMER:
 384                 value = 0;
 385                 break;
 386         case I915_PARAM_HAS_POOLED_EU:
 387                 value = HAS_POOLED_EU(dev_priv);
 388                 break;
 389         case I915_PARAM_MIN_EU_IN_POOL:
 390                 value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
 391                 break;
 392         case I915_PARAM_HUC_STATUS:
 393                 value = intel_huc_check_status(&dev_priv->huc);
 394                 if (value < 0)
 395                         return value;
 396                 break;
 397         case I915_PARAM_MMAP_GTT_VERSION:
 398                 /* Though we've started our numbering from 1, and so class all
 399                  * earlier versions as 0, in effect their value is undefined as
 400                  * the ioctl will report EINVAL for the unknown param!
 401                  */
 402                 value = i915_gem_mmap_gtt_version();
 403                 break;
 404         case I915_PARAM_HAS_SCHEDULER:
 405                 value = dev_priv->caps.scheduler;
 406                 break;
 407
 408         case I915_PARAM_MMAP_VERSION:
 409                 /* Remember to bump this if the version changes! */
 410         case I915_PARAM_HAS_GEM:
 411         case I915_PARAM_HAS_PAGEFLIPPING:
 412         case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
 413         case I915_PARAM_HAS_RELAXED_FENCING:
 414         case I915_PARAM_HAS_COHERENT_RINGS:
 415         case I915_PARAM_HAS_RELAXED_DELTA:
 416         case I915_PARAM_HAS_GEN7_SOL_RESET:
 417         case I915_PARAM_HAS_WAIT_TIMEOUT:
 418         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 419         case I915_PARAM_HAS_PINNED_BATCHES:
 420         case I915_PARAM_HAS_EXEC_NO_RELOC:
 421         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 422         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 423         case I915_PARAM_HAS_EXEC_SOFTPIN:
 424         case I915_PARAM_HAS_EXEC_ASYNC:
 425         case I915_PARAM_HAS_EXEC_FENCE:
 426         case I915_PARAM_HAS_EXEC_CAPTURE:
 427         case I915_PARAM_HAS_EXEC_BATCH_FIRST:
 428         case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
 429                 /* For the time being all of these are always true;
 430                  * if some supported hardware does not have one of these
 431                  * features this value needs to be provided from
 432                  * INTEL_INFO(), a feature macro, or similar.
 433                  */
 434                 value = 1;
 435                 break;
 436         case I915_PARAM_HAS_CONTEXT_ISOLATION:
 437                 value = intel_engines_has_context_isolation(dev_priv);
 438                 break;
 439         case I915_PARAM_SLICE_MASK:
 440                 value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
 441                 if (!value)
 442                         return -ENODEV;
 443                 break;
 444         case I915_PARAM_SUBSLICE_MASK:
 445                 value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
 446                 if (!value)
 447                         return -ENODEV;
 448                 break;
 449         case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
 450                 value = 1000 * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz;
 451                 break;
 452         case I915_PARAM_MMAP_GTT_COHERENT:
 453                 value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
 454                 break;
 455         default:
 456                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 457                 return -EINVAL;
 458         }
 459
 460         if (put_user(value, param->value))
 461                 return -EFAULT;
 462
 463         return 0;
 464 }
 465
 466 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 467 {
 468         int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
 469
 470         dev_priv->bridge_dev =
 471                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 472         if (!dev_priv->bridge_dev) {
 473                 DRM_ERROR("bridge device not found\n");
 474                 return -1;
 475         }
 476         return 0;
 477 }
 478
 479 /* Allocate space for the MCH regs if needed, return nonzero on error */
 480 static int
 481 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 482 {
 483         int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 484         u32 temp_lo, temp_hi = 0;
 485         u64 mchbar_addr;
 486         int ret;
 487
 488         if (INTEL_GEN(dev_priv) >= 4)
 489                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 490         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 491         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 492
 493         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 494 #ifdef CONFIG_PNP
 495         if (mchbar_addr &&
 496             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 497                 return 0;
 498 #endif
 499
 500         /* Get some space for it */
 501         dev_priv->mch_res.name = "i915 MCHBAR";
 502         dev_priv->mch_res.flags = IORESOURCE_MEM;
 503         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 504                                      &dev_priv->mch_res,
 505                                      MCHBAR_SIZE, MCHBAR_SIZE,
 506                                      PCIBIOS_MIN_MEM,
 507                                      0, pcibios_align_resource,
 508                                      dev_priv->bridge_dev);
 509         if (ret) {
 510                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 511                 dev_priv->mch_res.start = 0;
 512                 return ret;
 513         }
 514
 515         if (INTEL_GEN(dev_priv) >= 4)
 516                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 517                                        upper_32_bits(dev_priv->mch_res.start));
 518
 519         pci_write_config_dword(dev_priv->bridge_dev, reg,
 520                                lower_32_bits(dev_priv->mch_res.start));
 521         return 0;
 522 }
 523
 524 /* Setup MCHBAR if possible, return true if we should disable it again */
 525 static void
 526 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 527 {
 528         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 529         u32 temp;
 530         bool enabled;
 531
 532         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 533                 return;
 534
 535         dev_priv->mchbar_need_disable = false;
 536
 537         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 538                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 539                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 540         } else {
 541                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 542                 enabled = temp & 1;
 543         }
 544
 545         /* If it's already enabled, don't have to do anything */
 546         if (enabled)
 547                 return;
 548
 549         if (intel_alloc_mchbar_resource(dev_priv))
 550                 return;
 551
 552         dev_priv->mchbar_need_disable = true;
 553
 554         /* Space is allocated or reserved, so enable it. */
 555         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 556                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 557                                        temp | DEVEN_MCHBAR_EN);
 558         } else {
 559                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 560                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 561         }
 562 }
 563
 564 static void
 565 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 566 {
 567         int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 568
 569         if (dev_priv->mchbar_need_disable) {
 570                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 571                         u32 deven_val;
 572
 573                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 574                                               &deven_val);
 575                         deven_val &= ~DEVEN_MCHBAR_EN;
 576                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 577                                                deven_val);
 578                 } else {
 579                         u32 mchbar_val;
 580
 581                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 582                                               &mchbar_val);
 583                         mchbar_val &= ~1;
 584                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 585                                                mchbar_val);
 586                 }
 587         }
 588
 589         if (dev_priv->mch_res.start)
 590                 release_resource(&dev_priv->mch_res);
 591 }
 592
 593 /* true = enable decode, false = disable decoder */
 594 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 595 {
 596         struct drm_i915_private *dev_priv = cookie;
 597
 598         intel_modeset_vga_set_state(dev_priv, state);
 599         if (state)
 600                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 601                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 602         else
 603                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 604 }
 605
 606 static int i915_resume_switcheroo(struct drm_device *dev);
 607 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
 608
 609 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 610 {
 611         struct drm_device *dev = pci_get_drvdata(pdev);
 612         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 613
 614         if (state == VGA_SWITCHEROO_ON) {
 615                 pr_info("switched on\n");
 616                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 617                 /* i915 resume handler doesn't set to D0 */
 618                 pci_set_power_state(pdev, PCI_D0);
 619                 i915_resume_switcheroo(dev);
 620                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 621         } else {
 622                 pr_info("switched off\n");
 623                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 624                 i915_suspend_switcheroo(dev, pmm);
 625                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 626         }
 627 }
 628
 629 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 630 {
 631         struct drm_device *dev = pci_get_drvdata(pdev);
 632
 633         /*
 634          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 635          * locking inversion with the driver load path. And the access here is
 636          * completely racy anyway. So don't bother with locking for now.
 637          */
 638         return dev->open_count == 0;
 639 }
 640
 641 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 642         .set_gpu_state = i915_switcheroo_set_state,
 643         .reprobe = NULL,
 644         .can_switch = i915_switcheroo_can_switch,
 645 };
 646
 647 static int i915_load_modeset_init(struct drm_device *dev)
 648 {
 649         struct drm_i915_private *dev_priv = to_i915(dev);
 650         struct pci_dev *pdev = dev_priv->drm.pdev;
 651         int ret;
 652
 653         if (i915_inject_load_failure())
 654                 return -ENODEV;
 655
 656         if (HAS_DISPLAY(dev_priv)) {
 657                 ret = drm_vblank_init(&dev_priv->drm,
 658                                       INTEL_INFO(dev_priv)->num_pipes);
 659                 if (ret)
 660                         goto out;
 661         }
 662
 663         intel_bios_init(dev_priv);
 664
 665         /* If we have > 1 VGA cards, then we need to arbitrate access
 666          * to the common VGA resources.
 667          *
 668          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 669          * then we do not take part in VGA arbitration and the
 670          * vga_client_register() fails with -ENODEV.
 671          */
 672         ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
 673         if (ret && ret != -ENODEV)
 674                 goto out;
 675
 676         intel_register_dsm_handler();
 677
 678         ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
 679         if (ret)
 680                 goto cleanup_vga_client;
 681
 682         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 683         intel_update_rawclk(dev_priv);
 684
 685         intel_power_domains_init_hw(dev_priv, false);
 686
 687         intel_csr_ucode_init(dev_priv);
 688
 689         ret = intel_irq_install(dev_priv);
 690         if (ret)
 691                 goto cleanup_csr;
 692
 693         intel_setup_gmbus(dev_priv);
 694
 695         /* Important: The output setup functions called by modeset_init need
 696          * working irqs for e.g. gmbus and dp aux transfers. */
 697         ret = intel_modeset_init(dev);
 698         if (ret)
 699                 goto cleanup_irq;
 700
 701         ret = i915_gem_init(dev_priv);
 702         if (ret)
 703                 goto cleanup_modeset;
 704
 705         intel_overlay_setup(dev_priv);
 706
 707         if (!HAS_DISPLAY(dev_priv))
 708                 return 0;
 709
 710         ret = intel_fbdev_init(dev);
 711         if (ret)
 712                 goto cleanup_gem;
 713
 714         /* Only enable hotplug handling once the fbdev is fully set up. */
 715         intel_hpd_init(dev_priv);
 716
 717         intel_init_ipc(dev_priv);
 718
 719         return 0;
 720
 721 cleanup_gem:
 722         i915_gem_suspend(dev_priv);
 723         i915_gem_fini(dev_priv);
 724 cleanup_modeset:
 725         intel_modeset_cleanup(dev);
 726 cleanup_irq:
 727         drm_irq_uninstall(dev);
 728         intel_teardown_gmbus(dev_priv);
 729 cleanup_csr:
 730         intel_csr_ucode_fini(dev_priv);
 731         intel_power_domains_fini_hw(dev_priv);
 732         vga_switcheroo_unregister_client(pdev);
 733 cleanup_vga_client:
 734         vga_client_register(pdev, NULL, NULL, NULL);
 735 out:
 736         return ret;
 737 }
 738
 739 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 740 {
 741         struct apertures_struct *ap;
 742         struct pci_dev *pdev = dev_priv->drm.pdev;
 743         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 744         bool primary;
 745         int ret;
 746
 747         ap = alloc_apertures(1);
 748         if (!ap)
 749                 return -ENOMEM;
 750
 751         ap->ranges[0].base = ggtt->gmadr.start;
 752         ap->ranges[0].size = ggtt->mappable_end;
 753
 754         primary =
 755                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 756
 757         ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 758
 759         kfree(ap);
 760
 761         return ret;
 762 }
 763
 764 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 765 {
 766         /*
 767          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 768          * CHV x1 PHY (DP/HDMI D)
 769          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 770          */
 771         if (IS_CHERRYVIEW(dev_priv)) {
 772                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 773                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 774         } else if (IS_VALLEYVIEW(dev_priv)) {
 775                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 776         }
 777 }
 778
 779 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 780 {
 781         /*
 782          * The i915 workqueue is primarily used for batched retirement of
 783          * requests (and thus managing bo) once the task has been completed
 784          * by the GPU. i915_retire_requests() is called directly when we
 785          * need high-priority retirement, such as waiting for an explicit
 786          * bo.
 787          *
 788          * It is also used for periodic low-priority events, such as
 789          * idle-timers and recording error state.
 790          *
 791          * All tasks on the workqueue are expected to acquire the dev mutex
 792          * so there is no point in running more than one instance of the
 793          * workqueue at any time.  Use an ordered one.
 794          */
 795         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 796         if (dev_priv->wq == NULL)
 797                 goto out_err;
 798
 799         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 800         if (dev_priv->hotplug.dp_wq == NULL)
 801                 goto out_free_wq;
 802
 803         return 0;
 804
 805 out_free_wq:
 806         destroy_workqueue(dev_priv->wq);
 807 out_err:
 808         DRM_ERROR("Failed to allocate workqueues.\n");
 809
 810         return -ENOMEM;
 811 }
 812
 813 static void i915_engines_cleanup(struct drm_i915_private *i915)
 814 {
 815         struct intel_engine_cs *engine;
 816         enum intel_engine_id id;
 817
 818         for_each_engine(engine, i915, id)
 819                 kfree(engine);
 820 }
 821
 822 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 823 {
 824         destroy_workqueue(dev_priv->hotplug.dp_wq);
 825         destroy_workqueue(dev_priv->wq);
 826 }
 827
 828 /*
 829  * We don't keep the workarounds for pre-production hardware, so we expect our
 830  * driver to fail on these machines in one way or another. A little warning on
 831  * dmesg may help both the user and the bug triagers.
 832  *
 833  * Our policy for removing pre-production workarounds is to keep the
 834  * current gen workarounds as a guide to the bring-up of the next gen
 835  * (workarounds have a habit of persisting!). Anything older than that
 836  * should be removed along with the complications they introduce.
 837  */
 838 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 839 {
 840         bool pre = false;
 841
 842         pre |= IS_HSW_EARLY_SDV(dev_priv);
 843         pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
 844         pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
 845         pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
 846
 847         if (pre) {
 848                 DRM_ERROR("This is a pre-production stepping. "
 849                           "It may not be fully functional.\n");
 850                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 851         }
 852 }
 853
 854 /**
 855  * i915_driver_init_early - setup state not requiring device access
 856  * @dev_priv: device private
 857  *
 858  * Initialize everything that is a "SW-only" state, that is state not
 859  * requiring accessing the device or exposing the driver via kernel internal
 860  * or userspace interfaces. Example steps belonging here: lock initialization,
 861  * system memory allocation, setting up device specific attributes and
 862  * function hooks not requiring accessing the device.
 863  */
 864 static int i915_driver_init_early(struct drm_i915_private *dev_priv)
 865 {
 866         int ret = 0;
 867
 868         if (i915_inject_load_failure())
 869                 return -ENODEV;
 870
 871         spin_lock_init(&dev_priv->irq_lock);
 872         spin_lock_init(&dev_priv->gpu_error.lock);
 873         mutex_init(&dev_priv->backlight_lock);
 874         spin_lock_init(&dev_priv->uncore.lock);
 875
 876         mutex_init(&dev_priv->sb_lock);
 877         mutex_init(&dev_priv->av_mutex);
 878         mutex_init(&dev_priv->wm.wm_mutex);
 879         mutex_init(&dev_priv->pps_mutex);
 880         mutex_init(&dev_priv->hdcp_comp_mutex);
 881
 882         i915_memcpy_init_early(dev_priv);
 883         intel_runtime_pm_init_early(dev_priv);
 884
 885         ret = i915_workqueues_init(dev_priv);
 886         if (ret < 0)
 887                 goto err_engines;
 888
 889         ret = i915_gem_init_early(dev_priv);
 890         if (ret < 0)
 891                 goto err_workqueues;
 892
 893         /* This must be called before any calls to HAS_PCH_* */
 894         intel_detect_pch(dev_priv);
 895
 896         intel_wopcm_init_early(&dev_priv->wopcm);
 897         intel_uc_init_early(dev_priv);
 898         intel_pm_setup(dev_priv);
 899         intel_init_dpio(dev_priv);
 900         ret = intel_power_domains_init(dev_priv);
 901         if (ret < 0)
 902                 goto err_uc;
 903         intel_irq_init(dev_priv);
 904         intel_hangcheck_init(dev_priv);
 905         intel_init_display_hooks(dev_priv);
 906         intel_init_clock_gating_hooks(dev_priv);
 907         intel_init_audio_hooks(dev_priv);
 908         intel_display_crc_init(dev_priv);
 909
 910         intel_detect_preproduction_hw(dev_priv);
 911
 912         return 0;
 913
 914 err_uc:
 915         intel_uc_cleanup_early(dev_priv);
 916         i915_gem_cleanup_early(dev_priv);
 917 err_workqueues:
 918         i915_workqueues_cleanup(dev_priv);
 919 err_engines:
 920         i915_engines_cleanup(dev_priv);
 921         return ret;
 922 }
 923
 924 /**
 925  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 926  * @dev_priv: device private
 927  */
 928 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 929 {
 930         intel_irq_fini(dev_priv);
 931         intel_power_domains_cleanup(dev_priv);
 932         intel_uc_cleanup_early(dev_priv);
 933         i915_gem_cleanup_early(dev_priv);
 934         i915_workqueues_cleanup(dev_priv);
 935         i915_engines_cleanup(dev_priv);
 936 }
 937
 938 static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 939 {
 940         struct pci_dev *pdev = dev_priv->drm.pdev;
 941         int mmio_bar;
 942         int mmio_size;
 943
 944         mmio_bar = IS_GEN(dev_priv, 2) ? 1 : 0;
 945         /*
 946          * Before gen4, the registers and the GTT are behind different BARs.
 947          * However, from gen4 onwards, the registers and the GTT are shared
 948          * in the same BAR, so we want to restrict this ioremap from
 949          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 950          * the register BAR remains the same size for all the earlier
 951          * generations up to Ironlake.
 952          */
 953         if (INTEL_GEN(dev_priv) < 5)
 954                 mmio_size = 512 * 1024;
 955         else
 956                 mmio_size = 2 * 1024 * 1024;
 957         dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 958         if (dev_priv->regs == NULL) {
 959                 DRM_ERROR("failed to map registers\n");
 960
 961                 return -EIO;
 962         }
 963
 964         /* Try to make sure MCHBAR is enabled before poking at it */
 965         intel_setup_mchbar(dev_priv);
 966
 967         return 0;
 968 }
 969
 970 static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 971 {
 972         struct pci_dev *pdev = dev_priv->drm.pdev;
 973
 974         intel_teardown_mchbar(dev_priv);
 975         pci_iounmap(pdev, dev_priv->regs);
 976 }
 977
 978 /**
 979  * i915_driver_init_mmio - setup device MMIO
 980  * @dev_priv: device private
 981  *
 982  * Setup minimal device state necessary for MMIO accesses later in the
 983  * initialization sequence. The setup here should avoid any other device-wide
 984  * side effects or exposing the driver via kernel internal or user space
 985  * interfaces.
 986  */
 987 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 988 {
 989         int ret;
 990
 991         if (i915_inject_load_failure())
 992                 return -ENODEV;
 993
 994         if (i915_get_bridge_dev(dev_priv))
 995                 return -EIO;
 996
 997         ret = i915_mmio_setup(dev_priv);
 998         if (ret < 0)
 999                 goto err_bridge;
1000
1001         intel_uncore_init(dev_priv);
1002
1003         intel_device_info_init_mmio(dev_priv);
1004
1005         intel_uncore_prune(dev_priv);
1006
1007         intel_uc_init_mmio(dev_priv);
1008
1009         ret = intel_engines_init_mmio(dev_priv);
1010         if (ret)
1011                 goto err_uncore;
1012
1013         i915_gem_init_mmio(dev_priv);
1014
1015         return 0;
1016
1017 err_uncore:
1018         intel_uncore_fini(dev_priv);
1019         i915_mmio_cleanup(dev_priv);
1020 err_bridge:
1021         pci_dev_put(dev_priv->bridge_dev);
1022
1023         return ret;
1024 }
1025
1026 /**
1027  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1028  * @dev_priv: device private
1029  */
1030 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1031 {
1032         intel_uncore_fini(dev_priv);
1033         i915_mmio_cleanup(dev_priv);
1034         pci_dev_put(dev_priv->bridge_dev);
1035 }
1036
1037 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1038 {
1039         intel_gvt_sanitize_options(dev_priv);
1040 }
1041
1042 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
1043
1044 static const char *intel_dram_type_str(enum intel_dram_type type)
1045 {
1046         static const char * const str[] = {
1047                 DRAM_TYPE_STR(UNKNOWN),
1048                 DRAM_TYPE_STR(DDR3),
1049                 DRAM_TYPE_STR(DDR4),
1050                 DRAM_TYPE_STR(LPDDR3),
1051                 DRAM_TYPE_STR(LPDDR4),
1052         };
1053
1054         if (type >= ARRAY_SIZE(str))
1055                 type = INTEL_DRAM_UNKNOWN;
1056
1057         return str[type];
1058 }
1059
1060 #undef DRAM_TYPE_STR
1061
1062 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
1063 {
1064         return dimm->ranks * 64 / (dimm->width ?: 1);
1065 }
1066
1067 /* Returns total GB for the whole DIMM */
1068 static int skl_get_dimm_size(u16 val)
1069 {
1070         return val & SKL_DRAM_SIZE_MASK;
1071 }
1072
1073 static int skl_get_dimm_width(u16 val)
1074 {
1075         if (skl_get_dimm_size(val) == 0)
1076                 return 0;
1077
1078         switch (val & SKL_DRAM_WIDTH_MASK) {
1079         case SKL_DRAM_WIDTH_X8:
1080         case SKL_DRAM_WIDTH_X16:
1081         case SKL_DRAM_WIDTH_X32:
1082                 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1083                 return 8 << val;
1084         default:
1085                 MISSING_CASE(val);
1086                 return 0;
1087         }
1088 }
1089
1090 static int skl_get_dimm_ranks(u16 val)
1091 {
1092         if (skl_get_dimm_size(val) == 0)
1093                 return 0;
1094
1095         val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
1096
1097         return val + 1;
1098 }
1099
1100 /* Returns total GB for the whole DIMM */
1101 static int cnl_get_dimm_size(u16 val)
1102 {
1103         return (val & CNL_DRAM_SIZE_MASK) / 2;
1104 }
1105
1106 static int cnl_get_dimm_width(u16 val)
1107 {
1108         if (cnl_get_dimm_size(val) == 0)
1109                 return 0;
1110
1111         switch (val & CNL_DRAM_WIDTH_MASK) {
1112         case CNL_DRAM_WIDTH_X8:
1113         case CNL_DRAM_WIDTH_X16:
1114         case CNL_DRAM_WIDTH_X32:
1115                 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
1116                 return 8 << val;
1117         default:
1118                 MISSING_CASE(val);
1119                 return 0;
1120         }
1121 }
1122
1123 static int cnl_get_dimm_ranks(u16 val)
1124 {
1125         if (cnl_get_dimm_size(val) == 0)
1126                 return 0;
1127
1128         val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
1129
1130         return val + 1;
1131 }
1132
1133 static bool
1134 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
1135 {
1136         /* Convert total GB to Gb per DRAM device */
1137         return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
1138 }
1139
1140 static void
1141 skl_dram_get_dimm_info(struct drm_i915_private *dev_priv,
1142                        struct dram_dimm_info *dimm,
1143                        int channel, char dimm_name, u16 val)
1144 {
1145         if (INTEL_GEN(dev_priv) >= 10) {
1146                 dimm->size = cnl_get_dimm_size(val);
1147                 dimm->width = cnl_get_dimm_width(val);
1148                 dimm->ranks = cnl_get_dimm_ranks(val);
1149         } else {
1150                 dimm->size = skl_get_dimm_size(val);
1151                 dimm->width = skl_get_dimm_width(val);
1152                 dimm->ranks = skl_get_dimm_ranks(val);
1153         }
1154
1155         DRM_DEBUG_KMS("CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
1156                       channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
1157                       yesno(skl_is_16gb_dimm(dimm)));
1158 }
1159
1160 static int
1161 skl_dram_get_channel_info(struct drm_i915_private *dev_priv,
1162                           struct dram_channel_info *ch,
1163                           int channel, u32 val)
1164 {
1165         skl_dram_get_dimm_info(dev_priv, &ch->dimm_l,
1166                                channel, 'L', val & 0xffff);
1167         skl_dram_get_dimm_info(dev_priv, &ch->dimm_s,
1168                                channel, 'S', val >> 16);
1169
1170         if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
1171                 DRM_DEBUG_KMS("CH%u not populated\n", channel);
1172                 return -EINVAL;
1173         }
1174
1175         if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
1176                 ch->ranks = 2;
1177         else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
1178                 ch->ranks = 2;
1179         else
1180                 ch->ranks = 1;
1181
1182         ch->is_16gb_dimm =
1183                 skl_is_16gb_dimm(&ch->dimm_l) ||
1184                 skl_is_16gb_dimm(&ch->dimm_s);
1185
1186         DRM_DEBUG_KMS("CH%u ranks: %u, 16Gb DIMMs: %s\n",
1187                       channel, ch->ranks, yesno(ch->is_16gb_dimm));
1188
1189         return 0;
1190 }
1191
1192 static bool
1193 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
1194                         const struct dram_channel_info *ch1)
1195 {
1196         return !memcmp(ch0, ch1, sizeof(*ch0)) &&
1197                 (ch0->dimm_s.size == 0 ||
1198                  !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
1199 }
1200
1201 static int
1202 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
1203 {
1204         struct dram_info *dram_info = &dev_priv->dram_info;
1205         struct dram_channel_info ch0 = {}, ch1 = {};
1206         u32 val;
1207         int ret;
1208
1209         val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
1210         ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
1211         if (ret == 0)
1212                 dram_info->num_channels++;
1213
1214         val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
1215         ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
1216         if (ret == 0)
1217                 dram_info->num_channels++;
1218
1219         if (dram_info->num_channels == 0) {
1220                 DRM_INFO("Number of memory channels is zero\n");
1221                 return -EINVAL;
1222         }
1223
1224         /*
1225          * If any of the channel is single rank channel, worst case output
1226          * will be same as if single rank memory, so consider single rank
1227          * memory.
1228          */
1229         if (ch0.ranks == 1 || ch1.ranks == 1)
1230                 dram_info->ranks = 1;
1231         else
1232                 dram_info->ranks = max(ch0.ranks, ch1.ranks);
1233
1234         if (dram_info->ranks == 0) {
1235                 DRM_INFO("couldn't get memory rank information\n");
1236                 return -EINVAL;
1237         }
1238
1239         dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
1240
1241         dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
1242
1243         DRM_DEBUG_KMS("Memory configuration is symmetric? %s\n",
1244                       yesno(dram_info->symmetric_memory));
1245         return 0;
1246 }
1247
1248 static enum intel_dram_type
1249 skl_get_dram_type(struct drm_i915_private *dev_priv)
1250 {
1251         u32 val;
1252
1253         val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
1254
1255         switch (val & SKL_DRAM_DDR_TYPE_MASK) {
1256         case SKL_DRAM_DDR_TYPE_DDR3:
1257                 return INTEL_DRAM_DDR3;
1258         case SKL_DRAM_DDR_TYPE_DDR4:
1259                 return INTEL_DRAM_DDR4;
1260         case SKL_DRAM_DDR_TYPE_LPDDR3:
1261                 return INTEL_DRAM_LPDDR3;
1262         case SKL_DRAM_DDR_TYPE_LPDDR4:
1263                 return INTEL_DRAM_LPDDR4;
1264         default:
1265                 MISSING_CASE(val);
1266                 return INTEL_DRAM_UNKNOWN;
1267         }
1268 }
1269
1270 static int
1271 skl_get_dram_info(struct drm_i915_private *dev_priv)
1272 {
1273         struct dram_info *dram_info = &dev_priv->dram_info;
1274         u32 mem_freq_khz, val;
1275         int ret;
1276
1277         dram_info->type = skl_get_dram_type(dev_priv);
1278         DRM_DEBUG_KMS("DRAM type: %s\n", intel_dram_type_str(dram_info->type));
1279
1280         ret = skl_dram_get_channels_info(dev_priv);
1281         if (ret)
1282                 return ret;
1283
1284         val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
1285         mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
1286                                     SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1287
1288         dram_info->bandwidth_kbps = dram_info->num_channels *
1289                                                         mem_freq_khz * 8;
1290
1291         if (dram_info->bandwidth_kbps == 0) {
1292                 DRM_INFO("Couldn't get system memory bandwidth\n");
1293                 return -EINVAL;
1294         }
1295
1296         dram_info->valid = true;
1297         return 0;
1298 }
1299
1300 /* Returns Gb per DRAM device */
1301 static int bxt_get_dimm_size(u32 val)
1302 {
1303         switch (val & BXT_DRAM_SIZE_MASK) {
1304         case BXT_DRAM_SIZE_4GBIT:
1305                 return 4;
1306         case BXT_DRAM_SIZE_6GBIT:
1307                 return 6;
1308         case BXT_DRAM_SIZE_8GBIT:
1309                 return 8;
1310         case BXT_DRAM_SIZE_12GBIT:
1311                 return 12;
1312         case BXT_DRAM_SIZE_16GBIT:
1313                 return 16;
1314         default:
1315                 MISSING_CASE(val);
1316                 return 0;
1317         }
1318 }
1319
1320 static int bxt_get_dimm_width(u32 val)
1321 {
1322         if (!bxt_get_dimm_size(val))
1323                 return 0;
1324
1325         val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
1326
1327         return 8 << val;
1328 }
1329
1330 static int bxt_get_dimm_ranks(u32 val)
1331 {
1332         if (!bxt_get_dimm_size(val))
1333                 return 0;
1334
1335         switch (val & BXT_DRAM_RANK_MASK) {
1336         case BXT_DRAM_RANK_SINGLE:
1337                 return 1;
1338         case BXT_DRAM_RANK_DUAL:
1339                 return 2;
1340         default:
1341                 MISSING_CASE(val);
1342                 return 0;
1343         }
1344 }
1345
1346 static enum intel_dram_type bxt_get_dimm_type(u32 val)
1347 {
1348         if (!bxt_get_dimm_size(val))
1349                 return INTEL_DRAM_UNKNOWN;
1350
1351         switch (val & BXT_DRAM_TYPE_MASK) {
1352         case BXT_DRAM_TYPE_DDR3:
1353                 return INTEL_DRAM_DDR3;
1354         case BXT_DRAM_TYPE_LPDDR3:
1355                 return INTEL_DRAM_LPDDR3;
1356         case BXT_DRAM_TYPE_DDR4:
1357                 return INTEL_DRAM_DDR4;
1358         case BXT_DRAM_TYPE_LPDDR4:
1359                 return INTEL_DRAM_LPDDR4;
1360         default:
1361                 MISSING_CASE(val);
1362                 return INTEL_DRAM_UNKNOWN;
1363         }
1364 }
1365
1366 static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
1367                               u32 val)
1368 {
1369         dimm->width = bxt_get_dimm_width(val);
1370         dimm->ranks = bxt_get_dimm_ranks(val);
1371
1372         /*
1373          * Size in register is Gb per DRAM device. Convert to total
1374          * GB to match the way we report this for non-LP platforms.
1375          */
1376         dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
1377 }
1378
1379 static int
1380 bxt_get_dram_info(struct drm_i915_private *dev_priv)
1381 {
1382         struct dram_info *dram_info = &dev_priv->dram_info;
1383         u32 dram_channels;
1384         u32 mem_freq_khz, val;
1385         u8 num_active_channels;
1386         int i;
1387
1388         val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1389         mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1390                                     BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1391
1392         dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1393         num_active_channels = hweight32(dram_channels);
1394
1395         /* Each active bit represents 4-byte channel */
1396         dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1397
1398         if (dram_info->bandwidth_kbps == 0) {
1399                 DRM_INFO("Couldn't get system memory bandwidth\n");
1400                 return -EINVAL;
1401         }
1402
1403         /*
1404          * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1405          */
1406         for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1407                 struct dram_dimm_info dimm;
1408                 enum intel_dram_type type;
1409
1410                 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1411                 if (val == 0xFFFFFFFF)
1412                         continue;
1413
1414                 dram_info->num_channels++;
1415
1416                 bxt_get_dimm_info(&dimm, val);
1417                 type = bxt_get_dimm_type(val);
1418
1419                 WARN_ON(type != INTEL_DRAM_UNKNOWN &&
1420                         dram_info->type != INTEL_DRAM_UNKNOWN &&
1421                         dram_info->type != type);
1422
1423                 DRM_DEBUG_KMS("CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
1424                               i - BXT_D_CR_DRP0_DUNIT_START,
1425                               dimm.size, dimm.width, dimm.ranks,
1426                               intel_dram_type_str(type));
1427
1428                 /*
1429                  * If any of the channel is single rank channel,
1430                  * worst case output will be same as if single rank
1431                  * memory, so consider single rank memory.
1432                  */
1433                 if (dram_info->ranks == 0)
1434                         dram_info->ranks = dimm.ranks;
1435                 else if (dimm.ranks == 1)
1436                         dram_info->ranks = 1;
1437
1438                 if (type != INTEL_DRAM_UNKNOWN)
1439                         dram_info->type = type;
1440         }
1441
1442         if (dram_info->type == INTEL_DRAM_UNKNOWN ||
1443             dram_info->ranks == 0) {
1444                 DRM_INFO("couldn't get memory information\n");
1445                 return -EINVAL;
1446         }
1447
1448         dram_info->valid = true;
1449         return 0;
1450 }
1451
1452 static void
1453 intel_get_dram_info(struct drm_i915_private *dev_priv)
1454 {
1455         struct dram_info *dram_info = &dev_priv->dram_info;
1456         int ret;
1457
1458         /*
1459          * Assume 16Gb DIMMs are present until proven otherwise.
1460          * This is only used for the level 0 watermark latency
1461          * w/a which does not apply to bxt/glk.
1462          */
1463         dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1464
1465         if (INTEL_GEN(dev_priv) < 9)
1466                 return;
1467
1468         if (IS_GEN9_LP(dev_priv))
1469                 ret = bxt_get_dram_info(dev_priv);
1470         else
1471                 ret = skl_get_dram_info(dev_priv);
1472         if (ret)
1473                 return;
1474
1475         DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
1476                       dram_info->bandwidth_kbps,
1477                       dram_info->num_channels);
1478
1479         DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
1480                       dram_info->ranks, yesno(dram_info->is_16gb_dimm));
1481 }
1482
1483 /**
1484  * i915_driver_init_hw - setup state requiring device access
1485  * @dev_priv: device private
1486  *
1487  * Setup state that requires accessing the device, but doesn't require
1488  * exposing the driver via kernel internal or userspace interfaces.
1489  */
1490 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1491 {
1492         struct pci_dev *pdev = dev_priv->drm.pdev;
1493         int ret;
1494
1495         if (i915_inject_load_failure())
1496                 return -ENODEV;
1497
1498         intel_device_info_runtime_init(dev_priv);
1499
1500         if (HAS_PPGTT(dev_priv)) {
1501                 if (intel_vgpu_active(dev_priv) &&
1502                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
1503                         i915_report_error(dev_priv,
1504                                           "incompatible vGPU found, support for isolated ppGTT required\n");
1505                         return -ENXIO;
1506                 }
1507         }
1508
1509         if (HAS_EXECLISTS(dev_priv)) {
1510                 /*
1511                  * Older GVT emulation depends upon intercepting CSB mmio,
1512                  * which we no longer use, preferring to use the HWSP cache
1513                  * instead.
1514                  */
1515                 if (intel_vgpu_active(dev_priv) &&
1516                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1517                         i915_report_error(dev_priv,
1518                                           "old vGPU host found, support for HWSP emulation required\n");
1519                         return -ENXIO;
1520                 }
1521         }
1522
1523         intel_sanitize_options(dev_priv);
1524
1525         i915_perf_init(dev_priv);
1526
1527         ret = i915_ggtt_probe_hw(dev_priv);
1528         if (ret)
1529                 goto err_perf;
1530
1531         /*
1532          * WARNING: Apparently we must kick fbdev drivers before vgacon,
1533          * otherwise the vga fbdev driver falls over.
1534          */
1535         ret = i915_kick_out_firmware_fb(dev_priv);
1536         if (ret) {
1537                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1538                 goto err_ggtt;
1539         }
1540
1541         ret = vga_remove_vgacon(pdev);
1542         if (ret) {
1543                 DRM_ERROR("failed to remove conflicting VGA console\n");
1544                 goto err_ggtt;
1545         }
1546
1547         ret = i915_ggtt_init_hw(dev_priv);
1548         if (ret)
1549                 goto err_ggtt;
1550
1551         ret = i915_ggtt_enable_hw(dev_priv);
1552         if (ret) {
1553                 DRM_ERROR("failed to enable GGTT\n");
1554                 goto err_ggtt;
1555         }
1556
1557         pci_set_master(pdev);
1558
1559         /* overlay on gen2 is broken and can't address above 1G */
1560         if (IS_GEN(dev_priv, 2)) {
1561                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
1562                 if (ret) {
1563                         DRM_ERROR("failed to set DMA mask\n");
1564
1565                         goto err_ggtt;
1566                 }
1567         }
1568
1569         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1570          * using 32bit addressing, overwriting memory if HWS is located
1571          * above 4GB.
1572          *
1573          * The documentation also mentions an issue with undefined
1574          * behaviour if any general state is accessed within a page above 4GB,
1575          * which also needs to be handled carefully.
1576          */
1577         if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
1578                 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1579
1580                 if (ret) {
1581                         DRM_ERROR("failed to set DMA mask\n");
1582
1583                         goto err_ggtt;
1584                 }
1585         }
1586
1587         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1588                            PM_QOS_DEFAULT_VALUE);
1589
1590         intel_uncore_sanitize(dev_priv);
1591
1592         intel_gt_init_workarounds(dev_priv);
1593         i915_gem_load_init_fences(dev_priv);
1594
1595         /* On the 945G/GM, the chipset reports the MSI capability on the
1596          * integrated graphics even though the support isn't actually there
1597          * according to the published specs.  It doesn't appear to function
1598          * correctly in testing on 945G.
1599          * This may be a side effect of MSI having been made available for PEG
1600          * and the registers being closely associated.
1601          *
1602          * According to chipset errata, on the 965GM, MSI interrupts may
1603          * be lost or delayed, and was defeatured. MSI interrupts seem to
1604          * get lost on g4x as well, and interrupt delivery seems to stay
1605          * properly dead afterwards. So we'll just disable them for all
1606          * pre-gen5 chipsets.
1607          *
1608          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1609          * interrupts even when in MSI mode. This results in spurious
1610          * interrupt warnings if the legacy irq no. is shared with another
1611          * device. The kernel then disables that interrupt source and so
1612          * prevents the other device from working properly.
1613          */
1614         if (INTEL_GEN(dev_priv) >= 5) {
1615                 if (pci_enable_msi(pdev) < 0)
1616                         DRM_DEBUG_DRIVER("can't enable MSI");
1617         }
1618
1619         ret = intel_gvt_init(dev_priv);
1620         if (ret)
1621                 goto err_msi;
1622
1623         intel_opregion_setup(dev_priv);
1624         /*
1625          * Fill the dram structure to get the system raw bandwidth and
1626          * dram info. This will be used for memory latency calculation.
1627          */
1628         intel_get_dram_info(dev_priv);
1629
1630
1631         return 0;
1632
1633 err_msi:
1634         if (pdev->msi_enabled)
1635                 pci_disable_msi(pdev);
1636         pm_qos_remove_request(&dev_priv->pm_qos);
1637 err_ggtt:
1638         i915_ggtt_cleanup_hw(dev_priv);
1639 err_perf:
1640         i915_perf_fini(dev_priv);
1641         return ret;
1642 }
1643
1644 /**
1645  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1646  * @dev_priv: device private
1647  */
1648 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1649 {
1650         struct pci_dev *pdev = dev_priv->drm.pdev;
1651
1652         i915_perf_fini(dev_priv);
1653
1654         if (pdev->msi_enabled)
1655                 pci_disable_msi(pdev);
1656
1657         pm_qos_remove_request(&dev_priv->pm_qos);
1658         i915_ggtt_cleanup_hw(dev_priv);
1659 }
1660
1661 /**
1662  * i915_driver_register - register the driver with the rest of the system
1663  * @dev_priv: device private
1664  *
1665  * Perform any steps necessary to make the driver available via kernel
1666  * internal or userspace interfaces.
1667  */
1668 static void i915_driver_register(struct drm_i915_private *dev_priv)
1669 {
1670         struct drm_device *dev = &dev_priv->drm;
1671
1672         i915_gem_shrinker_register(dev_priv);
1673         i915_pmu_register(dev_priv);
1674
1675         /*
1676          * Notify a valid surface after modesetting,
1677          * when running inside a VM.
1678          */
1679         if (intel_vgpu_active(dev_priv))
1680                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1681
1682         /* Reveal our presence to userspace */
1683         if (drm_dev_register(dev, 0) == 0) {
1684                 i915_debugfs_register(dev_priv);
1685                 i915_setup_sysfs(dev_priv);
1686
1687                 /* Depends on sysfs having been initialized */
1688                 i915_perf_register(dev_priv);
1689         } else
1690                 DRM_ERROR("Failed to register driver for userspace access!\n");
1691
1692         if (HAS_DISPLAY(dev_priv)) {
1693                 /* Must be done after probing outputs */
1694                 intel_opregion_register(dev_priv);
1695                 acpi_video_register();
1696         }
1697
1698         if (IS_GEN(dev_priv, 5))
1699                 intel_gpu_ips_init(dev_priv);
1700
1701         intel_audio_init(dev_priv);
1702
1703         /*
1704          * Some ports require correctly set-up hpd registers for detection to
1705          * work properly (leading to ghost connected connector status), e.g. VGA
1706          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1707          * irqs are fully enabled. We do it last so that the async config
1708          * cannot run before the connectors are registered.
1709          */
1710         intel_fbdev_initial_config_async(dev);
1711
1712         /*
1713          * We need to coordinate the hotplugs with the asynchronous fbdev
1714          * configuration, for which we use the fbdev->async_cookie.
1715          */
1716         if (HAS_DISPLAY(dev_priv))
1717                 drm_kms_helper_poll_init(dev);
1718
1719         intel_power_domains_enable(dev_priv);
1720         intel_runtime_pm_enable(dev_priv);
1721 }
1722
1723 /**
1724  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1725  * @dev_priv: device private
1726  */
1727 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1728 {
1729         intel_runtime_pm_disable(dev_priv);
1730         intel_power_domains_disable(dev_priv);
1731
1732         intel_fbdev_unregister(dev_priv);
1733         intel_audio_deinit(dev_priv);
1734
1735         /*
1736          * After flushing the fbdev (incl. a late async config which will
1737          * have delayed queuing of a hotplug event), then flush the hotplug
1738          * events.
1739          */
1740         drm_kms_helper_poll_fini(&dev_priv->drm);
1741
1742         intel_gpu_ips_teardown();
1743         acpi_video_unregister();
1744         intel_opregion_unregister(dev_priv);
1745
1746         i915_perf_unregister(dev_priv);
1747         i915_pmu_unregister(dev_priv);
1748
1749         i915_teardown_sysfs(dev_priv);
1750         drm_dev_unregister(&dev_priv->drm);
1751
1752         i915_gem_shrinker_unregister(dev_priv);
1753 }
1754
1755 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1756 {
1757         if (drm_debug & DRM_UT_DRIVER) {
1758                 struct drm_printer p = drm_debug_printer("i915 device info:");
1759
1760                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
1761                            INTEL_DEVID(dev_priv),
1762                            INTEL_REVID(dev_priv),
1763                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
1764                            INTEL_GEN(dev_priv));
1765
1766                 intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
1767                 intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
1768         }
1769
1770         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1771                 DRM_INFO("DRM_I915_DEBUG enabled\n");
1772         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1773                 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
1774         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1775                 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
1776 }
1777
1778 static struct drm_i915_private *
1779 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1780 {
1781         const struct intel_device_info *match_info =
1782                 (struct intel_device_info *)ent->driver_data;
1783         struct intel_device_info *device_info;
1784         struct drm_i915_private *i915;
1785         int err;
1786
1787         i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1788         if (!i915)
1789                 return ERR_PTR(-ENOMEM);
1790
1791         err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1792         if (err) {
1793                 kfree(i915);
1794                 return ERR_PTR(err);
1795         }
1796
1797         i915->drm.pdev = pdev;
1798         i915->drm.dev_private = i915;
1799         pci_set_drvdata(pdev, &i915->drm);
1800
1801         /* Setup the write-once "constant" device info */
1802         device_info = mkwrite_device_info(i915);
1803         memcpy(device_info, match_info, sizeof(*device_info));
1804         RUNTIME_INFO(i915)->device_id = pdev->device;
1805
1806         BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
1807                      BITS_PER_TYPE(device_info->platform_mask));
1808         BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
1809
1810         return i915;
1811 }
1812
1813 static void i915_driver_destroy(struct drm_i915_private *i915)
1814 {
1815         struct pci_dev *pdev = i915->drm.pdev;
1816
1817         drm_dev_fini(&i915->drm);
1818         kfree(i915);
1819
1820         /* And make sure we never chase our dangling pointer from pci_dev */
1821         pci_set_drvdata(pdev, NULL);
1822 }
1823
1824 /**
1825  * i915_driver_load - setup chip and create an initial config
1826  * @pdev: PCI device
1827  * @ent: matching PCI ID entry
1828  *
1829  * The driver load routine has to do several things:
1830  *   - drive output discovery via intel_modeset_init()
1831  *   - initialize the memory manager
1832  *   - allocate initial config memory
1833  *   - setup the DRM framebuffer with the allocated memory
1834  */
1835 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1836 {
1837         const struct intel_device_info *match_info =
1838                 (struct intel_device_info *)ent->driver_data;
1839         struct drm_i915_private *dev_priv;
1840         int ret;
1841
1842         dev_priv = i915_driver_create(pdev, ent);
1843         if (IS_ERR(dev_priv))
1844                 return PTR_ERR(dev_priv);
1845
1846         /* Disable nuclear pageflip by default on pre-ILK */
1847         if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1848                 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1849
1850         ret = pci_enable_device(pdev);
1851         if (ret)
1852                 goto out_fini;
1853
1854         ret = i915_driver_init_early(dev_priv);
1855         if (ret < 0)
1856                 goto out_pci_disable;
1857
1858         disable_rpm_wakeref_asserts(dev_priv);
1859
1860         ret = i915_driver_init_mmio(dev_priv);
1861         if (ret < 0)
1862                 goto out_runtime_pm_put;
1863
1864         ret = i915_driver_init_hw(dev_priv);
1865         if (ret < 0)
1866                 goto out_cleanup_mmio;
1867
1868         ret = i915_load_modeset_init(&dev_priv->drm);
1869         if (ret < 0)
1870                 goto out_cleanup_hw;
1871
1872         i915_driver_register(dev_priv);
1873
1874         enable_rpm_wakeref_asserts(dev_priv);
1875
1876         i915_welcome_messages(dev_priv);
1877
1878         return 0;
1879
1880 out_cleanup_hw:
1881         i915_driver_cleanup_hw(dev_priv);
1882 out_cleanup_mmio:
1883         i915_driver_cleanup_mmio(dev_priv);
1884 out_runtime_pm_put:
1885         enable_rpm_wakeref_asserts(dev_priv);
1886         i915_driver_cleanup_early(dev_priv);
1887 out_pci_disable:
1888         pci_disable_device(pdev);
1889 out_fini:
1890         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1891         i915_driver_destroy(dev_priv);
1892         return ret;
1893 }
1894
1895 void i915_driver_unload(struct drm_device *dev)
1896 {
1897         struct drm_i915_private *dev_priv = to_i915(dev);
1898         struct pci_dev *pdev = dev_priv->drm.pdev;
1899
1900         disable_rpm_wakeref_asserts(dev_priv);
1901
1902         i915_driver_unregister(dev_priv);
1903
1904         /* Flush any external code that still may be under the RCU lock */
1905         synchronize_rcu();
1906
1907         i915_gem_suspend(dev_priv);
1908
1909         drm_atomic_helper_shutdown(dev);
1910
1911         intel_gvt_cleanup(dev_priv);
1912
1913         intel_modeset_cleanup(dev);
1914
1915         intel_bios_cleanup(dev_priv);
1916
1917         vga_switcheroo_unregister_client(pdev);
1918         vga_client_register(pdev, NULL, NULL, NULL);
1919
1920         intel_csr_ucode_fini(dev_priv);
1921
1922         /* Free error state after interrupts are fully disabled. */
1923         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1924         i915_reset_error_state(dev_priv);
1925
1926         i915_gem_fini(dev_priv);
1927
1928         intel_power_domains_fini_hw(dev_priv);
1929
1930         i915_driver_cleanup_hw(dev_priv);
1931         i915_driver_cleanup_mmio(dev_priv);
1932
1933         enable_rpm_wakeref_asserts(dev_priv);
1934         intel_runtime_pm_cleanup(dev_priv);
1935 }
1936
1937 static void i915_driver_release(struct drm_device *dev)
1938 {
1939         struct drm_i915_private *dev_priv = to_i915(dev);
1940
1941         i915_driver_cleanup_early(dev_priv);
1942         i915_driver_destroy(dev_priv);
1943 }
1944
1945 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1946 {
1947         struct drm_i915_private *i915 = to_i915(dev);
1948         int ret;
1949
1950         ret = i915_gem_open(i915, file);
1951         if (ret)
1952                 return ret;
1953
1954         return 0;
1955 }
1956
1957 /**
1958  * i915_driver_lastclose - clean up after all DRM clients have exited
1959  * @dev: DRM device
1960  *
1961  * Take care of cleaning up after all DRM clients have exited.  In the
1962  * mode setting case, we want to restore the kernel's initial mode (just
1963  * in case the last client left us in a bad state).
1964  *
1965  * Additionally, in the non-mode setting case, we'll tear down the GTT
1966  * and DMA structures, since the kernel won't be using them, and clea
1967  * up any GEM state.
1968  */
1969 static void i915_driver_lastclose(struct drm_device *dev)
1970 {
1971         intel_fbdev_restore_mode(dev);
1972         vga_switcheroo_process_delayed_switch();
1973 }
1974
1975 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1976 {
1977         struct drm_i915_file_private *file_priv = file->driver_priv;
1978
1979         mutex_lock(&dev->struct_mutex);
1980         i915_gem_context_close(file);
1981         i915_gem_release(dev, file);
1982         mutex_unlock(&dev->struct_mutex);
1983
1984         kfree(file_priv);
1985 }
1986
1987 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1988 {
1989         struct drm_device *dev = &dev_priv->drm;
1990         struct intel_encoder *encoder;
1991
1992         drm_modeset_lock_all(dev);
1993         for_each_intel_encoder(dev, encoder)
1994                 if (encoder->suspend)
1995                         encoder->suspend(encoder);
1996         drm_modeset_unlock_all(dev);
1997 }
1998
1999 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2000                               bool rpm_resume);
2001 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
2002
2003 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
2004 {
2005 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
2006         if (acpi_target_system_state() < ACPI_STATE_S3)
2007                 return true;
2008 #endif
2009         return false;
2010 }
2011
2012 static int i915_drm_prepare(struct drm_device *dev)
2013 {
2014         struct drm_i915_private *i915 = to_i915(dev);
2015
2016         /*
2017          * NB intel_display_suspend() may issue new requests after we've
2018          * ostensibly marked the GPU as ready-to-sleep here. We need to
2019          * split out that work and pull it forward so that after point,
2020          * the GPU is not woken again.
2021          */
2022         i915_gem_suspend(i915);
2023
2024         return 0;
2025 }
2026
2027 static int i915_drm_suspend(struct drm_device *dev)
2028 {
2029         struct drm_i915_private *dev_priv = to_i915(dev);
2030         struct pci_dev *pdev = dev_priv->drm.pdev;
2031         pci_power_t opregion_target_state;
2032
2033         disable_rpm_wakeref_asserts(dev_priv);
2034
2035         /* We do a lot of poking in a lot of registers, make sure they work
2036          * properly. */
2037         intel_power_domains_disable(dev_priv);
2038
2039         drm_kms_helper_poll_disable(dev);
2040
2041         pci_save_state(pdev);
2042
2043         intel_display_suspend(dev);
2044
2045         intel_dp_mst_suspend(dev_priv);
2046
2047         intel_runtime_pm_disable_interrupts(dev_priv);
2048         intel_hpd_cancel_work(dev_priv);
2049
2050         intel_suspend_encoders(dev_priv);
2051
2052         intel_suspend_hw(dev_priv);
2053
2054         i915_gem_suspend_gtt_mappings(dev_priv);
2055
2056         i915_save_state(dev_priv);
2057
2058         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
2059         intel_opregion_suspend(dev_priv, opregion_target_state);
2060
2061         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
2062
2063         dev_priv->suspend_count++;
2064
2065         intel_csr_ucode_suspend(dev_priv);
2066
2067         enable_rpm_wakeref_asserts(dev_priv);
2068
2069         return 0;
2070 }
2071
2072 static enum i915_drm_suspend_mode
2073 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
2074 {
2075         if (hibernate)
2076                 return I915_DRM_SUSPEND_HIBERNATE;
2077
2078         if (suspend_to_idle(dev_priv))
2079                 return I915_DRM_SUSPEND_IDLE;
2080
2081         return I915_DRM_SUSPEND_MEM;
2082 }
2083
2084 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
2085 {
2086         struct drm_i915_private *dev_priv = to_i915(dev);
2087         struct pci_dev *pdev = dev_priv->drm.pdev;
2088         int ret;
2089
2090         disable_rpm_wakeref_asserts(dev_priv);
2091
2092         i915_gem_suspend_late(dev_priv);
2093
2094         intel_uncore_suspend(dev_priv);
2095
2096         intel_power_domains_suspend(dev_priv,
2097                                     get_suspend_mode(dev_priv, hibernation));
2098
2099         ret = 0;
2100         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
2101                 bxt_enable_dc9(dev_priv);
2102         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2103                 hsw_enable_pc8(dev_priv);
2104         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2105                 ret = vlv_suspend_complete(dev_priv);
2106
2107         if (ret) {
2108                 DRM_ERROR("Suspend complete failed: %d\n", ret);
2109                 intel_power_domains_resume(dev_priv);
2110
2111                 goto out;
2112         }
2113
2114         pci_disable_device(pdev);
2115         /*
2116          * During hibernation on some platforms the BIOS may try to access
2117          * the device even though it's already in D3 and hang the machine. So
2118          * leave the device in D0 on those platforms and hope the BIOS will
2119          * power down the device properly. The issue was seen on multiple old
2120          * GENs with different BIOS vendors, so having an explicit blacklist
2121          * is inpractical; apply the workaround on everything pre GEN6. The
2122          * platforms where the issue was seen:
2123          * Lenovo Thinkpad X301, X61s, X60, T60, X41
2124          * Fujitsu FSC S7110
2125          * Acer Aspire 1830T
2126          */
2127         if (!(hibernation && INTEL_GEN(dev_priv) < 6))
2128                 pci_set_power_state(pdev, PCI_D3hot);
2129
2130 out:
2131         enable_rpm_wakeref_asserts(dev_priv);
2132         if (!dev_priv->uncore.user_forcewake.count)
2133                 intel_runtime_pm_cleanup(dev_priv);
2134
2135         return ret;
2136 }
2137
2138 static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
2139 {
2140         int error;
2141
2142         if (!dev) {
2143                 DRM_ERROR("dev: %p\n", dev);
2144                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
2145                 return -ENODEV;
2146         }
2147
2148         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
2149                          state.event != PM_EVENT_FREEZE))
2150                 return -EINVAL;
2151
2152         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2153                 return 0;
2154
2155         error = i915_drm_suspend(dev);
2156         if (error)
2157                 return error;
2158
2159         return i915_drm_suspend_late(dev, false);
2160 }
2161
2162 static int i915_drm_resume(struct drm_device *dev)
2163 {
2164         struct drm_i915_private *dev_priv = to_i915(dev);
2165         int ret;
2166
2167         disable_rpm_wakeref_asserts(dev_priv);
2168         intel_sanitize_gt_powersave(dev_priv);
2169
2170         i915_gem_sanitize(dev_priv);
2171
2172         ret = i915_ggtt_enable_hw(dev_priv);
2173         if (ret)
2174                 DRM_ERROR("failed to re-enable GGTT\n");
2175
2176         intel_csr_ucode_resume(dev_priv);
2177
2178         i915_restore_state(dev_priv);
2179         intel_pps_unlock_regs_wa(dev_priv);
2180
2181         intel_init_pch_refclk(dev_priv);
2182
2183         /*
2184          * Interrupts have to be enabled before any batches are run. If not the
2185          * GPU will hang. i915_gem_init_hw() will initiate batches to
2186          * update/restore the context.
2187          *
2188          * drm_mode_config_reset() needs AUX interrupts.
2189          *
2190          * Modeset enabling in intel_modeset_init_hw() also needs working
2191          * interrupts.
2192          */
2193         intel_runtime_pm_enable_interrupts(dev_priv);
2194
2195         drm_mode_config_reset(dev);
2196
2197         i915_gem_resume(dev_priv);
2198
2199         intel_modeset_init_hw(dev);
2200         intel_init_clock_gating(dev_priv);
2201
2202         spin_lock_irq(&dev_priv->irq_lock);
2203         if (dev_priv->display.hpd_irq_setup)
2204                 dev_priv->display.hpd_irq_setup(dev_priv);
2205         spin_unlock_irq(&dev_priv->irq_lock);
2206
2207         intel_dp_mst_resume(dev_priv);
2208
2209         intel_display_resume(dev);
2210
2211         drm_kms_helper_poll_enable(dev);
2212
2213         /*
2214          * ... but also need to make sure that hotplug processing
2215          * doesn't cause havoc. Like in the driver load code we don't
2216          * bother with the tiny race here where we might lose hotplug
2217          * notifications.
2218          * */
2219         intel_hpd_init(dev_priv);
2220
2221         intel_opregion_resume(dev_priv);
2222
2223         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
2224
2225         intel_power_domains_enable(dev_priv);
2226
2227         enable_rpm_wakeref_asserts(dev_priv);
2228
2229         return 0;
2230 }
2231
2232 static int i915_drm_resume_early(struct drm_device *dev)
2233 {
2234         struct drm_i915_private *dev_priv = to_i915(dev);
2235         struct pci_dev *pdev = dev_priv->drm.pdev;
2236         int ret;
2237
2238         /*
2239          * We have a resume ordering issue with the snd-hda driver also
2240          * requiring our device to be power up. Due to the lack of a
2241          * parent/child relationship we currently solve this with an early
2242          * resume hook.
2243          *
2244          * FIXME: This should be solved with a special hdmi sink device or
2245          * similar so that power domains can be employed.
2246          */
2247
2248         /*
2249          * Note that we need to set the power state explicitly, since we
2250          * powered off the device during freeze and the PCI core won't power
2251          * it back up for us during thaw. Powering off the device during
2252          * freeze is not a hard requirement though, and during the
2253          * suspend/resume phases the PCI core makes sure we get here with the
2254          * device powered on. So in case we change our freeze logic and keep
2255          * the device powered we can also remove the following set power state
2256          * call.
2257          */
2258         ret = pci_set_power_state(pdev, PCI_D0);
2259         if (ret) {
2260                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2261                 return ret;
2262         }
2263
2264         /*
2265          * Note that pci_enable_device() first enables any parent bridge
2266          * device and only then sets the power state for this device. The
2267          * bridge enabling is a nop though, since bridge devices are resumed
2268          * first. The order of enabling power and enabling the device is
2269          * imposed by the PCI core as described above, so here we preserve the
2270          * same order for the freeze/thaw phases.
2271          *
2272          * TODO: eventually we should remove pci_disable_device() /
2273          * pci_enable_enable_device() from suspend/resume. Due to how they
2274          * depend on the device enable refcount we can't anyway depend on them
2275          * disabling/enabling the device.
2276          */
2277         if (pci_enable_device(pdev))
2278                 return -EIO;
2279
2280         pci_set_master(pdev);
2281
2282         disable_rpm_wakeref_asserts(dev_priv);
2283
2284         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2285                 ret = vlv_resume_prepare(dev_priv, false);
2286         if (ret)
2287                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2288                           ret);
2289
2290         intel_uncore_resume_early(dev_priv);
2291
2292         if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
2293                 gen9_sanitize_dc_state(dev_priv);
2294                 bxt_disable_dc9(dev_priv);
2295         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2296                 hsw_disable_pc8(dev_priv);
2297         }
2298
2299         intel_uncore_sanitize(dev_priv);
2300
2301         intel_power_domains_resume(dev_priv);
2302
2303         intel_engines_sanitize(dev_priv, true);
2304
2305         enable_rpm_wakeref_asserts(dev_priv);
2306
2307         return ret;
2308 }
2309
2310 static int i915_resume_switcheroo(struct drm_device *dev)
2311 {
2312         int ret;
2313
2314         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2315                 return 0;
2316
2317         ret = i915_drm_resume_early(dev);
2318         if (ret)
2319                 return ret;
2320
2321         return i915_drm_resume(dev);
2322 }
2323
2324 static int i915_pm_prepare(struct device *kdev)
2325 {
2326         struct pci_dev *pdev = to_pci_dev(kdev);
2327         struct drm_device *dev = pci_get_drvdata(pdev);
2328
2329         if (!dev) {
2330                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2331                 return -ENODEV;
2332         }
2333
2334         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2335                 return 0;
2336
2337         return i915_drm_prepare(dev);
2338 }
2339
2340 static int i915_pm_suspend(struct device *kdev)
2341 {
2342         struct pci_dev *pdev = to_pci_dev(kdev);
2343         struct drm_device *dev = pci_get_drvdata(pdev);
2344
2345         if (!dev) {
2346                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2347                 return -ENODEV;
2348         }
2349
2350         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2351                 return 0;
2352
2353         return i915_drm_suspend(dev);
2354 }
2355
2356 static int i915_pm_suspend_late(struct device *kdev)
2357 {
2358         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2359
2360         /*
2361          * We have a suspend ordering issue with the snd-hda driver also
2362          * requiring our device to be power up. Due to the lack of a
2363          * parent/child relationship we currently solve this with an late
2364          * suspend hook.
2365          *
2366          * FIXME: This should be solved with a special hdmi sink device or
2367          * similar so that power domains can be employed.
2368          */
2369         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2370                 return 0;
2371
2372         return i915_drm_suspend_late(dev, false);
2373 }
2374
2375 static int i915_pm_poweroff_late(struct device *kdev)
2376 {
2377         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2378
2379         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2380                 return 0;
2381
2382         return i915_drm_suspend_late(dev, true);
2383 }
2384
2385 static int i915_pm_resume_early(struct device *kdev)
2386 {
2387         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2388
2389         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2390                 return 0;
2391
2392         return i915_drm_resume_early(dev);
2393 }
2394
2395 static int i915_pm_resume(struct device *kdev)
2396 {
2397         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2398
2399         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2400                 return 0;
2401
2402         return i915_drm_resume(dev);
2403 }
2404
2405 /* freeze: before creating the hibernation_image */
2406 static int i915_pm_freeze(struct device *kdev)
2407 {
2408         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2409         int ret;
2410
2411         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2412                 ret = i915_drm_suspend(dev);
2413                 if (ret)
2414                         return ret;
2415         }
2416
2417         ret = i915_gem_freeze(kdev_to_i915(kdev));
2418         if (ret)
2419                 return ret;
2420
2421         return 0;
2422 }
2423
2424 static int i915_pm_freeze_late(struct device *kdev)
2425 {
2426         struct drm_device *dev = &kdev_to_i915(kdev)->drm;
2427         int ret;
2428
2429         if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2430                 ret = i915_drm_suspend_late(dev, true);
2431                 if (ret)
2432                         return ret;
2433         }
2434
2435         ret = i915_gem_freeze_late(kdev_to_i915(kdev));
2436         if (ret)
2437                 return ret;
2438
2439         return 0;
2440 }
2441
2442 /* thaw: called after creating the hibernation image, but before turning off. */
2443 static int i915_pm_thaw_early(struct device *kdev)
2444 {
2445         return i915_pm_resume_early(kdev);
2446 }
2447
2448 static int i915_pm_thaw(struct device *kdev)
2449 {
2450         return i915_pm_resume(kdev);
2451 }
2452
2453 /* restore: called after loading the hibernation image. */
2454 static int i915_pm_restore_early(struct device *kdev)
2455 {
2456         return i915_pm_resume_early(kdev);
2457 }
2458
2459 static int i915_pm_restore(struct device *kdev)
2460 {
2461         return i915_pm_resume(kdev);
2462 }
2463
2464 /*
2465  * Save all Gunit registers that may be lost after a D3 and a subsequent
2466  * S0i[R123] transition. The list of registers needing a save/restore is
2467  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2468  * registers in the following way:
2469  * - Driver: saved/restored by the driver
2470  * - Punit : saved/restored by the Punit firmware
2471  * - No, w/o marking: no need to save/restore, since the register is R/O or
2472  *                    used internally by the HW in a way that doesn't depend
2473  *                    keeping the content across a suspend/resume.
2474  * - Debug : used for debugging
2475  *
2476  * We save/restore all registers marked with 'Driver', with the following
2477  * exceptions:
2478  * - Registers out of use, including also registers marked with 'Debug'.
2479  *   These have no effect on the driver's operation, so we don't save/restore
2480  *   them to reduce the overhead.
2481  * - Registers that are fully setup by an initialization function called from
2482  *   the resume path. For example many clock gating and RPS/RC6 registers.
2483  * - Registers that provide the right functionality with their reset defaults.
2484  *
2485  * TODO: Except for registers that based on the above 3 criteria can be safely
2486  * ignored, we save/restore all others, practically treating the HW context as
2487  * a black-box for the driver. Further investigation is needed to reduce the
2488  * saved/restored registers even further, by following the same 3 criteria.
2489  */
2490 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2491 {
2492         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2493         int i;
2494
2495         /* GAM 0x4000-0x4770 */
2496         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2497         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2498         s->arb_mode             = I915_READ(ARB_MODE);
2499         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2500         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2501
2502         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2503                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2504
2505         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2506         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2507
2508         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2509         s->ecochk               = I915_READ(GAM_ECOCHK);
2510         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2511         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2512
2513         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2514
2515         /* MBC 0x9024-0x91D0, 0x8500 */
2516         s->g3dctl               = I915_READ(VLV_G3DCTL);
2517         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2518         s->mbctl                = I915_READ(GEN6_MBCTL);
2519
2520         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2521         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2522         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2523         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2524         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2525         s->rstctl               = I915_READ(GEN6_RSTCTL);
2526         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2527
2528         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2529         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2530         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2531         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2532         s->ecobus               = I915_READ(ECOBUS);
2533         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2534         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2535         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2536         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2537         s->rcedata              = I915_READ(VLV_RCEDATA);
2538         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2539
2540         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2541         s->gt_imr               = I915_READ(GTIMR);
2542         s->gt_ier               = I915_READ(GTIER);
2543         s->pm_imr               = I915_READ(GEN6_PMIMR);
2544         s->pm_ier               = I915_READ(GEN6_PMIER);
2545
2546         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2547                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2548
2549         /* GT SA CZ domain, 0x100000-0x138124 */
2550         s->tilectl              = I915_READ(TILECTL);
2551         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2552         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2553         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2554         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2555
2556         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2557         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2558         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2559         s->pcbr                 = I915_READ(VLV_PCBR);
2560         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2561
2562         /*
2563          * Not saving any of:
2564          * DFT,         0x9800-0x9EC0
2565          * SARB,        0xB000-0xB1FC
2566          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2567          * PCI CFG
2568          */
2569 }
2570
2571 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2572 {
2573         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2574         u32 val;
2575         int i;
2576
2577         /* GAM 0x4000-0x4770 */
2578         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2579         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2580         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2581         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2582         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2583
2584         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2585                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2586
2587         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2588         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2589
2590         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2591         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2592         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2593         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2594
2595         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2596
2597         /* MBC 0x9024-0x91D0, 0x8500 */
2598         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2599         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2600         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2601
2602         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2603         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2604         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2605         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2606         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2607         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2608         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2609
2610         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2611         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2612         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2613         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2614         I915_WRITE(ECOBUS,              s->ecobus);
2615         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2616         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2617         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2618         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2619         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2620         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2621
2622         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2623         I915_WRITE(GTIMR,               s->gt_imr);
2624         I915_WRITE(GTIER,               s->gt_ier);
2625         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2626         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2627
2628         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2629                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2630
2631         /* GT SA CZ domain, 0x100000-0x138124 */
2632         I915_WRITE(TILECTL,                     s->tilectl);
2633         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2634         /*
2635          * Preserve the GT allow wake and GFX force clock bit, they are not
2636          * be restored, as they are used to control the s0ix suspend/resume
2637          * sequence by the caller.
2638          */
2639         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2640         val &= VLV_GTLC_ALLOWWAKEREQ;
2641         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2642         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2643
2644         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2645         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2646         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2647         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2648
2649         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2650
2651         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2652         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2653         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2654         I915_WRITE(VLV_PCBR,                    s->pcbr);
2655         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2656 }
2657
2658 static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2659                                   u32 mask, u32 val)
2660 {
2661         i915_reg_t reg = VLV_GTLC_PW_STATUS;
2662         u32 reg_value;
2663         int ret;
2664
2665         /* The HW does not like us polling for PW_STATUS frequently, so
2666          * use the sleeping loop rather than risk the busy spin within
2667          * intel_wait_for_register().
2668          *
2669          * Transitioning between RC6 states should be at most 2ms (see
2670          * valleyview_enable_rps) so use a 3ms timeout.
2671          */
2672         ret = wait_for(((reg_value = I915_READ_NOTRACE(reg)) & mask) == val, 3);
2673
2674         /* just trace the final value */
2675         trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2676
2677         return ret;
2678 }
2679
2680 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2681 {
2682         u32 val;
2683         int err;
2684
2685         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2686         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2687         if (force_on)
2688                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2689         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2690
2691         if (!force_on)
2692                 return 0;
2693
2694         err = intel_wait_for_register(dev_priv,
2695                                       VLV_GTLC_SURVIVABILITY_REG,
2696                                       VLV_GFX_CLK_STATUS_BIT,
2697                                       VLV_GFX_CLK_STATUS_BIT,
2698                                       20);
2699         if (err)
2700                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2701                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2702
2703         return err;
2704 }
2705
2706 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2707 {
2708         u32 mask;
2709         u32 val;
2710         int err;
2711
2712         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2713         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2714         if (allow)
2715                 val |= VLV_GTLC_ALLOWWAKEREQ;
2716         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2717         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2718
2719         mask = VLV_GTLC_ALLOWWAKEACK;
2720         val = allow ? mask : 0;
2721
2722         err = vlv_wait_for_pw_status(dev_priv, mask, val);
2723         if (err)
2724                 DRM_ERROR("timeout disabling GT waking\n");
2725
2726         return err;
2727 }
2728
2729 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2730                                   bool wait_for_on)
2731 {
2732         u32 mask;
2733         u32 val;
2734
2735         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2736         val = wait_for_on ? mask : 0;
2737
2738         /*
2739          * RC6 transitioning can be delayed up to 2 msec (see
2740          * valleyview_enable_rps), use 3 msec for safety.
2741          *
2742          * This can fail to turn off the rc6 if the GPU is stuck after a failed
2743          * reset and we are trying to force the machine to sleep.
2744          */
2745         if (vlv_wait_for_pw_status(dev_priv, mask, val))
2746                 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2747                                  onoff(wait_for_on));
2748 }
2749
2750 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2751 {
2752         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2753                 return;
2754
2755         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2756         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2757 }
2758
2759 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2760 {
2761         u32 mask;
2762         int err;
2763
2764         /*
2765          * Bspec defines the following GT well on flags as debug only, so
2766          * don't treat them as hard failures.
2767          */
2768         vlv_wait_for_gt_wells(dev_priv, false);
2769
2770         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2771         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2772
2773         vlv_check_no_gt_access(dev_priv);
2774
2775         err = vlv_force_gfx_clock(dev_priv, true);
2776         if (err)
2777                 goto err1;
2778
2779         err = vlv_allow_gt_wake(dev_priv, false);
2780         if (err)
2781                 goto err2;
2782
2783         if (!IS_CHERRYVIEW(dev_priv))
2784                 vlv_save_gunit_s0ix_state(dev_priv);
2785
2786         err = vlv_force_gfx_clock(dev_priv, false);
2787         if (err)
2788                 goto err2;
2789
2790         return 0;
2791
2792 err2:
2793         /* For safety always re-enable waking and disable gfx clock forcing */
2794         vlv_allow_gt_wake(dev_priv, true);
2795 err1:
2796         vlv_force_gfx_clock(dev_priv, false);
2797
2798         return err;
2799 }
2800
2801 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2802                                 bool rpm_resume)
2803 {
2804         int err;
2805         int ret;
2806
2807         /*
2808          * If any of the steps fail just try to continue, that's the best we
2809          * can do at this point. Return the first error code (which will also
2810          * leave RPM permanently disabled).
2811          */
2812         ret = vlv_force_gfx_clock(dev_priv, true);
2813
2814         if (!IS_CHERRYVIEW(dev_priv))
2815                 vlv_restore_gunit_s0ix_state(dev_priv);
2816
2817         err = vlv_allow_gt_wake(dev_priv, true);
2818         if (!ret)
2819                 ret = err;
2820
2821         err = vlv_force_gfx_clock(dev_priv, false);
2822         if (!ret)
2823                 ret = err;
2824
2825         vlv_check_no_gt_access(dev_priv);
2826
2827         if (rpm_resume)
2828                 intel_init_clock_gating(dev_priv);
2829
2830         return ret;
2831 }
2832
2833 static int intel_runtime_suspend(struct device *kdev)
2834 {
2835         struct pci_dev *pdev = to_pci_dev(kdev);
2836         struct drm_device *dev = pci_get_drvdata(pdev);
2837         struct drm_i915_private *dev_priv = to_i915(dev);
2838         int ret;
2839
2840         if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
2841                 return -ENODEV;
2842
2843         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2844                 return -ENODEV;
2845
2846         DRM_DEBUG_KMS("Suspending device\n");
2847
2848         disable_rpm_wakeref_asserts(dev_priv);
2849
2850         /*
2851          * We are safe here against re-faults, since the fault handler takes
2852          * an RPM reference.
2853          */
2854         i915_gem_runtime_suspend(dev_priv);
2855
2856         intel_uc_suspend(dev_priv);
2857
2858         intel_runtime_pm_disable_interrupts(dev_priv);
2859
2860         intel_uncore_suspend(dev_priv);
2861
2862         ret = 0;
2863         if (INTEL_GEN(dev_priv) >= 11) {
2864                 icl_display_core_uninit(dev_priv);
2865                 bxt_enable_dc9(dev_priv);
2866         } else if (IS_GEN9_LP(dev_priv)) {
2867                 bxt_display_core_uninit(dev_priv);
2868                 bxt_enable_dc9(dev_priv);
2869         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2870                 hsw_enable_pc8(dev_priv);
2871         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2872                 ret = vlv_suspend_complete(dev_priv);
2873         }
2874
2875         if (ret) {
2876                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2877                 intel_uncore_runtime_resume(dev_priv);
2878
2879                 intel_runtime_pm_enable_interrupts(dev_priv);
2880
2881                 intel_uc_resume(dev_priv);
2882
2883                 i915_gem_init_swizzling(dev_priv);
2884                 i915_gem_restore_fences(dev_priv);
2885
2886                 enable_rpm_wakeref_asserts(dev_priv);
2887
2888                 return ret;
2889         }
2890
2891         enable_rpm_wakeref_asserts(dev_priv);
2892         intel_runtime_pm_cleanup(dev_priv);
2893
2894         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2895                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2896
2897         dev_priv->runtime_pm.suspended = true;
2898
2899         /*
2900          * FIXME: We really should find a document that references the arguments
2901          * used below!
2902          */
2903         if (IS_BROADWELL(dev_priv)) {
2904                 /*
2905                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2906                  * being detected, and the call we do at intel_runtime_resume()
2907                  * won't be able to restore them. Since PCI_D3hot matches the
2908                  * actual specification and appears to be working, use it.
2909                  */
2910                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2911         } else {
2912                 /*
2913                  * current versions of firmware which depend on this opregion
2914                  * notification have repurposed the D1 definition to mean
2915                  * "runtime suspended" vs. what you would normally expect (D3)
2916                  * to distinguish it from notifications that might be sent via
2917                  * the suspend path.
2918                  */
2919                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2920         }
2921
2922         assert_forcewakes_inactive(dev_priv);
2923
2924         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2925                 intel_hpd_poll_init(dev_priv);
2926
2927         DRM_DEBUG_KMS("Device suspended\n");
2928         return 0;
2929 }
2930
2931 static int intel_runtime_resume(struct device *kdev)
2932 {
2933         struct pci_dev *pdev = to_pci_dev(kdev);
2934         struct drm_device *dev = pci_get_drvdata(pdev);
2935         struct drm_i915_private *dev_priv = to_i915(dev);
2936         int ret = 0;
2937
2938         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
2939                 return -ENODEV;
2940
2941         DRM_DEBUG_KMS("Resuming device\n");
2942
2943         WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
2944         disable_rpm_wakeref_asserts(dev_priv);
2945
2946         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2947         dev_priv->runtime_pm.suspended = false;
2948         if (intel_uncore_unclaimed_mmio(dev_priv))
2949                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2950
2951         if (INTEL_GEN(dev_priv) >= 11) {
2952                 bxt_disable_dc9(dev_priv);
2953                 icl_display_core_init(dev_priv, true);
2954                 if (dev_priv->csr.dmc_payload) {
2955                         if (dev_priv->csr.allowed_dc_mask &
2956                             DC_STATE_EN_UPTO_DC6)
2957                                 skl_enable_dc6(dev_priv);
2958                         else if (dev_priv->csr.allowed_dc_mask &
2959                                  DC_STATE_EN_UPTO_DC5)
2960                                 gen9_enable_dc5(dev_priv);
2961                 }
2962         } else if (IS_GEN9_LP(dev_priv)) {
2963                 bxt_disable_dc9(dev_priv);
2964                 bxt_display_core_init(dev_priv, true);
2965                 if (dev_priv->csr.dmc_payload &&
2966                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2967                         gen9_enable_dc5(dev_priv);
2968         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2969                 hsw_disable_pc8(dev_priv);
2970         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2971                 ret = vlv_resume_prepare(dev_priv, true);
2972         }
2973
2974         intel_uncore_runtime_resume(dev_priv);
2975
2976         intel_runtime_pm_enable_interrupts(dev_priv);
2977
2978         intel_uc_resume(dev_priv);
2979
2980         /*
2981          * No point of rolling back things in case of an error, as the best
2982          * we can do is to hope that things will still work (and disable RPM).
2983          */
2984         i915_gem_init_swizzling(dev_priv);
2985         i915_gem_restore_fences(dev_priv);
2986
2987         /*
2988          * On VLV/CHV display interrupts are part of the display
2989          * power well, so hpd is reinitialized from there. For
2990          * everyone else do it here.
2991          */
2992         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2993                 intel_hpd_init(dev_priv);
2994
2995         intel_enable_ipc(dev_priv);
2996
2997         enable_rpm_wakeref_asserts(dev_priv);
2998
2999         if (ret)
3000                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
3001         else
3002                 DRM_DEBUG_KMS("Device resumed\n");
3003
3004         return ret;
3005 }
3006
3007 const struct dev_pm_ops i915_pm_ops = {
3008         /*
3009          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
3010          * PMSG_RESUME]
3011          */
3012         .prepare = i915_pm_prepare,
3013         .suspend = i915_pm_suspend,
3014         .suspend_late = i915_pm_suspend_late,
3015         .resume_early = i915_pm_resume_early,
3016         .resume = i915_pm_resume,
3017
3018         /*
3019          * S4 event handlers
3020          * @freeze, @freeze_late    : called (1) before creating the
3021          *                            hibernation image [PMSG_FREEZE] and
3022          *                            (2) after rebooting, before restoring
3023          *                            the image [PMSG_QUIESCE]
3024          * @thaw, @thaw_early       : called (1) after creating the hibernation
3025          *                            image, before writing it [PMSG_THAW]
3026          *                            and (2) after failing to create or
3027          *                            restore the image [PMSG_RECOVER]
3028          * @poweroff, @poweroff_late: called after writing the hibernation
3029          *                            image, before rebooting [PMSG_HIBERNATE]
3030          * @restore, @restore_early : called after rebooting and restoring the
3031          *                            hibernation image [PMSG_RESTORE]
3032          */
3033         .freeze = i915_pm_freeze,
3034         .freeze_late = i915_pm_freeze_late,
3035         .thaw_early = i915_pm_thaw_early,
3036         .thaw = i915_pm_thaw,
3037         .poweroff = i915_pm_suspend,
3038         .poweroff_late = i915_pm_poweroff_late,
3039         .restore_early = i915_pm_restore_early,
3040         .restore = i915_pm_restore,
3041
3042         /* S0ix (via runtime suspend) event handlers */
3043         .runtime_suspend = intel_runtime_suspend,
3044         .runtime_resume = intel_runtime_resume,
3045 };
3046
3047 static const struct vm_operations_struct i915_gem_vm_ops = {
3048         .fault = i915_gem_fault,
3049         .open = drm_gem_vm_open,
3050         .close = drm_gem_vm_close,
3051 };
3052
3053 static const struct file_operations i915_driver_fops = {
3054         .owner = THIS_MODULE,
3055         .open = drm_open,
3056         .release = drm_release,
3057         .unlocked_ioctl = drm_ioctl,
3058         .mmap = drm_gem_mmap,
3059         .poll = drm_poll,
3060         .read = drm_read,
3061         .compat_ioctl = i915_compat_ioctl,
3062         .llseek = noop_llseek,
3063 };
3064
3065 static int
3066 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
3067                           struct drm_file *file)
3068 {
3069         return -ENODEV;
3070 }
3071
3072 static const struct drm_ioctl_desc i915_ioctls[] = {
3073         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3074         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
3075         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
3076         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
3077         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
3078         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
3079         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3080         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3081         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
3082         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
3083         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3084         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
3085         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3086         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3087         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
3088         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
3089         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3090         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3091         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
3092         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3093         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3094         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
3095         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3096         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
3097         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
3098         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3099         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3100         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3101         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
3102         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
3103         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
3104         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
3105         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
3106         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
3107         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
3108         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
3109         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
3110         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
3111         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
3112         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
3113         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
3114         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
3115         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
3116         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
3117         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3118         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
3119         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
3120         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
3121         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
3122         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
3123         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
3124         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
3125         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
3126         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3127         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3128         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3129 };
3130
3131 static struct drm_driver driver = {
3132         /* Don't use MTRRs here; the Xserver or userspace app should
3133          * deal with them for Intel hardware.
3134          */
3135         .driver_features =
3136             DRIVER_GEM | DRIVER_PRIME |
3137             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
3138         .release = i915_driver_release,
3139         .open = i915_driver_open,
3140         .lastclose = i915_driver_lastclose,
3141         .postclose = i915_driver_postclose,
3142
3143         .gem_close_object = i915_gem_close_object,
3144         .gem_free_object_unlocked = i915_gem_free_object,
3145         .gem_vm_ops = &i915_gem_vm_ops,
3146
3147         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
3148         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
3149         .gem_prime_export = i915_gem_prime_export,
3150         .gem_prime_import = i915_gem_prime_import,
3151
3152         .dumb_create = i915_gem_dumb_create,
3153         .dumb_map_offset = i915_gem_mmap_gtt,
3154         .ioctls = i915_ioctls,
3155         .num_ioctls = ARRAY_SIZE(i915_ioctls),
3156         .fops = &i915_driver_fops,
3157         .name = DRIVER_NAME,
3158         .desc = DRIVER_DESC,
3159         .date = DRIVER_DATE,
3160         .major = DRIVER_MAJOR,
3161         .minor = DRIVER_MINOR,
3162         .patchlevel = DRIVER_PATCHLEVEL,
3163 };
3164
3165 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3166 #include "selftests/mock_drm.c"
3167 #endif