drivers/gpu/drm/i915/display/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/delay.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/i2c.h>
  32 #include <linux/slab.h>
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_hdcp.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <drm/i915_drm.h>
  40 #include <drm/intel_lpe_audio.h>
  41
  42 #include "i915_debugfs.h"
  43 #include "i915_drv.h"
  44 #include "intel_atomic.h"
  45 #include "intel_audio.h"
  46 #include "intel_connector.h"
  47 #include "intel_ddi.h"
  48 #include "intel_display_types.h"
  49 #include "intel_dp.h"
  50 #include "intel_dpio_phy.h"
  51 #include "intel_fifo_underrun.h"
  52 #include "intel_gmbus.h"
  53 #include "intel_hdcp.h"
  54 #include "intel_hdmi.h"
  55 #include "intel_hotplug.h"
  56 #include "intel_lspcon.h"
  57 #include "intel_panel.h"
  58 #include "intel_sdvo.h"
  59 #include "intel_sideband.h"
  60
  61 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  62 {
  63         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  64 }
  65
  66 static void
  67 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  68 {
  69         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  70         struct drm_i915_private *dev_priv = to_i915(dev);
  71         u32 enabled_bits;
  72
  73         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  74
  75         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  76              "HDMI port enabled, expecting disabled\n");
  77 }
  78
  79 static void
  80 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  81                                      enum transcoder cpu_transcoder)
  82 {
  83         WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  84              TRANS_DDI_FUNC_ENABLE,
  85              "HDMI transcoder function enabled, expecting disabled\n");
  86 }
  87
  88 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  89 {
  90         struct intel_digital_port *intel_dig_port =
  91                 container_of(encoder, struct intel_digital_port, base.base);
  92         return &intel_dig_port->hdmi;
  93 }
  94
  95 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  96 {
  97         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  98 }
  99
 100 static u32 g4x_infoframe_index(unsigned int type)
 101 {
 102         switch (type) {
 103         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 104                 return VIDEO_DIP_SELECT_GAMUT;
 105         case HDMI_INFOFRAME_TYPE_AVI:
 106                 return VIDEO_DIP_SELECT_AVI;
 107         case HDMI_INFOFRAME_TYPE_SPD:
 108                 return VIDEO_DIP_SELECT_SPD;
 109         case HDMI_INFOFRAME_TYPE_VENDOR:
 110                 return VIDEO_DIP_SELECT_VENDOR;
 111         default:
 112                 MISSING_CASE(type);
 113                 return 0;
 114         }
 115 }
 116
 117 static u32 g4x_infoframe_enable(unsigned int type)
 118 {
 119         switch (type) {
 120         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 121                 return VIDEO_DIP_ENABLE_GCP;
 122         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 123                 return VIDEO_DIP_ENABLE_GAMUT;
 124         case DP_SDP_VSC:
 125                 return 0;
 126         case HDMI_INFOFRAME_TYPE_AVI:
 127                 return VIDEO_DIP_ENABLE_AVI;
 128         case HDMI_INFOFRAME_TYPE_SPD:
 129                 return VIDEO_DIP_ENABLE_SPD;
 130         case HDMI_INFOFRAME_TYPE_VENDOR:
 131                 return VIDEO_DIP_ENABLE_VENDOR;
 132         case HDMI_INFOFRAME_TYPE_DRM:
 133                 return 0;
 134         default:
 135                 MISSING_CASE(type);
 136                 return 0;
 137         }
 138 }
 139
 140 static u32 hsw_infoframe_enable(unsigned int type)
 141 {
 142         switch (type) {
 143         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 144                 return VIDEO_DIP_ENABLE_GCP_HSW;
 145         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 146                 return VIDEO_DIP_ENABLE_GMP_HSW;
 147         case DP_SDP_VSC:
 148                 return VIDEO_DIP_ENABLE_VSC_HSW;
 149         case DP_SDP_PPS:
 150                 return VDIP_ENABLE_PPS;
 151         case HDMI_INFOFRAME_TYPE_AVI:
 152                 return VIDEO_DIP_ENABLE_AVI_HSW;
 153         case HDMI_INFOFRAME_TYPE_SPD:
 154                 return VIDEO_DIP_ENABLE_SPD_HSW;
 155         case HDMI_INFOFRAME_TYPE_VENDOR:
 156                 return VIDEO_DIP_ENABLE_VS_HSW;
 157         case HDMI_INFOFRAME_TYPE_DRM:
 158                 return VIDEO_DIP_ENABLE_DRM_GLK;
 159         default:
 160                 MISSING_CASE(type);
 161                 return 0;
 162         }
 163 }
 164
 165 static i915_reg_t
 166 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 167                  enum transcoder cpu_transcoder,
 168                  unsigned int type,
 169                  int i)
 170 {
 171         switch (type) {
 172         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 173                 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
 174         case DP_SDP_VSC:
 175                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 176         case DP_SDP_PPS:
 177                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 178         case HDMI_INFOFRAME_TYPE_AVI:
 179                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 180         case HDMI_INFOFRAME_TYPE_SPD:
 181                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 182         case HDMI_INFOFRAME_TYPE_VENDOR:
 183                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 184         case HDMI_INFOFRAME_TYPE_DRM:
 185                 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
 186         default:
 187                 MISSING_CASE(type);
 188                 return INVALID_MMIO_REG;
 189         }
 190 }
 191
 192 static int hsw_dip_data_size(unsigned int type)
 193 {
 194         switch (type) {
 195         case DP_SDP_VSC:
 196                 return VIDEO_DIP_VSC_DATA_SIZE;
 197         case DP_SDP_PPS:
 198                 return VIDEO_DIP_PPS_DATA_SIZE;
 199         default:
 200                 return VIDEO_DIP_DATA_SIZE;
 201         }
 202 }
 203
 204 static void g4x_write_infoframe(struct intel_encoder *encoder,
 205                                 const struct intel_crtc_state *crtc_state,
 206                                 unsigned int type,
 207                                 const void *frame, ssize_t len)
 208 {
 209         const u32 *data = frame;
 210         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 211         u32 val = I915_READ(VIDEO_DIP_CTL);
 212         int i;
 213
 214         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 215
 216         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 217         val |= g4x_infoframe_index(type);
 218
 219         val &= ~g4x_infoframe_enable(type);
 220
 221         I915_WRITE(VIDEO_DIP_CTL, val);
 222
 223         for (i = 0; i < len; i += 4) {
 224                 I915_WRITE(VIDEO_DIP_DATA, *data);
 225                 data++;
 226         }
 227         /* Write every possible data byte to force correct ECC calculation. */
 228         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 229                 I915_WRITE(VIDEO_DIP_DATA, 0);
 230
 231         val |= g4x_infoframe_enable(type);
 232         val &= ~VIDEO_DIP_FREQ_MASK;
 233         val |= VIDEO_DIP_FREQ_VSYNC;
 234
 235         I915_WRITE(VIDEO_DIP_CTL, val);
 236         POSTING_READ(VIDEO_DIP_CTL);
 237 }
 238
 239 static void g4x_read_infoframe(struct intel_encoder *encoder,
 240                                const struct intel_crtc_state *crtc_state,
 241                                unsigned int type,
 242                                void *frame, ssize_t len)
 243 {
 244         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 245         u32 val, *data = frame;
 246         int i;
 247
 248         val = I915_READ(VIDEO_DIP_CTL);
 249
 250         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 251         val |= g4x_infoframe_index(type);
 252
 253         I915_WRITE(VIDEO_DIP_CTL, val);
 254
 255         for (i = 0; i < len; i += 4)
 256                 *data++ = I915_READ(VIDEO_DIP_DATA);
 257 }
 258
 259 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
 260                                   const struct intel_crtc_state *pipe_config)
 261 {
 262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 263         u32 val = I915_READ(VIDEO_DIP_CTL);
 264
 265         if ((val & VIDEO_DIP_ENABLE) == 0)
 266                 return 0;
 267
 268         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 269                 return 0;
 270
 271         return val & (VIDEO_DIP_ENABLE_AVI |
 272                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 273 }
 274
 275 static void ibx_write_infoframe(struct intel_encoder *encoder,
 276                                 const struct intel_crtc_state *crtc_state,
 277                                 unsigned int type,
 278                                 const void *frame, ssize_t len)
 279 {
 280         const u32 *data = frame;
 281         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 283         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 284         u32 val = I915_READ(reg);
 285         int i;
 286
 287         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 288
 289         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 290         val |= g4x_infoframe_index(type);
 291
 292         val &= ~g4x_infoframe_enable(type);
 293
 294         I915_WRITE(reg, val);
 295
 296         for (i = 0; i < len; i += 4) {
 297                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 298                 data++;
 299         }
 300         /* Write every possible data byte to force correct ECC calculation. */
 301         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 302                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 303
 304         val |= g4x_infoframe_enable(type);
 305         val &= ~VIDEO_DIP_FREQ_MASK;
 306         val |= VIDEO_DIP_FREQ_VSYNC;
 307
 308         I915_WRITE(reg, val);
 309         POSTING_READ(reg);
 310 }
 311
 312 static void ibx_read_infoframe(struct intel_encoder *encoder,
 313                                const struct intel_crtc_state *crtc_state,
 314                                unsigned int type,
 315                                void *frame, ssize_t len)
 316 {
 317         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 318         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 319         u32 val, *data = frame;
 320         int i;
 321
 322         val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
 323
 324         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 325         val |= g4x_infoframe_index(type);
 326
 327         I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
 328
 329         for (i = 0; i < len; i += 4)
 330                 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
 331 }
 332
 333 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
 334                                   const struct intel_crtc_state *pipe_config)
 335 {
 336         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 337         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 338         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 339         u32 val = I915_READ(reg);
 340
 341         if ((val & VIDEO_DIP_ENABLE) == 0)
 342                 return 0;
 343
 344         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 345                 return 0;
 346
 347         return val & (VIDEO_DIP_ENABLE_AVI |
 348                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 349                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 350 }
 351
 352 static void cpt_write_infoframe(struct intel_encoder *encoder,
 353                                 const struct intel_crtc_state *crtc_state,
 354                                 unsigned int type,
 355                                 const void *frame, ssize_t len)
 356 {
 357         const u32 *data = frame;
 358         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 359         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 360         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 361         u32 val = I915_READ(reg);
 362         int i;
 363
 364         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 365
 366         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 367         val |= g4x_infoframe_index(type);
 368
 369         /* The DIP control register spec says that we need to update the AVI
 370          * infoframe without clearing its enable bit */
 371         if (type != HDMI_INFOFRAME_TYPE_AVI)
 372                 val &= ~g4x_infoframe_enable(type);
 373
 374         I915_WRITE(reg, val);
 375
 376         for (i = 0; i < len; i += 4) {
 377                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 378                 data++;
 379         }
 380         /* Write every possible data byte to force correct ECC calculation. */
 381         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 382                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 383
 384         val |= g4x_infoframe_enable(type);
 385         val &= ~VIDEO_DIP_FREQ_MASK;
 386         val |= VIDEO_DIP_FREQ_VSYNC;
 387
 388         I915_WRITE(reg, val);
 389         POSTING_READ(reg);
 390 }
 391
 392 static void cpt_read_infoframe(struct intel_encoder *encoder,
 393                                const struct intel_crtc_state *crtc_state,
 394                                unsigned int type,
 395                                void *frame, ssize_t len)
 396 {
 397         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 398         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 399         u32 val, *data = frame;
 400         int i;
 401
 402         val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
 403
 404         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 405         val |= g4x_infoframe_index(type);
 406
 407         I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
 408
 409         for (i = 0; i < len; i += 4)
 410                 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
 411 }
 412
 413 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
 414                                   const struct intel_crtc_state *pipe_config)
 415 {
 416         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 417         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 418         u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
 419
 420         if ((val & VIDEO_DIP_ENABLE) == 0)
 421                 return 0;
 422
 423         return val & (VIDEO_DIP_ENABLE_AVI |
 424                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 425                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 426 }
 427
 428 static void vlv_write_infoframe(struct intel_encoder *encoder,
 429                                 const struct intel_crtc_state *crtc_state,
 430                                 unsigned int type,
 431                                 const void *frame, ssize_t len)
 432 {
 433         const u32 *data = frame;
 434         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 435         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
 436         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 437         u32 val = I915_READ(reg);
 438         int i;
 439
 440         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 441
 442         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 443         val |= g4x_infoframe_index(type);
 444
 445         val &= ~g4x_infoframe_enable(type);
 446
 447         I915_WRITE(reg, val);
 448
 449         for (i = 0; i < len; i += 4) {
 450                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 451                 data++;
 452         }
 453         /* Write every possible data byte to force correct ECC calculation. */
 454         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 455                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 456
 457         val |= g4x_infoframe_enable(type);
 458         val &= ~VIDEO_DIP_FREQ_MASK;
 459         val |= VIDEO_DIP_FREQ_VSYNC;
 460
 461         I915_WRITE(reg, val);
 462         POSTING_READ(reg);
 463 }
 464
 465 static void vlv_read_infoframe(struct intel_encoder *encoder,
 466                                const struct intel_crtc_state *crtc_state,
 467                                unsigned int type,
 468                                void *frame, ssize_t len)
 469 {
 470         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 471         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 472         u32 val, *data = frame;
 473         int i;
 474
 475         val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe));
 476
 477         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 478         val |= g4x_infoframe_index(type);
 479
 480         I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
 481
 482         for (i = 0; i < len; i += 4)
 483                 *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe));
 484 }
 485
 486 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
 487                                   const struct intel_crtc_state *pipe_config)
 488 {
 489         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 490         enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
 491         u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
 492
 493         if ((val & VIDEO_DIP_ENABLE) == 0)
 494                 return 0;
 495
 496         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 497                 return 0;
 498
 499         return val & (VIDEO_DIP_ENABLE_AVI |
 500                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 501                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 502 }
 503
 504 static void hsw_write_infoframe(struct intel_encoder *encoder,
 505                                 const struct intel_crtc_state *crtc_state,
 506                                 unsigned int type,
 507                                 const void *frame, ssize_t len)
 508 {
 509         const u32 *data = frame;
 510         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 511         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 512         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 513         int data_size;
 514         int i;
 515         u32 val = I915_READ(ctl_reg);
 516
 517         data_size = hsw_dip_data_size(type);
 518
 519         val &= ~hsw_infoframe_enable(type);
 520         I915_WRITE(ctl_reg, val);
 521
 522         for (i = 0; i < len; i += 4) {
 523                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 524                                             type, i >> 2), *data);
 525                 data++;
 526         }
 527         /* Write every possible data byte to force correct ECC calculation. */
 528         for (; i < data_size; i += 4)
 529                 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 530                                             type, i >> 2), 0);
 531
 532         val |= hsw_infoframe_enable(type);
 533         I915_WRITE(ctl_reg, val);
 534         POSTING_READ(ctl_reg);
 535 }
 536
 537 static void hsw_read_infoframe(struct intel_encoder *encoder,
 538                                const struct intel_crtc_state *crtc_state,
 539                                unsigned int type,
 540                                void *frame, ssize_t len)
 541 {
 542         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 543         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 544         u32 val, *data = frame;
 545         int i;
 546
 547         val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder));
 548
 549         for (i = 0; i < len; i += 4)
 550                 *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder,
 551                                                      type, i >> 2));
 552 }
 553
 554 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 555                                   const struct intel_crtc_state *pipe_config)
 556 {
 557         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 558         u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 559         u32 mask;
 560
 561         mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 562                 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 563                 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 564
 565         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 566                 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
 567
 568         return val & mask;
 569 }
 570
 571 static const u8 infoframe_type_to_idx[] = {
 572         HDMI_PACKET_TYPE_GENERAL_CONTROL,
 573         HDMI_PACKET_TYPE_GAMUT_METADATA,
 574         DP_SDP_VSC,
 575         HDMI_INFOFRAME_TYPE_AVI,
 576         HDMI_INFOFRAME_TYPE_SPD,
 577         HDMI_INFOFRAME_TYPE_VENDOR,
 578         HDMI_INFOFRAME_TYPE_DRM,
 579 };
 580
 581 u32 intel_hdmi_infoframe_enable(unsigned int type)
 582 {
 583         int i;
 584
 585         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 586                 if (infoframe_type_to_idx[i] == type)
 587                         return BIT(i);
 588         }
 589
 590         return 0;
 591 }
 592
 593 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
 594                                   const struct intel_crtc_state *crtc_state)
 595 {
 596         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 597         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
 598         u32 val, ret = 0;
 599         int i;
 600
 601         val = dig_port->infoframes_enabled(encoder, crtc_state);
 602
 603         /* map from hardware bits to dip idx */
 604         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 605                 unsigned int type = infoframe_type_to_idx[i];
 606
 607                 if (HAS_DDI(dev_priv)) {
 608                         if (val & hsw_infoframe_enable(type))
 609                                 ret |= BIT(i);
 610                 } else {
 611                         if (val & g4x_infoframe_enable(type))
 612                                 ret |= BIT(i);
 613                 }
 614         }
 615
 616         return ret;
 617 }
 618
 619 /*
 620  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 621  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 622  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 623  * used for both technologies.
 624  *
 625  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 626  * DW1:       DB3       | DB2 | DB1 | DB0
 627  * DW2:       DB7       | DB6 | DB5 | DB4
 628  * DW3: ...
 629  *
 630  * (HB is Header Byte, DB is Data Byte)
 631  *
 632  * The hdmi pack() functions don't know about that hardware specific hole so we
 633  * trick them by giving an offset into the buffer and moving back the header
 634  * bytes by one.
 635  */
 636 static void intel_write_infoframe(struct intel_encoder *encoder,
 637                                   const struct intel_crtc_state *crtc_state,
 638                                   enum hdmi_infoframe_type type,
 639                                   const union hdmi_infoframe *frame)
 640 {
 641         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 642         u8 buffer[VIDEO_DIP_DATA_SIZE];
 643         ssize_t len;
 644
 645         if ((crtc_state->infoframes.enable &
 646              intel_hdmi_infoframe_enable(type)) == 0)
 647                 return;
 648
 649         if (WARN_ON(frame->any.type != type))
 650                 return;
 651
 652         /* see comment above for the reason for this offset */
 653         len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
 654         if (WARN_ON(len < 0))
 655                 return;
 656
 657         /* Insert the 'hole' (see big comment above) at position 3 */
 658         memmove(&buffer[0], &buffer[1], 3);
 659         buffer[3] = 0;
 660         len++;
 661
 662         intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
 663 }
 664
 665 void intel_read_infoframe(struct intel_encoder *encoder,
 666                           const struct intel_crtc_state *crtc_state,
 667                           enum hdmi_infoframe_type type,
 668                           union hdmi_infoframe *frame)
 669 {
 670         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 671         u8 buffer[VIDEO_DIP_DATA_SIZE];
 672         int ret;
 673
 674         if ((crtc_state->infoframes.enable &
 675              intel_hdmi_infoframe_enable(type)) == 0)
 676                 return;
 677
 678         intel_dig_port->read_infoframe(encoder, crtc_state,
 679                                        type, buffer, sizeof(buffer));
 680
 681         /* Fill the 'hole' (see big comment above) at position 3 */
 682         memmove(&buffer[1], &buffer[0], 3);
 683
 684         /* see comment above for the reason for this offset */
 685         ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
 686         if (ret) {
 687                 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type);
 688                 return;
 689         }
 690
 691         if (frame->any.type != type)
 692                 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
 693                               frame->any.type, type);
 694 }
 695
 696 static bool
 697 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
 698                                  struct intel_crtc_state *crtc_state,
 699                                  struct drm_connector_state *conn_state)
 700 {
 701         struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 702         const struct drm_display_mode *adjusted_mode =
 703                 &crtc_state->base.adjusted_mode;
 704         struct drm_connector *connector = conn_state->connector;
 705         int ret;
 706
 707         if (!crtc_state->has_infoframe)
 708                 return true;
 709
 710         crtc_state->infoframes.enable |=
 711                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
 712
 713         ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
 714                                                        adjusted_mode);
 715         if (ret)
 716                 return false;
 717
 718         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 719                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 720         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 721                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 722         else
 723                 frame->colorspace = HDMI_COLORSPACE_RGB;
 724
 725         drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
 726
 727         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
 728                 drm_hdmi_avi_infoframe_quant_range(frame, connector,
 729                                                    adjusted_mode,
 730                                                    crtc_state->limited_color_range ?
 731                                                    HDMI_QUANTIZATION_RANGE_LIMITED :
 732                                                    HDMI_QUANTIZATION_RANGE_FULL);
 733         } else {
 734                 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
 735                 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
 736         }
 737
 738         drm_hdmi_avi_infoframe_content_type(frame, conn_state);
 739
 740         /* TODO: handle pixel repetition for YCBCR420 outputs */
 741
 742         ret = hdmi_avi_infoframe_check(frame);
 743         if (WARN_ON(ret))
 744                 return false;
 745
 746         return true;
 747 }
 748
 749 static bool
 750 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
 751                                  struct intel_crtc_state *crtc_state,
 752                                  struct drm_connector_state *conn_state)
 753 {
 754         struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
 755         int ret;
 756
 757         if (!crtc_state->has_infoframe)
 758                 return true;
 759
 760         crtc_state->infoframes.enable |=
 761                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
 762
 763         ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
 764         if (WARN_ON(ret))
 765                 return false;
 766
 767         frame->sdi = HDMI_SPD_SDI_PC;
 768
 769         ret = hdmi_spd_infoframe_check(frame);
 770         if (WARN_ON(ret))
 771                 return false;
 772
 773         return true;
 774 }
 775
 776 static bool
 777 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
 778                                   struct intel_crtc_state *crtc_state,
 779                                   struct drm_connector_state *conn_state)
 780 {
 781         struct hdmi_vendor_infoframe *frame =
 782                 &crtc_state->infoframes.hdmi.vendor.hdmi;
 783         const struct drm_display_info *info =
 784                 &conn_state->connector->display_info;
 785         int ret;
 786
 787         if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
 788                 return true;
 789
 790         crtc_state->infoframes.enable |=
 791                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
 792
 793         ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
 794                                                           conn_state->connector,
 795                                                           &crtc_state->base.adjusted_mode);
 796         if (WARN_ON(ret))
 797                 return false;
 798
 799         ret = hdmi_vendor_infoframe_check(frame);
 800         if (WARN_ON(ret))
 801                 return false;
 802
 803         return true;
 804 }
 805
 806 static bool
 807 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
 808                                  struct intel_crtc_state *crtc_state,
 809                                  struct drm_connector_state *conn_state)
 810 {
 811         struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
 812         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 813         int ret;
 814
 815         if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
 816                 return true;
 817
 818         if (!crtc_state->has_infoframe)
 819                 return true;
 820
 821         if (!conn_state->hdr_output_metadata)
 822                 return true;
 823
 824         crtc_state->infoframes.enable |=
 825                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
 826
 827         ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
 828         if (ret < 0) {
 829                 DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
 830                 return false;
 831         }
 832
 833         ret = hdmi_drm_infoframe_check(frame);
 834         if (WARN_ON(ret))
 835                 return false;
 836
 837         return true;
 838 }
 839
 840 static void g4x_set_infoframes(struct intel_encoder *encoder,
 841                                bool enable,
 842                                const struct intel_crtc_state *crtc_state,
 843                                const struct drm_connector_state *conn_state)
 844 {
 845         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 846         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
 847         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 848         i915_reg_t reg = VIDEO_DIP_CTL;
 849         u32 val = I915_READ(reg);
 850         u32 port = VIDEO_DIP_PORT(encoder->port);
 851
 852         assert_hdmi_port_disabled(intel_hdmi);
 853
 854         /* If the registers were not initialized yet, they might be zeroes,
 855          * which means we're selecting the AVI DIP and we're setting its
 856          * frequency to once. This seems to really confuse the HW and make
 857          * things stop working (the register spec says the AVI always needs to
 858          * be sent every VSync). So here we avoid writing to the register more
 859          * than we need and also explicitly select the AVI DIP and explicitly
 860          * set its frequency to every VSync. Avoiding to write it twice seems to
 861          * be enough to solve the problem, but being defensive shouldn't hurt us
 862          * either. */
 863         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 864
 865         if (!enable) {
 866                 if (!(val & VIDEO_DIP_ENABLE))
 867                         return;
 868                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 869                         DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
 870                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 871                         return;
 872                 }
 873                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 874                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 875                 I915_WRITE(reg, val);
 876                 POSTING_READ(reg);
 877                 return;
 878         }
 879
 880         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 881                 if (val & VIDEO_DIP_ENABLE) {
 882                         DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
 883                                       (val & VIDEO_DIP_PORT_MASK) >> 29);
 884                         return;
 885                 }
 886                 val &= ~VIDEO_DIP_PORT_MASK;
 887                 val |= port;
 888         }
 889
 890         val |= VIDEO_DIP_ENABLE;
 891         val &= ~(VIDEO_DIP_ENABLE_AVI |
 892                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 893
 894         I915_WRITE(reg, val);
 895         POSTING_READ(reg);
 896
 897         intel_write_infoframe(encoder, crtc_state,
 898                               HDMI_INFOFRAME_TYPE_AVI,
 899                               &crtc_state->infoframes.avi);
 900         intel_write_infoframe(encoder, crtc_state,
 901                               HDMI_INFOFRAME_TYPE_SPD,
 902                               &crtc_state->infoframes.spd);
 903         intel_write_infoframe(encoder, crtc_state,
 904                               HDMI_INFOFRAME_TYPE_VENDOR,
 905                               &crtc_state->infoframes.hdmi);
 906 }
 907
 908 /*
 909  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 910  *
 911  * From HDMI specification 1.4a:
 912  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 913  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 914  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 915  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 916  *   phase of 0
 917  */
 918 static bool gcp_default_phase_possible(int pipe_bpp,
 919                                        const struct drm_display_mode *mode)
 920 {
 921         unsigned int pixels_per_group;
 922
 923         switch (pipe_bpp) {
 924         case 30:
 925                 /* 4 pixels in 5 clocks */
 926                 pixels_per_group = 4;
 927                 break;
 928         case 36:
 929                 /* 2 pixels in 3 clocks */
 930                 pixels_per_group = 2;
 931                 break;
 932         case 48:
 933                 /* 1 pixel in 2 clocks */
 934                 pixels_per_group = 1;
 935                 break;
 936         default:
 937                 /* phase information not relevant for 8bpc */
 938                 return false;
 939         }
 940
 941         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 942                 mode->crtc_htotal % pixels_per_group == 0 &&
 943                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 944                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 945                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 946                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 947                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 948                  mode->crtc_htotal/2 % pixels_per_group == 0);
 949 }
 950
 951 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 952                                          const struct intel_crtc_state *crtc_state,
 953                                          const struct drm_connector_state *conn_state)
 954 {
 955         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 956         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 957         i915_reg_t reg;
 958
 959         if ((crtc_state->infoframes.enable &
 960              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 961                 return false;
 962
 963         if (HAS_DDI(dev_priv))
 964                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 965         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 966                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 967         else if (HAS_PCH_SPLIT(dev_priv))
 968                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 969         else
 970                 return false;
 971
 972         I915_WRITE(reg, crtc_state->infoframes.gcp);
 973
 974         return true;
 975 }
 976
 977 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
 978                                    struct intel_crtc_state *crtc_state)
 979 {
 980         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 981         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 982         i915_reg_t reg;
 983
 984         if ((crtc_state->infoframes.enable &
 985              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 986                 return;
 987
 988         if (HAS_DDI(dev_priv))
 989                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 990         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 991                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 992         else if (HAS_PCH_SPLIT(dev_priv))
 993                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 994         else
 995                 return;
 996
 997         crtc_state->infoframes.gcp = I915_READ(reg);
 998 }
 999
1000 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1001                                              struct intel_crtc_state *crtc_state,
1002                                              struct drm_connector_state *conn_state)
1003 {
1004         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1005
1006         if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1007                 return;
1008
1009         crtc_state->infoframes.enable |=
1010                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1011
1012         /* Indicate color indication for deep color mode */
1013         if (crtc_state->pipe_bpp > 24)
1014                 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1015
1016         /* Enable default_phase whenever the display mode is suitably aligned */
1017         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1018                                        &crtc_state->base.adjusted_mode))
1019                 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1020 }
1021
1022 static void ibx_set_infoframes(struct intel_encoder *encoder,
1023                                bool enable,
1024                                const struct intel_crtc_state *crtc_state,
1025                                const struct drm_connector_state *conn_state)
1026 {
1027         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1028         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1029         struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1030         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1031         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1032         u32 val = I915_READ(reg);
1033         u32 port = VIDEO_DIP_PORT(encoder->port);
1034
1035         assert_hdmi_port_disabled(intel_hdmi);
1036
1037         /* See the big comment in g4x_set_infoframes() */
1038         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1039
1040         if (!enable) {
1041                 if (!(val & VIDEO_DIP_ENABLE))
1042                         return;
1043                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1044                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1045                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1046                 I915_WRITE(reg, val);
1047                 POSTING_READ(reg);
1048                 return;
1049         }
1050
1051         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1052                 WARN(val & VIDEO_DIP_ENABLE,
1053                      "DIP already enabled on port %c\n",
1054                      (val & VIDEO_DIP_PORT_MASK) >> 29);
1055                 val &= ~VIDEO_DIP_PORT_MASK;
1056                 val |= port;
1057         }
1058
1059         val |= VIDEO_DIP_ENABLE;
1060         val &= ~(VIDEO_DIP_ENABLE_AVI |
1061                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1062                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1063
1064         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1065                 val |= VIDEO_DIP_ENABLE_GCP;
1066
1067         I915_WRITE(reg, val);
1068         POSTING_READ(reg);
1069
1070         intel_write_infoframe(encoder, crtc_state,
1071                               HDMI_INFOFRAME_TYPE_AVI,
1072                               &crtc_state->infoframes.avi);
1073         intel_write_infoframe(encoder, crtc_state,
1074                               HDMI_INFOFRAME_TYPE_SPD,
1075                               &crtc_state->infoframes.spd);
1076         intel_write_infoframe(encoder, crtc_state,
1077                               HDMI_INFOFRAME_TYPE_VENDOR,
1078                               &crtc_state->infoframes.hdmi);
1079 }
1080
1081 static void cpt_set_infoframes(struct intel_encoder *encoder,
1082                                bool enable,
1083                                const struct intel_crtc_state *crtc_state,
1084                                const struct drm_connector_state *conn_state)
1085 {
1086         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1087         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1088         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1089         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1090         u32 val = I915_READ(reg);
1091
1092         assert_hdmi_port_disabled(intel_hdmi);
1093
1094         /* See the big comment in g4x_set_infoframes() */
1095         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1096
1097         if (!enable) {
1098                 if (!(val & VIDEO_DIP_ENABLE))
1099                         return;
1100                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1101                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1102                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1103                 I915_WRITE(reg, val);
1104                 POSTING_READ(reg);
1105                 return;
1106         }
1107
1108         /* Set both together, unset both together: see the spec. */
1109         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1110         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1111                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1112
1113         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1114                 val |= VIDEO_DIP_ENABLE_GCP;
1115
1116         I915_WRITE(reg, val);
1117         POSTING_READ(reg);
1118
1119         intel_write_infoframe(encoder, crtc_state,
1120                               HDMI_INFOFRAME_TYPE_AVI,
1121                               &crtc_state->infoframes.avi);
1122         intel_write_infoframe(encoder, crtc_state,
1123                               HDMI_INFOFRAME_TYPE_SPD,
1124                               &crtc_state->infoframes.spd);
1125         intel_write_infoframe(encoder, crtc_state,
1126                               HDMI_INFOFRAME_TYPE_VENDOR,
1127                               &crtc_state->infoframes.hdmi);
1128 }
1129
1130 static void vlv_set_infoframes(struct intel_encoder *encoder,
1131                                bool enable,
1132                                const struct intel_crtc_state *crtc_state,
1133                                const struct drm_connector_state *conn_state)
1134 {
1135         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1137         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1138         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1139         u32 val = I915_READ(reg);
1140         u32 port = VIDEO_DIP_PORT(encoder->port);
1141
1142         assert_hdmi_port_disabled(intel_hdmi);
1143
1144         /* See the big comment in g4x_set_infoframes() */
1145         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1146
1147         if (!enable) {
1148                 if (!(val & VIDEO_DIP_ENABLE))
1149                         return;
1150                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1151                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1152                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1153                 I915_WRITE(reg, val);
1154                 POSTING_READ(reg);
1155                 return;
1156         }
1157
1158         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1159                 WARN(val & VIDEO_DIP_ENABLE,
1160                      "DIP already enabled on port %c\n",
1161                      (val & VIDEO_DIP_PORT_MASK) >> 29);
1162                 val &= ~VIDEO_DIP_PORT_MASK;
1163                 val |= port;
1164         }
1165
1166         val |= VIDEO_DIP_ENABLE;
1167         val &= ~(VIDEO_DIP_ENABLE_AVI |
1168                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1169                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1170
1171         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1172                 val |= VIDEO_DIP_ENABLE_GCP;
1173
1174         I915_WRITE(reg, val);
1175         POSTING_READ(reg);
1176
1177         intel_write_infoframe(encoder, crtc_state,
1178                               HDMI_INFOFRAME_TYPE_AVI,
1179                               &crtc_state->infoframes.avi);
1180         intel_write_infoframe(encoder, crtc_state,
1181                               HDMI_INFOFRAME_TYPE_SPD,
1182                               &crtc_state->infoframes.spd);
1183         intel_write_infoframe(encoder, crtc_state,
1184                               HDMI_INFOFRAME_TYPE_VENDOR,
1185                               &crtc_state->infoframes.hdmi);
1186 }
1187
1188 static void hsw_set_infoframes(struct intel_encoder *encoder,
1189                                bool enable,
1190                                const struct intel_crtc_state *crtc_state,
1191                                const struct drm_connector_state *conn_state)
1192 {
1193         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1194         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1195         u32 val = I915_READ(reg);
1196
1197         assert_hdmi_transcoder_func_disabled(dev_priv,
1198                                              crtc_state->cpu_transcoder);
1199
1200         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1201                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1202                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1203                  VIDEO_DIP_ENABLE_DRM_GLK);
1204
1205         if (!enable) {
1206                 I915_WRITE(reg, val);
1207                 POSTING_READ(reg);
1208                 return;
1209         }
1210
1211         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1212                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1213
1214         I915_WRITE(reg, val);
1215         POSTING_READ(reg);
1216
1217         intel_write_infoframe(encoder, crtc_state,
1218                               HDMI_INFOFRAME_TYPE_AVI,
1219                               &crtc_state->infoframes.avi);
1220         intel_write_infoframe(encoder, crtc_state,
1221                               HDMI_INFOFRAME_TYPE_SPD,
1222                               &crtc_state->infoframes.spd);
1223         intel_write_infoframe(encoder, crtc_state,
1224                               HDMI_INFOFRAME_TYPE_VENDOR,
1225                               &crtc_state->infoframes.hdmi);
1226         intel_write_infoframe(encoder, crtc_state,
1227                               HDMI_INFOFRAME_TYPE_DRM,
1228                               &crtc_state->infoframes.drm);
1229 }
1230
1231 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1232 {
1233         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1234         struct i2c_adapter *adapter =
1235                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1236
1237         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1238                 return;
1239
1240         DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
1241                       enable ? "Enabling" : "Disabling");
1242
1243         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
1244                                          adapter, enable);
1245 }
1246
1247 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
1248                                 unsigned int offset, void *buffer, size_t size)
1249 {
1250         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1251         struct drm_i915_private *dev_priv =
1252                 intel_dig_port->base.base.dev->dev_private;
1253         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1254                                                               hdmi->ddc_bus);
1255         int ret;
1256         u8 start = offset & 0xff;
1257         struct i2c_msg msgs[] = {
1258                 {
1259                         .addr = DRM_HDCP_DDC_ADDR,
1260                         .flags = 0,
1261                         .len = 1,
1262                         .buf = &start,
1263                 },
1264                 {
1265                         .addr = DRM_HDCP_DDC_ADDR,
1266                         .flags = I2C_M_RD,
1267                         .len = size,
1268                         .buf = buffer
1269                 }
1270         };
1271         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1272         if (ret == ARRAY_SIZE(msgs))
1273                 return 0;
1274         return ret >= 0 ? -EIO : ret;
1275 }
1276
1277 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
1278                                  unsigned int offset, void *buffer, size_t size)
1279 {
1280         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1281         struct drm_i915_private *dev_priv =
1282                 intel_dig_port->base.base.dev->dev_private;
1283         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1284                                                               hdmi->ddc_bus);
1285         int ret;
1286         u8 *write_buf;
1287         struct i2c_msg msg;
1288
1289         write_buf = kzalloc(size + 1, GFP_KERNEL);
1290         if (!write_buf)
1291                 return -ENOMEM;
1292
1293         write_buf[0] = offset & 0xff;
1294         memcpy(&write_buf[1], buffer, size);
1295
1296         msg.addr = DRM_HDCP_DDC_ADDR;
1297         msg.flags = 0,
1298         msg.len = size + 1,
1299         msg.buf = write_buf;
1300
1301         ret = i2c_transfer(adapter, &msg, 1);
1302         if (ret == 1)
1303                 ret = 0;
1304         else if (ret >= 0)
1305                 ret = -EIO;
1306
1307         kfree(write_buf);
1308         return ret;
1309 }
1310
1311 static
1312 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
1313                                   u8 *an)
1314 {
1315         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1316         struct drm_i915_private *dev_priv =
1317                 intel_dig_port->base.base.dev->dev_private;
1318         struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1319                                                               hdmi->ddc_bus);
1320         int ret;
1321
1322         ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
1323                                     DRM_HDCP_AN_LEN);
1324         if (ret) {
1325                 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
1326                 return ret;
1327         }
1328
1329         ret = intel_gmbus_output_aksv(adapter);
1330         if (ret < 0) {
1331                 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
1332                 return ret;
1333         }
1334         return 0;
1335 }
1336
1337 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
1338                                      u8 *bksv)
1339 {
1340         int ret;
1341         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
1342                                    DRM_HDCP_KSV_LEN);
1343         if (ret)
1344                 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
1345         return ret;
1346 }
1347
1348 static
1349 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1350                                  u8 *bstatus)
1351 {
1352         int ret;
1353         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1354                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1355         if (ret)
1356                 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1357         return ret;
1358 }
1359
1360 static
1361 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1362                                      bool *repeater_present)
1363 {
1364         int ret;
1365         u8 val;
1366
1367         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1368         if (ret) {
1369                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1370                 return ret;
1371         }
1372         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1373         return 0;
1374 }
1375
1376 static
1377 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1378                                   u8 *ri_prime)
1379 {
1380         int ret;
1381         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1382                                    ri_prime, DRM_HDCP_RI_LEN);
1383         if (ret)
1384                 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1385         return ret;
1386 }
1387
1388 static
1389 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1390                                    bool *ksv_ready)
1391 {
1392         int ret;
1393         u8 val;
1394
1395         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1396         if (ret) {
1397                 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1398                 return ret;
1399         }
1400         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1401         return 0;
1402 }
1403
1404 static
1405 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1406                                   int num_downstream, u8 *ksv_fifo)
1407 {
1408         int ret;
1409         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1410                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1411         if (ret) {
1412                 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1413                 return ret;
1414         }
1415         return 0;
1416 }
1417
1418 static
1419 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1420                                       int i, u32 *part)
1421 {
1422         int ret;
1423
1424         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1425                 return -EINVAL;
1426
1427         ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1428                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1429         if (ret)
1430                 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1431         return ret;
1432 }
1433
1434 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector)
1435 {
1436         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1437         struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
1438         struct drm_crtc *crtc = connector->base.state->crtc;
1439         struct intel_crtc *intel_crtc = container_of(crtc,
1440                                                      struct intel_crtc, base);
1441         u32 scanline;
1442         int ret;
1443
1444         for (;;) {
1445                 scanline = I915_READ(PIPEDSL(intel_crtc->pipe));
1446                 if (scanline > 100 && scanline < 200)
1447                         break;
1448                 usleep_range(25, 50);
1449         }
1450
1451         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false);
1452         if (ret) {
1453                 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret);
1454                 return ret;
1455         }
1456         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true);
1457         if (ret) {
1458                 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret);
1459                 return ret;
1460         }
1461
1462         return 0;
1463 }
1464
1465 static
1466 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1467                                       bool enable)
1468 {
1469         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1470         struct intel_connector *connector = hdmi->attached_connector;
1471         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1472         int ret;
1473
1474         if (!enable)
1475                 usleep_range(6, 60); /* Bspec says >= 6us */
1476
1477         ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1478         if (ret) {
1479                 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1480                           enable ? "Enable" : "Disable", ret);
1481                 return ret;
1482         }
1483
1484         /*
1485          * WA: To fix incorrect positioning of the window of
1486          * opportunity and enc_en signalling in KABYLAKE.
1487          */
1488         if (IS_KABYLAKE(dev_priv) && enable)
1489                 return kbl_repositioning_enc_en_signal(connector);
1490
1491         return 0;
1492 }
1493
1494 static
1495 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1496 {
1497         struct drm_i915_private *dev_priv =
1498                 intel_dig_port->base.base.dev->dev_private;
1499         struct intel_connector *connector =
1500                 intel_dig_port->hdmi.attached_connector;
1501         enum port port = intel_dig_port->base.port;
1502         enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1503         int ret;
1504         union {
1505                 u32 reg;
1506                 u8 shim[DRM_HDCP_RI_LEN];
1507         } ri;
1508
1509         ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1510         if (ret)
1511                 return false;
1512
1513         I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg);
1514
1515         /* Wait for Ri prime match */
1516         if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
1517                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1518                 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1519                           I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
1520                                                 port)));
1521                 return false;
1522         }
1523         return true;
1524 }
1525
1526 struct hdcp2_hdmi_msg_data {
1527         u8 msg_id;
1528         u32 timeout;
1529         u32 timeout2;
1530 };
1531
1532 static const struct hdcp2_hdmi_msg_data hdcp2_msg_data[] = {
1533         { HDCP_2_2_AKE_INIT, 0, 0 },
1534         { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
1535         { HDCP_2_2_AKE_NO_STORED_KM, 0, 0 },
1536         { HDCP_2_2_AKE_STORED_KM, 0, 0 },
1537         { HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
1538           HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
1539         { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
1540         { HDCP_2_2_LC_INIT, 0, 0 },
1541         { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0 },
1542         { HDCP_2_2_SKE_SEND_EKS, 0, 0 },
1543         { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
1544         { HDCP_2_2_REP_SEND_ACK, 0, 0 },
1545         { HDCP_2_2_REP_STREAM_MANAGE, 0, 0 },
1546         { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
1547 };
1548
1549 static
1550 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
1551                                     u8 *rx_status)
1552 {
1553         return intel_hdmi_hdcp_read(intel_dig_port,
1554                                     HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1555                                     rx_status,
1556                                     HDCP_2_2_HDMI_RXSTATUS_LEN);
1557 }
1558
1559 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1560 {
1561         int i;
1562
1563         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++)
1564                 if (hdcp2_msg_data[i].msg_id == msg_id &&
1565                     (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired))
1566                         return hdcp2_msg_data[i].timeout;
1567                 else if (hdcp2_msg_data[i].msg_id == msg_id)
1568                         return hdcp2_msg_data[i].timeout2;
1569
1570         return -EINVAL;
1571 }
1572
1573 static inline
1574 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port,
1575                                   u8 msg_id, bool *msg_ready,
1576                                   ssize_t *msg_sz)
1577 {
1578         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1579         int ret;
1580
1581         ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status);
1582         if (ret < 0) {
1583                 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
1584                 return ret;
1585         }
1586
1587         *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1588                   rx_status[0]);
1589
1590         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1591                 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1592                              *msg_sz);
1593         else
1594                 *msg_ready = *msg_sz;
1595
1596         return 0;
1597 }
1598
1599 static ssize_t
1600 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
1601                               u8 msg_id, bool paired)
1602 {
1603         bool msg_ready = false;
1604         int timeout, ret;
1605         ssize_t msg_sz = 0;
1606
1607         timeout = get_hdcp2_msg_timeout(msg_id, paired);
1608         if (timeout < 0)
1609                 return timeout;
1610
1611         ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
1612                                                              msg_id, &msg_ready,
1613                                                              &msg_sz),
1614                          !ret && msg_ready && msg_sz, timeout * 1000,
1615                          1000, 5 * 1000);
1616         if (ret)
1617                 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n",
1618                               msg_id, ret, timeout);
1619
1620         return ret ? ret : msg_sz;
1621 }
1622
1623 static
1624 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
1625                                void *buf, size_t size)
1626 {
1627         unsigned int offset;
1628
1629         offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1630         return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
1631 }
1632
1633 static
1634 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
1635                               u8 msg_id, void *buf, size_t size)
1636 {
1637         struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1638         struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1639         unsigned int offset;
1640         ssize_t ret;
1641
1642         ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id,
1643                                             hdcp->is_paired);
1644         if (ret < 0)
1645                 return ret;
1646
1647         /*
1648          * Available msg size should be equal to or lesser than the
1649          * available buffer.
1650          */
1651         if (ret > size) {
1652                 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n",
1653                               ret, size);
1654                 return -1;
1655         }
1656
1657         offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1658         ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret);
1659         if (ret)
1660                 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret);
1661
1662         return ret;
1663 }
1664
1665 static
1666 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
1667 {
1668         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1669         int ret;
1670
1671         ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status);
1672         if (ret)
1673                 return ret;
1674
1675         /*
1676          * Re-auth request and Link Integrity Failures are represented by
1677          * same bit. i.e reauth_req.
1678          */
1679         if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1680                 ret = HDCP_REAUTH_REQUEST;
1681         else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1682                 ret = HDCP_TOPOLOGY_CHANGE;
1683
1684         return ret;
1685 }
1686
1687 static
1688 int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port,
1689                              bool *capable)
1690 {
1691         u8 hdcp2_version;
1692         int ret;
1693
1694         *capable = false;
1695         ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1696                                    &hdcp2_version, sizeof(hdcp2_version));
1697         if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1698                 *capable = true;
1699
1700         return ret;
1701 }
1702
1703 static inline
1704 enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void)
1705 {
1706         return HDCP_PROTOCOL_HDMI;
1707 }
1708
1709 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1710         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1711         .read_bksv = intel_hdmi_hdcp_read_bksv,
1712         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1713         .repeater_present = intel_hdmi_hdcp_repeater_present,
1714         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1715         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1716         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1717         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1718         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1719         .check_link = intel_hdmi_hdcp_check_link,
1720         .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1721         .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1722         .check_2_2_link = intel_hdmi_hdcp2_check_link,
1723         .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1724         .protocol = HDCP_PROTOCOL_HDMI,
1725 };
1726
1727 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1728                                const struct intel_crtc_state *crtc_state)
1729 {
1730         struct drm_device *dev = encoder->base.dev;
1731         struct drm_i915_private *dev_priv = to_i915(dev);
1732         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1733         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1734         const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1735         u32 hdmi_val;
1736
1737         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1738
1739         hdmi_val = SDVO_ENCODING_HDMI;
1740         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1741                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1742         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1743                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1744         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1745                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1746
1747         if (crtc_state->pipe_bpp > 24)
1748                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1749         else
1750                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1751
1752         if (crtc_state->has_hdmi_sink)
1753                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1754
1755         if (HAS_PCH_CPT(dev_priv))
1756                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1757         else if (IS_CHERRYVIEW(dev_priv))
1758                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1759         else
1760                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1761
1762         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1763         POSTING_READ(intel_hdmi->hdmi_reg);
1764 }
1765
1766 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1767                                     enum pipe *pipe)
1768 {
1769         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1770         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1771         intel_wakeref_t wakeref;
1772         bool ret;
1773
1774         wakeref = intel_display_power_get_if_enabled(dev_priv,
1775                                                      encoder->power_domain);
1776         if (!wakeref)
1777                 return false;
1778
1779         ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1780
1781         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1782
1783         return ret;
1784 }
1785
1786 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1787                                   struct intel_crtc_state *pipe_config)
1788 {
1789         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1790         struct drm_device *dev = encoder->base.dev;
1791         struct drm_i915_private *dev_priv = to_i915(dev);
1792         u32 tmp, flags = 0;
1793         int dotclock;
1794
1795         pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1796
1797         tmp = I915_READ(intel_hdmi->hdmi_reg);
1798
1799         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1800                 flags |= DRM_MODE_FLAG_PHSYNC;
1801         else
1802                 flags |= DRM_MODE_FLAG_NHSYNC;
1803
1804         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1805                 flags |= DRM_MODE_FLAG_PVSYNC;
1806         else
1807                 flags |= DRM_MODE_FLAG_NVSYNC;
1808
1809         if (tmp & HDMI_MODE_SELECT_HDMI)
1810                 pipe_config->has_hdmi_sink = true;
1811
1812         pipe_config->infoframes.enable |=
1813                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
1814
1815         if (pipe_config->infoframes.enable)
1816                 pipe_config->has_infoframe = true;
1817
1818         if (tmp & HDMI_AUDIO_ENABLE)
1819                 pipe_config->has_audio = true;
1820
1821         if (!HAS_PCH_SPLIT(dev_priv) &&
1822             tmp & HDMI_COLOR_RANGE_16_235)
1823                 pipe_config->limited_color_range = true;
1824
1825         pipe_config->base.adjusted_mode.flags |= flags;
1826
1827         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1828                 dotclock = pipe_config->port_clock * 2 / 3;
1829         else
1830                 dotclock = pipe_config->port_clock;
1831
1832         if (pipe_config->pixel_multiplier)
1833                 dotclock /= pipe_config->pixel_multiplier;
1834
1835         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1836
1837         pipe_config->lane_count = 4;
1838
1839         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
1840
1841         intel_read_infoframe(encoder, pipe_config,
1842                              HDMI_INFOFRAME_TYPE_AVI,
1843                              &pipe_config->infoframes.avi);
1844         intel_read_infoframe(encoder, pipe_config,
1845                              HDMI_INFOFRAME_TYPE_SPD,
1846                              &pipe_config->infoframes.spd);
1847         intel_read_infoframe(encoder, pipe_config,
1848                              HDMI_INFOFRAME_TYPE_VENDOR,
1849                              &pipe_config->infoframes.hdmi);
1850 }
1851
1852 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1853                                     const struct intel_crtc_state *pipe_config,
1854                                     const struct drm_connector_state *conn_state)
1855 {
1856         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1857
1858         WARN_ON(!pipe_config->has_hdmi_sink);
1859         DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1860                          pipe_name(crtc->pipe));
1861         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1862 }
1863
1864 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1865                             const struct intel_crtc_state *pipe_config,
1866                             const struct drm_connector_state *conn_state)
1867 {
1868         struct drm_device *dev = encoder->base.dev;
1869         struct drm_i915_private *dev_priv = to_i915(dev);
1870         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1871         u32 temp;
1872
1873         temp = I915_READ(intel_hdmi->hdmi_reg);
1874
1875         temp |= SDVO_ENABLE;
1876         if (pipe_config->has_audio)
1877                 temp |= HDMI_AUDIO_ENABLE;
1878
1879         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1880         POSTING_READ(intel_hdmi->hdmi_reg);
1881
1882         if (pipe_config->has_audio)
1883                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1884 }
1885
1886 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1887                             const struct intel_crtc_state *pipe_config,
1888                             const struct drm_connector_state *conn_state)
1889 {
1890         struct drm_device *dev = encoder->base.dev;
1891         struct drm_i915_private *dev_priv = to_i915(dev);
1892         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1893         u32 temp;
1894
1895         temp = I915_READ(intel_hdmi->hdmi_reg);
1896
1897         temp |= SDVO_ENABLE;
1898         if (pipe_config->has_audio)
1899                 temp |= HDMI_AUDIO_ENABLE;
1900
1901         /*
1902          * HW workaround, need to write this twice for issue
1903          * that may result in first write getting masked.
1904          */
1905         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1906         POSTING_READ(intel_hdmi->hdmi_reg);
1907         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1908         POSTING_READ(intel_hdmi->hdmi_reg);
1909
1910         /*
1911          * HW workaround, need to toggle enable bit off and on
1912          * for 12bpc with pixel repeat.
1913          *
1914          * FIXME: BSpec says this should be done at the end of
1915          * of the modeset sequence, so not sure if this isn't too soon.
1916          */
1917         if (pipe_config->pipe_bpp > 24 &&
1918             pipe_config->pixel_multiplier > 1) {
1919                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1920                 POSTING_READ(intel_hdmi->hdmi_reg);
1921
1922                 /*
1923                  * HW workaround, need to write this twice for issue
1924                  * that may result in first write getting masked.
1925                  */
1926                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1927                 POSTING_READ(intel_hdmi->hdmi_reg);
1928                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1929                 POSTING_READ(intel_hdmi->hdmi_reg);
1930         }
1931
1932         if (pipe_config->has_audio)
1933                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1934 }
1935
1936 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1937                             const struct intel_crtc_state *pipe_config,
1938                             const struct drm_connector_state *conn_state)
1939 {
1940         struct drm_device *dev = encoder->base.dev;
1941         struct drm_i915_private *dev_priv = to_i915(dev);
1942         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1943         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1944         enum pipe pipe = crtc->pipe;
1945         u32 temp;
1946
1947         temp = I915_READ(intel_hdmi->hdmi_reg);
1948
1949         temp |= SDVO_ENABLE;
1950         if (pipe_config->has_audio)
1951                 temp |= HDMI_AUDIO_ENABLE;
1952
1953         /*
1954          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1955          *
1956          * The procedure for 12bpc is as follows:
1957          * 1. disable HDMI clock gating
1958          * 2. enable HDMI with 8bpc
1959          * 3. enable HDMI with 12bpc
1960          * 4. enable HDMI clock gating
1961          */
1962
1963         if (pipe_config->pipe_bpp > 24) {
1964                 I915_WRITE(TRANS_CHICKEN1(pipe),
1965                            I915_READ(TRANS_CHICKEN1(pipe)) |
1966                            TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1967
1968                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1969                 temp |= SDVO_COLOR_FORMAT_8bpc;
1970         }
1971
1972         I915_WRITE(intel_hdmi->hdmi_reg, temp);
1973         POSTING_READ(intel_hdmi->hdmi_reg);
1974
1975         if (pipe_config->pipe_bpp > 24) {
1976                 temp &= ~SDVO_COLOR_FORMAT_MASK;
1977                 temp |= HDMI_COLOR_FORMAT_12bpc;
1978
1979                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1980                 POSTING_READ(intel_hdmi->hdmi_reg);
1981
1982                 I915_WRITE(TRANS_CHICKEN1(pipe),
1983                            I915_READ(TRANS_CHICKEN1(pipe)) &
1984                            ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1985         }
1986
1987         if (pipe_config->has_audio)
1988                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1989 }
1990
1991 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1992                             const struct intel_crtc_state *pipe_config,
1993                             const struct drm_connector_state *conn_state)
1994 {
1995 }
1996
1997 static void intel_disable_hdmi(struct intel_encoder *encoder,
1998                                const struct intel_crtc_state *old_crtc_state,
1999                                const struct drm_connector_state *old_conn_state)
2000 {
2001         struct drm_device *dev = encoder->base.dev;
2002         struct drm_i915_private *dev_priv = to_i915(dev);
2003         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2004         struct intel_digital_port *intel_dig_port =
2005                 hdmi_to_dig_port(intel_hdmi);
2006         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2007         u32 temp;
2008
2009         temp = I915_READ(intel_hdmi->hdmi_reg);
2010
2011         temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
2012         I915_WRITE(intel_hdmi->hdmi_reg, temp);
2013         POSTING_READ(intel_hdmi->hdmi_reg);
2014
2015         /*
2016          * HW workaround for IBX, we need to move the port
2017          * to transcoder A after disabling it to allow the
2018          * matching DP port to be enabled on transcoder A.
2019          */
2020         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
2021                 /*
2022                  * We get CPU/PCH FIFO underruns on the other pipe when
2023                  * doing the workaround. Sweep them under the rug.
2024                  */
2025                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2026                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2027
2028                 temp &= ~SDVO_PIPE_SEL_MASK;
2029                 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
2030                 /*
2031                  * HW workaround, need to write this twice for issue
2032                  * that may result in first write getting masked.
2033                  */
2034                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2035                 POSTING_READ(intel_hdmi->hdmi_reg);
2036                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2037                 POSTING_READ(intel_hdmi->hdmi_reg);
2038
2039                 temp &= ~SDVO_ENABLE;
2040                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2041                 POSTING_READ(intel_hdmi->hdmi_reg);
2042
2043                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
2044                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2045                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2046         }
2047
2048         intel_dig_port->set_infoframes(encoder,
2049                                        false,
2050                                        old_crtc_state, old_conn_state);
2051
2052         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2053 }
2054
2055 static void g4x_disable_hdmi(struct intel_encoder *encoder,
2056                              const struct intel_crtc_state *old_crtc_state,
2057                              const struct drm_connector_state *old_conn_state)
2058 {
2059         if (old_crtc_state->has_audio)
2060                 intel_audio_codec_disable(encoder,
2061                                           old_crtc_state, old_conn_state);
2062
2063         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2064 }
2065
2066 static void pch_disable_hdmi(struct intel_encoder *encoder,
2067                              const struct intel_crtc_state *old_crtc_state,
2068                              const struct drm_connector_state *old_conn_state)
2069 {
2070         if (old_crtc_state->has_audio)
2071                 intel_audio_codec_disable(encoder,
2072                                           old_crtc_state, old_conn_state);
2073 }
2074
2075 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
2076                                   const struct intel_crtc_state *old_crtc_state,
2077                                   const struct drm_connector_state *old_conn_state)
2078 {
2079         intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2080 }
2081
2082 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
2083 {
2084         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2085         const struct ddi_vbt_port_info *info =
2086                 &dev_priv->vbt.ddi_port_info[encoder->port];
2087         int max_tmds_clock;
2088
2089         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2090                 max_tmds_clock = 594000;
2091         else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
2092                 max_tmds_clock = 300000;
2093         else if (INTEL_GEN(dev_priv) >= 5)
2094                 max_tmds_clock = 225000;
2095         else
2096                 max_tmds_clock = 165000;
2097
2098         if (info->max_tmds_clock)
2099                 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
2100
2101         return max_tmds_clock;
2102 }
2103
2104 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
2105                                  bool respect_downstream_limits,
2106                                  bool force_dvi)
2107 {
2108         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2109         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
2110
2111         if (respect_downstream_limits) {
2112                 struct intel_connector *connector = hdmi->attached_connector;
2113                 const struct drm_display_info *info = &connector->base.display_info;
2114
2115                 if (hdmi->dp_dual_mode.max_tmds_clock)
2116                         max_tmds_clock = min(max_tmds_clock,
2117                                              hdmi->dp_dual_mode.max_tmds_clock);
2118
2119                 if (info->max_tmds_clock)
2120                         max_tmds_clock = min(max_tmds_clock,
2121                                              info->max_tmds_clock);
2122                 else if (!hdmi->has_hdmi_sink || force_dvi)
2123                         max_tmds_clock = min(max_tmds_clock, 165000);
2124         }
2125
2126         return max_tmds_clock;
2127 }
2128
2129 static enum drm_mode_status
2130 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
2131                       int clock, bool respect_downstream_limits,
2132                       bool force_dvi)
2133 {
2134         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
2135
2136         if (clock < 25000)
2137                 return MODE_CLOCK_LOW;
2138         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
2139                 return MODE_CLOCK_HIGH;
2140
2141         /* BXT DPLL can't generate 223-240 MHz */
2142         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
2143                 return MODE_CLOCK_RANGE;
2144
2145         /* CHV DPLL can't generate 216-240 MHz */
2146         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
2147                 return MODE_CLOCK_RANGE;
2148
2149         return MODE_OK;
2150 }
2151
2152 static enum drm_mode_status
2153 intel_hdmi_mode_valid(struct drm_connector *connector,
2154                       struct drm_display_mode *mode)
2155 {
2156         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2157         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
2158         struct drm_i915_private *dev_priv = to_i915(dev);
2159         enum drm_mode_status status;
2160         int clock;
2161         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
2162         bool force_dvi =
2163                 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
2164
2165         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
2166                 return MODE_NO_DBLESCAN;
2167
2168         clock = mode->clock;
2169
2170         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2171                 clock *= 2;
2172
2173         if (clock > max_dotclk)
2174                 return MODE_CLOCK_HIGH;
2175
2176         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2177                 clock *= 2;
2178
2179         if (drm_mode_is_420_only(&connector->display_info, mode))
2180                 clock /= 2;
2181
2182         /* check if we can do 8bpc */
2183         status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
2184
2185         if (hdmi->has_hdmi_sink && !force_dvi) {
2186                 /* if we can't do 8bpc we may still be able to do 12bpc */
2187                 if (status != MODE_OK && !HAS_GMCH(dev_priv))
2188                         status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
2189                                                        true, force_dvi);
2190
2191                 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2192                 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
2193                         status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
2194                                                        true, force_dvi);
2195         }
2196         if (status != MODE_OK)
2197                 return status;
2198
2199         return intel_mode_valid_max_plane_size(dev_priv, mode);
2200 }
2201
2202 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2203                                      int bpc)
2204 {
2205         struct drm_i915_private *dev_priv =
2206                 to_i915(crtc_state->base.crtc->dev);
2207         struct drm_atomic_state *state = crtc_state->base.state;
2208         struct drm_connector_state *connector_state;
2209         struct drm_connector *connector;
2210         const struct drm_display_mode *adjusted_mode =
2211                 &crtc_state->base.adjusted_mode;
2212         int i;
2213
2214         if (HAS_GMCH(dev_priv))
2215                 return false;
2216
2217         if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
2218                 return false;
2219
2220         if (crtc_state->pipe_bpp < bpc * 3)
2221                 return false;
2222
2223         if (!crtc_state->has_hdmi_sink)
2224                 return false;
2225
2226         /*
2227          * HDMI deep color affects the clocks, so it's only possible
2228          * when not cloning with other encoder types.
2229          */
2230         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
2231                 return false;
2232
2233         for_each_new_connector_in_state(state, connector, connector_state, i) {
2234                 const struct drm_display_info *info = &connector->display_info;
2235
2236                 if (connector_state->crtc != crtc_state->base.crtc)
2237                         continue;
2238
2239                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2240                         const struct drm_hdmi_info *hdmi = &info->hdmi;
2241
2242                         if (bpc == 12 && !(hdmi->y420_dc_modes &
2243                                            DRM_EDID_YCBCR420_DC_36))
2244                                 return false;
2245                         else if (bpc == 10 && !(hdmi->y420_dc_modes &
2246                                                 DRM_EDID_YCBCR420_DC_30))
2247                                 return false;
2248                 } else {
2249                         if (bpc == 12 && !(info->edid_hdmi_dc_modes &
2250                                            DRM_EDID_HDMI_DC_36))
2251                                 return false;
2252                         else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
2253                                                 DRM_EDID_HDMI_DC_30))
2254                                 return false;
2255                 }
2256         }
2257
2258         /* Display WA #1139: glk */
2259         if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
2260             adjusted_mode->htotal > 5460)
2261                 return false;
2262
2263         /* Display Wa_1405510057:icl */
2264         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2265             bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
2266             (adjusted_mode->crtc_hblank_end -
2267              adjusted_mode->crtc_hblank_start) % 8 == 2)
2268                 return false;
2269
2270         return true;
2271 }
2272
2273 static bool
2274 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
2275                            struct intel_crtc_state *config)
2276 {
2277         struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
2278
2279         if (!connector->ycbcr_420_allowed) {
2280                 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
2281                 return false;
2282         }
2283
2284         config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2285
2286         /* YCBCR 420 output conversion needs a scaler */
2287         if (skl_update_scaler_crtc(config)) {
2288                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2289                 return false;
2290         }
2291
2292         intel_pch_panel_fitting(intel_crtc, config,
2293                                 DRM_MODE_SCALE_FULLSCREEN);
2294
2295         return true;
2296 }
2297
2298 static int intel_hdmi_port_clock(int clock, int bpc)
2299 {
2300         /*
2301          * Need to adjust the port link by:
2302          *  1.5x for 12bpc
2303          *  1.25x for 10bpc
2304          */
2305         return clock * bpc / 8;
2306 }
2307
2308 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2309                                   struct intel_crtc_state *crtc_state,
2310                                   int clock, bool force_dvi)
2311 {
2312         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2313         int bpc;
2314
2315         for (bpc = 12; bpc >= 10; bpc -= 2) {
2316                 if (hdmi_deep_color_possible(crtc_state, bpc) &&
2317                     hdmi_port_clock_valid(intel_hdmi,
2318                                           intel_hdmi_port_clock(clock, bpc),
2319                                           true, force_dvi) == MODE_OK)
2320                         return bpc;
2321         }
2322
2323         return 8;
2324 }
2325
2326 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2327                                     struct intel_crtc_state *crtc_state,
2328                                     bool force_dvi)
2329 {
2330         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2331         const struct drm_display_mode *adjusted_mode =
2332                 &crtc_state->base.adjusted_mode;
2333         int bpc, clock = adjusted_mode->crtc_clock;
2334
2335         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2336                 clock *= 2;
2337
2338         /* YCBCR420 TMDS rate requirement is half the pixel clock */
2339         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2340                 clock /= 2;
2341
2342         bpc = intel_hdmi_compute_bpc(encoder, crtc_state,
2343                                      clock, force_dvi);
2344
2345         crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
2346
2347         /*
2348          * pipe_bpp could already be below 8bpc due to
2349          * FDI bandwidth constraints. We shouldn't bump it
2350          * back up to 8bpc in that case.
2351          */
2352         if (crtc_state->pipe_bpp > bpc * 3)
2353                 crtc_state->pipe_bpp = bpc * 3;
2354
2355         DRM_DEBUG_KMS("picking %d bpc for HDMI output (pipe bpp: %d)\n",
2356                       bpc, crtc_state->pipe_bpp);
2357
2358         if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2359                                   false, force_dvi) != MODE_OK) {
2360                 DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n",
2361                               crtc_state->port_clock);
2362                 return -EINVAL;
2363         }
2364
2365         return 0;
2366 }
2367
2368 static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2369                                            const struct drm_connector_state *conn_state)
2370 {
2371         const struct intel_digital_connector_state *intel_conn_state =
2372                 to_intel_digital_connector_state(conn_state);
2373         const struct drm_display_mode *adjusted_mode =
2374                 &crtc_state->base.adjusted_mode;
2375
2376         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2377                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2378                 return crtc_state->has_hdmi_sink &&
2379                         drm_default_rgb_quant_range(adjusted_mode) ==
2380                         HDMI_QUANTIZATION_RANGE_LIMITED;
2381         } else {
2382                 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2383         }
2384 }
2385
2386 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2387                               struct intel_crtc_state *pipe_config,
2388                               struct drm_connector_state *conn_state)
2389 {
2390         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2391         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2392         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2393         struct drm_connector *connector = conn_state->connector;
2394         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2395         struct intel_digital_connector_state *intel_conn_state =
2396                 to_intel_digital_connector_state(conn_state);
2397         bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
2398         int ret;
2399
2400         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2401                 return -EINVAL;
2402
2403         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2404         pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
2405
2406         if (pipe_config->has_hdmi_sink)
2407                 pipe_config->has_infoframe = true;
2408
2409         pipe_config->limited_color_range =
2410                 intel_hdmi_limited_color_range(pipe_config, conn_state);
2411
2412         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2413                 pipe_config->pixel_multiplier = 2;
2414
2415         if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
2416                 if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) {
2417                         DRM_ERROR("Can't support YCBCR420 output\n");
2418                         return -EINVAL;
2419                 }
2420         }
2421
2422         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2423                 pipe_config->has_pch_encoder = true;
2424
2425         if (pipe_config->has_hdmi_sink) {
2426                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2427                         pipe_config->has_audio = intel_hdmi->has_audio;
2428                 else
2429                         pipe_config->has_audio =
2430                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
2431         }
2432
2433         ret = intel_hdmi_compute_clock(encoder, pipe_config, force_dvi);
2434         if (ret)
2435                 return ret;
2436
2437         /* Set user selected PAR to incoming mode's member */
2438         adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
2439
2440         pipe_config->lane_count = 4;
2441
2442         if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
2443                                            IS_GEMINILAKE(dev_priv))) {
2444                 if (scdc->scrambling.low_rates)
2445                         pipe_config->hdmi_scrambling = true;
2446
2447                 if (pipe_config->port_clock > 340000) {
2448                         pipe_config->hdmi_scrambling = true;
2449                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2450                 }
2451         }
2452
2453         intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state);
2454
2455         if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2456                 DRM_DEBUG_KMS("bad AVI infoframe\n");
2457                 return -EINVAL;
2458         }
2459
2460         if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2461                 DRM_DEBUG_KMS("bad SPD infoframe\n");
2462                 return -EINVAL;
2463         }
2464
2465         if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2466                 DRM_DEBUG_KMS("bad HDMI infoframe\n");
2467                 return -EINVAL;
2468         }
2469
2470         if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2471                 DRM_DEBUG_KMS("bad DRM infoframe\n");
2472                 return -EINVAL;
2473         }
2474
2475         intel_hdcp_transcoder_config(intel_hdmi->attached_connector,
2476                                      pipe_config->cpu_transcoder);
2477
2478         return 0;
2479 }
2480
2481 static void
2482 intel_hdmi_unset_edid(struct drm_connector *connector)
2483 {
2484         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2485
2486         intel_hdmi->has_hdmi_sink = false;
2487         intel_hdmi->has_audio = false;
2488
2489         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2490         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2491
2492         kfree(to_intel_connector(connector)->detect_edid);
2493         to_intel_connector(connector)->detect_edid = NULL;
2494 }
2495
2496 static void
2497 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2498 {
2499         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2500         struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2501         enum port port = hdmi_to_dig_port(hdmi)->base.port;
2502         struct i2c_adapter *adapter =
2503                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2504         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2505
2506         /*
2507          * Type 1 DVI adaptors are not required to implement any
2508          * registers, so we can't always detect their presence.
2509          * Ideally we should be able to check the state of the
2510          * CONFIG1 pin, but no such luck on our hardware.
2511          *
2512          * The only method left to us is to check the VBT to see
2513          * if the port is a dual mode capable DP port. But let's
2514          * only do that when we sucesfully read the EDID, to avoid
2515          * confusing log messages about DP dual mode adaptors when
2516          * there's nothing connected to the port.
2517          */
2518         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2519                 /* An overridden EDID imply that we want this port for testing.
2520                  * Make sure not to set limits for that port.
2521                  */
2522                 if (has_edid && !connector->override_edid &&
2523                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2524                         DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
2525                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2526                 } else {
2527                         type = DRM_DP_DUAL_MODE_NONE;
2528                 }
2529         }
2530
2531         if (type == DRM_DP_DUAL_MODE_NONE)
2532                 return;
2533
2534         hdmi->dp_dual_mode.type = type;
2535         hdmi->dp_dual_mode.max_tmds_clock =
2536                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
2537
2538         DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2539                       drm_dp_get_dual_mode_type_name(type),
2540                       hdmi->dp_dual_mode.max_tmds_clock);
2541 }
2542
2543 static bool
2544 intel_hdmi_set_edid(struct drm_connector *connector)
2545 {
2546         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2547         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2548         intel_wakeref_t wakeref;
2549         struct edid *edid;
2550         bool connected = false;
2551         struct i2c_adapter *i2c;
2552
2553         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2554
2555         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2556
2557         edid = drm_get_edid(connector, i2c);
2558
2559         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2560                 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2561                 intel_gmbus_force_bit(i2c, true);
2562                 edid = drm_get_edid(connector, i2c);
2563                 intel_gmbus_force_bit(i2c, false);
2564         }
2565
2566         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2567
2568         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2569
2570         to_intel_connector(connector)->detect_edid = edid;
2571         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2572                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2573                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2574
2575                 connected = true;
2576         }
2577
2578         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2579
2580         return connected;
2581 }
2582
2583 static enum drm_connector_status
2584 intel_hdmi_detect(struct drm_connector *connector, bool force)
2585 {
2586         enum drm_connector_status status = connector_status_disconnected;
2587         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2588         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2589         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2590         intel_wakeref_t wakeref;
2591
2592         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2593                       connector->base.id, connector->name);
2594
2595         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2596
2597         if (INTEL_GEN(dev_priv) >= 11 &&
2598             !intel_digital_port_connected(encoder))
2599                 goto out;
2600
2601         intel_hdmi_unset_edid(connector);
2602
2603         if (intel_hdmi_set_edid(connector))
2604                 status = connector_status_connected;
2605
2606 out:
2607         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2608
2609         if (status != connector_status_connected)
2610                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2611
2612         return status;
2613 }
2614
2615 static void
2616 intel_hdmi_force(struct drm_connector *connector)
2617 {
2618         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2619                       connector->base.id, connector->name);
2620
2621         intel_hdmi_unset_edid(connector);
2622
2623         if (connector->status != connector_status_connected)
2624                 return;
2625
2626         intel_hdmi_set_edid(connector);
2627 }
2628
2629 static int intel_hdmi_get_modes(struct drm_connector *connector)
2630 {
2631         struct edid *edid;
2632
2633         edid = to_intel_connector(connector)->detect_edid;
2634         if (edid == NULL)
2635                 return 0;
2636
2637         return intel_connector_update_modes(connector, edid);
2638 }
2639
2640 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
2641                                   const struct intel_crtc_state *pipe_config,
2642                                   const struct drm_connector_state *conn_state)
2643 {
2644         struct intel_digital_port *intel_dig_port =
2645                 enc_to_dig_port(&encoder->base);
2646
2647         intel_hdmi_prepare(encoder, pipe_config);
2648
2649         intel_dig_port->set_infoframes(encoder,
2650                                        pipe_config->has_infoframe,
2651                                        pipe_config, conn_state);
2652 }
2653
2654 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
2655                                 const struct intel_crtc_state *pipe_config,
2656                                 const struct drm_connector_state *conn_state)
2657 {
2658         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2659         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2660
2661         vlv_phy_pre_encoder_enable(encoder, pipe_config);
2662
2663         /* HDMI 1.0V-2dB */
2664         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2665                                  0x2b247878);
2666
2667         dport->set_infoframes(encoder,
2668                               pipe_config->has_infoframe,
2669                               pipe_config, conn_state);
2670
2671         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2672
2673         vlv_wait_port_ready(dev_priv, dport, 0x0);
2674 }
2675
2676 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2677                                     const struct intel_crtc_state *pipe_config,
2678                                     const struct drm_connector_state *conn_state)
2679 {
2680         intel_hdmi_prepare(encoder, pipe_config);
2681
2682         vlv_phy_pre_pll_enable(encoder, pipe_config);
2683 }
2684
2685 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2686                                     const struct intel_crtc_state *pipe_config,
2687                                     const struct drm_connector_state *conn_state)
2688 {
2689         intel_hdmi_prepare(encoder, pipe_config);
2690
2691         chv_phy_pre_pll_enable(encoder, pipe_config);
2692 }
2693
2694 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2695                                       const struct intel_crtc_state *old_crtc_state,
2696                                       const struct drm_connector_state *old_conn_state)
2697 {
2698         chv_phy_post_pll_disable(encoder, old_crtc_state);
2699 }
2700
2701 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2702                                   const struct intel_crtc_state *old_crtc_state,
2703                                   const struct drm_connector_state *old_conn_state)
2704 {
2705         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2706         vlv_phy_reset_lanes(encoder, old_crtc_state);
2707 }
2708
2709 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2710                                   const struct intel_crtc_state *old_crtc_state,
2711                                   const struct drm_connector_state *old_conn_state)
2712 {
2713         struct drm_device *dev = encoder->base.dev;
2714         struct drm_i915_private *dev_priv = to_i915(dev);
2715
2716         vlv_dpio_get(dev_priv);
2717
2718         /* Assert data lane reset */
2719         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2720
2721         vlv_dpio_put(dev_priv);
2722 }
2723
2724 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2725                                 const struct intel_crtc_state *pipe_config,
2726                                 const struct drm_connector_state *conn_state)
2727 {
2728         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2729         struct drm_device *dev = encoder->base.dev;
2730         struct drm_i915_private *dev_priv = to_i915(dev);
2731
2732         chv_phy_pre_encoder_enable(encoder, pipe_config);
2733
2734         /* FIXME: Program the support xxx V-dB */
2735         /* Use 800mV-0dB */
2736         chv_set_phy_signal_level(encoder, 128, 102, false);
2737
2738         dport->set_infoframes(encoder,
2739                               pipe_config->has_infoframe,
2740                               pipe_config, conn_state);
2741
2742         g4x_enable_hdmi(encoder, pipe_config, conn_state);
2743
2744         vlv_wait_port_ready(dev_priv, dport, 0x0);
2745
2746         /* Second common lane will stay alive on its own now */
2747         chv_phy_release_cl2_override(encoder);
2748 }
2749
2750 static struct i2c_adapter *
2751 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2752 {
2753         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2754         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2755
2756         return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2757 }
2758
2759 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2760 {
2761         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2762         struct kobject *i2c_kobj = &adapter->dev.kobj;
2763         struct kobject *connector_kobj = &connector->kdev->kobj;
2764         int ret;
2765
2766         ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2767         if (ret)
2768                 DRM_ERROR("Failed to create i2c symlink (%d)\n", ret);
2769 }
2770
2771 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2772 {
2773         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2774         struct kobject *i2c_kobj = &adapter->dev.kobj;
2775         struct kobject *connector_kobj = &connector->kdev->kobj;
2776
2777         sysfs_remove_link(connector_kobj, i2c_kobj->name);
2778 }
2779
2780 static int
2781 intel_hdmi_connector_register(struct drm_connector *connector)
2782 {
2783         int ret;
2784
2785         ret = intel_connector_register(connector);
2786         if (ret)
2787                 return ret;
2788
2789         i915_debugfs_connector_add(connector);
2790
2791         intel_hdmi_create_i2c_symlink(connector);
2792
2793         return ret;
2794 }
2795
2796 static void intel_hdmi_destroy(struct drm_connector *connector)
2797 {
2798         if (intel_attached_hdmi(connector)->cec_notifier)
2799                 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2800
2801         intel_connector_destroy(connector);
2802 }
2803
2804 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2805 {
2806         intel_hdmi_remove_i2c_symlink(connector);
2807
2808         intel_connector_unregister(connector);
2809 }
2810
2811 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2812         .detect = intel_hdmi_detect,
2813         .force = intel_hdmi_force,
2814         .fill_modes = drm_helper_probe_single_connector_modes,
2815         .atomic_get_property = intel_digital_connector_atomic_get_property,
2816         .atomic_set_property = intel_digital_connector_atomic_set_property,
2817         .late_register = intel_hdmi_connector_register,
2818         .early_unregister = intel_hdmi_connector_unregister,
2819         .destroy = intel_hdmi_destroy,
2820         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2821         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2822 };
2823
2824 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2825         .get_modes = intel_hdmi_get_modes,
2826         .mode_valid = intel_hdmi_mode_valid,
2827         .atomic_check = intel_digital_connector_atomic_check,
2828 };
2829
2830 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2831         .destroy = intel_encoder_destroy,
2832 };
2833
2834 static void
2835 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2836 {
2837         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2838         struct intel_digital_port *intel_dig_port =
2839                                 hdmi_to_dig_port(intel_hdmi);
2840
2841         intel_attach_force_audio_property(connector);
2842         intel_attach_broadcast_rgb_property(connector);
2843         intel_attach_aspect_ratio_property(connector);
2844
2845         /*
2846          * Attach Colorspace property for Non LSPCON based device
2847          * ToDo: This needs to be extended for LSPCON implementation
2848          * as well. Will be implemented separately.
2849          */
2850         if (!intel_dig_port->lspcon.active)
2851                 intel_attach_colorspace_property(connector);
2852
2853         drm_connector_attach_content_type_property(connector);
2854         connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2855
2856         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2857                 drm_object_attach_property(&connector->base,
2858                         connector->dev->mode_config.hdr_output_metadata_property, 0);
2859
2860         if (!HAS_GMCH(dev_priv))
2861                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2862 }
2863
2864 /*
2865  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2866  * @encoder: intel_encoder
2867  * @connector: drm_connector
2868  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2869  *  or reset the high tmds clock ratio for scrambling
2870  * @scrambling: bool to Indicate if the function needs to set or reset
2871  *  sink scrambling
2872  *
2873  * This function handles scrambling on HDMI 2.0 capable sinks.
2874  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2875  * it enables scrambling. This should be called before enabling the HDMI
2876  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2877  * detect a scrambled clock within 100 ms.
2878  *
2879  * Returns:
2880  * True on success, false on failure.
2881  */
2882 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2883                                        struct drm_connector *connector,
2884                                        bool high_tmds_clock_ratio,
2885                                        bool scrambling)
2886 {
2887         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2888         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2889         struct drm_scrambling *sink_scrambling =
2890                 &connector->display_info.hdmi.scdc.scrambling;
2891         struct i2c_adapter *adapter =
2892                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2893
2894         if (!sink_scrambling->supported)
2895                 return true;
2896
2897         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2898                       connector->base.id, connector->name,
2899                       yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2900
2901         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2902         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2903                                                   high_tmds_clock_ratio) &&
2904                 drm_scdc_set_scrambling(adapter, scrambling);
2905 }
2906
2907 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2908 {
2909         u8 ddc_pin;
2910
2911         switch (port) {
2912         case PORT_B:
2913                 ddc_pin = GMBUS_PIN_DPB;
2914                 break;
2915         case PORT_C:
2916                 ddc_pin = GMBUS_PIN_DPC;
2917                 break;
2918         case PORT_D:
2919                 ddc_pin = GMBUS_PIN_DPD_CHV;
2920                 break;
2921         default:
2922                 MISSING_CASE(port);
2923                 ddc_pin = GMBUS_PIN_DPB;
2924                 break;
2925         }
2926         return ddc_pin;
2927 }
2928
2929 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2930 {
2931         u8 ddc_pin;
2932
2933         switch (port) {
2934         case PORT_B:
2935                 ddc_pin = GMBUS_PIN_1_BXT;
2936                 break;
2937         case PORT_C:
2938                 ddc_pin = GMBUS_PIN_2_BXT;
2939                 break;
2940         default:
2941                 MISSING_CASE(port);
2942                 ddc_pin = GMBUS_PIN_1_BXT;
2943                 break;
2944         }
2945         return ddc_pin;
2946 }
2947
2948 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2949                               enum port port)
2950 {
2951         u8 ddc_pin;
2952
2953         switch (port) {
2954         case PORT_B:
2955                 ddc_pin = GMBUS_PIN_1_BXT;
2956                 break;
2957         case PORT_C:
2958                 ddc_pin = GMBUS_PIN_2_BXT;
2959                 break;
2960         case PORT_D:
2961                 ddc_pin = GMBUS_PIN_4_CNP;
2962                 break;
2963         case PORT_F:
2964                 ddc_pin = GMBUS_PIN_3_BXT;
2965                 break;
2966         default:
2967                 MISSING_CASE(port);
2968                 ddc_pin = GMBUS_PIN_1_BXT;
2969                 break;
2970         }
2971         return ddc_pin;
2972 }
2973
2974 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2975 {
2976         enum phy phy = intel_port_to_phy(dev_priv, port);
2977
2978         if (intel_phy_is_combo(dev_priv, phy))
2979                 return GMBUS_PIN_1_BXT + port;
2980         else if (intel_phy_is_tc(dev_priv, phy))
2981                 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2982
2983         WARN(1, "Unknown port:%c\n", port_name(port));
2984         return GMBUS_PIN_2_BXT;
2985 }
2986
2987 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2988 {
2989         enum phy phy = intel_port_to_phy(dev_priv, port);
2990         u8 ddc_pin;
2991
2992         switch (phy) {
2993         case PHY_A:
2994                 ddc_pin = GMBUS_PIN_1_BXT;
2995                 break;
2996         case PHY_B:
2997                 ddc_pin = GMBUS_PIN_2_BXT;
2998                 break;
2999         case PHY_C:
3000                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
3001                 break;
3002         default:
3003                 MISSING_CASE(phy);
3004                 ddc_pin = GMBUS_PIN_1_BXT;
3005                 break;
3006         }
3007         return ddc_pin;
3008 }
3009
3010 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
3011                               enum port port)
3012 {
3013         u8 ddc_pin;
3014
3015         switch (port) {
3016         case PORT_B:
3017                 ddc_pin = GMBUS_PIN_DPB;
3018                 break;
3019         case PORT_C:
3020                 ddc_pin = GMBUS_PIN_DPC;
3021                 break;
3022         case PORT_D:
3023                 ddc_pin = GMBUS_PIN_DPD;
3024                 break;
3025         default:
3026                 MISSING_CASE(port);
3027                 ddc_pin = GMBUS_PIN_DPB;
3028                 break;
3029         }
3030         return ddc_pin;
3031 }
3032
3033 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
3034                              enum port port)
3035 {
3036         const struct ddi_vbt_port_info *info =
3037                 &dev_priv->vbt.ddi_port_info[port];
3038         u8 ddc_pin;
3039
3040         if (info->alternate_ddc_pin) {
3041                 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
3042                               info->alternate_ddc_pin, port_name(port));
3043                 return info->alternate_ddc_pin;
3044         }
3045
3046         if (HAS_PCH_MCC(dev_priv))
3047                 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
3048         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3049                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
3050         else if (HAS_PCH_CNP(dev_priv))
3051                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
3052         else if (IS_GEN9_LP(dev_priv))
3053                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
3054         else if (IS_CHERRYVIEW(dev_priv))
3055                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
3056         else
3057                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
3058
3059         DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
3060                       ddc_pin, port_name(port));
3061
3062         return ddc_pin;
3063 }
3064
3065 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
3066 {
3067         struct drm_i915_private *dev_priv =
3068                 to_i915(intel_dig_port->base.base.dev);
3069
3070         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3071                 intel_dig_port->write_infoframe = vlv_write_infoframe;
3072                 intel_dig_port->read_infoframe = vlv_read_infoframe;
3073                 intel_dig_port->set_infoframes = vlv_set_infoframes;
3074                 intel_dig_port->infoframes_enabled = vlv_infoframes_enabled;
3075         } else if (IS_G4X(dev_priv)) {
3076                 intel_dig_port->write_infoframe = g4x_write_infoframe;
3077                 intel_dig_port->read_infoframe = g4x_read_infoframe;
3078                 intel_dig_port->set_infoframes = g4x_set_infoframes;
3079                 intel_dig_port->infoframes_enabled = g4x_infoframes_enabled;
3080         } else if (HAS_DDI(dev_priv)) {
3081                 if (intel_dig_port->lspcon.active) {
3082                         intel_dig_port->write_infoframe = lspcon_write_infoframe;
3083                         intel_dig_port->read_infoframe = lspcon_read_infoframe;
3084                         intel_dig_port->set_infoframes = lspcon_set_infoframes;
3085                         intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled;
3086                 } else {
3087                         intel_dig_port->write_infoframe = hsw_write_infoframe;
3088                         intel_dig_port->read_infoframe = hsw_read_infoframe;
3089                         intel_dig_port->set_infoframes = hsw_set_infoframes;
3090                         intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;
3091                 }
3092         } else if (HAS_PCH_IBX(dev_priv)) {
3093                 intel_dig_port->write_infoframe = ibx_write_infoframe;
3094                 intel_dig_port->read_infoframe = ibx_read_infoframe;
3095                 intel_dig_port->set_infoframes = ibx_set_infoframes;
3096                 intel_dig_port->infoframes_enabled = ibx_infoframes_enabled;
3097         } else {
3098                 intel_dig_port->write_infoframe = cpt_write_infoframe;
3099                 intel_dig_port->read_infoframe = cpt_read_infoframe;
3100                 intel_dig_port->set_infoframes = cpt_set_infoframes;
3101                 intel_dig_port->infoframes_enabled = cpt_infoframes_enabled;
3102         }
3103 }
3104
3105 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
3106                                struct intel_connector *intel_connector)
3107 {
3108         struct drm_connector *connector = &intel_connector->base;
3109         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3110         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3111         struct drm_device *dev = intel_encoder->base.dev;
3112         struct drm_i915_private *dev_priv = to_i915(dev);
3113         enum port port = intel_encoder->port;
3114
3115         DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n",
3116                       intel_encoder->base.base.id, intel_encoder->base.name);
3117
3118         if (WARN(intel_dig_port->max_lanes < 4,
3119                  "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
3120                  intel_dig_port->max_lanes, intel_encoder->base.base.id,
3121                  intel_encoder->base.name))
3122                 return;
3123
3124         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
3125                            DRM_MODE_CONNECTOR_HDMIA);
3126         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3127
3128         connector->interlace_allowed = 1;
3129         connector->doublescan_allowed = 0;
3130         connector->stereo_allowed = 1;
3131
3132         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3133                 connector->ycbcr_420_allowed = true;
3134
3135         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
3136
3137         if (WARN_ON(port == PORT_A))
3138                 return;
3139         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
3140
3141         if (HAS_DDI(dev_priv))
3142                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3143         else
3144                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3145
3146         intel_hdmi_add_properties(intel_hdmi, connector);
3147
3148         intel_connector_attach_encoder(intel_connector, intel_encoder);
3149         intel_hdmi->attached_connector = intel_connector;
3150
3151         if (is_hdcp_supported(dev_priv, port)) {
3152                 int ret = intel_hdcp_init(intel_connector,
3153                                           &intel_hdmi_hdcp_shim);
3154                 if (ret)
3155                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
3156         }
3157
3158         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3159          * 0xd.  Failure to do so will result in spurious interrupts being
3160          * generated on the port when a cable is not attached.
3161          */
3162         if (IS_G45(dev_priv)) {
3163                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3164                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3165         }
3166
3167         intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
3168                                                          port_identifier(port));
3169         if (!intel_hdmi->cec_notifier)
3170                 DRM_DEBUG_KMS("CEC notifier get failed\n");
3171 }
3172
3173 static enum intel_hotplug_state
3174 intel_hdmi_hotplug(struct intel_encoder *encoder,
3175                    struct intel_connector *connector, bool irq_received)
3176 {
3177         enum intel_hotplug_state state;
3178
3179         state = intel_encoder_hotplug(encoder, connector, irq_received);
3180
3181         /*
3182          * On many platforms the HDMI live state signal is known to be
3183          * unreliable, so we can't use it to detect if a sink is connected or
3184          * not. Instead we detect if it's connected based on whether we can
3185          * read the EDID or not. That in turn has a problem during disconnect,
3186          * since the HPD interrupt may be raised before the DDC lines get
3187          * disconnected (due to how the required length of DDC vs. HPD
3188          * connector pins are specified) and so we'll still be able to get a
3189          * valid EDID. To solve this schedule another detection cycle if this
3190          * time around we didn't detect any change in the sink's connection
3191          * status.
3192          */
3193         if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
3194                 state = INTEL_HOTPLUG_RETRY;
3195
3196         return state;
3197 }
3198
3199 void intel_hdmi_init(struct drm_i915_private *dev_priv,
3200                      i915_reg_t hdmi_reg, enum port port)
3201 {
3202         struct intel_digital_port *intel_dig_port;
3203         struct intel_encoder *intel_encoder;
3204         struct intel_connector *intel_connector;
3205
3206         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3207         if (!intel_dig_port)
3208                 return;
3209
3210         intel_connector = intel_connector_alloc();
3211         if (!intel_connector) {
3212                 kfree(intel_dig_port);
3213                 return;
3214         }
3215
3216         intel_encoder = &intel_dig_port->base;
3217
3218         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3219                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
3220                          "HDMI %c", port_name(port));
3221
3222         intel_encoder->hotplug = intel_hdmi_hotplug;
3223         intel_encoder->compute_config = intel_hdmi_compute_config;
3224         if (HAS_PCH_SPLIT(dev_priv)) {
3225                 intel_encoder->disable = pch_disable_hdmi;
3226                 intel_encoder->post_disable = pch_post_disable_hdmi;
3227         } else {
3228                 intel_encoder->disable = g4x_disable_hdmi;
3229         }
3230         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
3231         intel_encoder->get_config = intel_hdmi_get_config;
3232         if (IS_CHERRYVIEW(dev_priv)) {
3233                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
3234                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
3235                 intel_encoder->enable = vlv_enable_hdmi;
3236                 intel_encoder->post_disable = chv_hdmi_post_disable;
3237                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
3238         } else if (IS_VALLEYVIEW(dev_priv)) {
3239                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
3240                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
3241                 intel_encoder->enable = vlv_enable_hdmi;
3242                 intel_encoder->post_disable = vlv_hdmi_post_disable;
3243         } else {
3244                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
3245                 if (HAS_PCH_CPT(dev_priv))
3246                         intel_encoder->enable = cpt_enable_hdmi;
3247                 else if (HAS_PCH_IBX(dev_priv))
3248                         intel_encoder->enable = ibx_enable_hdmi;
3249                 else
3250                         intel_encoder->enable = g4x_enable_hdmi;
3251         }
3252
3253         intel_encoder->type = INTEL_OUTPUT_HDMI;
3254         intel_encoder->power_domain = intel_port_to_power_domain(port);
3255         intel_encoder->port = port;
3256         if (IS_CHERRYVIEW(dev_priv)) {
3257                 if (port == PORT_D)
3258                         intel_encoder->crtc_mask = 1 << 2;
3259                 else
3260                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
3261         } else {
3262                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3263         }
3264         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
3265         /*
3266          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3267          * to work on real hardware. And since g4x can send infoframes to
3268          * only one port anyway, nothing is lost by allowing it.
3269          */
3270         if (IS_G4X(dev_priv))
3271                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
3272
3273         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
3274         intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3275         intel_dig_port->max_lanes = 4;
3276
3277         intel_infoframe_init(intel_dig_port);
3278
3279         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
3280         intel_hdmi_init_connector(intel_dig_port, intel_connector);
3281 }