2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/delay.h>
30 #include <linux/hdmi.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_hdcp.h>
38 #include <drm/drm_scdc_helper.h>
39 #include <drm/i915_drm.h>
40 #include <drm/intel_lpe_audio.h>
42 #include "i915_debugfs.h"
44 #include "intel_atomic.h"
45 #include "intel_audio.h"
46 #include "intel_connector.h"
47 #include "intel_ddi.h"
48 #include "intel_display_types.h"
50 #include "intel_dpio_phy.h"
51 #include "intel_fifo_underrun.h"
52 #include "intel_gmbus.h"
53 #include "intel_hdcp.h"
54 #include "intel_hdmi.h"
55 #include "intel_hotplug.h"
56 #include "intel_lspcon.h"
57 #include "intel_panel.h"
58 #include "intel_sdvo.h"
59 #include "intel_sideband.h"
61 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
63 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
67 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
69 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
70 struct drm_i915_private *dev_priv = to_i915(dev);
73 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
75 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
76 "HDMI port enabled, expecting disabled\n");
80 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
81 enum transcoder cpu_transcoder)
83 WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
84 TRANS_DDI_FUNC_ENABLE,
85 "HDMI transcoder function enabled, expecting disabled\n");
88 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
90 struct intel_digital_port *intel_dig_port =
91 container_of(encoder, struct intel_digital_port, base.base);
92 return &intel_dig_port->hdmi;
95 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
97 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
100 static u32 g4x_infoframe_index(unsigned int type)
103 case HDMI_PACKET_TYPE_GAMUT_METADATA:
104 return VIDEO_DIP_SELECT_GAMUT;
105 case HDMI_INFOFRAME_TYPE_AVI:
106 return VIDEO_DIP_SELECT_AVI;
107 case HDMI_INFOFRAME_TYPE_SPD:
108 return VIDEO_DIP_SELECT_SPD;
109 case HDMI_INFOFRAME_TYPE_VENDOR:
110 return VIDEO_DIP_SELECT_VENDOR;
117 static u32 g4x_infoframe_enable(unsigned int type)
120 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
121 return VIDEO_DIP_ENABLE_GCP;
122 case HDMI_PACKET_TYPE_GAMUT_METADATA:
123 return VIDEO_DIP_ENABLE_GAMUT;
126 case HDMI_INFOFRAME_TYPE_AVI:
127 return VIDEO_DIP_ENABLE_AVI;
128 case HDMI_INFOFRAME_TYPE_SPD:
129 return VIDEO_DIP_ENABLE_SPD;
130 case HDMI_INFOFRAME_TYPE_VENDOR:
131 return VIDEO_DIP_ENABLE_VENDOR;
132 case HDMI_INFOFRAME_TYPE_DRM:
140 static u32 hsw_infoframe_enable(unsigned int type)
143 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
144 return VIDEO_DIP_ENABLE_GCP_HSW;
145 case HDMI_PACKET_TYPE_GAMUT_METADATA:
146 return VIDEO_DIP_ENABLE_GMP_HSW;
148 return VIDEO_DIP_ENABLE_VSC_HSW;
150 return VDIP_ENABLE_PPS;
151 case HDMI_INFOFRAME_TYPE_AVI:
152 return VIDEO_DIP_ENABLE_AVI_HSW;
153 case HDMI_INFOFRAME_TYPE_SPD:
154 return VIDEO_DIP_ENABLE_SPD_HSW;
155 case HDMI_INFOFRAME_TYPE_VENDOR:
156 return VIDEO_DIP_ENABLE_VS_HSW;
157 case HDMI_INFOFRAME_TYPE_DRM:
158 return VIDEO_DIP_ENABLE_DRM_GLK;
166 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
167 enum transcoder cpu_transcoder,
172 case HDMI_PACKET_TYPE_GAMUT_METADATA:
173 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
175 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
177 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
178 case HDMI_INFOFRAME_TYPE_AVI:
179 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
180 case HDMI_INFOFRAME_TYPE_SPD:
181 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
182 case HDMI_INFOFRAME_TYPE_VENDOR:
183 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
184 case HDMI_INFOFRAME_TYPE_DRM:
185 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
188 return INVALID_MMIO_REG;
192 static int hsw_dip_data_size(unsigned int type)
196 return VIDEO_DIP_VSC_DATA_SIZE;
198 return VIDEO_DIP_PPS_DATA_SIZE;
200 return VIDEO_DIP_DATA_SIZE;
204 static void g4x_write_infoframe(struct intel_encoder *encoder,
205 const struct intel_crtc_state *crtc_state,
207 const void *frame, ssize_t len)
209 const u32 *data = frame;
210 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
211 u32 val = I915_READ(VIDEO_DIP_CTL);
214 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
216 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
217 val |= g4x_infoframe_index(type);
219 val &= ~g4x_infoframe_enable(type);
221 I915_WRITE(VIDEO_DIP_CTL, val);
223 for (i = 0; i < len; i += 4) {
224 I915_WRITE(VIDEO_DIP_DATA, *data);
227 /* Write every possible data byte to force correct ECC calculation. */
228 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
229 I915_WRITE(VIDEO_DIP_DATA, 0);
231 val |= g4x_infoframe_enable(type);
232 val &= ~VIDEO_DIP_FREQ_MASK;
233 val |= VIDEO_DIP_FREQ_VSYNC;
235 I915_WRITE(VIDEO_DIP_CTL, val);
236 POSTING_READ(VIDEO_DIP_CTL);
239 static void g4x_read_infoframe(struct intel_encoder *encoder,
240 const struct intel_crtc_state *crtc_state,
242 void *frame, ssize_t len)
244 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
245 u32 val, *data = frame;
248 val = I915_READ(VIDEO_DIP_CTL);
250 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
251 val |= g4x_infoframe_index(type);
253 I915_WRITE(VIDEO_DIP_CTL, val);
255 for (i = 0; i < len; i += 4)
256 *data++ = I915_READ(VIDEO_DIP_DATA);
259 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
260 const struct intel_crtc_state *pipe_config)
262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
263 u32 val = I915_READ(VIDEO_DIP_CTL);
265 if ((val & VIDEO_DIP_ENABLE) == 0)
268 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
271 return val & (VIDEO_DIP_ENABLE_AVI |
272 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
275 static void ibx_write_infoframe(struct intel_encoder *encoder,
276 const struct intel_crtc_state *crtc_state,
278 const void *frame, ssize_t len)
280 const u32 *data = frame;
281 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
283 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
284 u32 val = I915_READ(reg);
287 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
289 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
290 val |= g4x_infoframe_index(type);
292 val &= ~g4x_infoframe_enable(type);
294 I915_WRITE(reg, val);
296 for (i = 0; i < len; i += 4) {
297 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
300 /* Write every possible data byte to force correct ECC calculation. */
301 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
302 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
304 val |= g4x_infoframe_enable(type);
305 val &= ~VIDEO_DIP_FREQ_MASK;
306 val |= VIDEO_DIP_FREQ_VSYNC;
308 I915_WRITE(reg, val);
312 static void ibx_read_infoframe(struct intel_encoder *encoder,
313 const struct intel_crtc_state *crtc_state,
315 void *frame, ssize_t len)
317 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
318 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
319 u32 val, *data = frame;
322 val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
324 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
325 val |= g4x_infoframe_index(type);
327 I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
329 for (i = 0; i < len; i += 4)
330 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
333 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
334 const struct intel_crtc_state *pipe_config)
336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
337 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
338 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
339 u32 val = I915_READ(reg);
341 if ((val & VIDEO_DIP_ENABLE) == 0)
344 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
347 return val & (VIDEO_DIP_ENABLE_AVI |
348 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
349 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
352 static void cpt_write_infoframe(struct intel_encoder *encoder,
353 const struct intel_crtc_state *crtc_state,
355 const void *frame, ssize_t len)
357 const u32 *data = frame;
358 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
360 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
361 u32 val = I915_READ(reg);
364 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
366 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
367 val |= g4x_infoframe_index(type);
369 /* The DIP control register spec says that we need to update the AVI
370 * infoframe without clearing its enable bit */
371 if (type != HDMI_INFOFRAME_TYPE_AVI)
372 val &= ~g4x_infoframe_enable(type);
374 I915_WRITE(reg, val);
376 for (i = 0; i < len; i += 4) {
377 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
380 /* Write every possible data byte to force correct ECC calculation. */
381 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
382 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
384 val |= g4x_infoframe_enable(type);
385 val &= ~VIDEO_DIP_FREQ_MASK;
386 val |= VIDEO_DIP_FREQ_VSYNC;
388 I915_WRITE(reg, val);
392 static void cpt_read_infoframe(struct intel_encoder *encoder,
393 const struct intel_crtc_state *crtc_state,
395 void *frame, ssize_t len)
397 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
398 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
399 u32 val, *data = frame;
402 val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
404 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
405 val |= g4x_infoframe_index(type);
407 I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
409 for (i = 0; i < len; i += 4)
410 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
413 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
414 const struct intel_crtc_state *pipe_config)
416 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
417 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
418 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
420 if ((val & VIDEO_DIP_ENABLE) == 0)
423 return val & (VIDEO_DIP_ENABLE_AVI |
424 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
425 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
428 static void vlv_write_infoframe(struct intel_encoder *encoder,
429 const struct intel_crtc_state *crtc_state,
431 const void *frame, ssize_t len)
433 const u32 *data = frame;
434 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
436 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
437 u32 val = I915_READ(reg);
440 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
442 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
443 val |= g4x_infoframe_index(type);
445 val &= ~g4x_infoframe_enable(type);
447 I915_WRITE(reg, val);
449 for (i = 0; i < len; i += 4) {
450 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
453 /* Write every possible data byte to force correct ECC calculation. */
454 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
455 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
457 val |= g4x_infoframe_enable(type);
458 val &= ~VIDEO_DIP_FREQ_MASK;
459 val |= VIDEO_DIP_FREQ_VSYNC;
461 I915_WRITE(reg, val);
465 static void vlv_read_infoframe(struct intel_encoder *encoder,
466 const struct intel_crtc_state *crtc_state,
468 void *frame, ssize_t len)
470 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
471 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
472 u32 val, *data = frame;
475 val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe));
477 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
478 val |= g4x_infoframe_index(type);
480 I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
482 for (i = 0; i < len; i += 4)
483 *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe));
486 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
487 const struct intel_crtc_state *pipe_config)
489 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
490 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
491 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
493 if ((val & VIDEO_DIP_ENABLE) == 0)
496 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
499 return val & (VIDEO_DIP_ENABLE_AVI |
500 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
501 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
504 static void hsw_write_infoframe(struct intel_encoder *encoder,
505 const struct intel_crtc_state *crtc_state,
507 const void *frame, ssize_t len)
509 const u32 *data = frame;
510 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
511 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
512 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
515 u32 val = I915_READ(ctl_reg);
517 data_size = hsw_dip_data_size(type);
519 val &= ~hsw_infoframe_enable(type);
520 I915_WRITE(ctl_reg, val);
522 for (i = 0; i < len; i += 4) {
523 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
524 type, i >> 2), *data);
527 /* Write every possible data byte to force correct ECC calculation. */
528 for (; i < data_size; i += 4)
529 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
532 val |= hsw_infoframe_enable(type);
533 I915_WRITE(ctl_reg, val);
534 POSTING_READ(ctl_reg);
537 static void hsw_read_infoframe(struct intel_encoder *encoder,
538 const struct intel_crtc_state *crtc_state,
540 void *frame, ssize_t len)
542 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
543 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
544 u32 val, *data = frame;
547 val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder));
549 for (i = 0; i < len; i += 4)
550 *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder,
554 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
555 const struct intel_crtc_state *pipe_config)
557 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
558 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
561 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
562 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
563 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
565 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
566 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
571 static const u8 infoframe_type_to_idx[] = {
572 HDMI_PACKET_TYPE_GENERAL_CONTROL,
573 HDMI_PACKET_TYPE_GAMUT_METADATA,
575 HDMI_INFOFRAME_TYPE_AVI,
576 HDMI_INFOFRAME_TYPE_SPD,
577 HDMI_INFOFRAME_TYPE_VENDOR,
578 HDMI_INFOFRAME_TYPE_DRM,
581 u32 intel_hdmi_infoframe_enable(unsigned int type)
585 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
586 if (infoframe_type_to_idx[i] == type)
593 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
594 const struct intel_crtc_state *crtc_state)
596 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
597 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
601 val = dig_port->infoframes_enabled(encoder, crtc_state);
603 /* map from hardware bits to dip idx */
604 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
605 unsigned int type = infoframe_type_to_idx[i];
607 if (HAS_DDI(dev_priv)) {
608 if (val & hsw_infoframe_enable(type))
611 if (val & g4x_infoframe_enable(type))
620 * The data we write to the DIP data buffer registers is 1 byte bigger than the
621 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
622 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
623 * used for both technologies.
625 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
626 * DW1: DB3 | DB2 | DB1 | DB0
627 * DW2: DB7 | DB6 | DB5 | DB4
630 * (HB is Header Byte, DB is Data Byte)
632 * The hdmi pack() functions don't know about that hardware specific hole so we
633 * trick them by giving an offset into the buffer and moving back the header
636 static void intel_write_infoframe(struct intel_encoder *encoder,
637 const struct intel_crtc_state *crtc_state,
638 enum hdmi_infoframe_type type,
639 const union hdmi_infoframe *frame)
641 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
642 u8 buffer[VIDEO_DIP_DATA_SIZE];
645 if ((crtc_state->infoframes.enable &
646 intel_hdmi_infoframe_enable(type)) == 0)
649 if (WARN_ON(frame->any.type != type))
652 /* see comment above for the reason for this offset */
653 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
654 if (WARN_ON(len < 0))
657 /* Insert the 'hole' (see big comment above) at position 3 */
658 memmove(&buffer[0], &buffer[1], 3);
662 intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
665 void intel_read_infoframe(struct intel_encoder *encoder,
666 const struct intel_crtc_state *crtc_state,
667 enum hdmi_infoframe_type type,
668 union hdmi_infoframe *frame)
670 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
671 u8 buffer[VIDEO_DIP_DATA_SIZE];
674 if ((crtc_state->infoframes.enable &
675 intel_hdmi_infoframe_enable(type)) == 0)
678 intel_dig_port->read_infoframe(encoder, crtc_state,
679 type, buffer, sizeof(buffer));
681 /* Fill the 'hole' (see big comment above) at position 3 */
682 memmove(&buffer[1], &buffer[0], 3);
684 /* see comment above for the reason for this offset */
685 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
687 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type);
691 if (frame->any.type != type)
692 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
693 frame->any.type, type);
697 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
698 struct intel_crtc_state *crtc_state,
699 struct drm_connector_state *conn_state)
701 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
702 const struct drm_display_mode *adjusted_mode =
703 &crtc_state->base.adjusted_mode;
704 struct drm_connector *connector = conn_state->connector;
707 if (!crtc_state->has_infoframe)
710 crtc_state->infoframes.enable |=
711 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
713 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
718 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
719 frame->colorspace = HDMI_COLORSPACE_YUV420;
720 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
721 frame->colorspace = HDMI_COLORSPACE_YUV444;
723 frame->colorspace = HDMI_COLORSPACE_RGB;
725 drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
727 drm_hdmi_avi_infoframe_quant_range(frame, connector,
729 crtc_state->limited_color_range ?
730 HDMI_QUANTIZATION_RANGE_LIMITED :
731 HDMI_QUANTIZATION_RANGE_FULL);
733 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
735 /* TODO: handle pixel repetition for YCBCR420 outputs */
737 ret = hdmi_avi_infoframe_check(frame);
745 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
746 struct intel_crtc_state *crtc_state,
747 struct drm_connector_state *conn_state)
749 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
752 if (!crtc_state->has_infoframe)
755 crtc_state->infoframes.enable |=
756 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
758 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
762 frame->sdi = HDMI_SPD_SDI_PC;
764 ret = hdmi_spd_infoframe_check(frame);
772 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
773 struct intel_crtc_state *crtc_state,
774 struct drm_connector_state *conn_state)
776 struct hdmi_vendor_infoframe *frame =
777 &crtc_state->infoframes.hdmi.vendor.hdmi;
778 const struct drm_display_info *info =
779 &conn_state->connector->display_info;
782 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
785 crtc_state->infoframes.enable |=
786 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
788 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
789 conn_state->connector,
790 &crtc_state->base.adjusted_mode);
794 ret = hdmi_vendor_infoframe_check(frame);
802 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
803 struct intel_crtc_state *crtc_state,
804 struct drm_connector_state *conn_state)
806 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
807 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
810 if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
813 if (!crtc_state->has_infoframe)
816 if (!conn_state->hdr_output_metadata)
819 crtc_state->infoframes.enable |=
820 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
822 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
824 DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
828 ret = hdmi_drm_infoframe_check(frame);
835 static void g4x_set_infoframes(struct intel_encoder *encoder,
837 const struct intel_crtc_state *crtc_state,
838 const struct drm_connector_state *conn_state)
840 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
841 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
842 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
843 i915_reg_t reg = VIDEO_DIP_CTL;
844 u32 val = I915_READ(reg);
845 u32 port = VIDEO_DIP_PORT(encoder->port);
847 assert_hdmi_port_disabled(intel_hdmi);
849 /* If the registers were not initialized yet, they might be zeroes,
850 * which means we're selecting the AVI DIP and we're setting its
851 * frequency to once. This seems to really confuse the HW and make
852 * things stop working (the register spec says the AVI always needs to
853 * be sent every VSync). So here we avoid writing to the register more
854 * than we need and also explicitly select the AVI DIP and explicitly
855 * set its frequency to every VSync. Avoiding to write it twice seems to
856 * be enough to solve the problem, but being defensive shouldn't hurt us
858 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
861 if (!(val & VIDEO_DIP_ENABLE))
863 if (port != (val & VIDEO_DIP_PORT_MASK)) {
864 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
865 (val & VIDEO_DIP_PORT_MASK) >> 29);
868 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
869 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
870 I915_WRITE(reg, val);
875 if (port != (val & VIDEO_DIP_PORT_MASK)) {
876 if (val & VIDEO_DIP_ENABLE) {
877 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
878 (val & VIDEO_DIP_PORT_MASK) >> 29);
881 val &= ~VIDEO_DIP_PORT_MASK;
885 val |= VIDEO_DIP_ENABLE;
886 val &= ~(VIDEO_DIP_ENABLE_AVI |
887 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
889 I915_WRITE(reg, val);
892 intel_write_infoframe(encoder, crtc_state,
893 HDMI_INFOFRAME_TYPE_AVI,
894 &crtc_state->infoframes.avi);
895 intel_write_infoframe(encoder, crtc_state,
896 HDMI_INFOFRAME_TYPE_SPD,
897 &crtc_state->infoframes.spd);
898 intel_write_infoframe(encoder, crtc_state,
899 HDMI_INFOFRAME_TYPE_VENDOR,
900 &crtc_state->infoframes.hdmi);
904 * Determine if default_phase=1 can be indicated in the GCP infoframe.
906 * From HDMI specification 1.4a:
907 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
908 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
909 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
910 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
913 static bool gcp_default_phase_possible(int pipe_bpp,
914 const struct drm_display_mode *mode)
916 unsigned int pixels_per_group;
920 /* 4 pixels in 5 clocks */
921 pixels_per_group = 4;
924 /* 2 pixels in 3 clocks */
925 pixels_per_group = 2;
928 /* 1 pixel in 2 clocks */
929 pixels_per_group = 1;
932 /* phase information not relevant for 8bpc */
936 return mode->crtc_hdisplay % pixels_per_group == 0 &&
937 mode->crtc_htotal % pixels_per_group == 0 &&
938 mode->crtc_hblank_start % pixels_per_group == 0 &&
939 mode->crtc_hblank_end % pixels_per_group == 0 &&
940 mode->crtc_hsync_start % pixels_per_group == 0 &&
941 mode->crtc_hsync_end % pixels_per_group == 0 &&
942 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
943 mode->crtc_htotal/2 % pixels_per_group == 0);
946 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
947 const struct intel_crtc_state *crtc_state,
948 const struct drm_connector_state *conn_state)
950 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
951 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
954 if ((crtc_state->infoframes.enable &
955 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
958 if (HAS_DDI(dev_priv))
959 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
960 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
961 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
962 else if (HAS_PCH_SPLIT(dev_priv))
963 reg = TVIDEO_DIP_GCP(crtc->pipe);
967 I915_WRITE(reg, crtc_state->infoframes.gcp);
972 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
973 struct intel_crtc_state *crtc_state)
975 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
976 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
979 if ((crtc_state->infoframes.enable &
980 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
983 if (HAS_DDI(dev_priv))
984 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
985 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
986 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
987 else if (HAS_PCH_SPLIT(dev_priv))
988 reg = TVIDEO_DIP_GCP(crtc->pipe);
992 crtc_state->infoframes.gcp = I915_READ(reg);
995 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
996 struct intel_crtc_state *crtc_state,
997 struct drm_connector_state *conn_state)
999 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1001 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1004 crtc_state->infoframes.enable |=
1005 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1007 /* Indicate color indication for deep color mode */
1008 if (crtc_state->pipe_bpp > 24)
1009 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1011 /* Enable default_phase whenever the display mode is suitably aligned */
1012 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1013 &crtc_state->base.adjusted_mode))
1014 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1017 static void ibx_set_infoframes(struct intel_encoder *encoder,
1019 const struct intel_crtc_state *crtc_state,
1020 const struct drm_connector_state *conn_state)
1022 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1024 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1025 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1026 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1027 u32 val = I915_READ(reg);
1028 u32 port = VIDEO_DIP_PORT(encoder->port);
1030 assert_hdmi_port_disabled(intel_hdmi);
1032 /* See the big comment in g4x_set_infoframes() */
1033 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1036 if (!(val & VIDEO_DIP_ENABLE))
1038 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1039 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1040 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1041 I915_WRITE(reg, val);
1046 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1047 WARN(val & VIDEO_DIP_ENABLE,
1048 "DIP already enabled on port %c\n",
1049 (val & VIDEO_DIP_PORT_MASK) >> 29);
1050 val &= ~VIDEO_DIP_PORT_MASK;
1054 val |= VIDEO_DIP_ENABLE;
1055 val &= ~(VIDEO_DIP_ENABLE_AVI |
1056 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1057 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1059 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1060 val |= VIDEO_DIP_ENABLE_GCP;
1062 I915_WRITE(reg, val);
1065 intel_write_infoframe(encoder, crtc_state,
1066 HDMI_INFOFRAME_TYPE_AVI,
1067 &crtc_state->infoframes.avi);
1068 intel_write_infoframe(encoder, crtc_state,
1069 HDMI_INFOFRAME_TYPE_SPD,
1070 &crtc_state->infoframes.spd);
1071 intel_write_infoframe(encoder, crtc_state,
1072 HDMI_INFOFRAME_TYPE_VENDOR,
1073 &crtc_state->infoframes.hdmi);
1076 static void cpt_set_infoframes(struct intel_encoder *encoder,
1078 const struct intel_crtc_state *crtc_state,
1079 const struct drm_connector_state *conn_state)
1081 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1083 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1084 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1085 u32 val = I915_READ(reg);
1087 assert_hdmi_port_disabled(intel_hdmi);
1089 /* See the big comment in g4x_set_infoframes() */
1090 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1093 if (!(val & VIDEO_DIP_ENABLE))
1095 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1096 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1097 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1098 I915_WRITE(reg, val);
1103 /* Set both together, unset both together: see the spec. */
1104 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1105 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1106 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1108 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1109 val |= VIDEO_DIP_ENABLE_GCP;
1111 I915_WRITE(reg, val);
1114 intel_write_infoframe(encoder, crtc_state,
1115 HDMI_INFOFRAME_TYPE_AVI,
1116 &crtc_state->infoframes.avi);
1117 intel_write_infoframe(encoder, crtc_state,
1118 HDMI_INFOFRAME_TYPE_SPD,
1119 &crtc_state->infoframes.spd);
1120 intel_write_infoframe(encoder, crtc_state,
1121 HDMI_INFOFRAME_TYPE_VENDOR,
1122 &crtc_state->infoframes.hdmi);
1125 static void vlv_set_infoframes(struct intel_encoder *encoder,
1127 const struct intel_crtc_state *crtc_state,
1128 const struct drm_connector_state *conn_state)
1130 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1132 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1133 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1134 u32 val = I915_READ(reg);
1135 u32 port = VIDEO_DIP_PORT(encoder->port);
1137 assert_hdmi_port_disabled(intel_hdmi);
1139 /* See the big comment in g4x_set_infoframes() */
1140 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1143 if (!(val & VIDEO_DIP_ENABLE))
1145 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1146 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1147 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1148 I915_WRITE(reg, val);
1153 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1154 WARN(val & VIDEO_DIP_ENABLE,
1155 "DIP already enabled on port %c\n",
1156 (val & VIDEO_DIP_PORT_MASK) >> 29);
1157 val &= ~VIDEO_DIP_PORT_MASK;
1161 val |= VIDEO_DIP_ENABLE;
1162 val &= ~(VIDEO_DIP_ENABLE_AVI |
1163 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1164 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1166 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1167 val |= VIDEO_DIP_ENABLE_GCP;
1169 I915_WRITE(reg, val);
1172 intel_write_infoframe(encoder, crtc_state,
1173 HDMI_INFOFRAME_TYPE_AVI,
1174 &crtc_state->infoframes.avi);
1175 intel_write_infoframe(encoder, crtc_state,
1176 HDMI_INFOFRAME_TYPE_SPD,
1177 &crtc_state->infoframes.spd);
1178 intel_write_infoframe(encoder, crtc_state,
1179 HDMI_INFOFRAME_TYPE_VENDOR,
1180 &crtc_state->infoframes.hdmi);
1183 static void hsw_set_infoframes(struct intel_encoder *encoder,
1185 const struct intel_crtc_state *crtc_state,
1186 const struct drm_connector_state *conn_state)
1188 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1189 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1190 u32 val = I915_READ(reg);
1192 assert_hdmi_transcoder_func_disabled(dev_priv,
1193 crtc_state->cpu_transcoder);
1195 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1196 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1197 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1198 VIDEO_DIP_ENABLE_DRM_GLK);
1201 I915_WRITE(reg, val);
1206 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1207 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1209 I915_WRITE(reg, val);
1212 intel_write_infoframe(encoder, crtc_state,
1213 HDMI_INFOFRAME_TYPE_AVI,
1214 &crtc_state->infoframes.avi);
1215 intel_write_infoframe(encoder, crtc_state,
1216 HDMI_INFOFRAME_TYPE_SPD,
1217 &crtc_state->infoframes.spd);
1218 intel_write_infoframe(encoder, crtc_state,
1219 HDMI_INFOFRAME_TYPE_VENDOR,
1220 &crtc_state->infoframes.hdmi);
1221 intel_write_infoframe(encoder, crtc_state,
1222 HDMI_INFOFRAME_TYPE_DRM,
1223 &crtc_state->infoframes.drm);
1226 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1228 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1229 struct i2c_adapter *adapter =
1230 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1232 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1235 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
1236 enable ? "Enabling" : "Disabling");
1238 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
1242 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
1243 unsigned int offset, void *buffer, size_t size)
1245 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1246 struct drm_i915_private *dev_priv =
1247 intel_dig_port->base.base.dev->dev_private;
1248 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1251 u8 start = offset & 0xff;
1252 struct i2c_msg msgs[] = {
1254 .addr = DRM_HDCP_DDC_ADDR,
1260 .addr = DRM_HDCP_DDC_ADDR,
1266 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1267 if (ret == ARRAY_SIZE(msgs))
1269 return ret >= 0 ? -EIO : ret;
1272 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
1273 unsigned int offset, void *buffer, size_t size)
1275 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1276 struct drm_i915_private *dev_priv =
1277 intel_dig_port->base.base.dev->dev_private;
1278 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1284 write_buf = kzalloc(size + 1, GFP_KERNEL);
1288 write_buf[0] = offset & 0xff;
1289 memcpy(&write_buf[1], buffer, size);
1291 msg.addr = DRM_HDCP_DDC_ADDR;
1294 msg.buf = write_buf;
1296 ret = i2c_transfer(adapter, &msg, 1);
1307 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
1310 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1311 struct drm_i915_private *dev_priv =
1312 intel_dig_port->base.base.dev->dev_private;
1313 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1317 ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
1320 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
1324 ret = intel_gmbus_output_aksv(adapter);
1326 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
1332 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
1336 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
1339 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
1344 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1348 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1349 bstatus, DRM_HDCP_BSTATUS_LEN);
1351 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1356 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1357 bool *repeater_present)
1362 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1364 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1367 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1372 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1376 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1377 ri_prime, DRM_HDCP_RI_LEN);
1379 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1384 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1390 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1392 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1395 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1400 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1401 int num_downstream, u8 *ksv_fifo)
1404 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1405 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1407 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1414 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1419 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1422 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1423 part, DRM_HDCP_V_PRIME_PART_LEN);
1425 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1429 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector)
1431 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1432 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
1433 struct drm_crtc *crtc = connector->base.state->crtc;
1434 struct intel_crtc *intel_crtc = container_of(crtc,
1435 struct intel_crtc, base);
1440 scanline = I915_READ(PIPEDSL(intel_crtc->pipe));
1441 if (scanline > 100 && scanline < 200)
1443 usleep_range(25, 50);
1446 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false);
1448 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret);
1451 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true);
1453 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret);
1461 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1464 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1465 struct intel_connector *connector = hdmi->attached_connector;
1466 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1470 usleep_range(6, 60); /* Bspec says >= 6us */
1472 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1474 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1475 enable ? "Enable" : "Disable", ret);
1480 * WA: To fix incorrect positioning of the window of
1481 * opportunity and enc_en signalling in KABYLAKE.
1483 if (IS_KABYLAKE(dev_priv) && enable)
1484 return kbl_repositioning_enc_en_signal(connector);
1490 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1492 struct drm_i915_private *dev_priv =
1493 intel_dig_port->base.base.dev->dev_private;
1494 struct intel_connector *connector =
1495 intel_dig_port->hdmi.attached_connector;
1496 enum port port = intel_dig_port->base.port;
1497 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1501 u8 shim[DRM_HDCP_RI_LEN];
1504 ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1508 I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg);
1510 /* Wait for Ri prime match */
1511 if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
1512 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1513 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1514 I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
1521 struct hdcp2_hdmi_msg_data {
1527 static const struct hdcp2_hdmi_msg_data hdcp2_msg_data[] = {
1528 { HDCP_2_2_AKE_INIT, 0, 0 },
1529 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
1530 { HDCP_2_2_AKE_NO_STORED_KM, 0, 0 },
1531 { HDCP_2_2_AKE_STORED_KM, 0, 0 },
1532 { HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
1533 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
1534 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
1535 { HDCP_2_2_LC_INIT, 0, 0 },
1536 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0 },
1537 { HDCP_2_2_SKE_SEND_EKS, 0, 0 },
1538 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
1539 { HDCP_2_2_REP_SEND_ACK, 0, 0 },
1540 { HDCP_2_2_REP_STREAM_MANAGE, 0, 0 },
1541 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
1545 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
1548 return intel_hdmi_hdcp_read(intel_dig_port,
1549 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1551 HDCP_2_2_HDMI_RXSTATUS_LEN);
1554 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1558 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++)
1559 if (hdcp2_msg_data[i].msg_id == msg_id &&
1560 (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired))
1561 return hdcp2_msg_data[i].timeout;
1562 else if (hdcp2_msg_data[i].msg_id == msg_id)
1563 return hdcp2_msg_data[i].timeout2;
1569 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port,
1570 u8 msg_id, bool *msg_ready,
1573 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1576 ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status);
1578 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
1582 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1585 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1586 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1589 *msg_ready = *msg_sz;
1595 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
1596 u8 msg_id, bool paired)
1598 bool msg_ready = false;
1602 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1606 ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
1609 !ret && msg_ready && msg_sz, timeout * 1000,
1612 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n",
1613 msg_id, ret, timeout);
1615 return ret ? ret : msg_sz;
1619 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
1620 void *buf, size_t size)
1622 unsigned int offset;
1624 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1625 return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
1629 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
1630 u8 msg_id, void *buf, size_t size)
1632 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1633 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1634 unsigned int offset;
1637 ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id,
1643 * Available msg size should be equal to or lesser than the
1647 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n",
1652 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1653 ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret);
1655 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret);
1661 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
1663 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1666 ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status);
1671 * Re-auth request and Link Integrity Failures are represented by
1672 * same bit. i.e reauth_req.
1674 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1675 ret = HDCP_REAUTH_REQUEST;
1676 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1677 ret = HDCP_TOPOLOGY_CHANGE;
1683 int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port,
1690 ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1691 &hdcp2_version, sizeof(hdcp2_version));
1692 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1699 enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void)
1701 return HDCP_PROTOCOL_HDMI;
1704 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1705 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1706 .read_bksv = intel_hdmi_hdcp_read_bksv,
1707 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1708 .repeater_present = intel_hdmi_hdcp_repeater_present,
1709 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1710 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1711 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1712 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1713 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1714 .check_link = intel_hdmi_hdcp_check_link,
1715 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1716 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1717 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1718 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1719 .protocol = HDCP_PROTOCOL_HDMI,
1722 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1723 const struct intel_crtc_state *crtc_state)
1725 struct drm_device *dev = encoder->base.dev;
1726 struct drm_i915_private *dev_priv = to_i915(dev);
1727 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1728 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1729 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1732 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1734 hdmi_val = SDVO_ENCODING_HDMI;
1735 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1736 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1737 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1738 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1739 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1740 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1742 if (crtc_state->pipe_bpp > 24)
1743 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1745 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1747 if (crtc_state->has_hdmi_sink)
1748 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1750 if (HAS_PCH_CPT(dev_priv))
1751 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1752 else if (IS_CHERRYVIEW(dev_priv))
1753 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1755 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1757 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1758 POSTING_READ(intel_hdmi->hdmi_reg);
1761 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1764 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1765 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1766 intel_wakeref_t wakeref;
1769 wakeref = intel_display_power_get_if_enabled(dev_priv,
1770 encoder->power_domain);
1774 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1776 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1781 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1782 struct intel_crtc_state *pipe_config)
1784 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1785 struct drm_device *dev = encoder->base.dev;
1786 struct drm_i915_private *dev_priv = to_i915(dev);
1790 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1792 tmp = I915_READ(intel_hdmi->hdmi_reg);
1794 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1795 flags |= DRM_MODE_FLAG_PHSYNC;
1797 flags |= DRM_MODE_FLAG_NHSYNC;
1799 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1800 flags |= DRM_MODE_FLAG_PVSYNC;
1802 flags |= DRM_MODE_FLAG_NVSYNC;
1804 if (tmp & HDMI_MODE_SELECT_HDMI)
1805 pipe_config->has_hdmi_sink = true;
1807 pipe_config->infoframes.enable |=
1808 intel_hdmi_infoframes_enabled(encoder, pipe_config);
1810 if (pipe_config->infoframes.enable)
1811 pipe_config->has_infoframe = true;
1813 if (tmp & HDMI_AUDIO_ENABLE)
1814 pipe_config->has_audio = true;
1816 if (!HAS_PCH_SPLIT(dev_priv) &&
1817 tmp & HDMI_COLOR_RANGE_16_235)
1818 pipe_config->limited_color_range = true;
1820 pipe_config->base.adjusted_mode.flags |= flags;
1822 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1823 dotclock = pipe_config->port_clock * 2 / 3;
1825 dotclock = pipe_config->port_clock;
1827 if (pipe_config->pixel_multiplier)
1828 dotclock /= pipe_config->pixel_multiplier;
1830 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1832 pipe_config->lane_count = 4;
1834 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
1836 intel_read_infoframe(encoder, pipe_config,
1837 HDMI_INFOFRAME_TYPE_AVI,
1838 &pipe_config->infoframes.avi);
1839 intel_read_infoframe(encoder, pipe_config,
1840 HDMI_INFOFRAME_TYPE_SPD,
1841 &pipe_config->infoframes.spd);
1842 intel_read_infoframe(encoder, pipe_config,
1843 HDMI_INFOFRAME_TYPE_VENDOR,
1844 &pipe_config->infoframes.hdmi);
1847 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1848 const struct intel_crtc_state *pipe_config,
1849 const struct drm_connector_state *conn_state)
1851 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1853 WARN_ON(!pipe_config->has_hdmi_sink);
1854 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1855 pipe_name(crtc->pipe));
1856 intel_audio_codec_enable(encoder, pipe_config, conn_state);
1859 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1860 const struct intel_crtc_state *pipe_config,
1861 const struct drm_connector_state *conn_state)
1863 struct drm_device *dev = encoder->base.dev;
1864 struct drm_i915_private *dev_priv = to_i915(dev);
1865 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1868 temp = I915_READ(intel_hdmi->hdmi_reg);
1870 temp |= SDVO_ENABLE;
1871 if (pipe_config->has_audio)
1872 temp |= HDMI_AUDIO_ENABLE;
1874 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1875 POSTING_READ(intel_hdmi->hdmi_reg);
1877 if (pipe_config->has_audio)
1878 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1881 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1882 const struct intel_crtc_state *pipe_config,
1883 const struct drm_connector_state *conn_state)
1885 struct drm_device *dev = encoder->base.dev;
1886 struct drm_i915_private *dev_priv = to_i915(dev);
1887 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1890 temp = I915_READ(intel_hdmi->hdmi_reg);
1892 temp |= SDVO_ENABLE;
1893 if (pipe_config->has_audio)
1894 temp |= HDMI_AUDIO_ENABLE;
1897 * HW workaround, need to write this twice for issue
1898 * that may result in first write getting masked.
1900 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1901 POSTING_READ(intel_hdmi->hdmi_reg);
1902 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1903 POSTING_READ(intel_hdmi->hdmi_reg);
1906 * HW workaround, need to toggle enable bit off and on
1907 * for 12bpc with pixel repeat.
1909 * FIXME: BSpec says this should be done at the end of
1910 * of the modeset sequence, so not sure if this isn't too soon.
1912 if (pipe_config->pipe_bpp > 24 &&
1913 pipe_config->pixel_multiplier > 1) {
1914 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1915 POSTING_READ(intel_hdmi->hdmi_reg);
1918 * HW workaround, need to write this twice for issue
1919 * that may result in first write getting masked.
1921 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1922 POSTING_READ(intel_hdmi->hdmi_reg);
1923 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1924 POSTING_READ(intel_hdmi->hdmi_reg);
1927 if (pipe_config->has_audio)
1928 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1931 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1932 const struct intel_crtc_state *pipe_config,
1933 const struct drm_connector_state *conn_state)
1935 struct drm_device *dev = encoder->base.dev;
1936 struct drm_i915_private *dev_priv = to_i915(dev);
1937 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1938 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1939 enum pipe pipe = crtc->pipe;
1942 temp = I915_READ(intel_hdmi->hdmi_reg);
1944 temp |= SDVO_ENABLE;
1945 if (pipe_config->has_audio)
1946 temp |= HDMI_AUDIO_ENABLE;
1949 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1951 * The procedure for 12bpc is as follows:
1952 * 1. disable HDMI clock gating
1953 * 2. enable HDMI with 8bpc
1954 * 3. enable HDMI with 12bpc
1955 * 4. enable HDMI clock gating
1958 if (pipe_config->pipe_bpp > 24) {
1959 I915_WRITE(TRANS_CHICKEN1(pipe),
1960 I915_READ(TRANS_CHICKEN1(pipe)) |
1961 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1963 temp &= ~SDVO_COLOR_FORMAT_MASK;
1964 temp |= SDVO_COLOR_FORMAT_8bpc;
1967 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1968 POSTING_READ(intel_hdmi->hdmi_reg);
1970 if (pipe_config->pipe_bpp > 24) {
1971 temp &= ~SDVO_COLOR_FORMAT_MASK;
1972 temp |= HDMI_COLOR_FORMAT_12bpc;
1974 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1975 POSTING_READ(intel_hdmi->hdmi_reg);
1977 I915_WRITE(TRANS_CHICKEN1(pipe),
1978 I915_READ(TRANS_CHICKEN1(pipe)) &
1979 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1982 if (pipe_config->has_audio)
1983 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1986 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1987 const struct intel_crtc_state *pipe_config,
1988 const struct drm_connector_state *conn_state)
1992 static void intel_disable_hdmi(struct intel_encoder *encoder,
1993 const struct intel_crtc_state *old_crtc_state,
1994 const struct drm_connector_state *old_conn_state)
1996 struct drm_device *dev = encoder->base.dev;
1997 struct drm_i915_private *dev_priv = to_i915(dev);
1998 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1999 struct intel_digital_port *intel_dig_port =
2000 hdmi_to_dig_port(intel_hdmi);
2001 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2004 temp = I915_READ(intel_hdmi->hdmi_reg);
2006 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
2007 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2008 POSTING_READ(intel_hdmi->hdmi_reg);
2011 * HW workaround for IBX, we need to move the port
2012 * to transcoder A after disabling it to allow the
2013 * matching DP port to be enabled on transcoder A.
2015 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
2017 * We get CPU/PCH FIFO underruns on the other pipe when
2018 * doing the workaround. Sweep them under the rug.
2020 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2021 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2023 temp &= ~SDVO_PIPE_SEL_MASK;
2024 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
2026 * HW workaround, need to write this twice for issue
2027 * that may result in first write getting masked.
2029 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2030 POSTING_READ(intel_hdmi->hdmi_reg);
2031 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2032 POSTING_READ(intel_hdmi->hdmi_reg);
2034 temp &= ~SDVO_ENABLE;
2035 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2036 POSTING_READ(intel_hdmi->hdmi_reg);
2038 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
2039 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2040 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2043 intel_dig_port->set_infoframes(encoder,
2045 old_crtc_state, old_conn_state);
2047 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2050 static void g4x_disable_hdmi(struct intel_encoder *encoder,
2051 const struct intel_crtc_state *old_crtc_state,
2052 const struct drm_connector_state *old_conn_state)
2054 if (old_crtc_state->has_audio)
2055 intel_audio_codec_disable(encoder,
2056 old_crtc_state, old_conn_state);
2058 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2061 static void pch_disable_hdmi(struct intel_encoder *encoder,
2062 const struct intel_crtc_state *old_crtc_state,
2063 const struct drm_connector_state *old_conn_state)
2065 if (old_crtc_state->has_audio)
2066 intel_audio_codec_disable(encoder,
2067 old_crtc_state, old_conn_state);
2070 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
2071 const struct intel_crtc_state *old_crtc_state,
2072 const struct drm_connector_state *old_conn_state)
2074 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2077 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
2079 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2080 const struct ddi_vbt_port_info *info =
2081 &dev_priv->vbt.ddi_port_info[encoder->port];
2084 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2085 max_tmds_clock = 594000;
2086 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
2087 max_tmds_clock = 300000;
2088 else if (INTEL_GEN(dev_priv) >= 5)
2089 max_tmds_clock = 225000;
2091 max_tmds_clock = 165000;
2093 if (info->max_tmds_clock)
2094 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
2096 return max_tmds_clock;
2099 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
2100 bool respect_downstream_limits,
2103 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2104 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
2106 if (respect_downstream_limits) {
2107 struct intel_connector *connector = hdmi->attached_connector;
2108 const struct drm_display_info *info = &connector->base.display_info;
2110 if (hdmi->dp_dual_mode.max_tmds_clock)
2111 max_tmds_clock = min(max_tmds_clock,
2112 hdmi->dp_dual_mode.max_tmds_clock);
2114 if (info->max_tmds_clock)
2115 max_tmds_clock = min(max_tmds_clock,
2116 info->max_tmds_clock);
2117 else if (!hdmi->has_hdmi_sink || force_dvi)
2118 max_tmds_clock = min(max_tmds_clock, 165000);
2121 return max_tmds_clock;
2124 static enum drm_mode_status
2125 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
2126 int clock, bool respect_downstream_limits,
2129 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
2132 return MODE_CLOCK_LOW;
2133 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
2134 return MODE_CLOCK_HIGH;
2136 /* BXT DPLL can't generate 223-240 MHz */
2137 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
2138 return MODE_CLOCK_RANGE;
2140 /* CHV DPLL can't generate 216-240 MHz */
2141 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
2142 return MODE_CLOCK_RANGE;
2147 static enum drm_mode_status
2148 intel_hdmi_mode_valid(struct drm_connector *connector,
2149 struct drm_display_mode *mode)
2151 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2152 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
2153 struct drm_i915_private *dev_priv = to_i915(dev);
2154 enum drm_mode_status status;
2156 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
2158 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
2160 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
2161 return MODE_NO_DBLESCAN;
2163 clock = mode->clock;
2165 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2168 if (clock > max_dotclk)
2169 return MODE_CLOCK_HIGH;
2171 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2174 if (drm_mode_is_420_only(&connector->display_info, mode))
2177 /* check if we can do 8bpc */
2178 status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
2180 if (hdmi->has_hdmi_sink && !force_dvi) {
2181 /* if we can't do 8bpc we may still be able to do 12bpc */
2182 if (status != MODE_OK && !HAS_GMCH(dev_priv))
2183 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
2186 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2187 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
2188 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
2195 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2198 struct drm_i915_private *dev_priv =
2199 to_i915(crtc_state->base.crtc->dev);
2200 struct drm_atomic_state *state = crtc_state->base.state;
2201 struct drm_connector_state *connector_state;
2202 struct drm_connector *connector;
2203 const struct drm_display_mode *adjusted_mode =
2204 &crtc_state->base.adjusted_mode;
2207 if (HAS_GMCH(dev_priv))
2210 if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
2213 if (crtc_state->pipe_bpp < bpc * 3)
2216 if (!crtc_state->has_hdmi_sink)
2220 * HDMI deep color affects the clocks, so it's only possible
2221 * when not cloning with other encoder types.
2223 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
2226 for_each_new_connector_in_state(state, connector, connector_state, i) {
2227 const struct drm_display_info *info = &connector->display_info;
2229 if (connector_state->crtc != crtc_state->base.crtc)
2232 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2233 const struct drm_hdmi_info *hdmi = &info->hdmi;
2235 if (bpc == 12 && !(hdmi->y420_dc_modes &
2236 DRM_EDID_YCBCR420_DC_36))
2238 else if (bpc == 10 && !(hdmi->y420_dc_modes &
2239 DRM_EDID_YCBCR420_DC_30))
2242 if (bpc == 12 && !(info->edid_hdmi_dc_modes &
2243 DRM_EDID_HDMI_DC_36))
2245 else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
2246 DRM_EDID_HDMI_DC_30))
2251 /* Display WA #1139: glk */
2252 if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
2253 adjusted_mode->htotal > 5460)
2256 /* Display Wa_1405510057:icl */
2257 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2258 bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
2259 (adjusted_mode->crtc_hblank_end -
2260 adjusted_mode->crtc_hblank_start) % 8 == 2)
2267 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
2268 struct intel_crtc_state *config)
2270 struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
2272 if (!connector->ycbcr_420_allowed) {
2273 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
2277 config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2279 /* YCBCR 420 output conversion needs a scaler */
2280 if (skl_update_scaler_crtc(config)) {
2281 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2285 intel_pch_panel_fitting(intel_crtc, config,
2286 DRM_MODE_SCALE_FULLSCREEN);
2291 static int intel_hdmi_port_clock(int clock, int bpc)
2294 * Need to adjust the port link by:
2298 return clock * bpc / 8;
2301 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2302 struct intel_crtc_state *crtc_state,
2303 int clock, bool force_dvi)
2305 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2308 for (bpc = 12; bpc >= 10; bpc -= 2) {
2309 if (hdmi_deep_color_possible(crtc_state, bpc) &&
2310 hdmi_port_clock_valid(intel_hdmi,
2311 intel_hdmi_port_clock(clock, bpc),
2312 true, force_dvi) == MODE_OK)
2319 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2320 struct intel_crtc_state *crtc_state,
2323 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2324 const struct drm_display_mode *adjusted_mode =
2325 &crtc_state->base.adjusted_mode;
2326 int bpc, clock = adjusted_mode->crtc_clock;
2328 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2331 /* YCBCR420 TMDS rate requirement is half the pixel clock */
2332 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2335 bpc = intel_hdmi_compute_bpc(encoder, crtc_state,
2338 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
2341 * pipe_bpp could already be below 8bpc due to
2342 * FDI bandwidth constraints. We shouldn't bump it
2343 * back up to 8bpc in that case.
2345 if (crtc_state->pipe_bpp > bpc * 3)
2346 crtc_state->pipe_bpp = bpc * 3;
2348 DRM_DEBUG_KMS("picking %d bpc for HDMI output (pipe bpp: %d)\n",
2349 bpc, crtc_state->pipe_bpp);
2351 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2352 false, force_dvi) != MODE_OK) {
2353 DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n",
2354 crtc_state->port_clock);
2361 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2362 struct intel_crtc_state *pipe_config,
2363 struct drm_connector_state *conn_state)
2365 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2366 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2367 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2368 struct drm_connector *connector = conn_state->connector;
2369 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2370 struct intel_digital_connector_state *intel_conn_state =
2371 to_intel_digital_connector_state(conn_state);
2372 bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
2375 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2378 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2379 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
2381 if (pipe_config->has_hdmi_sink)
2382 pipe_config->has_infoframe = true;
2384 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2385 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2386 pipe_config->limited_color_range =
2387 pipe_config->has_hdmi_sink &&
2388 drm_default_rgb_quant_range(adjusted_mode) ==
2389 HDMI_QUANTIZATION_RANGE_LIMITED;
2391 pipe_config->limited_color_range =
2392 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2395 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2396 pipe_config->pixel_multiplier = 2;
2398 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
2399 if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) {
2400 DRM_ERROR("Can't support YCBCR420 output\n");
2405 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2406 pipe_config->has_pch_encoder = true;
2408 if (pipe_config->has_hdmi_sink) {
2409 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2410 pipe_config->has_audio = intel_hdmi->has_audio;
2412 pipe_config->has_audio =
2413 intel_conn_state->force_audio == HDMI_AUDIO_ON;
2416 ret = intel_hdmi_compute_clock(encoder, pipe_config, force_dvi);
2420 /* Set user selected PAR to incoming mode's member */
2421 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
2423 pipe_config->lane_count = 4;
2425 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
2426 IS_GEMINILAKE(dev_priv))) {
2427 if (scdc->scrambling.low_rates)
2428 pipe_config->hdmi_scrambling = true;
2430 if (pipe_config->port_clock > 340000) {
2431 pipe_config->hdmi_scrambling = true;
2432 pipe_config->hdmi_high_tmds_clock_ratio = true;
2436 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state);
2438 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2439 DRM_DEBUG_KMS("bad AVI infoframe\n");
2443 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2444 DRM_DEBUG_KMS("bad SPD infoframe\n");
2448 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2449 DRM_DEBUG_KMS("bad HDMI infoframe\n");
2453 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2454 DRM_DEBUG_KMS("bad DRM infoframe\n");
2458 intel_hdcp_transcoder_config(intel_hdmi->attached_connector,
2459 pipe_config->cpu_transcoder);
2465 intel_hdmi_unset_edid(struct drm_connector *connector)
2467 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2469 intel_hdmi->has_hdmi_sink = false;
2470 intel_hdmi->has_audio = false;
2472 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2473 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2475 kfree(to_intel_connector(connector)->detect_edid);
2476 to_intel_connector(connector)->detect_edid = NULL;
2480 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2482 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2483 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2484 enum port port = hdmi_to_dig_port(hdmi)->base.port;
2485 struct i2c_adapter *adapter =
2486 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2487 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2490 * Type 1 DVI adaptors are not required to implement any
2491 * registers, so we can't always detect their presence.
2492 * Ideally we should be able to check the state of the
2493 * CONFIG1 pin, but no such luck on our hardware.
2495 * The only method left to us is to check the VBT to see
2496 * if the port is a dual mode capable DP port. But let's
2497 * only do that when we sucesfully read the EDID, to avoid
2498 * confusing log messages about DP dual mode adaptors when
2499 * there's nothing connected to the port.
2501 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2502 /* An overridden EDID imply that we want this port for testing.
2503 * Make sure not to set limits for that port.
2505 if (has_edid && !connector->override_edid &&
2506 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2507 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
2508 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2510 type = DRM_DP_DUAL_MODE_NONE;
2514 if (type == DRM_DP_DUAL_MODE_NONE)
2517 hdmi->dp_dual_mode.type = type;
2518 hdmi->dp_dual_mode.max_tmds_clock =
2519 drm_dp_dual_mode_max_tmds_clock(type, adapter);
2521 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2522 drm_dp_get_dual_mode_type_name(type),
2523 hdmi->dp_dual_mode.max_tmds_clock);
2527 intel_hdmi_set_edid(struct drm_connector *connector)
2529 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2530 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2531 intel_wakeref_t wakeref;
2533 bool connected = false;
2534 struct i2c_adapter *i2c;
2536 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2538 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2540 edid = drm_get_edid(connector, i2c);
2542 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2543 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2544 intel_gmbus_force_bit(i2c, true);
2545 edid = drm_get_edid(connector, i2c);
2546 intel_gmbus_force_bit(i2c, false);
2549 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2551 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2553 to_intel_connector(connector)->detect_edid = edid;
2554 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2555 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2556 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2561 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2566 static enum drm_connector_status
2567 intel_hdmi_detect(struct drm_connector *connector, bool force)
2569 enum drm_connector_status status = connector_status_disconnected;
2570 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2571 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2572 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2573 intel_wakeref_t wakeref;
2575 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2576 connector->base.id, connector->name);
2578 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2580 if (INTEL_GEN(dev_priv) >= 11 &&
2581 !intel_digital_port_connected(encoder))
2584 intel_hdmi_unset_edid(connector);
2586 if (intel_hdmi_set_edid(connector))
2587 status = connector_status_connected;
2590 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2592 if (status != connector_status_connected)
2593 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2599 intel_hdmi_force(struct drm_connector *connector)
2601 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2602 connector->base.id, connector->name);
2604 intel_hdmi_unset_edid(connector);
2606 if (connector->status != connector_status_connected)
2609 intel_hdmi_set_edid(connector);
2612 static int intel_hdmi_get_modes(struct drm_connector *connector)
2616 edid = to_intel_connector(connector)->detect_edid;
2620 return intel_connector_update_modes(connector, edid);
2623 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
2624 const struct intel_crtc_state *pipe_config,
2625 const struct drm_connector_state *conn_state)
2627 struct intel_digital_port *intel_dig_port =
2628 enc_to_dig_port(&encoder->base);
2630 intel_hdmi_prepare(encoder, pipe_config);
2632 intel_dig_port->set_infoframes(encoder,
2633 pipe_config->has_infoframe,
2634 pipe_config, conn_state);
2637 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
2638 const struct intel_crtc_state *pipe_config,
2639 const struct drm_connector_state *conn_state)
2641 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2642 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2644 vlv_phy_pre_encoder_enable(encoder, pipe_config);
2647 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2650 dport->set_infoframes(encoder,
2651 pipe_config->has_infoframe,
2652 pipe_config, conn_state);
2654 g4x_enable_hdmi(encoder, pipe_config, conn_state);
2656 vlv_wait_port_ready(dev_priv, dport, 0x0);
2659 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2660 const struct intel_crtc_state *pipe_config,
2661 const struct drm_connector_state *conn_state)
2663 intel_hdmi_prepare(encoder, pipe_config);
2665 vlv_phy_pre_pll_enable(encoder, pipe_config);
2668 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2669 const struct intel_crtc_state *pipe_config,
2670 const struct drm_connector_state *conn_state)
2672 intel_hdmi_prepare(encoder, pipe_config);
2674 chv_phy_pre_pll_enable(encoder, pipe_config);
2677 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2678 const struct intel_crtc_state *old_crtc_state,
2679 const struct drm_connector_state *old_conn_state)
2681 chv_phy_post_pll_disable(encoder, old_crtc_state);
2684 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2685 const struct intel_crtc_state *old_crtc_state,
2686 const struct drm_connector_state *old_conn_state)
2688 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2689 vlv_phy_reset_lanes(encoder, old_crtc_state);
2692 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2693 const struct intel_crtc_state *old_crtc_state,
2694 const struct drm_connector_state *old_conn_state)
2696 struct drm_device *dev = encoder->base.dev;
2697 struct drm_i915_private *dev_priv = to_i915(dev);
2699 vlv_dpio_get(dev_priv);
2701 /* Assert data lane reset */
2702 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2704 vlv_dpio_put(dev_priv);
2707 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2708 const struct intel_crtc_state *pipe_config,
2709 const struct drm_connector_state *conn_state)
2711 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2712 struct drm_device *dev = encoder->base.dev;
2713 struct drm_i915_private *dev_priv = to_i915(dev);
2715 chv_phy_pre_encoder_enable(encoder, pipe_config);
2717 /* FIXME: Program the support xxx V-dB */
2719 chv_set_phy_signal_level(encoder, 128, 102, false);
2721 dport->set_infoframes(encoder,
2722 pipe_config->has_infoframe,
2723 pipe_config, conn_state);
2725 g4x_enable_hdmi(encoder, pipe_config, conn_state);
2727 vlv_wait_port_ready(dev_priv, dport, 0x0);
2729 /* Second common lane will stay alive on its own now */
2730 chv_phy_release_cl2_override(encoder);
2733 static struct i2c_adapter *
2734 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2736 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2737 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2739 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2742 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2744 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2745 struct kobject *i2c_kobj = &adapter->dev.kobj;
2746 struct kobject *connector_kobj = &connector->kdev->kobj;
2749 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2751 DRM_ERROR("Failed to create i2c symlink (%d)\n", ret);
2754 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2756 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2757 struct kobject *i2c_kobj = &adapter->dev.kobj;
2758 struct kobject *connector_kobj = &connector->kdev->kobj;
2760 sysfs_remove_link(connector_kobj, i2c_kobj->name);
2764 intel_hdmi_connector_register(struct drm_connector *connector)
2768 ret = intel_connector_register(connector);
2772 i915_debugfs_connector_add(connector);
2774 intel_hdmi_create_i2c_symlink(connector);
2779 static void intel_hdmi_destroy(struct drm_connector *connector)
2781 if (intel_attached_hdmi(connector)->cec_notifier)
2782 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2784 intel_connector_destroy(connector);
2787 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2789 intel_hdmi_remove_i2c_symlink(connector);
2791 intel_connector_unregister(connector);
2794 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2795 .detect = intel_hdmi_detect,
2796 .force = intel_hdmi_force,
2797 .fill_modes = drm_helper_probe_single_connector_modes,
2798 .atomic_get_property = intel_digital_connector_atomic_get_property,
2799 .atomic_set_property = intel_digital_connector_atomic_set_property,
2800 .late_register = intel_hdmi_connector_register,
2801 .early_unregister = intel_hdmi_connector_unregister,
2802 .destroy = intel_hdmi_destroy,
2803 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2804 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2807 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2808 .get_modes = intel_hdmi_get_modes,
2809 .mode_valid = intel_hdmi_mode_valid,
2810 .atomic_check = intel_digital_connector_atomic_check,
2813 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2814 .destroy = intel_encoder_destroy,
2818 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2820 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2821 struct intel_digital_port *intel_dig_port =
2822 hdmi_to_dig_port(intel_hdmi);
2824 intel_attach_force_audio_property(connector);
2825 intel_attach_broadcast_rgb_property(connector);
2826 intel_attach_aspect_ratio_property(connector);
2829 * Attach Colorspace property for Non LSPCON based device
2830 * ToDo: This needs to be extended for LSPCON implementation
2831 * as well. Will be implemented separately.
2833 if (!intel_dig_port->lspcon.active)
2834 intel_attach_colorspace_property(connector);
2836 drm_connector_attach_content_type_property(connector);
2837 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2839 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2840 drm_object_attach_property(&connector->base,
2841 connector->dev->mode_config.hdr_output_metadata_property, 0);
2843 if (!HAS_GMCH(dev_priv))
2844 drm_connector_attach_max_bpc_property(connector, 8, 12);
2848 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2849 * @encoder: intel_encoder
2850 * @connector: drm_connector
2851 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2852 * or reset the high tmds clock ratio for scrambling
2853 * @scrambling: bool to Indicate if the function needs to set or reset
2856 * This function handles scrambling on HDMI 2.0 capable sinks.
2857 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2858 * it enables scrambling. This should be called before enabling the HDMI
2859 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2860 * detect a scrambled clock within 100 ms.
2863 * True on success, false on failure.
2865 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2866 struct drm_connector *connector,
2867 bool high_tmds_clock_ratio,
2870 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2871 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2872 struct drm_scrambling *sink_scrambling =
2873 &connector->display_info.hdmi.scdc.scrambling;
2874 struct i2c_adapter *adapter =
2875 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2877 if (!sink_scrambling->supported)
2880 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2881 connector->base.id, connector->name,
2882 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2884 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2885 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2886 high_tmds_clock_ratio) &&
2887 drm_scdc_set_scrambling(adapter, scrambling);
2890 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2896 ddc_pin = GMBUS_PIN_DPB;
2899 ddc_pin = GMBUS_PIN_DPC;
2902 ddc_pin = GMBUS_PIN_DPD_CHV;
2906 ddc_pin = GMBUS_PIN_DPB;
2912 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2918 ddc_pin = GMBUS_PIN_1_BXT;
2921 ddc_pin = GMBUS_PIN_2_BXT;
2925 ddc_pin = GMBUS_PIN_1_BXT;
2931 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2938 ddc_pin = GMBUS_PIN_1_BXT;
2941 ddc_pin = GMBUS_PIN_2_BXT;
2944 ddc_pin = GMBUS_PIN_4_CNP;
2947 ddc_pin = GMBUS_PIN_3_BXT;
2951 ddc_pin = GMBUS_PIN_1_BXT;
2957 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2959 enum phy phy = intel_port_to_phy(dev_priv, port);
2961 if (intel_phy_is_combo(dev_priv, phy))
2962 return GMBUS_PIN_1_BXT + port;
2963 else if (intel_phy_is_tc(dev_priv, phy))
2964 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2966 WARN(1, "Unknown port:%c\n", port_name(port));
2967 return GMBUS_PIN_2_BXT;
2970 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2972 enum phy phy = intel_port_to_phy(dev_priv, port);
2977 ddc_pin = GMBUS_PIN_1_BXT;
2980 ddc_pin = GMBUS_PIN_2_BXT;
2983 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2987 ddc_pin = GMBUS_PIN_1_BXT;
2993 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
3000 ddc_pin = GMBUS_PIN_DPB;
3003 ddc_pin = GMBUS_PIN_DPC;
3006 ddc_pin = GMBUS_PIN_DPD;
3010 ddc_pin = GMBUS_PIN_DPB;
3016 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
3019 const struct ddi_vbt_port_info *info =
3020 &dev_priv->vbt.ddi_port_info[port];
3023 if (info->alternate_ddc_pin) {
3024 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
3025 info->alternate_ddc_pin, port_name(port));
3026 return info->alternate_ddc_pin;
3029 if (HAS_PCH_MCC(dev_priv))
3030 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
3031 else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_ICP(dev_priv))
3032 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
3033 else if (HAS_PCH_CNP(dev_priv))
3034 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
3035 else if (IS_GEN9_LP(dev_priv))
3036 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
3037 else if (IS_CHERRYVIEW(dev_priv))
3038 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
3040 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
3042 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
3043 ddc_pin, port_name(port));
3048 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
3050 struct drm_i915_private *dev_priv =
3051 to_i915(intel_dig_port->base.base.dev);
3053 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3054 intel_dig_port->write_infoframe = vlv_write_infoframe;
3055 intel_dig_port->read_infoframe = vlv_read_infoframe;
3056 intel_dig_port->set_infoframes = vlv_set_infoframes;
3057 intel_dig_port->infoframes_enabled = vlv_infoframes_enabled;
3058 } else if (IS_G4X(dev_priv)) {
3059 intel_dig_port->write_infoframe = g4x_write_infoframe;
3060 intel_dig_port->read_infoframe = g4x_read_infoframe;
3061 intel_dig_port->set_infoframes = g4x_set_infoframes;
3062 intel_dig_port->infoframes_enabled = g4x_infoframes_enabled;
3063 } else if (HAS_DDI(dev_priv)) {
3064 if (intel_dig_port->lspcon.active) {
3065 intel_dig_port->write_infoframe = lspcon_write_infoframe;
3066 intel_dig_port->read_infoframe = lspcon_read_infoframe;
3067 intel_dig_port->set_infoframes = lspcon_set_infoframes;
3068 intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled;
3070 intel_dig_port->write_infoframe = hsw_write_infoframe;
3071 intel_dig_port->read_infoframe = hsw_read_infoframe;
3072 intel_dig_port->set_infoframes = hsw_set_infoframes;
3073 intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;
3075 } else if (HAS_PCH_IBX(dev_priv)) {
3076 intel_dig_port->write_infoframe = ibx_write_infoframe;
3077 intel_dig_port->read_infoframe = ibx_read_infoframe;
3078 intel_dig_port->set_infoframes = ibx_set_infoframes;
3079 intel_dig_port->infoframes_enabled = ibx_infoframes_enabled;
3081 intel_dig_port->write_infoframe = cpt_write_infoframe;
3082 intel_dig_port->read_infoframe = cpt_read_infoframe;
3083 intel_dig_port->set_infoframes = cpt_set_infoframes;
3084 intel_dig_port->infoframes_enabled = cpt_infoframes_enabled;
3088 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
3089 struct intel_connector *intel_connector)
3091 struct drm_connector *connector = &intel_connector->base;
3092 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3093 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3094 struct drm_device *dev = intel_encoder->base.dev;
3095 struct drm_i915_private *dev_priv = to_i915(dev);
3096 enum port port = intel_encoder->port;
3098 DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n",
3099 intel_encoder->base.base.id, intel_encoder->base.name);
3101 if (WARN(intel_dig_port->max_lanes < 4,
3102 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
3103 intel_dig_port->max_lanes, intel_encoder->base.base.id,
3104 intel_encoder->base.name))
3107 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
3108 DRM_MODE_CONNECTOR_HDMIA);
3109 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3111 connector->interlace_allowed = 1;
3112 connector->doublescan_allowed = 0;
3113 connector->stereo_allowed = 1;
3115 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3116 connector->ycbcr_420_allowed = true;
3118 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
3120 if (WARN_ON(port == PORT_A))
3122 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
3124 if (HAS_DDI(dev_priv))
3125 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3127 intel_connector->get_hw_state = intel_connector_get_hw_state;
3129 intel_hdmi_add_properties(intel_hdmi, connector);
3131 intel_connector_attach_encoder(intel_connector, intel_encoder);
3132 intel_hdmi->attached_connector = intel_connector;
3134 if (is_hdcp_supported(dev_priv, port)) {
3135 int ret = intel_hdcp_init(intel_connector,
3136 &intel_hdmi_hdcp_shim);
3138 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
3141 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3142 * 0xd. Failure to do so will result in spurious interrupts being
3143 * generated on the port when a cable is not attached.
3145 if (IS_G45(dev_priv)) {
3146 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3147 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3150 intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
3151 port_identifier(port));
3152 if (!intel_hdmi->cec_notifier)
3153 DRM_DEBUG_KMS("CEC notifier get failed\n");
3156 static enum intel_hotplug_state
3157 intel_hdmi_hotplug(struct intel_encoder *encoder,
3158 struct intel_connector *connector, bool irq_received)
3160 enum intel_hotplug_state state;
3162 state = intel_encoder_hotplug(encoder, connector, irq_received);
3165 * On many platforms the HDMI live state signal is known to be
3166 * unreliable, so we can't use it to detect if a sink is connected or
3167 * not. Instead we detect if it's connected based on whether we can
3168 * read the EDID or not. That in turn has a problem during disconnect,
3169 * since the HPD interrupt may be raised before the DDC lines get
3170 * disconnected (due to how the required length of DDC vs. HPD
3171 * connector pins are specified) and so we'll still be able to get a
3172 * valid EDID. To solve this schedule another detection cycle if this
3173 * time around we didn't detect any change in the sink's connection
3176 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
3177 state = INTEL_HOTPLUG_RETRY;
3182 void intel_hdmi_init(struct drm_i915_private *dev_priv,
3183 i915_reg_t hdmi_reg, enum port port)
3185 struct intel_digital_port *intel_dig_port;
3186 struct intel_encoder *intel_encoder;
3187 struct intel_connector *intel_connector;
3189 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3190 if (!intel_dig_port)
3193 intel_connector = intel_connector_alloc();
3194 if (!intel_connector) {
3195 kfree(intel_dig_port);
3199 intel_encoder = &intel_dig_port->base;
3201 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3202 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
3203 "HDMI %c", port_name(port));
3205 intel_encoder->hotplug = intel_hdmi_hotplug;
3206 intel_encoder->compute_config = intel_hdmi_compute_config;
3207 if (HAS_PCH_SPLIT(dev_priv)) {
3208 intel_encoder->disable = pch_disable_hdmi;
3209 intel_encoder->post_disable = pch_post_disable_hdmi;
3211 intel_encoder->disable = g4x_disable_hdmi;
3213 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
3214 intel_encoder->get_config = intel_hdmi_get_config;
3215 if (IS_CHERRYVIEW(dev_priv)) {
3216 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
3217 intel_encoder->pre_enable = chv_hdmi_pre_enable;
3218 intel_encoder->enable = vlv_enable_hdmi;
3219 intel_encoder->post_disable = chv_hdmi_post_disable;
3220 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
3221 } else if (IS_VALLEYVIEW(dev_priv)) {
3222 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
3223 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
3224 intel_encoder->enable = vlv_enable_hdmi;
3225 intel_encoder->post_disable = vlv_hdmi_post_disable;
3227 intel_encoder->pre_enable = intel_hdmi_pre_enable;
3228 if (HAS_PCH_CPT(dev_priv))
3229 intel_encoder->enable = cpt_enable_hdmi;
3230 else if (HAS_PCH_IBX(dev_priv))
3231 intel_encoder->enable = ibx_enable_hdmi;
3233 intel_encoder->enable = g4x_enable_hdmi;
3236 intel_encoder->type = INTEL_OUTPUT_HDMI;
3237 intel_encoder->power_domain = intel_port_to_power_domain(port);
3238 intel_encoder->port = port;
3239 if (IS_CHERRYVIEW(dev_priv)) {
3241 intel_encoder->crtc_mask = 1 << 2;
3243 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
3245 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3247 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
3249 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3250 * to work on real hardware. And since g4x can send infoframes to
3251 * only one port anyway, nothing is lost by allowing it.
3253 if (IS_G4X(dev_priv))
3254 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
3256 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
3257 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3258 intel_dig_port->max_lanes = 4;
3260 intel_infoframe_init(intel_dig_port);
3262 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
3263 intel_hdmi_init_connector(intel_dig_port, intel_connector);