2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/delay.h>
30 #include <linux/hdmi.h>
31 #include <linux/i2c.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_hdcp.h>
38 #include <drm/drm_scdc_helper.h>
39 #include <drm/i915_drm.h>
40 #include <drm/intel_lpe_audio.h>
42 #include "i915_debugfs.h"
44 #include "intel_atomic.h"
45 #include "intel_audio.h"
46 #include "intel_connector.h"
47 #include "intel_ddi.h"
48 #include "intel_display_types.h"
50 #include "intel_dpio_phy.h"
51 #include "intel_fifo_underrun.h"
52 #include "intel_gmbus.h"
53 #include "intel_hdcp.h"
54 #include "intel_hdmi.h"
55 #include "intel_hotplug.h"
56 #include "intel_lspcon.h"
57 #include "intel_panel.h"
58 #include "intel_sdvo.h"
59 #include "intel_sideband.h"
61 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
63 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
67 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
69 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
70 struct drm_i915_private *dev_priv = to_i915(dev);
73 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
75 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
76 "HDMI port enabled, expecting disabled\n");
80 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
81 enum transcoder cpu_transcoder)
83 WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
84 TRANS_DDI_FUNC_ENABLE,
85 "HDMI transcoder function enabled, expecting disabled\n");
88 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
90 struct intel_digital_port *intel_dig_port =
91 container_of(encoder, struct intel_digital_port, base.base);
92 return &intel_dig_port->hdmi;
95 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
97 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
100 static u32 g4x_infoframe_index(unsigned int type)
103 case HDMI_PACKET_TYPE_GAMUT_METADATA:
104 return VIDEO_DIP_SELECT_GAMUT;
105 case HDMI_INFOFRAME_TYPE_AVI:
106 return VIDEO_DIP_SELECT_AVI;
107 case HDMI_INFOFRAME_TYPE_SPD:
108 return VIDEO_DIP_SELECT_SPD;
109 case HDMI_INFOFRAME_TYPE_VENDOR:
110 return VIDEO_DIP_SELECT_VENDOR;
117 static u32 g4x_infoframe_enable(unsigned int type)
120 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
121 return VIDEO_DIP_ENABLE_GCP;
122 case HDMI_PACKET_TYPE_GAMUT_METADATA:
123 return VIDEO_DIP_ENABLE_GAMUT;
126 case HDMI_INFOFRAME_TYPE_AVI:
127 return VIDEO_DIP_ENABLE_AVI;
128 case HDMI_INFOFRAME_TYPE_SPD:
129 return VIDEO_DIP_ENABLE_SPD;
130 case HDMI_INFOFRAME_TYPE_VENDOR:
131 return VIDEO_DIP_ENABLE_VENDOR;
132 case HDMI_INFOFRAME_TYPE_DRM:
140 static u32 hsw_infoframe_enable(unsigned int type)
143 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
144 return VIDEO_DIP_ENABLE_GCP_HSW;
145 case HDMI_PACKET_TYPE_GAMUT_METADATA:
146 return VIDEO_DIP_ENABLE_GMP_HSW;
148 return VIDEO_DIP_ENABLE_VSC_HSW;
150 return VDIP_ENABLE_PPS;
151 case HDMI_INFOFRAME_TYPE_AVI:
152 return VIDEO_DIP_ENABLE_AVI_HSW;
153 case HDMI_INFOFRAME_TYPE_SPD:
154 return VIDEO_DIP_ENABLE_SPD_HSW;
155 case HDMI_INFOFRAME_TYPE_VENDOR:
156 return VIDEO_DIP_ENABLE_VS_HSW;
157 case HDMI_INFOFRAME_TYPE_DRM:
158 return VIDEO_DIP_ENABLE_DRM_GLK;
166 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
167 enum transcoder cpu_transcoder,
172 case HDMI_PACKET_TYPE_GAMUT_METADATA:
173 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
175 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
177 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
178 case HDMI_INFOFRAME_TYPE_AVI:
179 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
180 case HDMI_INFOFRAME_TYPE_SPD:
181 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
182 case HDMI_INFOFRAME_TYPE_VENDOR:
183 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
184 case HDMI_INFOFRAME_TYPE_DRM:
185 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
188 return INVALID_MMIO_REG;
192 static int hsw_dip_data_size(unsigned int type)
196 return VIDEO_DIP_VSC_DATA_SIZE;
198 return VIDEO_DIP_PPS_DATA_SIZE;
200 return VIDEO_DIP_DATA_SIZE;
204 static void g4x_write_infoframe(struct intel_encoder *encoder,
205 const struct intel_crtc_state *crtc_state,
207 const void *frame, ssize_t len)
209 const u32 *data = frame;
210 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
211 u32 val = I915_READ(VIDEO_DIP_CTL);
214 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
216 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
217 val |= g4x_infoframe_index(type);
219 val &= ~g4x_infoframe_enable(type);
221 I915_WRITE(VIDEO_DIP_CTL, val);
223 for (i = 0; i < len; i += 4) {
224 I915_WRITE(VIDEO_DIP_DATA, *data);
227 /* Write every possible data byte to force correct ECC calculation. */
228 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
229 I915_WRITE(VIDEO_DIP_DATA, 0);
231 val |= g4x_infoframe_enable(type);
232 val &= ~VIDEO_DIP_FREQ_MASK;
233 val |= VIDEO_DIP_FREQ_VSYNC;
235 I915_WRITE(VIDEO_DIP_CTL, val);
236 POSTING_READ(VIDEO_DIP_CTL);
239 static void g4x_read_infoframe(struct intel_encoder *encoder,
240 const struct intel_crtc_state *crtc_state,
242 void *frame, ssize_t len)
244 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
245 u32 val, *data = frame;
248 val = I915_READ(VIDEO_DIP_CTL);
250 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
251 val |= g4x_infoframe_index(type);
253 I915_WRITE(VIDEO_DIP_CTL, val);
255 for (i = 0; i < len; i += 4)
256 *data++ = I915_READ(VIDEO_DIP_DATA);
259 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
260 const struct intel_crtc_state *pipe_config)
262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
263 u32 val = I915_READ(VIDEO_DIP_CTL);
265 if ((val & VIDEO_DIP_ENABLE) == 0)
268 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
271 return val & (VIDEO_DIP_ENABLE_AVI |
272 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
275 static void ibx_write_infoframe(struct intel_encoder *encoder,
276 const struct intel_crtc_state *crtc_state,
278 const void *frame, ssize_t len)
280 const u32 *data = frame;
281 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
283 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
284 u32 val = I915_READ(reg);
287 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
289 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
290 val |= g4x_infoframe_index(type);
292 val &= ~g4x_infoframe_enable(type);
294 I915_WRITE(reg, val);
296 for (i = 0; i < len; i += 4) {
297 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
300 /* Write every possible data byte to force correct ECC calculation. */
301 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
302 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
304 val |= g4x_infoframe_enable(type);
305 val &= ~VIDEO_DIP_FREQ_MASK;
306 val |= VIDEO_DIP_FREQ_VSYNC;
308 I915_WRITE(reg, val);
312 static void ibx_read_infoframe(struct intel_encoder *encoder,
313 const struct intel_crtc_state *crtc_state,
315 void *frame, ssize_t len)
317 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
318 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
319 u32 val, *data = frame;
322 val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
324 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
325 val |= g4x_infoframe_index(type);
327 I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
329 for (i = 0; i < len; i += 4)
330 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
333 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
334 const struct intel_crtc_state *pipe_config)
336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
337 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
338 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
339 u32 val = I915_READ(reg);
341 if ((val & VIDEO_DIP_ENABLE) == 0)
344 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
347 return val & (VIDEO_DIP_ENABLE_AVI |
348 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
349 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
352 static void cpt_write_infoframe(struct intel_encoder *encoder,
353 const struct intel_crtc_state *crtc_state,
355 const void *frame, ssize_t len)
357 const u32 *data = frame;
358 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
360 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
361 u32 val = I915_READ(reg);
364 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
366 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
367 val |= g4x_infoframe_index(type);
369 /* The DIP control register spec says that we need to update the AVI
370 * infoframe without clearing its enable bit */
371 if (type != HDMI_INFOFRAME_TYPE_AVI)
372 val &= ~g4x_infoframe_enable(type);
374 I915_WRITE(reg, val);
376 for (i = 0; i < len; i += 4) {
377 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
380 /* Write every possible data byte to force correct ECC calculation. */
381 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
382 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
384 val |= g4x_infoframe_enable(type);
385 val &= ~VIDEO_DIP_FREQ_MASK;
386 val |= VIDEO_DIP_FREQ_VSYNC;
388 I915_WRITE(reg, val);
392 static void cpt_read_infoframe(struct intel_encoder *encoder,
393 const struct intel_crtc_state *crtc_state,
395 void *frame, ssize_t len)
397 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
398 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
399 u32 val, *data = frame;
402 val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe));
404 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
405 val |= g4x_infoframe_index(type);
407 I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val);
409 for (i = 0; i < len; i += 4)
410 *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe));
413 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
414 const struct intel_crtc_state *pipe_config)
416 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
417 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
418 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
420 if ((val & VIDEO_DIP_ENABLE) == 0)
423 return val & (VIDEO_DIP_ENABLE_AVI |
424 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
425 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
428 static void vlv_write_infoframe(struct intel_encoder *encoder,
429 const struct intel_crtc_state *crtc_state,
431 const void *frame, ssize_t len)
433 const u32 *data = frame;
434 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
436 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
437 u32 val = I915_READ(reg);
440 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
442 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
443 val |= g4x_infoframe_index(type);
445 val &= ~g4x_infoframe_enable(type);
447 I915_WRITE(reg, val);
449 for (i = 0; i < len; i += 4) {
450 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
453 /* Write every possible data byte to force correct ECC calculation. */
454 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
455 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
457 val |= g4x_infoframe_enable(type);
458 val &= ~VIDEO_DIP_FREQ_MASK;
459 val |= VIDEO_DIP_FREQ_VSYNC;
461 I915_WRITE(reg, val);
465 static void vlv_read_infoframe(struct intel_encoder *encoder,
466 const struct intel_crtc_state *crtc_state,
468 void *frame, ssize_t len)
470 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
471 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
472 u32 val, *data = frame;
475 val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe));
477 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
478 val |= g4x_infoframe_index(type);
480 I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
482 for (i = 0; i < len; i += 4)
483 *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe));
486 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
487 const struct intel_crtc_state *pipe_config)
489 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
490 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
491 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
493 if ((val & VIDEO_DIP_ENABLE) == 0)
496 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
499 return val & (VIDEO_DIP_ENABLE_AVI |
500 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
501 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
504 static void hsw_write_infoframe(struct intel_encoder *encoder,
505 const struct intel_crtc_state *crtc_state,
507 const void *frame, ssize_t len)
509 const u32 *data = frame;
510 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
511 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
512 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
515 u32 val = I915_READ(ctl_reg);
517 data_size = hsw_dip_data_size(type);
519 val &= ~hsw_infoframe_enable(type);
520 I915_WRITE(ctl_reg, val);
522 for (i = 0; i < len; i += 4) {
523 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
524 type, i >> 2), *data);
527 /* Write every possible data byte to force correct ECC calculation. */
528 for (; i < data_size; i += 4)
529 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
532 val |= hsw_infoframe_enable(type);
533 I915_WRITE(ctl_reg, val);
534 POSTING_READ(ctl_reg);
537 static void hsw_read_infoframe(struct intel_encoder *encoder,
538 const struct intel_crtc_state *crtc_state,
540 void *frame, ssize_t len)
542 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
543 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
544 u32 val, *data = frame;
547 val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder));
549 for (i = 0; i < len; i += 4)
550 *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder,
554 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
555 const struct intel_crtc_state *pipe_config)
557 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
558 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
561 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
562 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
563 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
565 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
566 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
571 static const u8 infoframe_type_to_idx[] = {
572 HDMI_PACKET_TYPE_GENERAL_CONTROL,
573 HDMI_PACKET_TYPE_GAMUT_METADATA,
575 HDMI_INFOFRAME_TYPE_AVI,
576 HDMI_INFOFRAME_TYPE_SPD,
577 HDMI_INFOFRAME_TYPE_VENDOR,
578 HDMI_INFOFRAME_TYPE_DRM,
581 u32 intel_hdmi_infoframe_enable(unsigned int type)
585 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
586 if (infoframe_type_to_idx[i] == type)
593 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
594 const struct intel_crtc_state *crtc_state)
596 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
597 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
601 val = dig_port->infoframes_enabled(encoder, crtc_state);
603 /* map from hardware bits to dip idx */
604 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
605 unsigned int type = infoframe_type_to_idx[i];
607 if (HAS_DDI(dev_priv)) {
608 if (val & hsw_infoframe_enable(type))
611 if (val & g4x_infoframe_enable(type))
620 * The data we write to the DIP data buffer registers is 1 byte bigger than the
621 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
622 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
623 * used for both technologies.
625 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
626 * DW1: DB3 | DB2 | DB1 | DB0
627 * DW2: DB7 | DB6 | DB5 | DB4
630 * (HB is Header Byte, DB is Data Byte)
632 * The hdmi pack() functions don't know about that hardware specific hole so we
633 * trick them by giving an offset into the buffer and moving back the header
636 static void intel_write_infoframe(struct intel_encoder *encoder,
637 const struct intel_crtc_state *crtc_state,
638 enum hdmi_infoframe_type type,
639 const union hdmi_infoframe *frame)
641 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
642 u8 buffer[VIDEO_DIP_DATA_SIZE];
645 if ((crtc_state->infoframes.enable &
646 intel_hdmi_infoframe_enable(type)) == 0)
649 if (WARN_ON(frame->any.type != type))
652 /* see comment above for the reason for this offset */
653 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
654 if (WARN_ON(len < 0))
657 /* Insert the 'hole' (see big comment above) at position 3 */
658 memmove(&buffer[0], &buffer[1], 3);
662 intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
665 void intel_read_infoframe(struct intel_encoder *encoder,
666 const struct intel_crtc_state *crtc_state,
667 enum hdmi_infoframe_type type,
668 union hdmi_infoframe *frame)
670 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
671 u8 buffer[VIDEO_DIP_DATA_SIZE];
674 if ((crtc_state->infoframes.enable &
675 intel_hdmi_infoframe_enable(type)) == 0)
678 intel_dig_port->read_infoframe(encoder, crtc_state,
679 type, buffer, sizeof(buffer));
681 /* Fill the 'hole' (see big comment above) at position 3 */
682 memmove(&buffer[1], &buffer[0], 3);
684 /* see comment above for the reason for this offset */
685 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
687 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type);
691 if (frame->any.type != type)
692 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
693 frame->any.type, type);
697 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
698 struct intel_crtc_state *crtc_state,
699 struct drm_connector_state *conn_state)
701 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
702 const struct drm_display_mode *adjusted_mode =
703 &crtc_state->base.adjusted_mode;
704 struct drm_connector *connector = conn_state->connector;
707 if (!crtc_state->has_infoframe)
710 crtc_state->infoframes.enable |=
711 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
713 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
718 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
719 frame->colorspace = HDMI_COLORSPACE_YUV420;
720 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
721 frame->colorspace = HDMI_COLORSPACE_YUV444;
723 frame->colorspace = HDMI_COLORSPACE_RGB;
725 drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
727 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
728 drm_hdmi_avi_infoframe_quant_range(frame, connector,
730 crtc_state->limited_color_range ?
731 HDMI_QUANTIZATION_RANGE_LIMITED :
732 HDMI_QUANTIZATION_RANGE_FULL);
734 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
735 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
738 drm_hdmi_avi_infoframe_content_type(frame, conn_state);
740 /* TODO: handle pixel repetition for YCBCR420 outputs */
742 ret = hdmi_avi_infoframe_check(frame);
750 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
751 struct intel_crtc_state *crtc_state,
752 struct drm_connector_state *conn_state)
754 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
757 if (!crtc_state->has_infoframe)
760 crtc_state->infoframes.enable |=
761 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
763 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
767 frame->sdi = HDMI_SPD_SDI_PC;
769 ret = hdmi_spd_infoframe_check(frame);
777 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
778 struct intel_crtc_state *crtc_state,
779 struct drm_connector_state *conn_state)
781 struct hdmi_vendor_infoframe *frame =
782 &crtc_state->infoframes.hdmi.vendor.hdmi;
783 const struct drm_display_info *info =
784 &conn_state->connector->display_info;
787 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
790 crtc_state->infoframes.enable |=
791 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
793 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
794 conn_state->connector,
795 &crtc_state->base.adjusted_mode);
799 ret = hdmi_vendor_infoframe_check(frame);
807 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
808 struct intel_crtc_state *crtc_state,
809 struct drm_connector_state *conn_state)
811 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
812 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
815 if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
818 if (!crtc_state->has_infoframe)
821 if (!conn_state->hdr_output_metadata)
824 crtc_state->infoframes.enable |=
825 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
827 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
829 DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n");
833 ret = hdmi_drm_infoframe_check(frame);
840 static void g4x_set_infoframes(struct intel_encoder *encoder,
842 const struct intel_crtc_state *crtc_state,
843 const struct drm_connector_state *conn_state)
845 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
846 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
847 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
848 i915_reg_t reg = VIDEO_DIP_CTL;
849 u32 val = I915_READ(reg);
850 u32 port = VIDEO_DIP_PORT(encoder->port);
852 assert_hdmi_port_disabled(intel_hdmi);
854 /* If the registers were not initialized yet, they might be zeroes,
855 * which means we're selecting the AVI DIP and we're setting its
856 * frequency to once. This seems to really confuse the HW and make
857 * things stop working (the register spec says the AVI always needs to
858 * be sent every VSync). So here we avoid writing to the register more
859 * than we need and also explicitly select the AVI DIP and explicitly
860 * set its frequency to every VSync. Avoiding to write it twice seems to
861 * be enough to solve the problem, but being defensive shouldn't hurt us
863 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
866 if (!(val & VIDEO_DIP_ENABLE))
868 if (port != (val & VIDEO_DIP_PORT_MASK)) {
869 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
870 (val & VIDEO_DIP_PORT_MASK) >> 29);
873 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
874 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
875 I915_WRITE(reg, val);
880 if (port != (val & VIDEO_DIP_PORT_MASK)) {
881 if (val & VIDEO_DIP_ENABLE) {
882 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
883 (val & VIDEO_DIP_PORT_MASK) >> 29);
886 val &= ~VIDEO_DIP_PORT_MASK;
890 val |= VIDEO_DIP_ENABLE;
891 val &= ~(VIDEO_DIP_ENABLE_AVI |
892 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
894 I915_WRITE(reg, val);
897 intel_write_infoframe(encoder, crtc_state,
898 HDMI_INFOFRAME_TYPE_AVI,
899 &crtc_state->infoframes.avi);
900 intel_write_infoframe(encoder, crtc_state,
901 HDMI_INFOFRAME_TYPE_SPD,
902 &crtc_state->infoframes.spd);
903 intel_write_infoframe(encoder, crtc_state,
904 HDMI_INFOFRAME_TYPE_VENDOR,
905 &crtc_state->infoframes.hdmi);
909 * Determine if default_phase=1 can be indicated in the GCP infoframe.
911 * From HDMI specification 1.4a:
912 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
913 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
914 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
915 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
918 static bool gcp_default_phase_possible(int pipe_bpp,
919 const struct drm_display_mode *mode)
921 unsigned int pixels_per_group;
925 /* 4 pixels in 5 clocks */
926 pixels_per_group = 4;
929 /* 2 pixels in 3 clocks */
930 pixels_per_group = 2;
933 /* 1 pixel in 2 clocks */
934 pixels_per_group = 1;
937 /* phase information not relevant for 8bpc */
941 return mode->crtc_hdisplay % pixels_per_group == 0 &&
942 mode->crtc_htotal % pixels_per_group == 0 &&
943 mode->crtc_hblank_start % pixels_per_group == 0 &&
944 mode->crtc_hblank_end % pixels_per_group == 0 &&
945 mode->crtc_hsync_start % pixels_per_group == 0 &&
946 mode->crtc_hsync_end % pixels_per_group == 0 &&
947 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
948 mode->crtc_htotal/2 % pixels_per_group == 0);
951 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
952 const struct intel_crtc_state *crtc_state,
953 const struct drm_connector_state *conn_state)
955 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
956 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
959 if ((crtc_state->infoframes.enable &
960 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
963 if (HAS_DDI(dev_priv))
964 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
965 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
966 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
967 else if (HAS_PCH_SPLIT(dev_priv))
968 reg = TVIDEO_DIP_GCP(crtc->pipe);
972 I915_WRITE(reg, crtc_state->infoframes.gcp);
977 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
978 struct intel_crtc_state *crtc_state)
980 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
981 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
984 if ((crtc_state->infoframes.enable &
985 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
988 if (HAS_DDI(dev_priv))
989 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
990 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
991 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
992 else if (HAS_PCH_SPLIT(dev_priv))
993 reg = TVIDEO_DIP_GCP(crtc->pipe);
997 crtc_state->infoframes.gcp = I915_READ(reg);
1000 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1001 struct intel_crtc_state *crtc_state,
1002 struct drm_connector_state *conn_state)
1004 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1006 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1009 crtc_state->infoframes.enable |=
1010 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1012 /* Indicate color indication for deep color mode */
1013 if (crtc_state->pipe_bpp > 24)
1014 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1016 /* Enable default_phase whenever the display mode is suitably aligned */
1017 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1018 &crtc_state->base.adjusted_mode))
1019 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1022 static void ibx_set_infoframes(struct intel_encoder *encoder,
1024 const struct intel_crtc_state *crtc_state,
1025 const struct drm_connector_state *conn_state)
1027 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1029 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
1030 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1031 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1032 u32 val = I915_READ(reg);
1033 u32 port = VIDEO_DIP_PORT(encoder->port);
1035 assert_hdmi_port_disabled(intel_hdmi);
1037 /* See the big comment in g4x_set_infoframes() */
1038 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1041 if (!(val & VIDEO_DIP_ENABLE))
1043 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1044 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1045 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1046 I915_WRITE(reg, val);
1051 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1052 WARN(val & VIDEO_DIP_ENABLE,
1053 "DIP already enabled on port %c\n",
1054 (val & VIDEO_DIP_PORT_MASK) >> 29);
1055 val &= ~VIDEO_DIP_PORT_MASK;
1059 val |= VIDEO_DIP_ENABLE;
1060 val &= ~(VIDEO_DIP_ENABLE_AVI |
1061 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1062 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1064 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1065 val |= VIDEO_DIP_ENABLE_GCP;
1067 I915_WRITE(reg, val);
1070 intel_write_infoframe(encoder, crtc_state,
1071 HDMI_INFOFRAME_TYPE_AVI,
1072 &crtc_state->infoframes.avi);
1073 intel_write_infoframe(encoder, crtc_state,
1074 HDMI_INFOFRAME_TYPE_SPD,
1075 &crtc_state->infoframes.spd);
1076 intel_write_infoframe(encoder, crtc_state,
1077 HDMI_INFOFRAME_TYPE_VENDOR,
1078 &crtc_state->infoframes.hdmi);
1081 static void cpt_set_infoframes(struct intel_encoder *encoder,
1083 const struct intel_crtc_state *crtc_state,
1084 const struct drm_connector_state *conn_state)
1086 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1088 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1089 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1090 u32 val = I915_READ(reg);
1092 assert_hdmi_port_disabled(intel_hdmi);
1094 /* See the big comment in g4x_set_infoframes() */
1095 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1098 if (!(val & VIDEO_DIP_ENABLE))
1100 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1101 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1102 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1103 I915_WRITE(reg, val);
1108 /* Set both together, unset both together: see the spec. */
1109 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1110 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1111 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1113 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1114 val |= VIDEO_DIP_ENABLE_GCP;
1116 I915_WRITE(reg, val);
1119 intel_write_infoframe(encoder, crtc_state,
1120 HDMI_INFOFRAME_TYPE_AVI,
1121 &crtc_state->infoframes.avi);
1122 intel_write_infoframe(encoder, crtc_state,
1123 HDMI_INFOFRAME_TYPE_SPD,
1124 &crtc_state->infoframes.spd);
1125 intel_write_infoframe(encoder, crtc_state,
1126 HDMI_INFOFRAME_TYPE_VENDOR,
1127 &crtc_state->infoframes.hdmi);
1130 static void vlv_set_infoframes(struct intel_encoder *encoder,
1132 const struct intel_crtc_state *crtc_state,
1133 const struct drm_connector_state *conn_state)
1135 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
1137 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1138 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1139 u32 val = I915_READ(reg);
1140 u32 port = VIDEO_DIP_PORT(encoder->port);
1142 assert_hdmi_port_disabled(intel_hdmi);
1144 /* See the big comment in g4x_set_infoframes() */
1145 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1148 if (!(val & VIDEO_DIP_ENABLE))
1150 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1151 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1152 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1153 I915_WRITE(reg, val);
1158 if (port != (val & VIDEO_DIP_PORT_MASK)) {
1159 WARN(val & VIDEO_DIP_ENABLE,
1160 "DIP already enabled on port %c\n",
1161 (val & VIDEO_DIP_PORT_MASK) >> 29);
1162 val &= ~VIDEO_DIP_PORT_MASK;
1166 val |= VIDEO_DIP_ENABLE;
1167 val &= ~(VIDEO_DIP_ENABLE_AVI |
1168 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1169 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1171 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1172 val |= VIDEO_DIP_ENABLE_GCP;
1174 I915_WRITE(reg, val);
1177 intel_write_infoframe(encoder, crtc_state,
1178 HDMI_INFOFRAME_TYPE_AVI,
1179 &crtc_state->infoframes.avi);
1180 intel_write_infoframe(encoder, crtc_state,
1181 HDMI_INFOFRAME_TYPE_SPD,
1182 &crtc_state->infoframes.spd);
1183 intel_write_infoframe(encoder, crtc_state,
1184 HDMI_INFOFRAME_TYPE_VENDOR,
1185 &crtc_state->infoframes.hdmi);
1188 static void hsw_set_infoframes(struct intel_encoder *encoder,
1190 const struct intel_crtc_state *crtc_state,
1191 const struct drm_connector_state *conn_state)
1193 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1194 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1195 u32 val = I915_READ(reg);
1197 assert_hdmi_transcoder_func_disabled(dev_priv,
1198 crtc_state->cpu_transcoder);
1200 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1201 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1202 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1203 VIDEO_DIP_ENABLE_DRM_GLK);
1206 I915_WRITE(reg, val);
1211 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1212 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1214 I915_WRITE(reg, val);
1217 intel_write_infoframe(encoder, crtc_state,
1218 HDMI_INFOFRAME_TYPE_AVI,
1219 &crtc_state->infoframes.avi);
1220 intel_write_infoframe(encoder, crtc_state,
1221 HDMI_INFOFRAME_TYPE_SPD,
1222 &crtc_state->infoframes.spd);
1223 intel_write_infoframe(encoder, crtc_state,
1224 HDMI_INFOFRAME_TYPE_VENDOR,
1225 &crtc_state->infoframes.hdmi);
1226 intel_write_infoframe(encoder, crtc_state,
1227 HDMI_INFOFRAME_TYPE_DRM,
1228 &crtc_state->infoframes.drm);
1231 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1233 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1234 struct i2c_adapter *adapter =
1235 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1237 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1240 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
1241 enable ? "Enabling" : "Disabling");
1243 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
1247 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
1248 unsigned int offset, void *buffer, size_t size)
1250 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1251 struct drm_i915_private *dev_priv =
1252 intel_dig_port->base.base.dev->dev_private;
1253 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1256 u8 start = offset & 0xff;
1257 struct i2c_msg msgs[] = {
1259 .addr = DRM_HDCP_DDC_ADDR,
1265 .addr = DRM_HDCP_DDC_ADDR,
1271 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1272 if (ret == ARRAY_SIZE(msgs))
1274 return ret >= 0 ? -EIO : ret;
1277 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
1278 unsigned int offset, void *buffer, size_t size)
1280 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1281 struct drm_i915_private *dev_priv =
1282 intel_dig_port->base.base.dev->dev_private;
1283 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1289 write_buf = kzalloc(size + 1, GFP_KERNEL);
1293 write_buf[0] = offset & 0xff;
1294 memcpy(&write_buf[1], buffer, size);
1296 msg.addr = DRM_HDCP_DDC_ADDR;
1299 msg.buf = write_buf;
1301 ret = i2c_transfer(adapter, &msg, 1);
1312 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
1315 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1316 struct drm_i915_private *dev_priv =
1317 intel_dig_port->base.base.dev->dev_private;
1318 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1322 ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
1325 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
1329 ret = intel_gmbus_output_aksv(adapter);
1331 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
1337 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
1341 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
1344 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
1349 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1353 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1354 bstatus, DRM_HDCP_BSTATUS_LEN);
1356 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
1361 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1362 bool *repeater_present)
1367 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1369 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1372 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1377 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1381 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1382 ri_prime, DRM_HDCP_RI_LEN);
1384 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
1389 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1395 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1397 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
1400 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1405 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1406 int num_downstream, u8 *ksv_fifo)
1409 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1410 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1412 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
1419 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1424 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1427 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1428 part, DRM_HDCP_V_PRIME_PART_LEN);
1430 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
1434 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector)
1436 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1437 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
1438 struct drm_crtc *crtc = connector->base.state->crtc;
1439 struct intel_crtc *intel_crtc = container_of(crtc,
1440 struct intel_crtc, base);
1445 scanline = I915_READ(PIPEDSL(intel_crtc->pipe));
1446 if (scanline > 100 && scanline < 200)
1448 usleep_range(25, 50);
1451 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false);
1453 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret);
1456 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true);
1458 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret);
1466 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1469 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1470 struct intel_connector *connector = hdmi->attached_connector;
1471 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1475 usleep_range(6, 60); /* Bspec says >= 6us */
1477 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1479 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1480 enable ? "Enable" : "Disable", ret);
1485 * WA: To fix incorrect positioning of the window of
1486 * opportunity and enc_en signalling in KABYLAKE.
1488 if (IS_KABYLAKE(dev_priv) && enable)
1489 return kbl_repositioning_enc_en_signal(connector);
1495 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1497 struct drm_i915_private *dev_priv =
1498 intel_dig_port->base.base.dev->dev_private;
1499 struct intel_connector *connector =
1500 intel_dig_port->hdmi.attached_connector;
1501 enum port port = intel_dig_port->base.port;
1502 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1506 u8 shim[DRM_HDCP_RI_LEN];
1509 ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1513 I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg);
1515 /* Wait for Ri prime match */
1516 if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) &
1517 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1518 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1519 I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder,
1526 struct hdcp2_hdmi_msg_data {
1532 static const struct hdcp2_hdmi_msg_data hdcp2_msg_data[] = {
1533 { HDCP_2_2_AKE_INIT, 0, 0 },
1534 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
1535 { HDCP_2_2_AKE_NO_STORED_KM, 0, 0 },
1536 { HDCP_2_2_AKE_STORED_KM, 0, 0 },
1537 { HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
1538 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
1539 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
1540 { HDCP_2_2_LC_INIT, 0, 0 },
1541 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0 },
1542 { HDCP_2_2_SKE_SEND_EKS, 0, 0 },
1543 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
1544 { HDCP_2_2_REP_SEND_ACK, 0, 0 },
1545 { HDCP_2_2_REP_STREAM_MANAGE, 0, 0 },
1546 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
1550 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
1553 return intel_hdmi_hdcp_read(intel_dig_port,
1554 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1556 HDCP_2_2_HDMI_RXSTATUS_LEN);
1559 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1563 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++)
1564 if (hdcp2_msg_data[i].msg_id == msg_id &&
1565 (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired))
1566 return hdcp2_msg_data[i].timeout;
1567 else if (hdcp2_msg_data[i].msg_id == msg_id)
1568 return hdcp2_msg_data[i].timeout2;
1574 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port,
1575 u8 msg_id, bool *msg_ready,
1578 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1581 ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status);
1583 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
1587 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1590 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1591 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1594 *msg_ready = *msg_sz;
1600 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
1601 u8 msg_id, bool paired)
1603 bool msg_ready = false;
1607 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1611 ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
1614 !ret && msg_ready && msg_sz, timeout * 1000,
1617 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n",
1618 msg_id, ret, timeout);
1620 return ret ? ret : msg_sz;
1624 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
1625 void *buf, size_t size)
1627 unsigned int offset;
1629 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1630 return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
1634 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
1635 u8 msg_id, void *buf, size_t size)
1637 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1638 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1639 unsigned int offset;
1642 ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id,
1648 * Available msg size should be equal to or lesser than the
1652 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n",
1657 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1658 ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret);
1660 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret);
1666 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
1668 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1671 ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status);
1676 * Re-auth request and Link Integrity Failures are represented by
1677 * same bit. i.e reauth_req.
1679 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1680 ret = HDCP_REAUTH_REQUEST;
1681 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1682 ret = HDCP_TOPOLOGY_CHANGE;
1688 int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port,
1695 ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1696 &hdcp2_version, sizeof(hdcp2_version));
1697 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1704 enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void)
1706 return HDCP_PROTOCOL_HDMI;
1709 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1710 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1711 .read_bksv = intel_hdmi_hdcp_read_bksv,
1712 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1713 .repeater_present = intel_hdmi_hdcp_repeater_present,
1714 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1715 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1716 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1717 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1718 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1719 .check_link = intel_hdmi_hdcp_check_link,
1720 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1721 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1722 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1723 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1724 .protocol = HDCP_PROTOCOL_HDMI,
1727 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1728 const struct intel_crtc_state *crtc_state)
1730 struct drm_device *dev = encoder->base.dev;
1731 struct drm_i915_private *dev_priv = to_i915(dev);
1732 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1733 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1734 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1737 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1739 hdmi_val = SDVO_ENCODING_HDMI;
1740 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1741 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1742 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1743 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1744 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1745 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1747 if (crtc_state->pipe_bpp > 24)
1748 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1750 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1752 if (crtc_state->has_hdmi_sink)
1753 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1755 if (HAS_PCH_CPT(dev_priv))
1756 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1757 else if (IS_CHERRYVIEW(dev_priv))
1758 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1760 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1762 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1763 POSTING_READ(intel_hdmi->hdmi_reg);
1766 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1769 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1770 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1771 intel_wakeref_t wakeref;
1774 wakeref = intel_display_power_get_if_enabled(dev_priv,
1775 encoder->power_domain);
1779 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1781 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1786 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1787 struct intel_crtc_state *pipe_config)
1789 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1790 struct drm_device *dev = encoder->base.dev;
1791 struct drm_i915_private *dev_priv = to_i915(dev);
1795 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1797 tmp = I915_READ(intel_hdmi->hdmi_reg);
1799 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1800 flags |= DRM_MODE_FLAG_PHSYNC;
1802 flags |= DRM_MODE_FLAG_NHSYNC;
1804 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1805 flags |= DRM_MODE_FLAG_PVSYNC;
1807 flags |= DRM_MODE_FLAG_NVSYNC;
1809 if (tmp & HDMI_MODE_SELECT_HDMI)
1810 pipe_config->has_hdmi_sink = true;
1812 pipe_config->infoframes.enable |=
1813 intel_hdmi_infoframes_enabled(encoder, pipe_config);
1815 if (pipe_config->infoframes.enable)
1816 pipe_config->has_infoframe = true;
1818 if (tmp & HDMI_AUDIO_ENABLE)
1819 pipe_config->has_audio = true;
1821 if (!HAS_PCH_SPLIT(dev_priv) &&
1822 tmp & HDMI_COLOR_RANGE_16_235)
1823 pipe_config->limited_color_range = true;
1825 pipe_config->base.adjusted_mode.flags |= flags;
1827 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1828 dotclock = pipe_config->port_clock * 2 / 3;
1830 dotclock = pipe_config->port_clock;
1832 if (pipe_config->pixel_multiplier)
1833 dotclock /= pipe_config->pixel_multiplier;
1835 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1837 pipe_config->lane_count = 4;
1839 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
1841 intel_read_infoframe(encoder, pipe_config,
1842 HDMI_INFOFRAME_TYPE_AVI,
1843 &pipe_config->infoframes.avi);
1844 intel_read_infoframe(encoder, pipe_config,
1845 HDMI_INFOFRAME_TYPE_SPD,
1846 &pipe_config->infoframes.spd);
1847 intel_read_infoframe(encoder, pipe_config,
1848 HDMI_INFOFRAME_TYPE_VENDOR,
1849 &pipe_config->infoframes.hdmi);
1852 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1853 const struct intel_crtc_state *pipe_config,
1854 const struct drm_connector_state *conn_state)
1856 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1858 WARN_ON(!pipe_config->has_hdmi_sink);
1859 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1860 pipe_name(crtc->pipe));
1861 intel_audio_codec_enable(encoder, pipe_config, conn_state);
1864 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1865 const struct intel_crtc_state *pipe_config,
1866 const struct drm_connector_state *conn_state)
1868 struct drm_device *dev = encoder->base.dev;
1869 struct drm_i915_private *dev_priv = to_i915(dev);
1870 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1873 temp = I915_READ(intel_hdmi->hdmi_reg);
1875 temp |= SDVO_ENABLE;
1876 if (pipe_config->has_audio)
1877 temp |= HDMI_AUDIO_ENABLE;
1879 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1880 POSTING_READ(intel_hdmi->hdmi_reg);
1882 if (pipe_config->has_audio)
1883 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1886 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1887 const struct intel_crtc_state *pipe_config,
1888 const struct drm_connector_state *conn_state)
1890 struct drm_device *dev = encoder->base.dev;
1891 struct drm_i915_private *dev_priv = to_i915(dev);
1892 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1895 temp = I915_READ(intel_hdmi->hdmi_reg);
1897 temp |= SDVO_ENABLE;
1898 if (pipe_config->has_audio)
1899 temp |= HDMI_AUDIO_ENABLE;
1902 * HW workaround, need to write this twice for issue
1903 * that may result in first write getting masked.
1905 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1906 POSTING_READ(intel_hdmi->hdmi_reg);
1907 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1908 POSTING_READ(intel_hdmi->hdmi_reg);
1911 * HW workaround, need to toggle enable bit off and on
1912 * for 12bpc with pixel repeat.
1914 * FIXME: BSpec says this should be done at the end of
1915 * of the modeset sequence, so not sure if this isn't too soon.
1917 if (pipe_config->pipe_bpp > 24 &&
1918 pipe_config->pixel_multiplier > 1) {
1919 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1920 POSTING_READ(intel_hdmi->hdmi_reg);
1923 * HW workaround, need to write this twice for issue
1924 * that may result in first write getting masked.
1926 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1927 POSTING_READ(intel_hdmi->hdmi_reg);
1928 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1929 POSTING_READ(intel_hdmi->hdmi_reg);
1932 if (pipe_config->has_audio)
1933 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1936 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1937 const struct intel_crtc_state *pipe_config,
1938 const struct drm_connector_state *conn_state)
1940 struct drm_device *dev = encoder->base.dev;
1941 struct drm_i915_private *dev_priv = to_i915(dev);
1942 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1943 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1944 enum pipe pipe = crtc->pipe;
1947 temp = I915_READ(intel_hdmi->hdmi_reg);
1949 temp |= SDVO_ENABLE;
1950 if (pipe_config->has_audio)
1951 temp |= HDMI_AUDIO_ENABLE;
1954 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1956 * The procedure for 12bpc is as follows:
1957 * 1. disable HDMI clock gating
1958 * 2. enable HDMI with 8bpc
1959 * 3. enable HDMI with 12bpc
1960 * 4. enable HDMI clock gating
1963 if (pipe_config->pipe_bpp > 24) {
1964 I915_WRITE(TRANS_CHICKEN1(pipe),
1965 I915_READ(TRANS_CHICKEN1(pipe)) |
1966 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1968 temp &= ~SDVO_COLOR_FORMAT_MASK;
1969 temp |= SDVO_COLOR_FORMAT_8bpc;
1972 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1973 POSTING_READ(intel_hdmi->hdmi_reg);
1975 if (pipe_config->pipe_bpp > 24) {
1976 temp &= ~SDVO_COLOR_FORMAT_MASK;
1977 temp |= HDMI_COLOR_FORMAT_12bpc;
1979 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1980 POSTING_READ(intel_hdmi->hdmi_reg);
1982 I915_WRITE(TRANS_CHICKEN1(pipe),
1983 I915_READ(TRANS_CHICKEN1(pipe)) &
1984 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1987 if (pipe_config->has_audio)
1988 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1991 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1992 const struct intel_crtc_state *pipe_config,
1993 const struct drm_connector_state *conn_state)
1997 static void intel_disable_hdmi(struct intel_encoder *encoder,
1998 const struct intel_crtc_state *old_crtc_state,
1999 const struct drm_connector_state *old_conn_state)
2001 struct drm_device *dev = encoder->base.dev;
2002 struct drm_i915_private *dev_priv = to_i915(dev);
2003 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2004 struct intel_digital_port *intel_dig_port =
2005 hdmi_to_dig_port(intel_hdmi);
2006 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2009 temp = I915_READ(intel_hdmi->hdmi_reg);
2011 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
2012 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2013 POSTING_READ(intel_hdmi->hdmi_reg);
2016 * HW workaround for IBX, we need to move the port
2017 * to transcoder A after disabling it to allow the
2018 * matching DP port to be enabled on transcoder A.
2020 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
2022 * We get CPU/PCH FIFO underruns on the other pipe when
2023 * doing the workaround. Sweep them under the rug.
2025 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2026 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2028 temp &= ~SDVO_PIPE_SEL_MASK;
2029 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
2031 * HW workaround, need to write this twice for issue
2032 * that may result in first write getting masked.
2034 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2035 POSTING_READ(intel_hdmi->hdmi_reg);
2036 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2037 POSTING_READ(intel_hdmi->hdmi_reg);
2039 temp &= ~SDVO_ENABLE;
2040 I915_WRITE(intel_hdmi->hdmi_reg, temp);
2041 POSTING_READ(intel_hdmi->hdmi_reg);
2043 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
2044 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2045 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2048 intel_dig_port->set_infoframes(encoder,
2050 old_crtc_state, old_conn_state);
2052 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2055 static void g4x_disable_hdmi(struct intel_encoder *encoder,
2056 const struct intel_crtc_state *old_crtc_state,
2057 const struct drm_connector_state *old_conn_state)
2059 if (old_crtc_state->has_audio)
2060 intel_audio_codec_disable(encoder,
2061 old_crtc_state, old_conn_state);
2063 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2066 static void pch_disable_hdmi(struct intel_encoder *encoder,
2067 const struct intel_crtc_state *old_crtc_state,
2068 const struct drm_connector_state *old_conn_state)
2070 if (old_crtc_state->has_audio)
2071 intel_audio_codec_disable(encoder,
2072 old_crtc_state, old_conn_state);
2075 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
2076 const struct intel_crtc_state *old_crtc_state,
2077 const struct drm_connector_state *old_conn_state)
2079 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
2082 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
2084 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2085 const struct ddi_vbt_port_info *info =
2086 &dev_priv->vbt.ddi_port_info[encoder->port];
2089 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2090 max_tmds_clock = 594000;
2091 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
2092 max_tmds_clock = 300000;
2093 else if (INTEL_GEN(dev_priv) >= 5)
2094 max_tmds_clock = 225000;
2096 max_tmds_clock = 165000;
2098 if (info->max_tmds_clock)
2099 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
2101 return max_tmds_clock;
2104 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
2105 bool respect_downstream_limits,
2108 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2109 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
2111 if (respect_downstream_limits) {
2112 struct intel_connector *connector = hdmi->attached_connector;
2113 const struct drm_display_info *info = &connector->base.display_info;
2115 if (hdmi->dp_dual_mode.max_tmds_clock)
2116 max_tmds_clock = min(max_tmds_clock,
2117 hdmi->dp_dual_mode.max_tmds_clock);
2119 if (info->max_tmds_clock)
2120 max_tmds_clock = min(max_tmds_clock,
2121 info->max_tmds_clock);
2122 else if (!hdmi->has_hdmi_sink || force_dvi)
2123 max_tmds_clock = min(max_tmds_clock, 165000);
2126 return max_tmds_clock;
2129 static enum drm_mode_status
2130 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
2131 int clock, bool respect_downstream_limits,
2134 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
2137 return MODE_CLOCK_LOW;
2138 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
2139 return MODE_CLOCK_HIGH;
2141 /* BXT DPLL can't generate 223-240 MHz */
2142 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
2143 return MODE_CLOCK_RANGE;
2145 /* CHV DPLL can't generate 216-240 MHz */
2146 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
2147 return MODE_CLOCK_RANGE;
2152 static enum drm_mode_status
2153 intel_hdmi_mode_valid(struct drm_connector *connector,
2154 struct drm_display_mode *mode)
2156 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2157 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
2158 struct drm_i915_private *dev_priv = to_i915(dev);
2159 enum drm_mode_status status;
2161 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
2163 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
2165 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
2166 return MODE_NO_DBLESCAN;
2168 clock = mode->clock;
2170 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2173 if (clock > max_dotclk)
2174 return MODE_CLOCK_HIGH;
2176 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2179 if (drm_mode_is_420_only(&connector->display_info, mode))
2182 /* check if we can do 8bpc */
2183 status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
2185 if (hdmi->has_hdmi_sink && !force_dvi) {
2186 /* if we can't do 8bpc we may still be able to do 12bpc */
2187 if (status != MODE_OK && !HAS_GMCH(dev_priv))
2188 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
2191 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2192 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
2193 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
2196 if (status != MODE_OK)
2199 return intel_mode_valid_max_plane_size(dev_priv, mode);
2202 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2205 struct drm_i915_private *dev_priv =
2206 to_i915(crtc_state->base.crtc->dev);
2207 struct drm_atomic_state *state = crtc_state->base.state;
2208 struct drm_connector_state *connector_state;
2209 struct drm_connector *connector;
2210 const struct drm_display_mode *adjusted_mode =
2211 &crtc_state->base.adjusted_mode;
2214 if (HAS_GMCH(dev_priv))
2217 if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
2220 if (crtc_state->pipe_bpp < bpc * 3)
2223 if (!crtc_state->has_hdmi_sink)
2227 * HDMI deep color affects the clocks, so it's only possible
2228 * when not cloning with other encoder types.
2230 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
2233 for_each_new_connector_in_state(state, connector, connector_state, i) {
2234 const struct drm_display_info *info = &connector->display_info;
2236 if (connector_state->crtc != crtc_state->base.crtc)
2239 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2240 const struct drm_hdmi_info *hdmi = &info->hdmi;
2242 if (bpc == 12 && !(hdmi->y420_dc_modes &
2243 DRM_EDID_YCBCR420_DC_36))
2245 else if (bpc == 10 && !(hdmi->y420_dc_modes &
2246 DRM_EDID_YCBCR420_DC_30))
2249 if (bpc == 12 && !(info->edid_hdmi_dc_modes &
2250 DRM_EDID_HDMI_DC_36))
2252 else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
2253 DRM_EDID_HDMI_DC_30))
2258 /* Display WA #1139: glk */
2259 if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
2260 adjusted_mode->htotal > 5460)
2263 /* Display Wa_1405510057:icl */
2264 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2265 bpc == 10 && INTEL_GEN(dev_priv) >= 11 &&
2266 (adjusted_mode->crtc_hblank_end -
2267 adjusted_mode->crtc_hblank_start) % 8 == 2)
2274 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
2275 struct intel_crtc_state *config)
2277 struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
2279 if (!connector->ycbcr_420_allowed) {
2280 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
2284 config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2286 /* YCBCR 420 output conversion needs a scaler */
2287 if (skl_update_scaler_crtc(config)) {
2288 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2292 intel_pch_panel_fitting(intel_crtc, config,
2293 DRM_MODE_SCALE_FULLSCREEN);
2298 static int intel_hdmi_port_clock(int clock, int bpc)
2301 * Need to adjust the port link by:
2305 return clock * bpc / 8;
2308 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2309 struct intel_crtc_state *crtc_state,
2310 int clock, bool force_dvi)
2312 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2315 for (bpc = 12; bpc >= 10; bpc -= 2) {
2316 if (hdmi_deep_color_possible(crtc_state, bpc) &&
2317 hdmi_port_clock_valid(intel_hdmi,
2318 intel_hdmi_port_clock(clock, bpc),
2319 true, force_dvi) == MODE_OK)
2326 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2327 struct intel_crtc_state *crtc_state,
2330 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2331 const struct drm_display_mode *adjusted_mode =
2332 &crtc_state->base.adjusted_mode;
2333 int bpc, clock = adjusted_mode->crtc_clock;
2335 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2338 /* YCBCR420 TMDS rate requirement is half the pixel clock */
2339 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2342 bpc = intel_hdmi_compute_bpc(encoder, crtc_state,
2345 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
2348 * pipe_bpp could already be below 8bpc due to
2349 * FDI bandwidth constraints. We shouldn't bump it
2350 * back up to 8bpc in that case.
2352 if (crtc_state->pipe_bpp > bpc * 3)
2353 crtc_state->pipe_bpp = bpc * 3;
2355 DRM_DEBUG_KMS("picking %d bpc for HDMI output (pipe bpp: %d)\n",
2356 bpc, crtc_state->pipe_bpp);
2358 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2359 false, force_dvi) != MODE_OK) {
2360 DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n",
2361 crtc_state->port_clock);
2368 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2369 struct intel_crtc_state *pipe_config,
2370 struct drm_connector_state *conn_state)
2372 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2373 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2374 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2375 struct drm_connector *connector = conn_state->connector;
2376 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2377 struct intel_digital_connector_state *intel_conn_state =
2378 to_intel_digital_connector_state(conn_state);
2379 bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
2382 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2385 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2386 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
2388 if (pipe_config->has_hdmi_sink)
2389 pipe_config->has_infoframe = true;
2391 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2392 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2393 pipe_config->limited_color_range =
2394 pipe_config->has_hdmi_sink &&
2395 drm_default_rgb_quant_range(adjusted_mode) ==
2396 HDMI_QUANTIZATION_RANGE_LIMITED;
2398 pipe_config->limited_color_range =
2399 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2402 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2403 pipe_config->pixel_multiplier = 2;
2405 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
2406 if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) {
2407 DRM_ERROR("Can't support YCBCR420 output\n");
2412 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2413 pipe_config->has_pch_encoder = true;
2415 if (pipe_config->has_hdmi_sink) {
2416 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2417 pipe_config->has_audio = intel_hdmi->has_audio;
2419 pipe_config->has_audio =
2420 intel_conn_state->force_audio == HDMI_AUDIO_ON;
2423 ret = intel_hdmi_compute_clock(encoder, pipe_config, force_dvi);
2427 /* Set user selected PAR to incoming mode's member */
2428 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
2430 pipe_config->lane_count = 4;
2432 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
2433 IS_GEMINILAKE(dev_priv))) {
2434 if (scdc->scrambling.low_rates)
2435 pipe_config->hdmi_scrambling = true;
2437 if (pipe_config->port_clock > 340000) {
2438 pipe_config->hdmi_scrambling = true;
2439 pipe_config->hdmi_high_tmds_clock_ratio = true;
2443 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state);
2445 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2446 DRM_DEBUG_KMS("bad AVI infoframe\n");
2450 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2451 DRM_DEBUG_KMS("bad SPD infoframe\n");
2455 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2456 DRM_DEBUG_KMS("bad HDMI infoframe\n");
2460 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2461 DRM_DEBUG_KMS("bad DRM infoframe\n");
2465 intel_hdcp_transcoder_config(intel_hdmi->attached_connector,
2466 pipe_config->cpu_transcoder);
2472 intel_hdmi_unset_edid(struct drm_connector *connector)
2474 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2476 intel_hdmi->has_hdmi_sink = false;
2477 intel_hdmi->has_audio = false;
2479 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2480 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2482 kfree(to_intel_connector(connector)->detect_edid);
2483 to_intel_connector(connector)->detect_edid = NULL;
2487 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2489 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2490 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
2491 enum port port = hdmi_to_dig_port(hdmi)->base.port;
2492 struct i2c_adapter *adapter =
2493 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2494 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2497 * Type 1 DVI adaptors are not required to implement any
2498 * registers, so we can't always detect their presence.
2499 * Ideally we should be able to check the state of the
2500 * CONFIG1 pin, but no such luck on our hardware.
2502 * The only method left to us is to check the VBT to see
2503 * if the port is a dual mode capable DP port. But let's
2504 * only do that when we sucesfully read the EDID, to avoid
2505 * confusing log messages about DP dual mode adaptors when
2506 * there's nothing connected to the port.
2508 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2509 /* An overridden EDID imply that we want this port for testing.
2510 * Make sure not to set limits for that port.
2512 if (has_edid && !connector->override_edid &&
2513 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2514 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
2515 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2517 type = DRM_DP_DUAL_MODE_NONE;
2521 if (type == DRM_DP_DUAL_MODE_NONE)
2524 hdmi->dp_dual_mode.type = type;
2525 hdmi->dp_dual_mode.max_tmds_clock =
2526 drm_dp_dual_mode_max_tmds_clock(type, adapter);
2528 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2529 drm_dp_get_dual_mode_type_name(type),
2530 hdmi->dp_dual_mode.max_tmds_clock);
2534 intel_hdmi_set_edid(struct drm_connector *connector)
2536 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2537 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2538 intel_wakeref_t wakeref;
2540 bool connected = false;
2541 struct i2c_adapter *i2c;
2543 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2545 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2547 edid = drm_get_edid(connector, i2c);
2549 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2550 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2551 intel_gmbus_force_bit(i2c, true);
2552 edid = drm_get_edid(connector, i2c);
2553 intel_gmbus_force_bit(i2c, false);
2556 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2558 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2560 to_intel_connector(connector)->detect_edid = edid;
2561 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2562 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2563 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2568 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2573 static enum drm_connector_status
2574 intel_hdmi_detect(struct drm_connector *connector, bool force)
2576 enum drm_connector_status status = connector_status_disconnected;
2577 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2578 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2579 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2580 intel_wakeref_t wakeref;
2582 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2583 connector->base.id, connector->name);
2585 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2587 if (INTEL_GEN(dev_priv) >= 11 &&
2588 !intel_digital_port_connected(encoder))
2591 intel_hdmi_unset_edid(connector);
2593 if (intel_hdmi_set_edid(connector))
2594 status = connector_status_connected;
2597 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2599 if (status != connector_status_connected)
2600 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2606 intel_hdmi_force(struct drm_connector *connector)
2608 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2609 connector->base.id, connector->name);
2611 intel_hdmi_unset_edid(connector);
2613 if (connector->status != connector_status_connected)
2616 intel_hdmi_set_edid(connector);
2619 static int intel_hdmi_get_modes(struct drm_connector *connector)
2623 edid = to_intel_connector(connector)->detect_edid;
2627 return intel_connector_update_modes(connector, edid);
2630 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
2631 const struct intel_crtc_state *pipe_config,
2632 const struct drm_connector_state *conn_state)
2634 struct intel_digital_port *intel_dig_port =
2635 enc_to_dig_port(&encoder->base);
2637 intel_hdmi_prepare(encoder, pipe_config);
2639 intel_dig_port->set_infoframes(encoder,
2640 pipe_config->has_infoframe,
2641 pipe_config, conn_state);
2644 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
2645 const struct intel_crtc_state *pipe_config,
2646 const struct drm_connector_state *conn_state)
2648 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2649 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2651 vlv_phy_pre_encoder_enable(encoder, pipe_config);
2654 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2657 dport->set_infoframes(encoder,
2658 pipe_config->has_infoframe,
2659 pipe_config, conn_state);
2661 g4x_enable_hdmi(encoder, pipe_config, conn_state);
2663 vlv_wait_port_ready(dev_priv, dport, 0x0);
2666 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2667 const struct intel_crtc_state *pipe_config,
2668 const struct drm_connector_state *conn_state)
2670 intel_hdmi_prepare(encoder, pipe_config);
2672 vlv_phy_pre_pll_enable(encoder, pipe_config);
2675 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
2676 const struct intel_crtc_state *pipe_config,
2677 const struct drm_connector_state *conn_state)
2679 intel_hdmi_prepare(encoder, pipe_config);
2681 chv_phy_pre_pll_enable(encoder, pipe_config);
2684 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
2685 const struct intel_crtc_state *old_crtc_state,
2686 const struct drm_connector_state *old_conn_state)
2688 chv_phy_post_pll_disable(encoder, old_crtc_state);
2691 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
2692 const struct intel_crtc_state *old_crtc_state,
2693 const struct drm_connector_state *old_conn_state)
2695 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2696 vlv_phy_reset_lanes(encoder, old_crtc_state);
2699 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
2700 const struct intel_crtc_state *old_crtc_state,
2701 const struct drm_connector_state *old_conn_state)
2703 struct drm_device *dev = encoder->base.dev;
2704 struct drm_i915_private *dev_priv = to_i915(dev);
2706 vlv_dpio_get(dev_priv);
2708 /* Assert data lane reset */
2709 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2711 vlv_dpio_put(dev_priv);
2714 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
2715 const struct intel_crtc_state *pipe_config,
2716 const struct drm_connector_state *conn_state)
2718 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2719 struct drm_device *dev = encoder->base.dev;
2720 struct drm_i915_private *dev_priv = to_i915(dev);
2722 chv_phy_pre_encoder_enable(encoder, pipe_config);
2724 /* FIXME: Program the support xxx V-dB */
2726 chv_set_phy_signal_level(encoder, 128, 102, false);
2728 dport->set_infoframes(encoder,
2729 pipe_config->has_infoframe,
2730 pipe_config, conn_state);
2732 g4x_enable_hdmi(encoder, pipe_config, conn_state);
2734 vlv_wait_port_ready(dev_priv, dport, 0x0);
2736 /* Second common lane will stay alive on its own now */
2737 chv_phy_release_cl2_override(encoder);
2740 static struct i2c_adapter *
2741 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2743 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2744 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
2746 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2749 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2751 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2752 struct kobject *i2c_kobj = &adapter->dev.kobj;
2753 struct kobject *connector_kobj = &connector->kdev->kobj;
2756 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2758 DRM_ERROR("Failed to create i2c symlink (%d)\n", ret);
2761 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2763 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2764 struct kobject *i2c_kobj = &adapter->dev.kobj;
2765 struct kobject *connector_kobj = &connector->kdev->kobj;
2767 sysfs_remove_link(connector_kobj, i2c_kobj->name);
2771 intel_hdmi_connector_register(struct drm_connector *connector)
2775 ret = intel_connector_register(connector);
2779 i915_debugfs_connector_add(connector);
2781 intel_hdmi_create_i2c_symlink(connector);
2786 static void intel_hdmi_destroy(struct drm_connector *connector)
2788 if (intel_attached_hdmi(connector)->cec_notifier)
2789 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
2791 intel_connector_destroy(connector);
2794 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2796 intel_hdmi_remove_i2c_symlink(connector);
2798 intel_connector_unregister(connector);
2801 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2802 .detect = intel_hdmi_detect,
2803 .force = intel_hdmi_force,
2804 .fill_modes = drm_helper_probe_single_connector_modes,
2805 .atomic_get_property = intel_digital_connector_atomic_get_property,
2806 .atomic_set_property = intel_digital_connector_atomic_set_property,
2807 .late_register = intel_hdmi_connector_register,
2808 .early_unregister = intel_hdmi_connector_unregister,
2809 .destroy = intel_hdmi_destroy,
2810 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2811 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2814 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2815 .get_modes = intel_hdmi_get_modes,
2816 .mode_valid = intel_hdmi_mode_valid,
2817 .atomic_check = intel_digital_connector_atomic_check,
2820 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2821 .destroy = intel_encoder_destroy,
2825 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2827 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2828 struct intel_digital_port *intel_dig_port =
2829 hdmi_to_dig_port(intel_hdmi);
2831 intel_attach_force_audio_property(connector);
2832 intel_attach_broadcast_rgb_property(connector);
2833 intel_attach_aspect_ratio_property(connector);
2836 * Attach Colorspace property for Non LSPCON based device
2837 * ToDo: This needs to be extended for LSPCON implementation
2838 * as well. Will be implemented separately.
2840 if (!intel_dig_port->lspcon.active)
2841 intel_attach_colorspace_property(connector);
2843 drm_connector_attach_content_type_property(connector);
2844 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2846 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2847 drm_object_attach_property(&connector->base,
2848 connector->dev->mode_config.hdr_output_metadata_property, 0);
2850 if (!HAS_GMCH(dev_priv))
2851 drm_connector_attach_max_bpc_property(connector, 8, 12);
2855 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2856 * @encoder: intel_encoder
2857 * @connector: drm_connector
2858 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2859 * or reset the high tmds clock ratio for scrambling
2860 * @scrambling: bool to Indicate if the function needs to set or reset
2863 * This function handles scrambling on HDMI 2.0 capable sinks.
2864 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2865 * it enables scrambling. This should be called before enabling the HDMI
2866 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2867 * detect a scrambled clock within 100 ms.
2870 * True on success, false on failure.
2872 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2873 struct drm_connector *connector,
2874 bool high_tmds_clock_ratio,
2877 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2878 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2879 struct drm_scrambling *sink_scrambling =
2880 &connector->display_info.hdmi.scdc.scrambling;
2881 struct i2c_adapter *adapter =
2882 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2884 if (!sink_scrambling->supported)
2887 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2888 connector->base.id, connector->name,
2889 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2891 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2892 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2893 high_tmds_clock_ratio) &&
2894 drm_scdc_set_scrambling(adapter, scrambling);
2897 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2903 ddc_pin = GMBUS_PIN_DPB;
2906 ddc_pin = GMBUS_PIN_DPC;
2909 ddc_pin = GMBUS_PIN_DPD_CHV;
2913 ddc_pin = GMBUS_PIN_DPB;
2919 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2925 ddc_pin = GMBUS_PIN_1_BXT;
2928 ddc_pin = GMBUS_PIN_2_BXT;
2932 ddc_pin = GMBUS_PIN_1_BXT;
2938 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2945 ddc_pin = GMBUS_PIN_1_BXT;
2948 ddc_pin = GMBUS_PIN_2_BXT;
2951 ddc_pin = GMBUS_PIN_4_CNP;
2954 ddc_pin = GMBUS_PIN_3_BXT;
2958 ddc_pin = GMBUS_PIN_1_BXT;
2964 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2966 enum phy phy = intel_port_to_phy(dev_priv, port);
2968 if (intel_phy_is_combo(dev_priv, phy))
2969 return GMBUS_PIN_1_BXT + port;
2970 else if (intel_phy_is_tc(dev_priv, phy))
2971 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2973 WARN(1, "Unknown port:%c\n", port_name(port));
2974 return GMBUS_PIN_2_BXT;
2977 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2979 enum phy phy = intel_port_to_phy(dev_priv, port);
2984 ddc_pin = GMBUS_PIN_1_BXT;
2987 ddc_pin = GMBUS_PIN_2_BXT;
2990 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2994 ddc_pin = GMBUS_PIN_1_BXT;
3000 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
3007 ddc_pin = GMBUS_PIN_DPB;
3010 ddc_pin = GMBUS_PIN_DPC;
3013 ddc_pin = GMBUS_PIN_DPD;
3017 ddc_pin = GMBUS_PIN_DPB;
3023 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
3026 const struct ddi_vbt_port_info *info =
3027 &dev_priv->vbt.ddi_port_info[port];
3030 if (info->alternate_ddc_pin) {
3031 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
3032 info->alternate_ddc_pin, port_name(port));
3033 return info->alternate_ddc_pin;
3036 if (HAS_PCH_MCC(dev_priv))
3037 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
3038 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3039 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
3040 else if (HAS_PCH_CNP(dev_priv))
3041 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
3042 else if (IS_GEN9_LP(dev_priv))
3043 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
3044 else if (IS_CHERRYVIEW(dev_priv))
3045 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
3047 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
3049 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
3050 ddc_pin, port_name(port));
3055 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
3057 struct drm_i915_private *dev_priv =
3058 to_i915(intel_dig_port->base.base.dev);
3060 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3061 intel_dig_port->write_infoframe = vlv_write_infoframe;
3062 intel_dig_port->read_infoframe = vlv_read_infoframe;
3063 intel_dig_port->set_infoframes = vlv_set_infoframes;
3064 intel_dig_port->infoframes_enabled = vlv_infoframes_enabled;
3065 } else if (IS_G4X(dev_priv)) {
3066 intel_dig_port->write_infoframe = g4x_write_infoframe;
3067 intel_dig_port->read_infoframe = g4x_read_infoframe;
3068 intel_dig_port->set_infoframes = g4x_set_infoframes;
3069 intel_dig_port->infoframes_enabled = g4x_infoframes_enabled;
3070 } else if (HAS_DDI(dev_priv)) {
3071 if (intel_dig_port->lspcon.active) {
3072 intel_dig_port->write_infoframe = lspcon_write_infoframe;
3073 intel_dig_port->read_infoframe = lspcon_read_infoframe;
3074 intel_dig_port->set_infoframes = lspcon_set_infoframes;
3075 intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled;
3077 intel_dig_port->write_infoframe = hsw_write_infoframe;
3078 intel_dig_port->read_infoframe = hsw_read_infoframe;
3079 intel_dig_port->set_infoframes = hsw_set_infoframes;
3080 intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;
3082 } else if (HAS_PCH_IBX(dev_priv)) {
3083 intel_dig_port->write_infoframe = ibx_write_infoframe;
3084 intel_dig_port->read_infoframe = ibx_read_infoframe;
3085 intel_dig_port->set_infoframes = ibx_set_infoframes;
3086 intel_dig_port->infoframes_enabled = ibx_infoframes_enabled;
3088 intel_dig_port->write_infoframe = cpt_write_infoframe;
3089 intel_dig_port->read_infoframe = cpt_read_infoframe;
3090 intel_dig_port->set_infoframes = cpt_set_infoframes;
3091 intel_dig_port->infoframes_enabled = cpt_infoframes_enabled;
3095 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
3096 struct intel_connector *intel_connector)
3098 struct drm_connector *connector = &intel_connector->base;
3099 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
3100 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3101 struct drm_device *dev = intel_encoder->base.dev;
3102 struct drm_i915_private *dev_priv = to_i915(dev);
3103 enum port port = intel_encoder->port;
3105 DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n",
3106 intel_encoder->base.base.id, intel_encoder->base.name);
3108 if (WARN(intel_dig_port->max_lanes < 4,
3109 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
3110 intel_dig_port->max_lanes, intel_encoder->base.base.id,
3111 intel_encoder->base.name))
3114 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
3115 DRM_MODE_CONNECTOR_HDMIA);
3116 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3118 connector->interlace_allowed = 1;
3119 connector->doublescan_allowed = 0;
3120 connector->stereo_allowed = 1;
3122 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3123 connector->ycbcr_420_allowed = true;
3125 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
3127 if (WARN_ON(port == PORT_A))
3129 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
3131 if (HAS_DDI(dev_priv))
3132 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3134 intel_connector->get_hw_state = intel_connector_get_hw_state;
3136 intel_hdmi_add_properties(intel_hdmi, connector);
3138 intel_connector_attach_encoder(intel_connector, intel_encoder);
3139 intel_hdmi->attached_connector = intel_connector;
3141 if (is_hdcp_supported(dev_priv, port)) {
3142 int ret = intel_hdcp_init(intel_connector,
3143 &intel_hdmi_hdcp_shim);
3145 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
3148 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3149 * 0xd. Failure to do so will result in spurious interrupts being
3150 * generated on the port when a cable is not attached.
3152 if (IS_G45(dev_priv)) {
3153 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3154 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3157 intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
3158 port_identifier(port));
3159 if (!intel_hdmi->cec_notifier)
3160 DRM_DEBUG_KMS("CEC notifier get failed\n");
3163 static enum intel_hotplug_state
3164 intel_hdmi_hotplug(struct intel_encoder *encoder,
3165 struct intel_connector *connector, bool irq_received)
3167 enum intel_hotplug_state state;
3169 state = intel_encoder_hotplug(encoder, connector, irq_received);
3172 * On many platforms the HDMI live state signal is known to be
3173 * unreliable, so we can't use it to detect if a sink is connected or
3174 * not. Instead we detect if it's connected based on whether we can
3175 * read the EDID or not. That in turn has a problem during disconnect,
3176 * since the HPD interrupt may be raised before the DDC lines get
3177 * disconnected (due to how the required length of DDC vs. HPD
3178 * connector pins are specified) and so we'll still be able to get a
3179 * valid EDID. To solve this schedule another detection cycle if this
3180 * time around we didn't detect any change in the sink's connection
3183 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
3184 state = INTEL_HOTPLUG_RETRY;
3189 void intel_hdmi_init(struct drm_i915_private *dev_priv,
3190 i915_reg_t hdmi_reg, enum port port)
3192 struct intel_digital_port *intel_dig_port;
3193 struct intel_encoder *intel_encoder;
3194 struct intel_connector *intel_connector;
3196 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3197 if (!intel_dig_port)
3200 intel_connector = intel_connector_alloc();
3201 if (!intel_connector) {
3202 kfree(intel_dig_port);
3206 intel_encoder = &intel_dig_port->base;
3208 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3209 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
3210 "HDMI %c", port_name(port));
3212 intel_encoder->hotplug = intel_hdmi_hotplug;
3213 intel_encoder->compute_config = intel_hdmi_compute_config;
3214 if (HAS_PCH_SPLIT(dev_priv)) {
3215 intel_encoder->disable = pch_disable_hdmi;
3216 intel_encoder->post_disable = pch_post_disable_hdmi;
3218 intel_encoder->disable = g4x_disable_hdmi;
3220 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
3221 intel_encoder->get_config = intel_hdmi_get_config;
3222 if (IS_CHERRYVIEW(dev_priv)) {
3223 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
3224 intel_encoder->pre_enable = chv_hdmi_pre_enable;
3225 intel_encoder->enable = vlv_enable_hdmi;
3226 intel_encoder->post_disable = chv_hdmi_post_disable;
3227 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
3228 } else if (IS_VALLEYVIEW(dev_priv)) {
3229 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
3230 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
3231 intel_encoder->enable = vlv_enable_hdmi;
3232 intel_encoder->post_disable = vlv_hdmi_post_disable;
3234 intel_encoder->pre_enable = intel_hdmi_pre_enable;
3235 if (HAS_PCH_CPT(dev_priv))
3236 intel_encoder->enable = cpt_enable_hdmi;
3237 else if (HAS_PCH_IBX(dev_priv))
3238 intel_encoder->enable = ibx_enable_hdmi;
3240 intel_encoder->enable = g4x_enable_hdmi;
3243 intel_encoder->type = INTEL_OUTPUT_HDMI;
3244 intel_encoder->power_domain = intel_port_to_power_domain(port);
3245 intel_encoder->port = port;
3246 if (IS_CHERRYVIEW(dev_priv)) {
3248 intel_encoder->crtc_mask = 1 << 2;
3250 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
3252 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3254 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
3256 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3257 * to work on real hardware. And since g4x can send infoframes to
3258 * only one port anyway, nothing is lost by allowing it.
3260 if (IS_G4X(dev_priv))
3261 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
3263 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
3264 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
3265 intel_dig_port->max_lanes = 4;
3267 intel_infoframe_init(intel_dig_port);
3269 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
3270 intel_hdmi_init_connector(intel_dig_port, intel_connector);