drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/reboot.h>
  32 #include <linux/slab.h>
  33 #include <linux/types.h>
  34
  35 #include <asm/byteorder.h>
  36
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_crtc.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/i915_drm.h>
  44
  45 #include "i915_debugfs.h"
  46 #include "i915_drv.h"
  47 #include "i915_trace.h"
  48 #include "intel_atomic.h"
  49 #include "intel_audio.h"
  50 #include "intel_connector.h"
  51 #include "intel_ddi.h"
  52 #include "intel_display_types.h"
  53 #include "intel_dp.h"
  54 #include "intel_dp_link_training.h"
  55 #include "intel_dp_mst.h"
  56 #include "intel_dpio_phy.h"
  57 #include "intel_fifo_underrun.h"
  58 #include "intel_hdcp.h"
  59 #include "intel_hdmi.h"
  60 #include "intel_hotplug.h"
  61 #include "intel_lspcon.h"
  62 #include "intel_lvds.h"
  63 #include "intel_panel.h"
  64 #include "intel_psr.h"
  65 #include "intel_sideband.h"
  66 #include "intel_tc.h"
  67 #include "intel_vdsc.h"
  68
  69 #define DP_DPRX_ESI_LEN 14
  70
  71 /* DP DSC throughput values used for slice count calculations KPixels/s */
  72 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  73 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  74 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  75
  76 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  77 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  78
  79 /* Compliance test status bits  */
  80 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  81 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  82 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  83 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  84
  85 struct dp_link_dpll {
  86         int clock;
  87         struct dpll dpll;
  88 };
  89
  90 static const struct dp_link_dpll g4x_dpll[] = {
  91         { 162000,
  92                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  93         { 270000,
  94                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  95 };
  96
  97 static const struct dp_link_dpll pch_dpll[] = {
  98         { 162000,
  99                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
 100         { 270000,
 101                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
 102 };
 103
 104 static const struct dp_link_dpll vlv_dpll[] = {
 105         { 162000,
 106                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 107         { 270000,
 108                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 109 };
 110
 111 /*
 112  * CHV supports eDP 1.4 that have  more link rates.
 113  * Below only provides the fixed rate but exclude variable rate.
 114  */
 115 static const struct dp_link_dpll chv_dpll[] = {
 116         /*
 117          * CHV requires to program fractional division for m2.
 118          * m2 is stored in fixed point format using formula below
 119          * (m2_int << 22) | m2_fraction
 120          */
 121         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 122                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 123         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 124                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 125 };
 126
 127 /* Constants for DP DSC configurations */
 128 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 129
 130 /* With Single pipe configuration, HW is capable of supporting maximum
 131  * of 4 slices per line.
 132  */
 133 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 134
 135 /**
 136  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 137  * @intel_dp: DP struct
 138  *
 139  * If a CPU or PCH DP output is attached to an eDP panel, this function
 140  * will return true, and false otherwise.
 141  */
 142 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 143 {
 144         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 145
 146         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 147 }
 148
 149 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 150 {
 151         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 152 }
 153
 154 static void intel_dp_link_down(struct intel_encoder *encoder,
 155                                const struct intel_crtc_state *old_crtc_state);
 156 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 157 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 158 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 159                                            const struct intel_crtc_state *crtc_state);
 160 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 161                                       enum pipe pipe);
 162 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 163
 164 /* update sink rates from dpcd */
 165 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 166 {
 167         static const int dp_rates[] = {
 168                 162000, 270000, 540000, 810000
 169         };
 170         int i, max_rate;
 171
 172         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 173
 174         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 175                 if (dp_rates[i] > max_rate)
 176                         break;
 177                 intel_dp->sink_rates[i] = dp_rates[i];
 178         }
 179
 180         intel_dp->num_sink_rates = i;
 181 }
 182
 183 /* Get length of rates array potentially limited by max_rate. */
 184 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 185 {
 186         int i;
 187
 188         /* Limit results by potentially reduced max rate */
 189         for (i = 0; i < len; i++) {
 190                 if (rates[len - i - 1] <= max_rate)
 191                         return len - i;
 192         }
 193
 194         return 0;
 195 }
 196
 197 /* Get length of common rates array potentially limited by max_rate. */
 198 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 199                                           int max_rate)
 200 {
 201         return intel_dp_rate_limit_len(intel_dp->common_rates,
 202                                        intel_dp->num_common_rates, max_rate);
 203 }
 204
 205 /* Theoretical max between source and sink */
 206 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 207 {
 208         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 209 }
 210
 211 /* Theoretical max between source and sink */
 212 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 213 {
 214         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 215         int source_max = intel_dig_port->max_lanes;
 216         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 217         int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port);
 218
 219         return min3(source_max, sink_max, fia_max);
 220 }
 221
 222 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 223 {
 224         return intel_dp->max_link_lane_count;
 225 }
 226
 227 int
 228 intel_dp_link_required(int pixel_clock, int bpp)
 229 {
 230         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 231         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 232 }
 233
 234 int
 235 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 236 {
 237         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 238          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 239          * is transmitted every LS_Clk per lane, there is no need to account for
 240          * the channel encoding that is done in the PHY layer here.
 241          */
 242
 243         return max_link_clock * max_lanes;
 244 }
 245
 246 static int
 247 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 248 {
 249         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 250         struct intel_encoder *encoder = &intel_dig_port->base;
 251         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 252         int max_dotclk = dev_priv->max_dotclk_freq;
 253         int ds_max_dotclk;
 254
 255         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 256
 257         if (type != DP_DS_PORT_TYPE_VGA)
 258                 return max_dotclk;
 259
 260         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 261                                                     intel_dp->downstream_ports);
 262
 263         if (ds_max_dotclk != 0)
 264                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 265
 266         return max_dotclk;
 267 }
 268
 269 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 270 {
 271         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 272         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 273         enum port port = dig_port->base.port;
 274
 275         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 276
 277         /* Low voltage SKUs are limited to max of 5.4G */
 278         if (voltage == VOLTAGE_INFO_0_85V)
 279                 return 540000;
 280
 281         /* For this SKU 8.1G is supported in all ports */
 282         if (IS_CNL_WITH_PORT_F(dev_priv))
 283                 return 810000;
 284
 285         /* For other SKUs, max rate on ports A and D is 5.4G */
 286         if (port == PORT_A || port == PORT_D)
 287                 return 540000;
 288
 289         return 810000;
 290 }
 291
 292 static int icl_max_source_rate(struct intel_dp *intel_dp)
 293 {
 294         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 295         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 296         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 297
 298         if (intel_phy_is_combo(dev_priv, phy) &&
 299             !IS_ELKHARTLAKE(dev_priv) &&
 300             !intel_dp_is_edp(intel_dp))
 301                 return 540000;
 302
 303         return 810000;
 304 }
 305
 306 static void
 307 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 308 {
 309         /* The values must be in increasing order */
 310         static const int cnl_rates[] = {
 311                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 312         };
 313         static const int bxt_rates[] = {
 314                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 315         };
 316         static const int skl_rates[] = {
 317                 162000, 216000, 270000, 324000, 432000, 540000
 318         };
 319         static const int hsw_rates[] = {
 320                 162000, 270000, 540000
 321         };
 322         static const int g4x_rates[] = {
 323                 162000, 270000
 324         };
 325         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 326         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 327         const struct ddi_vbt_port_info *info =
 328                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 329         const int *source_rates;
 330         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 331
 332         /* This should only be done once */
 333         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 334
 335         if (INTEL_GEN(dev_priv) >= 10) {
 336                 source_rates = cnl_rates;
 337                 size = ARRAY_SIZE(cnl_rates);
 338                 if (IS_GEN(dev_priv, 10))
 339                         max_rate = cnl_max_source_rate(intel_dp);
 340                 else
 341                         max_rate = icl_max_source_rate(intel_dp);
 342         } else if (IS_GEN9_LP(dev_priv)) {
 343                 source_rates = bxt_rates;
 344                 size = ARRAY_SIZE(bxt_rates);
 345         } else if (IS_GEN9_BC(dev_priv)) {
 346                 source_rates = skl_rates;
 347                 size = ARRAY_SIZE(skl_rates);
 348         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 349                    IS_BROADWELL(dev_priv)) {
 350                 source_rates = hsw_rates;
 351                 size = ARRAY_SIZE(hsw_rates);
 352         } else {
 353                 source_rates = g4x_rates;
 354                 size = ARRAY_SIZE(g4x_rates);
 355         }
 356
 357         if (max_rate && vbt_max_rate)
 358                 max_rate = min(max_rate, vbt_max_rate);
 359         else if (vbt_max_rate)
 360                 max_rate = vbt_max_rate;
 361
 362         if (max_rate)
 363                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 364
 365         intel_dp->source_rates = source_rates;
 366         intel_dp->num_source_rates = size;
 367 }
 368
 369 static int intersect_rates(const int *source_rates, int source_len,
 370                            const int *sink_rates, int sink_len,
 371                            int *common_rates)
 372 {
 373         int i = 0, j = 0, k = 0;
 374
 375         while (i < source_len && j < sink_len) {
 376                 if (source_rates[i] == sink_rates[j]) {
 377                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 378                                 return k;
 379                         common_rates[k] = source_rates[i];
 380                         ++k;
 381                         ++i;
 382                         ++j;
 383                 } else if (source_rates[i] < sink_rates[j]) {
 384                         ++i;
 385                 } else {
 386                         ++j;
 387                 }
 388         }
 389         return k;
 390 }
 391
 392 /* return index of rate in rates array, or -1 if not found */
 393 static int intel_dp_rate_index(const int *rates, int len, int rate)
 394 {
 395         int i;
 396
 397         for (i = 0; i < len; i++)
 398                 if (rate == rates[i])
 399                         return i;
 400
 401         return -1;
 402 }
 403
 404 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 405 {
 406         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 407
 408         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 409                                                      intel_dp->num_source_rates,
 410                                                      intel_dp->sink_rates,
 411                                                      intel_dp->num_sink_rates,
 412                                                      intel_dp->common_rates);
 413
 414         /* Paranoia, there should always be something in common. */
 415         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 416                 intel_dp->common_rates[0] = 162000;
 417                 intel_dp->num_common_rates = 1;
 418         }
 419 }
 420
 421 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 422                                        u8 lane_count)
 423 {
 424         /*
 425          * FIXME: we need to synchronize the current link parameters with
 426          * hardware readout. Currently fast link training doesn't work on
 427          * boot-up.
 428          */
 429         if (link_rate == 0 ||
 430             link_rate > intel_dp->max_link_rate)
 431                 return false;
 432
 433         if (lane_count == 0 ||
 434             lane_count > intel_dp_max_lane_count(intel_dp))
 435                 return false;
 436
 437         return true;
 438 }
 439
 440 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 441                                                      int link_rate,
 442                                                      u8 lane_count)
 443 {
 444         const struct drm_display_mode *fixed_mode =
 445                 intel_dp->attached_connector->panel.fixed_mode;
 446         int mode_rate, max_rate;
 447
 448         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 449         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 450         if (mode_rate > max_rate)
 451                 return false;
 452
 453         return true;
 454 }
 455
 456 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 457                                             int link_rate, u8 lane_count)
 458 {
 459         int index;
 460
 461         index = intel_dp_rate_index(intel_dp->common_rates,
 462                                     intel_dp->num_common_rates,
 463                                     link_rate);
 464         if (index > 0) {
 465                 if (intel_dp_is_edp(intel_dp) &&
 466                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 467                                                               intel_dp->common_rates[index - 1],
 468                                                               lane_count)) {
 469                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 470                         return 0;
 471                 }
 472                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 473                 intel_dp->max_link_lane_count = lane_count;
 474         } else if (lane_count > 1) {
 475                 if (intel_dp_is_edp(intel_dp) &&
 476                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 477                                                               intel_dp_max_common_rate(intel_dp),
 478                                                               lane_count >> 1)) {
 479                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 480                         return 0;
 481                 }
 482                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 483                 intel_dp->max_link_lane_count = lane_count >> 1;
 484         } else {
 485                 DRM_ERROR("Link Training Unsuccessful\n");
 486                 return -1;
 487         }
 488
 489         return 0;
 490 }
 491
 492 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 493 {
 494         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 495                        DP_DSC_FEC_OVERHEAD_FACTOR);
 496 }
 497
 498 static int
 499 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 500 {
 501         if (INTEL_GEN(i915) >= 11)
 502                 return 7680 * 8;
 503         else
 504                 return 6144 * 8;
 505 }
 506
 507 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 508                                        u32 link_clock, u32 lane_count,
 509                                        u32 mode_clock, u32 mode_hdisplay)
 510 {
 511         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 512         int i;
 513
 514         /*
 515          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 516          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 517          * for SST -> TimeSlotsPerMTP is 1,
 518          * for MST -> TimeSlotsPerMTP has to be calculated
 519          */
 520         bits_per_pixel = (link_clock * lane_count * 8) /
 521                          intel_dp_mode_to_fec_clock(mode_clock);
 522         DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel);
 523
 524         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 525         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 526                 mode_hdisplay;
 527         DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram);
 528
 529         /*
 530          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 531          * check, output bpp from small joiner RAM check)
 532          */
 533         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 534
 535         /* Error out if the max bpp is less than smallest allowed valid bpp */
 536         if (bits_per_pixel < valid_dsc_bpp[0]) {
 537                 DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n",
 538                               bits_per_pixel, valid_dsc_bpp[0]);
 539                 return 0;
 540         }
 541
 542         /* Find the nearest match in the array of known BPPs from VESA */
 543         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 544                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
 545                         break;
 546         }
 547         bits_per_pixel = valid_dsc_bpp[i];
 548
 549         /*
 550          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 551          * fractional part is 0
 552          */
 553         return bits_per_pixel << 4;
 554 }
 555
 556 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 557                                        int mode_clock, int mode_hdisplay)
 558 {
 559         u8 min_slice_count, i;
 560         int max_slice_width;
 561
 562         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 563                 min_slice_count = DIV_ROUND_UP(mode_clock,
 564                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 565         else
 566                 min_slice_count = DIV_ROUND_UP(mode_clock,
 567                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 568
 569         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 570         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 571                 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n",
 572                               max_slice_width);
 573                 return 0;
 574         }
 575         /* Also take into account max slice width */
 576         min_slice_count = min_t(u8, min_slice_count,
 577                                 DIV_ROUND_UP(mode_hdisplay,
 578                                              max_slice_width));
 579
 580         /* Find the closest match to the valid slice count values */
 581         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 582                 if (valid_dsc_slicecount[i] >
 583                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 584                                                     false))
 585                         break;
 586                 if (min_slice_count  <= valid_dsc_slicecount[i])
 587                         return valid_dsc_slicecount[i];
 588         }
 589
 590         DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count);
 591         return 0;
 592 }
 593
 594 static enum drm_mode_status
 595 intel_dp_mode_valid(struct drm_connector *connector,
 596                     struct drm_display_mode *mode)
 597 {
 598         struct intel_dp *intel_dp = intel_attached_dp(connector);
 599         struct intel_connector *intel_connector = to_intel_connector(connector);
 600         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 601         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 602         int target_clock = mode->clock;
 603         int max_rate, mode_rate, max_lanes, max_link_clock;
 604         int max_dotclk;
 605         u16 dsc_max_output_bpp = 0;
 606         u8 dsc_slice_count = 0;
 607
 608         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 609                 return MODE_NO_DBLESCAN;
 610
 611         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 612
 613         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 614                 if (mode->hdisplay > fixed_mode->hdisplay)
 615                         return MODE_PANEL;
 616
 617                 if (mode->vdisplay > fixed_mode->vdisplay)
 618                         return MODE_PANEL;
 619
 620                 target_clock = fixed_mode->clock;
 621         }
 622
 623         max_link_clock = intel_dp_max_link_rate(intel_dp);
 624         max_lanes = intel_dp_max_lane_count(intel_dp);
 625
 626         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 627         mode_rate = intel_dp_link_required(target_clock, 18);
 628
 629         /*
 630          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 631          * integer value since we support only integer values of bpp.
 632          */
 633         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 634             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 635                 if (intel_dp_is_edp(intel_dp)) {
 636                         dsc_max_output_bpp =
 637                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 638                         dsc_slice_count =
 639                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 640                                                                 true);
 641                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 642                         dsc_max_output_bpp =
 643                                 intel_dp_dsc_get_output_bpp(dev_priv,
 644                                                             max_link_clock,
 645                                                             max_lanes,
 646                                                             target_clock,
 647                                                             mode->hdisplay) >> 4;
 648                         dsc_slice_count =
 649                                 intel_dp_dsc_get_slice_count(intel_dp,
 650                                                              target_clock,
 651                                                              mode->hdisplay);
 652                 }
 653         }
 654
 655         if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) ||
 656             target_clock > max_dotclk)
 657                 return MODE_CLOCK_HIGH;
 658
 659         if (mode->clock < 10000)
 660                 return MODE_CLOCK_LOW;
 661
 662         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 663                 return MODE_H_ILLEGAL;
 664
 665         return intel_mode_valid_max_plane_size(dev_priv, mode);
 666 }
 667
 668 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 669 {
 670         int i;
 671         u32 v = 0;
 672
 673         if (src_bytes > 4)
 674                 src_bytes = 4;
 675         for (i = 0; i < src_bytes; i++)
 676                 v |= ((u32)src[i]) << ((3 - i) * 8);
 677         return v;
 678 }
 679
 680 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 681 {
 682         int i;
 683         if (dst_bytes > 4)
 684                 dst_bytes = 4;
 685         for (i = 0; i < dst_bytes; i++)
 686                 dst[i] = src >> ((3-i) * 8);
 687 }
 688
 689 static void
 690 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 691 static void
 692 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 693                                               bool force_disable_vdd);
 694 static void
 695 intel_dp_pps_init(struct intel_dp *intel_dp);
 696
 697 static intel_wakeref_t
 698 pps_lock(struct intel_dp *intel_dp)
 699 {
 700         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 701         intel_wakeref_t wakeref;
 702
 703         /*
 704          * See intel_power_sequencer_reset() why we need
 705          * a power domain reference here.
 706          */
 707         wakeref = intel_display_power_get(dev_priv,
 708                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 709
 710         mutex_lock(&dev_priv->pps_mutex);
 711
 712         return wakeref;
 713 }
 714
 715 static intel_wakeref_t
 716 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 717 {
 718         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 719
 720         mutex_unlock(&dev_priv->pps_mutex);
 721         intel_display_power_put(dev_priv,
 722                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 723                                 wakeref);
 724         return 0;
 725 }
 726
 727 #define with_pps_lock(dp, wf) \
 728         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 729
 730 static void
 731 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 732 {
 733         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 734         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 735         enum pipe pipe = intel_dp->pps_pipe;
 736         bool pll_enabled, release_cl_override = false;
 737         enum dpio_phy phy = DPIO_PHY(pipe);
 738         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 739         u32 DP;
 740
 741         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 742                  "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
 743                  pipe_name(pipe), intel_dig_port->base.base.base.id,
 744                  intel_dig_port->base.base.name))
 745                 return;
 746
 747         DRM_DEBUG_KMS("kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
 748                       pipe_name(pipe), intel_dig_port->base.base.base.id,
 749                       intel_dig_port->base.base.name);
 750
 751         /* Preserve the BIOS-computed detected bit. This is
 752          * supposed to be read-only.
 753          */
 754         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 755         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 756         DP |= DP_PORT_WIDTH(1);
 757         DP |= DP_LINK_TRAIN_PAT_1;
 758
 759         if (IS_CHERRYVIEW(dev_priv))
 760                 DP |= DP_PIPE_SEL_CHV(pipe);
 761         else
 762                 DP |= DP_PIPE_SEL(pipe);
 763
 764         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 765
 766         /*
 767          * The DPLL for the pipe must be enabled for this to work.
 768          * So enable temporarily it if it's not already enabled.
 769          */
 770         if (!pll_enabled) {
 771                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 772                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 773
 774                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 775                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 776                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 777                                   pipe_name(pipe));
 778                         return;
 779                 }
 780         }
 781
 782         /*
 783          * Similar magic as in intel_dp_enable_port().
 784          * We _must_ do this port enable + disable trick
 785          * to make this power sequencer lock onto the port.
 786          * Otherwise even VDD force bit won't work.
 787          */
 788         I915_WRITE(intel_dp->output_reg, DP);
 789         POSTING_READ(intel_dp->output_reg);
 790
 791         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 792         POSTING_READ(intel_dp->output_reg);
 793
 794         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 795         POSTING_READ(intel_dp->output_reg);
 796
 797         if (!pll_enabled) {
 798                 vlv_force_pll_off(dev_priv, pipe);
 799
 800                 if (release_cl_override)
 801                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 802         }
 803 }
 804
 805 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 806 {
 807         struct intel_encoder *encoder;
 808         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 809
 810         /*
 811          * We don't have power sequencer currently.
 812          * Pick one that's not used by other ports.
 813          */
 814         for_each_intel_dp(&dev_priv->drm, encoder) {
 815                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 816
 817                 if (encoder->type == INTEL_OUTPUT_EDP) {
 818                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 819                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 820
 821                         if (intel_dp->pps_pipe != INVALID_PIPE)
 822                                 pipes &= ~(1 << intel_dp->pps_pipe);
 823                 } else {
 824                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 825
 826                         if (intel_dp->active_pipe != INVALID_PIPE)
 827                                 pipes &= ~(1 << intel_dp->active_pipe);
 828                 }
 829         }
 830
 831         if (pipes == 0)
 832                 return INVALID_PIPE;
 833
 834         return ffs(pipes) - 1;
 835 }
 836
 837 static enum pipe
 838 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 839 {
 840         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 841         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 842         enum pipe pipe;
 843
 844         lockdep_assert_held(&dev_priv->pps_mutex);
 845
 846         /* We should never land here with regular DP ports */
 847         WARN_ON(!intel_dp_is_edp(intel_dp));
 848
 849         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 850                 intel_dp->active_pipe != intel_dp->pps_pipe);
 851
 852         if (intel_dp->pps_pipe != INVALID_PIPE)
 853                 return intel_dp->pps_pipe;
 854
 855         pipe = vlv_find_free_pps(dev_priv);
 856
 857         /*
 858          * Didn't find one. This should not happen since there
 859          * are two power sequencers and up to two eDP ports.
 860          */
 861         if (WARN_ON(pipe == INVALID_PIPE))
 862                 pipe = PIPE_A;
 863
 864         vlv_steal_power_sequencer(dev_priv, pipe);
 865         intel_dp->pps_pipe = pipe;
 866
 867         DRM_DEBUG_KMS("picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
 868                       pipe_name(intel_dp->pps_pipe),
 869                       intel_dig_port->base.base.base.id,
 870                       intel_dig_port->base.base.name);
 871
 872         /* init power sequencer on this pipe and port */
 873         intel_dp_init_panel_power_sequencer(intel_dp);
 874         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 875
 876         /*
 877          * Even vdd force doesn't work until we've made
 878          * the power sequencer lock in on the port.
 879          */
 880         vlv_power_sequencer_kick(intel_dp);
 881
 882         return intel_dp->pps_pipe;
 883 }
 884
 885 static int
 886 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 887 {
 888         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 889         int backlight_controller = dev_priv->vbt.backlight.controller;
 890
 891         lockdep_assert_held(&dev_priv->pps_mutex);
 892
 893         /* We should never land here with regular DP ports */
 894         WARN_ON(!intel_dp_is_edp(intel_dp));
 895
 896         if (!intel_dp->pps_reset)
 897                 return backlight_controller;
 898
 899         intel_dp->pps_reset = false;
 900
 901         /*
 902          * Only the HW needs to be reprogrammed, the SW state is fixed and
 903          * has been setup during connector init.
 904          */
 905         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 906
 907         return backlight_controller;
 908 }
 909
 910 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 911                                enum pipe pipe);
 912
 913 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 914                                enum pipe pipe)
 915 {
 916         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 917 }
 918
 919 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 920                                 enum pipe pipe)
 921 {
 922         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 923 }
 924
 925 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 926                          enum pipe pipe)
 927 {
 928         return true;
 929 }
 930
 931 static enum pipe
 932 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 933                      enum port port,
 934                      vlv_pipe_check pipe_check)
 935 {
 936         enum pipe pipe;
 937
 938         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 939                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 940                         PANEL_PORT_SELECT_MASK;
 941
 942                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 943                         continue;
 944
 945                 if (!pipe_check(dev_priv, pipe))
 946                         continue;
 947
 948                 return pipe;
 949         }
 950
 951         return INVALID_PIPE;
 952 }
 953
 954 static void
 955 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 956 {
 957         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 958         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 959         enum port port = intel_dig_port->base.port;
 960
 961         lockdep_assert_held(&dev_priv->pps_mutex);
 962
 963         /* try to find a pipe with this port selected */
 964         /* first pick one where the panel is on */
 965         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 966                                                   vlv_pipe_has_pp_on);
 967         /* didn't find one? pick one where vdd is on */
 968         if (intel_dp->pps_pipe == INVALID_PIPE)
 969                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 970                                                           vlv_pipe_has_vdd_on);
 971         /* didn't find one? pick one with just the correct port */
 972         if (intel_dp->pps_pipe == INVALID_PIPE)
 973                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 974                                                           vlv_pipe_any);
 975
 976         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 977         if (intel_dp->pps_pipe == INVALID_PIPE) {
 978                 DRM_DEBUG_KMS("no initial power sequencer for [ENCODER:%d:%s]\n",
 979                               intel_dig_port->base.base.base.id,
 980                               intel_dig_port->base.base.name);
 981                 return;
 982         }
 983
 984         DRM_DEBUG_KMS("initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
 985                       intel_dig_port->base.base.base.id,
 986                       intel_dig_port->base.base.name,
 987                       pipe_name(intel_dp->pps_pipe));
 988
 989         intel_dp_init_panel_power_sequencer(intel_dp);
 990         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 991 }
 992
 993 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 994 {
 995         struct intel_encoder *encoder;
 996
 997         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 998                     !IS_GEN9_LP(dev_priv)))
 999                 return;
1000
1001         /*
1002          * We can't grab pps_mutex here due to deadlock with power_domain
1003          * mutex when power_domain functions are called while holding pps_mutex.
1004          * That also means that in order to use pps_pipe the code needs to
1005          * hold both a power domain reference and pps_mutex, and the power domain
1006          * reference get/put must be done while _not_ holding pps_mutex.
1007          * pps_{lock,unlock}() do these steps in the correct order, so one
1008          * should use them always.
1009          */
1010
1011         for_each_intel_dp(&dev_priv->drm, encoder) {
1012                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1013
1014                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
1015
1016                 if (encoder->type != INTEL_OUTPUT_EDP)
1017                         continue;
1018
1019                 if (IS_GEN9_LP(dev_priv))
1020                         intel_dp->pps_reset = true;
1021                 else
1022                         intel_dp->pps_pipe = INVALID_PIPE;
1023         }
1024 }
1025
1026 struct pps_registers {
1027         i915_reg_t pp_ctrl;
1028         i915_reg_t pp_stat;
1029         i915_reg_t pp_on;
1030         i915_reg_t pp_off;
1031         i915_reg_t pp_div;
1032 };
1033
1034 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1035                                     struct pps_registers *regs)
1036 {
1037         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1038         int pps_idx = 0;
1039
1040         memset(regs, 0, sizeof(*regs));
1041
1042         if (IS_GEN9_LP(dev_priv))
1043                 pps_idx = bxt_power_sequencer_idx(intel_dp);
1044         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1045                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1046
1047         regs->pp_ctrl = PP_CONTROL(pps_idx);
1048         regs->pp_stat = PP_STATUS(pps_idx);
1049         regs->pp_on = PP_ON_DELAYS(pps_idx);
1050         regs->pp_off = PP_OFF_DELAYS(pps_idx);
1051
1052         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1053         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1054                 regs->pp_div = INVALID_MMIO_REG;
1055         else
1056                 regs->pp_div = PP_DIVISOR(pps_idx);
1057 }
1058
1059 static i915_reg_t
1060 _pp_ctrl_reg(struct intel_dp *intel_dp)
1061 {
1062         struct pps_registers regs;
1063
1064         intel_pps_get_registers(intel_dp, &regs);
1065
1066         return regs.pp_ctrl;
1067 }
1068
1069 static i915_reg_t
1070 _pp_stat_reg(struct intel_dp *intel_dp)
1071 {
1072         struct pps_registers regs;
1073
1074         intel_pps_get_registers(intel_dp, &regs);
1075
1076         return regs.pp_stat;
1077 }
1078
1079 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
1080    This function only applicable when panel PM state is not to be tracked */
1081 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
1082                               void *unused)
1083 {
1084         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
1085                                                  edp_notifier);
1086         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1087         intel_wakeref_t wakeref;
1088
1089         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
1090                 return 0;
1091
1092         with_pps_lock(intel_dp, wakeref) {
1093                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1094                         enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
1095                         i915_reg_t pp_ctrl_reg, pp_div_reg;
1096                         u32 pp_div;
1097
1098                         pp_ctrl_reg = PP_CONTROL(pipe);
1099                         pp_div_reg  = PP_DIVISOR(pipe);
1100                         pp_div = I915_READ(pp_div_reg);
1101                         pp_div &= PP_REFERENCE_DIVIDER_MASK;
1102
1103                         /* 0x1F write to PP_DIV_REG sets max cycle delay */
1104                         I915_WRITE(pp_div_reg, pp_div | 0x1F);
1105                         I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS);
1106                         msleep(intel_dp->panel_power_cycle_delay);
1107                 }
1108         }
1109
1110         return 0;
1111 }
1112
1113 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1114 {
1115         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1116
1117         lockdep_assert_held(&dev_priv->pps_mutex);
1118
1119         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1120             intel_dp->pps_pipe == INVALID_PIPE)
1121                 return false;
1122
1123         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
1124 }
1125
1126 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1127 {
1128         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1129
1130         lockdep_assert_held(&dev_priv->pps_mutex);
1131
1132         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1133             intel_dp->pps_pipe == INVALID_PIPE)
1134                 return false;
1135
1136         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1137 }
1138
1139 static void
1140 intel_dp_check_edp(struct intel_dp *intel_dp)
1141 {
1142         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1143
1144         if (!intel_dp_is_edp(intel_dp))
1145                 return;
1146
1147         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1148                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
1149                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
1150                               I915_READ(_pp_stat_reg(intel_dp)),
1151                               I915_READ(_pp_ctrl_reg(intel_dp)));
1152         }
1153 }
1154
1155 static u32
1156 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1157 {
1158         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1159         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1160         u32 status;
1161         bool done;
1162
1163 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1164         done = wait_event_timeout(i915->gmbus_wait_queue, C,
1165                                   msecs_to_jiffies_timeout(10));
1166
1167         /* just trace the final value */
1168         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1169
1170         if (!done)
1171                 DRM_ERROR("dp aux hw did not signal timeout!\n");
1172 #undef C
1173
1174         return status;
1175 }
1176
1177 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1178 {
1179         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1180
1181         if (index)
1182                 return 0;
1183
1184         /*
1185          * The clock divider is based off the hrawclk, and would like to run at
1186          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1187          */
1188         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1189 }
1190
1191 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1192 {
1193         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1194         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1195
1196         if (index)
1197                 return 0;
1198
1199         /*
1200          * The clock divider is based off the cdclk or PCH rawclk, and would
1201          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1202          * divide by 2000 and use that
1203          */
1204         if (dig_port->aux_ch == AUX_CH_A)
1205                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1206         else
1207                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1208 }
1209
1210 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1211 {
1212         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1213         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1214
1215         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1216                 /* Workaround for non-ULT HSW */
1217                 switch (index) {
1218                 case 0: return 63;
1219                 case 1: return 72;
1220                 default: return 0;
1221                 }
1222         }
1223
1224         return ilk_get_aux_clock_divider(intel_dp, index);
1225 }
1226
1227 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1228 {
1229         /*
1230          * SKL doesn't need us to program the AUX clock divider (Hardware will
1231          * derive the clock from CDCLK automatically). We still implement the
1232          * get_aux_clock_divider vfunc to plug-in into the existing code.
1233          */
1234         return index ? 0 : 1;
1235 }
1236
1237 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1238                                 int send_bytes,
1239                                 u32 aux_clock_divider)
1240 {
1241         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1242         struct drm_i915_private *dev_priv =
1243                         to_i915(intel_dig_port->base.base.dev);
1244         u32 precharge, timeout;
1245
1246         if (IS_GEN(dev_priv, 6))
1247                 precharge = 3;
1248         else
1249                 precharge = 5;
1250
1251         if (IS_BROADWELL(dev_priv))
1252                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1253         else
1254                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1255
1256         return DP_AUX_CH_CTL_SEND_BUSY |
1257                DP_AUX_CH_CTL_DONE |
1258                DP_AUX_CH_CTL_INTERRUPT |
1259                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1260                timeout |
1261                DP_AUX_CH_CTL_RECEIVE_ERROR |
1262                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1263                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1264                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1265 }
1266
1267 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1268                                 int send_bytes,
1269                                 u32 unused)
1270 {
1271         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1272         u32 ret;
1273
1274         ret = DP_AUX_CH_CTL_SEND_BUSY |
1275               DP_AUX_CH_CTL_DONE |
1276               DP_AUX_CH_CTL_INTERRUPT |
1277               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1278               DP_AUX_CH_CTL_TIME_OUT_MAX |
1279               DP_AUX_CH_CTL_RECEIVE_ERROR |
1280               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1281               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1282               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1283
1284         if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT)
1285                 ret |= DP_AUX_CH_CTL_TBT_IO;
1286
1287         return ret;
1288 }
1289
1290 static int
1291 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1292                   const u8 *send, int send_bytes,
1293                   u8 *recv, int recv_size,
1294                   u32 aux_send_ctl_flags)
1295 {
1296         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1297         struct drm_i915_private *i915 =
1298                         to_i915(intel_dig_port->base.base.dev);
1299         struct intel_uncore *uncore = &i915->uncore;
1300         enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
1301         bool is_tc_port = intel_phy_is_tc(i915, phy);
1302         i915_reg_t ch_ctl, ch_data[5];
1303         u32 aux_clock_divider;
1304         enum intel_display_power_domain aux_domain =
1305                 intel_aux_power_domain(intel_dig_port);
1306         intel_wakeref_t aux_wakeref;
1307         intel_wakeref_t pps_wakeref;
1308         int i, ret, recv_bytes;
1309         int try, clock = 0;
1310         u32 status;
1311         bool vdd;
1312
1313         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1314         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1315                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1316
1317         if (is_tc_port)
1318                 intel_tc_port_lock(intel_dig_port);
1319
1320         aux_wakeref = intel_display_power_get(i915, aux_domain);
1321         pps_wakeref = pps_lock(intel_dp);
1322
1323         /*
1324          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1325          * In such cases we want to leave VDD enabled and it's up to upper layers
1326          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1327          * ourselves.
1328          */
1329         vdd = edp_panel_vdd_on(intel_dp);
1330
1331         /* dp aux is extremely sensitive to irq latency, hence request the
1332          * lowest possible wakeup latency and so prevent the cpu from going into
1333          * deep sleep states.
1334          */
1335         pm_qos_update_request(&i915->pm_qos, 0);
1336
1337         intel_dp_check_edp(intel_dp);
1338
1339         /* Try to wait for any previous AUX channel activity */
1340         for (try = 0; try < 3; try++) {
1341                 status = intel_uncore_read_notrace(uncore, ch_ctl);
1342                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1343                         break;
1344                 msleep(1);
1345         }
1346         /* just trace the final value */
1347         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1348
1349         if (try == 3) {
1350                 static u32 last_status = -1;
1351                 const u32 status = intel_uncore_read(uncore, ch_ctl);
1352
1353                 if (status != last_status) {
1354                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1355                              status);
1356                         last_status = status;
1357                 }
1358
1359                 ret = -EBUSY;
1360                 goto out;
1361         }
1362
1363         /* Only 5 data registers! */
1364         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1365                 ret = -E2BIG;
1366                 goto out;
1367         }
1368
1369         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1370                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1371                                                           send_bytes,
1372                                                           aux_clock_divider);
1373
1374                 send_ctl |= aux_send_ctl_flags;
1375
1376                 /* Must try at least 3 times according to DP spec */
1377                 for (try = 0; try < 5; try++) {
1378                         /* Load the send data into the aux channel data registers */
1379                         for (i = 0; i < send_bytes; i += 4)
1380                                 intel_uncore_write(uncore,
1381                                                    ch_data[i >> 2],
1382                                                    intel_dp_pack_aux(send + i,
1383                                                                      send_bytes - i));
1384
1385                         /* Send the command and wait for it to complete */
1386                         intel_uncore_write(uncore, ch_ctl, send_ctl);
1387
1388                         status = intel_dp_aux_wait_done(intel_dp);
1389
1390                         /* Clear done status and any errors */
1391                         intel_uncore_write(uncore,
1392                                            ch_ctl,
1393                                            status |
1394                                            DP_AUX_CH_CTL_DONE |
1395                                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
1396                                            DP_AUX_CH_CTL_RECEIVE_ERROR);
1397
1398                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1399                          *   400us delay required for errors and timeouts
1400                          *   Timeout errors from the HW already meet this
1401                          *   requirement so skip to next iteration
1402                          */
1403                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1404                                 continue;
1405
1406                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1407                                 usleep_range(400, 500);
1408                                 continue;
1409                         }
1410                         if (status & DP_AUX_CH_CTL_DONE)
1411                                 goto done;
1412                 }
1413         }
1414
1415         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1416                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1417                 ret = -EBUSY;
1418                 goto out;
1419         }
1420
1421 done:
1422         /* Check for timeout or receive error.
1423          * Timeouts occur when the sink is not connected
1424          */
1425         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1426                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1427                 ret = -EIO;
1428                 goto out;
1429         }
1430
1431         /* Timeouts occur when the device isn't connected, so they're
1432          * "normal" -- don't fill the kernel log with these */
1433         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1434                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1435                 ret = -ETIMEDOUT;
1436                 goto out;
1437         }
1438
1439         /* Unload any bytes sent back from the other side */
1440         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1441                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1442
1443         /*
1444          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1445          * We have no idea of what happened so we return -EBUSY so
1446          * drm layer takes care for the necessary retries.
1447          */
1448         if (recv_bytes == 0 || recv_bytes > 20) {
1449                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1450                               recv_bytes);
1451                 ret = -EBUSY;
1452                 goto out;
1453         }
1454
1455         if (recv_bytes > recv_size)
1456                 recv_bytes = recv_size;
1457
1458         for (i = 0; i < recv_bytes; i += 4)
1459                 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1460                                     recv + i, recv_bytes - i);
1461
1462         ret = recv_bytes;
1463 out:
1464         pm_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1465
1466         if (vdd)
1467                 edp_panel_vdd_off(intel_dp, false);
1468
1469         pps_unlock(intel_dp, pps_wakeref);
1470         intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1471
1472         if (is_tc_port)
1473                 intel_tc_port_unlock(intel_dig_port);
1474
1475         return ret;
1476 }
1477
1478 #define BARE_ADDRESS_SIZE       3
1479 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1480
1481 static void
1482 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1483                     const struct drm_dp_aux_msg *msg)
1484 {
1485         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1486         txbuf[1] = (msg->address >> 8) & 0xff;
1487         txbuf[2] = msg->address & 0xff;
1488         txbuf[3] = msg->size - 1;
1489 }
1490
1491 static ssize_t
1492 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1493 {
1494         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1495         u8 txbuf[20], rxbuf[20];
1496         size_t txsize, rxsize;
1497         int ret;
1498
1499         intel_dp_aux_header(txbuf, msg);
1500
1501         switch (msg->request & ~DP_AUX_I2C_MOT) {
1502         case DP_AUX_NATIVE_WRITE:
1503         case DP_AUX_I2C_WRITE:
1504         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1505                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1506                 rxsize = 2; /* 0 or 1 data bytes */
1507
1508                 if (WARN_ON(txsize > 20))
1509                         return -E2BIG;
1510
1511                 WARN_ON(!msg->buffer != !msg->size);
1512
1513                 if (msg->buffer)
1514                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1515
1516                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1517                                         rxbuf, rxsize, 0);
1518                 if (ret > 0) {
1519                         msg->reply = rxbuf[0] >> 4;
1520
1521                         if (ret > 1) {
1522                                 /* Number of bytes written in a short write. */
1523                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1524                         } else {
1525                                 /* Return payload size. */
1526                                 ret = msg->size;
1527                         }
1528                 }
1529                 break;
1530
1531         case DP_AUX_NATIVE_READ:
1532         case DP_AUX_I2C_READ:
1533                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1534                 rxsize = msg->size + 1;
1535
1536                 if (WARN_ON(rxsize > 20))
1537                         return -E2BIG;
1538
1539                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1540                                         rxbuf, rxsize, 0);
1541                 if (ret > 0) {
1542                         msg->reply = rxbuf[0] >> 4;
1543                         /*
1544                          * Assume happy day, and copy the data. The caller is
1545                          * expected to check msg->reply before touching it.
1546                          *
1547                          * Return payload size.
1548                          */
1549                         ret--;
1550                         memcpy(msg->buffer, rxbuf + 1, ret);
1551                 }
1552                 break;
1553
1554         default:
1555                 ret = -EINVAL;
1556                 break;
1557         }
1558
1559         return ret;
1560 }
1561
1562
1563 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1564 {
1565         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1566         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1567         enum aux_ch aux_ch = dig_port->aux_ch;
1568
1569         switch (aux_ch) {
1570         case AUX_CH_B:
1571         case AUX_CH_C:
1572         case AUX_CH_D:
1573                 return DP_AUX_CH_CTL(aux_ch);
1574         default:
1575                 MISSING_CASE(aux_ch);
1576                 return DP_AUX_CH_CTL(AUX_CH_B);
1577         }
1578 }
1579
1580 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1581 {
1582         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1583         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1584         enum aux_ch aux_ch = dig_port->aux_ch;
1585
1586         switch (aux_ch) {
1587         case AUX_CH_B:
1588         case AUX_CH_C:
1589         case AUX_CH_D:
1590                 return DP_AUX_CH_DATA(aux_ch, index);
1591         default:
1592                 MISSING_CASE(aux_ch);
1593                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1594         }
1595 }
1596
1597 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1598 {
1599         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1600         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1601         enum aux_ch aux_ch = dig_port->aux_ch;
1602
1603         switch (aux_ch) {
1604         case AUX_CH_A:
1605                 return DP_AUX_CH_CTL(aux_ch);
1606         case AUX_CH_B:
1607         case AUX_CH_C:
1608         case AUX_CH_D:
1609                 return PCH_DP_AUX_CH_CTL(aux_ch);
1610         default:
1611                 MISSING_CASE(aux_ch);
1612                 return DP_AUX_CH_CTL(AUX_CH_A);
1613         }
1614 }
1615
1616 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1617 {
1618         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1619         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1620         enum aux_ch aux_ch = dig_port->aux_ch;
1621
1622         switch (aux_ch) {
1623         case AUX_CH_A:
1624                 return DP_AUX_CH_DATA(aux_ch, index);
1625         case AUX_CH_B:
1626         case AUX_CH_C:
1627         case AUX_CH_D:
1628                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1629         default:
1630                 MISSING_CASE(aux_ch);
1631                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1632         }
1633 }
1634
1635 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1636 {
1637         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1638         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1639         enum aux_ch aux_ch = dig_port->aux_ch;
1640
1641         switch (aux_ch) {
1642         case AUX_CH_A:
1643         case AUX_CH_B:
1644         case AUX_CH_C:
1645         case AUX_CH_D:
1646         case AUX_CH_E:
1647         case AUX_CH_F:
1648                 return DP_AUX_CH_CTL(aux_ch);
1649         default:
1650                 MISSING_CASE(aux_ch);
1651                 return DP_AUX_CH_CTL(AUX_CH_A);
1652         }
1653 }
1654
1655 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1656 {
1657         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1658         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1659         enum aux_ch aux_ch = dig_port->aux_ch;
1660
1661         switch (aux_ch) {
1662         case AUX_CH_A:
1663         case AUX_CH_B:
1664         case AUX_CH_C:
1665         case AUX_CH_D:
1666         case AUX_CH_E:
1667         case AUX_CH_F:
1668                 return DP_AUX_CH_DATA(aux_ch, index);
1669         default:
1670                 MISSING_CASE(aux_ch);
1671                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1672         }
1673 }
1674
1675 static void
1676 intel_dp_aux_fini(struct intel_dp *intel_dp)
1677 {
1678         kfree(intel_dp->aux.name);
1679 }
1680
1681 static void
1682 intel_dp_aux_init(struct intel_dp *intel_dp)
1683 {
1684         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1685         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1686         struct intel_encoder *encoder = &dig_port->base;
1687
1688         if (INTEL_GEN(dev_priv) >= 9) {
1689                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1690                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1691         } else if (HAS_PCH_SPLIT(dev_priv)) {
1692                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1693                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1694         } else {
1695                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1696                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1697         }
1698
1699         if (INTEL_GEN(dev_priv) >= 9)
1700                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1701         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1702                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1703         else if (HAS_PCH_SPLIT(dev_priv))
1704                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1705         else
1706                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1707
1708         if (INTEL_GEN(dev_priv) >= 9)
1709                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1710         else
1711                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1712
1713         drm_dp_aux_init(&intel_dp->aux);
1714
1715         /* Failure to allocate our preferred name is not critical */
1716         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1717                                        port_name(encoder->port));
1718         intel_dp->aux.transfer = intel_dp_aux_transfer;
1719 }
1720
1721 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1722 {
1723         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1724
1725         return max_rate >= 540000;
1726 }
1727
1728 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1729 {
1730         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1731
1732         return max_rate >= 810000;
1733 }
1734
1735 static void
1736 intel_dp_set_clock(struct intel_encoder *encoder,
1737                    struct intel_crtc_state *pipe_config)
1738 {
1739         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1740         const struct dp_link_dpll *divisor = NULL;
1741         int i, count = 0;
1742
1743         if (IS_G4X(dev_priv)) {
1744                 divisor = g4x_dpll;
1745                 count = ARRAY_SIZE(g4x_dpll);
1746         } else if (HAS_PCH_SPLIT(dev_priv)) {
1747                 divisor = pch_dpll;
1748                 count = ARRAY_SIZE(pch_dpll);
1749         } else if (IS_CHERRYVIEW(dev_priv)) {
1750                 divisor = chv_dpll;
1751                 count = ARRAY_SIZE(chv_dpll);
1752         } else if (IS_VALLEYVIEW(dev_priv)) {
1753                 divisor = vlv_dpll;
1754                 count = ARRAY_SIZE(vlv_dpll);
1755         }
1756
1757         if (divisor && count) {
1758                 for (i = 0; i < count; i++) {
1759                         if (pipe_config->port_clock == divisor[i].clock) {
1760                                 pipe_config->dpll = divisor[i].dpll;
1761                                 pipe_config->clock_set = true;
1762                                 break;
1763                         }
1764                 }
1765         }
1766 }
1767
1768 static void snprintf_int_array(char *str, size_t len,
1769                                const int *array, int nelem)
1770 {
1771         int i;
1772
1773         str[0] = '\0';
1774
1775         for (i = 0; i < nelem; i++) {
1776                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1777                 if (r >= len)
1778                         return;
1779                 str += r;
1780                 len -= r;
1781         }
1782 }
1783
1784 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1785 {
1786         char str[128]; /* FIXME: too big for stack? */
1787
1788         if ((drm_debug & DRM_UT_KMS) == 0)
1789                 return;
1790
1791         snprintf_int_array(str, sizeof(str),
1792                            intel_dp->source_rates, intel_dp->num_source_rates);
1793         DRM_DEBUG_KMS("source rates: %s\n", str);
1794
1795         snprintf_int_array(str, sizeof(str),
1796                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1797         DRM_DEBUG_KMS("sink rates: %s\n", str);
1798
1799         snprintf_int_array(str, sizeof(str),
1800                            intel_dp->common_rates, intel_dp->num_common_rates);
1801         DRM_DEBUG_KMS("common rates: %s\n", str);
1802 }
1803
1804 int
1805 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1806 {
1807         int len;
1808
1809         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1810         if (WARN_ON(len <= 0))
1811                 return 162000;
1812
1813         return intel_dp->common_rates[len - 1];
1814 }
1815
1816 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1817 {
1818         int i = intel_dp_rate_index(intel_dp->sink_rates,
1819                                     intel_dp->num_sink_rates, rate);
1820
1821         if (WARN_ON(i < 0))
1822                 i = 0;
1823
1824         return i;
1825 }
1826
1827 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1828                            u8 *link_bw, u8 *rate_select)
1829 {
1830         /* eDP 1.4 rate select method. */
1831         if (intel_dp->use_rate_select) {
1832                 *link_bw = 0;
1833                 *rate_select =
1834                         intel_dp_rate_select(intel_dp, port_clock);
1835         } else {
1836                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1837                 *rate_select = 0;
1838         }
1839 }
1840
1841 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1842                                          const struct intel_crtc_state *pipe_config)
1843 {
1844         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1845
1846         /* On TGL, FEC is supported on all Pipes */
1847         if (INTEL_GEN(dev_priv) >= 12)
1848                 return true;
1849
1850         if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
1851                 return true;
1852
1853         return false;
1854 }
1855
1856 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1857                                   const struct intel_crtc_state *pipe_config)
1858 {
1859         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1860                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
1861 }
1862
1863 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
1864                                          const struct intel_crtc_state *pipe_config)
1865 {
1866         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1867
1868         /* On TGL, DSC is supported on all Pipes */
1869         if (INTEL_GEN(dev_priv) >= 12)
1870                 return true;
1871
1872         if (INTEL_GEN(dev_priv) >= 10 &&
1873             pipe_config->cpu_transcoder != TRANSCODER_A)
1874                 return true;
1875
1876         return false;
1877 }
1878
1879 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1880                                   const struct intel_crtc_state *pipe_config)
1881 {
1882         if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable)
1883                 return false;
1884
1885         return intel_dp_source_supports_dsc(intel_dp, pipe_config) &&
1886                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
1887 }
1888
1889 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1890                                 struct intel_crtc_state *pipe_config)
1891 {
1892         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1893         struct intel_connector *intel_connector = intel_dp->attached_connector;
1894         int bpp, bpc;
1895
1896         bpp = pipe_config->pipe_bpp;
1897         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1898
1899         if (bpc > 0)
1900                 bpp = min(bpp, 3*bpc);
1901
1902         if (intel_dp_is_edp(intel_dp)) {
1903                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1904                 if (intel_connector->base.display_info.bpc == 0 &&
1905                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1906                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1907                                       dev_priv->vbt.edp.bpp);
1908                         bpp = dev_priv->vbt.edp.bpp;
1909                 }
1910         }
1911
1912         return bpp;
1913 }
1914
1915 /* Adjust link config limits based on compliance test requests. */
1916 void
1917 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1918                                   struct intel_crtc_state *pipe_config,
1919                                   struct link_config_limits *limits)
1920 {
1921         /* For DP Compliance we override the computed bpp for the pipe */
1922         if (intel_dp->compliance.test_data.bpc != 0) {
1923                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1924
1925                 limits->min_bpp = limits->max_bpp = bpp;
1926                 pipe_config->dither_force_disable = bpp == 6 * 3;
1927
1928                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1929         }
1930
1931         /* Use values requested by Compliance Test Request */
1932         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1933                 int index;
1934
1935                 /* Validate the compliance test data since max values
1936                  * might have changed due to link train fallback.
1937                  */
1938                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1939                                                intel_dp->compliance.test_lane_count)) {
1940                         index = intel_dp_rate_index(intel_dp->common_rates,
1941                                                     intel_dp->num_common_rates,
1942                                                     intel_dp->compliance.test_link_rate);
1943                         if (index >= 0)
1944                                 limits->min_clock = limits->max_clock = index;
1945                         limits->min_lane_count = limits->max_lane_count =
1946                                 intel_dp->compliance.test_lane_count;
1947                 }
1948         }
1949 }
1950
1951 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp)
1952 {
1953         /*
1954          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1955          * format of the number of bytes per pixel will be half the number
1956          * of bytes of RGB pixel.
1957          */
1958         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1959                 bpp /= 2;
1960
1961         return bpp;
1962 }
1963
1964 /* Optimize link config in order: max bpp, min clock, min lanes */
1965 static int
1966 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1967                                   struct intel_crtc_state *pipe_config,
1968                                   const struct link_config_limits *limits)
1969 {
1970         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1971         int bpp, clock, lane_count;
1972         int mode_rate, link_clock, link_avail;
1973
1974         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1975                 int output_bpp = intel_dp_output_bpp(pipe_config, bpp);
1976
1977                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1978                                                    output_bpp);
1979
1980                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1981                         for (lane_count = limits->min_lane_count;
1982                              lane_count <= limits->max_lane_count;
1983                              lane_count <<= 1) {
1984                                 link_clock = intel_dp->common_rates[clock];
1985                                 link_avail = intel_dp_max_data_rate(link_clock,
1986                                                                     lane_count);
1987
1988                                 if (mode_rate <= link_avail) {
1989                                         pipe_config->lane_count = lane_count;
1990                                         pipe_config->pipe_bpp = bpp;
1991                                         pipe_config->port_clock = link_clock;
1992
1993                                         return 0;
1994                                 }
1995                         }
1996                 }
1997         }
1998
1999         return -EINVAL;
2000 }
2001
2002 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2003 {
2004         int i, num_bpc;
2005         u8 dsc_bpc[3] = {0};
2006
2007         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2008                                                        dsc_bpc);
2009         for (i = 0; i < num_bpc; i++) {
2010                 if (dsc_max_bpc >= dsc_bpc[i])
2011                         return dsc_bpc[i] * 3;
2012         }
2013
2014         return 0;
2015 }
2016
2017 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2018                                        struct intel_crtc_state *pipe_config,
2019                                        struct drm_connector_state *conn_state,
2020                                        struct link_config_limits *limits)
2021 {
2022         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2023         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2024         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2025         u8 dsc_max_bpc;
2026         int pipe_bpp;
2027         int ret;
2028
2029         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2030                 intel_dp_supports_fec(intel_dp, pipe_config);
2031
2032         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2033                 return -EINVAL;
2034
2035         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2036         if (INTEL_GEN(dev_priv) >= 12)
2037                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2038         else
2039                 dsc_max_bpc = min_t(u8, 10,
2040                                     conn_state->max_requested_bpc);
2041
2042         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2043
2044         /* Min Input BPC for ICL+ is 8 */
2045         if (pipe_bpp < 8 * 3) {
2046                 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
2047                 return -EINVAL;
2048         }
2049
2050         /*
2051          * For now enable DSC for max bpp, max link rate, max lane count.
2052          * Optimize this later for the minimum possible link rate/lane count
2053          * with DSC enabled for the requested mode.
2054          */
2055         pipe_config->pipe_bpp = pipe_bpp;
2056         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2057         pipe_config->lane_count = limits->max_lane_count;
2058
2059         if (intel_dp_is_edp(intel_dp)) {
2060                 pipe_config->dsc_params.compressed_bpp =
2061                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2062                               pipe_config->pipe_bpp);
2063                 pipe_config->dsc_params.slice_count =
2064                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2065                                                         true);
2066         } else {
2067                 u16 dsc_max_output_bpp;
2068                 u8 dsc_dp_slice_count;
2069
2070                 dsc_max_output_bpp =
2071                         intel_dp_dsc_get_output_bpp(dev_priv,
2072                                                     pipe_config->port_clock,
2073                                                     pipe_config->lane_count,
2074                                                     adjusted_mode->crtc_clock,
2075                                                     adjusted_mode->crtc_hdisplay);
2076                 dsc_dp_slice_count =
2077                         intel_dp_dsc_get_slice_count(intel_dp,
2078                                                      adjusted_mode->crtc_clock,
2079                                                      adjusted_mode->crtc_hdisplay);
2080                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2081                         DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n");
2082                         return -EINVAL;
2083                 }
2084                 pipe_config->dsc_params.compressed_bpp = min_t(u16,
2085                                                                dsc_max_output_bpp >> 4,
2086                                                                pipe_config->pipe_bpp);
2087                 pipe_config->dsc_params.slice_count = dsc_dp_slice_count;
2088         }
2089         /*
2090          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2091          * is greater than the maximum Cdclock and if slice count is even
2092          * then we need to use 2 VDSC instances.
2093          */
2094         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
2095                 if (pipe_config->dsc_params.slice_count > 1) {
2096                         pipe_config->dsc_params.dsc_split = true;
2097                 } else {
2098                         DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
2099                         return -EINVAL;
2100                 }
2101         }
2102
2103         ret = intel_dp_compute_dsc_params(intel_dp, pipe_config);
2104         if (ret < 0) {
2105                 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
2106                               "Compressed BPP = %d\n",
2107                               pipe_config->pipe_bpp,
2108                               pipe_config->dsc_params.compressed_bpp);
2109                 return ret;
2110         }
2111
2112         pipe_config->dsc_params.compression_enable = true;
2113         DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d "
2114                       "Compressed Bpp = %d Slice Count = %d\n",
2115                       pipe_config->pipe_bpp,
2116                       pipe_config->dsc_params.compressed_bpp,
2117                       pipe_config->dsc_params.slice_count);
2118
2119         return 0;
2120 }
2121
2122 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
2123 {
2124         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
2125                 return 6 * 3;
2126         else
2127                 return 8 * 3;
2128 }
2129
2130 static int
2131 intel_dp_compute_link_config(struct intel_encoder *encoder,
2132                              struct intel_crtc_state *pipe_config,
2133                              struct drm_connector_state *conn_state)
2134 {
2135         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2136         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2137         struct link_config_limits limits;
2138         int common_len;
2139         int ret;
2140
2141         common_len = intel_dp_common_len_rate_limit(intel_dp,
2142                                                     intel_dp->max_link_rate);
2143
2144         /* No common link rates between source and sink */
2145         WARN_ON(common_len <= 0);
2146
2147         limits.min_clock = 0;
2148         limits.max_clock = common_len - 1;
2149
2150         limits.min_lane_count = 1;
2151         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2152
2153         limits.min_bpp = intel_dp_min_bpp(pipe_config);
2154         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
2155
2156         if (intel_dp_is_edp(intel_dp)) {
2157                 /*
2158                  * Use the maximum clock and number of lanes the eDP panel
2159                  * advertizes being capable of. The panels are generally
2160                  * designed to support only a single clock and lane
2161                  * configuration, and typically these values correspond to the
2162                  * native resolution of the panel.
2163                  */
2164                 limits.min_lane_count = limits.max_lane_count;
2165                 limits.min_clock = limits.max_clock;
2166         }
2167
2168         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2169
2170         DRM_DEBUG_KMS("DP link computation with max lane count %i "
2171                       "max rate %d max bpp %d pixel clock %iKHz\n",
2172                       limits.max_lane_count,
2173                       intel_dp->common_rates[limits.max_clock],
2174                       limits.max_bpp, adjusted_mode->crtc_clock);
2175
2176         /*
2177          * Optimize for slow and wide. This is the place to add alternative
2178          * optimization policy.
2179          */
2180         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2181
2182         /* enable compression if the mode doesn't fit available BW */
2183         DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en);
2184         if (ret || intel_dp->force_dsc_en) {
2185                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2186                                                   conn_state, &limits);
2187                 if (ret < 0)
2188                         return ret;
2189         }
2190
2191         if (pipe_config->dsc_params.compression_enable) {
2192                 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2193                               pipe_config->lane_count, pipe_config->port_clock,
2194                               pipe_config->pipe_bpp,
2195                               pipe_config->dsc_params.compressed_bpp);
2196
2197                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2198                               intel_dp_link_required(adjusted_mode->crtc_clock,
2199                                                      pipe_config->dsc_params.compressed_bpp),
2200                               intel_dp_max_data_rate(pipe_config->port_clock,
2201                                                      pipe_config->lane_count));
2202         } else {
2203                 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
2204                               pipe_config->lane_count, pipe_config->port_clock,
2205                               pipe_config->pipe_bpp);
2206
2207                 DRM_DEBUG_KMS("DP link rate required %i available %i\n",
2208                               intel_dp_link_required(adjusted_mode->crtc_clock,
2209                                                      pipe_config->pipe_bpp),
2210                               intel_dp_max_data_rate(pipe_config->port_clock,
2211                                                      pipe_config->lane_count));
2212         }
2213         return 0;
2214 }
2215
2216 static int
2217 intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
2218                          struct drm_connector *connector,
2219                          struct intel_crtc_state *crtc_state)
2220 {
2221         const struct drm_display_info *info = &connector->display_info;
2222         const struct drm_display_mode *adjusted_mode =
2223                 &crtc_state->base.adjusted_mode;
2224         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2225         int ret;
2226
2227         if (!drm_mode_is_420_only(info, adjusted_mode) ||
2228             !intel_dp_get_colorimetry_status(intel_dp) ||
2229             !connector->ycbcr_420_allowed)
2230                 return 0;
2231
2232         crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2233
2234         /* YCBCR 420 output conversion needs a scaler */
2235         ret = skl_update_scaler_crtc(crtc_state);
2236         if (ret) {
2237                 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
2238                 return ret;
2239         }
2240
2241         intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
2242
2243         return 0;
2244 }
2245
2246 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2247                                   const struct drm_connector_state *conn_state)
2248 {
2249         const struct intel_digital_connector_state *intel_conn_state =
2250                 to_intel_digital_connector_state(conn_state);
2251         const struct drm_display_mode *adjusted_mode =
2252                 &crtc_state->base.adjusted_mode;
2253
2254         /*
2255          * Our YCbCr output is always limited range.
2256          * crtc_state->limited_color_range only applies to RGB,
2257          * and it must never be set for YCbCr or we risk setting
2258          * some conflicting bits in PIPECONF which will mess up
2259          * the colors on the monitor.
2260          */
2261         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2262                 return false;
2263
2264         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2265                 /*
2266                  * See:
2267                  * CEA-861-E - 5.1 Default Encoding Parameters
2268                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2269                  */
2270                 return crtc_state->pipe_bpp != 18 &&
2271                         drm_default_rgb_quant_range(adjusted_mode) ==
2272                         HDMI_QUANTIZATION_RANGE_LIMITED;
2273         } else {
2274                 return intel_conn_state->broadcast_rgb ==
2275                         INTEL_BROADCAST_RGB_LIMITED;
2276         }
2277 }
2278
2279 int
2280 intel_dp_compute_config(struct intel_encoder *encoder,
2281                         struct intel_crtc_state *pipe_config,
2282                         struct drm_connector_state *conn_state)
2283 {
2284         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2285         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2286         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2287         struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
2288         enum port port = encoder->port;
2289         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
2290         struct intel_connector *intel_connector = intel_dp->attached_connector;
2291         struct intel_digital_connector_state *intel_conn_state =
2292                 to_intel_digital_connector_state(conn_state);
2293         bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
2294                                            DP_DPCD_QUIRK_CONSTANT_N);
2295         int ret = 0, output_bpp;
2296
2297         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2298                 pipe_config->has_pch_encoder = true;
2299
2300         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2301         if (lspcon->active)
2302                 lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
2303         else
2304                 ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
2305                                                pipe_config);
2306
2307         if (ret)
2308                 return ret;
2309
2310         pipe_config->has_drrs = false;
2311         if (IS_G4X(dev_priv) || port == PORT_A)
2312                 pipe_config->has_audio = false;
2313         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2314                 pipe_config->has_audio = intel_dp->has_audio;
2315         else
2316                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2317
2318         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2319                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2320                                        adjusted_mode);
2321
2322                 if (INTEL_GEN(dev_priv) >= 9) {
2323                         ret = skl_update_scaler_crtc(pipe_config);
2324                         if (ret)
2325                                 return ret;
2326                 }
2327
2328                 if (HAS_GMCH(dev_priv))
2329                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
2330                                                  conn_state->scaling_mode);
2331                 else
2332                         intel_pch_panel_fitting(intel_crtc, pipe_config,
2333                                                 conn_state->scaling_mode);
2334         }
2335
2336         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2337                 return -EINVAL;
2338
2339         if (HAS_GMCH(dev_priv) &&
2340             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2341                 return -EINVAL;
2342
2343         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2344                 return -EINVAL;
2345
2346         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2347         if (ret < 0)
2348                 return ret;
2349
2350         pipe_config->limited_color_range =
2351                 intel_dp_limited_color_range(pipe_config, conn_state);
2352
2353         if (pipe_config->dsc_params.compression_enable)
2354                 output_bpp = pipe_config->dsc_params.compressed_bpp;
2355         else
2356                 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp);
2357
2358         intel_link_compute_m_n(output_bpp,
2359                                pipe_config->lane_count,
2360                                adjusted_mode->crtc_clock,
2361                                pipe_config->port_clock,
2362                                &pipe_config->dp_m_n,
2363                                constant_n, pipe_config->fec_enable);
2364
2365         if (intel_connector->panel.downclock_mode != NULL &&
2366                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
2367                         pipe_config->has_drrs = true;
2368                         intel_link_compute_m_n(output_bpp,
2369                                                pipe_config->lane_count,
2370                                                intel_connector->panel.downclock_mode->clock,
2371                                                pipe_config->port_clock,
2372                                                &pipe_config->dp_m2_n2,
2373                                                constant_n, pipe_config->fec_enable);
2374         }
2375
2376         if (!HAS_DDI(dev_priv))
2377                 intel_dp_set_clock(encoder, pipe_config);
2378
2379         intel_psr_compute_config(intel_dp, pipe_config);
2380
2381         intel_hdcp_transcoder_config(intel_connector,
2382                                      pipe_config->cpu_transcoder);
2383
2384         return 0;
2385 }
2386
2387 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2388                               int link_rate, u8 lane_count,
2389                               bool link_mst)
2390 {
2391         intel_dp->link_trained = false;
2392         intel_dp->link_rate = link_rate;
2393         intel_dp->lane_count = lane_count;
2394         intel_dp->link_mst = link_mst;
2395 }
2396
2397 static void intel_dp_prepare(struct intel_encoder *encoder,
2398                              const struct intel_crtc_state *pipe_config)
2399 {
2400         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2401         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2402         enum port port = encoder->port;
2403         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2404         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2405
2406         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
2407                                  pipe_config->lane_count,
2408                                  intel_crtc_has_type(pipe_config,
2409                                                      INTEL_OUTPUT_DP_MST));
2410
2411         intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
2412         intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
2413
2414         /*
2415          * There are four kinds of DP registers:
2416          *
2417          *      IBX PCH
2418          *      SNB CPU
2419          *      IVB CPU
2420          *      CPT PCH
2421          *
2422          * IBX PCH and CPU are the same for almost everything,
2423          * except that the CPU DP PLL is configured in this
2424          * register
2425          *
2426          * CPT PCH is quite different, having many bits moved
2427          * to the TRANS_DP_CTL register instead. That
2428          * configuration happens (oddly) in ironlake_pch_enable
2429          */
2430
2431         /* Preserve the BIOS-computed detected bit. This is
2432          * supposed to be read-only.
2433          */
2434         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
2435
2436         /* Handle DP bits in common between all three register formats */
2437         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2438         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2439
2440         /* Split out the IBX/CPU vs CPT settings */
2441
2442         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2443                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2444                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2445                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2446                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2447                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2448
2449                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2450                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2451
2452                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2453         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2454                 u32 trans_dp;
2455
2456                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2457
2458                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2459                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2460                         trans_dp |= TRANS_DP_ENH_FRAMING;
2461                 else
2462                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2463                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2464         } else {
2465                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2466                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2467
2468                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2469                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2470                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2471                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2472                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2473
2474                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2475                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2476
2477                 if (IS_CHERRYVIEW(dev_priv))
2478                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2479                 else
2480                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2481         }
2482 }
2483
2484 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2485 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2486
2487 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2488 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2489
2490 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2491 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2492
2493 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2494
2495 static void wait_panel_status(struct intel_dp *intel_dp,
2496                                        u32 mask,
2497                                        u32 value)
2498 {
2499         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2500         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2501
2502         lockdep_assert_held(&dev_priv->pps_mutex);
2503
2504         intel_pps_verify_state(intel_dp);
2505
2506         pp_stat_reg = _pp_stat_reg(intel_dp);
2507         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2508
2509         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2510                         mask, value,
2511                         I915_READ(pp_stat_reg),
2512                         I915_READ(pp_ctrl_reg));
2513
2514         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2515                                        mask, value, 5000))
2516                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2517                                 I915_READ(pp_stat_reg),
2518                                 I915_READ(pp_ctrl_reg));
2519
2520         DRM_DEBUG_KMS("Wait complete\n");
2521 }
2522
2523 static void wait_panel_on(struct intel_dp *intel_dp)
2524 {
2525         DRM_DEBUG_KMS("Wait for panel power on\n");
2526         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2527 }
2528
2529 static void wait_panel_off(struct intel_dp *intel_dp)
2530 {
2531         DRM_DEBUG_KMS("Wait for panel power off time\n");
2532         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2533 }
2534
2535 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2536 {
2537         ktime_t panel_power_on_time;
2538         s64 panel_power_off_duration;
2539
2540         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2541
2542         /* take the difference of currrent time and panel power off time
2543          * and then make panel wait for t11_t12 if needed. */
2544         panel_power_on_time = ktime_get_boottime();
2545         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2546
2547         /* When we disable the VDD override bit last we have to do the manual
2548          * wait. */
2549         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2550                 wait_remaining_ms_from_jiffies(jiffies,
2551                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2552
2553         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2554 }
2555
2556 static void wait_backlight_on(struct intel_dp *intel_dp)
2557 {
2558         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2559                                        intel_dp->backlight_on_delay);
2560 }
2561
2562 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2563 {
2564         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2565                                        intel_dp->backlight_off_delay);
2566 }
2567
2568 /* Read the current pp_control value, unlocking the register if it
2569  * is locked
2570  */
2571
2572 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2573 {
2574         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2575         u32 control;
2576
2577         lockdep_assert_held(&dev_priv->pps_mutex);
2578
2579         control = I915_READ(_pp_ctrl_reg(intel_dp));
2580         if (WARN_ON(!HAS_DDI(dev_priv) &&
2581                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2582                 control &= ~PANEL_UNLOCK_MASK;
2583                 control |= PANEL_UNLOCK_REGS;
2584         }
2585         return control;
2586 }
2587
2588 /*
2589  * Must be paired with edp_panel_vdd_off().
2590  * Must hold pps_mutex around the whole on/off sequence.
2591  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2592  */
2593 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2594 {
2595         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2596         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2597         u32 pp;
2598         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2599         bool need_to_disable = !intel_dp->want_panel_vdd;
2600
2601         lockdep_assert_held(&dev_priv->pps_mutex);
2602
2603         if (!intel_dp_is_edp(intel_dp))
2604                 return false;
2605
2606         cancel_delayed_work(&intel_dp->panel_vdd_work);
2607         intel_dp->want_panel_vdd = true;
2608
2609         if (edp_have_panel_vdd(intel_dp))
2610                 return need_to_disable;
2611
2612         intel_display_power_get(dev_priv,
2613                                 intel_aux_power_domain(intel_dig_port));
2614
2615         DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD on\n",
2616                       intel_dig_port->base.base.base.id,
2617                       intel_dig_port->base.base.name);
2618
2619         if (!edp_have_panel_power(intel_dp))
2620                 wait_panel_power_cycle(intel_dp);
2621
2622         pp = ironlake_get_pp_control(intel_dp);
2623         pp |= EDP_FORCE_VDD;
2624
2625         pp_stat_reg = _pp_stat_reg(intel_dp);
2626         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2627
2628         I915_WRITE(pp_ctrl_reg, pp);
2629         POSTING_READ(pp_ctrl_reg);
2630         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2631                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2632         /*
2633          * If the panel wasn't on, delay before accessing aux channel
2634          */
2635         if (!edp_have_panel_power(intel_dp)) {
2636                 DRM_DEBUG_KMS("[ENCODER:%d:%s] panel power wasn't enabled\n",
2637                               intel_dig_port->base.base.base.id,
2638                               intel_dig_port->base.base.name);
2639                 msleep(intel_dp->panel_power_up_delay);
2640         }
2641
2642         return need_to_disable;
2643 }
2644
2645 /*
2646  * Must be paired with intel_edp_panel_vdd_off() or
2647  * intel_edp_panel_off().
2648  * Nested calls to these functions are not allowed since
2649  * we drop the lock. Caller must use some higher level
2650  * locking to prevent nested calls from other threads.
2651  */
2652 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2653 {
2654         intel_wakeref_t wakeref;
2655         bool vdd;
2656
2657         if (!intel_dp_is_edp(intel_dp))
2658                 return;
2659
2660         vdd = false;
2661         with_pps_lock(intel_dp, wakeref)
2662                 vdd = edp_panel_vdd_on(intel_dp);
2663         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
2664                         dp_to_dig_port(intel_dp)->base.base.base.id,
2665                         dp_to_dig_port(intel_dp)->base.base.name);
2666 }
2667
2668 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2669 {
2670         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2671         struct intel_digital_port *intel_dig_port =
2672                 dp_to_dig_port(intel_dp);
2673         u32 pp;
2674         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2675
2676         lockdep_assert_held(&dev_priv->pps_mutex);
2677
2678         WARN_ON(intel_dp->want_panel_vdd);
2679
2680         if (!edp_have_panel_vdd(intel_dp))
2681                 return;
2682
2683         DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD off\n",
2684                       intel_dig_port->base.base.base.id,
2685                       intel_dig_port->base.base.name);
2686
2687         pp = ironlake_get_pp_control(intel_dp);
2688         pp &= ~EDP_FORCE_VDD;
2689
2690         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2691         pp_stat_reg = _pp_stat_reg(intel_dp);
2692
2693         I915_WRITE(pp_ctrl_reg, pp);
2694         POSTING_READ(pp_ctrl_reg);
2695
2696         /* Make sure sequencer is idle before allowing subsequent activity */
2697         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2698         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2699
2700         if ((pp & PANEL_POWER_ON) == 0)
2701                 intel_dp->panel_power_off_time = ktime_get_boottime();
2702
2703         intel_display_power_put_unchecked(dev_priv,
2704                                           intel_aux_power_domain(intel_dig_port));
2705 }
2706
2707 static void edp_panel_vdd_work(struct work_struct *__work)
2708 {
2709         struct intel_dp *intel_dp =
2710                 container_of(to_delayed_work(__work),
2711                              struct intel_dp, panel_vdd_work);
2712         intel_wakeref_t wakeref;
2713
2714         with_pps_lock(intel_dp, wakeref) {
2715                 if (!intel_dp->want_panel_vdd)
2716                         edp_panel_vdd_off_sync(intel_dp);
2717         }
2718 }
2719
2720 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2721 {
2722         unsigned long delay;
2723
2724         /*
2725          * Queue the timer to fire a long time from now (relative to the power
2726          * down delay) to keep the panel power up across a sequence of
2727          * operations.
2728          */
2729         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2730         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2731 }
2732
2733 /*
2734  * Must be paired with edp_panel_vdd_on().
2735  * Must hold pps_mutex around the whole on/off sequence.
2736  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2737  */
2738 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2739 {
2740         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2741
2742         lockdep_assert_held(&dev_priv->pps_mutex);
2743
2744         if (!intel_dp_is_edp(intel_dp))
2745                 return;
2746
2747         I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
2748                         dp_to_dig_port(intel_dp)->base.base.base.id,
2749                         dp_to_dig_port(intel_dp)->base.base.name);
2750
2751         intel_dp->want_panel_vdd = false;
2752
2753         if (sync)
2754                 edp_panel_vdd_off_sync(intel_dp);
2755         else
2756                 edp_panel_vdd_schedule_off(intel_dp);
2757 }
2758
2759 static void edp_panel_on(struct intel_dp *intel_dp)
2760 {
2761         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2762         u32 pp;
2763         i915_reg_t pp_ctrl_reg;
2764
2765         lockdep_assert_held(&dev_priv->pps_mutex);
2766
2767         if (!intel_dp_is_edp(intel_dp))
2768                 return;
2769
2770         DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power on\n",
2771                       dp_to_dig_port(intel_dp)->base.base.base.id,
2772                       dp_to_dig_port(intel_dp)->base.base.name);
2773
2774         if (WARN(edp_have_panel_power(intel_dp),
2775                  "[ENCODER:%d:%s] panel power already on\n",
2776                  dp_to_dig_port(intel_dp)->base.base.base.id,
2777                  dp_to_dig_port(intel_dp)->base.base.name))
2778                 return;
2779
2780         wait_panel_power_cycle(intel_dp);
2781
2782         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2783         pp = ironlake_get_pp_control(intel_dp);
2784         if (IS_GEN(dev_priv, 5)) {
2785                 /* ILK workaround: disable reset around power sequence */
2786                 pp &= ~PANEL_POWER_RESET;
2787                 I915_WRITE(pp_ctrl_reg, pp);
2788                 POSTING_READ(pp_ctrl_reg);
2789         }
2790
2791         pp |= PANEL_POWER_ON;
2792         if (!IS_GEN(dev_priv, 5))
2793                 pp |= PANEL_POWER_RESET;
2794
2795         I915_WRITE(pp_ctrl_reg, pp);
2796         POSTING_READ(pp_ctrl_reg);
2797
2798         wait_panel_on(intel_dp);
2799         intel_dp->last_power_on = jiffies;
2800
2801         if (IS_GEN(dev_priv, 5)) {
2802                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2803                 I915_WRITE(pp_ctrl_reg, pp);
2804                 POSTING_READ(pp_ctrl_reg);
2805         }
2806 }
2807
2808 void intel_edp_panel_on(struct intel_dp *intel_dp)
2809 {
2810         intel_wakeref_t wakeref;
2811
2812         if (!intel_dp_is_edp(intel_dp))
2813                 return;
2814
2815         with_pps_lock(intel_dp, wakeref)
2816                 edp_panel_on(intel_dp);
2817 }
2818
2819
2820 static void edp_panel_off(struct intel_dp *intel_dp)
2821 {
2822         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2823         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2824         u32 pp;
2825         i915_reg_t pp_ctrl_reg;
2826
2827         lockdep_assert_held(&dev_priv->pps_mutex);
2828
2829         if (!intel_dp_is_edp(intel_dp))
2830                 return;
2831
2832         DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power off\n",
2833                       dig_port->base.base.base.id, dig_port->base.base.name);
2834
2835         WARN(!intel_dp->want_panel_vdd, "Need [ENCODER:%d:%s] VDD to turn off panel\n",
2836              dig_port->base.base.base.id, dig_port->base.base.name);
2837
2838         pp = ironlake_get_pp_control(intel_dp);
2839         /* We need to switch off panel power _and_ force vdd, for otherwise some
2840          * panels get very unhappy and cease to work. */
2841         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2842                 EDP_BLC_ENABLE);
2843
2844         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2845
2846         intel_dp->want_panel_vdd = false;
2847
2848         I915_WRITE(pp_ctrl_reg, pp);
2849         POSTING_READ(pp_ctrl_reg);
2850
2851         wait_panel_off(intel_dp);
2852         intel_dp->panel_power_off_time = ktime_get_boottime();
2853
2854         /* We got a reference when we enabled the VDD. */
2855         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
2856 }
2857
2858 void intel_edp_panel_off(struct intel_dp *intel_dp)
2859 {
2860         intel_wakeref_t wakeref;
2861
2862         if (!intel_dp_is_edp(intel_dp))
2863                 return;
2864
2865         with_pps_lock(intel_dp, wakeref)
2866                 edp_panel_off(intel_dp);
2867 }
2868
2869 /* Enable backlight in the panel power control. */
2870 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2871 {
2872         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2873         intel_wakeref_t wakeref;
2874
2875         /*
2876          * If we enable the backlight right away following a panel power
2877          * on, we may see slight flicker as the panel syncs with the eDP
2878          * link.  So delay a bit to make sure the image is solid before
2879          * allowing it to appear.
2880          */
2881         wait_backlight_on(intel_dp);
2882
2883         with_pps_lock(intel_dp, wakeref) {
2884                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2885                 u32 pp;
2886
2887                 pp = ironlake_get_pp_control(intel_dp);
2888                 pp |= EDP_BLC_ENABLE;
2889
2890                 I915_WRITE(pp_ctrl_reg, pp);
2891                 POSTING_READ(pp_ctrl_reg);
2892         }
2893 }
2894
2895 /* Enable backlight PWM and backlight PP control. */
2896 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2897                             const struct drm_connector_state *conn_state)
2898 {
2899         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2900
2901         if (!intel_dp_is_edp(intel_dp))
2902                 return;
2903
2904         DRM_DEBUG_KMS("\n");
2905
2906         intel_panel_enable_backlight(crtc_state, conn_state);
2907         _intel_edp_backlight_on(intel_dp);
2908 }
2909
2910 /* Disable backlight in the panel power control. */
2911 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2912 {
2913         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2914         intel_wakeref_t wakeref;
2915
2916         if (!intel_dp_is_edp(intel_dp))
2917                 return;
2918
2919         with_pps_lock(intel_dp, wakeref) {
2920                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2921                 u32 pp;
2922
2923                 pp = ironlake_get_pp_control(intel_dp);
2924                 pp &= ~EDP_BLC_ENABLE;
2925
2926                 I915_WRITE(pp_ctrl_reg, pp);
2927                 POSTING_READ(pp_ctrl_reg);
2928         }
2929
2930         intel_dp->last_backlight_off = jiffies;
2931         edp_wait_backlight_off(intel_dp);
2932 }
2933
2934 /* Disable backlight PP control and backlight PWM. */
2935 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2936 {
2937         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2938
2939         if (!intel_dp_is_edp(intel_dp))
2940                 return;
2941
2942         DRM_DEBUG_KMS("\n");
2943
2944         _intel_edp_backlight_off(intel_dp);
2945         intel_panel_disable_backlight(old_conn_state);
2946 }
2947
2948 /*
2949  * Hook for controlling the panel power control backlight through the bl_power
2950  * sysfs attribute. Take care to handle multiple calls.
2951  */
2952 static void intel_edp_backlight_power(struct intel_connector *connector,
2953                                       bool enable)
2954 {
2955         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2956         intel_wakeref_t wakeref;
2957         bool is_enabled;
2958
2959         is_enabled = false;
2960         with_pps_lock(intel_dp, wakeref)
2961                 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2962         if (is_enabled == enable)
2963                 return;
2964
2965         DRM_DEBUG_KMS("panel power control backlight %s\n",
2966                       enable ? "enable" : "disable");
2967
2968         if (enable)
2969                 _intel_edp_backlight_on(intel_dp);
2970         else
2971                 _intel_edp_backlight_off(intel_dp);
2972 }
2973
2974 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2975 {
2976         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2977         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2978         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2979
2980         I915_STATE_WARN(cur_state != state,
2981                         "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
2982                         dig_port->base.base.base.id, dig_port->base.base.name,
2983                         onoff(state), onoff(cur_state));
2984 }
2985 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2986
2987 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2988 {
2989         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2990
2991         I915_STATE_WARN(cur_state != state,
2992                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2993                         onoff(state), onoff(cur_state));
2994 }
2995 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2996 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2997
2998 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2999                                 const struct intel_crtc_state *pipe_config)
3000 {
3001         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3002         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3003
3004         assert_pipe_disabled(dev_priv, crtc->pipe);
3005         assert_dp_port_disabled(intel_dp);
3006         assert_edp_pll_disabled(dev_priv);
3007
3008         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
3009                       pipe_config->port_clock);
3010
3011         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3012
3013         if (pipe_config->port_clock == 162000)
3014                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3015         else
3016                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3017
3018         I915_WRITE(DP_A, intel_dp->DP);
3019         POSTING_READ(DP_A);
3020         udelay(500);
3021
3022         /*
3023          * [DevILK] Work around required when enabling DP PLL
3024          * while a pipe is enabled going to FDI:
3025          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3026          * 2. Program DP PLL enable
3027          */
3028         if (IS_GEN(dev_priv, 5))
3029                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3030
3031         intel_dp->DP |= DP_PLL_ENABLE;
3032
3033         I915_WRITE(DP_A, intel_dp->DP);
3034         POSTING_READ(DP_A);
3035         udelay(200);
3036 }
3037
3038 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
3039                                  const struct intel_crtc_state *old_crtc_state)
3040 {
3041         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3042         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3043
3044         assert_pipe_disabled(dev_priv, crtc->pipe);
3045         assert_dp_port_disabled(intel_dp);
3046         assert_edp_pll_enabled(dev_priv);
3047
3048         DRM_DEBUG_KMS("disabling eDP PLL\n");
3049
3050         intel_dp->DP &= ~DP_PLL_ENABLE;
3051
3052         I915_WRITE(DP_A, intel_dp->DP);
3053         POSTING_READ(DP_A);
3054         udelay(200);
3055 }
3056
3057 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3058 {
3059         /*
3060          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3061          * be capable of signalling downstream hpd with a long pulse.
3062          * Whether or not that means D3 is safe to use is not clear,
3063          * but let's assume so until proven otherwise.
3064          *
3065          * FIXME should really check all downstream ports...
3066          */
3067         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3068                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
3069                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3070 }
3071
3072 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3073                                            const struct intel_crtc_state *crtc_state,
3074                                            bool enable)
3075 {
3076         int ret;
3077
3078         if (!crtc_state->dsc_params.compression_enable)
3079                 return;
3080
3081         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3082                                  enable ? DP_DECOMPRESSION_EN : 0);
3083         if (ret < 0)
3084                 DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
3085                               enable ? "enable" : "disable");
3086 }
3087
3088 /* If the sink supports it, try to set the power state appropriately */
3089 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
3090 {
3091         int ret, i;
3092
3093         /* Should have a valid DPCD by this point */
3094         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3095                 return;
3096
3097         if (mode != DRM_MODE_DPMS_ON) {
3098                 if (downstream_hpd_needs_d0(intel_dp))
3099                         return;
3100
3101                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3102                                          DP_SET_POWER_D3);
3103         } else {
3104                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3105
3106                 /*
3107                  * When turning on, we need to retry for 1ms to give the sink
3108                  * time to wake up.
3109                  */
3110                 for (i = 0; i < 3; i++) {
3111                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
3112                                                  DP_SET_POWER_D0);
3113                         if (ret == 1)
3114                                 break;
3115                         msleep(1);
3116                 }
3117
3118                 if (ret == 1 && lspcon->active)
3119                         lspcon_wait_pcon_mode(lspcon);
3120         }
3121
3122         if (ret != 1)
3123                 DRM_DEBUG_KMS("failed to %s sink power state\n",
3124                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
3125 }
3126
3127 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3128                                  enum port port, enum pipe *pipe)
3129 {
3130         enum pipe p;
3131
3132         for_each_pipe(dev_priv, p) {
3133                 u32 val = I915_READ(TRANS_DP_CTL(p));
3134
3135                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3136                         *pipe = p;
3137                         return true;
3138                 }
3139         }
3140
3141         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
3142
3143         /* must initialize pipe to something for the asserts */
3144         *pipe = PIPE_A;
3145
3146         return false;
3147 }
3148
3149 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3150                            i915_reg_t dp_reg, enum port port,
3151                            enum pipe *pipe)
3152 {
3153         bool ret;
3154         u32 val;
3155
3156         val = I915_READ(dp_reg);
3157
3158         ret = val & DP_PORT_EN;
3159
3160         /* asserts want to know the pipe even if the port is disabled */
3161         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3162                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3163         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3164                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3165         else if (IS_CHERRYVIEW(dev_priv))
3166                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3167         else
3168                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3169
3170         return ret;
3171 }
3172
3173 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3174                                   enum pipe *pipe)
3175 {
3176         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3177         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3178         intel_wakeref_t wakeref;
3179         bool ret;
3180
3181         wakeref = intel_display_power_get_if_enabled(dev_priv,
3182                                                      encoder->power_domain);
3183         if (!wakeref)
3184                 return false;
3185
3186         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3187                                     encoder->port, pipe);
3188
3189         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3190
3191         return ret;
3192 }
3193
3194 static void intel_dp_get_config(struct intel_encoder *encoder,
3195                                 struct intel_crtc_state *pipe_config)
3196 {
3197         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3198         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3199         u32 tmp, flags = 0;
3200         enum port port = encoder->port;
3201         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3202
3203         if (encoder->type == INTEL_OUTPUT_EDP)
3204                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3205         else
3206                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3207
3208         tmp = I915_READ(intel_dp->output_reg);
3209
3210         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3211
3212         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3213                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
3214
3215                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3216                         flags |= DRM_MODE_FLAG_PHSYNC;
3217                 else
3218                         flags |= DRM_MODE_FLAG_NHSYNC;
3219
3220                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3221                         flags |= DRM_MODE_FLAG_PVSYNC;
3222                 else
3223                         flags |= DRM_MODE_FLAG_NVSYNC;
3224         } else {
3225                 if (tmp & DP_SYNC_HS_HIGH)
3226                         flags |= DRM_MODE_FLAG_PHSYNC;
3227                 else
3228                         flags |= DRM_MODE_FLAG_NHSYNC;
3229
3230                 if (tmp & DP_SYNC_VS_HIGH)
3231                         flags |= DRM_MODE_FLAG_PVSYNC;
3232                 else
3233                         flags |= DRM_MODE_FLAG_NVSYNC;
3234         }
3235
3236         pipe_config->base.adjusted_mode.flags |= flags;
3237
3238         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3239                 pipe_config->limited_color_range = true;
3240
3241         pipe_config->lane_count =
3242                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3243
3244         intel_dp_get_m_n(crtc, pipe_config);
3245
3246         if (port == PORT_A) {
3247                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3248                         pipe_config->port_clock = 162000;
3249                 else
3250                         pipe_config->port_clock = 270000;
3251         }
3252
3253         pipe_config->base.adjusted_mode.crtc_clock =
3254                 intel_dotclock_calculate(pipe_config->port_clock,
3255                                          &pipe_config->dp_m_n);
3256
3257         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3258             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3259                 /*
3260                  * This is a big fat ugly hack.
3261                  *
3262                  * Some machines in UEFI boot mode provide us a VBT that has 18
3263                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3264                  * unknown we fail to light up. Yet the same BIOS boots up with
3265                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3266                  * max, not what it tells us to use.
3267                  *
3268                  * Note: This will still be broken if the eDP panel is not lit
3269                  * up by the BIOS, and thus we can't get the mode at module
3270                  * load.
3271                  */
3272                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3273                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3274                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3275         }
3276 }
3277
3278 static void intel_disable_dp(struct intel_encoder *encoder,
3279                              const struct intel_crtc_state *old_crtc_state,
3280                              const struct drm_connector_state *old_conn_state)
3281 {
3282         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3283
3284         intel_dp->link_trained = false;
3285
3286         if (old_crtc_state->has_audio)
3287                 intel_audio_codec_disable(encoder,
3288                                           old_crtc_state, old_conn_state);
3289
3290         /* Make sure the panel is off before trying to change the mode. But also
3291          * ensure that we have vdd while we switch off the panel. */
3292         intel_edp_panel_vdd_on(intel_dp);
3293         intel_edp_backlight_off(old_conn_state);
3294         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3295         intel_edp_panel_off(intel_dp);
3296 }
3297
3298 static void g4x_disable_dp(struct intel_encoder *encoder,
3299                            const struct intel_crtc_state *old_crtc_state,
3300                            const struct drm_connector_state *old_conn_state)
3301 {
3302         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3303 }
3304
3305 static void vlv_disable_dp(struct intel_encoder *encoder,
3306                            const struct intel_crtc_state *old_crtc_state,
3307                            const struct drm_connector_state *old_conn_state)
3308 {
3309         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
3310 }
3311
3312 static void g4x_post_disable_dp(struct intel_encoder *encoder,
3313                                 const struct intel_crtc_state *old_crtc_state,
3314                                 const struct drm_connector_state *old_conn_state)
3315 {
3316         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3317         enum port port = encoder->port;
3318
3319         /*
3320          * Bspec does not list a specific disable sequence for g4x DP.
3321          * Follow the ilk+ sequence (disable pipe before the port) for
3322          * g4x DP as it does not suffer from underruns like the normal
3323          * g4x modeset sequence (disable pipe after the port).
3324          */
3325         intel_dp_link_down(encoder, old_crtc_state);
3326
3327         /* Only ilk+ has port A */
3328         if (port == PORT_A)
3329                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
3330 }
3331
3332 static void vlv_post_disable_dp(struct intel_encoder *encoder,
3333                                 const struct intel_crtc_state *old_crtc_state,
3334                                 const struct drm_connector_state *old_conn_state)
3335 {
3336         intel_dp_link_down(encoder, old_crtc_state);
3337 }
3338
3339 static void chv_post_disable_dp(struct intel_encoder *encoder,
3340                                 const struct intel_crtc_state *old_crtc_state,
3341                                 const struct drm_connector_state *old_conn_state)
3342 {
3343         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3344
3345         intel_dp_link_down(encoder, old_crtc_state);
3346
3347         vlv_dpio_get(dev_priv);
3348
3349         /* Assert data lane reset */
3350         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3351
3352         vlv_dpio_put(dev_priv);
3353 }
3354
3355 static void
3356 _intel_dp_set_link_train(struct intel_dp *intel_dp,
3357                          u32 *DP,
3358                          u8 dp_train_pat)
3359 {
3360         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3361         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3362         enum port port = intel_dig_port->base.port;
3363         u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
3364
3365         if (dp_train_pat & train_pat_mask)
3366                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
3367                               dp_train_pat & train_pat_mask);
3368
3369         if (HAS_DDI(dev_priv)) {
3370                 u32 temp = I915_READ(intel_dp->regs.dp_tp_ctl);
3371
3372                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3373                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3374                 else
3375                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3376
3377                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3378                 switch (dp_train_pat & train_pat_mask) {
3379                 case DP_TRAINING_PATTERN_DISABLE:
3380                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3381
3382                         break;
3383                 case DP_TRAINING_PATTERN_1:
3384                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3385                         break;
3386                 case DP_TRAINING_PATTERN_2:
3387                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3388                         break;
3389                 case DP_TRAINING_PATTERN_3:
3390                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3391                         break;
3392                 case DP_TRAINING_PATTERN_4:
3393                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3394                         break;
3395                 }
3396                 I915_WRITE(intel_dp->regs.dp_tp_ctl, temp);
3397
3398         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3399                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3400                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3401
3402                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3403                 case DP_TRAINING_PATTERN_DISABLE:
3404                         *DP |= DP_LINK_TRAIN_OFF_CPT;
3405                         break;
3406                 case DP_TRAINING_PATTERN_1:
3407                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3408                         break;
3409                 case DP_TRAINING_PATTERN_2:
3410                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3411                         break;
3412                 case DP_TRAINING_PATTERN_3:
3413                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3414                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3415                         break;
3416                 }
3417
3418         } else {
3419                 *DP &= ~DP_LINK_TRAIN_MASK;
3420
3421                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3422                 case DP_TRAINING_PATTERN_DISABLE:
3423                         *DP |= DP_LINK_TRAIN_OFF;
3424                         break;
3425                 case DP_TRAINING_PATTERN_1:
3426                         *DP |= DP_LINK_TRAIN_PAT_1;
3427                         break;
3428                 case DP_TRAINING_PATTERN_2:
3429                         *DP |= DP_LINK_TRAIN_PAT_2;
3430                         break;
3431                 case DP_TRAINING_PATTERN_3:
3432                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
3433                         *DP |= DP_LINK_TRAIN_PAT_2;
3434                         break;
3435                 }
3436         }
3437 }
3438
3439 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3440                                  const struct intel_crtc_state *old_crtc_state)
3441 {
3442         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3443
3444         /* enable with pattern 1 (as per spec) */
3445
3446         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
3447
3448         /*
3449          * Magic for VLV/CHV. We _must_ first set up the register
3450          * without actually enabling the port, and then do another
3451          * write to enable the port. Otherwise link training will
3452          * fail when the power sequencer is freshly used for this port.
3453          */
3454         intel_dp->DP |= DP_PORT_EN;
3455         if (old_crtc_state->has_audio)
3456                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
3457
3458         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3459         POSTING_READ(intel_dp->output_reg);
3460 }
3461
3462 static void intel_enable_dp(struct intel_encoder *encoder,
3463                             const struct intel_crtc_state *pipe_config,
3464                             const struct drm_connector_state *conn_state)
3465 {
3466         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3467         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3468         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3469         u32 dp_reg = I915_READ(intel_dp->output_reg);
3470         enum pipe pipe = crtc->pipe;
3471         intel_wakeref_t wakeref;
3472
3473         if (WARN_ON(dp_reg & DP_PORT_EN))
3474                 return;
3475
3476         with_pps_lock(intel_dp, wakeref) {
3477                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3478                         vlv_init_panel_power_sequencer(encoder, pipe_config);
3479
3480                 intel_dp_enable_port(intel_dp, pipe_config);
3481
3482                 edp_panel_vdd_on(intel_dp);
3483                 edp_panel_on(intel_dp);
3484                 edp_panel_vdd_off(intel_dp, true);
3485         }
3486
3487         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3488                 unsigned int lane_mask = 0x0;
3489
3490                 if (IS_CHERRYVIEW(dev_priv))
3491                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3492
3493                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3494                                     lane_mask);
3495         }
3496
3497         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3498         intel_dp_start_link_train(intel_dp);
3499         intel_dp_stop_link_train(intel_dp);
3500
3501         if (pipe_config->has_audio) {
3502                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3503                                  pipe_name(pipe));
3504                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3505         }
3506 }
3507
3508 static void g4x_enable_dp(struct intel_encoder *encoder,
3509                           const struct intel_crtc_state *pipe_config,
3510                           const struct drm_connector_state *conn_state)
3511 {
3512         intel_enable_dp(encoder, pipe_config, conn_state);
3513         intel_edp_backlight_on(pipe_config, conn_state);
3514 }
3515
3516 static void vlv_enable_dp(struct intel_encoder *encoder,
3517                           const struct intel_crtc_state *pipe_config,
3518                           const struct drm_connector_state *conn_state)
3519 {
3520         intel_edp_backlight_on(pipe_config, conn_state);
3521 }
3522
3523 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3524                               const struct intel_crtc_state *pipe_config,
3525                               const struct drm_connector_state *conn_state)
3526 {
3527         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3528         enum port port = encoder->port;
3529
3530         intel_dp_prepare(encoder, pipe_config);
3531
3532         /* Only ilk+ has port A */
3533         if (port == PORT_A)
3534                 ironlake_edp_pll_on(intel_dp, pipe_config);
3535 }
3536
3537 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3538 {
3539         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3540         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3541         enum pipe pipe = intel_dp->pps_pipe;
3542         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3543
3544         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3545
3546         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3547                 return;
3548
3549         edp_panel_vdd_off_sync(intel_dp);
3550
3551         /*
3552          * VLV seems to get confused when multiple power sequencers
3553          * have the same port selected (even if only one has power/vdd
3554          * enabled). The failure manifests as vlv_wait_port_ready() failing
3555          * CHV on the other hand doesn't seem to mind having the same port
3556          * selected in multiple power sequencers, but let's clear the
3557          * port select always when logically disconnecting a power sequencer
3558          * from a port.
3559          */
3560         DRM_DEBUG_KMS("detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
3561                       pipe_name(pipe), intel_dig_port->base.base.base.id,
3562                       intel_dig_port->base.base.name);
3563         I915_WRITE(pp_on_reg, 0);
3564         POSTING_READ(pp_on_reg);
3565
3566         intel_dp->pps_pipe = INVALID_PIPE;
3567 }
3568
3569 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3570                                       enum pipe pipe)
3571 {
3572         struct intel_encoder *encoder;
3573
3574         lockdep_assert_held(&dev_priv->pps_mutex);
3575
3576         for_each_intel_dp(&dev_priv->drm, encoder) {
3577                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3578
3579                 WARN(intel_dp->active_pipe == pipe,
3580                      "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
3581                      pipe_name(pipe), encoder->base.base.id,
3582                      encoder->base.name);
3583
3584                 if (intel_dp->pps_pipe != pipe)
3585                         continue;
3586
3587                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
3588                               pipe_name(pipe), encoder->base.base.id,
3589                               encoder->base.name);
3590
3591                 /* make sure vdd is off before we steal it */
3592                 vlv_detach_power_sequencer(intel_dp);
3593         }
3594 }
3595
3596 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3597                                            const struct intel_crtc_state *crtc_state)
3598 {
3599         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3600         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3601         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3602
3603         lockdep_assert_held(&dev_priv->pps_mutex);
3604
3605         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3606
3607         if (intel_dp->pps_pipe != INVALID_PIPE &&
3608             intel_dp->pps_pipe != crtc->pipe) {
3609                 /*
3610                  * If another power sequencer was being used on this
3611                  * port previously make sure to turn off vdd there while
3612                  * we still have control of it.
3613                  */
3614                 vlv_detach_power_sequencer(intel_dp);
3615         }
3616
3617         /*
3618          * We may be stealing the power
3619          * sequencer from another port.
3620          */
3621         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3622
3623         intel_dp->active_pipe = crtc->pipe;
3624
3625         if (!intel_dp_is_edp(intel_dp))
3626                 return;
3627
3628         /* now it's all ours */
3629         intel_dp->pps_pipe = crtc->pipe;
3630
3631         DRM_DEBUG_KMS("initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
3632                       pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
3633                       encoder->base.name);
3634
3635         /* init power sequencer on this pipe and port */
3636         intel_dp_init_panel_power_sequencer(intel_dp);
3637         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3638 }
3639
3640 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3641                               const struct intel_crtc_state *pipe_config,
3642                               const struct drm_connector_state *conn_state)
3643 {
3644         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3645
3646         intel_enable_dp(encoder, pipe_config, conn_state);
3647 }
3648
3649 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3650                                   const struct intel_crtc_state *pipe_config,
3651                                   const struct drm_connector_state *conn_state)
3652 {
3653         intel_dp_prepare(encoder, pipe_config);
3654
3655         vlv_phy_pre_pll_enable(encoder, pipe_config);
3656 }
3657
3658 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3659                               const struct intel_crtc_state *pipe_config,
3660                               const struct drm_connector_state *conn_state)
3661 {
3662         chv_phy_pre_encoder_enable(encoder, pipe_config);
3663
3664         intel_enable_dp(encoder, pipe_config, conn_state);
3665
3666         /* Second common lane will stay alive on its own now */
3667         chv_phy_release_cl2_override(encoder);
3668 }
3669
3670 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3671                                   const struct intel_crtc_state *pipe_config,
3672                                   const struct drm_connector_state *conn_state)
3673 {
3674         intel_dp_prepare(encoder, pipe_config);
3675
3676         chv_phy_pre_pll_enable(encoder, pipe_config);
3677 }
3678
3679 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3680                                     const struct intel_crtc_state *old_crtc_state,
3681                                     const struct drm_connector_state *old_conn_state)
3682 {
3683         chv_phy_post_pll_disable(encoder, old_crtc_state);
3684 }
3685
3686 /*
3687  * Fetch AUX CH registers 0x202 - 0x207 which contain
3688  * link status information
3689  */
3690 bool
3691 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])
3692 {
3693         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3694                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3695 }
3696
3697 /* These are source-specific values. */
3698 u8
3699 intel_dp_voltage_max(struct intel_dp *intel_dp)
3700 {
3701         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3702         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3703         enum port port = encoder->port;
3704
3705         if (HAS_DDI(dev_priv))
3706                 return intel_ddi_dp_voltage_max(encoder);
3707         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3708                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3709         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3710                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3711         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3712                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3713         else
3714                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3715 }
3716
3717 u8
3718 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
3719 {
3720         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3721         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3722         enum port port = encoder->port;
3723
3724         if (HAS_DDI(dev_priv)) {
3725                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3726         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3727                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3728                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3729                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3730                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3731                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3732                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3733                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3734                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3735                 default:
3736                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3737                 }
3738         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3739                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3740                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3741                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3742                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3743                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3744                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3745                 default:
3746                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3747                 }
3748         } else {
3749                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3750                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3751                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3752                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3753                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3754                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3755                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3756                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3757                 default:
3758                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3759                 }
3760         }
3761 }
3762
3763 static u32 vlv_signal_levels(struct intel_dp *intel_dp)
3764 {
3765         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3766         unsigned long demph_reg_value, preemph_reg_value,
3767                 uniqtranscale_reg_value;
3768         u8 train_set = intel_dp->train_set[0];
3769
3770         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3771         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3772                 preemph_reg_value = 0x0004000;
3773                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3774                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3775                         demph_reg_value = 0x2B405555;
3776                         uniqtranscale_reg_value = 0x552AB83A;
3777                         break;
3778                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3779                         demph_reg_value = 0x2B404040;
3780                         uniqtranscale_reg_value = 0x5548B83A;
3781                         break;
3782                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3783                         demph_reg_value = 0x2B245555;
3784                         uniqtranscale_reg_value = 0x5560B83A;
3785                         break;
3786                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3787                         demph_reg_value = 0x2B405555;
3788                         uniqtranscale_reg_value = 0x5598DA3A;
3789                         break;
3790                 default:
3791                         return 0;
3792                 }
3793                 break;
3794         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3795                 preemph_reg_value = 0x0002000;
3796                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3797                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3798                         demph_reg_value = 0x2B404040;
3799                         uniqtranscale_reg_value = 0x5552B83A;
3800                         break;
3801                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3802                         demph_reg_value = 0x2B404848;
3803                         uniqtranscale_reg_value = 0x5580B83A;
3804                         break;
3805                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3806                         demph_reg_value = 0x2B404040;
3807                         uniqtranscale_reg_value = 0x55ADDA3A;
3808                         break;
3809                 default:
3810                         return 0;
3811                 }
3812                 break;
3813         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3814                 preemph_reg_value = 0x0000000;
3815                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3816                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3817                         demph_reg_value = 0x2B305555;
3818                         uniqtranscale_reg_value = 0x5570B83A;
3819                         break;
3820                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3821                         demph_reg_value = 0x2B2B4040;
3822                         uniqtranscale_reg_value = 0x55ADDA3A;
3823                         break;
3824                 default:
3825                         return 0;
3826                 }
3827                 break;
3828         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3829                 preemph_reg_value = 0x0006000;
3830                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3831                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3832                         demph_reg_value = 0x1B405555;
3833                         uniqtranscale_reg_value = 0x55ADDA3A;
3834                         break;
3835                 default:
3836                         return 0;
3837                 }
3838                 break;
3839         default:
3840                 return 0;
3841         }
3842
3843         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3844                                  uniqtranscale_reg_value, 0);
3845
3846         return 0;
3847 }
3848
3849 static u32 chv_signal_levels(struct intel_dp *intel_dp)
3850 {
3851         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3852         u32 deemph_reg_value, margin_reg_value;
3853         bool uniq_trans_scale = false;
3854         u8 train_set = intel_dp->train_set[0];
3855
3856         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3857         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3858                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3859                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3860                         deemph_reg_value = 128;
3861                         margin_reg_value = 52;
3862                         break;
3863                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3864                         deemph_reg_value = 128;
3865                         margin_reg_value = 77;
3866                         break;
3867                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3868                         deemph_reg_value = 128;
3869                         margin_reg_value = 102;
3870                         break;
3871                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3872                         deemph_reg_value = 128;
3873                         margin_reg_value = 154;
3874                         uniq_trans_scale = true;
3875                         break;
3876                 default:
3877                         return 0;
3878                 }
3879                 break;
3880         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3881                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3882                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3883                         deemph_reg_value = 85;
3884                         margin_reg_value = 78;
3885                         break;
3886                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3887                         deemph_reg_value = 85;
3888                         margin_reg_value = 116;
3889                         break;
3890                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3891                         deemph_reg_value = 85;
3892                         margin_reg_value = 154;
3893                         break;
3894                 default:
3895                         return 0;
3896                 }
3897                 break;
3898         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3899                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3900                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3901                         deemph_reg_value = 64;
3902                         margin_reg_value = 104;
3903                         break;
3904                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3905                         deemph_reg_value = 64;
3906                         margin_reg_value = 154;
3907                         break;
3908                 default:
3909                         return 0;
3910                 }
3911                 break;
3912         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3913                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3914                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3915                         deemph_reg_value = 43;
3916                         margin_reg_value = 154;
3917                         break;
3918                 default:
3919                         return 0;
3920                 }
3921                 break;
3922         default:
3923                 return 0;
3924         }
3925
3926         chv_set_phy_signal_level(encoder, deemph_reg_value,
3927                                  margin_reg_value, uniq_trans_scale);
3928
3929         return 0;
3930 }
3931
3932 static u32
3933 g4x_signal_levels(u8 train_set)
3934 {
3935         u32 signal_levels = 0;
3936
3937         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3938         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3939         default:
3940                 signal_levels |= DP_VOLTAGE_0_4;
3941                 break;
3942         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3943                 signal_levels |= DP_VOLTAGE_0_6;
3944                 break;
3945         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3946                 signal_levels |= DP_VOLTAGE_0_8;
3947                 break;
3948         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3949                 signal_levels |= DP_VOLTAGE_1_2;
3950                 break;
3951         }
3952         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3953         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3954         default:
3955                 signal_levels |= DP_PRE_EMPHASIS_0;
3956                 break;
3957         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3958                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3959                 break;
3960         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3961                 signal_levels |= DP_PRE_EMPHASIS_6;
3962                 break;
3963         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3964                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3965                 break;
3966         }
3967         return signal_levels;
3968 }
3969
3970 /* SNB CPU eDP voltage swing and pre-emphasis control */
3971 static u32
3972 snb_cpu_edp_signal_levels(u8 train_set)
3973 {
3974         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3975                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3976         switch (signal_levels) {
3977         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3978         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3979                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3980         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3981                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3982         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3983         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3984                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3985         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3986         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3987                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3988         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3989         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3990                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3991         default:
3992                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3993                               "0x%x\n", signal_levels);
3994                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3995         }
3996 }
3997
3998 /* IVB CPU eDP voltage swing and pre-emphasis control */
3999 static u32
4000 ivb_cpu_edp_signal_levels(u8 train_set)
4001 {
4002         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4003                                          DP_TRAIN_PRE_EMPHASIS_MASK);
4004         switch (signal_levels) {
4005         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4006                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4007         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4008                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4009         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4010                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4011
4012         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4013                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4014         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4015                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4016
4017         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4018                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4019         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4020                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4021
4022         default:
4023                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4024                               "0x%x\n", signal_levels);
4025                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4026         }
4027 }
4028
4029 void
4030 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
4031 {
4032         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4033         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4034         enum port port = intel_dig_port->base.port;
4035         u32 signal_levels, mask = 0;
4036         u8 train_set = intel_dp->train_set[0];
4037
4038         if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
4039                 signal_levels = bxt_signal_levels(intel_dp);
4040         } else if (HAS_DDI(dev_priv)) {
4041                 signal_levels = ddi_signal_levels(intel_dp);
4042                 mask = DDI_BUF_EMP_MASK;
4043         } else if (IS_CHERRYVIEW(dev_priv)) {
4044                 signal_levels = chv_signal_levels(intel_dp);
4045         } else if (IS_VALLEYVIEW(dev_priv)) {
4046                 signal_levels = vlv_signal_levels(intel_dp);
4047         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
4048                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
4049                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4050         } else if (IS_GEN(dev_priv, 6) && port == PORT_A) {
4051                 signal_levels = snb_cpu_edp_signal_levels(train_set);
4052                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4053         } else {
4054                 signal_levels = g4x_signal_levels(train_set);
4055                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
4056         }
4057
4058         if (mask)
4059                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
4060
4061         DRM_DEBUG_KMS("Using vswing level %d\n",
4062                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
4063         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
4064                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4065                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
4066
4067         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
4068
4069         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
4070         POSTING_READ(intel_dp->output_reg);
4071 }
4072
4073 void
4074 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4075                                        u8 dp_train_pat)
4076 {
4077         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4078         struct drm_i915_private *dev_priv =
4079                 to_i915(intel_dig_port->base.base.dev);
4080
4081         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
4082
4083         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
4084         POSTING_READ(intel_dp->output_reg);
4085 }
4086
4087 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
4088 {
4089         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4090         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4091         enum port port = intel_dig_port->base.port;
4092         u32 val;
4093
4094         if (!HAS_DDI(dev_priv))
4095                 return;
4096
4097         val = I915_READ(intel_dp->regs.dp_tp_ctl);
4098         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4099         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4100         I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
4101
4102         /*
4103          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4104          * reason we need to set idle transmission mode is to work around a HW
4105          * issue where we enable the pipe while not in idle link-training mode.
4106          * In this case there is requirement to wait for a minimum number of
4107          * idle patterns to be sent.
4108          */
4109         if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4110                 return;
4111
4112         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4113                                   DP_TP_STATUS_IDLE_DONE, 1))
4114                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
4115 }
4116
4117 static void
4118 intel_dp_link_down(struct intel_encoder *encoder,
4119                    const struct intel_crtc_state *old_crtc_state)
4120 {
4121         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4122         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4123         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4124         enum port port = encoder->port;
4125         u32 DP = intel_dp->DP;
4126
4127         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
4128                 return;
4129
4130         DRM_DEBUG_KMS("\n");
4131
4132         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4133             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4134                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4135                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4136         } else {
4137                 DP &= ~DP_LINK_TRAIN_MASK;
4138                 DP |= DP_LINK_TRAIN_PAT_IDLE;
4139         }
4140         I915_WRITE(intel_dp->output_reg, DP);
4141         POSTING_READ(intel_dp->output_reg);
4142
4143         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4144         I915_WRITE(intel_dp->output_reg, DP);
4145         POSTING_READ(intel_dp->output_reg);
4146
4147         /*
4148          * HW workaround for IBX, we need to move the port
4149          * to transcoder A after disabling it to allow the
4150          * matching HDMI port to be enabled on transcoder A.
4151          */
4152         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4153                 /*
4154                  * We get CPU/PCH FIFO underruns on the other pipe when
4155                  * doing the workaround. Sweep them under the rug.
4156                  */
4157                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4158                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4159
4160                 /* always enable with pattern 1 (as per spec) */
4161                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4162                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4163                         DP_LINK_TRAIN_PAT_1;
4164                 I915_WRITE(intel_dp->output_reg, DP);
4165                 POSTING_READ(intel_dp->output_reg);
4166
4167                 DP &= ~DP_PORT_EN;
4168                 I915_WRITE(intel_dp->output_reg, DP);
4169                 POSTING_READ(intel_dp->output_reg);
4170
4171                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4172                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4173                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4174         }
4175
4176         msleep(intel_dp->panel_power_down_delay);
4177
4178         intel_dp->DP = DP;
4179
4180         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4181                 intel_wakeref_t wakeref;
4182
4183                 with_pps_lock(intel_dp, wakeref)
4184                         intel_dp->active_pipe = INVALID_PIPE;
4185         }
4186 }
4187
4188 static void
4189 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
4190 {
4191         u8 dpcd_ext[6];
4192
4193         /*
4194          * Prior to DP1.3 the bit represented by
4195          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
4196          * if it is set DP_DPCD_REV at 0000h could be at a value less than
4197          * the true capability of the panel. The only way to check is to
4198          * then compare 0000h and 2200h.
4199          */
4200         if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
4201               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
4202                 return;
4203
4204         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
4205                              &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) {
4206                 DRM_ERROR("DPCD failed read at extended capabilities\n");
4207                 return;
4208         }
4209
4210         if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
4211                 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n");
4212                 return;
4213         }
4214
4215         if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)))
4216                 return;
4217
4218         DRM_DEBUG_KMS("Base DPCD: %*ph\n",
4219                       (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);
4220
4221         memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext));
4222 }
4223
4224 bool
4225 intel_dp_read_dpcd(struct intel_dp *intel_dp)
4226 {
4227         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
4228                              sizeof(intel_dp->dpcd)) < 0)
4229                 return false; /* aux transfer failed */
4230
4231         intel_dp_extended_receiver_capabilities(intel_dp);
4232
4233         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
4234
4235         return intel_dp->dpcd[DP_DPCD_REV] != 0;
4236 }
4237
4238 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4239 {
4240         u8 dprx = 0;
4241
4242         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4243                               &dprx) != 1)
4244                 return false;
4245         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4246 }
4247
4248 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4249 {
4250         /*
4251          * Clear the cached register set to avoid using stale values
4252          * for the sinks that do not support DSC.
4253          */
4254         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4255
4256         /* Clear fec_capable to avoid using stale values */
4257         intel_dp->fec_capable = 0;
4258
4259         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4260         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4261             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4262                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4263                                      intel_dp->dsc_dpcd,
4264                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4265                         DRM_ERROR("Failed to read DPCD register 0x%x\n",
4266                                   DP_DSC_SUPPORT);
4267
4268                 DRM_DEBUG_KMS("DSC DPCD: %*ph\n",
4269                               (int)sizeof(intel_dp->dsc_dpcd),
4270                               intel_dp->dsc_dpcd);
4271
4272                 /* FEC is supported only on DP 1.4 */
4273                 if (!intel_dp_is_edp(intel_dp) &&
4274                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4275                                       &intel_dp->fec_capable) < 0)
4276                         DRM_ERROR("Failed to read FEC DPCD register\n");
4277
4278                 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable);
4279         }
4280 }
4281
4282 static bool
4283 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4284 {
4285         struct drm_i915_private *dev_priv =
4286                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4287
4288         /* this function is meant to be called only once */
4289         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
4290
4291         if (!intel_dp_read_dpcd(intel_dp))
4292                 return false;
4293
4294         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4295                          drm_dp_is_branch(intel_dp->dpcd));
4296
4297         /*
4298          * Read the eDP display control registers.
4299          *
4300          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4301          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4302          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4303          * method). The display control registers should read zero if they're
4304          * not supported anyway.
4305          */
4306         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4307                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4308                              sizeof(intel_dp->edp_dpcd))
4309                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
4310                               intel_dp->edp_dpcd);
4311
4312         /*
4313          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4314          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4315          */
4316         intel_psr_init_dpcd(intel_dp);
4317
4318         /* Read the eDP 1.4+ supported link rates. */
4319         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4320                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4321                 int i;
4322
4323                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4324                                 sink_rates, sizeof(sink_rates));
4325
4326                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4327                         int val = le16_to_cpu(sink_rates[i]);
4328
4329                         if (val == 0)
4330                                 break;
4331
4332                         /* Value read multiplied by 200kHz gives the per-lane
4333                          * link rate in kHz. The source rates are, however,
4334                          * stored in terms of LS_Clk kHz. The full conversion
4335                          * back to symbols is
4336                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4337                          */
4338                         intel_dp->sink_rates[i] = (val * 200) / 10;
4339                 }
4340                 intel_dp->num_sink_rates = i;
4341         }
4342
4343         /*
4344          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4345          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4346          */
4347         if (intel_dp->num_sink_rates)
4348                 intel_dp->use_rate_select = true;
4349         else
4350                 intel_dp_set_sink_rates(intel_dp);
4351
4352         intel_dp_set_common_rates(intel_dp);
4353
4354         /* Read the eDP DSC DPCD registers */
4355         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4356                 intel_dp_get_dsc_sink_cap(intel_dp);
4357
4358         return true;
4359 }
4360
4361
4362 static bool
4363 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4364 {
4365         if (!intel_dp_read_dpcd(intel_dp))
4366                 return false;
4367
4368         /*
4369          * Don't clobber cached eDP rates. Also skip re-reading
4370          * the OUI/ID since we know it won't change.
4371          */
4372         if (!intel_dp_is_edp(intel_dp)) {
4373                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4374                                  drm_dp_is_branch(intel_dp->dpcd));
4375
4376                 intel_dp_set_sink_rates(intel_dp);
4377                 intel_dp_set_common_rates(intel_dp);
4378         }
4379
4380         /*
4381          * Some eDP panels do not set a valid value for sink count, that is why
4382          * it don't care about read it here and in intel_edp_init_dpcd().
4383          */
4384         if (!intel_dp_is_edp(intel_dp) &&
4385             !drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_SINK_COUNT)) {
4386                 u8 count;
4387                 ssize_t r;
4388
4389                 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count);
4390                 if (r < 1)
4391                         return false;
4392
4393                 /*
4394                  * Sink count can change between short pulse hpd hence
4395                  * a member variable in intel_dp will track any changes
4396                  * between short pulse interrupts.
4397                  */
4398                 intel_dp->sink_count = DP_GET_SINK_COUNT(count);
4399
4400                 /*
4401                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4402                  * a dongle is present but no display. Unless we require to know
4403                  * if a dongle is present or not, we don't need to update
4404                  * downstream port information. So, an early return here saves
4405                  * time from performing other operations which are not required.
4406                  */
4407                 if (!intel_dp->sink_count)
4408                         return false;
4409         }
4410
4411         if (!drm_dp_is_branch(intel_dp->dpcd))
4412                 return true; /* native DP sink */
4413
4414         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
4415                 return true; /* no per-port downstream info */
4416
4417         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
4418                              intel_dp->downstream_ports,
4419                              DP_MAX_DOWNSTREAM_PORTS) < 0)
4420                 return false; /* downstream port status fetch failed */
4421
4422         return true;
4423 }
4424
4425 static bool
4426 intel_dp_sink_can_mst(struct intel_dp *intel_dp)
4427 {
4428         u8 mstm_cap;
4429
4430         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4431                 return false;
4432
4433         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
4434                 return false;
4435
4436         return mstm_cap & DP_MST_CAP;
4437 }
4438
4439 static bool
4440 intel_dp_can_mst(struct intel_dp *intel_dp)
4441 {
4442         return i915_modparams.enable_dp_mst &&
4443                 intel_dp->can_mst &&
4444                 intel_dp_sink_can_mst(intel_dp);
4445 }
4446
4447 static void
4448 intel_dp_configure_mst(struct intel_dp *intel_dp)
4449 {
4450         struct intel_encoder *encoder =
4451                 &dp_to_dig_port(intel_dp)->base;
4452         bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);
4453
4454         DRM_DEBUG_KMS("[ENCODER:%d:%s] MST support? port: %s, sink: %s, modparam: %s\n",
4455                       encoder->base.base.id, encoder->base.name,
4456                       yesno(intel_dp->can_mst), yesno(sink_can_mst),
4457                       yesno(i915_modparams.enable_dp_mst));
4458
4459         if (!intel_dp->can_mst)
4460                 return;
4461
4462         intel_dp->is_mst = sink_can_mst &&
4463                 i915_modparams.enable_dp_mst;
4464
4465         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4466                                         intel_dp->is_mst);
4467 }
4468
4469 static bool
4470 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4471 {
4472         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4473                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4474                 DP_DPRX_ESI_LEN;
4475 }
4476
4477 static void
4478 intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
4479                                const struct intel_crtc_state *crtc_state)
4480 {
4481         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4482         struct dp_sdp vsc_sdp = {};
4483
4484         /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
4485         vsc_sdp.sdp_header.HB0 = 0;
4486         vsc_sdp.sdp_header.HB1 = 0x7;
4487
4488         /*
4489          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
4490          * Colorimetry Format indication.
4491          */
4492         vsc_sdp.sdp_header.HB2 = 0x5;
4493
4494         /*
4495          * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
4496          * Colorimetry Format indication (HB2 = 05h).
4497          */
4498         vsc_sdp.sdp_header.HB3 = 0x13;
4499
4500         /*
4501          * YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h
4502          * DB16[3:0] DP 1.4a spec, Table 2-120
4503          */
4504         vsc_sdp.db[16] = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
4505         /* RGB->YCBCR color conversion uses the BT.709 color space. */
4506         vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */
4507
4508         /*
4509          * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
4510          * the following Component Bit Depth values are defined:
4511          * 001b = 8bpc.
4512          * 010b = 10bpc.
4513          * 011b = 12bpc.
4514          * 100b = 16bpc.
4515          */
4516         switch (crtc_state->pipe_bpp) {
4517         case 24: /* 8bpc */
4518                 vsc_sdp.db[17] = 0x1;
4519                 break;
4520         case 30: /* 10bpc */
4521                 vsc_sdp.db[17] = 0x2;
4522                 break;
4523         case 36: /* 12bpc */
4524                 vsc_sdp.db[17] = 0x3;
4525                 break;
4526         case 48: /* 16bpc */
4527                 vsc_sdp.db[17] = 0x4;
4528                 break;
4529         default:
4530                 MISSING_CASE(crtc_state->pipe_bpp);
4531                 break;
4532         }
4533
4534         /*
4535          * Dynamic Range (Bit 7)
4536          * 0 = VESA range, 1 = CTA range.
4537          * all YCbCr are always limited range
4538          */
4539         vsc_sdp.db[17] |= 0x80;
4540
4541         /*
4542          * Content Type (Bits 2:0)
4543          * 000b = Not defined.
4544          * 001b = Graphics.
4545          * 010b = Photo.
4546          * 011b = Video.
4547          * 100b = Game
4548          * All other values are RESERVED.
4549          * Note: See CTA-861-G for the definition and expected
4550          * processing by a stream sink for the above contect types.
4551          */
4552         vsc_sdp.db[18] = 0;
4553
4554         intel_dig_port->write_infoframe(&intel_dig_port->base,
4555                         crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
4556 }
4557
4558 void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
4559                                const struct intel_crtc_state *crtc_state)
4560 {
4561         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
4562                 return;
4563
4564         intel_pixel_encoding_setup_vsc(intel_dp, crtc_state);
4565 }
4566
4567 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4568 {
4569         int status = 0;
4570         int test_link_rate;
4571         u8 test_lane_count, test_link_bw;
4572         /* (DP CTS 1.2)
4573          * 4.3.1.11
4574          */
4575         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
4576         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
4577                                    &test_lane_count);
4578
4579         if (status <= 0) {
4580                 DRM_DEBUG_KMS("Lane count read failed\n");
4581                 return DP_TEST_NAK;
4582         }
4583         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
4584
4585         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
4586                                    &test_link_bw);
4587         if (status <= 0) {
4588                 DRM_DEBUG_KMS("Link Rate read failed\n");
4589                 return DP_TEST_NAK;
4590         }
4591         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
4592
4593         /* Validate the requested link rate and lane count */
4594         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
4595                                         test_lane_count))
4596                 return DP_TEST_NAK;
4597
4598         intel_dp->compliance.test_lane_count = test_lane_count;
4599         intel_dp->compliance.test_link_rate = test_link_rate;
4600
4601         return DP_TEST_ACK;
4602 }
4603
4604 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4605 {
4606         u8 test_pattern;
4607         u8 test_misc;
4608         __be16 h_width, v_height;
4609         int status = 0;
4610
4611         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4612         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4613                                    &test_pattern);
4614         if (status <= 0) {
4615                 DRM_DEBUG_KMS("Test pattern read failed\n");
4616                 return DP_TEST_NAK;
4617         }
4618         if (test_pattern != DP_COLOR_RAMP)
4619                 return DP_TEST_NAK;
4620
4621         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4622                                   &h_width, 2);
4623         if (status <= 0) {
4624                 DRM_DEBUG_KMS("H Width read failed\n");
4625                 return DP_TEST_NAK;
4626         }
4627
4628         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4629                                   &v_height, 2);
4630         if (status <= 0) {
4631                 DRM_DEBUG_KMS("V Height read failed\n");
4632                 return DP_TEST_NAK;
4633         }
4634
4635         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4636                                    &test_misc);
4637         if (status <= 0) {
4638                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4639                 return DP_TEST_NAK;
4640         }
4641         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4642                 return DP_TEST_NAK;
4643         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4644                 return DP_TEST_NAK;
4645         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4646         case DP_TEST_BIT_DEPTH_6:
4647                 intel_dp->compliance.test_data.bpc = 6;
4648                 break;
4649         case DP_TEST_BIT_DEPTH_8:
4650                 intel_dp->compliance.test_data.bpc = 8;
4651                 break;
4652         default:
4653                 return DP_TEST_NAK;
4654         }
4655
4656         intel_dp->compliance.test_data.video_pattern = test_pattern;
4657         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4658         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4659         /* Set test active flag here so userspace doesn't interrupt things */
4660         intel_dp->compliance.test_active = 1;
4661
4662         return DP_TEST_ACK;
4663 }
4664
4665 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
4666 {
4667         u8 test_result = DP_TEST_ACK;
4668         struct intel_connector *intel_connector = intel_dp->attached_connector;
4669         struct drm_connector *connector = &intel_connector->base;
4670
4671         if (intel_connector->detect_edid == NULL ||
4672             connector->edid_corrupt ||
4673             intel_dp->aux.i2c_defer_count > 6) {
4674                 /* Check EDID read for NACKs, DEFERs and corruption
4675                  * (DP CTS 1.2 Core r1.1)
4676                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4677                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4678                  *    4.2.2.6 : EDID corruption detected
4679                  * Use failsafe mode for all cases
4680                  */
4681                 if (intel_dp->aux.i2c_nack_count > 0 ||
4682                         intel_dp->aux.i2c_defer_count > 0)
4683                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4684                                       intel_dp->aux.i2c_nack_count,
4685                                       intel_dp->aux.i2c_defer_count);
4686                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4687         } else {
4688                 struct edid *block = intel_connector->detect_edid;
4689
4690                 /* We have to write the checksum
4691                  * of the last block read
4692                  */
4693                 block += intel_connector->detect_edid->extensions;
4694
4695                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4696                                        block->checksum) <= 0)
4697                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4698
4699                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4700                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4701         }
4702
4703         /* Set test active flag here so userspace doesn't interrupt things */
4704         intel_dp->compliance.test_active = 1;
4705
4706         return test_result;
4707 }
4708
4709 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4710 {
4711         u8 test_result = DP_TEST_NAK;
4712         return test_result;
4713 }
4714
4715 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4716 {
4717         u8 response = DP_TEST_NAK;
4718         u8 request = 0;
4719         int status;
4720
4721         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4722         if (status <= 0) {
4723                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4724                 goto update_status;
4725         }
4726
4727         switch (request) {
4728         case DP_TEST_LINK_TRAINING:
4729                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4730                 response = intel_dp_autotest_link_training(intel_dp);
4731                 break;
4732         case DP_TEST_LINK_VIDEO_PATTERN:
4733                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4734                 response = intel_dp_autotest_video_pattern(intel_dp);
4735                 break;
4736         case DP_TEST_LINK_EDID_READ:
4737                 DRM_DEBUG_KMS("EDID test requested\n");
4738                 response = intel_dp_autotest_edid(intel_dp);
4739                 break;
4740         case DP_TEST_LINK_PHY_TEST_PATTERN:
4741                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4742                 response = intel_dp_autotest_phy_pattern(intel_dp);
4743                 break;
4744         default:
4745                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4746                 break;
4747         }
4748
4749         if (response & DP_TEST_ACK)
4750                 intel_dp->compliance.test_type = request;
4751
4752 update_status:
4753         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4754         if (status <= 0)
4755                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4756 }
4757
4758 static int
4759 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4760 {
4761         bool bret;
4762
4763         if (intel_dp->is_mst) {
4764                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4765                 int ret = 0;
4766                 int retry;
4767                 bool handled;
4768
4769                 WARN_ON_ONCE(intel_dp->active_mst_links < 0);
4770                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4771 go_again:
4772                 if (bret == true) {
4773
4774                         /* check link status - esi[10] = 0x200c */
4775                         if (intel_dp->active_mst_links > 0 &&
4776                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4777                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4778                                 intel_dp_start_link_train(intel_dp);
4779                                 intel_dp_stop_link_train(intel_dp);
4780                         }
4781
4782                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4783                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4784
4785                         if (handled) {
4786                                 for (retry = 0; retry < 3; retry++) {
4787                                         int wret;
4788                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4789                                                                  DP_SINK_COUNT_ESI+1,
4790                                                                  &esi[1], 3);
4791                                         if (wret == 3) {
4792                                                 break;
4793                                         }
4794                                 }
4795
4796                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4797                                 if (bret == true) {
4798                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4799                                         goto go_again;
4800                                 }
4801                         } else
4802                                 ret = 0;
4803
4804                         return ret;
4805                 } else {
4806                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4807                         intel_dp->is_mst = false;
4808                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4809                                                         intel_dp->is_mst);
4810                 }
4811         }
4812         return -EINVAL;
4813 }
4814
4815 static bool
4816 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4817 {
4818         u8 link_status[DP_LINK_STATUS_SIZE];
4819
4820         if (!intel_dp->link_trained)
4821                 return false;
4822
4823         /*
4824          * While PSR source HW is enabled, it will control main-link sending
4825          * frames, enabling and disabling it so trying to do a retrain will fail
4826          * as the link would or not be on or it could mix training patterns
4827          * and frame data at the same time causing retrain to fail.
4828          * Also when exiting PSR, HW will retrain the link anyways fixing
4829          * any link status error.
4830          */
4831         if (intel_psr_enabled(intel_dp))
4832                 return false;
4833
4834         if (!intel_dp_get_link_status(intel_dp, link_status))
4835                 return false;
4836
4837         /*
4838          * Validate the cached values of intel_dp->link_rate and
4839          * intel_dp->lane_count before attempting to retrain.
4840          */
4841         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4842                                         intel_dp->lane_count))
4843                 return false;
4844
4845         /* Retrain if Channel EQ or CR not ok */
4846         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4847 }
4848
4849 int intel_dp_retrain_link(struct intel_encoder *encoder,
4850                           struct drm_modeset_acquire_ctx *ctx)
4851 {
4852         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4853         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4854         struct intel_connector *connector = intel_dp->attached_connector;
4855         struct drm_connector_state *conn_state;
4856         struct intel_crtc_state *crtc_state;
4857         struct intel_crtc *crtc;
4858         int ret;
4859
4860         /* FIXME handle the MST connectors as well */
4861
4862         if (!connector || connector->base.status != connector_status_connected)
4863                 return 0;
4864
4865         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4866                                ctx);
4867         if (ret)
4868                 return ret;
4869
4870         conn_state = connector->base.state;
4871
4872         crtc = to_intel_crtc(conn_state->crtc);
4873         if (!crtc)
4874                 return 0;
4875
4876         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4877         if (ret)
4878                 return ret;
4879
4880         crtc_state = to_intel_crtc_state(crtc->base.state);
4881
4882         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4883
4884         if (!crtc_state->base.active)
4885                 return 0;
4886
4887         if (conn_state->commit &&
4888             !try_wait_for_completion(&conn_state->commit->hw_done))
4889                 return 0;
4890
4891         if (!intel_dp_needs_link_retrain(intel_dp))
4892                 return 0;
4893
4894         /* Suppress underruns caused by re-training */
4895         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4896         if (crtc_state->has_pch_encoder)
4897                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4898                                                       intel_crtc_pch_transcoder(crtc), false);
4899
4900         intel_dp_start_link_train(intel_dp);
4901         intel_dp_stop_link_train(intel_dp);
4902
4903         /* Keep underrun reporting disabled until things are stable */
4904         intel_wait_for_vblank(dev_priv, crtc->pipe);
4905
4906         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4907         if (crtc_state->has_pch_encoder)
4908                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4909                                                       intel_crtc_pch_transcoder(crtc), true);
4910
4911         return 0;
4912 }
4913
4914 /*
4915  * If display is now connected check links status,
4916  * there has been known issues of link loss triggering
4917  * long pulse.
4918  *
4919  * Some sinks (eg. ASUS PB287Q) seem to perform some
4920  * weird HPD ping pong during modesets. So we can apparently
4921  * end up with HPD going low during a modeset, and then
4922  * going back up soon after. And once that happens we must
4923  * retrain the link to get a picture. That's in case no
4924  * userspace component reacted to intermittent HPD dip.
4925  */
4926 static enum intel_hotplug_state
4927 intel_dp_hotplug(struct intel_encoder *encoder,
4928                  struct intel_connector *connector,
4929                  bool irq_received)
4930 {
4931         struct drm_modeset_acquire_ctx ctx;
4932         enum intel_hotplug_state state;
4933         int ret;
4934
4935         state = intel_encoder_hotplug(encoder, connector, irq_received);
4936
4937         drm_modeset_acquire_init(&ctx, 0);
4938
4939         for (;;) {
4940                 ret = intel_dp_retrain_link(encoder, &ctx);
4941
4942                 if (ret == -EDEADLK) {
4943                         drm_modeset_backoff(&ctx);
4944                         continue;
4945                 }
4946
4947                 break;
4948         }
4949
4950         drm_modeset_drop_locks(&ctx);
4951         drm_modeset_acquire_fini(&ctx);
4952         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4953
4954         /*
4955          * Keeping it consistent with intel_ddi_hotplug() and
4956          * intel_hdmi_hotplug().
4957          */
4958         if (state == INTEL_HOTPLUG_UNCHANGED && irq_received)
4959                 state = INTEL_HOTPLUG_RETRY;
4960
4961         return state;
4962 }
4963
4964 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
4965 {
4966         u8 val;
4967
4968         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
4969                 return;
4970
4971         if (drm_dp_dpcd_readb(&intel_dp->aux,
4972                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
4973                 return;
4974
4975         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
4976
4977         if (val & DP_AUTOMATED_TEST_REQUEST)
4978                 intel_dp_handle_test_request(intel_dp);
4979
4980         if (val & DP_CP_IRQ)
4981                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4982
4983         if (val & DP_SINK_SPECIFIC_IRQ)
4984                 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n");
4985 }
4986
4987 /*
4988  * According to DP spec
4989  * 5.1.2:
4990  *  1. Read DPCD
4991  *  2. Configure link according to Receiver Capabilities
4992  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4993  *  4. Check link status on receipt of hot-plug interrupt
4994  *
4995  * intel_dp_short_pulse -  handles short pulse interrupts
4996  * when full detection is not required.
4997  * Returns %true if short pulse is handled and full detection
4998  * is NOT required and %false otherwise.
4999  */
5000 static bool
5001 intel_dp_short_pulse(struct intel_dp *intel_dp)
5002 {
5003         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
5004         u8 old_sink_count = intel_dp->sink_count;
5005         bool ret;
5006
5007         /*
5008          * Clearing compliance test variables to allow capturing
5009          * of values for next automated test request.
5010          */
5011         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5012
5013         /*
5014          * Now read the DPCD to see if it's actually running
5015          * If the current value of sink count doesn't match with
5016          * the value that was stored earlier or dpcd read failed
5017          * we need to do full detection
5018          */
5019         ret = intel_dp_get_dpcd(intel_dp);
5020
5021         if ((old_sink_count != intel_dp->sink_count) || !ret) {
5022                 /* No need to proceed if we are going to do full detect */
5023                 return false;
5024         }
5025
5026         intel_dp_check_service_irq(intel_dp);
5027
5028         /* Handle CEC interrupts, if any */
5029         drm_dp_cec_irq(&intel_dp->aux);
5030
5031         /* defer to the hotplug work for link retraining if needed */
5032         if (intel_dp_needs_link_retrain(intel_dp))
5033                 return false;
5034
5035         intel_psr_short_pulse(intel_dp);
5036
5037         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
5038                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
5039                 /* Send a Hotplug Uevent to userspace to start modeset */
5040                 drm_kms_helper_hotplug_event(&dev_priv->drm);
5041         }
5042
5043         return true;
5044 }
5045
5046 /* XXX this is probably wrong for multiple downstream ports */
5047 static enum drm_connector_status
5048 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5049 {
5050         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5051         u8 *dpcd = intel_dp->dpcd;
5052         u8 type;
5053
5054         if (WARN_ON(intel_dp_is_edp(intel_dp)))
5055                 return connector_status_connected;
5056
5057         if (lspcon->active)
5058                 lspcon_resume(lspcon);
5059
5060         if (!intel_dp_get_dpcd(intel_dp))
5061                 return connector_status_disconnected;
5062
5063         /* if there's no downstream port, we're done */
5064         if (!drm_dp_is_branch(dpcd))
5065                 return connector_status_connected;
5066
5067         /* If we're HPD-aware, SINK_COUNT changes dynamically */
5068         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
5069             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5070
5071                 return intel_dp->sink_count ?
5072                 connector_status_connected : connector_status_disconnected;
5073         }
5074
5075         if (intel_dp_can_mst(intel_dp))
5076                 return connector_status_connected;
5077
5078         /* If no HPD, poke DDC gently */
5079         if (drm_probe_ddc(&intel_dp->aux.ddc))
5080                 return connector_status_connected;
5081
5082         /* Well we tried, say unknown for unreliable port types */
5083         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5084                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5085                 if (type == DP_DS_PORT_TYPE_VGA ||
5086                     type == DP_DS_PORT_TYPE_NON_EDID)
5087                         return connector_status_unknown;
5088         } else {
5089                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5090                         DP_DWN_STRM_PORT_TYPE_MASK;
5091                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5092                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
5093                         return connector_status_unknown;
5094         }
5095
5096         /* Anything else is out of spec, warn and ignore */
5097         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
5098         return connector_status_disconnected;
5099 }
5100
5101 static enum drm_connector_status
5102 edp_detect(struct intel_dp *intel_dp)
5103 {
5104         return connector_status_connected;
5105 }
5106
5107 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
5108 {
5109         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5110         u32 bit;
5111
5112         switch (encoder->hpd_pin) {
5113         case HPD_PORT_B:
5114                 bit = SDE_PORTB_HOTPLUG;
5115                 break;
5116         case HPD_PORT_C:
5117                 bit = SDE_PORTC_HOTPLUG;
5118                 break;
5119         case HPD_PORT_D:
5120                 bit = SDE_PORTD_HOTPLUG;
5121                 break;
5122         default:
5123                 MISSING_CASE(encoder->hpd_pin);
5124                 return false;
5125         }
5126
5127         return I915_READ(SDEISR) & bit;
5128 }
5129
5130 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
5131 {
5132         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5133         u32 bit;
5134
5135         switch (encoder->hpd_pin) {
5136         case HPD_PORT_B:
5137                 bit = SDE_PORTB_HOTPLUG_CPT;
5138                 break;
5139         case HPD_PORT_C:
5140                 bit = SDE_PORTC_HOTPLUG_CPT;
5141                 break;
5142         case HPD_PORT_D:
5143                 bit = SDE_PORTD_HOTPLUG_CPT;
5144                 break;
5145         default:
5146                 MISSING_CASE(encoder->hpd_pin);
5147                 return false;
5148         }
5149
5150         return I915_READ(SDEISR) & bit;
5151 }
5152
5153 static bool spt_digital_port_connected(struct intel_encoder *encoder)
5154 {
5155         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5156         u32 bit;
5157
5158         switch (encoder->hpd_pin) {
5159         case HPD_PORT_A:
5160                 bit = SDE_PORTA_HOTPLUG_SPT;
5161                 break;
5162         case HPD_PORT_E:
5163                 bit = SDE_PORTE_HOTPLUG_SPT;
5164                 break;
5165         default:
5166                 return cpt_digital_port_connected(encoder);
5167         }
5168
5169         return I915_READ(SDEISR) & bit;
5170 }
5171
5172 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
5173 {
5174         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5175         u32 bit;
5176
5177         switch (encoder->hpd_pin) {
5178         case HPD_PORT_B:
5179                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
5180                 break;
5181         case HPD_PORT_C:
5182                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
5183                 break;
5184         case HPD_PORT_D:
5185                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
5186                 break;
5187         default:
5188                 MISSING_CASE(encoder->hpd_pin);
5189                 return false;
5190         }
5191
5192         return I915_READ(PORT_HOTPLUG_STAT) & bit;
5193 }
5194
5195 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
5196 {
5197         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5198         u32 bit;
5199
5200         switch (encoder->hpd_pin) {
5201         case HPD_PORT_B:
5202                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
5203                 break;
5204         case HPD_PORT_C:
5205                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
5206                 break;
5207         case HPD_PORT_D:
5208                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
5209                 break;
5210         default:
5211                 MISSING_CASE(encoder->hpd_pin);
5212                 return false;
5213         }
5214
5215         return I915_READ(PORT_HOTPLUG_STAT) & bit;
5216 }
5217
5218 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
5219 {
5220         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5221
5222         if (encoder->hpd_pin == HPD_PORT_A)
5223                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5224         else
5225                 return ibx_digital_port_connected(encoder);
5226 }
5227
5228 static bool snb_digital_port_connected(struct intel_encoder *encoder)
5229 {
5230         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5231
5232         if (encoder->hpd_pin == HPD_PORT_A)
5233                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
5234         else
5235                 return cpt_digital_port_connected(encoder);
5236 }
5237
5238 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
5239 {
5240         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5241
5242         if (encoder->hpd_pin == HPD_PORT_A)
5243                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
5244         else
5245                 return cpt_digital_port_connected(encoder);
5246 }
5247
5248 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
5249 {
5250         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5251
5252         if (encoder->hpd_pin == HPD_PORT_A)
5253                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
5254         else
5255                 return cpt_digital_port_connected(encoder);
5256 }
5257
5258 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
5259 {
5260         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5261         u32 bit;
5262
5263         switch (encoder->hpd_pin) {
5264         case HPD_PORT_A:
5265                 bit = BXT_DE_PORT_HP_DDIA;
5266                 break;
5267         case HPD_PORT_B:
5268                 bit = BXT_DE_PORT_HP_DDIB;
5269                 break;
5270         case HPD_PORT_C:
5271                 bit = BXT_DE_PORT_HP_DDIC;
5272                 break;
5273         default:
5274                 MISSING_CASE(encoder->hpd_pin);
5275                 return false;
5276         }
5277
5278         return I915_READ(GEN8_DE_PORT_ISR) & bit;
5279 }
5280
5281 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv,
5282                                      struct intel_digital_port *intel_dig_port)
5283 {
5284         enum port port = intel_dig_port->base.port;
5285
5286         return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port);
5287 }
5288
5289 static bool icl_digital_port_connected(struct intel_encoder *encoder)
5290 {
5291         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5292         struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
5293         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
5294
5295         if (intel_phy_is_combo(dev_priv, phy))
5296                 return icl_combo_port_connected(dev_priv, dig_port);
5297         else if (intel_phy_is_tc(dev_priv, phy))
5298                 return intel_tc_port_connected(dig_port);
5299         else
5300                 MISSING_CASE(encoder->hpd_pin);
5301
5302         return false;
5303 }
5304
5305 /*
5306  * intel_digital_port_connected - is the specified port connected?
5307  * @encoder: intel_encoder
5308  *
5309  * In cases where there's a connector physically connected but it can't be used
5310  * by our hardware we also return false, since the rest of the driver should
5311  * pretty much treat the port as disconnected. This is relevant for type-C
5312  * (starting on ICL) where there's ownership involved.
5313  *
5314  * Return %true if port is connected, %false otherwise.
5315  */
5316 static bool __intel_digital_port_connected(struct intel_encoder *encoder)
5317 {
5318         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5319
5320         if (HAS_GMCH(dev_priv)) {
5321                 if (IS_GM45(dev_priv))
5322                         return gm45_digital_port_connected(encoder);
5323                 else
5324                         return g4x_digital_port_connected(encoder);
5325         }
5326
5327         if (INTEL_GEN(dev_priv) >= 11)
5328                 return icl_digital_port_connected(encoder);
5329         else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv))
5330                 return spt_digital_port_connected(encoder);
5331         else if (IS_GEN9_LP(dev_priv))
5332                 return bxt_digital_port_connected(encoder);
5333         else if (IS_GEN(dev_priv, 8))
5334                 return bdw_digital_port_connected(encoder);
5335         else if (IS_GEN(dev_priv, 7))
5336                 return ivb_digital_port_connected(encoder);
5337         else if (IS_GEN(dev_priv, 6))
5338                 return snb_digital_port_connected(encoder);
5339         else if (IS_GEN(dev_priv, 5))
5340                 return ilk_digital_port_connected(encoder);
5341
5342         MISSING_CASE(INTEL_GEN(dev_priv));
5343         return false;
5344 }
5345
5346 bool intel_digital_port_connected(struct intel_encoder *encoder)
5347 {
5348         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5349         bool is_connected = false;
5350         intel_wakeref_t wakeref;
5351
5352         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
5353                 is_connected = __intel_digital_port_connected(encoder);
5354
5355         return is_connected;
5356 }
5357
5358 static struct edid *
5359 intel_dp_get_edid(struct intel_dp *intel_dp)
5360 {
5361         struct intel_connector *intel_connector = intel_dp->attached_connector;
5362
5363         /* use cached edid if we have one */
5364         if (intel_connector->edid) {
5365                 /* invalid edid */
5366                 if (IS_ERR(intel_connector->edid))
5367                         return NULL;
5368
5369                 return drm_edid_duplicate(intel_connector->edid);
5370         } else
5371                 return drm_get_edid(&intel_connector->base,
5372                                     &intel_dp->aux.ddc);
5373 }
5374
5375 static void
5376 intel_dp_set_edid(struct intel_dp *intel_dp)
5377 {
5378         struct intel_connector *intel_connector = intel_dp->attached_connector;
5379         struct edid *edid;
5380
5381         intel_dp_unset_edid(intel_dp);
5382         edid = intel_dp_get_edid(intel_dp);
5383         intel_connector->detect_edid = edid;
5384
5385         intel_dp->has_audio = drm_detect_monitor_audio(edid);
5386         drm_dp_cec_set_edid(&intel_dp->aux, edid);
5387 }
5388
5389 static void
5390 intel_dp_unset_edid(struct intel_dp *intel_dp)
5391 {
5392         struct intel_connector *intel_connector = intel_dp->attached_connector;
5393
5394         drm_dp_cec_unset_edid(&intel_dp->aux);
5395         kfree(intel_connector->detect_edid);
5396         intel_connector->detect_edid = NULL;
5397
5398         intel_dp->has_audio = false;
5399 }
5400
5401 static int
5402 intel_dp_detect(struct drm_connector *connector,
5403                 struct drm_modeset_acquire_ctx *ctx,
5404                 bool force)
5405 {
5406         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5407         struct intel_dp *intel_dp = intel_attached_dp(connector);
5408         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5409         struct intel_encoder *encoder = &dig_port->base;
5410         enum drm_connector_status status;
5411
5412         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5413                       connector->base.id, connector->name);
5414         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
5415
5416         /* Can't disconnect eDP */
5417         if (intel_dp_is_edp(intel_dp))
5418                 status = edp_detect(intel_dp);
5419         else if (intel_digital_port_connected(encoder))
5420                 status = intel_dp_detect_dpcd(intel_dp);
5421         else
5422                 status = connector_status_disconnected;
5423
5424         if (status == connector_status_disconnected) {
5425                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
5426                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
5427
5428                 if (intel_dp->is_mst) {
5429                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5430                                       intel_dp->is_mst,
5431                                       intel_dp->mst_mgr.mst_state);
5432                         intel_dp->is_mst = false;
5433                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5434                                                         intel_dp->is_mst);
5435                 }
5436
5437                 goto out;
5438         }
5439
5440         if (intel_dp->reset_link_params) {
5441                 /* Initial max link lane count */
5442                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
5443
5444                 /* Initial max link rate */
5445                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
5446
5447                 intel_dp->reset_link_params = false;
5448         }
5449
5450         intel_dp_print_rates(intel_dp);
5451
5452         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
5453         if (INTEL_GEN(dev_priv) >= 11)
5454                 intel_dp_get_dsc_sink_cap(intel_dp);
5455
5456         intel_dp_configure_mst(intel_dp);
5457
5458         if (intel_dp->is_mst) {
5459                 /*
5460                  * If we are in MST mode then this connector
5461                  * won't appear connected or have anything
5462                  * with EDID on it
5463                  */
5464                 status = connector_status_disconnected;
5465                 goto out;
5466         }
5467
5468         /*
5469          * Some external monitors do not signal loss of link synchronization
5470          * with an IRQ_HPD, so force a link status check.
5471          */
5472         if (!intel_dp_is_edp(intel_dp)) {
5473                 int ret;
5474
5475                 ret = intel_dp_retrain_link(encoder, ctx);
5476                 if (ret)
5477                         return ret;
5478         }
5479
5480         /*
5481          * Clearing NACK and defer counts to get their exact values
5482          * while reading EDID which are required by Compliance tests
5483          * 4.2.2.4 and 4.2.2.5
5484          */
5485         intel_dp->aux.i2c_nack_count = 0;
5486         intel_dp->aux.i2c_defer_count = 0;
5487
5488         intel_dp_set_edid(intel_dp);
5489         if (intel_dp_is_edp(intel_dp) ||
5490             to_intel_connector(connector)->detect_edid)
5491                 status = connector_status_connected;
5492
5493         intel_dp_check_service_irq(intel_dp);
5494
5495 out:
5496         if (status != connector_status_connected && !intel_dp->is_mst)
5497                 intel_dp_unset_edid(intel_dp);
5498
5499         return status;
5500 }
5501
5502 static void
5503 intel_dp_force(struct drm_connector *connector)
5504 {
5505         struct intel_dp *intel_dp = intel_attached_dp(connector);
5506         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5507         struct intel_encoder *intel_encoder = &dig_port->base;
5508         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
5509         enum intel_display_power_domain aux_domain =
5510                 intel_aux_power_domain(dig_port);
5511         intel_wakeref_t wakeref;
5512
5513         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5514                       connector->base.id, connector->name);
5515         intel_dp_unset_edid(intel_dp);
5516
5517         if (connector->status != connector_status_connected)
5518                 return;
5519
5520         wakeref = intel_display_power_get(dev_priv, aux_domain);
5521
5522         intel_dp_set_edid(intel_dp);
5523
5524         intel_display_power_put(dev_priv, aux_domain, wakeref);
5525 }
5526
5527 static int intel_dp_get_modes(struct drm_connector *connector)
5528 {
5529         struct intel_connector *intel_connector = to_intel_connector(connector);
5530         struct edid *edid;
5531
5532         edid = intel_connector->detect_edid;
5533         if (edid) {
5534                 int ret = intel_connector_update_modes(connector, edid);
5535                 if (ret)
5536                         return ret;
5537         }
5538
5539         /* if eDP has no EDID, fall back to fixed mode */
5540         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
5541             intel_connector->panel.fixed_mode) {
5542                 struct drm_display_mode *mode;
5543
5544                 mode = drm_mode_duplicate(connector->dev,
5545                                           intel_connector->panel.fixed_mode);
5546                 if (mode) {
5547                         drm_mode_probed_add(connector, mode);
5548                         return 1;
5549                 }
5550         }
5551
5552         return 0;
5553 }
5554
5555 static int
5556 intel_dp_connector_register(struct drm_connector *connector)
5557 {
5558         struct intel_dp *intel_dp = intel_attached_dp(connector);
5559         struct drm_device *dev = connector->dev;
5560         int ret;
5561
5562         ret = intel_connector_register(connector);
5563         if (ret)
5564                 return ret;
5565
5566         i915_debugfs_connector_add(connector);
5567
5568         DRM_DEBUG_KMS("registering %s bus for %s\n",
5569                       intel_dp->aux.name, connector->kdev->kobj.name);
5570
5571         intel_dp->aux.dev = connector->kdev;
5572         ret = drm_dp_aux_register(&intel_dp->aux);
5573         if (!ret)
5574                 drm_dp_cec_register_connector(&intel_dp->aux,
5575                                               connector->name, dev->dev);
5576         return ret;
5577 }
5578
5579 static void
5580 intel_dp_connector_unregister(struct drm_connector *connector)
5581 {
5582         struct intel_dp *intel_dp = intel_attached_dp(connector);
5583
5584         drm_dp_cec_unregister_connector(&intel_dp->aux);
5585         drm_dp_aux_unregister(&intel_dp->aux);
5586         intel_connector_unregister(connector);
5587 }
5588
5589 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
5590 {
5591         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
5592         struct intel_dp *intel_dp = &intel_dig_port->dp;
5593
5594         intel_dp_mst_encoder_cleanup(intel_dig_port);
5595         if (intel_dp_is_edp(intel_dp)) {
5596                 intel_wakeref_t wakeref;
5597
5598                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5599                 /*
5600                  * vdd might still be enabled do to the delayed vdd off.
5601                  * Make sure vdd is actually turned off here.
5602                  */
5603                 with_pps_lock(intel_dp, wakeref)
5604                         edp_panel_vdd_off_sync(intel_dp);
5605
5606                 if (intel_dp->edp_notifier.notifier_call) {
5607                         unregister_reboot_notifier(&intel_dp->edp_notifier);
5608                         intel_dp->edp_notifier.notifier_call = NULL;
5609                 }
5610         }
5611
5612         intel_dp_aux_fini(intel_dp);
5613 }
5614
5615 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
5616 {
5617         intel_dp_encoder_flush_work(encoder);
5618
5619         drm_encoder_cleanup(encoder);
5620         kfree(enc_to_dig_port(encoder));
5621 }
5622
5623 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
5624 {
5625         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
5626         intel_wakeref_t wakeref;
5627
5628         if (!intel_dp_is_edp(intel_dp))
5629                 return;
5630
5631         /*
5632          * vdd might still be enabled do to the delayed vdd off.
5633          * Make sure vdd is actually turned off here.
5634          */
5635         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5636         with_pps_lock(intel_dp, wakeref)
5637                 edp_panel_vdd_off_sync(intel_dp);
5638 }
5639
5640 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
5641 {
5642         long ret;
5643
5644 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
5645         ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
5646                                                msecs_to_jiffies(timeout));
5647
5648         if (!ret)
5649                 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
5650 }
5651
5652 static
5653 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
5654                                 u8 *an)
5655 {
5656         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
5657         static const struct drm_dp_aux_msg msg = {
5658                 .request = DP_AUX_NATIVE_WRITE,
5659                 .address = DP_AUX_HDCP_AKSV,
5660                 .size = DRM_HDCP_KSV_LEN,
5661         };
5662         u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
5663         ssize_t dpcd_ret;
5664         int ret;
5665
5666         /* Output An first, that's easy */
5667         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5668                                      an, DRM_HDCP_AN_LEN);
5669         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5670                 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n",
5671                               dpcd_ret);
5672                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5673         }
5674
5675         /*
5676          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5677          * order to get it on the wire, we need to create the AUX header as if
5678          * we were writing the data, and then tickle the hardware to output the
5679          * data once the header is sent out.
5680          */
5681         intel_dp_aux_header(txbuf, &msg);
5682
5683         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5684                                 rxbuf, sizeof(rxbuf),
5685                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5686         if (ret < 0) {
5687                 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret);
5688                 return ret;
5689         } else if (ret == 0) {
5690                 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n");
5691                 return -EIO;
5692         }
5693
5694         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5695         if (reply != DP_AUX_NATIVE_REPLY_ACK) {
5696                 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n",
5697                               reply);
5698                 return -EIO;
5699         }
5700         return 0;
5701 }
5702
5703 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5704                                    u8 *bksv)
5705 {
5706         ssize_t ret;
5707         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5708                                DRM_HDCP_KSV_LEN);
5709         if (ret != DRM_HDCP_KSV_LEN) {
5710                 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret);
5711                 return ret >= 0 ? -EIO : ret;
5712         }
5713         return 0;
5714 }
5715
5716 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5717                                       u8 *bstatus)
5718 {
5719         ssize_t ret;
5720         /*
5721          * For some reason the HDMI and DP HDCP specs call this register
5722          * definition by different names. In the HDMI spec, it's called BSTATUS,
5723          * but in DP it's called BINFO.
5724          */
5725         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5726                                bstatus, DRM_HDCP_BSTATUS_LEN);
5727         if (ret != DRM_HDCP_BSTATUS_LEN) {
5728                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5729                 return ret >= 0 ? -EIO : ret;
5730         }
5731         return 0;
5732 }
5733
5734 static
5735 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5736                              u8 *bcaps)
5737 {
5738         ssize_t ret;
5739
5740         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5741                                bcaps, 1);
5742         if (ret != 1) {
5743                 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret);
5744                 return ret >= 0 ? -EIO : ret;
5745         }
5746
5747         return 0;
5748 }
5749
5750 static
5751 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5752                                    bool *repeater_present)
5753 {
5754         ssize_t ret;
5755         u8 bcaps;
5756
5757         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5758         if (ret)
5759                 return ret;
5760
5761         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5762         return 0;
5763 }
5764
5765 static
5766 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5767                                 u8 *ri_prime)
5768 {
5769         ssize_t ret;
5770         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5771                                ri_prime, DRM_HDCP_RI_LEN);
5772         if (ret != DRM_HDCP_RI_LEN) {
5773                 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret);
5774                 return ret >= 0 ? -EIO : ret;
5775         }
5776         return 0;
5777 }
5778
5779 static
5780 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5781                                  bool *ksv_ready)
5782 {
5783         ssize_t ret;
5784         u8 bstatus;
5785         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5786                                &bstatus, 1);
5787         if (ret != 1) {
5788                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5789                 return ret >= 0 ? -EIO : ret;
5790         }
5791         *ksv_ready = bstatus & DP_BSTATUS_READY;
5792         return 0;
5793 }
5794
5795 static
5796 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5797                                 int num_downstream, u8 *ksv_fifo)
5798 {
5799         ssize_t ret;
5800         int i;
5801
5802         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5803         for (i = 0; i < num_downstream; i += 3) {
5804                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5805                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5806                                        DP_AUX_HDCP_KSV_FIFO,
5807                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5808                                        len);
5809                 if (ret != len) {
5810                         DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n",
5811                                       i, ret);
5812                         return ret >= 0 ? -EIO : ret;
5813                 }
5814         }
5815         return 0;
5816 }
5817
5818 static
5819 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5820                                     int i, u32 *part)
5821 {
5822         ssize_t ret;
5823
5824         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5825                 return -EINVAL;
5826
5827         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5828                                DP_AUX_HDCP_V_PRIME(i), part,
5829                                DRM_HDCP_V_PRIME_PART_LEN);
5830         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5831                 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5832                 return ret >= 0 ? -EIO : ret;
5833         }
5834         return 0;
5835 }
5836
5837 static
5838 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5839                                     bool enable)
5840 {
5841         /* Not used for single stream DisplayPort setups */
5842         return 0;
5843 }
5844
5845 static
5846 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5847 {
5848         ssize_t ret;
5849         u8 bstatus;
5850
5851         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5852                                &bstatus, 1);
5853         if (ret != 1) {
5854                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5855                 return false;
5856         }
5857
5858         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5859 }
5860
5861 static
5862 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5863                           bool *hdcp_capable)
5864 {
5865         ssize_t ret;
5866         u8 bcaps;
5867
5868         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5869         if (ret)
5870                 return ret;
5871
5872         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5873         return 0;
5874 }
5875
5876 struct hdcp2_dp_errata_stream_type {
5877         u8      msg_id;
5878         u8      stream_type;
5879 } __packed;
5880
5881 struct hdcp2_dp_msg_data {
5882         u8 msg_id;
5883         u32 offset;
5884         bool msg_detectable;
5885         u32 timeout;
5886         u32 timeout2; /* Added for non_paired situation */
5887 };
5888
5889 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
5890         { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
5891         { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
5892           false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
5893         { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
5894           false, 0, 0 },
5895         { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
5896           false, 0, 0 },
5897         { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
5898           true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
5899           HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
5900         { HDCP_2_2_AKE_SEND_PAIRING_INFO,
5901           DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
5902           HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
5903         { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
5904         { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
5905           false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
5906         { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
5907           0, 0 },
5908         { HDCP_2_2_REP_SEND_RECVID_LIST,
5909           DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
5910           HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
5911         { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
5912           0, 0 },
5913         { HDCP_2_2_REP_STREAM_MANAGE,
5914           DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
5915           0, 0 },
5916         { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
5917           false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
5918 /* local define to shovel this through the write_2_2 interface */
5919 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE  50
5920         { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
5921           DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
5922           0, 0 },
5923 };
5924
5925 static inline
5926 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
5927                                   u8 *rx_status)
5928 {
5929         ssize_t ret;
5930
5931         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5932                                DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
5933                                HDCP_2_2_DP_RXSTATUS_LEN);
5934         if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
5935                 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret);
5936                 return ret >= 0 ? -EIO : ret;
5937         }
5938
5939         return 0;
5940 }
5941
5942 static
5943 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
5944                                   u8 msg_id, bool *msg_ready)
5945 {
5946         u8 rx_status;
5947         int ret;
5948
5949         *msg_ready = false;
5950         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
5951         if (ret < 0)
5952                 return ret;
5953
5954         switch (msg_id) {
5955         case HDCP_2_2_AKE_SEND_HPRIME:
5956                 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
5957                         *msg_ready = true;
5958                 break;
5959         case HDCP_2_2_AKE_SEND_PAIRING_INFO:
5960                 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
5961                         *msg_ready = true;
5962                 break;
5963         case HDCP_2_2_REP_SEND_RECVID_LIST:
5964                 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
5965                         *msg_ready = true;
5966                 break;
5967         default:
5968                 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
5969                 return -EINVAL;
5970         }
5971
5972         return 0;
5973 }
5974
5975 static ssize_t
5976 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
5977                             const struct hdcp2_dp_msg_data *hdcp2_msg_data)
5978 {
5979         struct intel_dp *dp = &intel_dig_port->dp;
5980         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
5981         u8 msg_id = hdcp2_msg_data->msg_id;
5982         int ret, timeout;
5983         bool msg_ready = false;
5984
5985         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
5986                 timeout = hdcp2_msg_data->timeout2;
5987         else
5988                 timeout = hdcp2_msg_data->timeout;
5989
5990         /*
5991          * There is no way to detect the CERT, LPRIME and STREAM_READY
5992          * availability. So Wait for timeout and read the msg.
5993          */
5994         if (!hdcp2_msg_data->msg_detectable) {
5995                 mdelay(timeout);
5996                 ret = 0;
5997         } else {
5998                 /*
5999                  * As we want to check the msg availability at timeout, Ignoring
6000                  * the timeout at wait for CP_IRQ.
6001                  */
6002                 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
6003                 ret = hdcp2_detect_msg_availability(intel_dig_port,
6004                                                     msg_id, &msg_ready);
6005                 if (!msg_ready)
6006                         ret = -ETIMEDOUT;
6007         }
6008
6009         if (ret)
6010                 DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n",
6011                               hdcp2_msg_data->msg_id, ret, timeout);
6012
6013         return ret;
6014 }
6015
6016 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
6017 {
6018         int i;
6019
6020         for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
6021                 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
6022                         return &hdcp2_dp_msg_data[i];
6023
6024         return NULL;
6025 }
6026
6027 static
6028 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
6029                              void *buf, size_t size)
6030 {
6031         struct intel_dp *dp = &intel_dig_port->dp;
6032         struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
6033         unsigned int offset;
6034         u8 *byte = buf;
6035         ssize_t ret, bytes_to_write, len;
6036         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6037
6038         hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
6039         if (!hdcp2_msg_data)
6040                 return -EINVAL;
6041
6042         offset = hdcp2_msg_data->offset;
6043
6044         /* No msg_id in DP HDCP2.2 msgs */
6045         bytes_to_write = size - 1;
6046         byte++;
6047
6048         hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
6049
6050         while (bytes_to_write) {
6051                 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
6052                                 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
6053
6054                 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
6055                                         offset, (void *)byte, len);
6056                 if (ret < 0)
6057                         return ret;
6058
6059                 bytes_to_write -= ret;
6060                 byte += ret;
6061                 offset += ret;
6062         }
6063
6064         return size;
6065 }
6066
6067 static
6068 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port)
6069 {
6070         u8 rx_info[HDCP_2_2_RXINFO_LEN];
6071         u32 dev_cnt;
6072         ssize_t ret;
6073
6074         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6075                                DP_HDCP_2_2_REG_RXINFO_OFFSET,
6076                                (void *)rx_info, HDCP_2_2_RXINFO_LEN);
6077         if (ret != HDCP_2_2_RXINFO_LEN)
6078                 return ret >= 0 ? -EIO : ret;
6079
6080         dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
6081                    HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
6082
6083         if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
6084                 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
6085
6086         ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
6087                 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
6088                 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
6089
6090         return ret;
6091 }
6092
6093 static
6094 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
6095                             u8 msg_id, void *buf, size_t size)
6096 {
6097         unsigned int offset;
6098         u8 *byte = buf;
6099         ssize_t ret, bytes_to_recv, len;
6100         const struct hdcp2_dp_msg_data *hdcp2_msg_data;
6101
6102         hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
6103         if (!hdcp2_msg_data)
6104                 return -EINVAL;
6105         offset = hdcp2_msg_data->offset;
6106
6107         ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
6108         if (ret < 0)
6109                 return ret;
6110
6111         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
6112                 ret = get_receiver_id_list_size(intel_dig_port);
6113                 if (ret < 0)
6114                         return ret;
6115
6116                 size = ret;
6117         }
6118         bytes_to_recv = size - 1;
6119
6120         /* DP adaptation msgs has no msg_id */
6121         byte++;
6122
6123         while (bytes_to_recv) {
6124                 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
6125                       DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
6126
6127                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
6128                                        (void *)byte, len);
6129                 if (ret < 0) {
6130                         DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret);
6131                         return ret;
6132                 }
6133
6134                 bytes_to_recv -= ret;
6135                 byte += ret;
6136                 offset += ret;
6137         }
6138         byte = buf;
6139         *byte = msg_id;
6140
6141         return size;
6142 }
6143
6144 static
6145 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,
6146                                       bool is_repeater, u8 content_type)
6147 {
6148         struct hdcp2_dp_errata_stream_type stream_type_msg;
6149
6150         if (is_repeater)
6151                 return 0;
6152
6153         /*
6154          * Errata for DP: As Stream type is used for encryption, Receiver
6155          * should be communicated with stream type for the decryption of the
6156          * content.
6157          * Repeater will be communicated with stream type as a part of it's
6158          * auth later in time.
6159          */
6160         stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
6161         stream_type_msg.stream_type = content_type;
6162
6163         return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,
6164                                         sizeof(stream_type_msg));
6165 }
6166
6167 static
6168 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
6169 {
6170         u8 rx_status;
6171         int ret;
6172
6173         ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
6174         if (ret)
6175                 return ret;
6176
6177         if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
6178                 ret = HDCP_REAUTH_REQUEST;
6179         else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
6180                 ret = HDCP_LINK_INTEGRITY_FAILURE;
6181         else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
6182                 ret = HDCP_TOPOLOGY_CHANGE;
6183
6184         return ret;
6185 }
6186
6187 static
6188 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
6189                            bool *capable)
6190 {
6191         u8 rx_caps[3];
6192         int ret;
6193
6194         *capable = false;
6195         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
6196                                DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
6197                                rx_caps, HDCP_2_2_RXCAPS_LEN);
6198         if (ret != HDCP_2_2_RXCAPS_LEN)
6199                 return ret >= 0 ? -EIO : ret;
6200
6201         if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
6202             HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
6203                 *capable = true;
6204
6205         return 0;
6206 }
6207
6208 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
6209         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
6210         .read_bksv = intel_dp_hdcp_read_bksv,
6211         .read_bstatus = intel_dp_hdcp_read_bstatus,
6212         .repeater_present = intel_dp_hdcp_repeater_present,
6213         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
6214         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
6215         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
6216         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
6217         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
6218         .check_link = intel_dp_hdcp_check_link,
6219         .hdcp_capable = intel_dp_hdcp_capable,
6220         .write_2_2_msg = intel_dp_hdcp2_write_msg,
6221         .read_2_2_msg = intel_dp_hdcp2_read_msg,
6222         .config_stream_type = intel_dp_hdcp2_config_stream_type,
6223         .check_2_2_link = intel_dp_hdcp2_check_link,
6224         .hdcp_2_2_capable = intel_dp_hdcp2_capable,
6225         .protocol = HDCP_PROTOCOL_DP,
6226 };
6227
6228 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6229 {
6230         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6231         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6232
6233         lockdep_assert_held(&dev_priv->pps_mutex);
6234
6235         if (!edp_have_panel_vdd(intel_dp))
6236                 return;
6237
6238         /*
6239          * The VDD bit needs a power domain reference, so if the bit is
6240          * already enabled when we boot or resume, grab this reference and
6241          * schedule a vdd off, so we don't hold on to the reference
6242          * indefinitely.
6243          */
6244         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
6245         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6246
6247         edp_panel_vdd_schedule_off(intel_dp);
6248 }
6249
6250 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
6251 {
6252         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6253         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6254         enum pipe pipe;
6255
6256         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
6257                                   encoder->port, &pipe))
6258                 return pipe;
6259
6260         return INVALID_PIPE;
6261 }
6262
6263 void intel_dp_encoder_reset(struct drm_encoder *encoder)
6264 {
6265         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6266         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6267         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
6268         intel_wakeref_t wakeref;
6269
6270         if (!HAS_DDI(dev_priv))
6271                 intel_dp->DP = I915_READ(intel_dp->output_reg);
6272
6273         if (lspcon->active)
6274                 lspcon_resume(lspcon);
6275
6276         intel_dp->reset_link_params = true;
6277
6278         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
6279             !intel_dp_is_edp(intel_dp))
6280                 return;
6281
6282         with_pps_lock(intel_dp, wakeref) {
6283                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6284                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6285
6286                 if (intel_dp_is_edp(intel_dp)) {
6287                         /*
6288                          * Reinit the power sequencer, in case BIOS did
6289                          * something nasty with it.
6290                          */
6291                         intel_dp_pps_init(intel_dp);
6292                         intel_edp_panel_vdd_sanitize(intel_dp);
6293                 }
6294         }
6295 }
6296
6297 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6298         .force = intel_dp_force,
6299         .fill_modes = drm_helper_probe_single_connector_modes,
6300         .atomic_get_property = intel_digital_connector_atomic_get_property,
6301         .atomic_set_property = intel_digital_connector_atomic_set_property,
6302         .late_register = intel_dp_connector_register,
6303         .early_unregister = intel_dp_connector_unregister,
6304         .destroy = intel_connector_destroy,
6305         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6306         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6307 };
6308
6309 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6310         .detect_ctx = intel_dp_detect,
6311         .get_modes = intel_dp_get_modes,
6312         .mode_valid = intel_dp_mode_valid,
6313         .atomic_check = intel_digital_connector_atomic_check,
6314 };
6315
6316 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6317         .reset = intel_dp_encoder_reset,
6318         .destroy = intel_dp_encoder_destroy,
6319 };
6320
6321 enum irqreturn
6322 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
6323 {
6324         struct intel_dp *intel_dp = &intel_dig_port->dp;
6325
6326         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
6327                 /*
6328                  * vdd off can generate a long pulse on eDP which
6329                  * would require vdd on to handle it, and thus we
6330                  * would end up in an endless cycle of
6331                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
6332                  */
6333                 DRM_DEBUG_KMS("ignoring long hpd on eDP [ENCODER:%d:%s]\n",
6334                               intel_dig_port->base.base.base.id,
6335                               intel_dig_port->base.base.name);
6336                 return IRQ_HANDLED;
6337         }
6338
6339         DRM_DEBUG_KMS("got hpd irq on [ENCODER:%d:%s] - %s\n",
6340                       intel_dig_port->base.base.base.id,
6341                       intel_dig_port->base.base.name,
6342                       long_hpd ? "long" : "short");
6343
6344         if (long_hpd) {
6345                 intel_dp->reset_link_params = true;
6346                 return IRQ_NONE;
6347         }
6348
6349         if (intel_dp->is_mst) {
6350                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
6351                         /*
6352                          * If we were in MST mode, and device is not
6353                          * there, get out of MST mode
6354                          */
6355                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
6356                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
6357                         intel_dp->is_mst = false;
6358                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6359                                                         intel_dp->is_mst);
6360
6361                         return IRQ_NONE;
6362                 }
6363         }
6364
6365         if (!intel_dp->is_mst) {
6366                 bool handled;
6367
6368                 handled = intel_dp_short_pulse(intel_dp);
6369
6370                 if (!handled)
6371                         return IRQ_NONE;
6372         }
6373
6374         return IRQ_HANDLED;
6375 }
6376
6377 /* check the VBT to see whether the eDP is on another port */
6378 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
6379 {
6380         /*
6381          * eDP not supported on g4x. so bail out early just
6382          * for a bit extra safety in case the VBT is bonkers.
6383          */
6384         if (INTEL_GEN(dev_priv) < 5)
6385                 return false;
6386
6387         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
6388                 return true;
6389
6390         return intel_bios_is_port_edp(dev_priv, port);
6391 }
6392
6393 static void
6394 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6395 {
6396         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6397         enum port port = dp_to_dig_port(intel_dp)->base.port;
6398
6399         if (!IS_G4X(dev_priv) && port != PORT_A)
6400                 intel_attach_force_audio_property(connector);
6401
6402         intel_attach_broadcast_rgb_property(connector);
6403         if (HAS_GMCH(dev_priv))
6404                 drm_connector_attach_max_bpc_property(connector, 6, 10);
6405         else if (INTEL_GEN(dev_priv) >= 5)
6406                 drm_connector_attach_max_bpc_property(connector, 6, 12);
6407
6408         if (intel_dp_is_edp(intel_dp)) {
6409                 u32 allowed_scalers;
6410
6411                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
6412                 if (!HAS_GMCH(dev_priv))
6413                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
6414
6415                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
6416
6417                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
6418
6419         }
6420 }
6421
6422 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
6423 {
6424         intel_dp->panel_power_off_time = ktime_get_boottime();
6425         intel_dp->last_power_on = jiffies;
6426         intel_dp->last_backlight_off = jiffies;
6427 }
6428
6429 static void
6430 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
6431 {
6432         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6433         u32 pp_on, pp_off, pp_ctl;
6434         struct pps_registers regs;
6435
6436         intel_pps_get_registers(intel_dp, &regs);
6437
6438         pp_ctl = ironlake_get_pp_control(intel_dp);
6439
6440         /* Ensure PPS is unlocked */
6441         if (!HAS_DDI(dev_priv))
6442                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6443
6444         pp_on = I915_READ(regs.pp_on);
6445         pp_off = I915_READ(regs.pp_off);
6446
6447         /* Pull timing values out of registers */
6448         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
6449         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
6450         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
6451         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
6452
6453         if (i915_mmio_reg_valid(regs.pp_div)) {
6454                 u32 pp_div;
6455
6456                 pp_div = I915_READ(regs.pp_div);
6457
6458                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
6459         } else {
6460                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
6461         }
6462 }
6463
6464 static void
6465 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
6466 {
6467         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
6468                       state_name,
6469                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
6470 }
6471
6472 static void
6473 intel_pps_verify_state(struct intel_dp *intel_dp)
6474 {
6475         struct edp_power_seq hw;
6476         struct edp_power_seq *sw = &intel_dp->pps_delays;
6477
6478         intel_pps_readout_hw_state(intel_dp, &hw);
6479
6480         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
6481             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
6482                 DRM_ERROR("PPS state mismatch\n");
6483                 intel_pps_dump_state("sw", sw);
6484                 intel_pps_dump_state("hw", &hw);
6485         }
6486 }
6487
6488 static void
6489 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
6490 {
6491         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6492         struct edp_power_seq cur, vbt, spec,
6493                 *final = &intel_dp->pps_delays;
6494
6495         lockdep_assert_held(&dev_priv->pps_mutex);
6496
6497         /* already initialized? */
6498         if (final->t11_t12 != 0)
6499                 return;
6500
6501         intel_pps_readout_hw_state(intel_dp, &cur);
6502
6503         intel_pps_dump_state("cur", &cur);
6504
6505         vbt = dev_priv->vbt.edp.pps;
6506         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
6507          * of 500ms appears to be too short. Ocassionally the panel
6508          * just fails to power back on. Increasing the delay to 800ms
6509          * seems sufficient to avoid this problem.
6510          */
6511         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
6512                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
6513                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
6514                               vbt.t11_t12);
6515         }
6516         /* T11_T12 delay is special and actually in units of 100ms, but zero
6517          * based in the hw (so we need to add 100 ms). But the sw vbt
6518          * table multiplies it with 1000 to make it in units of 100usec,
6519          * too. */
6520         vbt.t11_t12 += 100 * 10;
6521
6522         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
6523          * our hw here, which are all in 100usec. */
6524         spec.t1_t3 = 210 * 10;
6525         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
6526         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
6527         spec.t10 = 500 * 10;
6528         /* This one is special and actually in units of 100ms, but zero
6529          * based in the hw (so we need to add 100 ms). But the sw vbt
6530          * table multiplies it with 1000 to make it in units of 100usec,
6531          * too. */
6532         spec.t11_t12 = (510 + 100) * 10;
6533
6534         intel_pps_dump_state("vbt", &vbt);
6535
6536         /* Use the max of the register settings and vbt. If both are
6537          * unset, fall back to the spec limits. */
6538 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
6539                                        spec.field : \
6540                                        max(cur.field, vbt.field))
6541         assign_final(t1_t3);
6542         assign_final(t8);
6543         assign_final(t9);
6544         assign_final(t10);
6545         assign_final(t11_t12);
6546 #undef assign_final
6547
6548 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
6549         intel_dp->panel_power_up_delay = get_delay(t1_t3);
6550         intel_dp->backlight_on_delay = get_delay(t8);
6551         intel_dp->backlight_off_delay = get_delay(t9);
6552         intel_dp->panel_power_down_delay = get_delay(t10);
6553         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
6554 #undef get_delay
6555
6556         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
6557                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
6558                       intel_dp->panel_power_cycle_delay);
6559
6560         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
6561                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
6562
6563         /*
6564          * We override the HW backlight delays to 1 because we do manual waits
6565          * on them. For T8, even BSpec recommends doing it. For T9, if we
6566          * don't do this, we'll end up waiting for the backlight off delay
6567          * twice: once when we do the manual sleep, and once when we disable
6568          * the panel and wait for the PP_STATUS bit to become zero.
6569          */
6570         final->t8 = 1;
6571         final->t9 = 1;
6572
6573         /*
6574          * HW has only a 100msec granularity for t11_t12 so round it up
6575          * accordingly.
6576          */
6577         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
6578 }
6579
6580 static void
6581 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
6582                                               bool force_disable_vdd)
6583 {
6584         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6585         u32 pp_on, pp_off, port_sel = 0;
6586         int div = dev_priv->rawclk_freq / 1000;
6587         struct pps_registers regs;
6588         enum port port = dp_to_dig_port(intel_dp)->base.port;
6589         const struct edp_power_seq *seq = &intel_dp->pps_delays;
6590
6591         lockdep_assert_held(&dev_priv->pps_mutex);
6592
6593         intel_pps_get_registers(intel_dp, &regs);
6594
6595         /*
6596          * On some VLV machines the BIOS can leave the VDD
6597          * enabled even on power sequencers which aren't
6598          * hooked up to any port. This would mess up the
6599          * power domain tracking the first time we pick
6600          * one of these power sequencers for use since
6601          * edp_panel_vdd_on() would notice that the VDD was
6602          * already on and therefore wouldn't grab the power
6603          * domain reference. Disable VDD first to avoid this.
6604          * This also avoids spuriously turning the VDD on as
6605          * soon as the new power sequencer gets initialized.
6606          */
6607         if (force_disable_vdd) {
6608                 u32 pp = ironlake_get_pp_control(intel_dp);
6609
6610                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
6611
6612                 if (pp & EDP_FORCE_VDD)
6613                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
6614
6615                 pp &= ~EDP_FORCE_VDD;
6616
6617                 I915_WRITE(regs.pp_ctrl, pp);
6618         }
6619
6620         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
6621                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
6622         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
6623                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
6624
6625         /* Haswell doesn't have any port selection bits for the panel
6626          * power sequencer any more. */
6627         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6628                 port_sel = PANEL_PORT_SELECT_VLV(port);
6629         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
6630                 switch (port) {
6631                 case PORT_A:
6632                         port_sel = PANEL_PORT_SELECT_DPA;
6633                         break;
6634                 case PORT_C:
6635                         port_sel = PANEL_PORT_SELECT_DPC;
6636                         break;
6637                 case PORT_D:
6638                         port_sel = PANEL_PORT_SELECT_DPD;
6639                         break;
6640                 default:
6641                         MISSING_CASE(port);
6642                         break;
6643                 }
6644         }
6645
6646         pp_on |= port_sel;
6647
6648         I915_WRITE(regs.pp_on, pp_on);
6649         I915_WRITE(regs.pp_off, pp_off);
6650
6651         /*
6652          * Compute the divisor for the pp clock, simply match the Bspec formula.
6653          */
6654         if (i915_mmio_reg_valid(regs.pp_div)) {
6655                 I915_WRITE(regs.pp_div,
6656                            REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) |
6657                            REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
6658         } else {
6659                 u32 pp_ctl;
6660
6661                 pp_ctl = I915_READ(regs.pp_ctrl);
6662                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
6663                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
6664                 I915_WRITE(regs.pp_ctrl, pp_ctl);
6665         }
6666
6667         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
6668                       I915_READ(regs.pp_on),
6669                       I915_READ(regs.pp_off),
6670                       i915_mmio_reg_valid(regs.pp_div) ?
6671                       I915_READ(regs.pp_div) :
6672                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
6673 }
6674
6675 static void intel_dp_pps_init(struct intel_dp *intel_dp)
6676 {
6677         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6678
6679         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6680                 vlv_initial_power_sequencer_setup(intel_dp);
6681         } else {
6682                 intel_dp_init_panel_power_sequencer(intel_dp);
6683                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
6684         }
6685 }
6686
6687 /**
6688  * intel_dp_set_drrs_state - program registers for RR switch to take effect
6689  * @dev_priv: i915 device
6690  * @crtc_state: a pointer to the active intel_crtc_state
6691  * @refresh_rate: RR to be programmed
6692  *
6693  * This function gets called when refresh rate (RR) has to be changed from
6694  * one frequency to another. Switches can be between high and low RR
6695  * supported by the panel or to any other RR based on media playback (in
6696  * this case, RR value needs to be passed from user space).
6697  *
6698  * The caller of this function needs to take a lock on dev_priv->drrs.
6699  */
6700 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
6701                                     const struct intel_crtc_state *crtc_state,
6702                                     int refresh_rate)
6703 {
6704         struct intel_dp *intel_dp = dev_priv->drrs.dp;
6705         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
6706         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
6707
6708         if (refresh_rate <= 0) {
6709                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
6710                 return;
6711         }
6712
6713         if (intel_dp == NULL) {
6714                 DRM_DEBUG_KMS("DRRS not supported.\n");
6715                 return;
6716         }
6717
6718         if (!intel_crtc) {
6719                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
6720                 return;
6721         }
6722
6723         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
6724                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
6725                 return;
6726         }
6727
6728         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
6729                         refresh_rate)
6730                 index = DRRS_LOW_RR;
6731
6732         if (index == dev_priv->drrs.refresh_rate_type) {
6733                 DRM_DEBUG_KMS(
6734                         "DRRS requested for previously set RR...ignoring\n");
6735                 return;
6736         }
6737
6738         if (!crtc_state->base.active) {
6739                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
6740                 return;
6741         }
6742
6743         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
6744                 switch (index) {
6745                 case DRRS_HIGH_RR:
6746                         intel_dp_set_m_n(crtc_state, M1_N1);
6747                         break;
6748                 case DRRS_LOW_RR:
6749                         intel_dp_set_m_n(crtc_state, M2_N2);
6750                         break;
6751                 case DRRS_MAX_RR:
6752                 default:
6753                         DRM_ERROR("Unsupported refreshrate type\n");
6754                 }
6755         } else if (INTEL_GEN(dev_priv) > 6) {
6756                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
6757                 u32 val;
6758
6759                 val = I915_READ(reg);
6760                 if (index > DRRS_HIGH_RR) {
6761                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6762                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6763                         else
6764                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
6765                 } else {
6766                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6767                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
6768                         else
6769                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
6770                 }
6771                 I915_WRITE(reg, val);
6772         }
6773
6774         dev_priv->drrs.refresh_rate_type = index;
6775
6776         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
6777 }
6778
6779 /**
6780  * intel_edp_drrs_enable - init drrs struct if supported
6781  * @intel_dp: DP struct
6782  * @crtc_state: A pointer to the active crtc state.
6783  *
6784  * Initializes frontbuffer_bits and drrs.dp
6785  */
6786 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
6787                            const struct intel_crtc_state *crtc_state)
6788 {
6789         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6790
6791         if (!crtc_state->has_drrs) {
6792                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
6793                 return;
6794         }
6795
6796         if (dev_priv->psr.enabled) {
6797                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
6798                 return;
6799         }
6800
6801         mutex_lock(&dev_priv->drrs.mutex);
6802         if (dev_priv->drrs.dp) {
6803                 DRM_DEBUG_KMS("DRRS already enabled\n");
6804                 goto unlock;
6805         }
6806
6807         dev_priv->drrs.busy_frontbuffer_bits = 0;
6808
6809         dev_priv->drrs.dp = intel_dp;
6810
6811 unlock:
6812         mutex_unlock(&dev_priv->drrs.mutex);
6813 }
6814
6815 /**
6816  * intel_edp_drrs_disable - Disable DRRS
6817  * @intel_dp: DP struct
6818  * @old_crtc_state: Pointer to old crtc_state.
6819  *
6820  */
6821 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
6822                             const struct intel_crtc_state *old_crtc_state)
6823 {
6824         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6825
6826         if (!old_crtc_state->has_drrs)
6827                 return;
6828
6829         mutex_lock(&dev_priv->drrs.mutex);
6830         if (!dev_priv->drrs.dp) {
6831                 mutex_unlock(&dev_priv->drrs.mutex);
6832                 return;
6833         }
6834
6835         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6836                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
6837                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
6838
6839         dev_priv->drrs.dp = NULL;
6840         mutex_unlock(&dev_priv->drrs.mutex);
6841
6842         cancel_delayed_work_sync(&dev_priv->drrs.work);
6843 }
6844
6845 static void intel_edp_drrs_downclock_work(struct work_struct *work)
6846 {
6847         struct drm_i915_private *dev_priv =
6848                 container_of(work, typeof(*dev_priv), drrs.work.work);
6849         struct intel_dp *intel_dp;
6850
6851         mutex_lock(&dev_priv->drrs.mutex);
6852
6853         intel_dp = dev_priv->drrs.dp;
6854
6855         if (!intel_dp)
6856                 goto unlock;
6857
6858         /*
6859          * The delayed work can race with an invalidate hence we need to
6860          * recheck.
6861          */
6862
6863         if (dev_priv->drrs.busy_frontbuffer_bits)
6864                 goto unlock;
6865
6866         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
6867                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
6868
6869                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6870                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
6871         }
6872
6873 unlock:
6874         mutex_unlock(&dev_priv->drrs.mutex);
6875 }
6876
6877 /**
6878  * intel_edp_drrs_invalidate - Disable Idleness DRRS
6879  * @dev_priv: i915 device
6880  * @frontbuffer_bits: frontbuffer plane tracking bits
6881  *
6882  * This function gets called everytime rendering on the given planes start.
6883  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
6884  *
6885  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6886  */
6887 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
6888                                unsigned int frontbuffer_bits)
6889 {
6890         struct drm_crtc *crtc;
6891         enum pipe pipe;
6892
6893         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6894                 return;
6895
6896         cancel_delayed_work(&dev_priv->drrs.work);
6897
6898         mutex_lock(&dev_priv->drrs.mutex);
6899         if (!dev_priv->drrs.dp) {
6900                 mutex_unlock(&dev_priv->drrs.mutex);
6901                 return;
6902         }
6903
6904         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6905         pipe = to_intel_crtc(crtc)->pipe;
6906
6907         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6908         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
6909
6910         /* invalidate means busy screen hence upclock */
6911         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6912                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6913                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6914
6915         mutex_unlock(&dev_priv->drrs.mutex);
6916 }
6917
6918 /**
6919  * intel_edp_drrs_flush - Restart Idleness DRRS
6920  * @dev_priv: i915 device
6921  * @frontbuffer_bits: frontbuffer plane tracking bits
6922  *
6923  * This function gets called every time rendering on the given planes has
6924  * completed or flip on a crtc is completed. So DRRS should be upclocked
6925  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
6926  * if no other planes are dirty.
6927  *
6928  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
6929  */
6930 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
6931                           unsigned int frontbuffer_bits)
6932 {
6933         struct drm_crtc *crtc;
6934         enum pipe pipe;
6935
6936         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
6937                 return;
6938
6939         cancel_delayed_work(&dev_priv->drrs.work);
6940
6941         mutex_lock(&dev_priv->drrs.mutex);
6942         if (!dev_priv->drrs.dp) {
6943                 mutex_unlock(&dev_priv->drrs.mutex);
6944                 return;
6945         }
6946
6947         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
6948         pipe = to_intel_crtc(crtc)->pipe;
6949
6950         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
6951         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
6952
6953         /* flush means busy screen hence upclock */
6954         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
6955                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
6956                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
6957
6958         /*
6959          * flush also means no more activity hence schedule downclock, if all
6960          * other fbs are quiescent too
6961          */
6962         if (!dev_priv->drrs.busy_frontbuffer_bits)
6963                 schedule_delayed_work(&dev_priv->drrs.work,
6964                                 msecs_to_jiffies(1000));
6965         mutex_unlock(&dev_priv->drrs.mutex);
6966 }
6967
6968 /**
6969  * DOC: Display Refresh Rate Switching (DRRS)
6970  *
6971  * Display Refresh Rate Switching (DRRS) is a power conservation feature
6972  * which enables swtching between low and high refresh rates,
6973  * dynamically, based on the usage scenario. This feature is applicable
6974  * for internal panels.
6975  *
6976  * Indication that the panel supports DRRS is given by the panel EDID, which
6977  * would list multiple refresh rates for one resolution.
6978  *
6979  * DRRS is of 2 types - static and seamless.
6980  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
6981  * (may appear as a blink on screen) and is used in dock-undock scenario.
6982  * Seamless DRRS involves changing RR without any visual effect to the user
6983  * and can be used during normal system usage. This is done by programming
6984  * certain registers.
6985  *
6986  * Support for static/seamless DRRS may be indicated in the VBT based on
6987  * inputs from the panel spec.
6988  *
6989  * DRRS saves power by switching to low RR based on usage scenarios.
6990  *
6991  * The implementation is based on frontbuffer tracking implementation.  When
6992  * there is a disturbance on the screen triggered by user activity or a periodic
6993  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6994  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6995  * made.
6996  *
6997  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6998  * and intel_edp_drrs_flush() are called.
6999  *
7000  * DRRS can be further extended to support other internal panels and also
7001  * the scenario of video playback wherein RR is set based on the rate
7002  * requested by userspace.
7003  */
7004
7005 /**
7006  * intel_dp_drrs_init - Init basic DRRS work and mutex.
7007  * @connector: eDP connector
7008  * @fixed_mode: preferred mode of panel
7009  *
7010  * This function is  called only once at driver load to initialize basic
7011  * DRRS stuff.
7012  *
7013  * Returns:
7014  * Downclock mode if panel supports it, else return NULL.
7015  * DRRS support is determined by the presence of downclock mode (apart
7016  * from VBT setting).
7017  */
7018 static struct drm_display_mode *
7019 intel_dp_drrs_init(struct intel_connector *connector,
7020                    struct drm_display_mode *fixed_mode)
7021 {
7022         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7023         struct drm_display_mode *downclock_mode = NULL;
7024
7025         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
7026         mutex_init(&dev_priv->drrs.mutex);
7027
7028         if (INTEL_GEN(dev_priv) <= 6) {
7029                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
7030                 return NULL;
7031         }
7032
7033         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
7034                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
7035                 return NULL;
7036         }
7037
7038         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
7039         if (!downclock_mode) {
7040                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
7041                 return NULL;
7042         }
7043
7044         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
7045
7046         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
7047         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
7048         return downclock_mode;
7049 }
7050
7051 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
7052                                      struct intel_connector *intel_connector)
7053 {
7054         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7055         struct drm_device *dev = &dev_priv->drm;
7056         struct drm_connector *connector = &intel_connector->base;
7057         struct drm_display_mode *fixed_mode = NULL;
7058         struct drm_display_mode *downclock_mode = NULL;
7059         bool has_dpcd;
7060         enum pipe pipe = INVALID_PIPE;
7061         intel_wakeref_t wakeref;
7062         struct edid *edid;
7063
7064         if (!intel_dp_is_edp(intel_dp))
7065                 return true;
7066
7067         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
7068
7069         /*
7070          * On IBX/CPT we may get here with LVDS already registered. Since the
7071          * driver uses the only internal power sequencer available for both
7072          * eDP and LVDS bail out early in this case to prevent interfering
7073          * with an already powered-on LVDS power sequencer.
7074          */
7075         if (intel_get_lvds_encoder(dev_priv)) {
7076                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7077                 DRM_INFO("LVDS was detected, not registering eDP\n");
7078
7079                 return false;
7080         }
7081
7082         with_pps_lock(intel_dp, wakeref) {
7083                 intel_dp_init_panel_power_timestamps(intel_dp);
7084                 intel_dp_pps_init(intel_dp);
7085                 intel_edp_panel_vdd_sanitize(intel_dp);
7086         }
7087
7088         /* Cache DPCD and EDID for edp. */
7089         has_dpcd = intel_edp_init_dpcd(intel_dp);
7090
7091         if (!has_dpcd) {
7092                 /* if this fails, presume the device is a ghost */
7093                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
7094                 goto out_vdd_off;
7095         }
7096
7097         mutex_lock(&dev->mode_config.mutex);
7098         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
7099         if (edid) {
7100                 if (drm_add_edid_modes(connector, edid)) {
7101                         drm_connector_update_edid_property(connector,
7102                                                                 edid);
7103                 } else {
7104                         kfree(edid);
7105                         edid = ERR_PTR(-EINVAL);
7106                 }
7107         } else {
7108                 edid = ERR_PTR(-ENOENT);
7109         }
7110         intel_connector->edid = edid;
7111
7112         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
7113         if (fixed_mode)
7114                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
7115
7116         /* fallback to VBT if available for eDP */
7117         if (!fixed_mode)
7118                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
7119         mutex_unlock(&dev->mode_config.mutex);
7120
7121         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7122                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
7123                 register_reboot_notifier(&intel_dp->edp_notifier);
7124
7125                 /*
7126                  * Figure out the current pipe for the initial backlight setup.
7127                  * If the current pipe isn't valid, try the PPS pipe, and if that
7128                  * fails just assume pipe A.
7129                  */
7130                 pipe = vlv_active_pipe(intel_dp);
7131
7132                 if (pipe != PIPE_A && pipe != PIPE_B)
7133                         pipe = intel_dp->pps_pipe;
7134
7135                 if (pipe != PIPE_A && pipe != PIPE_B)
7136                         pipe = PIPE_A;
7137
7138                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
7139                               pipe_name(pipe));
7140         }
7141
7142         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
7143         intel_connector->panel.backlight.power = intel_edp_backlight_power;
7144         intel_panel_setup_backlight(connector, pipe);
7145
7146         if (fixed_mode)
7147                 drm_connector_init_panel_orientation_property(
7148                         connector, fixed_mode->hdisplay, fixed_mode->vdisplay);
7149
7150         return true;
7151
7152 out_vdd_off:
7153         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
7154         /*
7155          * vdd might still be enabled do to the delayed vdd off.
7156          * Make sure vdd is actually turned off here.
7157          */
7158         with_pps_lock(intel_dp, wakeref)
7159                 edp_panel_vdd_off_sync(intel_dp);
7160
7161         return false;
7162 }
7163
7164 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
7165 {
7166         struct intel_connector *intel_connector;
7167         struct drm_connector *connector;
7168
7169         intel_connector = container_of(work, typeof(*intel_connector),
7170                                        modeset_retry_work);
7171         connector = &intel_connector->base;
7172         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
7173                       connector->name);
7174
7175         /* Grab the locks before changing connector property*/
7176         mutex_lock(&connector->dev->mode_config.mutex);
7177         /* Set connector link status to BAD and send a Uevent to notify
7178          * userspace to do a modeset.
7179          */
7180         drm_connector_set_link_status_property(connector,
7181                                                DRM_MODE_LINK_STATUS_BAD);
7182         mutex_unlock(&connector->dev->mode_config.mutex);
7183         /* Send Hotplug uevent so userspace can reprobe */
7184         drm_kms_helper_hotplug_event(connector->dev);
7185 }
7186
7187 bool
7188 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
7189                         struct intel_connector *intel_connector)
7190 {
7191         struct drm_connector *connector = &intel_connector->base;
7192         struct intel_dp *intel_dp = &intel_dig_port->dp;
7193         struct intel_encoder *intel_encoder = &intel_dig_port->base;
7194         struct drm_device *dev = intel_encoder->base.dev;
7195         struct drm_i915_private *dev_priv = to_i915(dev);
7196         enum port port = intel_encoder->port;
7197         enum phy phy = intel_port_to_phy(dev_priv, port);
7198         int type;
7199
7200         /* Initialize the work for modeset in case of link train failure */
7201         INIT_WORK(&intel_connector->modeset_retry_work,
7202                   intel_dp_modeset_retry_work_fn);
7203
7204         if (WARN(intel_dig_port->max_lanes < 1,
7205                  "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
7206                  intel_dig_port->max_lanes, intel_encoder->base.base.id,
7207                  intel_encoder->base.name))
7208                 return false;
7209
7210         intel_dp_set_source_rates(intel_dp);
7211
7212         intel_dp->reset_link_params = true;
7213         intel_dp->pps_pipe = INVALID_PIPE;
7214         intel_dp->active_pipe = INVALID_PIPE;
7215
7216         /* Preserve the current hw state. */
7217         intel_dp->DP = I915_READ(intel_dp->output_reg);
7218         intel_dp->attached_connector = intel_connector;
7219
7220         if (intel_dp_is_port_edp(dev_priv, port)) {
7221                 /*
7222                  * Currently we don't support eDP on TypeC ports, although in
7223                  * theory it could work on TypeC legacy ports.
7224                  */
7225                 WARN_ON(intel_phy_is_tc(dev_priv, phy));
7226                 type = DRM_MODE_CONNECTOR_eDP;
7227         } else {
7228                 type = DRM_MODE_CONNECTOR_DisplayPort;
7229         }
7230
7231         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7232                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
7233
7234         /*
7235          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
7236          * for DP the encoder type can be set by the caller to
7237          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
7238          */
7239         if (type == DRM_MODE_CONNECTOR_eDP)
7240                 intel_encoder->type = INTEL_OUTPUT_EDP;
7241
7242         /* eDP only on port B and/or C on vlv/chv */
7243         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7244                     intel_dp_is_edp(intel_dp) &&
7245                     port != PORT_B && port != PORT_C))
7246                 return false;
7247
7248         DRM_DEBUG_KMS("Adding %s connector on [ENCODER:%d:%s]\n",
7249                       type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
7250                       intel_encoder->base.base.id, intel_encoder->base.name);
7251
7252         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
7253         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
7254
7255         if (!HAS_GMCH(dev_priv))
7256                 connector->interlace_allowed = true;
7257         connector->doublescan_allowed = 0;
7258
7259         if (INTEL_GEN(dev_priv) >= 11)
7260                 connector->ycbcr_420_allowed = true;
7261
7262         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
7263
7264         intel_dp_aux_init(intel_dp);
7265
7266         intel_connector_attach_encoder(intel_connector, intel_encoder);
7267
7268         if (HAS_DDI(dev_priv))
7269                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
7270         else
7271                 intel_connector->get_hw_state = intel_connector_get_hw_state;
7272
7273         /* init MST on ports that can support it */
7274         if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) &&
7275             (port == PORT_B || port == PORT_C ||
7276              port == PORT_D || port == PORT_F))
7277                 intel_dp_mst_encoder_init(intel_dig_port,
7278                                           intel_connector->base.base.id);
7279
7280         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
7281                 intel_dp_aux_fini(intel_dp);
7282                 intel_dp_mst_encoder_cleanup(intel_dig_port);
7283                 goto fail;
7284         }
7285
7286         intel_dp_add_properties(intel_dp, connector);
7287
7288         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
7289                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
7290                 if (ret)
7291                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
7292         }
7293
7294         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
7295          * 0xd.  Failure to do so will result in spurious interrupts being
7296          * generated on the port when a cable is not attached.
7297          */
7298         if (IS_G45(dev_priv)) {
7299                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
7300                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
7301         }
7302
7303         return true;
7304
7305 fail:
7306         drm_connector_cleanup(connector);
7307
7308         return false;
7309 }
7310
7311 bool intel_dp_init(struct drm_i915_private *dev_priv,
7312                    i915_reg_t output_reg,
7313                    enum port port)
7314 {
7315         struct intel_digital_port *intel_dig_port;
7316         struct intel_encoder *intel_encoder;
7317         struct drm_encoder *encoder;
7318         struct intel_connector *intel_connector;
7319
7320         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
7321         if (!intel_dig_port)
7322                 return false;
7323
7324         intel_connector = intel_connector_alloc();
7325         if (!intel_connector)
7326                 goto err_connector_alloc;
7327
7328         intel_encoder = &intel_dig_port->base;
7329         encoder = &intel_encoder->base;
7330
7331         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
7332                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
7333                              "DP %c", port_name(port)))
7334                 goto err_encoder_init;
7335
7336         intel_encoder->hotplug = intel_dp_hotplug;
7337         intel_encoder->compute_config = intel_dp_compute_config;
7338         intel_encoder->get_hw_state = intel_dp_get_hw_state;
7339         intel_encoder->get_config = intel_dp_get_config;
7340         intel_encoder->update_pipe = intel_panel_update_backlight;
7341         intel_encoder->suspend = intel_dp_encoder_suspend;
7342         if (IS_CHERRYVIEW(dev_priv)) {
7343                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
7344                 intel_encoder->pre_enable = chv_pre_enable_dp;
7345                 intel_encoder->enable = vlv_enable_dp;
7346                 intel_encoder->disable = vlv_disable_dp;
7347                 intel_encoder->post_disable = chv_post_disable_dp;
7348                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
7349         } else if (IS_VALLEYVIEW(dev_priv)) {
7350                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
7351                 intel_encoder->pre_enable = vlv_pre_enable_dp;
7352                 intel_encoder->enable = vlv_enable_dp;
7353                 intel_encoder->disable = vlv_disable_dp;
7354                 intel_encoder->post_disable = vlv_post_disable_dp;
7355         } else {
7356                 intel_encoder->pre_enable = g4x_pre_enable_dp;
7357                 intel_encoder->enable = g4x_enable_dp;
7358                 intel_encoder->disable = g4x_disable_dp;
7359                 intel_encoder->post_disable = g4x_post_disable_dp;
7360         }
7361
7362         intel_dig_port->dp.output_reg = output_reg;
7363         intel_dig_port->max_lanes = 4;
7364
7365         intel_encoder->type = INTEL_OUTPUT_DP;
7366         intel_encoder->power_domain = intel_port_to_power_domain(port);
7367         if (IS_CHERRYVIEW(dev_priv)) {
7368                 if (port == PORT_D)
7369                         intel_encoder->crtc_mask = 1 << 2;
7370                 else
7371                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
7372         } else {
7373                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
7374         }
7375         intel_encoder->cloneable = 0;
7376         intel_encoder->port = port;
7377
7378         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
7379
7380         if (port != PORT_A)
7381                 intel_infoframe_init(intel_dig_port);
7382
7383         intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
7384         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
7385                 goto err_init_connector;
7386
7387         return true;
7388
7389 err_init_connector:
7390         drm_encoder_cleanup(encoder);
7391 err_encoder_init:
7392         kfree(intel_connector);
7393 err_connector_alloc:
7394         kfree(intel_dig_port);
7395         return false;
7396 }
7397
7398 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
7399 {
7400         struct intel_encoder *encoder;
7401
7402         for_each_intel_encoder(&dev_priv->drm, encoder) {
7403                 struct intel_dp *intel_dp;
7404
7405                 if (encoder->type != INTEL_OUTPUT_DDI)
7406                         continue;
7407
7408                 intel_dp = enc_to_intel_dp(&encoder->base);
7409
7410                 if (!intel_dp->can_mst)
7411                         continue;
7412
7413                 if (intel_dp->is_mst)
7414                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
7415         }
7416 }
7417
7418 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
7419 {
7420         struct intel_encoder *encoder;
7421
7422         for_each_intel_encoder(&dev_priv->drm, encoder) {
7423                 struct intel_dp *intel_dp;
7424                 int ret;
7425
7426                 if (encoder->type != INTEL_OUTPUT_DDI)
7427                         continue;
7428
7429                 intel_dp = enc_to_intel_dp(&encoder->base);
7430
7431                 if (!intel_dp->can_mst)
7432                         continue;
7433
7434                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
7435                 if (ret) {
7436                         intel_dp->is_mst = false;
7437                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
7438                                                         false);
7439                 }
7440         }
7441 }