drivers/gpu/drm/armada/armada_crtc.c

   1 /*
   2  * Copyright (C) 2012 Russell King
   3  *  Rewritten from the dovefb driver, and Armada510 manuals.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9 #include <linux/clk.h>
  10 #include <linux/component.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <drm/drmP.h>
  14 #include <drm/drm_crtc_helper.h>
  15 #include <drm/drm_plane_helper.h>
  16 #include "armada_crtc.h"
  17 #include "armada_drm.h"
  18 #include "armada_fb.h"
  19 #include "armada_gem.h"
  20 #include "armada_hw.h"
  21 #include "armada_trace.h"
  22
  23 struct armada_frame_work {
  24         struct armada_plane_work work;
  25         struct drm_pending_vblank_event *event;
  26         struct armada_regs regs[4];
  27         struct drm_framebuffer *old_fb;
  28 };
  29
  30 enum csc_mode {
  31         CSC_AUTO = 0,
  32         CSC_YUV_CCIR601 = 1,
  33         CSC_YUV_CCIR709 = 2,
  34         CSC_RGB_COMPUTER = 1,
  35         CSC_RGB_STUDIO = 2,
  36 };
  37
  38 static const uint32_t armada_primary_formats[] = {
  39         DRM_FORMAT_UYVY,
  40         DRM_FORMAT_YUYV,
  41         DRM_FORMAT_VYUY,
  42         DRM_FORMAT_YVYU,
  43         DRM_FORMAT_ARGB8888,
  44         DRM_FORMAT_ABGR8888,
  45         DRM_FORMAT_XRGB8888,
  46         DRM_FORMAT_XBGR8888,
  47         DRM_FORMAT_RGB888,
  48         DRM_FORMAT_BGR888,
  49         DRM_FORMAT_ARGB1555,
  50         DRM_FORMAT_ABGR1555,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_BGR565,
  53 };
  54
  55 /*
  56  * A note about interlacing.  Let's consider HDMI 1920x1080i.
  57  * The timing parameters we have from X are:
  58  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  59  *  1920 2448 2492 2640  1080 1084 1094 1125
  60  * Which get translated to:
  61  *  Hact HsyA HsyI Htot  Vact VsyA VsyI Vtot
  62  *  1920 2448 2492 2640   540  542  547  562
  63  *
  64  * This is how it is defined by CEA-861-D - line and pixel numbers are
  65  * referenced to the rising edge of VSYNC and HSYNC.  Total clocks per
  66  * line: 2640.  The odd frame, the first active line is at line 21, and
  67  * the even frame, the first active line is 584.
  68  *
  69  * LN:    560     561     562     563             567     568    569
  70  * DE:    ~~~|____________________________//__________________________
  71  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  72  * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
  73  *  22 blanking lines.  VSYNC at 1320 (referenced to the HSYNC rising edge).
  74  *
  75  * LN:    1123   1124    1125      1               5       6      7
  76  * DE:    ~~~|____________________________//__________________________
  77  * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
  78  * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
  79  *  23 blanking lines
  80  *
  81  * The Armada LCD Controller line and pixel numbers are, like X timings,
  82  * referenced to the top left of the active frame.
  83  *
  84  * So, translating these to our LCD controller:
  85  *  Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
  86  *  Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
  87  * Note: Vsync front porch remains constant!
  88  *
  89  * if (odd_frame) {
  90  *   vtotal = mode->crtc_vtotal + 1;
  91  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
  92  *   vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
  93  * } else {
  94  *   vtotal = mode->crtc_vtotal;
  95  *   vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
  96  *   vhorizpos = mode->crtc_hsync_start;
  97  * }
  98  * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
  99  *
 100  * So, we need to reprogram these registers on each vsync event:
 101  *  LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
 102  *
 103  * Note: we do not use the frame done interrupts because these appear
 104  * to happen too early, and lead to jitter on the display (presumably
 105  * they occur at the end of the last active line, before the vsync back
 106  * porch, which we're reprogramming.)
 107  */
 108
 109 void
 110 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
 111 {
 112         while (regs->offset != ~0) {
 113                 void __iomem *reg = dcrtc->base + regs->offset;
 114                 uint32_t val;
 115
 116                 val = regs->mask;
 117                 if (val != 0)
 118                         val &= readl_relaxed(reg);
 119                 writel_relaxed(val | regs->val, reg);
 120                 ++regs;
 121         }
 122 }
 123
 124 #define dpms_blanked(dpms)      ((dpms) != DRM_MODE_DPMS_ON)
 125
 126 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
 127 {
 128         uint32_t dumb_ctrl;
 129
 130         dumb_ctrl = dcrtc->cfg_dumb_ctrl;
 131
 132         if (!dpms_blanked(dcrtc->dpms))
 133                 dumb_ctrl |= CFG_DUMB_ENA;
 134
 135         /*
 136          * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
 137          * be using SPI or GPIO.  If we set this to DUMB_BLANK, we will
 138          * force LCD_D[23:0] to output blank color, overriding the GPIO or
 139          * SPI usage.  So leave it as-is unless in DUMB24_RGB888_0 mode.
 140          */
 141         if (dpms_blanked(dcrtc->dpms) &&
 142             (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
 143                 dumb_ctrl &= ~DUMB_MASK;
 144                 dumb_ctrl |= DUMB_BLANK;
 145         }
 146
 147         /*
 148          * The documentation doesn't indicate what the normal state of
 149          * the sync signals are.  Sebastian Hesselbart kindly probed
 150          * these signals on his board to determine their state.
 151          *
 152          * The non-inverted state of the sync signals is active high.
 153          * Setting these bits makes the appropriate signal active low.
 154          */
 155         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
 156                 dumb_ctrl |= CFG_INV_CSYNC;
 157         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
 158                 dumb_ctrl |= CFG_INV_HSYNC;
 159         if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
 160                 dumb_ctrl |= CFG_INV_VSYNC;
 161
 162         if (dcrtc->dumb_ctrl != dumb_ctrl) {
 163                 dcrtc->dumb_ctrl = dumb_ctrl;
 164                 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
 165         }
 166 }
 167
 168 void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb,
 169         int x, int y)
 170 {
 171         u32 addr = drm_fb_obj(fb)->dev_addr;
 172         u32 pixel_format = fb->pixel_format;
 173         int num_planes = drm_format_num_planes(pixel_format);
 174         int i;
 175
 176         if (num_planes > 3)
 177                 num_planes = 3;
 178
 179         for (i = 0; i < num_planes; i++)
 180                 addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] +
 181                              x * drm_format_plane_cpp(pixel_format, i);
 182         for (; i < 3; i++)
 183                 addrs[i] = 0;
 184 }
 185
 186 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
 187         int x, int y, struct armada_regs *regs, bool interlaced)
 188 {
 189         unsigned pitch = fb->pitches[0];
 190         u32 addrs[3], addr_odd, addr_even;
 191         unsigned i = 0;
 192
 193         DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
 194                 pitch, x, y, fb->bits_per_pixel);
 195
 196         armada_drm_plane_calc_addrs(addrs, fb, x, y);
 197
 198         addr_odd = addr_even = addrs[0];
 199
 200         if (interlaced) {
 201                 addr_even += pitch;
 202                 pitch *= 2;
 203         }
 204
 205         /* write offset, base, and pitch */
 206         armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
 207         armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
 208         armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
 209
 210         return i;
 211 }
 212
 213 static void armada_drm_plane_work_run(struct armada_crtc *dcrtc,
 214         struct drm_plane *plane)
 215 {
 216         struct armada_plane *dplane = drm_to_armada_plane(plane);
 217         struct armada_plane_work *work = xchg(&dplane->work, NULL);
 218
 219         /* Handle any pending frame work. */
 220         if (work) {
 221                 work->fn(dcrtc, dplane, work);
 222                 drm_crtc_vblank_put(&dcrtc->crtc);
 223         }
 224
 225         wake_up(&dplane->frame_wait);
 226 }
 227
 228 int armada_drm_plane_work_queue(struct armada_crtc *dcrtc,
 229         struct armada_plane *plane, struct armada_plane_work *work)
 230 {
 231         int ret;
 232
 233         ret = drm_crtc_vblank_get(&dcrtc->crtc);
 234         if (ret) {
 235                 DRM_ERROR("failed to acquire vblank counter\n");
 236                 return ret;
 237         }
 238
 239         ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0;
 240         if (ret)
 241                 drm_crtc_vblank_put(&dcrtc->crtc);
 242
 243         return ret;
 244 }
 245
 246 int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout)
 247 {
 248         return wait_event_timeout(plane->frame_wait, !plane->work, timeout);
 249 }
 250
 251 struct armada_plane_work *armada_drm_plane_work_cancel(
 252         struct armada_crtc *dcrtc, struct armada_plane *plane)
 253 {
 254         struct armada_plane_work *work = xchg(&plane->work, NULL);
 255
 256         if (work)
 257                 drm_crtc_vblank_put(&dcrtc->crtc);
 258
 259         return work;
 260 }
 261
 262 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
 263         struct armada_frame_work *work)
 264 {
 265         struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary);
 266
 267         return armada_drm_plane_work_queue(dcrtc, plane, &work->work);
 268 }
 269
 270 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc,
 271         struct armada_plane *plane, struct armada_plane_work *work)
 272 {
 273         struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work);
 274         struct drm_device *dev = dcrtc->crtc.dev;
 275         unsigned long flags;
 276
 277         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 278         armada_drm_crtc_update_regs(dcrtc, fwork->regs);
 279         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 280
 281         if (fwork->event) {
 282                 spin_lock_irqsave(&dev->event_lock, flags);
 283                 drm_crtc_send_vblank_event(&dcrtc->crtc, fwork->event);
 284                 spin_unlock_irqrestore(&dev->event_lock, flags);
 285         }
 286
 287         /* Finally, queue the process-half of the cleanup. */
 288         __armada_drm_queue_unref_work(dcrtc->crtc.dev, fwork->old_fb);
 289         kfree(fwork);
 290 }
 291
 292 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
 293         struct drm_framebuffer *fb, bool force)
 294 {
 295         struct armada_frame_work *work;
 296
 297         if (!fb)
 298                 return;
 299
 300         if (force) {
 301                 /* Display is disabled, so just drop the old fb */
 302                 drm_framebuffer_unreference(fb);
 303                 return;
 304         }
 305
 306         work = kmalloc(sizeof(*work), GFP_KERNEL);
 307         if (work) {
 308                 int i = 0;
 309                 work->work.fn = armada_drm_crtc_complete_frame_work;
 310                 work->event = NULL;
 311                 work->old_fb = fb;
 312                 armada_reg_queue_end(work->regs, i);
 313
 314                 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
 315                         return;
 316
 317                 kfree(work);
 318         }
 319
 320         /*
 321          * Oops - just drop the reference immediately and hope for
 322          * the best.  The worst that will happen is the buffer gets
 323          * reused before it has finished being displayed.
 324          */
 325         drm_framebuffer_unreference(fb);
 326 }
 327
 328 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
 329 {
 330         /*
 331          * Tell the DRM core that vblank IRQs aren't going to happen for
 332          * a while.  This cleans up any pending vblank events for us.
 333          */
 334         drm_crtc_vblank_off(&dcrtc->crtc);
 335         armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
 336 }
 337
 338 void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
 339         int idx)
 340 {
 341 }
 342
 343 void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 344         int idx)
 345 {
 346 }
 347
 348 /* The mode_config.mutex will be held for this call */
 349 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
 350 {
 351         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 352
 353         if (dpms_blanked(dcrtc->dpms) != dpms_blanked(dpms)) {
 354                 if (dpms_blanked(dpms))
 355                         armada_drm_vblank_off(dcrtc);
 356                 else if (!IS_ERR(dcrtc->clk))
 357                         WARN_ON(clk_prepare_enable(dcrtc->clk));
 358                 dcrtc->dpms = dpms;
 359                 armada_drm_crtc_update(dcrtc);
 360                 if (!dpms_blanked(dpms))
 361                         drm_crtc_vblank_on(&dcrtc->crtc);
 362                 else if (!IS_ERR(dcrtc->clk))
 363                         clk_disable_unprepare(dcrtc->clk);
 364         } else if (dcrtc->dpms != dpms) {
 365                 dcrtc->dpms = dpms;
 366         }
 367 }
 368
 369 /*
 370  * Prepare for a mode set.  Turn off overlay to ensure that we don't end
 371  * up with the overlay size being bigger than the active screen size.
 372  * We rely upon X refreshing this state after the mode set has completed.
 373  *
 374  * The mode_config.mutex will be held for this call
 375  */
 376 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
 377 {
 378         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 379         struct drm_plane *plane;
 380
 381         /*
 382          * If we have an overlay plane associated with this CRTC, disable
 383          * it before the modeset to avoid its coordinates being outside
 384          * the new mode parameters.
 385          */
 386         plane = dcrtc->plane;
 387         if (plane)
 388                 drm_plane_force_disable(plane);
 389 }
 390
 391 /* The mode_config.mutex will be held for this call */
 392 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
 393 {
 394         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 395
 396         if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
 397                 dcrtc->dpms = DRM_MODE_DPMS_ON;
 398                 armada_drm_crtc_update(dcrtc);
 399         }
 400 }
 401
 402 /* The mode_config.mutex will be held for this call */
 403 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
 404         const struct drm_display_mode *mode, struct drm_display_mode *adj)
 405 {
 406         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 407         int ret;
 408
 409         /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
 410         if (!dcrtc->variant->has_spu_adv_reg &&
 411             adj->flags & DRM_MODE_FLAG_INTERLACE)
 412                 return false;
 413
 414         /* Check whether the display mode is possible */
 415         ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
 416         if (ret)
 417                 return false;
 418
 419         return true;
 420 }
 421
 422 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
 423 {
 424         void __iomem *base = dcrtc->base;
 425         struct drm_plane *ovl_plane;
 426
 427         if (stat & DMA_FF_UNDERFLOW)
 428                 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
 429         if (stat & GRA_FF_UNDERFLOW)
 430                 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
 431
 432         if (stat & VSYNC_IRQ)
 433                 drm_crtc_handle_vblank(&dcrtc->crtc);
 434
 435         spin_lock(&dcrtc->irq_lock);
 436         ovl_plane = dcrtc->plane;
 437         if (ovl_plane)
 438                 armada_drm_plane_work_run(dcrtc, ovl_plane);
 439
 440         if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
 441                 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
 442                 uint32_t val;
 443
 444                 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
 445                 writel_relaxed(dcrtc->v[i].spu_v_h_total,
 446                                base + LCD_SPUT_V_H_TOTAL);
 447
 448                 val = readl_relaxed(base + LCD_SPU_ADV_REG);
 449                 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
 450                 val |= dcrtc->v[i].spu_adv_reg;
 451                 writel_relaxed(val, base + LCD_SPU_ADV_REG);
 452         }
 453
 454         if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
 455                 writel_relaxed(dcrtc->cursor_hw_pos,
 456                                base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 457                 writel_relaxed(dcrtc->cursor_hw_sz,
 458                                base + LCD_SPU_HWC_HPXL_VLN);
 459                 armada_updatel(CFG_HWC_ENA,
 460                                CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
 461                                base + LCD_SPU_DMA_CTRL0);
 462                 dcrtc->cursor_update = false;
 463                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 464         }
 465
 466         spin_unlock(&dcrtc->irq_lock);
 467
 468         if (stat & GRA_FRAME_IRQ)
 469                 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
 470 }
 471
 472 static irqreturn_t armada_drm_irq(int irq, void *arg)
 473 {
 474         struct armada_crtc *dcrtc = arg;
 475         u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
 476
 477         /*
 478          * This is rediculous - rather than writing bits to clear, we
 479          * have to set the actual status register value.  This is racy.
 480          */
 481         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 482
 483         trace_armada_drm_irq(&dcrtc->crtc, stat);
 484
 485         /* Mask out those interrupts we haven't enabled */
 486         v = stat & dcrtc->irq_ena;
 487
 488         if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
 489                 armada_drm_crtc_irq(dcrtc, stat);
 490                 return IRQ_HANDLED;
 491         }
 492         return IRQ_NONE;
 493 }
 494
 495 /* These are locked by dev->vbl_lock */
 496 void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
 497 {
 498         if (dcrtc->irq_ena & mask) {
 499                 dcrtc->irq_ena &= ~mask;
 500                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 501         }
 502 }
 503
 504 void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
 505 {
 506         if ((dcrtc->irq_ena & mask) != mask) {
 507                 dcrtc->irq_ena |= mask;
 508                 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
 509                 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
 510                         writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
 511         }
 512 }
 513
 514 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
 515 {
 516         struct drm_display_mode *adj = &dcrtc->crtc.mode;
 517         uint32_t val = 0;
 518
 519         if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
 520                 val |= CFG_CSC_YUV_CCIR709;
 521         if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
 522                 val |= CFG_CSC_RGB_STUDIO;
 523
 524         /*
 525          * In auto mode, set the colorimetry, based upon the HDMI spec.
 526          * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
 527          * ITU601.  It may be more appropriate to set this depending on
 528          * the source - but what if the graphic frame is YUV and the
 529          * video frame is RGB?
 530          */
 531         if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
 532              !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
 533             (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
 534                 if (dcrtc->csc_yuv_mode == CSC_AUTO)
 535                         val |= CFG_CSC_YUV_CCIR709;
 536         }
 537
 538         /*
 539          * We assume we're connected to a TV-like device, so the YUV->RGB
 540          * conversion should produce a limited range.  We should set this
 541          * depending on the connectors attached to this CRTC, and what
 542          * kind of device they report being connected.
 543          */
 544         if (dcrtc->csc_rgb_mode == CSC_AUTO)
 545                 val |= CFG_CSC_RGB_STUDIO;
 546
 547         return val;
 548 }
 549
 550 static void armada_drm_primary_set(struct drm_crtc *crtc,
 551         struct drm_plane *plane, int x, int y)
 552 {
 553         struct armada_plane_state *state = &drm_to_armada_plane(plane)->state;
 554         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 555         struct armada_regs regs[8];
 556         bool interlaced = dcrtc->interlaced;
 557         unsigned i;
 558         u32 ctrl0;
 559
 560         i = armada_drm_crtc_calc_fb(plane->fb, x, y, regs, interlaced);
 561
 562         armada_reg_queue_set(regs, i, state->dst_yx, LCD_SPU_GRA_OVSA_HPXL_VLN);
 563         armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN);
 564         armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN);
 565
 566         ctrl0 = state->ctrl0;
 567         if (interlaced)
 568                 ctrl0 |= CFG_GRA_FTOGGLE;
 569
 570         armada_reg_queue_mod(regs, i, ctrl0, CFG_GRAFORMAT |
 571                              CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
 572                                          CFG_SWAPYU | CFG_YUV2RGB) |
 573                              CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
 574                              LCD_SPU_DMA_CTRL0);
 575         armada_reg_queue_end(regs, i);
 576         armada_drm_crtc_update_regs(dcrtc, regs);
 577 }
 578
 579 /* The mode_config.mutex will be held for this call */
 580 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
 581         struct drm_display_mode *mode, struct drm_display_mode *adj,
 582         int x, int y, struct drm_framebuffer *old_fb)
 583 {
 584         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 585         struct armada_regs regs[17];
 586         uint32_t lm, rm, tm, bm, val, sclk;
 587         unsigned long flags;
 588         unsigned i;
 589         bool interlaced;
 590
 591         drm_framebuffer_reference(crtc->primary->fb);
 592
 593         interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
 594
 595         val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
 596         val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
 597         val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
 598
 599         if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
 600                 val |= CFG_PALETTE_ENA;
 601
 602         drm_to_armada_plane(crtc->primary)->state.ctrl0 = val;
 603         drm_to_armada_plane(crtc->primary)->state.src_hw =
 604         drm_to_armada_plane(crtc->primary)->state.dst_hw =
 605                 adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
 606         drm_to_armada_plane(crtc->primary)->state.dst_yx = 0;
 607
 608         i = 0;
 609         rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
 610         lm = adj->crtc_htotal - adj->crtc_hsync_end;
 611         bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
 612         tm = adj->crtc_vtotal - adj->crtc_vsync_end;
 613
 614         DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
 615                 adj->crtc_hdisplay,
 616                 adj->crtc_hsync_start,
 617                 adj->crtc_hsync_end,
 618                 adj->crtc_htotal, lm, rm);
 619         DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
 620                 adj->crtc_vdisplay,
 621                 adj->crtc_vsync_start,
 622                 adj->crtc_vsync_end,
 623                 adj->crtc_vtotal, tm, bm);
 624
 625         /* Wait for pending flips to complete */
 626         armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
 627                                    MAX_SCHEDULE_TIMEOUT);
 628
 629         drm_crtc_vblank_off(crtc);
 630
 631         val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
 632         if (val != dcrtc->dumb_ctrl) {
 633                 dcrtc->dumb_ctrl = val;
 634                 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
 635         }
 636
 637         /*
 638          * If we are blanked, we would have disabled the clock.  Re-enable
 639          * it so that compute_clock() does the right thing.
 640          */
 641         if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms))
 642                 WARN_ON(clk_prepare_enable(dcrtc->clk));
 643
 644         /* Now compute the divider for real */
 645         dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
 646
 647         /* Ensure graphic fifo is enabled */
 648         armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
 649         armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
 650
 651         if (interlaced ^ dcrtc->interlaced) {
 652                 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
 653                         drm_crtc_vblank_get(&dcrtc->crtc);
 654                 else
 655                         drm_crtc_vblank_put(&dcrtc->crtc);
 656                 dcrtc->interlaced = interlaced;
 657         }
 658
 659         spin_lock_irqsave(&dcrtc->irq_lock, flags);
 660
 661         /* Even interlaced/progressive frame */
 662         dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
 663                                     adj->crtc_htotal;
 664         dcrtc->v[1].spu_v_porch = tm << 16 | bm;
 665         val = adj->crtc_hsync_start;
 666         dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 667                 dcrtc->variant->spu_adv_reg;
 668
 669         if (interlaced) {
 670                 /* Odd interlaced frame */
 671                 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
 672                                                 (1 << 16);
 673                 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
 674                 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
 675                 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
 676                         dcrtc->variant->spu_adv_reg;
 677         } else {
 678                 dcrtc->v[0] = dcrtc->v[1];
 679         }
 680
 681         val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
 682
 683         armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
 684         armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
 685         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
 686         armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
 687                            LCD_SPUT_V_H_TOTAL);
 688
 689         if (dcrtc->variant->has_spu_adv_reg) {
 690                 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
 691                                      ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
 692                                      ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
 693         }
 694
 695         val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
 696         armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
 697
 698         val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
 699         armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
 700         armada_reg_queue_end(regs, i);
 701
 702         armada_drm_crtc_update_regs(dcrtc, regs);
 703
 704         armada_drm_primary_set(crtc, crtc->primary, x, y);
 705         spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
 706
 707         armada_drm_crtc_update(dcrtc);
 708
 709         drm_crtc_vblank_on(crtc);
 710         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 711
 712         return 0;
 713 }
 714
 715 /* The mode_config.mutex will be held for this call */
 716 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 717         struct drm_framebuffer *old_fb)
 718 {
 719         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 720         struct armada_regs regs[4];
 721         unsigned i;
 722
 723         i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
 724                                     dcrtc->interlaced);
 725         armada_reg_queue_end(regs, i);
 726
 727         /* Wait for pending flips to complete */
 728         armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
 729                                    MAX_SCHEDULE_TIMEOUT);
 730
 731         /* Take a reference to the new fb as we're using it */
 732         drm_framebuffer_reference(crtc->primary->fb);
 733
 734         /* Update the base in the CRTC */
 735         armada_drm_crtc_update_regs(dcrtc, regs);
 736
 737         /* Drop our previously held reference */
 738         armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
 739
 740         return 0;
 741 }
 742
 743 void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc,
 744         struct drm_plane *plane)
 745 {
 746         u32 sram_para1, dma_ctrl0_mask;
 747
 748         /*
 749          * Drop our reference on any framebuffer attached to this plane.
 750          * We don't need to NULL this out as drm_plane_force_disable(),
 751          * and __setplane_internal() will do so for an overlay plane, and
 752          * __drm_helper_disable_unused_functions() will do so for the
 753          * primary plane.
 754          */
 755         if (plane->fb)
 756                 drm_framebuffer_unreference(plane->fb);
 757
 758         /* Power down the Y/U/V FIFOs */
 759         sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
 760
 761         /* Power down most RAMs and FIFOs if this is the primary plane */
 762         if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 763                 sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
 764                               CFG_PDWN32x32 | CFG_PDWN64x66;
 765                 dma_ctrl0_mask = CFG_GRA_ENA;
 766         } else {
 767                 dma_ctrl0_mask = CFG_DMA_ENA;
 768         }
 769
 770         spin_lock_irq(&dcrtc->irq_lock);
 771         armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0);
 772         spin_unlock_irq(&dcrtc->irq_lock);
 773
 774         armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1);
 775 }
 776
 777 /* The mode_config.mutex will be held for this call */
 778 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
 779 {
 780         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 781
 782         armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 783         armada_drm_crtc_plane_disable(dcrtc, crtc->primary);
 784 }
 785
 786 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
 787         .dpms           = armada_drm_crtc_dpms,
 788         .prepare        = armada_drm_crtc_prepare,
 789         .commit         = armada_drm_crtc_commit,
 790         .mode_fixup     = armada_drm_crtc_mode_fixup,
 791         .mode_set       = armada_drm_crtc_mode_set,
 792         .mode_set_base  = armada_drm_crtc_mode_set_base,
 793         .disable        = armada_drm_crtc_disable,
 794 };
 795
 796 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
 797         unsigned stride, unsigned width, unsigned height)
 798 {
 799         uint32_t addr;
 800         unsigned y;
 801
 802         addr = SRAM_HWC32_RAM1;
 803         for (y = 0; y < height; y++) {
 804                 uint32_t *p = &pix[y * stride];
 805                 unsigned x;
 806
 807                 for (x = 0; x < width; x++, p++) {
 808                         uint32_t val = *p;
 809
 810                         val = (val & 0xff00ff00) |
 811                               (val & 0x000000ff) << 16 |
 812                               (val & 0x00ff0000) >> 16;
 813
 814                         writel_relaxed(val,
 815                                        base + LCD_SPU_SRAM_WRDAT);
 816                         writel_relaxed(addr | SRAM_WRITE,
 817                                        base + LCD_SPU_SRAM_CTRL);
 818                         readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
 819                         addr += 1;
 820                         if ((addr & 0x00ff) == 0)
 821                                 addr += 0xf00;
 822                         if ((addr & 0x30ff) == 0)
 823                                 addr = SRAM_HWC32_RAM2;
 824                 }
 825         }
 826 }
 827
 828 static void armada_drm_crtc_cursor_tran(void __iomem *base)
 829 {
 830         unsigned addr;
 831
 832         for (addr = 0; addr < 256; addr++) {
 833                 /* write the default value */
 834                 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
 835                 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
 836                                base + LCD_SPU_SRAM_CTRL);
 837         }
 838 }
 839
 840 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
 841 {
 842         uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
 843         uint32_t yoff, yscr, h = dcrtc->cursor_h;
 844         uint32_t para1;
 845
 846         /*
 847          * Calculate the visible width and height of the cursor,
 848          * screen position, and the position in the cursor bitmap.
 849          */
 850         if (dcrtc->cursor_x < 0) {
 851                 xoff = -dcrtc->cursor_x;
 852                 xscr = 0;
 853                 w -= min(xoff, w);
 854         } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
 855                 xoff = 0;
 856                 xscr = dcrtc->cursor_x;
 857                 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
 858         } else {
 859                 xoff = 0;
 860                 xscr = dcrtc->cursor_x;
 861         }
 862
 863         if (dcrtc->cursor_y < 0) {
 864                 yoff = -dcrtc->cursor_y;
 865                 yscr = 0;
 866                 h -= min(yoff, h);
 867         } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
 868                 yoff = 0;
 869                 yscr = dcrtc->cursor_y;
 870                 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
 871         } else {
 872                 yoff = 0;
 873                 yscr = dcrtc->cursor_y;
 874         }
 875
 876         /* On interlaced modes, the vertical cursor size must be halved */
 877         s = dcrtc->cursor_w;
 878         if (dcrtc->interlaced) {
 879                 s *= 2;
 880                 yscr /= 2;
 881                 h /= 2;
 882         }
 883
 884         if (!dcrtc->cursor_obj || !h || !w) {
 885                 spin_lock_irq(&dcrtc->irq_lock);
 886                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 887                 dcrtc->cursor_update = false;
 888                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 889                 spin_unlock_irq(&dcrtc->irq_lock);
 890                 return 0;
 891         }
 892
 893         para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
 894         armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
 895                        dcrtc->base + LCD_SPU_SRAM_PARA1);
 896
 897         /*
 898          * Initialize the transparency if the SRAM was powered down.
 899          * We must also reload the cursor data as well.
 900          */
 901         if (!(para1 & CFG_CSB_256x32)) {
 902                 armada_drm_crtc_cursor_tran(dcrtc->base);
 903                 reload = true;
 904         }
 905
 906         if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
 907                 spin_lock_irq(&dcrtc->irq_lock);
 908                 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 909                 dcrtc->cursor_update = false;
 910                 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
 911                 spin_unlock_irq(&dcrtc->irq_lock);
 912                 reload = true;
 913         }
 914         if (reload) {
 915                 struct armada_gem_object *obj = dcrtc->cursor_obj;
 916                 uint32_t *pix;
 917                 /* Set the top-left corner of the cursor image */
 918                 pix = obj->addr;
 919                 pix += yoff * s + xoff;
 920                 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
 921         }
 922
 923         /* Reload the cursor position, size and enable in the IRQ handler */
 924         spin_lock_irq(&dcrtc->irq_lock);
 925         dcrtc->cursor_hw_pos = yscr << 16 | xscr;
 926         dcrtc->cursor_hw_sz = h << 16 | w;
 927         dcrtc->cursor_update = true;
 928         armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
 929         spin_unlock_irq(&dcrtc->irq_lock);
 930
 931         return 0;
 932 }
 933
 934 static void cursor_update(void *data)
 935 {
 936         armada_drm_crtc_cursor_update(data, true);
 937 }
 938
 939 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
 940         struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
 941 {
 942         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 943         struct armada_gem_object *obj = NULL;
 944         int ret;
 945
 946         /* If no cursor support, replicate drm's return value */
 947         if (!dcrtc->variant->has_spu_adv_reg)
 948                 return -ENXIO;
 949
 950         if (handle && w > 0 && h > 0) {
 951                 /* maximum size is 64x32 or 32x64 */
 952                 if (w > 64 || h > 64 || (w > 32 && h > 32))
 953                         return -ENOMEM;
 954
 955                 obj = armada_gem_object_lookup(file, handle);
 956                 if (!obj)
 957                         return -ENOENT;
 958
 959                 /* Must be a kernel-mapped object */
 960                 if (!obj->addr) {
 961                         drm_gem_object_unreference_unlocked(&obj->obj);
 962                         return -EINVAL;
 963                 }
 964
 965                 if (obj->obj.size < w * h * 4) {
 966                         DRM_ERROR("buffer is too small\n");
 967                         drm_gem_object_unreference_unlocked(&obj->obj);
 968                         return -ENOMEM;
 969                 }
 970         }
 971
 972         if (dcrtc->cursor_obj) {
 973                 dcrtc->cursor_obj->update = NULL;
 974                 dcrtc->cursor_obj->update_data = NULL;
 975                 drm_gem_object_unreference_unlocked(&dcrtc->cursor_obj->obj);
 976         }
 977         dcrtc->cursor_obj = obj;
 978         dcrtc->cursor_w = w;
 979         dcrtc->cursor_h = h;
 980         ret = armada_drm_crtc_cursor_update(dcrtc, true);
 981         if (obj) {
 982                 obj->update_data = dcrtc;
 983                 obj->update = cursor_update;
 984         }
 985
 986         return ret;
 987 }
 988
 989 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 990 {
 991         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
 992         int ret;
 993
 994         /* If no cursor support, replicate drm's return value */
 995         if (!dcrtc->variant->has_spu_adv_reg)
 996                 return -EFAULT;
 997
 998         dcrtc->cursor_x = x;
 999         dcrtc->cursor_y = y;
1000         ret = armada_drm_crtc_cursor_update(dcrtc, false);
1001
1002         return ret;
1003 }
1004
1005 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
1006 {
1007         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1008         struct armada_private *priv = crtc->dev->dev_private;
1009
1010         if (dcrtc->cursor_obj)
1011                 drm_gem_object_unreference_unlocked(&dcrtc->cursor_obj->obj);
1012
1013         priv->dcrtc[dcrtc->num] = NULL;
1014         drm_crtc_cleanup(&dcrtc->crtc);
1015
1016         if (!IS_ERR(dcrtc->clk))
1017                 clk_disable_unprepare(dcrtc->clk);
1018
1019         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
1020
1021         of_node_put(dcrtc->crtc.port);
1022
1023         kfree(dcrtc);
1024 }
1025
1026 /*
1027  * The mode_config lock is held here, to prevent races between this
1028  * and a mode_set.
1029  */
1030 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
1031         struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
1032 {
1033         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1034         struct armada_frame_work *work;
1035         unsigned i;
1036         int ret;
1037
1038         /* We don't support changing the pixel format */
1039         if (fb->pixel_format != crtc->primary->fb->pixel_format)
1040                 return -EINVAL;
1041
1042         work = kmalloc(sizeof(*work), GFP_KERNEL);
1043         if (!work)
1044                 return -ENOMEM;
1045
1046         work->work.fn = armada_drm_crtc_complete_frame_work;
1047         work->event = event;
1048         work->old_fb = dcrtc->crtc.primary->fb;
1049
1050         i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
1051                                     dcrtc->interlaced);
1052         armada_reg_queue_end(work->regs, i);
1053
1054         /*
1055          * Ensure that we hold a reference on the new framebuffer.
1056          * This has to match the behaviour in mode_set.
1057          */
1058         drm_framebuffer_reference(fb);
1059
1060         ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
1061         if (ret) {
1062                 /* Undo our reference above */
1063                 drm_framebuffer_unreference(fb);
1064                 kfree(work);
1065                 return ret;
1066         }
1067
1068         /*
1069          * Don't take a reference on the new framebuffer;
1070          * drm_mode_page_flip_ioctl() has already grabbed a reference and
1071          * will _not_ drop that reference on successful return from this
1072          * function.  Simply mark this new framebuffer as the current one.
1073          */
1074         dcrtc->crtc.primary->fb = fb;
1075
1076         /*
1077          * Finally, if the display is blanked, we won't receive an
1078          * interrupt, so complete it now.
1079          */
1080         if (dpms_blanked(dcrtc->dpms))
1081                 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
1082
1083         return 0;
1084 }
1085
1086 static int
1087 armada_drm_crtc_set_property(struct drm_crtc *crtc,
1088         struct drm_property *property, uint64_t val)
1089 {
1090         struct armada_private *priv = crtc->dev->dev_private;
1091         struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1092         bool update_csc = false;
1093
1094         if (property == priv->csc_yuv_prop) {
1095                 dcrtc->csc_yuv_mode = val;
1096                 update_csc = true;
1097         } else if (property == priv->csc_rgb_prop) {
1098                 dcrtc->csc_rgb_mode = val;
1099                 update_csc = true;
1100         }
1101
1102         if (update_csc) {
1103                 uint32_t val;
1104
1105                 val = dcrtc->spu_iopad_ctrl |
1106                       armada_drm_crtc_calculate_csc(dcrtc);
1107                 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1108         }
1109
1110         return 0;
1111 }
1112
1113 static const struct drm_crtc_funcs armada_crtc_funcs = {
1114         .cursor_set     = armada_drm_crtc_cursor_set,
1115         .cursor_move    = armada_drm_crtc_cursor_move,
1116         .destroy        = armada_drm_crtc_destroy,
1117         .set_config     = drm_crtc_helper_set_config,
1118         .page_flip      = armada_drm_crtc_page_flip,
1119         .set_property   = armada_drm_crtc_set_property,
1120 };
1121
1122 static const struct drm_plane_funcs armada_primary_plane_funcs = {
1123         .update_plane   = drm_primary_helper_update,
1124         .disable_plane  = drm_primary_helper_disable,
1125         .destroy        = drm_primary_helper_destroy,
1126 };
1127
1128 int armada_drm_plane_init(struct armada_plane *plane)
1129 {
1130         init_waitqueue_head(&plane->frame_wait);
1131
1132         return 0;
1133 }
1134
1135 static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1136         { CSC_AUTO,        "Auto" },
1137         { CSC_YUV_CCIR601, "CCIR601" },
1138         { CSC_YUV_CCIR709, "CCIR709" },
1139 };
1140
1141 static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1142         { CSC_AUTO,         "Auto" },
1143         { CSC_RGB_COMPUTER, "Computer system" },
1144         { CSC_RGB_STUDIO,   "Studio" },
1145 };
1146
1147 static int armada_drm_crtc_create_properties(struct drm_device *dev)
1148 {
1149         struct armada_private *priv = dev->dev_private;
1150
1151         if (priv->csc_yuv_prop)
1152                 return 0;
1153
1154         priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1155                                 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1156                                 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1157         priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1158                                 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1159                                 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1160
1161         if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1162                 return -ENOMEM;
1163
1164         return 0;
1165 }
1166
1167 static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1168         struct resource *res, int irq, const struct armada_variant *variant,
1169         struct device_node *port)
1170 {
1171         struct armada_private *priv = drm->dev_private;
1172         struct armada_crtc *dcrtc;
1173         struct armada_plane *primary;
1174         void __iomem *base;
1175         int ret;
1176
1177         ret = armada_drm_crtc_create_properties(drm);
1178         if (ret)
1179                 return ret;
1180
1181         base = devm_ioremap_resource(dev, res);
1182         if (IS_ERR(base))
1183                 return PTR_ERR(base);
1184
1185         dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1186         if (!dcrtc) {
1187                 DRM_ERROR("failed to allocate Armada crtc\n");
1188                 return -ENOMEM;
1189         }
1190
1191         if (dev != drm->dev)
1192                 dev_set_drvdata(dev, dcrtc);
1193
1194         dcrtc->variant = variant;
1195         dcrtc->base = base;
1196         dcrtc->num = drm->mode_config.num_crtc;
1197         dcrtc->clk = ERR_PTR(-EINVAL);
1198         dcrtc->csc_yuv_mode = CSC_AUTO;
1199         dcrtc->csc_rgb_mode = CSC_AUTO;
1200         dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1201         dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1202         spin_lock_init(&dcrtc->irq_lock);
1203         dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1204
1205         /* Initialize some registers which we don't otherwise set */
1206         writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1207         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1208         writel_relaxed(dcrtc->spu_iopad_ctrl,
1209                        dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1210         writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1211         writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1212                        CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1213                        CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1214         writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1215         writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1216         writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1217
1218         ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1219                                dcrtc);
1220         if (ret < 0) {
1221                 kfree(dcrtc);
1222                 return ret;
1223         }
1224
1225         if (dcrtc->variant->init) {
1226                 ret = dcrtc->variant->init(dcrtc, dev);
1227                 if (ret) {
1228                         kfree(dcrtc);
1229                         return ret;
1230                 }
1231         }
1232
1233         /* Ensure AXI pipeline is enabled */
1234         armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1235
1236         priv->dcrtc[dcrtc->num] = dcrtc;
1237
1238         dcrtc->crtc.port = port;
1239
1240         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
1241         if (!primary)
1242                 return -ENOMEM;
1243
1244         ret = armada_drm_plane_init(primary);
1245         if (ret) {
1246                 kfree(primary);
1247                 return ret;
1248         }
1249
1250         ret = drm_universal_plane_init(drm, &primary->base, 0,
1251                                        &armada_primary_plane_funcs,
1252                                        armada_primary_formats,
1253                                        ARRAY_SIZE(armada_primary_formats),
1254                                        DRM_PLANE_TYPE_PRIMARY, NULL);
1255         if (ret) {
1256                 kfree(primary);
1257                 return ret;
1258         }
1259
1260         ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL,
1261                                         &armada_crtc_funcs, NULL);
1262         if (ret)
1263                 goto err_crtc_init;
1264
1265         drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1266
1267         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1268                                    dcrtc->csc_yuv_mode);
1269         drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1270                                    dcrtc->csc_rgb_mode);
1271
1272         return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1273
1274 err_crtc_init:
1275         primary->base.funcs->destroy(&primary->base);
1276         return ret;
1277 }
1278
1279 static int
1280 armada_lcd_bind(struct device *dev, struct device *master, void *data)
1281 {
1282         struct platform_device *pdev = to_platform_device(dev);
1283         struct drm_device *drm = data;
1284         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1285         int irq = platform_get_irq(pdev, 0);
1286         const struct armada_variant *variant;
1287         struct device_node *port = NULL;
1288
1289         if (irq < 0)
1290                 return irq;
1291
1292         if (!dev->of_node) {
1293                 const struct platform_device_id *id;
1294
1295                 id = platform_get_device_id(pdev);
1296                 if (!id)
1297                         return -ENXIO;
1298
1299                 variant = (const struct armada_variant *)id->driver_data;
1300         } else {
1301                 const struct of_device_id *match;
1302                 struct device_node *np, *parent = dev->of_node;
1303
1304                 match = of_match_device(dev->driver->of_match_table, dev);
1305                 if (!match)
1306                         return -ENXIO;
1307
1308                 np = of_get_child_by_name(parent, "ports");
1309                 if (np)
1310                         parent = np;
1311                 port = of_get_child_by_name(parent, "port");
1312                 of_node_put(np);
1313                 if (!port) {
1314                         dev_err(dev, "no port node found in %s\n",
1315                                 parent->full_name);
1316                         return -ENXIO;
1317                 }
1318
1319                 variant = match->data;
1320         }
1321
1322         return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1323 }
1324
1325 static void
1326 armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1327 {
1328         struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1329
1330         armada_drm_crtc_destroy(&dcrtc->crtc);
1331 }
1332
1333 static const struct component_ops armada_lcd_ops = {
1334         .bind = armada_lcd_bind,
1335         .unbind = armada_lcd_unbind,
1336 };
1337
1338 static int armada_lcd_probe(struct platform_device *pdev)
1339 {
1340         return component_add(&pdev->dev, &armada_lcd_ops);
1341 }
1342
1343 static int armada_lcd_remove(struct platform_device *pdev)
1344 {
1345         component_del(&pdev->dev, &armada_lcd_ops);
1346         return 0;
1347 }
1348
1349 static struct of_device_id armada_lcd_of_match[] = {
1350         {
1351                 .compatible     = "marvell,dove-lcd",
1352                 .data           = &armada510_ops,
1353         },
1354         {}
1355 };
1356 MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1357
1358 static const struct platform_device_id armada_lcd_platform_ids[] = {
1359         {
1360                 .name           = "armada-lcd",
1361                 .driver_data    = (unsigned long)&armada510_ops,
1362         }, {
1363                 .name           = "armada-510-lcd",
1364                 .driver_data    = (unsigned long)&armada510_ops,
1365         },
1366         { },
1367 };
1368 MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1369
1370 struct platform_driver armada_lcd_platform_driver = {
1371         .probe  = armada_lcd_probe,
1372         .remove = armada_lcd_remove,
1373         .driver = {
1374                 .name   = "armada-lcd",
1375                 .owner  =  THIS_MODULE,
1376                 .of_match_table = armada_lcd_of_match,
1377         },
1378         .id_table = armada_lcd_platform_ids,
1379 };