drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "pp_debug.h"
  25 #include "smumgr.h"
  26 #include "smu74.h"
  27 #include "smu_ucode_xfer_vi.h"
  28 #include "polaris10_smumgr.h"
  29 #include "smu74_discrete.h"
  30 #include "smu/smu_7_1_3_d.h"
  31 #include "smu/smu_7_1_3_sh_mask.h"
  32 #include "gmc/gmc_8_1_d.h"
  33 #include "gmc/gmc_8_1_sh_mask.h"
  34 #include "oss/oss_3_0_d.h"
  35 #include "gca/gfx_8_0_d.h"
  36 #include "bif/bif_5_0_d.h"
  37 #include "bif/bif_5_0_sh_mask.h"
  38 #include "ppatomctrl.h"
  39 #include "cgs_common.h"
  40 #include "smu7_ppsmc.h"
  41 #include "smu7_smumgr.h"
  42
  43 #include "smu7_dyn_defaults.h"
  44
  45 #include "smu7_hwmgr.h"
  46 #include "hardwaremanager.h"
  47 #include "ppatomctrl.h"
  48 #include "atombios.h"
  49 #include "pppcielanes.h"
  50
  51 #include "dce/dce_10_0_d.h"
  52 #include "dce/dce_10_0_sh_mask.h"
  53
  54 #define POLARIS10_SMC_SIZE 0x20000
  55 #define VOLTAGE_VID_OFFSET_SCALE1   625
  56 #define VOLTAGE_VID_OFFSET_SCALE2   100
  57 #define POWERTUNE_DEFAULT_SET_MAX    1
  58 #define VDDC_VDDCI_DELTA            200
  59 #define MC_CG_ARB_FREQ_F1           0x0b
  60
  61 static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
  62         /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
  63          * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
  64         { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
  65         { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
  66         { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
  67 };
  68
  69 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
  70                         {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
  71                         {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
  72                         {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
  73                         {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
  74                         {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
  75                         {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
  76                         {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
  77                         {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
  78
  79 #define PPPOLARIS10_TARGETACTIVITY_DFLT                     50
  80
  81 static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
  82         /*  Min      pcie   DeepSleep Activity  CgSpll      CgSpll    CcPwr  CcPwr  Sclk         Enabled      Enabled                       Voltage    Power */
  83         /* Voltage, DpmLevel, DivId,  Level,  FuncCntl3,  FuncCntl4,  DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
  84         { 0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000, 0x3000, 0, 0x2600, 0, 0, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
  85         { 0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000, 0x2000, 0, 0x1e00, 1, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
  86         { 0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000, 0x2800, 0, 0x2000, 1, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } },
  87         { 0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000, 0x3000, 0, 0x2600, 1, 1, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
  88         { 0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100, 0x3800, 0, 0x2c00, 1, 1, 0x0004, 0x1203, 0xffff, 0x3600, 0xc9e2, 0x2e00 } },
  89         { 0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100, 0x2000, 0, 0x1e00, 2, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
  90         { 0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100, 0x2400, 0, 0x1e00, 2, 1, 0x0004, 0x8901, 0xffff, 0x2300, 0x314c, 0x1d00 } },
  91         { 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }
  92 };
  93
  94 static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
  95         0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
  96
  97 static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
  98 {
  99         int result = 0;
 100         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
 101
 102         if (0 != smu_data->avfs.avfs_btc_param) {
 103                 if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) {
 104                         pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
 105                         result = -1;
 106                 }
 107         }
 108         if (smu_data->avfs.avfs_btc_param > 1) {
 109                 /* Soft-Reset to reset the engine before loading uCode */
 110                 /* halt */
 111                 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
 112                 /* reset everything */
 113                 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
 114                 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
 115         }
 116         return result;
 117 }
 118
 119
 120 static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
 121 {
 122         uint32_t vr_config;
 123         uint32_t dpm_table_start;
 124
 125         uint16_t u16_boot_mvdd;
 126         uint32_t graphics_level_address, vr_config_address, graphics_level_size;
 127
 128         graphics_level_size = sizeof(avfs_graphics_level_polaris10);
 129         u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
 130
 131         PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
 132                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
 133                                 &dpm_table_start, 0x40000),
 134                         "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
 135                         return -1);
 136
 137         /*  Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
 138         vr_config = 0x01000500; /* Real value:0x50001 */
 139
 140         vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
 141
 142         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
 143                                 (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
 144                         "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
 145                         return -1);
 146
 147         graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
 148
 149         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
 150                                 (uint8_t *)(&avfs_graphics_level_polaris10),
 151                                 graphics_level_size, 0x40000),
 152                         "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
 153                         return -1);
 154
 155         graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
 156
 157         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
 158                                 (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
 159                                 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
 160                         return -1);
 161
 162         /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
 163
 164         graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
 165
 166         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
 167                         (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
 168                         "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
 169                         return -1);
 170
 171         return 0;
 172 }
 173
 174
 175 static int
 176 polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr, bool SMU_VFT_INTACT)
 177 {
 178         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
 179
 180         switch (smu_data->avfs.avfs_btc_status) {
 181         case AVFS_BTC_COMPLETED_PREVIOUSLY:
 182                 break;
 183
 184         case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */
 185
 186                 smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED;
 187                 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
 188                         "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
 189                         return -EINVAL);
 190
 191                 if (smu_data->avfs.avfs_btc_param > 1) {
 192                         pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
 193                         smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL;
 194                         PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
 195                         "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
 196                         return -EINVAL);
 197                 }
 198
 199                 smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED;
 200                 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
 201                                         "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
 202                                  return -EINVAL);
 203                 smu_data->avfs.avfs_btc_status = AVFS_BTC_ENABLEAVFS;
 204                 break;
 205
 206         case AVFS_BTC_DISABLED:
 207         case AVFS_BTC_ENABLEAVFS:
 208         case AVFS_BTC_NOTSUPPORTED:
 209                 break;
 210
 211         default:
 212                 pr_err("AVFS failed status is %x!\n", smu_data->avfs.avfs_btc_status);
 213                 break;
 214         }
 215
 216         return 0;
 217 }
 218
 219 static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
 220 {
 221         int result = 0;
 222
 223         /* Wait for smc boot up */
 224         /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
 225
 226         /* Assert reset */
 227         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 228                                         SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 229
 230         result = smu7_upload_smu_firmware_image(hwmgr);
 231         if (result != 0)
 232                 return result;
 233
 234         /* Clear status */
 235         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
 236
 237         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 238                                         SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 239
 240         /* De-assert reset */
 241         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 242                                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 243
 244
 245         PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
 246
 247
 248         /* Call Test SMU message with 0x20000 offset to trigger SMU start */
 249         smu7_send_msg_to_smc_offset(hwmgr);
 250
 251         /* Wait done bit to be set */
 252         /* Check pass/failed indicator */
 253
 254         PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
 255
 256         if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 257                                                 SMU_STATUS, SMU_PASS))
 258                 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
 259
 260         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
 261
 262         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 263                                         SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 264
 265         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 266                                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 267
 268         /* Wait for firmware to initialize */
 269         PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 270
 271         return result;
 272 }
 273
 274 static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
 275 {
 276         int result = 0;
 277
 278         /* wait for smc boot up */
 279         PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
 280
 281         /* Clear firmware interrupt enable flag */
 282         /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
 283         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 284                                 ixFIRMWARE_FLAGS, 0);
 285
 286         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 287                                         SMC_SYSCON_RESET_CNTL,
 288                                         rst_reg, 1);
 289
 290         result = smu7_upload_smu_firmware_image(hwmgr);
 291         if (result != 0)
 292                 return result;
 293
 294         /* Set smc instruct start point at 0x0 */
 295         smu7_program_jump_on_start(hwmgr);
 296
 297         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 298                                         SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 299
 300         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 301                                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 302
 303         /* Wait for firmware to initialize */
 304
 305         PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
 306                                         FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 307
 308         return result;
 309 }
 310
 311 static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
 312 {
 313         int result = 0;
 314         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 315         bool SMU_VFT_INTACT;
 316
 317         /* Only start SMC if SMC RAM is not running */
 318         if (!smu7_is_smc_ram_running(hwmgr)) {
 319                 SMU_VFT_INTACT = false;
 320                 smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
 321                 smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
 322
 323                 /* Check if SMU is running in protected mode */
 324                 if (smu_data->protected_mode == 0) {
 325                         result = polaris10_start_smu_in_non_protection_mode(hwmgr);
 326                 } else {
 327                         result = polaris10_start_smu_in_protection_mode(hwmgr);
 328
 329                         /* If failed, try with different security Key. */
 330                         if (result != 0) {
 331                                 smu_data->smu7_data.security_hard_key ^= 1;
 332                                 cgs_rel_firmware(hwmgr->device, CGS_UCODE_ID_SMU);
 333                                 result = polaris10_start_smu_in_protection_mode(hwmgr);
 334                         }
 335                 }
 336
 337                 if (result != 0)
 338                         PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
 339
 340                 polaris10_avfs_event_mgr(hwmgr, true);
 341         } else
 342                 SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */
 343
 344         polaris10_avfs_event_mgr(hwmgr, SMU_VFT_INTACT);
 345         /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
 346         smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
 347                                         &(smu_data->smu7_data.soft_regs_start), 0x40000);
 348
 349         result = smu7_request_smu_load_fw(hwmgr);
 350
 351         return result;
 352 }
 353
 354 static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
 355 {
 356         uint32_t efuse;
 357
 358         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
 359         efuse &= 0x00000001;
 360         if (efuse)
 361                 return true;
 362
 363         return false;
 364 }
 365
 366 static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
 367 {
 368         struct polaris10_smumgr *smu_data;
 369         int i;
 370
 371         smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
 372         if (smu_data == NULL)
 373                 return -ENOMEM;
 374
 375         hwmgr->smu_backend = smu_data;
 376
 377         if (smu7_init(hwmgr))
 378                 return -EINVAL;
 379
 380         for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++)
 381                 smu_data->activity_target[i] = PPPOLARIS10_TARGETACTIVITY_DFLT;
 382
 383         return 0;
 384 }
 385
 386 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
 387                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
 388                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
 389 {
 390         uint32_t i;
 391         uint16_t vddci;
 392         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 393
 394         *voltage = *mvdd = 0;
 395
 396         /* clock - voltage dependency table is empty table */
 397         if (dep_table->count == 0)
 398                 return -EINVAL;
 399
 400         for (i = 0; i < dep_table->count; i++) {
 401                 /* find first sclk bigger than request */
 402                 if (dep_table->entries[i].clk >= clock) {
 403                         *voltage |= (dep_table->entries[i].vddc *
 404                                         VOLTAGE_SCALE) << VDDC_SHIFT;
 405                         if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
 406                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
 407                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 408                         else if (dep_table->entries[i].vddci)
 409                                 *voltage |= (dep_table->entries[i].vddci *
 410                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 411                         else {
 412                                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
 413                                                 (dep_table->entries[i].vddc -
 414                                                                 (uint16_t)VDDC_VDDCI_DELTA));
 415                                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
 416                         }
 417
 418                         if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
 419                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
 420                                         VOLTAGE_SCALE;
 421                         else if (dep_table->entries[i].mvdd)
 422                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
 423                                         VOLTAGE_SCALE;
 424
 425                         *voltage |= 1 << PHASES_SHIFT;
 426                         return 0;
 427                 }
 428         }
 429
 430         /* sclk is bigger than max sclk in the dependence table */
 431         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
 432
 433         if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
 434                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
 435                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 436         else if (dep_table->entries[i-1].vddci) {
 437                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
 438                                 (dep_table->entries[i].vddc -
 439                                                 (uint16_t)VDDC_VDDCI_DELTA));
 440                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
 441         }
 442
 443         if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
 444                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
 445         else if (dep_table->entries[i].mvdd)
 446                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
 447
 448         return 0;
 449 }
 450
 451 static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
 452 {
 453         uint32_t tmp;
 454         tmp = raw_setting * 4096 / 100;
 455         return (uint16_t)tmp;
 456 }
 457
 458 static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
 459 {
 460         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 461
 462         const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
 463         SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
 464         struct phm_ppt_v1_information *table_info =
 465                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 466         struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
 467         struct pp_advance_fan_control_parameters *fan_table =
 468                         &hwmgr->thermal_controller.advanceFanControlParameters;
 469         int i, j, k;
 470         const uint16_t *pdef1;
 471         const uint16_t *pdef2;
 472
 473         table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
 474         table->TargetTdp  = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
 475
 476         PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
 477                                 "Target Operating Temp is out of Range!",
 478                                 );
 479
 480         table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
 481                         cac_dtp_table->usTargetOperatingTemp * 256);
 482         table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
 483                         cac_dtp_table->usTemperatureLimitHotspot * 256);
 484         table->FanGainEdge = PP_HOST_TO_SMC_US(
 485                         scale_fan_gain_settings(fan_table->usFanGainEdge));
 486         table->FanGainHotspot = PP_HOST_TO_SMC_US(
 487                         scale_fan_gain_settings(fan_table->usFanGainHotspot));
 488
 489         pdef1 = defaults->BAPMTI_R;
 490         pdef2 = defaults->BAPMTI_RC;
 491
 492         for (i = 0; i < SMU74_DTE_ITERATIONS; i++) {
 493                 for (j = 0; j < SMU74_DTE_SOURCES; j++) {
 494                         for (k = 0; k < SMU74_DTE_SINKS; k++) {
 495                                 table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
 496                                 table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
 497                                 pdef1++;
 498                                 pdef2++;
 499                         }
 500                 }
 501         }
 502
 503         return 0;
 504 }
 505
 506 static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
 507 {
 508         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 509         const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
 510
 511         smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
 512         smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
 513         smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
 514         smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
 515
 516         return 0;
 517 }
 518
 519 static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
 520 {
 521         uint16_t tdc_limit;
 522         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 523         struct phm_ppt_v1_information *table_info =
 524                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 525         const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
 526
 527         tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
 528         smu_data->power_tune_table.TDC_VDDC_PkgLimit =
 529                         CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
 530         smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
 531                         defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
 532         smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
 533
 534         return 0;
 535 }
 536
 537 static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
 538 {
 539         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 540         const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
 541         uint32_t temp;
 542
 543         if (smu7_read_smc_sram_dword(hwmgr,
 544                         fuse_table_offset +
 545                         offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
 546                         (uint32_t *)&temp, SMC_RAM_END))
 547                 PP_ASSERT_WITH_CODE(false,
 548                                 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
 549                                 return -EINVAL);
 550         else {
 551                 smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
 552                 smu_data->power_tune_table.LPMLTemperatureMin =
 553                                 (uint8_t)((temp >> 16) & 0xff);
 554                 smu_data->power_tune_table.LPMLTemperatureMax =
 555                                 (uint8_t)((temp >> 8) & 0xff);
 556                 smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
 557         }
 558         return 0;
 559 }
 560
 561 static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
 562 {
 563         int i;
 564         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 565
 566         /* Currently not used. Set all to zero. */
 567         for (i = 0; i < 16; i++)
 568                 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
 569
 570         return 0;
 571 }
 572
 573 static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
 574 {
 575         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 576
 577 /* TO DO move to hwmgr */
 578         if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
 579                 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
 580                 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
 581                         hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
 582
 583         smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
 584                                 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
 585         return 0;
 586 }
 587
 588 static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
 589 {
 590         int i;
 591         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 592
 593         /* Currently not used. Set all to zero. */
 594         for (i = 0; i < 16; i++)
 595                 smu_data->power_tune_table.GnbLPML[i] = 0;
 596
 597         return 0;
 598 }
 599
 600 static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
 601 {
 602         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 603         struct phm_ppt_v1_information *table_info =
 604                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 605         uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
 606         uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
 607         struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
 608
 609         hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
 610         lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
 611
 612         smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
 613                         CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
 614         smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
 615                         CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
 616
 617         return 0;
 618 }
 619
 620 static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
 621 {
 622         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 623         uint32_t pm_fuse_table_offset;
 624
 625         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 626                         PHM_PlatformCaps_PowerContainment)) {
 627                 if (smu7_read_smc_sram_dword(hwmgr,
 628                                 SMU7_FIRMWARE_HEADER_LOCATION +
 629                                 offsetof(SMU74_Firmware_Header, PmFuseTable),
 630                                 &pm_fuse_table_offset, SMC_RAM_END))
 631                         PP_ASSERT_WITH_CODE(false,
 632                                         "Attempt to get pm_fuse_table_offset Failed!",
 633                                         return -EINVAL);
 634
 635                 if (polaris10_populate_svi_load_line(hwmgr))
 636                         PP_ASSERT_WITH_CODE(false,
 637                                         "Attempt to populate SviLoadLine Failed!",
 638                                         return -EINVAL);
 639
 640                 if (polaris10_populate_tdc_limit(hwmgr))
 641                         PP_ASSERT_WITH_CODE(false,
 642                                         "Attempt to populate TDCLimit Failed!", return -EINVAL);
 643
 644                 if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
 645                         PP_ASSERT_WITH_CODE(false,
 646                                         "Attempt to populate TdcWaterfallCtl, "
 647                                         "LPMLTemperature Min and Max Failed!",
 648                                         return -EINVAL);
 649
 650                 if (0 != polaris10_populate_temperature_scaler(hwmgr))
 651                         PP_ASSERT_WITH_CODE(false,
 652                                         "Attempt to populate LPMLTemperatureScaler Failed!",
 653                                         return -EINVAL);
 654
 655                 if (polaris10_populate_fuzzy_fan(hwmgr))
 656                         PP_ASSERT_WITH_CODE(false,
 657                                         "Attempt to populate Fuzzy Fan Control parameters Failed!",
 658                                         return -EINVAL);
 659
 660                 if (polaris10_populate_gnb_lpml(hwmgr))
 661                         PP_ASSERT_WITH_CODE(false,
 662                                         "Attempt to populate GnbLPML Failed!",
 663                                         return -EINVAL);
 664
 665                 if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
 666                         PP_ASSERT_WITH_CODE(false,
 667                                         "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
 668                                         "Sidd Failed!", return -EINVAL);
 669
 670                 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
 671                                 (uint8_t *)&smu_data->power_tune_table,
 672                                 (sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END))
 673                         PP_ASSERT_WITH_CODE(false,
 674                                         "Attempt to download PmFuseTable Failed!",
 675                                         return -EINVAL);
 676         }
 677         return 0;
 678 }
 679
 680 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
 681                         SMU74_Discrete_DpmTable *table)
 682 {
 683         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 684         uint32_t count, level;
 685
 686         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 687                 count = data->mvdd_voltage_table.count;
 688                 if (count > SMU_MAX_SMIO_LEVELS)
 689                         count = SMU_MAX_SMIO_LEVELS;
 690                 for (level = 0; level < count; level++) {
 691                         table->SmioTable2.Pattern[level].Voltage =
 692                                 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
 693                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
 694                         table->SmioTable2.Pattern[level].Smio =
 695                                 (uint8_t) level;
 696                         table->Smio[level] |=
 697                                 data->mvdd_voltage_table.entries[level].smio_low;
 698                 }
 699                 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
 700
 701                 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
 702         }
 703
 704         return 0;
 705 }
 706
 707 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
 708                                         struct SMU74_Discrete_DpmTable *table)
 709 {
 710         uint32_t count, level;
 711         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 712
 713         count = data->vddci_voltage_table.count;
 714
 715         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 716                 if (count > SMU_MAX_SMIO_LEVELS)
 717                         count = SMU_MAX_SMIO_LEVELS;
 718                 for (level = 0; level < count; ++level) {
 719                         table->SmioTable1.Pattern[level].Voltage =
 720                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
 721                         table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
 722
 723                         table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
 724                 }
 725         }
 726
 727         table->SmioMask1 = data->vddci_voltage_table.mask_low;
 728
 729         return 0;
 730 }
 731
 732 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
 733                 struct SMU74_Discrete_DpmTable *table)
 734 {
 735         uint32_t count;
 736         uint8_t index;
 737         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 738         struct phm_ppt_v1_information *table_info =
 739                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 740         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
 741                         table_info->vddc_lookup_table;
 742         /* tables is already swapped, so in order to use the value from it,
 743          * we need to swap it back.
 744          * We are populating vddc CAC data to BapmVddc table
 745          * in split and merged mode
 746          */
 747         for (count = 0; count < lookup_table->count; count++) {
 748                 index = phm_get_voltage_index(lookup_table,
 749                                 data->vddc_voltage_table.entries[count].value);
 750                 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
 751                 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
 752                 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
 753         }
 754
 755         return 0;
 756 }
 757
 758 static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
 759                 struct SMU74_Discrete_DpmTable *table)
 760 {
 761         polaris10_populate_smc_vddci_table(hwmgr, table);
 762         polaris10_populate_smc_mvdd_table(hwmgr, table);
 763         polaris10_populate_cac_table(hwmgr, table);
 764
 765         return 0;
 766 }
 767
 768 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
 769                 struct SMU74_Discrete_Ulv *state)
 770 {
 771         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 772         struct phm_ppt_v1_information *table_info =
 773                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 774
 775         state->CcPwrDynRm = 0;
 776         state->CcPwrDynRm1 = 0;
 777
 778         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
 779         state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
 780                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
 781
 782         if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker)
 783                 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
 784         else
 785                 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
 786
 787         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
 788         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
 789         CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
 790
 791         return 0;
 792 }
 793
 794 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
 795                 struct SMU74_Discrete_DpmTable *table)
 796 {
 797         return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
 798 }
 799
 800 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
 801                 struct SMU74_Discrete_DpmTable *table)
 802 {
 803         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 804         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 805         struct smu7_dpm_table *dpm_table = &data->dpm_table;
 806         int i;
 807
 808         /* Index (dpm_table->pcie_speed_table.count)
 809          * is reserved for PCIE boot level. */
 810         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
 811                 table->LinkLevel[i].PcieGenSpeed  =
 812                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
 813                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
 814                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
 815                 table->LinkLevel[i].EnabledForActivity = 1;
 816                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
 817                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
 818                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
 819         }
 820
 821         smu_data->smc_state_table.LinkLevelCount =
 822                         (uint8_t)dpm_table->pcie_speed_table.count;
 823
 824 /* To Do move to hwmgr */
 825         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
 826                         phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
 827
 828         return 0;
 829 }
 830
 831
 832 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
 833                                    SMU74_Discrete_DpmTable  *table)
 834 {
 835         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 836         uint32_t i, ref_clk;
 837
 838         struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
 839
 840         ref_clk = smu7_get_xclk(hwmgr);
 841
 842         if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
 843                 for (i = 0; i < NUM_SCLK_RANGE; i++) {
 844                         table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
 845                         table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
 846                         table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
 847
 848                         table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
 849                         table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
 850
 851                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
 852                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
 853                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
 854                 }
 855                 return;
 856         }
 857
 858         for (i = 0; i < NUM_SCLK_RANGE; i++) {
 859                 smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
 860                 smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
 861
 862                 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
 863                 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
 864                 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
 865
 866                 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
 867                 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
 868
 869                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
 870                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
 871                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
 872         }
 873 }
 874
 875 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 876                 uint32_t clock, SMU_SclkSetting *sclk_setting)
 877 {
 878         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 879         const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
 880         struct pp_atomctrl_clock_dividers_ai dividers;
 881         uint32_t ref_clock;
 882         uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
 883         uint8_t i;
 884         int result;
 885         uint64_t temp;
 886
 887         sclk_setting->SclkFrequency = clock;
 888         /* get the engine clock dividers for this clock value */
 889         result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
 890         if (result == 0) {
 891                 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
 892                 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
 893                 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
 894                 sclk_setting->PllRange = dividers.ucSclkPllRange;
 895                 sclk_setting->Sclk_slew_rate = 0x400;
 896                 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
 897                 sclk_setting->Pcc_down_slew_rate = 0xffff;
 898                 sclk_setting->SSc_En = dividers.ucSscEnable;
 899                 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
 900                 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
 901                 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
 902                 return result;
 903         }
 904
 905         ref_clock = smu7_get_xclk(hwmgr);
 906
 907         for (i = 0; i < NUM_SCLK_RANGE; i++) {
 908                 if (clock > smu_data->range_table[i].trans_lower_frequency
 909                 && clock <= smu_data->range_table[i].trans_upper_frequency) {
 910                         sclk_setting->PllRange = i;
 911                         break;
 912                 }
 913         }
 914
 915         sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 916         temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 917         temp <<= 0x10;
 918         do_div(temp, ref_clock);
 919         sclk_setting->Fcw_frac = temp & 0xffff;
 920
 921         pcc_target_percent = 10; /*  Hardcode 10% for now. */
 922         pcc_target_freq = clock - (clock * pcc_target_percent / 100);
 923         sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 924
 925         ss_target_percent = 2; /*  Hardcode 2% for now. */
 926         sclk_setting->SSc_En = 0;
 927         if (ss_target_percent) {
 928                 sclk_setting->SSc_En = 1;
 929                 ss_target_freq = clock - (clock * ss_target_percent / 100);
 930                 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 931                 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 932                 temp <<= 0x10;
 933                 do_div(temp, ref_clock);
 934                 sclk_setting->Fcw1_frac = temp & 0xffff;
 935         }
 936
 937         return 0;
 938 }
 939
 940 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
 941                 uint32_t clock, uint16_t sclk_al_threshold,
 942                 struct SMU74_Discrete_GraphicsLevel *level)
 943 {
 944         int result;
 945         /* PP_Clocks minClocks; */
 946         uint32_t mvdd;
 947         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 948         struct phm_ppt_v1_information *table_info =
 949                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 950         SMU_SclkSetting curr_sclk_setting = { 0 };
 951
 952         result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
 953
 954         /* populate graphics levels */
 955         result = polaris10_get_dependency_volt_by_clk(hwmgr,
 956                         table_info->vdd_dep_on_sclk, clock,
 957                         &level->MinVoltage, &mvdd);
 958
 959         PP_ASSERT_WITH_CODE((0 == result),
 960                         "can not find VDDC voltage value for "
 961                         "VDDC engine clock dependency table",
 962                         return result);
 963         level->ActivityLevel = sclk_al_threshold;
 964
 965         level->CcPwrDynRm = 0;
 966         level->CcPwrDynRm1 = 0;
 967         level->EnabledForActivity = 0;
 968         level->EnabledForThrottle = 1;
 969         level->UpHyst = 10;
 970         level->DownHyst = 0;
 971         level->VoltageDownHyst = 0;
 972         level->PowerThrottle = 0;
 973         data->display_timing.min_clock_in_sr = hwmgr->display_config.min_core_set_clock_in_sr;
 974
 975         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
 976                 level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
 977                                                                 hwmgr->display_config.min_core_set_clock_in_sr);
 978
 979         /* Default to slow, highest DPM level will be
 980          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
 981          */
 982         if (data->update_up_hyst)
 983                 level->UpHyst = (uint8_t)data->up_hyst;
 984         if (data->update_down_hyst)
 985                 level->DownHyst = (uint8_t)data->down_hyst;
 986
 987         level->SclkSetting = curr_sclk_setting;
 988
 989         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
 990         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
 991         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
 992         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
 993         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
 994         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
 995         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
 996         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
 997         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
 998         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
 999         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1000         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1001         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1002         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1003         return 0;
1004 }
1005
1006 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1007 {
1008         struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1009         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1010         struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1011         struct phm_ppt_v1_information *table_info =
1012                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1013         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1014         uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
1015         int result = 0;
1016         uint32_t array = smu_data->smu7_data.dpm_table_start +
1017                         offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1018         uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1019                         SMU74_MAX_LEVELS_GRAPHICS;
1020         struct SMU74_Discrete_GraphicsLevel *levels =
1021                         smu_data->smc_state_table.GraphicsLevel;
1022         uint32_t i, max_entry;
1023         uint8_t hightest_pcie_level_enabled = 0,
1024                 lowest_pcie_level_enabled = 0,
1025                 mid_pcie_level_enabled = 0,
1026                 count = 0;
1027
1028         polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
1029
1030         for (i = 0; i < dpm_table->sclk_table.count; i++) {
1031
1032                 result = polaris10_populate_single_graphic_level(hwmgr,
1033                                 dpm_table->sclk_table.dpm_levels[i].value,
1034                                 (uint16_t)smu_data->activity_target[i],
1035                                 &(smu_data->smc_state_table.GraphicsLevel[i]));
1036                 if (result)
1037                         return result;
1038
1039                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1040                 if (i > 1)
1041                         levels[i].DeepSleepDivId = 0;
1042         }
1043         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1044                                         PHM_PlatformCaps_SPLLShutdownSupport))
1045                 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1046
1047         smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1048         smu_data->smc_state_table.GraphicsDpmLevelCount =
1049                         (uint8_t)dpm_table->sclk_table.count;
1050         hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1051                         phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1052
1053
1054         if (pcie_table != NULL) {
1055                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1056                                 "There must be 1 or more PCIE levels defined in PPTable.",
1057                                 return -EINVAL);
1058                 max_entry = pcie_entry_cnt - 1;
1059                 for (i = 0; i < dpm_table->sclk_table.count; i++)
1060                         levels[i].pcieDpmLevel =
1061                                         (uint8_t) ((i < max_entry) ? i : max_entry);
1062         } else {
1063                 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1064                                 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1065                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1066                         hightest_pcie_level_enabled++;
1067
1068                 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1069                                 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1070                                                 (1 << lowest_pcie_level_enabled)) == 0))
1071                         lowest_pcie_level_enabled++;
1072
1073                 while ((count < hightest_pcie_level_enabled) &&
1074                                 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1075                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1076                         count++;
1077
1078                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1079                                 hightest_pcie_level_enabled ?
1080                                                 (lowest_pcie_level_enabled + 1 + count) :
1081                                                 hightest_pcie_level_enabled;
1082
1083                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1084                 for (i = 2; i < dpm_table->sclk_table.count; i++)
1085                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1086
1087                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1088                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1089
1090                 /* set pcieDpmLevel to mid_pcie_level_enabled */
1091                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1092         }
1093         /* level count will send to smc once at init smc table and never change */
1094         result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1095                         (uint32_t)array_size, SMC_RAM_END);
1096
1097         return result;
1098 }
1099
1100
1101 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1102                 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1103 {
1104         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1105         struct phm_ppt_v1_information *table_info =
1106                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1107         int result = 0;
1108         struct cgs_display_info info = {0, 0, NULL};
1109         uint32_t mclk_stutter_mode_threshold = 40000;
1110
1111         cgs_get_active_displays_info(hwmgr->device, &info);
1112
1113         if (table_info->vdd_dep_on_mclk) {
1114                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1115                                 table_info->vdd_dep_on_mclk, clock,
1116                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
1117                 PP_ASSERT_WITH_CODE((0 == result),
1118                                 "can not find MinVddc voltage value from memory "
1119                                 "VDDC voltage dependency table", return result);
1120         }
1121
1122         mem_level->MclkFrequency = clock;
1123         mem_level->EnabledForThrottle = 1;
1124         mem_level->EnabledForActivity = 0;
1125         mem_level->UpHyst = 0;
1126         mem_level->DownHyst = 100;
1127         mem_level->VoltageDownHyst = 0;
1128         mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
1129         mem_level->StutterEnable = false;
1130         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1131
1132         data->display_timing.num_existing_displays = info.display_count;
1133
1134         if (mclk_stutter_mode_threshold &&
1135                 (clock <= mclk_stutter_mode_threshold) &&
1136                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1137                                 STUTTER_ENABLE) & 0x1))
1138                 mem_level->StutterEnable = true;
1139
1140         if (!result) {
1141                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1142                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1143                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1144                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1145         }
1146         return result;
1147 }
1148
1149 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1150 {
1151         struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1152         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1153         struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1154         int result;
1155         /* populate MCLK dpm table to SMU7 */
1156         uint32_t array = smu_data->smu7_data.dpm_table_start +
1157                         offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1158         uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1159                         SMU74_MAX_LEVELS_MEMORY;
1160         struct SMU74_Discrete_MemoryLevel *levels =
1161                         smu_data->smc_state_table.MemoryLevel;
1162         uint32_t i;
1163
1164         for (i = 0; i < dpm_table->mclk_table.count; i++) {
1165                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1166                                 "can not populate memory level as memory clock is zero",
1167                                 return -EINVAL);
1168                 result = polaris10_populate_single_memory_level(hwmgr,
1169                                 dpm_table->mclk_table.dpm_levels[i].value,
1170                                 &levels[i]);
1171                 if (i == dpm_table->mclk_table.count - 1) {
1172                         levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1173                         levels[i].EnabledForActivity = 1;
1174                 }
1175                 if (result)
1176                         return result;
1177         }
1178
1179         /* In order to prevent MC activity from stutter mode to push DPM up,
1180          * the UVD change complements this by putting the MCLK in
1181          * a higher state by default such that we are not affected by
1182          * up threshold or and MCLK DPM latency.
1183          */
1184         levels[0].ActivityLevel = 0x1f;
1185         CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1186
1187         smu_data->smc_state_table.MemoryDpmLevelCount =
1188                         (uint8_t)dpm_table->mclk_table.count;
1189         hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1190                         phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1191
1192         /* level count will send to smc once at init smc table and never change */
1193         result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1194                         (uint32_t)array_size, SMC_RAM_END);
1195
1196         return result;
1197 }
1198
1199 static int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1200                 uint32_t mclk, SMIO_Pattern *smio_pat)
1201 {
1202         const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1203         struct phm_ppt_v1_information *table_info =
1204                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1205         uint32_t i = 0;
1206
1207         if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1208                 /* find mvdd value which clock is more than request */
1209                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1210                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1211                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1212                                 break;
1213                         }
1214                 }
1215                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1216                                 "MVDD Voltage is outside the supported range.",
1217                                 return -EINVAL);
1218         } else
1219                 return -EINVAL;
1220
1221         return 0;
1222 }
1223
1224 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1225                 SMU74_Discrete_DpmTable *table)
1226 {
1227         int result = 0;
1228         uint32_t sclk_frequency;
1229         const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1230         struct phm_ppt_v1_information *table_info =
1231                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1232         SMIO_Pattern vol_level;
1233         uint32_t mvdd;
1234         uint16_t us_mvdd;
1235
1236         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1237
1238         /* Get MinVoltage and Frequency from DPM0,
1239          * already converted to SMC_UL */
1240         sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1241         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1242                         table_info->vdd_dep_on_sclk,
1243                         sclk_frequency,
1244                         &table->ACPILevel.MinVoltage, &mvdd);
1245         PP_ASSERT_WITH_CODE((0 == result),
1246                         "Cannot find ACPI VDDC voltage value "
1247                         "in Clock Dependency Table",
1248                         );
1249
1250         result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
1251         PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1252
1253         table->ACPILevel.DeepSleepDivId = 0;
1254         table->ACPILevel.CcPwrDynRm = 0;
1255         table->ACPILevel.CcPwrDynRm1 = 0;
1256
1257         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1258         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1259         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1260         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1261
1262         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1263         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1264         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1265         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1266         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1267         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1268         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1269         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1270         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1271         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1272
1273
1274         /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1275         table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
1276         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1277                         table_info->vdd_dep_on_mclk,
1278                         table->MemoryACPILevel.MclkFrequency,
1279                         &table->MemoryACPILevel.MinVoltage, &mvdd);
1280         PP_ASSERT_WITH_CODE((0 == result),
1281                         "Cannot find ACPI VDDCI voltage value "
1282                         "in Clock Dependency Table",
1283                         );
1284
1285         us_mvdd = 0;
1286         if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1287                         (data->mclk_dpm_key_disabled))
1288                 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1289         else {
1290                 if (!polaris10_populate_mvdd_value(hwmgr,
1291                                 data->dpm_table.mclk_table.dpm_levels[0].value,
1292                                 &vol_level))
1293                         us_mvdd = vol_level.Voltage;
1294         }
1295
1296         if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1297                 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1298         else
1299                 table->MemoryACPILevel.MinMvdd = 0;
1300
1301         table->MemoryACPILevel.StutterEnable = false;
1302
1303         table->MemoryACPILevel.EnabledForThrottle = 0;
1304         table->MemoryACPILevel.EnabledForActivity = 0;
1305         table->MemoryACPILevel.UpHyst = 0;
1306         table->MemoryACPILevel.DownHyst = 100;
1307         table->MemoryACPILevel.VoltageDownHyst = 0;
1308         table->MemoryACPILevel.ActivityLevel =
1309                         PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
1310
1311         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1312         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1313
1314         return result;
1315 }
1316
1317 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1318                 SMU74_Discrete_DpmTable *table)
1319 {
1320         int result = -EINVAL;
1321         uint8_t count;
1322         struct pp_atomctrl_clock_dividers_vi dividers;
1323         struct phm_ppt_v1_information *table_info =
1324                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1325         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1326                         table_info->mm_dep_table;
1327         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1328         uint32_t vddci;
1329
1330         table->VceLevelCount = (uint8_t)(mm_table->count);
1331         table->VceBootLevel = 0;
1332
1333         for (count = 0; count < table->VceLevelCount; count++) {
1334                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1335                 table->VceLevel[count].MinVoltage = 0;
1336                 table->VceLevel[count].MinVoltage |=
1337                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1338
1339                 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1340                         vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1341                                                 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1342                 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1343                         vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1344                 else
1345                         vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1346
1347
1348                 table->VceLevel[count].MinVoltage |=
1349                                 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1350                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1351
1352                 /*retrieve divider value for VBIOS */
1353                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1354                                 table->VceLevel[count].Frequency, &dividers);
1355                 PP_ASSERT_WITH_CODE((0 == result),
1356                                 "can not find divide id for VCE engine clock",
1357                                 return result);
1358
1359                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1360
1361                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1362                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1363         }
1364         return result;
1365 }
1366
1367
1368 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1369                 SMU74_Discrete_DpmTable *table)
1370 {
1371         int result = -EINVAL;
1372         uint8_t count;
1373         struct pp_atomctrl_clock_dividers_vi dividers;
1374         struct phm_ppt_v1_information *table_info =
1375                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1376         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1377                         table_info->mm_dep_table;
1378         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1379         uint32_t vddci;
1380
1381         table->SamuBootLevel = 0;
1382         table->SamuLevelCount = (uint8_t)(mm_table->count);
1383
1384         for (count = 0; count < table->SamuLevelCount; count++) {
1385                 /* not sure whether we need evclk or not */
1386                 table->SamuLevel[count].MinVoltage = 0;
1387                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1388                 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1389                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1390
1391                 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1392                         vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1393                                                 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1394                 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1395                         vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1396                 else
1397                         vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1398
1399                 table->SamuLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1400                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1401
1402                 /* retrieve divider value for VBIOS */
1403                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1404                                 table->SamuLevel[count].Frequency, &dividers);
1405                 PP_ASSERT_WITH_CODE((0 == result),
1406                                 "can not find divide id for samu clock", return result);
1407
1408                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1409
1410                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1411                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1412         }
1413         return result;
1414 }
1415
1416 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1417                 int32_t eng_clock, int32_t mem_clock,
1418                 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1419 {
1420         uint32_t dram_timing;
1421         uint32_t dram_timing2;
1422         uint32_t burst_time;
1423         int result;
1424
1425         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1426                         eng_clock, mem_clock);
1427         PP_ASSERT_WITH_CODE(result == 0,
1428                         "Error calling VBIOS to set DRAM_TIMING.", return result);
1429
1430         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1431         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1432         burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1433
1434
1435         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
1436         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1437         arb_regs->McArbBurstTime   = (uint8_t)burst_time;
1438
1439         return 0;
1440 }
1441
1442 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1443 {
1444         struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1445         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1446         struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1447         uint32_t i, j;
1448         int result = 0;
1449
1450         for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1451                 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
1452                         result = polaris10_populate_memory_timing_parameters(hwmgr,
1453                                         hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1454                                         hw_data->dpm_table.mclk_table.dpm_levels[j].value,
1455                                         &arb_regs.entries[i][j]);
1456                         if (result == 0)
1457                                 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
1458                         if (result != 0)
1459                                 return result;
1460                 }
1461         }
1462
1463         result = smu7_copy_bytes_to_smc(
1464                         hwmgr,
1465                         smu_data->smu7_data.arb_table_start,
1466                         (uint8_t *)&arb_regs,
1467                         sizeof(SMU74_Discrete_MCArbDramTimingTable),
1468                         SMC_RAM_END);
1469         return result;
1470 }
1471
1472 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1473                 struct SMU74_Discrete_DpmTable *table)
1474 {
1475         int result = -EINVAL;
1476         uint8_t count;
1477         struct pp_atomctrl_clock_dividers_vi dividers;
1478         struct phm_ppt_v1_information *table_info =
1479                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1480         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1481                         table_info->mm_dep_table;
1482         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1483         uint32_t vddci;
1484
1485         table->UvdLevelCount = (uint8_t)(mm_table->count);
1486         table->UvdBootLevel = 0;
1487
1488         for (count = 0; count < table->UvdLevelCount; count++) {
1489                 table->UvdLevel[count].MinVoltage = 0;
1490                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1491                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1492                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1493                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1494
1495                 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1496                         vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1497                                                 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1498                 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1499                         vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1500                 else
1501                         vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1502
1503                 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1504                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1505
1506                 /* retrieve divider value for VBIOS */
1507                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1508                                 table->UvdLevel[count].VclkFrequency, &dividers);
1509                 PP_ASSERT_WITH_CODE((0 == result),
1510                                 "can not find divide id for Vclk clock", return result);
1511
1512                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1513
1514                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1515                                 table->UvdLevel[count].DclkFrequency, &dividers);
1516                 PP_ASSERT_WITH_CODE((0 == result),
1517                                 "can not find divide id for Dclk clock", return result);
1518
1519                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1520
1521                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1522                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1523                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1524         }
1525
1526         return result;
1527 }
1528
1529 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1530                 struct SMU74_Discrete_DpmTable *table)
1531 {
1532         int result = 0;
1533         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1534
1535         table->GraphicsBootLevel = 0;
1536         table->MemoryBootLevel = 0;
1537
1538         /* find boot level from dpm table */
1539         result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1540                         data->vbios_boot_state.sclk_bootup_value,
1541                         (uint32_t *)&(table->GraphicsBootLevel));
1542
1543         result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1544                         data->vbios_boot_state.mclk_bootup_value,
1545                         (uint32_t *)&(table->MemoryBootLevel));
1546
1547         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
1548                         VOLTAGE_SCALE;
1549         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1550                         VOLTAGE_SCALE;
1551         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
1552                         VOLTAGE_SCALE;
1553
1554         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1555         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1556         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1557
1558         return 0;
1559 }
1560
1561 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1562 {
1563         struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1564         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1565         struct phm_ppt_v1_information *table_info =
1566                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1567         uint8_t count, level;
1568
1569         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1570
1571         for (level = 0; level < count; level++) {
1572                 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1573                                 hw_data->vbios_boot_state.sclk_bootup_value) {
1574                         smu_data->smc_state_table.GraphicsBootLevel = level;
1575                         break;
1576                 }
1577         }
1578
1579         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1580         for (level = 0; level < count; level++) {
1581                 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1582                                 hw_data->vbios_boot_state.mclk_bootup_value) {
1583                         smu_data->smc_state_table.MemoryBootLevel = level;
1584                         break;
1585                 }
1586         }
1587
1588         return 0;
1589 }
1590
1591 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1592 {
1593         uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1594         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1595
1596         uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1597         struct phm_ppt_v1_information *table_info =
1598                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1599         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1600                         table_info->vdd_dep_on_sclk;
1601
1602         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1603
1604         /* Read SMU_Eefuse to read and calculate RO and determine
1605          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1606          */
1607         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1608                         ixSMU_EFUSE_0 + (67 * 4));
1609         efuse &= 0xFF000000;
1610         efuse = efuse >> 24;
1611
1612         if (hwmgr->chip_id == CHIP_POLARIS10) {
1613                 min = 1000;
1614                 max = 2300;
1615         } else {
1616                 min = 1100;
1617                 max = 2100;
1618         }
1619
1620         ro = efuse * (max - min) / 255 + min;
1621
1622         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1623         for (i = 0; i < sclk_table->count; i++) {
1624                 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1625                                 sclk_table->entries[i].cks_enable << i;
1626                 if (hwmgr->chip_id == CHIP_POLARIS10) {
1627                         volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \
1628                                                 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1629                         volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
1630                                         (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1631                 } else {
1632                         volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \
1633                                                 (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
1634                         volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
1635                                         (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
1636                 }
1637
1638                 if (volt_without_cks >= volt_with_cks)
1639                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1640                                         sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1641
1642                 smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1643         }
1644
1645         smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
1646         /* Populate CKS Lookup Table */
1647         if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1648                 stretch_amount2 = 0;
1649         else if (stretch_amount == 3 || stretch_amount == 4)
1650                 stretch_amount2 = 1;
1651         else {
1652                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1653                                 PHM_PlatformCaps_ClockStretcher);
1654                 PP_ASSERT_WITH_CODE(false,
1655                                 "Stretch Amount in PPTable not supported",
1656                                 return -EINVAL);
1657         }
1658
1659         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1660         value &= 0xFFFFFFFE;
1661         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1662
1663         return 0;
1664 }
1665
1666 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1667                 struct SMU74_Discrete_DpmTable *table)
1668 {
1669         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1670         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1671         uint16_t config;
1672
1673         config = VR_MERGED_WITH_VDDC;
1674         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1675
1676         /* Set Vddc Voltage Controller */
1677         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1678                 config = VR_SVI2_PLANE_1;
1679                 table->VRConfig |= config;
1680         } else {
1681                 PP_ASSERT_WITH_CODE(false,
1682                                 "VDDC should be on SVI2 control in merged mode!",
1683                                 );
1684         }
1685         /* Set Vddci Voltage Controller */
1686         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1687                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
1688                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1689         } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1690                 config = VR_SMIO_PATTERN_1;
1691                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1692         } else {
1693                 config = VR_STATIC_VOLTAGE;
1694                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1695         }
1696         /* Set Mvdd Voltage Controller */
1697         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1698                 config = VR_SVI2_PLANE_2;
1699                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1700                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
1701                         offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
1702         } else {
1703                 config = VR_STATIC_VOLTAGE;
1704                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1705         }
1706
1707         return 0;
1708 }
1709
1710
1711 static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1712 {
1713         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1714         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1715
1716         SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
1717         int result = 0;
1718         struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1719         AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1720         AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1721         uint32_t tmp, i;
1722
1723         struct phm_ppt_v1_information *table_info =
1724                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1725         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1726                         table_info->vdd_dep_on_sclk;
1727
1728
1729         if (((struct smu7_smumgr *)smu_data)->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
1730                 return result;
1731
1732         result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1733
1734         if (0 == result) {
1735                 table->BTCGB_VDROOP_TABLE[0].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1736                 table->BTCGB_VDROOP_TABLE[0].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1737                 table->BTCGB_VDROOP_TABLE[0].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1738                 table->BTCGB_VDROOP_TABLE[1].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1739                 table->BTCGB_VDROOP_TABLE[1].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1740                 table->BTCGB_VDROOP_TABLE[1].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1741                 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1742                 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1743                 table->AVFSGB_VDROOP_TABLE[0].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1744                 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1745                 table->AVFSGB_VDROOP_TABLE[0].m2_shift  = 12;
1746                 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1747                 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1748                 table->AVFSGB_VDROOP_TABLE[1].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1749                 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1750                 table->AVFSGB_VDROOP_TABLE[1].m2_shift  = 12;
1751                 table->MaxVoltage                = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1752                 AVFS_meanNsigma.Aconstant[0]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1753                 AVFS_meanNsigma.Aconstant[1]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1754                 AVFS_meanNsigma.Aconstant[2]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1755                 AVFS_meanNsigma.DC_tol_sigma      = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1756                 AVFS_meanNsigma.Platform_mean     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1757                 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1758                 AVFS_meanNsigma.Platform_sigma     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1759
1760                 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1761                         AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1762                         AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1763                 }
1764
1765                 result = smu7_read_smc_sram_dword(hwmgr,
1766                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1767                                 &tmp, SMC_RAM_END);
1768
1769                 smu7_copy_bytes_to_smc(hwmgr,
1770                                         tmp,
1771                                         (uint8_t *)&AVFS_meanNsigma,
1772                                         sizeof(AVFS_meanNsigma_t),
1773                                         SMC_RAM_END);
1774
1775                 result = smu7_read_smc_sram_dword(hwmgr,
1776                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1777                                 &tmp, SMC_RAM_END);
1778                 smu7_copy_bytes_to_smc(hwmgr,
1779                                         tmp,
1780                                         (uint8_t *)&AVFS_SclkOffset,
1781                                         sizeof(AVFS_Sclk_Offset_t),
1782                                         SMC_RAM_END);
1783
1784                 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1785                                                 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1786                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1787                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1788                 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1789         }
1790         return result;
1791 }
1792
1793 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
1794 {
1795         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1796         uint32_t tmp;
1797         int result;
1798
1799         /* This is a read-modify-write on the first byte of the ARB table.
1800          * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
1801          * is the field 'current'.
1802          * This solution is ugly, but we never write the whole table only
1803          * individual fields in it.
1804          * In reality this field should not be in that structure
1805          * but in a soft register.
1806          */
1807         result = smu7_read_smc_sram_dword(hwmgr,
1808                         smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
1809
1810         if (result)
1811                 return result;
1812
1813         tmp &= 0x00FFFFFF;
1814         tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
1815
1816         return smu7_write_smc_sram_dword(hwmgr,
1817                         smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
1818 }
1819
1820 static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1821 {
1822         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1823         struct  phm_ppt_v1_information *table_info =
1824                         (struct  phm_ppt_v1_information *)(hwmgr->pptable);
1825
1826         if (table_info &&
1827                         table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
1828                         table_info->cac_dtp_table->usPowerTuneDataSetID)
1829                 smu_data->power_tune_defaults =
1830                                 &polaris10_power_tune_data_set_array
1831                                 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
1832         else
1833                 smu_data->power_tune_defaults = &polaris10_power_tune_data_set_array[0];
1834
1835 }
1836
1837 static void polaris10_save_default_power_profile(struct pp_hwmgr *hwmgr)
1838 {
1839         struct polaris10_smumgr *data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1840         struct SMU74_Discrete_GraphicsLevel *levels =
1841                                 data->smc_state_table.GraphicsLevel;
1842         unsigned min_level = 1;
1843
1844         hwmgr->default_gfx_power_profile.activity_threshold =
1845                         be16_to_cpu(levels[0].ActivityLevel);
1846         hwmgr->default_gfx_power_profile.up_hyst = levels[0].UpHyst;
1847         hwmgr->default_gfx_power_profile.down_hyst = levels[0].DownHyst;
1848         hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
1849
1850         hwmgr->default_compute_power_profile = hwmgr->default_gfx_power_profile;
1851         hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
1852
1853         /* Workaround compute SDMA instability: disable lowest SCLK
1854          * DPM level. Optimize compute power profile: Use only highest
1855          * 2 power levels (if more than 2 are available), Hysteresis:
1856          * 0ms up, 5ms down
1857          */
1858         if (data->smc_state_table.GraphicsDpmLevelCount > 2)
1859                 min_level = data->smc_state_table.GraphicsDpmLevelCount - 2;
1860         else if (data->smc_state_table.GraphicsDpmLevelCount == 2)
1861                 min_level = 1;
1862         else
1863                 min_level = 0;
1864         hwmgr->default_compute_power_profile.min_sclk =
1865                 be32_to_cpu(levels[min_level].SclkSetting.SclkFrequency);
1866         hwmgr->default_compute_power_profile.up_hyst = 0;
1867         hwmgr->default_compute_power_profile.down_hyst = 5;
1868
1869         hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
1870         hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
1871 }
1872
1873 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1874 {
1875         int result;
1876         struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1877         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1878
1879         struct phm_ppt_v1_information *table_info =
1880                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1881         struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1882         uint8_t i;
1883         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1884         pp_atomctrl_clock_dividers_vi dividers;
1885
1886         polaris10_initialize_power_tune_defaults(hwmgr);
1887
1888         if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
1889                 polaris10_populate_smc_voltage_tables(hwmgr, table);
1890
1891         table->SystemFlags = 0;
1892         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1893                         PHM_PlatformCaps_AutomaticDCTransition))
1894                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1895
1896         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1897                         PHM_PlatformCaps_StepVddc))
1898                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1899
1900         if (hw_data->is_memory_gddr5)
1901                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1902
1903         if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
1904                 result = polaris10_populate_ulv_state(hwmgr, table);
1905                 PP_ASSERT_WITH_CODE(0 == result,
1906                                 "Failed to initialize ULV state!", return result);
1907                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1908                                 ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
1909         }
1910
1911         result = polaris10_populate_smc_link_level(hwmgr, table);
1912         PP_ASSERT_WITH_CODE(0 == result,
1913                         "Failed to initialize Link Level!", return result);
1914
1915         result = polaris10_populate_all_graphic_levels(hwmgr);
1916         PP_ASSERT_WITH_CODE(0 == result,
1917                         "Failed to initialize Graphics Level!", return result);
1918
1919         result = polaris10_populate_all_memory_levels(hwmgr);
1920         PP_ASSERT_WITH_CODE(0 == result,
1921                         "Failed to initialize Memory Level!", return result);
1922
1923         result = polaris10_populate_smc_acpi_level(hwmgr, table);
1924         PP_ASSERT_WITH_CODE(0 == result,
1925                         "Failed to initialize ACPI Level!", return result);
1926
1927         result = polaris10_populate_smc_vce_level(hwmgr, table);
1928         PP_ASSERT_WITH_CODE(0 == result,
1929                         "Failed to initialize VCE Level!", return result);
1930
1931         result = polaris10_populate_smc_samu_level(hwmgr, table);
1932         PP_ASSERT_WITH_CODE(0 == result,
1933                         "Failed to initialize SAMU Level!", return result);
1934
1935         /* Since only the initial state is completely set up at this point
1936          * (the other states are just copies of the boot state) we only
1937          * need to populate the  ARB settings for the initial state.
1938          */
1939         result = polaris10_program_memory_timing_parameters(hwmgr);
1940         PP_ASSERT_WITH_CODE(0 == result,
1941                         "Failed to Write ARB settings for the initial state.", return result);
1942
1943         result = polaris10_populate_smc_uvd_level(hwmgr, table);
1944         PP_ASSERT_WITH_CODE(0 == result,
1945                         "Failed to initialize UVD Level!", return result);
1946
1947         result = polaris10_populate_smc_boot_level(hwmgr, table);
1948         PP_ASSERT_WITH_CODE(0 == result,
1949                         "Failed to initialize Boot Level!", return result);
1950
1951         result = polaris10_populate_smc_initailial_state(hwmgr);
1952         PP_ASSERT_WITH_CODE(0 == result,
1953                         "Failed to initialize Boot State!", return result);
1954
1955         result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
1956         PP_ASSERT_WITH_CODE(0 == result,
1957                         "Failed to populate BAPM Parameters!", return result);
1958
1959         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1960                         PHM_PlatformCaps_ClockStretcher)) {
1961                 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
1962                 PP_ASSERT_WITH_CODE(0 == result,
1963                                 "Failed to populate Clock Stretcher Data Table!",
1964                                 return result);
1965         }
1966
1967         result = polaris10_populate_avfs_parameters(hwmgr);
1968         PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
1969
1970         table->CurrSclkPllRange = 0xff;
1971         table->GraphicsVoltageChangeEnable  = 1;
1972         table->GraphicsThermThrottleEnable  = 1;
1973         table->GraphicsInterval = 1;
1974         table->VoltageInterval  = 1;
1975         table->ThermalInterval  = 1;
1976         table->TemperatureLimitHigh =
1977                         table_info->cac_dtp_table->usTargetOperatingTemp *
1978                         SMU7_Q88_FORMAT_CONVERSION_UNIT;
1979         table->TemperatureLimitLow  =
1980                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
1981                         SMU7_Q88_FORMAT_CONVERSION_UNIT;
1982         table->MemoryVoltageChangeEnable = 1;
1983         table->MemoryInterval = 1;
1984         table->VoltageResponseTime = 0;
1985         table->PhaseResponseTime = 0;
1986         table->MemoryThermThrottleEnable = 1;
1987         table->PCIeBootLinkLevel = 0;
1988         table->PCIeGenInterval = 1;
1989         table->VRConfig = 0;
1990
1991         result = polaris10_populate_vr_config(hwmgr, table);
1992         PP_ASSERT_WITH_CODE(0 == result,
1993                         "Failed to populate VRConfig setting!", return result);
1994
1995         table->ThermGpio = 17;
1996         table->SclkStepSize = 0x4000;
1997
1998         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
1999                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2000         } else {
2001                 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2002                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2003                                 PHM_PlatformCaps_RegulatorHot);
2004         }
2005
2006         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2007                         &gpio_pin)) {
2008                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2009                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2010                                 PHM_PlatformCaps_AutomaticDCTransition);
2011         } else {
2012                 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2013                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2014                                 PHM_PlatformCaps_AutomaticDCTransition);
2015         }
2016
2017         /* Thermal Output GPIO */
2018         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2019                         &gpio_pin)) {
2020                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2021                                 PHM_PlatformCaps_ThermalOutGPIO);
2022
2023                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2024
2025                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2026                  * since VBIOS will program this register to set 'inactive state',
2027                  * driver can then determine 'active state' from this and
2028                  * program SMU with correct polarity
2029                  */
2030                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2031                                         & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2032                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2033
2034                 /* if required, combine VRHot/PCC with thermal out GPIO */
2035                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2036                 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2037                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2038         } else {
2039                 table->ThermOutGpio = 17;
2040                 table->ThermOutPolarity = 1;
2041                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2042         }
2043
2044         /* Populate BIF_SCLK levels into SMC DPM table */
2045         for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
2046                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], &dividers);
2047                 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2048
2049                 if (i == 0)
2050                         table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2051                 else
2052                         table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2053         }
2054
2055         for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2056                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2057
2058         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2059         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2060         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2061         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2062         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2063         CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2064         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2065         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2066         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2067         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2068
2069         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2070         result = smu7_copy_bytes_to_smc(hwmgr,
2071                         smu_data->smu7_data.dpm_table_start +
2072                         offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2073                         (uint8_t *)&(table->SystemFlags),
2074                         sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2075                         SMC_RAM_END);
2076         PP_ASSERT_WITH_CODE(0 == result,
2077                         "Failed to upload dpm data to SMC memory!", return result);
2078
2079         result = polaris10_init_arb_table_index(hwmgr);
2080         PP_ASSERT_WITH_CODE(0 == result,
2081                         "Failed to upload arb data to SMC memory!", return result);
2082
2083         result = polaris10_populate_pm_fuses(hwmgr);
2084         PP_ASSERT_WITH_CODE(0 == result,
2085                         "Failed to  populate PM fuses to SMC memory!", return result);
2086
2087         polaris10_save_default_power_profile(hwmgr);
2088
2089         return 0;
2090 }
2091
2092 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2093 {
2094         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2095
2096         if (data->need_update_smu7_dpm_table &
2097                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2098                 return polaris10_program_memory_timing_parameters(hwmgr);
2099
2100         return 0;
2101 }
2102
2103 int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2104 {
2105         int ret;
2106         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
2107         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2108
2109         if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
2110                 return 0;
2111
2112         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2113                         PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting);
2114
2115         ret = (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs) == 0) ?
2116                         0 : -1;
2117
2118         if (!ret)
2119                 /* If this param is not changed, this function could fire unnecessarily */
2120                 smu_data->avfs.avfs_btc_status = AVFS_BTC_COMPLETED_PREVIOUSLY;
2121
2122         return ret;
2123 }
2124
2125 static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2126 {
2127         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2128         SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2129         uint32_t duty100;
2130         uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2131         uint16_t fdo_min, slope1, slope2;
2132         uint32_t reference_clock;
2133         int res;
2134         uint64_t tmp64;
2135
2136         if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2137                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2138                         PHM_PlatformCaps_MicrocodeFanControl);
2139                 return 0;
2140         }
2141
2142         if (smu_data->smu7_data.fan_table_start == 0) {
2143                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2144                                 PHM_PlatformCaps_MicrocodeFanControl);
2145                 return 0;
2146         }
2147
2148         duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2149                         CG_FDO_CTRL1, FMAX_DUTY100);
2150
2151         if (duty100 == 0) {
2152                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2153                                 PHM_PlatformCaps_MicrocodeFanControl);
2154                 return 0;
2155         }
2156
2157         tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
2158                         usPWMMin * duty100;
2159         do_div(tmp64, 10000);
2160         fdo_min = (uint16_t)tmp64;
2161
2162         t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
2163                         hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2164         t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
2165                         hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2166
2167         pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
2168                         hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2169         pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
2170                         hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2171
2172         slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2173         slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2174
2175         fan_table.TempMin = cpu_to_be16((50 + hwmgr->
2176                         thermal_controller.advanceFanControlParameters.usTMin) / 100);
2177         fan_table.TempMed = cpu_to_be16((50 + hwmgr->
2178                         thermal_controller.advanceFanControlParameters.usTMed) / 100);
2179         fan_table.TempMax = cpu_to_be16((50 + hwmgr->
2180                         thermal_controller.advanceFanControlParameters.usTMax) / 100);
2181
2182         fan_table.Slope1 = cpu_to_be16(slope1);
2183         fan_table.Slope2 = cpu_to_be16(slope2);
2184
2185         fan_table.FdoMin = cpu_to_be16(fdo_min);
2186
2187         fan_table.HystDown = cpu_to_be16(hwmgr->
2188                         thermal_controller.advanceFanControlParameters.ucTHyst);
2189
2190         fan_table.HystUp = cpu_to_be16(1);
2191
2192         fan_table.HystSlope = cpu_to_be16(1);
2193
2194         fan_table.TempRespLim = cpu_to_be16(5);
2195
2196         reference_clock = smu7_get_xclk(hwmgr);
2197
2198         fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
2199                         thermal_controller.advanceFanControlParameters.ulCycleDelay *
2200                         reference_clock) / 1600);
2201
2202         fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2203
2204         fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
2205                         hwmgr->device, CGS_IND_REG__SMC,
2206                         CG_MULT_THERMAL_CTRL, TEMP_SEL);
2207
2208         res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
2209                         (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
2210                         SMC_RAM_END);
2211
2212         if (!res && hwmgr->thermal_controller.
2213                         advanceFanControlParameters.ucMinimumPWMLimit)
2214                 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2215                                 PPSMC_MSG_SetFanMinPwm,
2216                                 hwmgr->thermal_controller.
2217                                 advanceFanControlParameters.ucMinimumPWMLimit);
2218
2219         if (!res && hwmgr->thermal_controller.
2220                         advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
2221                 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2222                                 PPSMC_MSG_SetFanSclkTarget,
2223                                 hwmgr->thermal_controller.
2224                                 advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
2225
2226         if (res)
2227                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2228                                 PHM_PlatformCaps_MicrocodeFanControl);
2229
2230         return 0;
2231 }
2232
2233 static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2234 {
2235         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2236         uint32_t mm_boot_level_offset, mm_boot_level_value;
2237         struct phm_ppt_v1_information *table_info =
2238                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2239
2240         smu_data->smc_state_table.UvdBootLevel = 0;
2241         if (table_info->mm_dep_table->count > 0)
2242                 smu_data->smc_state_table.UvdBootLevel =
2243                                 (uint8_t) (table_info->mm_dep_table->count - 1);
2244         mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable,
2245                                                 UvdBootLevel);
2246         mm_boot_level_offset /= 4;
2247         mm_boot_level_offset *= 4;
2248         mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2249                         CGS_IND_REG__SMC, mm_boot_level_offset);
2250         mm_boot_level_value &= 0x00FFFFFF;
2251         mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2252         cgs_write_ind_register(hwmgr->device,
2253                         CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2254
2255         if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2256                         PHM_PlatformCaps_UVDDPM) ||
2257                 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2258                         PHM_PlatformCaps_StablePState))
2259                 smum_send_msg_to_smc_with_parameter(hwmgr,
2260                                 PPSMC_MSG_UVDDPM_SetEnabledMask,
2261                                 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
2262         return 0;
2263 }
2264
2265 static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2266 {
2267         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2268         uint32_t mm_boot_level_offset, mm_boot_level_value;
2269         struct phm_ppt_v1_information *table_info =
2270                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2271
2272         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2273                                         PHM_PlatformCaps_StablePState))
2274                 smu_data->smc_state_table.VceBootLevel =
2275                         (uint8_t) (table_info->mm_dep_table->count - 1);
2276         else
2277                 smu_data->smc_state_table.VceBootLevel = 0;
2278
2279         mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
2280                                         offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2281         mm_boot_level_offset /= 4;
2282         mm_boot_level_offset *= 4;
2283         mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2284                         CGS_IND_REG__SMC, mm_boot_level_offset);
2285         mm_boot_level_value &= 0xFF00FFFF;
2286         mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2287         cgs_write_ind_register(hwmgr->device,
2288                         CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2289
2290         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
2291                 smum_send_msg_to_smc_with_parameter(hwmgr,
2292                                 PPSMC_MSG_VCEDPM_SetEnabledMask,
2293                                 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
2294         return 0;
2295 }
2296
2297 static int polaris10_update_samu_smc_table(struct pp_hwmgr *hwmgr)
2298 {
2299         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2300         uint32_t mm_boot_level_offset, mm_boot_level_value;
2301
2302
2303         smu_data->smc_state_table.SamuBootLevel = 0;
2304         mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
2305                                 offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
2306
2307         mm_boot_level_offset /= 4;
2308         mm_boot_level_offset *= 4;
2309         mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2310                         CGS_IND_REG__SMC, mm_boot_level_offset);
2311         mm_boot_level_value &= 0xFFFFFF00;
2312         mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
2313         cgs_write_ind_register(hwmgr->device,
2314                         CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2315
2316         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2317                         PHM_PlatformCaps_StablePState))
2318                 smum_send_msg_to_smc_with_parameter(hwmgr,
2319                                 PPSMC_MSG_SAMUDPM_SetEnabledMask,
2320                                 (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
2321         return 0;
2322 }
2323
2324
2325 static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr)
2326 {
2327         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2328         struct phm_ppt_v1_information *table_info =
2329                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2330         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
2331         int max_entry, i;
2332
2333         max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
2334                                                 SMU74_MAX_LEVELS_LINK :
2335                                                 pcie_table->count;
2336         /* Setup BIF_SCLK levels */
2337         for (i = 0; i < max_entry; i++)
2338                 smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
2339         return 0;
2340 }
2341
2342 static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2343 {
2344         switch (type) {
2345         case SMU_UVD_TABLE:
2346                 polaris10_update_uvd_smc_table(hwmgr);
2347                 break;
2348         case SMU_VCE_TABLE:
2349                 polaris10_update_vce_smc_table(hwmgr);
2350                 break;
2351         case SMU_SAMU_TABLE:
2352                 polaris10_update_samu_smc_table(hwmgr);
2353                 break;
2354         case SMU_BIF_TABLE:
2355                 polaris10_update_bif_smc_table(hwmgr);
2356         default:
2357                 break;
2358         }
2359         return 0;
2360 }
2361
2362 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2363 {
2364         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2365         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2366
2367         int result = 0;
2368         uint32_t low_sclk_interrupt_threshold = 0;
2369
2370         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2371                         PHM_PlatformCaps_SclkThrottleLowNotification)
2372                 && (data->low_sclk_interrupt_threshold != 0)) {
2373                 low_sclk_interrupt_threshold =
2374                                 data->low_sclk_interrupt_threshold;
2375
2376                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2377
2378                 result = smu7_copy_bytes_to_smc(
2379                                 hwmgr,
2380                                 smu_data->smu7_data.dpm_table_start +
2381                                 offsetof(SMU74_Discrete_DpmTable,
2382                                         LowSclkInterruptThreshold),
2383                                 (uint8_t *)&low_sclk_interrupt_threshold,
2384                                 sizeof(uint32_t),
2385                                 SMC_RAM_END);
2386         }
2387         PP_ASSERT_WITH_CODE((result == 0),
2388                         "Failed to update SCLK threshold!", return result);
2389
2390         result = polaris10_program_mem_timing_parameters(hwmgr);
2391         PP_ASSERT_WITH_CODE((result == 0),
2392                         "Failed to program memory timing parameters!",
2393                         );
2394
2395         return result;
2396 }
2397
2398 static uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
2399 {
2400         switch (type) {
2401         case SMU_SoftRegisters:
2402                 switch (member) {
2403                 case HandshakeDisables:
2404                         return offsetof(SMU74_SoftRegisters, HandshakeDisables);
2405                 case VoltageChangeTimeout:
2406                         return offsetof(SMU74_SoftRegisters, VoltageChangeTimeout);
2407                 case AverageGraphicsActivity:
2408                         return offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
2409                 case PreVBlankGap:
2410                         return offsetof(SMU74_SoftRegisters, PreVBlankGap);
2411                 case VBlankTimeout:
2412                         return offsetof(SMU74_SoftRegisters, VBlankTimeout);
2413                 case UcodeLoadStatus:
2414                         return offsetof(SMU74_SoftRegisters, UcodeLoadStatus);
2415                 case DRAM_LOG_ADDR_H:
2416                         return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_H);
2417                 case DRAM_LOG_ADDR_L:
2418                         return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_L);
2419                 case DRAM_LOG_PHY_ADDR_H:
2420                         return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2421                 case DRAM_LOG_PHY_ADDR_L:
2422                         return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2423                 case DRAM_LOG_BUFF_SIZE:
2424                         return offsetof(SMU74_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2425                 }
2426         case SMU_Discrete_DpmTable:
2427                 switch (member) {
2428                 case UvdBootLevel:
2429                         return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
2430                 case VceBootLevel:
2431                         return offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2432                 case SamuBootLevel:
2433                         return offsetof(SMU74_Discrete_DpmTable, SamuBootLevel);
2434                 case LowSclkInterruptThreshold:
2435                         return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold);
2436                 }
2437         }
2438         pr_warn("can't get the offset of type %x member %x\n", type, member);
2439         return 0;
2440 }
2441
2442 static uint32_t polaris10_get_mac_definition(uint32_t value)
2443 {
2444         switch (value) {
2445         case SMU_MAX_LEVELS_GRAPHICS:
2446                 return SMU74_MAX_LEVELS_GRAPHICS;
2447         case SMU_MAX_LEVELS_MEMORY:
2448                 return SMU74_MAX_LEVELS_MEMORY;
2449         case SMU_MAX_LEVELS_LINK:
2450                 return SMU74_MAX_LEVELS_LINK;
2451         case SMU_MAX_ENTRIES_SMIO:
2452                 return SMU74_MAX_ENTRIES_SMIO;
2453         case SMU_MAX_LEVELS_VDDC:
2454                 return SMU74_MAX_LEVELS_VDDC;
2455         case SMU_MAX_LEVELS_VDDGFX:
2456                 return SMU74_MAX_LEVELS_VDDGFX;
2457         case SMU_MAX_LEVELS_VDDCI:
2458                 return SMU74_MAX_LEVELS_VDDCI;
2459         case SMU_MAX_LEVELS_MVDD:
2460                 return SMU74_MAX_LEVELS_MVDD;
2461         case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
2462                 return SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2463         }
2464
2465         pr_warn("can't get the mac of %x\n", value);
2466         return 0;
2467 }
2468
2469 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2470 {
2471         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2472         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2473         uint32_t tmp;
2474         int result;
2475         bool error = false;
2476
2477         result = smu7_read_smc_sram_dword(hwmgr,
2478                         SMU7_FIRMWARE_HEADER_LOCATION +
2479                         offsetof(SMU74_Firmware_Header, DpmTable),
2480                         &tmp, SMC_RAM_END);
2481
2482         if (0 == result)
2483                 smu_data->smu7_data.dpm_table_start = tmp;
2484
2485         error |= (0 != result);
2486
2487         result = smu7_read_smc_sram_dword(hwmgr,
2488                         SMU7_FIRMWARE_HEADER_LOCATION +
2489                         offsetof(SMU74_Firmware_Header, SoftRegisters),
2490                         &tmp, SMC_RAM_END);
2491
2492         if (!result) {
2493                 data->soft_regs_start = tmp;
2494                 smu_data->smu7_data.soft_regs_start = tmp;
2495         }
2496
2497         error |= (0 != result);
2498
2499         result = smu7_read_smc_sram_dword(hwmgr,
2500                         SMU7_FIRMWARE_HEADER_LOCATION +
2501                         offsetof(SMU74_Firmware_Header, mcRegisterTable),
2502                         &tmp, SMC_RAM_END);
2503
2504         if (!result)
2505                 smu_data->smu7_data.mc_reg_table_start = tmp;
2506
2507         result = smu7_read_smc_sram_dword(hwmgr,
2508                         SMU7_FIRMWARE_HEADER_LOCATION +
2509                         offsetof(SMU74_Firmware_Header, FanTable),
2510                         &tmp, SMC_RAM_END);
2511
2512         if (!result)
2513                 smu_data->smu7_data.fan_table_start = tmp;
2514
2515         error |= (0 != result);
2516
2517         result = smu7_read_smc_sram_dword(hwmgr,
2518                         SMU7_FIRMWARE_HEADER_LOCATION +
2519                         offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
2520                         &tmp, SMC_RAM_END);
2521
2522         if (!result)
2523                 smu_data->smu7_data.arb_table_start = tmp;
2524
2525         error |= (0 != result);
2526
2527         result = smu7_read_smc_sram_dword(hwmgr,
2528                         SMU7_FIRMWARE_HEADER_LOCATION +
2529                         offsetof(SMU74_Firmware_Header, Version),
2530                         &tmp, SMC_RAM_END);
2531
2532         if (!result)
2533                 hwmgr->microcode_version_info.SMC = tmp;
2534
2535         error |= (0 != result);
2536
2537         return error ? -1 : 0;
2538 }
2539
2540 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
2541 {
2542         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
2543                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
2544                         ? true : false;
2545 }
2546
2547 static int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
2548                 struct amd_pp_profile *request)
2549 {
2550         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
2551                         (hwmgr->smu_backend);
2552         struct SMU74_Discrete_GraphicsLevel *levels =
2553                         smu_data->smc_state_table.GraphicsLevel;
2554         uint32_t array = smu_data->smu7_data.dpm_table_start +
2555                         offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
2556         uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
2557                         SMU74_MAX_LEVELS_GRAPHICS;
2558         uint32_t i;
2559
2560         for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
2561                 levels[i].ActivityLevel =
2562                                 cpu_to_be16(request->activity_threshold);
2563                 levels[i].EnabledForActivity = 1;
2564                 levels[i].UpHyst = request->up_hyst;
2565                 levels[i].DownHyst = request->down_hyst;
2566         }
2567
2568         return smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
2569                                 array_size, SMC_RAM_END);
2570 }
2571
2572 const struct pp_smumgr_func polaris10_smu_funcs = {
2573         .smu_init = polaris10_smu_init,
2574         .smu_fini = smu7_smu_fini,
2575         .start_smu = polaris10_start_smu,
2576         .check_fw_load_finish = smu7_check_fw_load_finish,
2577         .request_smu_load_fw = smu7_reload_firmware,
2578         .request_smu_load_specific_fw = NULL,
2579         .send_msg_to_smc = smu7_send_msg_to_smc,
2580         .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
2581         .download_pptable_settings = NULL,
2582         .upload_pptable_settings = NULL,
2583         .update_smc_table = polaris10_update_smc_table,
2584         .get_offsetof = polaris10_get_offsetof,
2585         .process_firmware_header = polaris10_process_firmware_header,
2586         .init_smc_table = polaris10_init_smc_table,
2587         .update_sclk_threshold = polaris10_update_sclk_threshold,
2588         .thermal_avfs_enable = polaris10_thermal_avfs_enable,
2589         .thermal_setup_fan_table = polaris10_thermal_setup_fan_table,
2590         .populate_all_graphic_levels = polaris10_populate_all_graphic_levels,
2591         .populate_all_memory_levels = polaris10_populate_all_memory_levels,
2592         .get_mac_definition = polaris10_get_mac_definition,
2593         .is_dpm_running = polaris10_is_dpm_running,
2594         .populate_requested_graphic_levels = polaris10_populate_requested_graphic_levels,
2595         .is_hw_avfs_present = polaris10_is_hw_avfs_present,
2596 };