2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/slab.h>
31 #include "amd_powerplay.h"
32 #include "hardwaremanager.h"
33 #include "ppatomfwctrl.h"
34 #include "atomfirmware.h"
35 #include "cgs_common.h"
36 #include "vega10_powertune.h"
38 #include "smu9_driver_if.h"
39 #include "vega10_inc.h"
40 #include "soc15_common.h"
41 #include "pppcielanes.h"
42 #include "vega10_hwmgr.h"
43 #include "vega10_smumgr.h"
44 #include "vega10_processpptables.h"
45 #include "vega10_pptable.h"
46 #include "vega10_thermal.h"
48 #include "amd_pcie_helpers.h"
49 #include "ppinterrupt.h"
50 #include "pp_overdriver.h"
51 #include "pp_thermal.h"
52 #include "vega10_baco.h"
54 #include "smuio/smuio_9_0_offset.h"
55 #include "smuio/smuio_9_0_sh_mask.h"
57 #define HBM_MEMORY_CHANNEL_WIDTH 128
59 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
61 #define mmDF_CS_AON0_DramBaseAddress0 0x0044
62 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
64 //DF_CS_AON0_DramBaseAddress0
65 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
66 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
67 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
68 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
69 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
70 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
71 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
72 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
73 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
74 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
91 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
93 struct vega10_power_state *cast_phw_vega10_power_state(
94 struct pp_hw_power_state *hw_ps)
96 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
97 "Invalid Powerstate Type!",
100 return (struct vega10_power_state *)hw_ps;
103 const struct vega10_power_state *cast_const_phw_vega10_power_state(
104 const struct pp_hw_power_state *hw_ps)
106 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
107 "Invalid Powerstate Type!",
110 return (const struct vega10_power_state *)hw_ps;
113 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
115 struct vega10_hwmgr *data = hwmgr->backend;
117 data->registry_data.sclk_dpm_key_disabled =
118 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
119 data->registry_data.socclk_dpm_key_disabled =
120 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
121 data->registry_data.mclk_dpm_key_disabled =
122 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
123 data->registry_data.pcie_dpm_key_disabled =
124 hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
126 data->registry_data.dcefclk_dpm_key_disabled =
127 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
129 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
130 data->registry_data.power_containment_support = 1;
131 data->registry_data.enable_pkg_pwr_tracking_feature = 1;
132 data->registry_data.enable_tdc_limit_feature = 1;
135 data->registry_data.clock_stretcher_support =
136 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
138 data->registry_data.ulv_support =
139 hwmgr->feature_mask & PP_ULV_MASK ? true : false;
141 data->registry_data.sclk_deep_sleep_support =
142 hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
144 data->registry_data.disable_water_mark = 0;
146 data->registry_data.fan_control_support = 1;
147 data->registry_data.thermal_support = 1;
148 data->registry_data.fw_ctf_enabled = 1;
150 data->registry_data.avfs_support =
151 hwmgr->feature_mask & PP_AVFS_MASK ? true : false;
152 data->registry_data.led_dpm_enabled = 1;
154 data->registry_data.vr0hot_enabled = 1;
155 data->registry_data.vr1hot_enabled = 1;
156 data->registry_data.regulator_hot_gpio_support = 1;
158 data->registry_data.didt_support = 1;
159 if (data->registry_data.didt_support) {
160 data->registry_data.didt_mode = 6;
161 data->registry_data.sq_ramping_support = 1;
162 data->registry_data.db_ramping_support = 0;
163 data->registry_data.td_ramping_support = 0;
164 data->registry_data.tcp_ramping_support = 0;
165 data->registry_data.dbr_ramping_support = 0;
166 data->registry_data.edc_didt_support = 1;
167 data->registry_data.gc_didt_support = 0;
168 data->registry_data.psm_didt_support = 0;
171 data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT;
172 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
173 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
174 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
175 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
176 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
177 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
178 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
179 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
180 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
181 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
182 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
183 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
185 data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT;
186 data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT;
187 data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT;
188 data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT;
191 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
193 struct vega10_hwmgr *data = hwmgr->backend;
194 struct phm_ppt_v2_information *table_info =
195 (struct phm_ppt_v2_information *)hwmgr->pptable;
196 struct amdgpu_device *adev = hwmgr->adev;
198 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
199 PHM_PlatformCaps_SclkDeepSleep);
201 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
202 PHM_PlatformCaps_DynamicPatchPowerState);
204 if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE)
205 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
206 PHM_PlatformCaps_ControlVDDCI);
208 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
209 PHM_PlatformCaps_EnableSMU7ThermalManagement);
211 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
212 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
213 PHM_PlatformCaps_UVDPowerGating);
215 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
216 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
217 PHM_PlatformCaps_VCEPowerGating);
219 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
220 PHM_PlatformCaps_UnTabledHardwareInterface);
222 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
223 PHM_PlatformCaps_FanSpeedInTableIsRPM);
225 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
226 PHM_PlatformCaps_ODFuzzyFanControlSupport);
228 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
229 PHM_PlatformCaps_DynamicPowerManagement);
231 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
232 PHM_PlatformCaps_SMC);
234 /* power tune caps */
235 /* assume disabled */
236 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
237 PHM_PlatformCaps_PowerContainment);
238 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
239 PHM_PlatformCaps_DiDtSupport);
240 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
241 PHM_PlatformCaps_SQRamping);
242 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
243 PHM_PlatformCaps_DBRamping);
244 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
245 PHM_PlatformCaps_TDRamping);
246 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
247 PHM_PlatformCaps_TCPRamping);
248 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
249 PHM_PlatformCaps_DBRRamping);
250 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
251 PHM_PlatformCaps_DiDtEDCEnable);
252 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
253 PHM_PlatformCaps_GCEDC);
254 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
255 PHM_PlatformCaps_PSM);
257 if (data->registry_data.didt_support) {
258 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
259 if (data->registry_data.sq_ramping_support)
260 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
261 if (data->registry_data.db_ramping_support)
262 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
263 if (data->registry_data.td_ramping_support)
264 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
265 if (data->registry_data.tcp_ramping_support)
266 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
267 if (data->registry_data.dbr_ramping_support)
268 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
269 if (data->registry_data.edc_didt_support)
270 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
271 if (data->registry_data.gc_didt_support)
272 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
273 if (data->registry_data.psm_didt_support)
274 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
277 if (data->registry_data.power_containment_support)
278 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
279 PHM_PlatformCaps_PowerContainment);
280 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
281 PHM_PlatformCaps_CAC);
283 if (table_info->tdp_table->usClockStretchAmount &&
284 data->registry_data.clock_stretcher_support)
285 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
286 PHM_PlatformCaps_ClockStretcher);
288 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
289 PHM_PlatformCaps_RegulatorHot);
290 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
291 PHM_PlatformCaps_AutomaticDCTransition);
293 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
294 PHM_PlatformCaps_UVDDPM);
295 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
296 PHM_PlatformCaps_VCEDPM);
301 static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
303 struct vega10_hwmgr *data = hwmgr->backend;
304 struct phm_ppt_v2_information *table_info =
305 (struct phm_ppt_v2_information *)(hwmgr->pptable);
306 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
307 struct vega10_odn_vddc_lookup_table *od_lookup_table;
308 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
309 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table[3];
310 struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3];
311 struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
315 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
317 data->odn_dpm_table.max_vddc = avfs_params.ulMaxVddc;
318 data->odn_dpm_table.min_vddc = avfs_params.ulMinVddc;
321 od_lookup_table = &odn_table->vddc_lookup_table;
322 vddc_lookup_table = table_info->vddc_lookup_table;
324 for (i = 0; i < vddc_lookup_table->count; i++)
325 od_lookup_table->entries[i].us_vdd = vddc_lookup_table->entries[i].us_vdd;
327 od_lookup_table->count = vddc_lookup_table->count;
329 dep_table[0] = table_info->vdd_dep_on_sclk;
330 dep_table[1] = table_info->vdd_dep_on_mclk;
331 dep_table[2] = table_info->vdd_dep_on_socclk;
332 od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk;
333 od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk;
334 od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk;
336 for (i = 0; i < 3; i++)
337 smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]);
339 if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000)
340 odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc;
341 if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000)
342 odn_table->min_vddc = dep_table[0]->entries[0].vddc;
344 i = od_table[2]->count - 1;
345 od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ?
346 hwmgr->platform_descriptor.overdriveLimit.memoryClock :
347 od_table[2]->entries[i].clk;
348 od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ?
349 odn_table->max_vddc :
350 od_table[2]->entries[i].vddc;
355 static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
357 struct vega10_hwmgr *data = hwmgr->backend;
359 uint32_t sub_vendor_id, hw_revision;
360 uint32_t top32, bottom32;
361 struct amdgpu_device *adev = hwmgr->adev;
363 vega10_initialize_power_tune_defaults(hwmgr);
365 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
366 data->smu_features[i].smu_feature_id = 0xffff;
367 data->smu_features[i].smu_feature_bitmap = 1 << i;
368 data->smu_features[i].enabled = false;
369 data->smu_features[i].supported = false;
372 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
373 FEATURE_DPM_PREFETCHER_BIT;
374 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
375 FEATURE_DPM_GFXCLK_BIT;
376 data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
377 FEATURE_DPM_UCLK_BIT;
378 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
379 FEATURE_DPM_SOCCLK_BIT;
380 data->smu_features[GNLD_DPM_UVD].smu_feature_id =
382 data->smu_features[GNLD_DPM_VCE].smu_feature_id =
384 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
385 FEATURE_DPM_MP0CLK_BIT;
386 data->smu_features[GNLD_DPM_LINK].smu_feature_id =
387 FEATURE_DPM_LINK_BIT;
388 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
389 FEATURE_DPM_DCEFCLK_BIT;
390 data->smu_features[GNLD_ULV].smu_feature_id =
392 data->smu_features[GNLD_AVFS].smu_feature_id =
394 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
395 FEATURE_DS_GFXCLK_BIT;
396 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
397 FEATURE_DS_SOCCLK_BIT;
398 data->smu_features[GNLD_DS_LCLK].smu_feature_id =
400 data->smu_features[GNLD_PPT].smu_feature_id =
402 data->smu_features[GNLD_TDC].smu_feature_id =
404 data->smu_features[GNLD_THERMAL].smu_feature_id =
406 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
407 FEATURE_GFX_PER_CU_CG_BIT;
408 data->smu_features[GNLD_RM].smu_feature_id =
410 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
411 FEATURE_DS_DCEFCLK_BIT;
412 data->smu_features[GNLD_ACDC].smu_feature_id =
414 data->smu_features[GNLD_VR0HOT].smu_feature_id =
416 data->smu_features[GNLD_VR1HOT].smu_feature_id =
418 data->smu_features[GNLD_FW_CTF].smu_feature_id =
420 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
421 FEATURE_LED_DISPLAY_BIT;
422 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
423 FEATURE_FAN_CONTROL_BIT;
424 data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
425 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
426 data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT;
428 if (!data->registry_data.prefetcher_dpm_key_disabled)
429 data->smu_features[GNLD_DPM_PREFETCHER].supported = true;
431 if (!data->registry_data.sclk_dpm_key_disabled)
432 data->smu_features[GNLD_DPM_GFXCLK].supported = true;
434 if (!data->registry_data.mclk_dpm_key_disabled)
435 data->smu_features[GNLD_DPM_UCLK].supported = true;
437 if (!data->registry_data.socclk_dpm_key_disabled)
438 data->smu_features[GNLD_DPM_SOCCLK].supported = true;
440 if (PP_CAP(PHM_PlatformCaps_UVDDPM))
441 data->smu_features[GNLD_DPM_UVD].supported = true;
443 if (PP_CAP(PHM_PlatformCaps_VCEDPM))
444 data->smu_features[GNLD_DPM_VCE].supported = true;
446 if (!data->registry_data.pcie_dpm_key_disabled)
447 data->smu_features[GNLD_DPM_LINK].supported = true;
449 if (!data->registry_data.dcefclk_dpm_key_disabled)
450 data->smu_features[GNLD_DPM_DCEFCLK].supported = true;
452 if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) &&
453 data->registry_data.sclk_deep_sleep_support) {
454 data->smu_features[GNLD_DS_GFXCLK].supported = true;
455 data->smu_features[GNLD_DS_SOCCLK].supported = true;
456 data->smu_features[GNLD_DS_LCLK].supported = true;
457 data->smu_features[GNLD_DS_DCEFCLK].supported = true;
460 if (data->registry_data.enable_pkg_pwr_tracking_feature)
461 data->smu_features[GNLD_PPT].supported = true;
463 if (data->registry_data.enable_tdc_limit_feature)
464 data->smu_features[GNLD_TDC].supported = true;
466 if (data->registry_data.thermal_support)
467 data->smu_features[GNLD_THERMAL].supported = true;
469 if (data->registry_data.fan_control_support)
470 data->smu_features[GNLD_FAN_CONTROL].supported = true;
472 if (data->registry_data.fw_ctf_enabled)
473 data->smu_features[GNLD_FW_CTF].supported = true;
475 if (data->registry_data.avfs_support)
476 data->smu_features[GNLD_AVFS].supported = true;
478 if (data->registry_data.led_dpm_enabled)
479 data->smu_features[GNLD_LED_DISPLAY].supported = true;
481 if (data->registry_data.vr1hot_enabled)
482 data->smu_features[GNLD_VR1HOT].supported = true;
484 if (data->registry_data.vr0hot_enabled)
485 data->smu_features[GNLD_VR0HOT].supported = true;
487 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
488 hwmgr->smu_version = smum_get_argument(hwmgr);
489 /* ACG firmware has major version 5 */
490 if ((hwmgr->smu_version & 0xff000000) == 0x5000000)
491 data->smu_features[GNLD_ACG].supported = true;
492 if (data->registry_data.didt_support)
493 data->smu_features[GNLD_DIDT].supported = true;
495 hw_revision = adev->pdev->revision;
496 sub_vendor_id = adev->pdev->subsystem_vendor;
498 if ((hwmgr->chip_id == 0x6862 ||
499 hwmgr->chip_id == 0x6861 ||
500 hwmgr->chip_id == 0x6868) &&
501 (hw_revision == 0) &&
502 (sub_vendor_id != 0x1002))
503 data->smu_features[GNLD_PCC_LIMIT].supported = true;
505 /* Get the SN to turn into a Unique ID */
506 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
507 top32 = smum_get_argument(hwmgr);
508 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
509 bottom32 = smum_get_argument(hwmgr);
511 adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
514 #ifdef PPLIB_VEGA10_EVV_SUPPORT
515 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
516 phm_ppt_v1_voltage_lookup_table *lookup_table,
517 uint16_t virtual_voltage_id, int32_t *socclk)
521 struct phm_ppt_v2_information *table_info =
522 (struct phm_ppt_v2_information *)(hwmgr->pptable);
524 PP_ASSERT_WITH_CODE(lookup_table->count != 0,
525 "Lookup table is empty",
528 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */
529 for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
530 voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd;
531 if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
535 PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count,
536 "Can't find requested voltage id in vdd_dep_on_socclk table!",
539 *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk;
544 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01
546 * Get Leakage VDDC based on leakage ID.
548 * @param hwmgr the address of the powerplay hardware manager.
551 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
553 struct vega10_hwmgr *data = hwmgr->backend;
558 struct phm_ppt_v2_information *table_info =
559 (struct phm_ppt_v2_information *)hwmgr->pptable;
560 struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table =
561 table_info->vdd_dep_on_socclk;
564 for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) {
565 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
567 if (!vega10_get_socclk_for_voltage_evv(hwmgr,
568 table_info->vddc_lookup_table, vv_id, &sclk)) {
569 if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) {
570 for (j = 1; j < socclk_table->count; j++) {
571 if (socclk_table->entries[j].clk == sclk &&
572 socclk_table->entries[j].cks_enable == 0) {
579 PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
580 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
581 "Error retrieving EVV voltage value!",
585 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
586 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
587 "Invalid VDDC value", result = -EINVAL;);
589 /* the voltage should not be zero nor equal to leakage ID */
590 if (vddc != 0 && vddc != vv_id) {
591 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
592 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
593 data->vddc_leakage.count++;
602 * Change virtual leakage voltage to actual value.
604 * @param hwmgr the address of the powerplay hardware manager.
605 * @param pointer to changing voltage
606 * @param pointer to leakage table
608 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
609 uint16_t *voltage, struct vega10_leakage_voltage *leakage_table)
613 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
614 for (index = 0; index < leakage_table->count; index++) {
615 /* if this voltage matches a leakage voltage ID */
616 /* patch with actual leakage voltage */
617 if (leakage_table->leakage_id[index] == *voltage) {
618 *voltage = leakage_table->actual_voltage[index];
623 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
624 pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
628 * Patch voltage lookup table by EVV leakages.
630 * @param hwmgr the address of the powerplay hardware manager.
631 * @param pointer to voltage lookup table
632 * @param pointer to leakage table
635 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
636 phm_ppt_v1_voltage_lookup_table *lookup_table,
637 struct vega10_leakage_voltage *leakage_table)
641 for (i = 0; i < lookup_table->count; i++)
642 vega10_patch_with_vdd_leakage(hwmgr,
643 &lookup_table->entries[i].us_vdd, leakage_table);
648 static int vega10_patch_clock_voltage_limits_with_vddc_leakage(
649 struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table,
652 vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
658 static int vega10_patch_voltage_dependency_tables_with_lookup_table(
659 struct pp_hwmgr *hwmgr)
661 uint8_t entry_id, voltage_id;
663 struct phm_ppt_v2_information *table_info =
664 (struct phm_ppt_v2_information *)(hwmgr->pptable);
665 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
666 table_info->mm_dep_table;
667 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
668 table_info->vdd_dep_on_mclk;
670 for (i = 0; i < 6; i++) {
671 struct phm_ppt_v1_clock_voltage_dependency_table *vdt;
673 case 0: vdt = table_info->vdd_dep_on_socclk; break;
674 case 1: vdt = table_info->vdd_dep_on_sclk; break;
675 case 2: vdt = table_info->vdd_dep_on_dcefclk; break;
676 case 3: vdt = table_info->vdd_dep_on_pixclk; break;
677 case 4: vdt = table_info->vdd_dep_on_dispclk; break;
678 case 5: vdt = table_info->vdd_dep_on_phyclk; break;
681 for (entry_id = 0; entry_id < vdt->count; entry_id++) {
682 voltage_id = vdt->entries[entry_id].vddInd;
683 vdt->entries[entry_id].vddc =
684 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
688 for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
689 voltage_id = mm_table->entries[entry_id].vddcInd;
690 mm_table->entries[entry_id].vddc =
691 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
694 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
695 voltage_id = mclk_table->entries[entry_id].vddInd;
696 mclk_table->entries[entry_id].vddc =
697 table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
698 voltage_id = mclk_table->entries[entry_id].vddciInd;
699 mclk_table->entries[entry_id].vddci =
700 table_info->vddci_lookup_table->entries[voltage_id].us_vdd;
701 voltage_id = mclk_table->entries[entry_id].mvddInd;
702 mclk_table->entries[entry_id].mvdd =
703 table_info->vddmem_lookup_table->entries[voltage_id].us_vdd;
711 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
712 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
714 uint32_t table_size, i, j;
716 PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,
717 "Lookup table is empty", return -EINVAL);
719 table_size = lookup_table->count;
721 /* Sorting voltages */
722 for (i = 0; i < table_size - 1; i++) {
723 for (j = i + 1; j > 0; j--) {
724 if (lookup_table->entries[j].us_vdd <
725 lookup_table->entries[j - 1].us_vdd) {
726 swap(lookup_table->entries[j - 1],
727 lookup_table->entries[j]);
735 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
739 struct phm_ppt_v2_information *table_info =
740 (struct phm_ppt_v2_information *)(hwmgr->pptable);
741 #ifdef PPLIB_VEGA10_EVV_SUPPORT
742 struct vega10_hwmgr *data = hwmgr->backend;
744 tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,
745 table_info->vddc_lookup_table, &(data->vddc_leakage));
749 tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
750 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
755 tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
759 tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
766 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
768 struct phm_ppt_v2_information *table_info =
769 (struct phm_ppt_v2_information *)(hwmgr->pptable);
770 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
771 table_info->vdd_dep_on_socclk;
772 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
773 table_info->vdd_dep_on_mclk;
775 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
776 "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL);
777 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
778 "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL);
780 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
781 "VDD dependency on MCLK table is missing. This table is mandatory", return -EINVAL);
782 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
783 "VDD dependency on MCLK table is empty. This table is mandatory", return -EINVAL);
785 table_info->max_clock_voltage_on_ac.sclk =
786 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
787 table_info->max_clock_voltage_on_ac.mclk =
788 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
789 table_info->max_clock_voltage_on_ac.vddc =
790 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
791 table_info->max_clock_voltage_on_ac.vddci =
792 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
794 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
795 table_info->max_clock_voltage_on_ac.sclk;
796 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
797 table_info->max_clock_voltage_on_ac.mclk;
798 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
799 table_info->max_clock_voltage_on_ac.vddc;
800 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
801 table_info->max_clock_voltage_on_ac.vddci;
806 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
808 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
809 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
811 kfree(hwmgr->backend);
812 hwmgr->backend = NULL;
817 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
820 struct vega10_hwmgr *data;
821 uint32_t config_telemetry = 0;
822 struct pp_atomfwctrl_voltage_table vol_table;
823 struct amdgpu_device *adev = hwmgr->adev;
825 data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
829 hwmgr->backend = data;
831 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
832 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
833 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
835 vega10_set_default_registry_data(hwmgr);
836 data->disable_dpm_mask = 0xff;
838 /* need to set voltage control types before EVV patching */
839 data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE;
840 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE;
841 data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE;
844 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
845 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
846 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
847 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2,
849 config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) |
850 (vol_table.telemetry_offset & 0xff);
851 data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
854 kfree(hwmgr->backend);
855 hwmgr->backend = NULL;
856 PP_ASSERT_WITH_CODE(false,
857 "VDDCR_SOC is not SVID2!",
862 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
863 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) {
864 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
865 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2,
868 ((vol_table.telemetry_slope << 24) & 0xff000000) |
869 ((vol_table.telemetry_offset << 16) & 0xff0000);
870 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
875 if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) {
876 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
877 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
878 data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO;
881 data->config_telemetry = config_telemetry;
883 vega10_set_features_platform_caps(hwmgr);
885 vega10_init_dpm_defaults(hwmgr);
887 #ifdef PPLIB_VEGA10_EVV_SUPPORT
888 /* Get leakage voltage based on leakage ID. */
889 PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr),
890 "Get EVV Voltage Failed. Abort Driver loading!",
894 /* Patch our voltage dependency table with actual leakage voltage
895 * We need to perform leakage translation before it's used by other functions
897 vega10_complete_dependency_tables(hwmgr);
899 /* Parse pptable data read from VBIOS */
900 vega10_set_private_data_based_on_pptable(hwmgr);
902 data->is_tlu_enabled = false;
904 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
905 VEGA10_MAX_HARDWARE_POWERLEVELS;
906 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
907 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
909 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
910 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
911 hwmgr->platform_descriptor.clockStep.engineClock = 500;
912 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
914 data->total_active_cus = adev->gfx.cu_info.number;
915 /* Setup default Overdrive Fan control settings */
916 data->odn_fan_table.target_fan_speed =
917 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
918 data->odn_fan_table.target_temperature =
919 hwmgr->thermal_controller.
920 advanceFanControlParameters.ucTargetTemperature;
921 data->odn_fan_table.min_performance_clock =
922 hwmgr->thermal_controller.advanceFanControlParameters.
923 ulMinFanSCLKAcousticLimit;
924 data->odn_fan_table.min_fan_limit =
925 hwmgr->thermal_controller.
926 advanceFanControlParameters.usFanPWMMinLimit *
927 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
929 data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) &
930 DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
931 DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
932 PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
933 "Mem Channel Index Exceeded maximum!",
939 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
941 struct vega10_hwmgr *data = hwmgr->backend;
943 data->low_sclk_interrupt_threshold = 0;
948 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
950 struct vega10_hwmgr *data = hwmgr->backend;
951 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
953 struct pp_atomfwctrl_voltage_table table;
959 ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM,
960 VOLTAGE_OBJ_GPIO_LUT, &table);
963 tmp = table.mask_low;
964 for (i = 0, j = 0; i < 32; i++) {
966 mask |= (uint32_t)(i << (8 * j));
974 pp_table->LedPin0 = (uint8_t)(mask & 0xff);
975 pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff);
976 pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff);
980 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)
982 PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr),
983 "Failed to init sclk threshold!",
986 PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr),
987 "Failed to set up led dpm config!",
990 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_NumOfDisplays, 0);
996 * Remove repeated voltage values and create table with unique values.
998 * @param hwmgr the address of the powerplay hardware manager.
999 * @param vol_table the pointer to changing voltage table
1000 * @return 0 in success
1003 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr,
1004 struct pp_atomfwctrl_voltage_table *vol_table)
1009 struct pp_atomfwctrl_voltage_table *table;
1011 PP_ASSERT_WITH_CODE(vol_table,
1012 "Voltage Table empty.", return -EINVAL);
1013 table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table),
1019 table->mask_low = vol_table->mask_low;
1020 table->phase_delay = vol_table->phase_delay;
1022 for (i = 0; i < vol_table->count; i++) {
1023 vvalue = vol_table->entries[i].value;
1026 for (j = 0; j < table->count; j++) {
1027 if (vvalue == table->entries[j].value) {
1034 table->entries[table->count].value = vvalue;
1035 table->entries[table->count].smio_low =
1036 vol_table->entries[i].smio_low;
1041 memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table));
1047 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
1048 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1049 struct pp_atomfwctrl_voltage_table *vol_table)
1053 PP_ASSERT_WITH_CODE(dep_table->count,
1054 "Voltage Dependency Table empty.",
1057 vol_table->mask_low = 0;
1058 vol_table->phase_delay = 0;
1059 vol_table->count = dep_table->count;
1061 for (i = 0; i < vol_table->count; i++) {
1062 vol_table->entries[i].value = dep_table->entries[i].mvdd;
1063 vol_table->entries[i].smio_low = 0;
1066 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr,
1068 "Failed to trim MVDD Table!",
1074 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr,
1075 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1076 struct pp_atomfwctrl_voltage_table *vol_table)
1080 PP_ASSERT_WITH_CODE(dep_table->count,
1081 "Voltage Dependency Table empty.",
1084 vol_table->mask_low = 0;
1085 vol_table->phase_delay = 0;
1086 vol_table->count = dep_table->count;
1088 for (i = 0; i < dep_table->count; i++) {
1089 vol_table->entries[i].value = dep_table->entries[i].vddci;
1090 vol_table->entries[i].smio_low = 0;
1093 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),
1094 "Failed to trim VDDCI table.",
1100 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr,
1101 phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1102 struct pp_atomfwctrl_voltage_table *vol_table)
1106 PP_ASSERT_WITH_CODE(dep_table->count,
1107 "Voltage Dependency Table empty.",
1110 vol_table->mask_low = 0;
1111 vol_table->phase_delay = 0;
1112 vol_table->count = dep_table->count;
1114 for (i = 0; i < vol_table->count; i++) {
1115 vol_table->entries[i].value = dep_table->entries[i].vddc;
1116 vol_table->entries[i].smio_low = 0;
1122 /* ---- Voltage Tables ----
1123 * If the voltage table would be bigger than
1124 * what will fit into the state table on
1125 * the SMC keep only the higher entries.
1127 static void vega10_trim_voltage_table_to_fit_state_table(
1128 struct pp_hwmgr *hwmgr,
1129 uint32_t max_vol_steps,
1130 struct pp_atomfwctrl_voltage_table *vol_table)
1132 unsigned int i, diff;
1134 if (vol_table->count <= max_vol_steps)
1137 diff = vol_table->count - max_vol_steps;
1139 for (i = 0; i < max_vol_steps; i++)
1140 vol_table->entries[i] = vol_table->entries[i + diff];
1142 vol_table->count = max_vol_steps;
1146 * Create Voltage Tables.
1148 * @param hwmgr the address of the powerplay hardware manager.
1151 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1153 struct vega10_hwmgr *data = hwmgr->backend;
1154 struct phm_ppt_v2_information *table_info =
1155 (struct phm_ppt_v2_information *)hwmgr->pptable;
1158 if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1159 data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1160 result = vega10_get_mvdd_voltage_table(hwmgr,
1161 table_info->vdd_dep_on_mclk,
1162 &(data->mvdd_voltage_table));
1163 PP_ASSERT_WITH_CODE(!result,
1164 "Failed to retrieve MVDDC table!",
1168 if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1169 result = vega10_get_vddci_voltage_table(hwmgr,
1170 table_info->vdd_dep_on_mclk,
1171 &(data->vddci_voltage_table));
1172 PP_ASSERT_WITH_CODE(!result,
1173 "Failed to retrieve VDDCI_MEM table!",
1177 if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1178 data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1179 result = vega10_get_vdd_voltage_table(hwmgr,
1180 table_info->vdd_dep_on_sclk,
1181 &(data->vddc_voltage_table));
1182 PP_ASSERT_WITH_CODE(!result,
1183 "Failed to retrieve VDDCR_SOC table!",
1187 PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16,
1188 "Too many voltage values for VDDC. Trimming to fit state table.",
1189 vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1190 16, &(data->vddc_voltage_table)));
1192 PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16,
1193 "Too many voltage values for VDDCI. Trimming to fit state table.",
1194 vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1195 16, &(data->vddci_voltage_table)));
1197 PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16,
1198 "Too many voltage values for MVDD. Trimming to fit state table.",
1199 vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1200 16, &(data->mvdd_voltage_table)));
1207 * @fn vega10_init_dpm_state
1208 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
1210 * @param dpm_state - the address of the DPM Table to initiailize.
1213 static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state)
1215 dpm_state->soft_min_level = 0xff;
1216 dpm_state->soft_max_level = 0xff;
1217 dpm_state->hard_min_level = 0xff;
1218 dpm_state->hard_max_level = 0xff;
1221 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,
1222 struct vega10_single_dpm_table *dpm_table,
1223 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
1227 dpm_table->count = 0;
1229 for (i = 0; i < dep_table->count; i++) {
1230 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <=
1231 dep_table->entries[i].clk) {
1232 dpm_table->dpm_levels[dpm_table->count].value =
1233 dep_table->entries[i].clk;
1234 dpm_table->dpm_levels[dpm_table->count].enabled = true;
1239 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1241 struct vega10_hwmgr *data = hwmgr->backend;
1242 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
1243 struct phm_ppt_v2_information *table_info =
1244 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1245 struct phm_ppt_v1_pcie_table *bios_pcie_table =
1246 table_info->pcie_table;
1249 PP_ASSERT_WITH_CODE(bios_pcie_table->count,
1250 "Incorrect number of PCIE States from VBIOS!",
1253 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1254 if (data->registry_data.pcieSpeedOverride)
1255 pcie_table->pcie_gen[i] =
1256 data->registry_data.pcieSpeedOverride;
1258 pcie_table->pcie_gen[i] =
1259 bios_pcie_table->entries[i].gen_speed;
1261 if (data->registry_data.pcieLaneOverride)
1262 pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1263 data->registry_data.pcieLaneOverride);
1265 pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1266 bios_pcie_table->entries[i].lane_width);
1267 if (data->registry_data.pcieClockOverride)
1268 pcie_table->lclk[i] =
1269 data->registry_data.pcieClockOverride;
1271 pcie_table->lclk[i] =
1272 bios_pcie_table->entries[i].pcie_sclk;
1275 pcie_table->count = NUM_LINK_LEVELS;
1281 * This function is to initialize all DPM state tables
1282 * for SMU based on the dependency table.
1283 * Dynamic state patching function will then trim these
1284 * state tables to the allowed range based
1285 * on the power policy or external client requests,
1286 * such as UVD request, etc.
1288 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1290 struct vega10_hwmgr *data = hwmgr->backend;
1291 struct phm_ppt_v2_information *table_info =
1292 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1293 struct vega10_single_dpm_table *dpm_table;
1296 struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table =
1297 table_info->vdd_dep_on_socclk;
1298 struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table =
1299 table_info->vdd_dep_on_sclk;
1300 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1301 table_info->vdd_dep_on_mclk;
1302 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table =
1303 table_info->mm_dep_table;
1304 struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table =
1305 table_info->vdd_dep_on_dcefclk;
1306 struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table =
1307 table_info->vdd_dep_on_pixclk;
1308 struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table =
1309 table_info->vdd_dep_on_dispclk;
1310 struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table =
1311 table_info->vdd_dep_on_phyclk;
1313 PP_ASSERT_WITH_CODE(dep_soc_table,
1314 "SOCCLK dependency table is missing. This table is mandatory",
1316 PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1,
1317 "SOCCLK dependency table is empty. This table is mandatory",
1320 PP_ASSERT_WITH_CODE(dep_gfx_table,
1321 "GFXCLK dependency table is missing. This table is mandatory",
1323 PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1,
1324 "GFXCLK dependency table is empty. This table is mandatory",
1327 PP_ASSERT_WITH_CODE(dep_mclk_table,
1328 "MCLK dependency table is missing. This table is mandatory",
1330 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1331 "MCLK dependency table has to have is missing. This table is mandatory",
1334 /* Initialize Sclk DPM table based on allow Sclk values */
1335 dpm_table = &(data->dpm_table.soc_table);
1336 vega10_setup_default_single_dpm_table(hwmgr,
1340 vega10_init_dpm_state(&(dpm_table->dpm_state));
1342 dpm_table = &(data->dpm_table.gfx_table);
1343 vega10_setup_default_single_dpm_table(hwmgr,
1346 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
1347 hwmgr->platform_descriptor.overdriveLimit.engineClock =
1348 dpm_table->dpm_levels[dpm_table->count-1].value;
1349 vega10_init_dpm_state(&(dpm_table->dpm_state));
1351 /* Initialize Mclk DPM table based on allow Mclk values */
1352 data->dpm_table.mem_table.count = 0;
1353 dpm_table = &(data->dpm_table.mem_table);
1354 vega10_setup_default_single_dpm_table(hwmgr,
1357 if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
1358 hwmgr->platform_descriptor.overdriveLimit.memoryClock =
1359 dpm_table->dpm_levels[dpm_table->count-1].value;
1360 vega10_init_dpm_state(&(dpm_table->dpm_state));
1362 data->dpm_table.eclk_table.count = 0;
1363 dpm_table = &(data->dpm_table.eclk_table);
1364 for (i = 0; i < dep_mm_table->count; i++) {
1365 if (i == 0 || dpm_table->dpm_levels
1366 [dpm_table->count - 1].value <=
1367 dep_mm_table->entries[i].eclk) {
1368 dpm_table->dpm_levels[dpm_table->count].value =
1369 dep_mm_table->entries[i].eclk;
1370 dpm_table->dpm_levels[dpm_table->count].enabled =
1371 (i == 0) ? true : false;
1375 vega10_init_dpm_state(&(dpm_table->dpm_state));
1377 data->dpm_table.vclk_table.count = 0;
1378 data->dpm_table.dclk_table.count = 0;
1379 dpm_table = &(data->dpm_table.vclk_table);
1380 for (i = 0; i < dep_mm_table->count; i++) {
1381 if (i == 0 || dpm_table->dpm_levels
1382 [dpm_table->count - 1].value <=
1383 dep_mm_table->entries[i].vclk) {
1384 dpm_table->dpm_levels[dpm_table->count].value =
1385 dep_mm_table->entries[i].vclk;
1386 dpm_table->dpm_levels[dpm_table->count].enabled =
1387 (i == 0) ? true : false;
1391 vega10_init_dpm_state(&(dpm_table->dpm_state));
1393 dpm_table = &(data->dpm_table.dclk_table);
1394 for (i = 0; i < dep_mm_table->count; i++) {
1395 if (i == 0 || dpm_table->dpm_levels
1396 [dpm_table->count - 1].value <=
1397 dep_mm_table->entries[i].dclk) {
1398 dpm_table->dpm_levels[dpm_table->count].value =
1399 dep_mm_table->entries[i].dclk;
1400 dpm_table->dpm_levels[dpm_table->count].enabled =
1401 (i == 0) ? true : false;
1405 vega10_init_dpm_state(&(dpm_table->dpm_state));
1407 /* Assume there is no headless Vega10 for now */
1408 dpm_table = &(data->dpm_table.dcef_table);
1409 vega10_setup_default_single_dpm_table(hwmgr,
1413 vega10_init_dpm_state(&(dpm_table->dpm_state));
1415 dpm_table = &(data->dpm_table.pixel_table);
1416 vega10_setup_default_single_dpm_table(hwmgr,
1420 vega10_init_dpm_state(&(dpm_table->dpm_state));
1422 dpm_table = &(data->dpm_table.display_table);
1423 vega10_setup_default_single_dpm_table(hwmgr,
1427 vega10_init_dpm_state(&(dpm_table->dpm_state));
1429 dpm_table = &(data->dpm_table.phy_table);
1430 vega10_setup_default_single_dpm_table(hwmgr,
1434 vega10_init_dpm_state(&(dpm_table->dpm_state));
1436 vega10_setup_default_pcie_table(hwmgr);
1438 /* Zero out the saved copy of the CUSTOM profile
1439 * This will be checked when trying to set the profile
1440 * and will require that new values be passed in
1442 data->custom_profile_mode[0] = 0;
1443 data->custom_profile_mode[1] = 0;
1444 data->custom_profile_mode[2] = 0;
1445 data->custom_profile_mode[3] = 0;
1447 /* save a copy of the default DPM table */
1448 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1449 sizeof(struct vega10_dpm_table));
1455 * @fn vega10_populate_ulv_state
1456 * @brief Function to provide parameters for Utral Low Voltage state to SMC.
1458 * @param hwmgr - the address of the hardware manager.
1461 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
1463 struct vega10_hwmgr *data = hwmgr->backend;
1464 struct phm_ppt_v2_information *table_info =
1465 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1467 data->smc_state_table.pp_table.UlvOffsetVid =
1468 (uint8_t)table_info->us_ulv_voltage_offset;
1470 data->smc_state_table.pp_table.UlvSmnclkDid =
1471 (uint8_t)(table_info->us_ulv_smnclk_did);
1472 data->smc_state_table.pp_table.UlvMp1clkDid =
1473 (uint8_t)(table_info->us_ulv_mp1clk_did);
1474 data->smc_state_table.pp_table.UlvGfxclkBypass =
1475 (uint8_t)(table_info->us_ulv_gfxclk_bypass);
1476 data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 =
1477 (uint8_t)(data->vddc_voltage_table.psi0_enable);
1478 data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 =
1479 (uint8_t)(data->vddc_voltage_table.psi1_enable);
1484 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr,
1485 uint32_t lclock, uint8_t *curr_lclk_did)
1487 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1489 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1491 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1493 "Failed to get LCLK clock settings from VBIOS!",
1496 *curr_lclk_did = dividers.ulDid;
1501 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
1504 struct vega10_hwmgr *data = hwmgr->backend;
1505 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1506 struct vega10_pcie_table *pcie_table =
1507 &(data->dpm_table.pcie_table);
1510 for (i = 0; i < pcie_table->count; i++) {
1511 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i];
1512 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i];
1514 result = vega10_populate_single_lclk_level(hwmgr,
1515 pcie_table->lclk[i], &(pp_table->LclkDid[i]));
1517 pr_info("Populate LClock Level %d Failed!\n", i);
1523 while (i < NUM_LINK_LEVELS) {
1524 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j];
1525 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j];
1527 result = vega10_populate_single_lclk_level(hwmgr,
1528 pcie_table->lclk[j], &(pp_table->LclkDid[i]));
1530 pr_info("Populate LClock Level %d Failed!\n", i);
1540 * Populates single SMC GFXSCLK structure using the provided engine clock
1542 * @param hwmgr the address of the hardware manager
1543 * @param gfx_clock the GFX clock to use to populate the structure.
1544 * @param current_gfxclk_level location in PPTable for the SMC GFXCLK structure.
1547 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
1548 uint32_t gfx_clock, PllSetting_t *current_gfxclk_level,
1551 struct phm_ppt_v2_information *table_info =
1552 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1553 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk;
1554 struct vega10_hwmgr *data = hwmgr->backend;
1555 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1556 uint32_t gfx_max_clock =
1557 hwmgr->platform_descriptor.overdriveLimit.engineClock;
1560 if (hwmgr->od_enabled)
1561 dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1562 &(data->odn_dpm_table.vdd_dep_on_sclk);
1564 dep_on_sclk = table_info->vdd_dep_on_sclk;
1566 PP_ASSERT_WITH_CODE(dep_on_sclk,
1567 "Invalid SOC_VDD-GFX_CLK Dependency Table!",
1570 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
1571 gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock;
1573 for (i = 0; i < dep_on_sclk->count; i++) {
1574 if (dep_on_sclk->entries[i].clk == gfx_clock)
1577 PP_ASSERT_WITH_CODE(dep_on_sclk->count > i,
1578 "Cannot find gfx_clk in SOC_VDD-GFX_CLK!",
1582 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1583 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK,
1584 gfx_clock, ÷rs),
1585 "Failed to get GFX Clock settings from VBIOS!",
1588 /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */
1589 current_gfxclk_level->FbMult =
1590 cpu_to_le32(dividers.ulPll_fb_mult);
1591 /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */
1592 current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
1593 current_gfxclk_level->SsFbMult =
1594 cpu_to_le32(dividers.ulPll_ss_fbsmult);
1595 current_gfxclk_level->SsSlewFrac =
1596 cpu_to_le16(dividers.usPll_ss_slew_frac);
1597 current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);
1599 *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */
1605 * @brief Populates single SMC SOCCLK structure using the provided clock.
1607 * @param hwmgr - the address of the hardware manager.
1608 * @param soc_clock - the SOC clock to use to populate the structure.
1609 * @param current_socclk_level - location in PPTable for the SMC SOCCLK structure.
1610 * @return 0 on success..
1612 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,
1613 uint32_t soc_clock, uint8_t *current_soc_did,
1614 uint8_t *current_vol_index)
1616 struct vega10_hwmgr *data = hwmgr->backend;
1617 struct phm_ppt_v2_information *table_info =
1618 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1619 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc;
1620 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1623 if (hwmgr->od_enabled) {
1624 dep_on_soc = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1625 &data->odn_dpm_table.vdd_dep_on_socclk;
1626 for (i = 0; i < dep_on_soc->count; i++) {
1627 if (dep_on_soc->entries[i].clk >= soc_clock)
1631 dep_on_soc = table_info->vdd_dep_on_socclk;
1632 for (i = 0; i < dep_on_soc->count; i++) {
1633 if (dep_on_soc->entries[i].clk == soc_clock)
1638 PP_ASSERT_WITH_CODE(dep_on_soc->count > i,
1639 "Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table",
1642 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1643 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1644 soc_clock, ÷rs),
1645 "Failed to get SOC Clock settings from VBIOS!",
1648 *current_soc_did = (uint8_t)dividers.ulDid;
1649 *current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd);
1654 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1656 * @param hwmgr the address of the hardware manager
1658 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1660 struct vega10_hwmgr *data = hwmgr->backend;
1661 struct phm_ppt_v2_information *table_info =
1662 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1663 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1664 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
1668 for (i = 0; i < dpm_table->count; i++) {
1669 result = vega10_populate_single_gfx_level(hwmgr,
1670 dpm_table->dpm_levels[i].value,
1671 &(pp_table->GfxclkLevel[i]),
1672 &(pp_table->AcgFreqTable[i]));
1678 while (i < NUM_GFXCLK_DPM_LEVELS) {
1679 result = vega10_populate_single_gfx_level(hwmgr,
1680 dpm_table->dpm_levels[j].value,
1681 &(pp_table->GfxclkLevel[i]),
1682 &(pp_table->AcgFreqTable[i]));
1688 pp_table->GfxclkSlewRate =
1689 cpu_to_le16(table_info->us_gfxclk_slew_rate);
1691 dpm_table = &(data->dpm_table.soc_table);
1692 for (i = 0; i < dpm_table->count; i++) {
1693 result = vega10_populate_single_soc_level(hwmgr,
1694 dpm_table->dpm_levels[i].value,
1695 &(pp_table->SocclkDid[i]),
1696 &(pp_table->SocDpmVoltageIndex[i]));
1702 while (i < NUM_SOCCLK_DPM_LEVELS) {
1703 result = vega10_populate_single_soc_level(hwmgr,
1704 dpm_table->dpm_levels[j].value,
1705 &(pp_table->SocclkDid[i]),
1706 &(pp_table->SocDpmVoltageIndex[i]));
1715 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr)
1717 struct vega10_hwmgr *data = hwmgr->backend;
1718 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1719 struct phm_ppt_v2_information *table_info = hwmgr->pptable;
1720 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
1722 uint8_t soc_vid = 0;
1723 uint32_t i, max_vddc_level;
1725 if (hwmgr->od_enabled)
1726 vddc_lookup_table = (struct phm_ppt_v1_voltage_lookup_table *)&data->odn_dpm_table.vddc_lookup_table;
1728 vddc_lookup_table = table_info->vddc_lookup_table;
1730 max_vddc_level = vddc_lookup_table->count;
1731 for (i = 0; i < max_vddc_level; i++) {
1732 soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd);
1733 pp_table->SocVid[i] = soc_vid;
1735 while (i < MAX_REGULAR_DPM_NUMBER) {
1736 pp_table->SocVid[i] = soc_vid;
1742 * @brief Populates single SMC GFXCLK structure using the provided clock.
1744 * @param hwmgr - the address of the hardware manager.
1745 * @param mem_clock - the memory clock to use to populate the structure.
1746 * @return 0 on success..
1748 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1749 uint32_t mem_clock, uint8_t *current_mem_vid,
1750 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)
1752 struct vega10_hwmgr *data = hwmgr->backend;
1753 struct phm_ppt_v2_information *table_info =
1754 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1755 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk;
1756 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1757 uint32_t mem_max_clock =
1758 hwmgr->platform_descriptor.overdriveLimit.memoryClock;
1761 if (hwmgr->od_enabled)
1762 dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1763 &data->odn_dpm_table.vdd_dep_on_mclk;
1765 dep_on_mclk = table_info->vdd_dep_on_mclk;
1767 PP_ASSERT_WITH_CODE(dep_on_mclk,
1768 "Invalid SOC_VDD-UCLK Dependency Table!",
1771 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
1772 mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock;
1774 for (i = 0; i < dep_on_mclk->count; i++) {
1775 if (dep_on_mclk->entries[i].clk == mem_clock)
1778 PP_ASSERT_WITH_CODE(dep_on_mclk->count > i,
1779 "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!",
1783 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1784 hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, ÷rs),
1785 "Failed to get UCLK settings from VBIOS!",
1789 (uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd));
1790 *current_mem_soc_vind =
1791 (uint8_t)(dep_on_mclk->entries[i].vddInd);
1792 current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult);
1793 current_memclk_level->Did = (uint8_t)(dividers.ulDid);
1795 PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1,
1796 "Invalid Divider ID!",
1803 * @brief Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states.
1805 * @param pHwMgr - the address of the hardware manager.
1806 * @return PP_Result_OK on success.
1808 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1810 struct vega10_hwmgr *data = hwmgr->backend;
1811 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1812 struct vega10_single_dpm_table *dpm_table =
1813 &(data->dpm_table.mem_table);
1817 for (i = 0; i < dpm_table->count; i++) {
1818 result = vega10_populate_single_memory_level(hwmgr,
1819 dpm_table->dpm_levels[i].value,
1820 &(pp_table->MemVid[i]),
1821 &(pp_table->UclkLevel[i]),
1822 &(pp_table->MemSocVoltageIndex[i]));
1828 while (i < NUM_UCLK_DPM_LEVELS) {
1829 result = vega10_populate_single_memory_level(hwmgr,
1830 dpm_table->dpm_levels[j].value,
1831 &(pp_table->MemVid[i]),
1832 &(pp_table->UclkLevel[i]),
1833 &(pp_table->MemSocVoltageIndex[i]));
1839 pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels);
1840 pp_table->MemoryChannelWidth =
1841 (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH *
1842 channel_number[data->mem_channels]);
1844 pp_table->LowestUclkReservedForUlv =
1845 (uint8_t)(data->lowest_uclk_reserved_for_ulv);
1850 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,
1851 DSPCLK_e disp_clock)
1853 struct vega10_hwmgr *data = hwmgr->backend;
1854 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1855 struct phm_ppt_v2_information *table_info =
1856 (struct phm_ppt_v2_information *)
1858 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
1860 uint16_t clk = 0, vddc = 0;
1863 switch (disp_clock) {
1864 case DSPCLK_DCEFCLK:
1865 dep_table = table_info->vdd_dep_on_dcefclk;
1867 case DSPCLK_DISPCLK:
1868 dep_table = table_info->vdd_dep_on_dispclk;
1871 dep_table = table_info->vdd_dep_on_pixclk;
1874 dep_table = table_info->vdd_dep_on_phyclk;
1880 PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS,
1881 "Number Of Entries Exceeded maximum!",
1884 for (i = 0; i < dep_table->count; i++) {
1885 clk = (uint16_t)(dep_table->entries[i].clk / 100);
1886 vddc = table_info->vddc_lookup_table->
1887 entries[dep_table->entries[i].vddInd].us_vdd;
1888 vid = (uint8_t)convert_to_vid(vddc);
1889 pp_table->DisplayClockTable[disp_clock][i].Freq =
1891 pp_table->DisplayClockTable[disp_clock][i].Vid =
1895 while (i < NUM_DSPCLK_LEVELS) {
1896 pp_table->DisplayClockTable[disp_clock][i].Freq =
1898 pp_table->DisplayClockTable[disp_clock][i].Vid =
1906 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr)
1910 for (i = 0; i < DSPCLK_COUNT; i++) {
1911 PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i),
1912 "Failed to populate Clock in DisplayClockTable!",
1919 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr,
1920 uint32_t eclock, uint8_t *current_eclk_did,
1921 uint8_t *current_soc_vol)
1923 struct phm_ppt_v2_information *table_info =
1924 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1925 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
1926 table_info->mm_dep_table;
1927 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1930 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1931 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1933 "Failed to get ECLK clock settings from VBIOS!",
1936 *current_eclk_did = (uint8_t)dividers.ulDid;
1938 for (i = 0; i < dep_table->count; i++) {
1939 if (dep_table->entries[i].eclk == eclock)
1940 *current_soc_vol = dep_table->entries[i].vddcInd;
1946 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)
1948 struct vega10_hwmgr *data = hwmgr->backend;
1949 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1950 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table);
1951 int result = -EINVAL;
1954 for (i = 0; i < dpm_table->count; i++) {
1955 result = vega10_populate_single_eclock_level(hwmgr,
1956 dpm_table->dpm_levels[i].value,
1957 &(pp_table->EclkDid[i]),
1958 &(pp_table->VceDpmVoltageIndex[i]));
1964 while (i < NUM_VCE_DPM_LEVELS) {
1965 result = vega10_populate_single_eclock_level(hwmgr,
1966 dpm_table->dpm_levels[j].value,
1967 &(pp_table->EclkDid[i]),
1968 &(pp_table->VceDpmVoltageIndex[i]));
1977 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr,
1978 uint32_t vclock, uint8_t *current_vclk_did)
1980 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1982 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1983 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1985 "Failed to get VCLK clock settings from VBIOS!",
1988 *current_vclk_did = (uint8_t)dividers.ulDid;
1993 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr,
1994 uint32_t dclock, uint8_t *current_dclk_did)
1996 struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1998 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1999 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2001 "Failed to get DCLK clock settings from VBIOS!",
2004 *current_dclk_did = (uint8_t)dividers.ulDid;
2009 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
2011 struct vega10_hwmgr *data = hwmgr->backend;
2012 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2013 struct vega10_single_dpm_table *vclk_dpm_table =
2014 &(data->dpm_table.vclk_table);
2015 struct vega10_single_dpm_table *dclk_dpm_table =
2016 &(data->dpm_table.dclk_table);
2017 struct phm_ppt_v2_information *table_info =
2018 (struct phm_ppt_v2_information *)(hwmgr->pptable);
2019 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
2020 table_info->mm_dep_table;
2021 int result = -EINVAL;
2024 for (i = 0; i < vclk_dpm_table->count; i++) {
2025 result = vega10_populate_single_vclock_level(hwmgr,
2026 vclk_dpm_table->dpm_levels[i].value,
2027 &(pp_table->VclkDid[i]));
2033 while (i < NUM_UVD_DPM_LEVELS) {
2034 result = vega10_populate_single_vclock_level(hwmgr,
2035 vclk_dpm_table->dpm_levels[j].value,
2036 &(pp_table->VclkDid[i]));
2042 for (i = 0; i < dclk_dpm_table->count; i++) {
2043 result = vega10_populate_single_dclock_level(hwmgr,
2044 dclk_dpm_table->dpm_levels[i].value,
2045 &(pp_table->DclkDid[i]));
2051 while (i < NUM_UVD_DPM_LEVELS) {
2052 result = vega10_populate_single_dclock_level(hwmgr,
2053 dclk_dpm_table->dpm_levels[j].value,
2054 &(pp_table->DclkDid[i]));
2060 for (i = 0; i < dep_table->count; i++) {
2061 if (dep_table->entries[i].vclk ==
2062 vclk_dpm_table->dpm_levels[i].value &&
2063 dep_table->entries[i].dclk ==
2064 dclk_dpm_table->dpm_levels[i].value)
2065 pp_table->UvdDpmVoltageIndex[i] =
2066 dep_table->entries[i].vddcInd;
2072 while (i < NUM_UVD_DPM_LEVELS) {
2073 pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd;
2080 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
2082 struct vega10_hwmgr *data = hwmgr->backend;
2083 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2084 struct phm_ppt_v2_information *table_info =
2085 (struct phm_ppt_v2_information *)(hwmgr->pptable);
2086 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2087 table_info->vdd_dep_on_sclk;
2090 for (i = 0; i < dep_table->count; i++) {
2091 pp_table->CksEnable[i] = dep_table->entries[i].cks_enable;
2092 pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset
2093 * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2099 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
2101 struct vega10_hwmgr *data = hwmgr->backend;
2102 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2103 struct phm_ppt_v2_information *table_info =
2104 (struct phm_ppt_v2_information *)(hwmgr->pptable);
2105 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2106 table_info->vdd_dep_on_sclk;
2107 struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
2111 pp_table->MinVoltageVid = (uint8_t)0xff;
2112 pp_table->MaxVoltageVid = (uint8_t)0;
2114 if (data->smu_features[GNLD_AVFS].supported) {
2115 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
2117 pp_table->MinVoltageVid = (uint8_t)
2118 convert_to_vid((uint16_t)(avfs_params.ulMinVddc));
2119 pp_table->MaxVoltageVid = (uint8_t)
2120 convert_to_vid((uint16_t)(avfs_params.ulMaxVddc));
2122 pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0);
2123 pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1);
2124 pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2);
2125 pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2126 pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean);
2127 pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2128 pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor);
2130 pp_table->BtcGbVdroopTableCksOff.a0 =
2131 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0);
2132 pp_table->BtcGbVdroopTableCksOff.a0_shift = 20;
2133 pp_table->BtcGbVdroopTableCksOff.a1 =
2134 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1);
2135 pp_table->BtcGbVdroopTableCksOff.a1_shift = 20;
2136 pp_table->BtcGbVdroopTableCksOff.a2 =
2137 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2);
2138 pp_table->BtcGbVdroopTableCksOff.a2_shift = 20;
2140 pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson;
2141 pp_table->BtcGbVdroopTableCksOn.a0 =
2142 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0);
2143 pp_table->BtcGbVdroopTableCksOn.a0_shift = 20;
2144 pp_table->BtcGbVdroopTableCksOn.a1 =
2145 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1);
2146 pp_table->BtcGbVdroopTableCksOn.a1_shift = 20;
2147 pp_table->BtcGbVdroopTableCksOn.a2 =
2148 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2);
2149 pp_table->BtcGbVdroopTableCksOn.a2_shift = 20;
2151 pp_table->AvfsGbCksOn.m1 =
2152 cpu_to_le32(avfs_params.ulGbFuseTableCksonM1);
2153 pp_table->AvfsGbCksOn.m2 =
2154 cpu_to_le32(avfs_params.ulGbFuseTableCksonM2);
2155 pp_table->AvfsGbCksOn.b =
2156 cpu_to_le32(avfs_params.ulGbFuseTableCksonB);
2157 pp_table->AvfsGbCksOn.m1_shift = 24;
2158 pp_table->AvfsGbCksOn.m2_shift = 12;
2159 pp_table->AvfsGbCksOn.b_shift = 0;
2161 pp_table->OverrideAvfsGbCksOn =
2162 avfs_params.ucEnableGbFuseTableCkson;
2163 pp_table->AvfsGbCksOff.m1 =
2164 cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1);
2165 pp_table->AvfsGbCksOff.m2 =
2166 cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2);
2167 pp_table->AvfsGbCksOff.b =
2168 cpu_to_le32(avfs_params.ulGbFuseTableCksoffB);
2169 pp_table->AvfsGbCksOff.m1_shift = 24;
2170 pp_table->AvfsGbCksOff.m2_shift = 12;
2171 pp_table->AvfsGbCksOff.b_shift = 0;
2173 for (i = 0; i < dep_table->count; i++)
2174 pp_table->StaticVoltageOffsetVid[i] =
2175 convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset));
2177 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2178 data->disp_clk_quad_eqn_a) &&
2179 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2180 data->disp_clk_quad_eqn_b)) {
2181 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2182 (int32_t)data->disp_clk_quad_eqn_a;
2183 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2184 (int32_t)data->disp_clk_quad_eqn_b;
2185 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2186 (int32_t)data->disp_clk_quad_eqn_c;
2188 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2189 (int32_t)avfs_params.ulDispclk2GfxclkM1;
2190 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2191 (int32_t)avfs_params.ulDispclk2GfxclkM2;
2192 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2193 (int32_t)avfs_params.ulDispclk2GfxclkB;
2196 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24;
2197 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12;
2198 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12;
2200 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2201 data->dcef_clk_quad_eqn_a) &&
2202 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2203 data->dcef_clk_quad_eqn_b)) {
2204 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2205 (int32_t)data->dcef_clk_quad_eqn_a;
2206 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2207 (int32_t)data->dcef_clk_quad_eqn_b;
2208 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2209 (int32_t)data->dcef_clk_quad_eqn_c;
2211 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2212 (int32_t)avfs_params.ulDcefclk2GfxclkM1;
2213 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2214 (int32_t)avfs_params.ulDcefclk2GfxclkM2;
2215 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2216 (int32_t)avfs_params.ulDcefclk2GfxclkB;
2219 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24;
2220 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12;
2221 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12;
2223 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2224 data->pixel_clk_quad_eqn_a) &&
2225 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2226 data->pixel_clk_quad_eqn_b)) {
2227 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2228 (int32_t)data->pixel_clk_quad_eqn_a;
2229 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2230 (int32_t)data->pixel_clk_quad_eqn_b;
2231 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2232 (int32_t)data->pixel_clk_quad_eqn_c;
2234 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2235 (int32_t)avfs_params.ulPixelclk2GfxclkM1;
2236 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2237 (int32_t)avfs_params.ulPixelclk2GfxclkM2;
2238 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2239 (int32_t)avfs_params.ulPixelclk2GfxclkB;
2242 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24;
2243 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12;
2244 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12;
2245 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2246 data->phy_clk_quad_eqn_a) &&
2247 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2248 data->phy_clk_quad_eqn_b)) {
2249 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2250 (int32_t)data->phy_clk_quad_eqn_a;
2251 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2252 (int32_t)data->phy_clk_quad_eqn_b;
2253 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2254 (int32_t)data->phy_clk_quad_eqn_c;
2256 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2257 (int32_t)avfs_params.ulPhyclk2GfxclkM1;
2258 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2259 (int32_t)avfs_params.ulPhyclk2GfxclkM2;
2260 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2261 (int32_t)avfs_params.ulPhyclk2GfxclkB;
2264 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24;
2265 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12;
2266 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12;
2268 pp_table->AcgBtcGbVdroopTable.a0 = avfs_params.ulAcgGbVdroopTableA0;
2269 pp_table->AcgBtcGbVdroopTable.a0_shift = 20;
2270 pp_table->AcgBtcGbVdroopTable.a1 = avfs_params.ulAcgGbVdroopTableA1;
2271 pp_table->AcgBtcGbVdroopTable.a1_shift = 20;
2272 pp_table->AcgBtcGbVdroopTable.a2 = avfs_params.ulAcgGbVdroopTableA2;
2273 pp_table->AcgBtcGbVdroopTable.a2_shift = 20;
2275 pp_table->AcgAvfsGb.m1 = avfs_params.ulAcgGbFuseTableM1;
2276 pp_table->AcgAvfsGb.m2 = avfs_params.ulAcgGbFuseTableM2;
2277 pp_table->AcgAvfsGb.b = avfs_params.ulAcgGbFuseTableB;
2278 pp_table->AcgAvfsGb.m1_shift = 24;
2279 pp_table->AcgAvfsGb.m2_shift = 12;
2280 pp_table->AcgAvfsGb.b_shift = 0;
2283 data->smu_features[GNLD_AVFS].supported = false;
2290 static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
2292 struct vega10_hwmgr *data = hwmgr->backend;
2293 uint32_t agc_btc_response;
2295 if (data->smu_features[GNLD_ACG].supported) {
2296 if (0 == vega10_enable_smc_features(hwmgr, true,
2297 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap))
2298 data->smu_features[GNLD_DPM_PREFETCHER].enabled = true;
2300 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg);
2302 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc);
2303 agc_btc_response = smum_get_argument(hwmgr);
2305 if (1 == agc_btc_response) {
2306 if (1 == data->acg_loop_state)
2307 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop);
2308 else if (2 == data->acg_loop_state)
2309 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop);
2310 if (0 == vega10_enable_smc_features(hwmgr, true,
2311 data->smu_features[GNLD_ACG].smu_feature_bitmap))
2312 data->smu_features[GNLD_ACG].enabled = true;
2314 pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n");
2315 data->smu_features[GNLD_ACG].enabled = false;
2322 static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
2324 struct vega10_hwmgr *data = hwmgr->backend;
2326 if (data->smu_features[GNLD_ACG].supported &&
2327 data->smu_features[GNLD_ACG].enabled)
2328 if (!vega10_enable_smc_features(hwmgr, false,
2329 data->smu_features[GNLD_ACG].smu_feature_bitmap))
2330 data->smu_features[GNLD_ACG].enabled = false;
2335 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
2337 struct vega10_hwmgr *data = hwmgr->backend;
2338 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2339 struct pp_atomfwctrl_gpio_parameters gpio_params = {0};
2342 result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params);
2344 if (PP_CAP(PHM_PlatformCaps_RegulatorHot) &&
2345 data->registry_data.regulator_hot_gpio_support) {
2346 pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio;
2347 pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity;
2348 pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio;
2349 pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity;
2351 pp_table->VR0HotGpio = 0;
2352 pp_table->VR0HotPolarity = 0;
2353 pp_table->VR1HotGpio = 0;
2354 pp_table->VR1HotPolarity = 0;
2357 if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) &&
2358 data->registry_data.ac_dc_switch_gpio_support) {
2359 pp_table->AcDcGpio = gpio_params.ucAcDcGpio;
2360 pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity;
2362 pp_table->AcDcGpio = 0;
2363 pp_table->AcDcPolarity = 0;
2370 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
2372 struct vega10_hwmgr *data = hwmgr->backend;
2374 if (data->smu_features[GNLD_AVFS].supported) {
2375 /* Already enabled or disabled */
2376 if (!(enable ^ data->smu_features[GNLD_AVFS].enabled))
2380 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2382 data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2383 "[avfs_control] Attempt to Enable AVFS feature Failed!",
2385 data->smu_features[GNLD_AVFS].enabled = true;
2387 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2389 data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2390 "[avfs_control] Attempt to Disable AVFS feature Failed!",
2392 data->smu_features[GNLD_AVFS].enabled = false;
2399 static int vega10_update_avfs(struct pp_hwmgr *hwmgr)
2401 struct vega10_hwmgr *data = hwmgr->backend;
2403 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
2404 vega10_avfs_enable(hwmgr, false);
2405 } else if (data->need_update_dpm_table) {
2406 vega10_avfs_enable(hwmgr, false);
2407 vega10_avfs_enable(hwmgr, true);
2409 vega10_avfs_enable(hwmgr, true);
2415 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
2419 uint64_t serial_number = 0;
2420 uint32_t top32, bottom32;
2421 struct phm_fuses_default fuse;
2423 struct vega10_hwmgr *data = hwmgr->backend;
2424 AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
2426 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
2427 top32 = smum_get_argument(hwmgr);
2429 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
2430 bottom32 = smum_get_argument(hwmgr);
2432 serial_number = ((uint64_t)bottom32 << 32) | top32;
2434 if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) {
2435 avfs_fuse_table->VFT0_b = fuse.VFT0_b;
2436 avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1;
2437 avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2;
2438 avfs_fuse_table->VFT1_b = fuse.VFT1_b;
2439 avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1;
2440 avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2;
2441 avfs_fuse_table->VFT2_b = fuse.VFT2_b;
2442 avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1;
2443 avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2;
2444 result = smum_smc_table_manager(hwmgr, (uint8_t *)avfs_fuse_table,
2445 AVFSFUSETABLE, false);
2446 PP_ASSERT_WITH_CODE(!result,
2447 "Failed to upload FuseOVerride!",
2454 static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
2456 struct vega10_hwmgr *data = hwmgr->backend;
2457 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2458 struct phm_ppt_v2_information *table_info = hwmgr->pptable;
2459 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
2460 struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
2463 dep_table = table_info->vdd_dep_on_mclk;
2464 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk);
2466 for (i = 0; i < dep_table->count; i++) {
2467 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2468 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
2473 dep_table = table_info->vdd_dep_on_sclk;
2474 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk);
2475 for (i = 0; i < dep_table->count; i++) {
2476 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2477 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
2484 * Initializes the SMC table and uploads it
2486 * @param hwmgr the address of the powerplay hardware manager.
2487 * @param pInput the pointer to input data (PowerState)
2490 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
2493 struct vega10_hwmgr *data = hwmgr->backend;
2494 struct phm_ppt_v2_information *table_info =
2495 (struct phm_ppt_v2_information *)(hwmgr->pptable);
2496 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2497 struct pp_atomfwctrl_voltage_table voltage_table;
2498 struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
2499 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2501 result = vega10_setup_default_dpm_tables(hwmgr);
2502 PP_ASSERT_WITH_CODE(!result,
2503 "Failed to setup default DPM tables!",
2506 /* initialize ODN table */
2507 if (hwmgr->od_enabled) {
2508 if (odn_table->max_vddc) {
2509 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
2510 vega10_check_dpm_table_updated(hwmgr);
2512 vega10_odn_initial_default_setting(hwmgr);
2516 pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC,
2517 VOLTAGE_OBJ_SVID2, &voltage_table);
2518 pp_table->MaxVidStep = voltage_table.max_vid_step;
2520 pp_table->GfxDpmVoltageMode =
2521 (uint8_t)(table_info->uc_gfx_dpm_voltage_mode);
2522 pp_table->SocDpmVoltageMode =
2523 (uint8_t)(table_info->uc_soc_dpm_voltage_mode);
2524 pp_table->UclkDpmVoltageMode =
2525 (uint8_t)(table_info->uc_uclk_dpm_voltage_mode);
2526 pp_table->UvdDpmVoltageMode =
2527 (uint8_t)(table_info->uc_uvd_dpm_voltage_mode);
2528 pp_table->VceDpmVoltageMode =
2529 (uint8_t)(table_info->uc_vce_dpm_voltage_mode);
2530 pp_table->Mp0DpmVoltageMode =
2531 (uint8_t)(table_info->uc_mp0_dpm_voltage_mode);
2533 pp_table->DisplayDpmVoltageMode =
2534 (uint8_t)(table_info->uc_dcef_dpm_voltage_mode);
2536 data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable;
2537 data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable;
2539 if (data->registry_data.ulv_support &&
2540 table_info->us_ulv_voltage_offset) {
2541 result = vega10_populate_ulv_state(hwmgr);
2542 PP_ASSERT_WITH_CODE(!result,
2543 "Failed to initialize ULV state!",
2547 result = vega10_populate_smc_link_levels(hwmgr);
2548 PP_ASSERT_WITH_CODE(!result,
2549 "Failed to initialize Link Level!",
2552 result = vega10_populate_all_graphic_levels(hwmgr);
2553 PP_ASSERT_WITH_CODE(!result,
2554 "Failed to initialize Graphics Level!",
2557 result = vega10_populate_all_memory_levels(hwmgr);
2558 PP_ASSERT_WITH_CODE(!result,
2559 "Failed to initialize Memory Level!",
2562 vega10_populate_vddc_soc_levels(hwmgr);
2564 result = vega10_populate_all_display_clock_levels(hwmgr);
2565 PP_ASSERT_WITH_CODE(!result,
2566 "Failed to initialize Display Level!",
2569 result = vega10_populate_smc_vce_levels(hwmgr);
2570 PP_ASSERT_WITH_CODE(!result,
2571 "Failed to initialize VCE Level!",
2574 result = vega10_populate_smc_uvd_levels(hwmgr);
2575 PP_ASSERT_WITH_CODE(!result,
2576 "Failed to initialize UVD Level!",
2579 if (data->registry_data.clock_stretcher_support) {
2580 result = vega10_populate_clock_stretcher_table(hwmgr);
2581 PP_ASSERT_WITH_CODE(!result,
2582 "Failed to populate Clock Stretcher Table!",
2586 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
2588 data->vbios_boot_state.vddc = boot_up_values.usVddc;
2589 data->vbios_boot_state.vddci = boot_up_values.usVddci;
2590 data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
2591 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
2592 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
2593 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2594 SMU9_SYSPLL0_SOCCLK_ID, 0, &boot_up_values.ulSocClk);
2596 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2597 SMU9_SYSPLL0_DCEFCLK_ID, 0, &boot_up_values.ulDCEFClk);
2599 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
2600 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
2601 if (0 != boot_up_values.usVddc) {
2602 smum_send_msg_to_smc_with_parameter(hwmgr,
2603 PPSMC_MSG_SetFloorSocVoltage,
2604 (boot_up_values.usVddc * 4));
2605 data->vbios_boot_state.bsoc_vddc_lock = true;
2607 data->vbios_boot_state.bsoc_vddc_lock = false;
2609 smum_send_msg_to_smc_with_parameter(hwmgr,
2610 PPSMC_MSG_SetMinDeepSleepDcefclk,
2611 (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
2614 result = vega10_populate_avfs_parameters(hwmgr);
2615 PP_ASSERT_WITH_CODE(!result,
2616 "Failed to initialize AVFS Parameters!",
2619 result = vega10_populate_gpio_parameters(hwmgr);
2620 PP_ASSERT_WITH_CODE(!result,
2621 "Failed to initialize GPIO Parameters!",
2624 pp_table->GfxclkAverageAlpha = (uint8_t)
2625 (data->gfxclk_average_alpha);
2626 pp_table->SocclkAverageAlpha = (uint8_t)
2627 (data->socclk_average_alpha);
2628 pp_table->UclkAverageAlpha = (uint8_t)
2629 (data->uclk_average_alpha);
2630 pp_table->GfxActivityAverageAlpha = (uint8_t)
2631 (data->gfx_activity_average_alpha);
2633 vega10_populate_and_upload_avfs_fuse_override(hwmgr);
2635 result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
2637 PP_ASSERT_WITH_CODE(!result,
2638 "Failed to upload PPtable!", return result);
2640 result = vega10_avfs_enable(hwmgr, true);
2641 PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!",
2643 vega10_acg_enable(hwmgr);
2648 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
2650 struct vega10_hwmgr *data = hwmgr->backend;
2652 if (data->smu_features[GNLD_THERMAL].supported) {
2653 if (data->smu_features[GNLD_THERMAL].enabled)
2654 pr_info("THERMAL Feature Already enabled!");
2656 PP_ASSERT_WITH_CODE(
2657 !vega10_enable_smc_features(hwmgr,
2659 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2660 "Enable THERMAL Feature Failed!",
2662 data->smu_features[GNLD_THERMAL].enabled = true;
2668 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
2670 struct vega10_hwmgr *data = hwmgr->backend;
2672 if (data->smu_features[GNLD_THERMAL].supported) {
2673 if (!data->smu_features[GNLD_THERMAL].enabled)
2674 pr_info("THERMAL Feature Already disabled!");
2676 PP_ASSERT_WITH_CODE(
2677 !vega10_enable_smc_features(hwmgr,
2679 data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2680 "disable THERMAL Feature Failed!",
2682 data->smu_features[GNLD_THERMAL].enabled = false;
2688 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
2690 struct vega10_hwmgr *data = hwmgr->backend;
2692 if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
2693 if (data->smu_features[GNLD_VR0HOT].supported) {
2694 PP_ASSERT_WITH_CODE(
2695 !vega10_enable_smc_features(hwmgr,
2697 data->smu_features[GNLD_VR0HOT].smu_feature_bitmap),
2698 "Attempt to Enable VR0 Hot feature Failed!",
2700 data->smu_features[GNLD_VR0HOT].enabled = true;
2702 if (data->smu_features[GNLD_VR1HOT].supported) {
2703 PP_ASSERT_WITH_CODE(
2704 !vega10_enable_smc_features(hwmgr,
2706 data->smu_features[GNLD_VR1HOT].smu_feature_bitmap),
2707 "Attempt to Enable VR0 Hot feature Failed!",
2709 data->smu_features[GNLD_VR1HOT].enabled = true;
2716 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
2718 struct vega10_hwmgr *data = hwmgr->backend;
2720 if (data->registry_data.ulv_support) {
2721 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2722 true, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2723 "Enable ULV Feature Failed!",
2725 data->smu_features[GNLD_ULV].enabled = true;
2731 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
2733 struct vega10_hwmgr *data = hwmgr->backend;
2735 if (data->registry_data.ulv_support) {
2736 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2737 false, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2738 "disable ULV Feature Failed!",
2740 data->smu_features[GNLD_ULV].enabled = false;
2746 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2748 struct vega10_hwmgr *data = hwmgr->backend;
2750 if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2751 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2752 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2753 "Attempt to Enable DS_GFXCLK Feature Failed!",
2755 data->smu_features[GNLD_DS_GFXCLK].enabled = true;
2758 if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2759 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2760 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2761 "Attempt to Enable DS_SOCCLK Feature Failed!",
2763 data->smu_features[GNLD_DS_SOCCLK].enabled = true;
2766 if (data->smu_features[GNLD_DS_LCLK].supported) {
2767 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2768 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2769 "Attempt to Enable DS_LCLK Feature Failed!",
2771 data->smu_features[GNLD_DS_LCLK].enabled = true;
2774 if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2775 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2776 true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2777 "Attempt to Enable DS_DCEFCLK Feature Failed!",
2779 data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
2785 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2787 struct vega10_hwmgr *data = hwmgr->backend;
2789 if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2790 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2791 false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2792 "Attempt to disable DS_GFXCLK Feature Failed!",
2794 data->smu_features[GNLD_DS_GFXCLK].enabled = false;
2797 if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2798 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2799 false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2800 "Attempt to disable DS_ Feature Failed!",
2802 data->smu_features[GNLD_DS_SOCCLK].enabled = false;
2805 if (data->smu_features[GNLD_DS_LCLK].supported) {
2806 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2807 false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2808 "Attempt to disable DS_LCLK Feature Failed!",
2810 data->smu_features[GNLD_DS_LCLK].enabled = false;
2813 if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2814 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2815 false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2816 "Attempt to disable DS_DCEFCLK Feature Failed!",
2818 data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
2824 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2826 struct vega10_hwmgr *data = hwmgr->backend;
2827 uint32_t i, feature_mask = 0;
2830 if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2831 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2832 false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2833 "Attempt to disable LED DPM feature failed!", return -EINVAL);
2834 data->smu_features[GNLD_LED_DISPLAY].enabled = false;
2837 for (i = 0; i < GNLD_DPM_MAX; i++) {
2838 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2839 if (data->smu_features[i].supported) {
2840 if (data->smu_features[i].enabled) {
2841 feature_mask |= data->smu_features[i].
2843 data->smu_features[i].enabled = false;
2849 vega10_enable_smc_features(hwmgr, false, feature_mask);
2855 * @brief Tell SMC to enabled the supported DPMs.
2857 * @param hwmgr - the address of the powerplay hardware manager.
2858 * @Param bitmap - bitmap for the features to enabled.
2859 * @return 0 on at least one DPM is successfully enabled.
2861 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2863 struct vega10_hwmgr *data = hwmgr->backend;
2864 uint32_t i, feature_mask = 0;
2866 for (i = 0; i < GNLD_DPM_MAX; i++) {
2867 if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2868 if (data->smu_features[i].supported) {
2869 if (!data->smu_features[i].enabled) {
2870 feature_mask |= data->smu_features[i].
2872 data->smu_features[i].enabled = true;
2878 if (vega10_enable_smc_features(hwmgr,
2879 true, feature_mask)) {
2880 for (i = 0; i < GNLD_DPM_MAX; i++) {
2881 if (data->smu_features[i].smu_feature_bitmap &
2883 data->smu_features[i].enabled = false;
2887 if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2888 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2889 true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2890 "Attempt to Enable LED DPM feature Failed!", return -EINVAL);
2891 data->smu_features[GNLD_LED_DISPLAY].enabled = true;
2894 if (data->vbios_boot_state.bsoc_vddc_lock) {
2895 smum_send_msg_to_smc_with_parameter(hwmgr,
2896 PPSMC_MSG_SetFloorSocVoltage, 0);
2897 data->vbios_boot_state.bsoc_vddc_lock = false;
2900 if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) {
2901 if (data->smu_features[GNLD_ACDC].supported) {
2902 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2903 true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),
2904 "Attempt to Enable DS_GFXCLK Feature Failed!",
2906 data->smu_features[GNLD_ACDC].enabled = true;
2913 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
2915 struct vega10_hwmgr *data = hwmgr->backend;
2917 if (data->smu_features[GNLD_PCC_LIMIT].supported) {
2918 if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)
2919 pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled");
2920 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2921 enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap),
2922 "Attempt to Enable PCC Limit feature Failed!",
2924 data->smu_features[GNLD_PCC_LIMIT].enabled = enable;
2930 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
2932 struct vega10_hwmgr *data = hwmgr->backend;
2933 int tmp_result, result = 0;
2935 vega10_enable_disable_PCC_limit_feature(hwmgr, true);
2937 smum_send_msg_to_smc_with_parameter(hwmgr,
2938 PPSMC_MSG_ConfigureTelemetry, data->config_telemetry);
2940 tmp_result = vega10_construct_voltage_tables(hwmgr);
2941 PP_ASSERT_WITH_CODE(!tmp_result,
2942 "Failed to construct voltage tables!",
2943 result = tmp_result);
2945 tmp_result = vega10_init_smc_table(hwmgr);
2946 PP_ASSERT_WITH_CODE(!tmp_result,
2947 "Failed to initialize SMC table!",
2948 result = tmp_result);
2950 if (PP_CAP(PHM_PlatformCaps_ThermalController)) {
2951 tmp_result = vega10_enable_thermal_protection(hwmgr);
2952 PP_ASSERT_WITH_CODE(!tmp_result,
2953 "Failed to enable thermal protection!",
2954 result = tmp_result);
2957 tmp_result = vega10_enable_vrhot_feature(hwmgr);
2958 PP_ASSERT_WITH_CODE(!tmp_result,
2959 "Failed to enable VR hot feature!",
2960 result = tmp_result);
2962 tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr);
2963 PP_ASSERT_WITH_CODE(!tmp_result,
2964 "Failed to enable deep sleep master switch!",
2965 result = tmp_result);
2967 tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES);
2968 PP_ASSERT_WITH_CODE(!tmp_result,
2969 "Failed to start DPM!", result = tmp_result);
2971 /* enable didt, do not abort if failed didt */
2972 tmp_result = vega10_enable_didt_config(hwmgr);
2973 PP_ASSERT(!tmp_result,
2974 "Failed to enable didt config!");
2976 tmp_result = vega10_enable_power_containment(hwmgr);
2977 PP_ASSERT_WITH_CODE(!tmp_result,
2978 "Failed to enable power containment!",
2979 result = tmp_result);
2981 tmp_result = vega10_power_control_set_level(hwmgr);
2982 PP_ASSERT_WITH_CODE(!tmp_result,
2983 "Failed to power control set level!",
2984 result = tmp_result);
2986 tmp_result = vega10_enable_ulv(hwmgr);
2987 PP_ASSERT_WITH_CODE(!tmp_result,
2988 "Failed to enable ULV!",
2989 result = tmp_result);
2994 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr)
2996 return sizeof(struct vega10_power_state);
2999 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3000 void *state, struct pp_power_state *power_state,
3001 void *pp_table, uint32_t classification_flag)
3003 ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2;
3004 struct vega10_power_state *vega10_power_state =
3005 cast_phw_vega10_power_state(&(power_state->hardware));
3006 struct vega10_performance_level *performance_level;
3007 ATOM_Vega10_State *state_entry = (ATOM_Vega10_State *)state;
3008 ATOM_Vega10_POWERPLAYTABLE *powerplay_table =
3009 (ATOM_Vega10_POWERPLAYTABLE *)pp_table;
3010 ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table =
3011 (ATOM_Vega10_SOCCLK_Dependency_Table *)
3012 (((unsigned long)powerplay_table) +
3013 le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
3014 ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
3015 (ATOM_Vega10_GFXCLK_Dependency_Table *)
3016 (((unsigned long)powerplay_table) +
3017 le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
3018 ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table =
3019 (ATOM_Vega10_MCLK_Dependency_Table *)
3020 (((unsigned long)powerplay_table) +
3021 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3024 /* The following fields are not initialized here:
3025 * id orderedList allStatesList
3027 power_state->classification.ui_label =
3028 (le16_to_cpu(state_entry->usClassification) &
3029 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3030 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3031 power_state->classification.flags = classification_flag;
3032 /* NOTE: There is a classification2 flag in BIOS
3033 * that is not being used right now
3035 power_state->classification.temporary_state = false;
3036 power_state->classification.to_be_deleted = false;
3038 power_state->validation.disallowOnDC =
3039 ((le32_to_cpu(state_entry->ulCapsAndSettings) &
3040 ATOM_Vega10_DISALLOW_ON_DC) != 0);
3042 power_state->display.disableFrameModulation = false;
3043 power_state->display.limitRefreshrate = false;
3044 power_state->display.enableVariBright =
3045 ((le32_to_cpu(state_entry->ulCapsAndSettings) &
3046 ATOM_Vega10_ENABLE_VARIBRIGHT) != 0);
3048 power_state->validation.supportedPowerLevels = 0;
3049 power_state->uvd_clocks.VCLK = 0;
3050 power_state->uvd_clocks.DCLK = 0;
3051 power_state->temperatures.min = 0;
3052 power_state->temperatures.max = 0;
3054 performance_level = &(vega10_power_state->performance_levels
3055 [vega10_power_state->performance_level_count++]);
3057 PP_ASSERT_WITH_CODE(
3058 (vega10_power_state->performance_level_count <
3059 NUM_GFXCLK_DPM_LEVELS),
3060 "Performance levels exceeds SMC limit!",
3063 PP_ASSERT_WITH_CODE(
3064 (vega10_power_state->performance_level_count <=
3065 hwmgr->platform_descriptor.
3066 hardwareActivityPerformanceLevels),
3067 "Performance levels exceeds Driver limit!",
3070 /* Performance levels are arranged from low to high. */
3071 performance_level->soc_clock = socclk_dep_table->entries
3072 [state_entry->ucSocClockIndexLow].ulClk;
3073 performance_level->gfx_clock = gfxclk_dep_table->entries
3074 [state_entry->ucGfxClockIndexLow].ulClk;
3075 performance_level->mem_clock = mclk_dep_table->entries
3076 [state_entry->ucMemClockIndexLow].ulMemClk;
3078 performance_level = &(vega10_power_state->performance_levels
3079 [vega10_power_state->performance_level_count++]);
3080 performance_level->soc_clock = socclk_dep_table->entries
3081 [state_entry->ucSocClockIndexHigh].ulClk;
3082 if (gfxclk_dep_table->ucRevId == 0) {
3083 performance_level->gfx_clock = gfxclk_dep_table->entries
3084 [state_entry->ucGfxClockIndexHigh].ulClk;
3085 } else if (gfxclk_dep_table->ucRevId == 1) {
3086 patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries;
3087 performance_level->gfx_clock = patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk;
3090 performance_level->mem_clock = mclk_dep_table->entries
3091 [state_entry->ucMemClockIndexHigh].ulMemClk;
3095 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3096 unsigned long entry_index, struct pp_power_state *state)
3099 struct vega10_power_state *ps;
3101 state->hardware.magic = PhwVega10_Magic;
3103 ps = cast_phw_vega10_power_state(&state->hardware);
3105 result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state,
3106 vega10_get_pp_table_entry_callback_func);
3109 * This is the earliest time we have all the dependency table
3110 * and the VBIOS boot state
3112 /* set DC compatible flag if this state supports DC */
3113 if (!state->validation.disallowOnDC)
3114 ps->dc_compatible = true;
3116 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3117 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3122 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr,
3123 struct pp_hw_power_state *hw_ps)
3128 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3129 struct pp_power_state *request_ps,
3130 const struct pp_power_state *current_ps)
3132 struct amdgpu_device *adev = hwmgr->adev;
3133 struct vega10_power_state *vega10_ps =
3134 cast_phw_vega10_power_state(&request_ps->hardware);
3137 struct PP_Clocks minimum_clocks = {0};
3138 bool disable_mclk_switching;
3139 bool disable_mclk_switching_for_frame_lock;
3140 bool disable_mclk_switching_for_vr;
3141 bool force_mclk_high;
3142 const struct phm_clock_and_voltage_limits *max_limits;
3144 struct vega10_hwmgr *data = hwmgr->backend;
3145 struct phm_ppt_v2_information *table_info =
3146 (struct phm_ppt_v2_information *)(hwmgr->pptable);
3148 uint32_t stable_pstate_sclk_dpm_percentage;
3149 uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3152 data->battery_state = (PP_StateUILabel_Battery ==
3153 request_ps->classification.ui_label);
3155 if (vega10_ps->performance_level_count != 2)
3156 pr_info("VI should always have 2 performance levels");
3158 max_limits = adev->pm.ac_power ?
3159 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3160 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3162 /* Cap clock DPM tables at DC MAX if it is in DC. */
3163 if (!adev->pm.ac_power) {
3164 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3165 if (vega10_ps->performance_levels[i].mem_clock >
3167 vega10_ps->performance_levels[i].mem_clock =
3169 if (vega10_ps->performance_levels[i].gfx_clock >
3171 vega10_ps->performance_levels[i].gfx_clock =
3176 /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3177 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
3178 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3180 if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3181 stable_pstate_sclk_dpm_percentage =
3182 data->registry_data.stable_pstate_sclk_dpm_percentage;
3183 PP_ASSERT_WITH_CODE(
3184 data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 &&
3185 data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
3186 "percent sclk value must range from 1% to 100%, setting default value",
3187 stable_pstate_sclk_dpm_percentage = 75);
3189 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3190 stable_pstate_sclk = (max_limits->sclk *
3191 stable_pstate_sclk_dpm_percentage) / 100;
3193 for (count = table_info->vdd_dep_on_sclk->count - 1;
3194 count >= 0; count--) {
3195 if (stable_pstate_sclk >=
3196 table_info->vdd_dep_on_sclk->entries[count].clk) {
3197 stable_pstate_sclk =
3198 table_info->vdd_dep_on_sclk->entries[count].clk;
3204 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3206 stable_pstate_mclk = max_limits->mclk;
3208 minimum_clocks.engineClock = stable_pstate_sclk;
3209 minimum_clocks.memoryClock = stable_pstate_mclk;
3212 disable_mclk_switching_for_frame_lock =
3213 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3214 disable_mclk_switching_for_vr =
3215 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
3216 force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
3218 if (hwmgr->display_config->num_display == 0)
3219 disable_mclk_switching = false;
3221 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3222 !hwmgr->display_config->multi_monitor_in_sync) ||
3223 disable_mclk_switching_for_frame_lock ||
3224 disable_mclk_switching_for_vr ||
3227 sclk = vega10_ps->performance_levels[0].gfx_clock;
3228 mclk = vega10_ps->performance_levels[0].mem_clock;
3230 if (sclk < minimum_clocks.engineClock)
3231 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3232 max_limits->sclk : minimum_clocks.engineClock;
3234 if (mclk < minimum_clocks.memoryClock)
3235 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3236 max_limits->mclk : minimum_clocks.memoryClock;
3238 vega10_ps->performance_levels[0].gfx_clock = sclk;
3239 vega10_ps->performance_levels[0].mem_clock = mclk;
3241 if (vega10_ps->performance_levels[1].gfx_clock <
3242 vega10_ps->performance_levels[0].gfx_clock)
3243 vega10_ps->performance_levels[0].gfx_clock =
3244 vega10_ps->performance_levels[1].gfx_clock;
3246 if (disable_mclk_switching) {
3247 /* Set Mclk the max of level 0 and level 1 */
3248 if (mclk < vega10_ps->performance_levels[1].mem_clock)
3249 mclk = vega10_ps->performance_levels[1].mem_clock;
3251 /* Find the lowest MCLK frequency that is within
3252 * the tolerable latency defined in DAL
3254 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3255 for (i = 0; i < data->mclk_latency_table.count; i++) {
3256 if ((data->mclk_latency_table.entries[i].latency <= latency) &&
3257 (data->mclk_latency_table.entries[i].frequency >=
3258 vega10_ps->performance_levels[0].mem_clock) &&
3259 (data->mclk_latency_table.entries[i].frequency <=
3260 vega10_ps->performance_levels[1].mem_clock))
3261 mclk = data->mclk_latency_table.entries[i].frequency;
3263 vega10_ps->performance_levels[0].mem_clock = mclk;
3265 if (vega10_ps->performance_levels[1].mem_clock <
3266 vega10_ps->performance_levels[0].mem_clock)
3267 vega10_ps->performance_levels[0].mem_clock =
3268 vega10_ps->performance_levels[1].mem_clock;
3271 if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3272 for (i = 0; i < vega10_ps->performance_level_count; i++) {
3273 vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk;
3274 vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk;
3281 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3283 struct vega10_hwmgr *data = hwmgr->backend;
3284 const struct phm_set_power_state_input *states =
3285 (const struct phm_set_power_state_input *)input;
3286 const struct vega10_power_state *vega10_ps =
3287 cast_const_phw_vega10_power_state(states->pnew_state);
3288 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
3289 uint32_t sclk = vega10_ps->performance_levels
3290 [vega10_ps->performance_level_count - 1].gfx_clock;
3291 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
3292 uint32_t mclk = vega10_ps->performance_levels
3293 [vega10_ps->performance_level_count - 1].mem_clock;
3296 for (i = 0; i < sclk_table->count; i++) {
3297 if (sclk == sclk_table->dpm_levels[i].value)
3301 if (i >= sclk_table->count) {
3302 if (sclk > sclk_table->dpm_levels[i-1].value) {
3303 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3304 sclk_table->dpm_levels[i-1].value = sclk;
3308 for (i = 0; i < mclk_table->count; i++) {
3309 if (mclk == mclk_table->dpm_levels[i].value)
3313 if (i >= mclk_table->count) {
3314 if (mclk > mclk_table->dpm_levels[i-1].value) {
3315 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3316 mclk_table->dpm_levels[i-1].value = mclk;
3320 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3321 data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
3326 static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
3327 struct pp_hwmgr *hwmgr, const void *input)
3330 struct vega10_hwmgr *data = hwmgr->backend;
3331 struct vega10_dpm_table *dpm_table = &data->dpm_table;
3332 struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table;
3333 struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk;
3336 if (!data->need_update_dpm_table)
3339 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3340 for (count = 0; count < dpm_table->gfx_table.count; count++)
3341 dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3344 odn_clk_table = &odn_table->vdd_dep_on_mclk;
3345 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3346 for (count = 0; count < dpm_table->mem_table.count; count++)
3347 dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3350 if (data->need_update_dpm_table &
3351 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK + DPMTABLE_UPDATE_SOCCLK)) {
3352 result = vega10_populate_all_graphic_levels(hwmgr);
3353 PP_ASSERT_WITH_CODE((0 == result),
3354 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3358 if (data->need_update_dpm_table &
3359 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
3360 result = vega10_populate_all_memory_levels(hwmgr);
3361 PP_ASSERT_WITH_CODE((0 == result),
3362 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3366 vega10_populate_vddc_soc_levels(hwmgr);
3371 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3372 struct vega10_single_dpm_table *dpm_table,
3373 uint32_t low_limit, uint32_t high_limit)
3377 for (i = 0; i < dpm_table->count; i++) {
3378 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3379 (dpm_table->dpm_levels[i].value > high_limit))
3380 dpm_table->dpm_levels[i].enabled = false;
3382 dpm_table->dpm_levels[i].enabled = true;
3387 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr,
3388 struct vega10_single_dpm_table *dpm_table,
3389 uint32_t low_limit, uint32_t high_limit,
3390 uint32_t disable_dpm_mask)
3394 for (i = 0; i < dpm_table->count; i++) {
3395 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3396 (dpm_table->dpm_levels[i].value > high_limit))
3397 dpm_table->dpm_levels[i].enabled = false;
3398 else if (!((1 << i) & disable_dpm_mask))
3399 dpm_table->dpm_levels[i].enabled = false;
3401 dpm_table->dpm_levels[i].enabled = true;
3406 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,
3407 const struct vega10_power_state *vega10_ps)
3409 struct vega10_hwmgr *data = hwmgr->backend;
3410 uint32_t high_limit_count;
3412 PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),
3413 "power state did not have any performance level",
3416 high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1;
3418 vega10_trim_single_dpm_states(hwmgr,
3419 &(data->dpm_table.soc_table),
3420 vega10_ps->performance_levels[0].soc_clock,
3421 vega10_ps->performance_levels[high_limit_count].soc_clock);
3423 vega10_trim_single_dpm_states_with_mask(hwmgr,
3424 &(data->dpm_table.gfx_table),
3425 vega10_ps->performance_levels[0].gfx_clock,
3426 vega10_ps->performance_levels[high_limit_count].gfx_clock,
3427 data->disable_dpm_mask);
3429 vega10_trim_single_dpm_states(hwmgr,
3430 &(data->dpm_table.mem_table),
3431 vega10_ps->performance_levels[0].mem_clock,
3432 vega10_ps->performance_levels[high_limit_count].mem_clock);
3437 static uint32_t vega10_find_lowest_dpm_level(
3438 struct vega10_single_dpm_table *table)
3442 for (i = 0; i < table->count; i++) {
3443 if (table->dpm_levels[i].enabled)
3450 static uint32_t vega10_find_highest_dpm_level(
3451 struct vega10_single_dpm_table *table)
3455 if (table->count <= MAX_REGULAR_DPM_NUMBER) {
3456 for (i = table->count; i > 0; i--) {
3457 if (table->dpm_levels[i - 1].enabled)
3461 pr_info("DPM Table Has Too Many Entries!");
3462 return MAX_REGULAR_DPM_NUMBER - 1;
3468 static void vega10_apply_dal_minimum_voltage_request(
3469 struct pp_hwmgr *hwmgr)
3474 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr)
3476 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table_on_mclk;
3477 struct phm_ppt_v2_information *table_info =
3478 (struct phm_ppt_v2_information *)(hwmgr->pptable);
3480 vdd_dep_table_on_mclk = table_info->vdd_dep_on_mclk;
3482 return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1;
3485 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
3487 struct vega10_hwmgr *data = hwmgr->backend;
3488 uint32_t socclk_idx;
3490 vega10_apply_dal_minimum_voltage_request(hwmgr);
3492 if (!data->registry_data.sclk_dpm_key_disabled) {
3493 if (data->smc_state_table.gfx_boot_level !=
3494 data->dpm_table.gfx_table.dpm_state.soft_min_level) {
3495 smum_send_msg_to_smc_with_parameter(hwmgr,
3496 PPSMC_MSG_SetSoftMinGfxclkByIndex,
3497 data->smc_state_table.gfx_boot_level);
3498 data->dpm_table.gfx_table.dpm_state.soft_min_level =
3499 data->smc_state_table.gfx_boot_level;
3503 if (!data->registry_data.mclk_dpm_key_disabled) {
3504 if (data->smc_state_table.mem_boot_level !=
3505 data->dpm_table.mem_table.dpm_state.soft_min_level) {
3506 if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) {
3507 socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
3508 smum_send_msg_to_smc_with_parameter(hwmgr,
3509 PPSMC_MSG_SetSoftMinSocclkByIndex,
3512 smum_send_msg_to_smc_with_parameter(hwmgr,
3513 PPSMC_MSG_SetSoftMinUclkByIndex,
3514 data->smc_state_table.mem_boot_level);
3516 data->dpm_table.mem_table.dpm_state.soft_min_level =
3517 data->smc_state_table.mem_boot_level;
3521 if (!data->registry_data.socclk_dpm_key_disabled) {
3522 if (data->smc_state_table.soc_boot_level !=
3523 data->dpm_table.soc_table.dpm_state.soft_min_level) {
3524 smum_send_msg_to_smc_with_parameter(hwmgr,
3525 PPSMC_MSG_SetSoftMinSocclkByIndex,
3526 data->smc_state_table.soc_boot_level);
3527 data->dpm_table.soc_table.dpm_state.soft_min_level =
3528 data->smc_state_table.soc_boot_level;
3535 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
3537 struct vega10_hwmgr *data = hwmgr->backend;
3539 vega10_apply_dal_minimum_voltage_request(hwmgr);
3541 if (!data->registry_data.sclk_dpm_key_disabled) {
3542 if (data->smc_state_table.gfx_max_level !=
3543 data->dpm_table.gfx_table.dpm_state.soft_max_level) {
3544 smum_send_msg_to_smc_with_parameter(hwmgr,
3545 PPSMC_MSG_SetSoftMaxGfxclkByIndex,
3546 data->smc_state_table.gfx_max_level);
3547 data->dpm_table.gfx_table.dpm_state.soft_max_level =
3548 data->smc_state_table.gfx_max_level;
3552 if (!data->registry_data.mclk_dpm_key_disabled) {
3553 if (data->smc_state_table.mem_max_level !=
3554 data->dpm_table.mem_table.dpm_state.soft_max_level) {
3555 smum_send_msg_to_smc_with_parameter(hwmgr,
3556 PPSMC_MSG_SetSoftMaxUclkByIndex,
3557 data->smc_state_table.mem_max_level);
3558 data->dpm_table.mem_table.dpm_state.soft_max_level =
3559 data->smc_state_table.mem_max_level;
3563 if (!data->registry_data.socclk_dpm_key_disabled) {
3564 if (data->smc_state_table.soc_max_level !=
3565 data->dpm_table.soc_table.dpm_state.soft_max_level) {
3566 smum_send_msg_to_smc_with_parameter(hwmgr,
3567 PPSMC_MSG_SetSoftMaxSocclkByIndex,
3568 data->smc_state_table.soc_max_level);
3569 data->dpm_table.soc_table.dpm_state.soft_max_level =
3570 data->smc_state_table.soc_max_level;
3577 static int vega10_generate_dpm_level_enable_mask(
3578 struct pp_hwmgr *hwmgr, const void *input)
3580 struct vega10_hwmgr *data = hwmgr->backend;
3581 const struct phm_set_power_state_input *states =
3582 (const struct phm_set_power_state_input *)input;
3583 const struct vega10_power_state *vega10_ps =
3584 cast_const_phw_vega10_power_state(states->pnew_state);
3587 PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
3588 "Attempt to Trim DPM States Failed!",
3591 data->smc_state_table.gfx_boot_level =
3592 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3593 data->smc_state_table.gfx_max_level =
3594 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3595 data->smc_state_table.mem_boot_level =
3596 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3597 data->smc_state_table.mem_max_level =
3598 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3599 data->smc_state_table.soc_boot_level =
3600 vega10_find_lowest_dpm_level(&(data->dpm_table.soc_table));
3601 data->smc_state_table.soc_max_level =
3602 vega10_find_highest_dpm_level(&(data->dpm_table.soc_table));
3604 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3605 "Attempt to upload DPM Bootup Levels Failed!",
3607 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3608 "Attempt to upload DPM Max Levels Failed!",
3610 for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++)
3611 data->dpm_table.gfx_table.dpm_levels[i].enabled = true;
3614 for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++)
3615 data->dpm_table.mem_table.dpm_levels[i].enabled = true;
3617 for (i = data->smc_state_table.soc_boot_level; i < data->smc_state_table.soc_max_level; i++)
3618 data->dpm_table.soc_table.dpm_levels[i].enabled = true;
3623 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
3625 struct vega10_hwmgr *data = hwmgr->backend;
3627 if (data->smu_features[GNLD_DPM_VCE].supported) {
3628 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
3630 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
3631 "Attempt to Enable/Disable DPM VCE Failed!",
3633 data->smu_features[GNLD_DPM_VCE].enabled = enable;
3639 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
3641 struct vega10_hwmgr *data = hwmgr->backend;
3642 uint32_t low_sclk_interrupt_threshold = 0;
3644 if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
3645 (data->low_sclk_interrupt_threshold != 0)) {
3646 low_sclk_interrupt_threshold =
3647 data->low_sclk_interrupt_threshold;
3649 data->smc_state_table.pp_table.LowGfxclkInterruptThreshold =
3650 cpu_to_le32(low_sclk_interrupt_threshold);
3652 /* This message will also enable SmcToHost Interrupt */
3653 smum_send_msg_to_smc_with_parameter(hwmgr,
3654 PPSMC_MSG_SetLowGfxclkInterruptThreshold,
3655 (uint32_t)low_sclk_interrupt_threshold);
3661 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
3664 int tmp_result, result = 0;
3665 struct vega10_hwmgr *data = hwmgr->backend;
3666 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
3668 tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
3669 PP_ASSERT_WITH_CODE(!tmp_result,
3670 "Failed to find DPM states clocks in DPM table!",
3671 result = tmp_result);
3673 tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
3674 PP_ASSERT_WITH_CODE(!tmp_result,
3675 "Failed to populate and upload SCLK MCLK DPM levels!",
3676 result = tmp_result);
3678 tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input);
3679 PP_ASSERT_WITH_CODE(!tmp_result,
3680 "Failed to generate DPM level enabled mask!",
3681 result = tmp_result);
3683 tmp_result = vega10_update_sclk_threshold(hwmgr);
3684 PP_ASSERT_WITH_CODE(!tmp_result,
3685 "Failed to update SCLK threshold!",
3686 result = tmp_result);
3688 result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
3689 PP_ASSERT_WITH_CODE(!result,
3690 "Failed to upload PPtable!", return result);
3692 vega10_update_avfs(hwmgr);
3695 * Clear all OD flags except DPMTABLE_OD_UPDATE_VDDC.
3696 * That will help to keep AVFS disabled.
3698 data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
3703 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3705 struct pp_power_state *ps;
3706 struct vega10_power_state *vega10_ps;
3711 ps = hwmgr->request_ps;
3716 vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3719 return vega10_ps->performance_levels[0].gfx_clock;
3721 return vega10_ps->performance_levels
3722 [vega10_ps->performance_level_count - 1].gfx_clock;
3725 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3727 struct pp_power_state *ps;
3728 struct vega10_power_state *vega10_ps;
3733 ps = hwmgr->request_ps;
3738 vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3741 return vega10_ps->performance_levels[0].mem_clock;
3743 return vega10_ps->performance_levels
3744 [vega10_ps->performance_level_count-1].mem_clock;
3747 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
3755 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);
3756 value = smum_get_argument(hwmgr);
3758 /* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */
3759 *query = value << 8;
3764 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3765 void *value, int *size)
3767 struct amdgpu_device *adev = hwmgr->adev;
3768 uint32_t sclk_mhz, mclk_idx, activity_percent = 0;
3769 struct vega10_hwmgr *data = hwmgr->backend;
3770 struct vega10_dpm_table *dpm_table = &data->dpm_table;
3775 case AMDGPU_PP_SENSOR_GFX_SCLK:
3776 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency);
3777 sclk_mhz = smum_get_argument(hwmgr);
3778 *((uint32_t *)value) = sclk_mhz * 100;
3780 case AMDGPU_PP_SENSOR_GFX_MCLK:
3781 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
3782 mclk_idx = smum_get_argument(hwmgr);
3783 if (mclk_idx < dpm_table->mem_table.count) {
3784 *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
3790 case AMDGPU_PP_SENSOR_GPU_LOAD:
3791 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
3792 activity_percent = smum_get_argument(hwmgr);
3793 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3796 case AMDGPU_PP_SENSOR_GPU_TEMP:
3797 *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);
3800 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3801 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHotspot);
3802 *((uint32_t *)value) = smum_get_argument(hwmgr) *
3803 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3806 case AMDGPU_PP_SENSOR_MEM_TEMP:
3807 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHBM);
3808 *((uint32_t *)value) = smum_get_argument(hwmgr) *
3809 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3812 case AMDGPU_PP_SENSOR_UVD_POWER:
3813 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3816 case AMDGPU_PP_SENSOR_VCE_POWER:
3817 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3820 case AMDGPU_PP_SENSOR_GPU_POWER:
3821 ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value);
3823 case AMDGPU_PP_SENSOR_VDDGFX:
3824 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) &
3825 SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >>
3826 SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT;
3827 *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);
3829 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
3830 ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value);
3842 static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
3845 smum_send_msg_to_smc_with_parameter(hwmgr,
3846 PPSMC_MSG_SetUclkFastSwitch,
3850 int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
3851 struct pp_display_clock_request *clock_req)
3854 enum amd_pp_clock_type clk_type = clock_req->clock_type;
3855 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
3856 DSPCLK_e clk_select = 0;
3857 uint32_t clk_request = 0;
3860 case amd_pp_dcef_clock:
3861 clk_select = DSPCLK_DCEFCLK;
3863 case amd_pp_disp_clock:
3864 clk_select = DSPCLK_DISPCLK;
3866 case amd_pp_pixel_clock:
3867 clk_select = DSPCLK_PIXCLK;
3869 case amd_pp_phy_clock:
3870 clk_select = DSPCLK_PHYCLK;
3873 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
3879 clk_request = (clk_freq << 16) | clk_select;
3880 smum_send_msg_to_smc_with_parameter(hwmgr,
3881 PPSMC_MSG_RequestDisplayClockByFreq,
3888 static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr,
3889 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table,
3895 if (mclk_table == NULL || mclk_table->count == 0)
3898 count = (uint8_t)(mclk_table->count);
3900 for(i = 0; i < count; i++) {
3901 if(mclk_table->entries[i].clk >= frequency)
3908 static int vega10_notify_smc_display_config_after_ps_adjustment(
3909 struct pp_hwmgr *hwmgr)
3911 struct vega10_hwmgr *data = hwmgr->backend;
3912 struct vega10_single_dpm_table *dpm_table =
3913 &data->dpm_table.dcef_table;
3914 struct phm_ppt_v2_information *table_info =
3915 (struct phm_ppt_v2_information *)hwmgr->pptable;
3916 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk;
3918 struct PP_Clocks min_clocks = {0};
3920 struct pp_display_clock_request clock_req;
3922 if ((hwmgr->display_config->num_display > 1) &&
3923 !hwmgr->display_config->multi_monitor_in_sync &&
3924 !hwmgr->display_config->nb_pstate_switch_disable)
3925 vega10_notify_smc_display_change(hwmgr, false);
3927 vega10_notify_smc_display_change(hwmgr, true);
3929 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
3930 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
3931 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3933 for (i = 0; i < dpm_table->count; i++) {
3934 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
3938 if (i < dpm_table->count) {
3939 clock_req.clock_type = amd_pp_dcef_clock;
3940 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10;
3941 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
3942 smum_send_msg_to_smc_with_parameter(
3943 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
3944 min_clocks.dcefClockInSR / 100);
3946 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
3949 pr_debug("Cannot find requested DCEFCLK!");
3952 if (min_clocks.memoryClock != 0) {
3953 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
3954 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx);
3955 data->dpm_table.mem_table.dpm_state.soft_min_level= idx;
3961 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)
3963 struct vega10_hwmgr *data = hwmgr->backend;
3965 data->smc_state_table.gfx_boot_level =
3966 data->smc_state_table.gfx_max_level =
3967 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3968 data->smc_state_table.mem_boot_level =
3969 data->smc_state_table.mem_max_level =
3970 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3972 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3973 "Failed to upload boot level to highest!",
3976 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3977 "Failed to upload dpm max level to highest!",
3983 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3985 struct vega10_hwmgr *data = hwmgr->backend;
3987 data->smc_state_table.gfx_boot_level =
3988 data->smc_state_table.gfx_max_level =
3989 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3990 data->smc_state_table.mem_boot_level =
3991 data->smc_state_table.mem_max_level =
3992 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3994 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3995 "Failed to upload boot level to highest!",
3998 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3999 "Failed to upload dpm max level to highest!",
4006 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
4008 struct vega10_hwmgr *data = hwmgr->backend;
4010 data->smc_state_table.gfx_boot_level =
4011 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
4012 data->smc_state_table.gfx_max_level =
4013 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
4014 data->smc_state_table.mem_boot_level =
4015 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
4016 data->smc_state_table.mem_max_level =
4017 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
4019 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4020 "Failed to upload DPM Bootup Levels!",
4023 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4024 "Failed to upload DPM Max Levels!",
4029 static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
4030 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
4032 struct phm_ppt_v2_information *table_info =
4033 (struct phm_ppt_v2_information *)(hwmgr->pptable);
4035 if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL &&
4036 table_info->vdd_dep_on_socclk->count > VEGA10_UMD_PSTATE_SOCCLK_LEVEL &&
4037 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
4038 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
4039 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
4040 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
4041 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
4042 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
4045 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
4047 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
4049 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
4050 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
4051 *soc_mask = table_info->vdd_dep_on_socclk->count - 1;
4052 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1;
4057 static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4060 case AMD_FAN_CTRL_NONE:
4061 vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
4063 case AMD_FAN_CTRL_MANUAL:
4064 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
4065 vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
4067 case AMD_FAN_CTRL_AUTO:
4068 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
4069 vega10_fan_ctrl_start_smc_fan_control(hwmgr);
4076 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
4077 enum pp_clock_type type, uint32_t mask)
4079 struct vega10_hwmgr *data = hwmgr->backend;
4083 data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
4084 data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
4086 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4087 "Failed to upload boot level to lowest!",
4090 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4091 "Failed to upload dpm max level to highest!",
4096 data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;
4097 data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;
4099 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4100 "Failed to upload boot level to lowest!",
4103 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4104 "Failed to upload dpm max level to highest!",
4110 data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0;
4111 data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0;
4113 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4114 "Failed to upload boot level to lowest!",
4117 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4118 "Failed to upload dpm max level to highest!",
4124 pr_info("Setting DCEFCLK min/max dpm level is not supported!\n");
4135 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
4136 enum amd_dpm_forced_level level)
4139 uint32_t sclk_mask = 0;
4140 uint32_t mclk_mask = 0;
4141 uint32_t soc_mask = 0;
4143 if (hwmgr->pstate_sclk == 0)
4144 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4147 case AMD_DPM_FORCED_LEVEL_HIGH:
4148 ret = vega10_force_dpm_highest(hwmgr);
4150 case AMD_DPM_FORCED_LEVEL_LOW:
4151 ret = vega10_force_dpm_lowest(hwmgr);
4153 case AMD_DPM_FORCED_LEVEL_AUTO:
4154 ret = vega10_unforce_dpm_levels(hwmgr);
4156 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
4157 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
4158 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
4159 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
4160 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4163 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
4164 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
4166 case AMD_DPM_FORCED_LEVEL_MANUAL:
4167 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
4173 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4174 vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);
4175 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4176 vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
4182 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4184 struct vega10_hwmgr *data = hwmgr->backend;
4186 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
4187 return AMD_FAN_CTRL_MANUAL;
4189 return AMD_FAN_CTRL_AUTO;
4192 static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr,
4193 struct amd_pp_simple_clock_info *info)
4195 struct phm_ppt_v2_information *table_info =
4196 (struct phm_ppt_v2_information *)hwmgr->pptable;
4197 struct phm_clock_and_voltage_limits *max_limits =
4198 &table_info->max_clock_voltage_on_ac;
4200 info->engine_max_clock = max_limits->sclk;
4201 info->memory_max_clock = max_limits->mclk;
4206 static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
4207 struct pp_clock_levels_with_latency *clocks)
4209 struct phm_ppt_v2_information *table_info =
4210 (struct phm_ppt_v2_information *)hwmgr->pptable;
4211 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4212 table_info->vdd_dep_on_sclk;
4215 clocks->num_levels = 0;
4216 for (i = 0; i < dep_table->count; i++) {
4217 if (dep_table->entries[i].clk) {
4218 clocks->data[clocks->num_levels].clocks_in_khz =
4219 dep_table->entries[i].clk * 10;
4220 clocks->num_levels++;
4226 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
4227 struct pp_clock_levels_with_latency *clocks)
4229 struct phm_ppt_v2_information *table_info =
4230 (struct phm_ppt_v2_information *)hwmgr->pptable;
4231 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4232 table_info->vdd_dep_on_mclk;
4233 struct vega10_hwmgr *data = hwmgr->backend;
4237 for (i = 0; i < dep_table->count; i++) {
4238 if (dep_table->entries[i].clk) {
4240 clocks->data[j].clocks_in_khz =
4241 dep_table->entries[i].clk * 10;
4242 data->mclk_latency_table.entries[j].frequency =
4243 dep_table->entries[i].clk;
4244 clocks->data[j].latency_in_us =
4245 data->mclk_latency_table.entries[j].latency = 25;
4249 clocks->num_levels = data->mclk_latency_table.count = j;
4252 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
4253 struct pp_clock_levels_with_latency *clocks)
4255 struct phm_ppt_v2_information *table_info =
4256 (struct phm_ppt_v2_information *)hwmgr->pptable;
4257 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4258 table_info->vdd_dep_on_dcefclk;
4261 for (i = 0; i < dep_table->count; i++) {
4262 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4263 clocks->data[i].latency_in_us = 0;
4264 clocks->num_levels++;
4268 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
4269 struct pp_clock_levels_with_latency *clocks)
4271 struct phm_ppt_v2_information *table_info =
4272 (struct phm_ppt_v2_information *)hwmgr->pptable;
4273 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4274 table_info->vdd_dep_on_socclk;
4277 for (i = 0; i < dep_table->count; i++) {
4278 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4279 clocks->data[i].latency_in_us = 0;
4280 clocks->num_levels++;
4284 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
4285 enum amd_pp_clock_type type,
4286 struct pp_clock_levels_with_latency *clocks)
4289 case amd_pp_sys_clock:
4290 vega10_get_sclks(hwmgr, clocks);
4292 case amd_pp_mem_clock:
4293 vega10_get_memclocks(hwmgr, clocks);
4295 case amd_pp_dcef_clock:
4296 vega10_get_dcefclocks(hwmgr, clocks);
4298 case amd_pp_soc_clock:
4299 vega10_get_socclocks(hwmgr, clocks);
4308 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
4309 enum amd_pp_clock_type type,
4310 struct pp_clock_levels_with_voltage *clocks)
4312 struct phm_ppt_v2_information *table_info =
4313 (struct phm_ppt_v2_information *)hwmgr->pptable;
4314 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
4318 case amd_pp_mem_clock:
4319 dep_table = table_info->vdd_dep_on_mclk;
4321 case amd_pp_dcef_clock:
4322 dep_table = table_info->vdd_dep_on_dcefclk;
4324 case amd_pp_disp_clock:
4325 dep_table = table_info->vdd_dep_on_dispclk;
4327 case amd_pp_pixel_clock:
4328 dep_table = table_info->vdd_dep_on_pixclk;
4330 case amd_pp_phy_clock:
4331 dep_table = table_info->vdd_dep_on_phyclk;
4337 for (i = 0; i < dep_table->count; i++) {
4338 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4339 clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
4340 entries[dep_table->entries[i].vddInd].us_vdd);
4341 clocks->num_levels++;
4344 if (i < dep_table->count)
4350 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
4353 struct vega10_hwmgr *data = hwmgr->backend;
4354 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
4355 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
4358 if (!data->registry_data.disable_water_mark) {
4359 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
4360 data->water_marks_bitmap = WaterMarksExist;
4366 static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
4368 static const char *ppfeature_name[] = {
4399 static const char *output_title[] = {
4403 uint64_t features_enabled;
4408 ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
4409 PP_ASSERT_WITH_CODE(!ret,
4410 "[EnableAllSmuFeatures] Failed to get enabled smc features!",
4413 size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
4414 size += sprintf(buf + size, "%-19s %-22s %s\n",
4418 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
4419 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
4422 (features_enabled & (1ULL << i)) ? "Y" : "N");
4428 static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
4430 uint64_t features_enabled;
4431 uint64_t features_to_enable;
4432 uint64_t features_to_disable;
4435 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
4438 ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
4442 features_to_disable =
4443 features_enabled & ~new_ppfeature_masks;
4444 features_to_enable =
4445 ~features_enabled & new_ppfeature_masks;
4447 pr_debug("features_to_disable 0x%llx\n", features_to_disable);
4448 pr_debug("features_to_enable 0x%llx\n", features_to_enable);
4450 if (features_to_disable) {
4451 ret = vega10_enable_smc_features(hwmgr, false, features_to_disable);
4456 if (features_to_enable) {
4457 ret = vega10_enable_smc_features(hwmgr, true, features_to_enable);
4465 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
4466 enum pp_clock_type type, char *buf)
4468 struct vega10_hwmgr *data = hwmgr->backend;
4469 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4470 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4471 struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table);
4472 struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table);
4473 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
4474 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
4476 int i, now, size = 0;
4480 if (data->registry_data.sclk_dpm_key_disabled)
4483 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
4484 now = smum_get_argument(hwmgr);
4486 for (i = 0; i < sclk_table->count; i++)
4487 size += sprintf(buf + size, "%d: %uMhz %s\n",
4488 i, sclk_table->dpm_levels[i].value / 100,
4489 (i == now) ? "*" : "");
4492 if (data->registry_data.mclk_dpm_key_disabled)
4495 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
4496 now = smum_get_argument(hwmgr);
4498 for (i = 0; i < mclk_table->count; i++)
4499 size += sprintf(buf + size, "%d: %uMhz %s\n",
4500 i, mclk_table->dpm_levels[i].value / 100,
4501 (i == now) ? "*" : "");
4504 if (data->registry_data.socclk_dpm_key_disabled)
4507 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex);
4508 now = smum_get_argument(hwmgr);
4510 for (i = 0; i < soc_table->count; i++)
4511 size += sprintf(buf + size, "%d: %uMhz %s\n",
4512 i, soc_table->dpm_levels[i].value / 100,
4513 (i == now) ? "*" : "");
4516 if (data->registry_data.dcefclk_dpm_key_disabled)
4519 smum_send_msg_to_smc_with_parameter(hwmgr,
4520 PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK);
4521 now = smum_get_argument(hwmgr);
4523 for (i = 0; i < dcef_table->count; i++)
4524 size += sprintf(buf + size, "%d: %uMhz %s\n",
4525 i, dcef_table->dpm_levels[i].value / 100,
4526 (dcef_table->dpm_levels[i].value / 100 == now) ?
4530 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex);
4531 now = smum_get_argument(hwmgr);
4533 for (i = 0; i < pcie_table->count; i++)
4534 size += sprintf(buf + size, "%d: %s %s\n", i,
4535 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s, x1" :
4536 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s, x16" :
4537 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s, x16" : "",
4538 (i == now) ? "*" : "");
4541 if (hwmgr->od_enabled) {
4542 size = sprintf(buf, "%s:\n", "OD_SCLK");
4543 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4544 for (i = 0; i < podn_vdd_dep->count; i++)
4545 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4546 i, podn_vdd_dep->entries[i].clk / 100,
4547 podn_vdd_dep->entries[i].vddc);
4551 if (hwmgr->od_enabled) {
4552 size = sprintf(buf, "%s:\n", "OD_MCLK");
4553 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4554 for (i = 0; i < podn_vdd_dep->count; i++)
4555 size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4556 i, podn_vdd_dep->entries[i].clk/100,
4557 podn_vdd_dep->entries[i].vddc);
4561 if (hwmgr->od_enabled) {
4562 size = sprintf(buf, "%s:\n", "OD_RANGE");
4563 size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
4564 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100,
4565 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4566 size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
4567 data->golden_dpm_table.mem_table.dpm_levels[0].value/100,
4568 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4569 size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
4570 data->odn_dpm_table.min_vddc,
4571 data->odn_dpm_table.max_vddc);
4580 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4582 struct vega10_hwmgr *data = hwmgr->backend;
4583 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
4586 if ((data->water_marks_bitmap & WaterMarksExist) &&
4587 !(data->water_marks_bitmap & WaterMarksLoaded)) {
4588 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
4589 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
4590 data->water_marks_bitmap |= WaterMarksLoaded;
4593 if (data->water_marks_bitmap & WaterMarksLoaded) {
4594 smum_send_msg_to_smc_with_parameter(hwmgr,
4595 PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);
4601 int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4603 struct vega10_hwmgr *data = hwmgr->backend;
4605 if (data->smu_features[GNLD_DPM_UVD].supported) {
4606 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
4608 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
4609 "Attempt to Enable/Disable DPM UVD Failed!",
4611 data->smu_features[GNLD_DPM_UVD].enabled = enable;
4616 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
4618 struct vega10_hwmgr *data = hwmgr->backend;
4620 data->vce_power_gated = bgate;
4621 vega10_enable_disable_vce_dpm(hwmgr, !bgate);
4624 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
4626 struct vega10_hwmgr *data = hwmgr->backend;
4628 data->uvd_power_gated = bgate;
4629 vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
4632 static inline bool vega10_are_power_levels_equal(
4633 const struct vega10_performance_level *pl1,
4634 const struct vega10_performance_level *pl2)
4636 return ((pl1->soc_clock == pl2->soc_clock) &&
4637 (pl1->gfx_clock == pl2->gfx_clock) &&
4638 (pl1->mem_clock == pl2->mem_clock));
4641 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,
4642 const struct pp_hw_power_state *pstate1,
4643 const struct pp_hw_power_state *pstate2, bool *equal)
4645 const struct vega10_power_state *psa;
4646 const struct vega10_power_state *psb;
4649 if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
4652 psa = cast_const_phw_vega10_power_state(pstate1);
4653 psb = cast_const_phw_vega10_power_state(pstate2);
4654 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
4655 if (psa->performance_level_count != psb->performance_level_count) {
4660 for (i = 0; i < psa->performance_level_count; i++) {
4661 if (!vega10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
4662 /* If we have found even one performance level pair that is different the states are different. */
4668 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
4669 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
4670 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
4671 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
4677 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
4679 struct vega10_hwmgr *data = hwmgr->backend;
4680 bool is_update_required = false;
4682 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
4683 is_update_required = true;
4685 if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) {
4686 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
4687 is_update_required = true;
4690 return is_update_required;
4693 static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
4695 int tmp_result, result = 0;
4697 if (PP_CAP(PHM_PlatformCaps_ThermalController))
4698 vega10_disable_thermal_protection(hwmgr);
4700 tmp_result = vega10_disable_power_containment(hwmgr);
4701 PP_ASSERT_WITH_CODE((tmp_result == 0),
4702 "Failed to disable power containment!", result = tmp_result);
4704 tmp_result = vega10_disable_didt_config(hwmgr);
4705 PP_ASSERT_WITH_CODE((tmp_result == 0),
4706 "Failed to disable didt config!", result = tmp_result);
4708 tmp_result = vega10_avfs_enable(hwmgr, false);
4709 PP_ASSERT_WITH_CODE((tmp_result == 0),
4710 "Failed to disable AVFS!", result = tmp_result);
4712 tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES);
4713 PP_ASSERT_WITH_CODE((tmp_result == 0),
4714 "Failed to stop DPM!", result = tmp_result);
4716 tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr);
4717 PP_ASSERT_WITH_CODE((tmp_result == 0),
4718 "Failed to disable deep sleep!", result = tmp_result);
4720 tmp_result = vega10_disable_ulv(hwmgr);
4721 PP_ASSERT_WITH_CODE((tmp_result == 0),
4722 "Failed to disable ulv!", result = tmp_result);
4724 tmp_result = vega10_acg_disable(hwmgr);
4725 PP_ASSERT_WITH_CODE((tmp_result == 0),
4726 "Failed to disable acg!", result = tmp_result);
4728 vega10_enable_disable_PCC_limit_feature(hwmgr, false);
4732 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
4734 struct vega10_hwmgr *data = hwmgr->backend;
4737 result = vega10_disable_dpm_tasks(hwmgr);
4738 PP_ASSERT_WITH_CODE((0 == result),
4739 "[disable_dpm_tasks] Failed to disable DPM!",
4741 data->water_marks_bitmap &= ~(WaterMarksLoaded);
4746 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
4748 struct vega10_hwmgr *data = hwmgr->backend;
4749 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4750 struct vega10_single_dpm_table *golden_sclk_table =
4751 &(data->golden_dpm_table.gfx_table);
4752 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
4753 int golden_value = golden_sclk_table->dpm_levels
4754 [golden_sclk_table->count - 1].value;
4756 value -= golden_value;
4757 value = DIV_ROUND_UP(value * 100, golden_value);
4762 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4764 struct vega10_hwmgr *data = hwmgr->backend;
4765 struct vega10_single_dpm_table *golden_sclk_table =
4766 &(data->golden_dpm_table.gfx_table);
4767 struct pp_power_state *ps;
4768 struct vega10_power_state *vega10_ps;
4770 ps = hwmgr->request_ps;
4775 vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
4777 vega10_ps->performance_levels
4778 [vega10_ps->performance_level_count - 1].gfx_clock =
4779 golden_sclk_table->dpm_levels
4780 [golden_sclk_table->count - 1].value *
4782 golden_sclk_table->dpm_levels
4783 [golden_sclk_table->count - 1].value;
4785 if (vega10_ps->performance_levels
4786 [vega10_ps->performance_level_count - 1].gfx_clock >
4787 hwmgr->platform_descriptor.overdriveLimit.engineClock) {
4788 vega10_ps->performance_levels
4789 [vega10_ps->performance_level_count - 1].gfx_clock =
4790 hwmgr->platform_descriptor.overdriveLimit.engineClock;
4791 pr_warn("max sclk supported by vbios is %d\n",
4792 hwmgr->platform_descriptor.overdriveLimit.engineClock);
4797 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)
4799 struct vega10_hwmgr *data = hwmgr->backend;
4800 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4801 struct vega10_single_dpm_table *golden_mclk_table =
4802 &(data->golden_dpm_table.mem_table);
4803 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
4804 int golden_value = golden_mclk_table->dpm_levels
4805 [golden_mclk_table->count - 1].value;
4807 value -= golden_value;
4808 value = DIV_ROUND_UP(value * 100, golden_value);
4813 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
4815 struct vega10_hwmgr *data = hwmgr->backend;
4816 struct vega10_single_dpm_table *golden_mclk_table =
4817 &(data->golden_dpm_table.mem_table);
4818 struct pp_power_state *ps;
4819 struct vega10_power_state *vega10_ps;
4821 ps = hwmgr->request_ps;
4826 vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
4828 vega10_ps->performance_levels
4829 [vega10_ps->performance_level_count - 1].mem_clock =
4830 golden_mclk_table->dpm_levels
4831 [golden_mclk_table->count - 1].value *
4833 golden_mclk_table->dpm_levels
4834 [golden_mclk_table->count - 1].value;
4836 if (vega10_ps->performance_levels
4837 [vega10_ps->performance_level_count - 1].mem_clock >
4838 hwmgr->platform_descriptor.overdriveLimit.memoryClock) {
4839 vega10_ps->performance_levels
4840 [vega10_ps->performance_level_count - 1].mem_clock =
4841 hwmgr->platform_descriptor.overdriveLimit.memoryClock;
4842 pr_warn("max mclk supported by vbios is %d\n",
4843 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
4849 static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
4850 uint32_t virtual_addr_low,
4851 uint32_t virtual_addr_hi,
4852 uint32_t mc_addr_low,
4853 uint32_t mc_addr_hi,
4856 smum_send_msg_to_smc_with_parameter(hwmgr,
4857 PPSMC_MSG_SetSystemVirtualDramAddrHigh,
4859 smum_send_msg_to_smc_with_parameter(hwmgr,
4860 PPSMC_MSG_SetSystemVirtualDramAddrLow,
4862 smum_send_msg_to_smc_with_parameter(hwmgr,
4863 PPSMC_MSG_DramLogSetDramAddrHigh,
4866 smum_send_msg_to_smc_with_parameter(hwmgr,
4867 PPSMC_MSG_DramLogSetDramAddrLow,
4870 smum_send_msg_to_smc_with_parameter(hwmgr,
4871 PPSMC_MSG_DramLogSetDramSize,
4876 static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
4877 struct PP_TemperatureRange *thermal_data)
4879 struct vega10_hwmgr *data = hwmgr->backend;
4880 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
4882 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
4884 thermal_data->max = pp_table->TedgeLimit *
4885 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4886 thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
4887 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4888 thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
4889 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4890 thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
4891 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4892 thermal_data->mem_crit_max = pp_table->ThbmLimit *
4893 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4894 thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
4895 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
4900 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
4902 struct vega10_hwmgr *data = hwmgr->backend;
4903 uint32_t i, size = 0;
4904 static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,},
4911 static const char *profile_name[7] = {"BOOTUP_DEFAULT",
4918 static const char *title[6] = {"NUM",
4923 "MIN_ACTIVE_LEVEL"};
4928 size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0],
4929 title[1], title[2], title[3], title[4], title[5]);
4931 for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++)
4932 size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n",
4933 i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
4934 profile_mode_setting[i][0], profile_mode_setting[i][1],
4935 profile_mode_setting[i][2], profile_mode_setting[i][3]);
4936 size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n", i,
4937 profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
4938 data->custom_profile_mode[0], data->custom_profile_mode[1],
4939 data->custom_profile_mode[2], data->custom_profile_mode[3]);
4943 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
4945 struct vega10_hwmgr *data = hwmgr->backend;
4946 uint8_t busy_set_point;
4948 uint8_t use_rlc_busy;
4949 uint8_t min_active_level;
4950 uint32_t power_profile_mode = input[size];
4952 if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
4953 if (size != 0 && size != 4)
4956 /* If size = 0 and the CUSTOM profile has been set already
4957 * then just apply the profile. The copy stored in the hwmgr
4958 * is zeroed out on init
4961 if (data->custom_profile_mode[0] != 0)
4967 data->custom_profile_mode[0] = busy_set_point = input[0];
4968 data->custom_profile_mode[1] = FPS = input[1];
4969 data->custom_profile_mode[2] = use_rlc_busy = input[2];
4970 data->custom_profile_mode[3] = min_active_level = input[3];
4971 smum_send_msg_to_smc_with_parameter(hwmgr,
4972 PPSMC_MSG_SetCustomGfxDpmParameters,
4973 busy_set_point | FPS<<8 |
4974 use_rlc_busy << 16 | min_active_level<<24);
4978 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
4979 1 << power_profile_mode);
4980 hwmgr->power_profile_mode = power_profile_mode;
4986 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
4987 enum PP_OD_DPM_TABLE_COMMAND type,
4991 struct vega10_hwmgr *data = hwmgr->backend;
4992 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
4993 struct vega10_single_dpm_table *golden_table;
4995 if (voltage < odn_table->min_vddc || voltage > odn_table->max_vddc) {
4996 pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc);
5000 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
5001 golden_table = &(data->golden_dpm_table.gfx_table);
5002 if (golden_table->dpm_levels[0].value > clk ||
5003 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
5004 pr_info("OD engine clock is out of range [%d - %d] MHz\n",
5005 golden_table->dpm_levels[0].value/100,
5006 hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
5009 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
5010 golden_table = &(data->golden_dpm_table.mem_table);
5011 if (golden_table->dpm_levels[0].value > clk ||
5012 hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
5013 pr_info("OD memory clock is out of range [%d - %d] MHz\n",
5014 golden_table->dpm_levels[0].value/100,
5015 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
5025 static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
5027 struct vega10_hwmgr *data = hwmgr->backend;
5028 struct pp_power_state *ps = hwmgr->request_ps;
5029 struct vega10_power_state *vega10_ps;
5030 struct vega10_single_dpm_table *gfx_dpm_table =
5031 &data->dpm_table.gfx_table;
5032 struct vega10_single_dpm_table *soc_dpm_table =
5033 &data->dpm_table.soc_table;
5034 struct vega10_single_dpm_table *mem_dpm_table =
5035 &data->dpm_table.mem_table;
5041 vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5042 max_level = vega10_ps->performance_level_count - 1;
5044 if (vega10_ps->performance_levels[max_level].gfx_clock !=
5045 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
5046 vega10_ps->performance_levels[max_level].gfx_clock =
5047 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
5049 if (vega10_ps->performance_levels[max_level].soc_clock !=
5050 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
5051 vega10_ps->performance_levels[max_level].soc_clock =
5052 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
5054 if (vega10_ps->performance_levels[max_level].mem_clock !=
5055 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
5056 vega10_ps->performance_levels[max_level].mem_clock =
5057 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
5062 ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1));
5063 vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5064 max_level = vega10_ps->performance_level_count - 1;
5066 if (vega10_ps->performance_levels[max_level].gfx_clock !=
5067 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
5068 vega10_ps->performance_levels[max_level].gfx_clock =
5069 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
5071 if (vega10_ps->performance_levels[max_level].soc_clock !=
5072 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
5073 vega10_ps->performance_levels[max_level].soc_clock =
5074 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
5076 if (vega10_ps->performance_levels[max_level].mem_clock !=
5077 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
5078 vega10_ps->performance_levels[max_level].mem_clock =
5079 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
5082 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
5083 enum PP_OD_DPM_TABLE_COMMAND type)
5085 struct vega10_hwmgr *data = hwmgr->backend;
5086 struct phm_ppt_v2_information *table_info = hwmgr->pptable;
5087 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = table_info->vdd_dep_on_socclk;
5088 struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table;
5090 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_on_socclk =
5091 &data->odn_dpm_table.vdd_dep_on_socclk;
5092 struct vega10_odn_vddc_lookup_table *od_vddc_lookup_table = &data->odn_dpm_table.vddc_lookup_table;
5094 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep;
5097 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
5098 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
5099 for (i = 0; i < podn_vdd_dep->count - 1; i++)
5100 od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
5101 if (od_vddc_lookup_table->entries[i].us_vdd < podn_vdd_dep->entries[i].vddc)
5102 od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
5103 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
5104 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
5105 for (i = 0; i < dpm_table->count; i++) {
5106 for (j = 0; j < od_vddc_lookup_table->count; j++) {
5107 if (od_vddc_lookup_table->entries[j].us_vdd >
5108 podn_vdd_dep->entries[i].vddc)
5111 if (j == od_vddc_lookup_table->count) {
5112 j = od_vddc_lookup_table->count - 1;
5113 od_vddc_lookup_table->entries[j].us_vdd =
5114 podn_vdd_dep->entries[i].vddc;
5115 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
5117 podn_vdd_dep->entries[i].vddInd = j;
5119 dpm_table = &data->dpm_table.soc_table;
5120 for (i = 0; i < dep_table->count; i++) {
5121 if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[podn_vdd_dep->count-1].vddInd &&
5122 dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count-1].clk) {
5123 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5124 for (; (i < dep_table->count) &&
5125 (dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk); i++) {
5126 podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[podn_vdd_dep->count-1].clk;
5127 dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk;
5131 dpm_table->dpm_levels[i].value = dep_table->entries[i].clk;
5132 podn_vdd_dep_on_socclk->entries[i].vddc = dep_table->entries[i].vddc;
5133 podn_vdd_dep_on_socclk->entries[i].vddInd = dep_table->entries[i].vddInd;
5134 podn_vdd_dep_on_socclk->entries[i].clk = dep_table->entries[i].clk;
5137 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk <
5138 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk) {
5139 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5140 podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk =
5141 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;
5142 dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value =
5143 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;
5145 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd <
5146 podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd) {
5147 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5148 podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd =
5149 podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd;
5152 vega10_odn_update_power_state(hwmgr);
5155 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
5156 enum PP_OD_DPM_TABLE_COMMAND type,
5157 long *input, uint32_t size)
5159 struct vega10_hwmgr *data = hwmgr->backend;
5160 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_table;
5161 struct vega10_single_dpm_table *dpm_table;
5165 uint32_t input_level;
5168 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
5171 if (!hwmgr->od_enabled) {
5172 pr_info("OverDrive feature not enabled\n");
5176 if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
5177 dpm_table = &data->dpm_table.gfx_table;
5178 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_sclk;
5179 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
5180 } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
5181 dpm_table = &data->dpm_table.mem_table;
5182 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk;
5183 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
5184 } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
5185 memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table));
5186 vega10_odn_initial_default_setting(hwmgr);
5187 vega10_odn_update_power_state(hwmgr);
5188 /* force to update all clock tables */
5189 data->need_update_dpm_table = DPMTABLE_UPDATE_SCLK |
5190 DPMTABLE_UPDATE_MCLK |
5191 DPMTABLE_UPDATE_SOCCLK;
5193 } else if (PP_OD_COMMIT_DPM_TABLE == type) {
5194 vega10_check_dpm_table_updated(hwmgr);
5200 for (i = 0; i < size; i += 3) {
5201 if (i + 3 > size || input[i] >= podn_vdd_dep_table->count) {
5202 pr_info("invalid clock voltage input\n");
5205 input_level = input[i];
5206 input_clk = input[i+1] * 100;
5207 input_vol = input[i+2];
5209 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
5210 dpm_table->dpm_levels[input_level].value = input_clk;
5211 podn_vdd_dep_table->entries[input_level].clk = input_clk;
5212 podn_vdd_dep_table->entries[input_level].vddc = input_vol;
5217 vega10_odn_update_soc_table(hwmgr, type);
5221 static int vega10_set_mp1_state(struct pp_hwmgr *hwmgr,
5222 enum pp_mp1_state mp1_state)
5227 switch (mp1_state) {
5228 case PP_MP1_STATE_UNLOAD:
5229 msg = PPSMC_MSG_PrepareMp1ForUnload;
5231 case PP_MP1_STATE_SHUTDOWN:
5232 case PP_MP1_STATE_RESET:
5233 case PP_MP1_STATE_NONE:
5238 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg)) == 0,
5239 "[PrepareMp1] Failed!",
5245 static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
5246 PHM_PerformanceLevelDesignation designation, uint32_t index,
5247 PHM_PerformanceLevel *level)
5249 const struct vega10_power_state *ps;
5250 struct vega10_hwmgr *data;
5253 if (level == NULL || hwmgr == NULL || state == NULL)
5256 data = hwmgr->backend;
5257 ps = cast_const_phw_vega10_power_state(state);
5259 i = index > ps->performance_level_count - 1 ?
5260 ps->performance_level_count - 1 : index;
5262 level->coreClock = ps->performance_levels[i].gfx_clock;
5263 level->memory_clock = ps->performance_levels[i].mem_clock;
5268 static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
5269 .backend_init = vega10_hwmgr_backend_init,
5270 .backend_fini = vega10_hwmgr_backend_fini,
5271 .asic_setup = vega10_setup_asic_task,
5272 .dynamic_state_management_enable = vega10_enable_dpm_tasks,
5273 .dynamic_state_management_disable = vega10_disable_dpm_tasks,
5274 .get_num_of_pp_table_entries =
5275 vega10_get_number_of_powerplay_table_entries,
5276 .get_power_state_size = vega10_get_power_state_size,
5277 .get_pp_table_entry = vega10_get_pp_table_entry,
5278 .patch_boot_state = vega10_patch_boot_state,
5279 .apply_state_adjust_rules = vega10_apply_state_adjust_rules,
5280 .power_state_set = vega10_set_power_state_tasks,
5281 .get_sclk = vega10_dpm_get_sclk,
5282 .get_mclk = vega10_dpm_get_mclk,
5283 .notify_smc_display_config_after_ps_adjustment =
5284 vega10_notify_smc_display_config_after_ps_adjustment,
5285 .force_dpm_level = vega10_dpm_force_dpm_level,
5286 .stop_thermal_controller = vega10_thermal_stop_thermal_controller,
5287 .get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info,
5288 .get_fan_speed_percent = vega10_fan_ctrl_get_fan_speed_percent,
5289 .set_fan_speed_percent = vega10_fan_ctrl_set_fan_speed_percent,
5290 .reset_fan_speed_to_default =
5291 vega10_fan_ctrl_reset_fan_speed_to_default,
5292 .get_fan_speed_rpm = vega10_fan_ctrl_get_fan_speed_rpm,
5293 .set_fan_speed_rpm = vega10_fan_ctrl_set_fan_speed_rpm,
5294 .uninitialize_thermal_controller =
5295 vega10_thermal_ctrl_uninitialize_thermal_controller,
5296 .set_fan_control_mode = vega10_set_fan_control_mode,
5297 .get_fan_control_mode = vega10_get_fan_control_mode,
5298 .read_sensor = vega10_read_sensor,
5299 .get_dal_power_level = vega10_get_dal_power_level,
5300 .get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency,
5301 .get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage,
5302 .set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges,
5303 .display_clock_voltage_request = vega10_display_clock_voltage_request,
5304 .force_clock_level = vega10_force_clock_level,
5305 .print_clock_levels = vega10_print_clock_levels,
5306 .display_config_changed = vega10_display_configuration_changed_task,
5307 .powergate_uvd = vega10_power_gate_uvd,
5308 .powergate_vce = vega10_power_gate_vce,
5309 .check_states_equal = vega10_check_states_equal,
5310 .check_smc_update_required_for_display_configuration =
5311 vega10_check_smc_update_required_for_display_configuration,
5312 .power_off_asic = vega10_power_off_asic,
5313 .disable_smc_firmware_ctf = vega10_thermal_disable_alert,
5314 .get_sclk_od = vega10_get_sclk_od,
5315 .set_sclk_od = vega10_set_sclk_od,
5316 .get_mclk_od = vega10_get_mclk_od,
5317 .set_mclk_od = vega10_set_mclk_od,
5318 .avfs_control = vega10_avfs_enable,
5319 .notify_cac_buffer_info = vega10_notify_cac_buffer_info,
5320 .get_thermal_temperature_range = vega10_get_thermal_temperature_range,
5321 .register_irq_handlers = smu9_register_irq_handlers,
5322 .start_thermal_controller = vega10_start_thermal_controller,
5323 .get_power_profile_mode = vega10_get_power_profile_mode,
5324 .set_power_profile_mode = vega10_set_power_profile_mode,
5325 .set_power_limit = vega10_set_power_limit,
5326 .odn_edit_dpm_table = vega10_odn_edit_dpm_table,
5327 .get_performance_level = vega10_get_performance_level,
5328 .get_asic_baco_capability = smu9_baco_get_capability,
5329 .get_asic_baco_state = smu9_baco_get_state,
5330 .set_asic_baco_state = vega10_baco_set_state,
5331 .enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost,
5332 .get_ppfeature_status = vega10_get_ppfeature_status,
5333 .set_ppfeature_status = vega10_set_ppfeature_status,
5334 .set_mp1_state = vega10_set_mp1_state,
5337 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
5339 struct amdgpu_device *adev = hwmgr->adev;
5341 hwmgr->hwmgr_func = &vega10_hwmgr_funcs;
5342 hwmgr->pptable_func = &vega10_pptable_funcs;
5343 if (amdgpu_passthrough(adev))
5344 return vega10_baco_set_cap(hwmgr);