drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Dave Airlie
  30  */
  31 #include <linux/seq_file.h>
  32 #include <linux/atomic.h>
  33 #include <linux/wait.h>
  34 #include <linux/kref.h>
  35 #include <linux/slab.h>
  36 #include <linux/firmware.h>
  37 #include <drm/drmP.h>
  38 #include "amdgpu.h"
  39 #include "amdgpu_trace.h"
  40
  41 /*
  42  * Fences
  43  * Fences mark an event in the GPUs pipeline and are used
  44  * for GPU/CPU synchronization.  When the fence is written,
  45  * it is expected that all buffers associated with that fence
  46  * are no longer in use by the associated ring on the GPU and
  47  * that the the relevant GPU caches have been flushed.
  48  */
  49
  50 struct amdgpu_fence {
  51         struct fence base;
  52
  53         /* RB, DMA, etc. */
  54         struct amdgpu_ring              *ring;
  55 };
  56
  57 static struct kmem_cache *amdgpu_fence_slab;
  58 static atomic_t amdgpu_fence_slab_ref = ATOMIC_INIT(0);
  59
  60 /*
  61  * Cast helper
  62  */
  63 static const struct fence_ops amdgpu_fence_ops;
  64 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
  65 {
  66         struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
  67
  68         if (__f->base.ops == &amdgpu_fence_ops)
  69                 return __f;
  70
  71         return NULL;
  72 }
  73
  74 /**
  75  * amdgpu_fence_write - write a fence value
  76  *
  77  * @ring: ring the fence is associated with
  78  * @seq: sequence number to write
  79  *
  80  * Writes a fence value to memory (all asics).
  81  */
  82 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
  83 {
  84         struct amdgpu_fence_driver *drv = &ring->fence_drv;
  85
  86         if (drv->cpu_addr)
  87                 *drv->cpu_addr = cpu_to_le32(seq);
  88 }
  89
  90 /**
  91  * amdgpu_fence_read - read a fence value
  92  *
  93  * @ring: ring the fence is associated with
  94  *
  95  * Reads a fence value from memory (all asics).
  96  * Returns the value of the fence read from memory.
  97  */
  98 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
  99 {
 100         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 101         u32 seq = 0;
 102
 103         if (drv->cpu_addr)
 104                 seq = le32_to_cpu(*drv->cpu_addr);
 105         else
 106                 seq = atomic_read(&drv->last_seq);
 107
 108         return seq;
 109 }
 110
 111 /**
 112  * amdgpu_fence_emit - emit a fence on the requested ring
 113  *
 114  * @ring: ring the fence is associated with
 115  * @f: resulting fence object
 116  *
 117  * Emits a fence command on the requested ring (all asics).
 118  * Returns 0 on success, -ENOMEM on failure.
 119  */
 120 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
 121 {
 122         struct amdgpu_device *adev = ring->adev;
 123         struct amdgpu_fence *fence;
 124         struct fence **ptr;
 125         uint32_t seq;
 126
 127         fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
 128         if (fence == NULL)
 129                 return -ENOMEM;
 130
 131         seq = ++ring->fence_drv.sync_seq;
 132         fence->ring = ring;
 133         fence_init(&fence->base, &amdgpu_fence_ops,
 134                    &ring->fence_drv.lock,
 135                    adev->fence_context + ring->idx,
 136                    seq);
 137         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 138                                seq, AMDGPU_FENCE_FLAG_INT);
 139
 140         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 141         /* This function can't be called concurrently anyway, otherwise
 142          * emitting the fence would mess up the hardware ring buffer.
 143          */
 144         BUG_ON(rcu_dereference_protected(*ptr, 1));
 145
 146         rcu_assign_pointer(*ptr, fence_get(&fence->base));
 147
 148         *f = &fence->base;
 149
 150         return 0;
 151 }
 152
 153 /**
 154  * amdgpu_fence_schedule_fallback - schedule fallback check
 155  *
 156  * @ring: pointer to struct amdgpu_ring
 157  *
 158  * Start a timer as fallback to our interrupts.
 159  */
 160 static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
 161 {
 162         mod_timer(&ring->fence_drv.fallback_timer,
 163                   jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
 164 }
 165
 166 /**
 167  * amdgpu_fence_process - check for fence activity
 168  *
 169  * @ring: pointer to struct amdgpu_ring
 170  *
 171  * Checks the current fence value and calculates the last
 172  * signalled fence value. Wakes the fence queue if the
 173  * sequence number has increased.
 174  */
 175 void amdgpu_fence_process(struct amdgpu_ring *ring)
 176 {
 177         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 178         uint32_t seq, last_seq;
 179         int r;
 180
 181         do {
 182                 last_seq = atomic_read(&ring->fence_drv.last_seq);
 183                 seq = amdgpu_fence_read(ring);
 184
 185         } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
 186
 187         if (seq != ring->fence_drv.sync_seq)
 188                 amdgpu_fence_schedule_fallback(ring);
 189
 190         while (last_seq != seq) {
 191                 struct fence *fence, **ptr;
 192
 193                 ptr = &drv->fences[++last_seq & drv->num_fences_mask];
 194
 195                 /* There is always exactly one thread signaling this fence slot */
 196                 fence = rcu_dereference_protected(*ptr, 1);
 197                 rcu_assign_pointer(*ptr, NULL);
 198
 199                 BUG_ON(!fence);
 200
 201                 r = fence_signal(fence);
 202                 if (!r)
 203                         FENCE_TRACE(fence, "signaled from irq context\n");
 204                 else
 205                         BUG();
 206
 207                 fence_put(fence);
 208         }
 209 }
 210
 211 /**
 212  * amdgpu_fence_fallback - fallback for hardware interrupts
 213  *
 214  * @work: delayed work item
 215  *
 216  * Checks for fence activity.
 217  */
 218 static void amdgpu_fence_fallback(unsigned long arg)
 219 {
 220         struct amdgpu_ring *ring = (void *)arg;
 221
 222         amdgpu_fence_process(ring);
 223 }
 224
 225 /**
 226  * amdgpu_fence_wait_empty - wait for all fences to signal
 227  *
 228  * @adev: amdgpu device pointer
 229  * @ring: ring index the fence is associated with
 230  *
 231  * Wait for all fences on the requested ring to signal (all asics).
 232  * Returns 0 if the fences have passed, error for all other cases.
 233  */
 234 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
 235 {
 236         uint64_t seq = ACCESS_ONCE(ring->fence_drv.sync_seq);
 237         struct fence *fence, **ptr;
 238         int r;
 239
 240         if (!seq)
 241                 return 0;
 242
 243         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 244         rcu_read_lock();
 245         fence = rcu_dereference(*ptr);
 246         if (!fence || !fence_get_rcu(fence)) {
 247                 rcu_read_unlock();
 248                 return 0;
 249         }
 250         rcu_read_unlock();
 251
 252         r = fence_wait(fence, false);
 253         fence_put(fence);
 254         return r;
 255 }
 256
 257 /**
 258  * amdgpu_fence_count_emitted - get the count of emitted fences
 259  *
 260  * @ring: ring the fence is associated with
 261  *
 262  * Get the number of fences emitted on the requested ring (all asics).
 263  * Returns the number of emitted fences on the ring.  Used by the
 264  * dynpm code to ring track activity.
 265  */
 266 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
 267 {
 268         uint64_t emitted;
 269
 270         /* We are not protected by ring lock when reading the last sequence
 271          * but it's ok to report slightly wrong fence count here.
 272          */
 273         amdgpu_fence_process(ring);
 274         emitted = 0x100000000ull;
 275         emitted -= atomic_read(&ring->fence_drv.last_seq);
 276         emitted += ACCESS_ONCE(ring->fence_drv.sync_seq);
 277         return lower_32_bits(emitted);
 278 }
 279
 280 /**
 281  * amdgpu_fence_driver_start_ring - make the fence driver
 282  * ready for use on the requested ring.
 283  *
 284  * @ring: ring to start the fence driver on
 285  * @irq_src: interrupt source to use for this ring
 286  * @irq_type: interrupt type to use for this ring
 287  *
 288  * Make the fence driver ready for processing (all asics).
 289  * Not all asics have all rings, so each asic will only
 290  * start the fence driver on the rings it has.
 291  * Returns 0 for success, errors for failure.
 292  */
 293 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
 294                                    struct amdgpu_irq_src *irq_src,
 295                                    unsigned irq_type)
 296 {
 297         struct amdgpu_device *adev = ring->adev;
 298         uint64_t index;
 299
 300         if (ring != &adev->uvd.ring) {
 301                 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
 302                 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
 303         } else {
 304                 /* put fence directly behind firmware */
 305                 index = ALIGN(adev->uvd.fw->size, 8);
 306                 ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index;
 307                 ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index;
 308         }
 309         amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
 310         amdgpu_irq_get(adev, irq_src, irq_type);
 311
 312         ring->fence_drv.irq_src = irq_src;
 313         ring->fence_drv.irq_type = irq_type;
 314         ring->fence_drv.initialized = true;
 315
 316         dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
 317                  "cpu addr 0x%p\n", ring->idx,
 318                  ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
 319         return 0;
 320 }
 321
 322 /**
 323  * amdgpu_fence_driver_init_ring - init the fence driver
 324  * for the requested ring.
 325  *
 326  * @ring: ring to init the fence driver on
 327  * @num_hw_submission: number of entries on the hardware queue
 328  *
 329  * Init the fence driver for the requested ring (all asics).
 330  * Helper function for amdgpu_fence_driver_init().
 331  */
 332 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
 333                                   unsigned num_hw_submission)
 334 {
 335         long timeout;
 336         int r;
 337
 338         /* Check that num_hw_submission is a power of two */
 339         if ((num_hw_submission & (num_hw_submission - 1)) != 0)
 340                 return -EINVAL;
 341
 342         ring->fence_drv.cpu_addr = NULL;
 343         ring->fence_drv.gpu_addr = 0;
 344         ring->fence_drv.sync_seq = 0;
 345         atomic_set(&ring->fence_drv.last_seq, 0);
 346         ring->fence_drv.initialized = false;
 347
 348         setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback,
 349                     (unsigned long)ring);
 350
 351         ring->fence_drv.num_fences_mask = num_hw_submission - 1;
 352         spin_lock_init(&ring->fence_drv.lock);
 353         ring->fence_drv.fences = kcalloc(num_hw_submission, sizeof(void *),
 354                                          GFP_KERNEL);
 355         if (!ring->fence_drv.fences)
 356                 return -ENOMEM;
 357
 358         timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
 359         if (timeout == 0) {
 360                 /*
 361                  * FIXME:
 362                  * Delayed workqueue cannot use it directly,
 363                  * so the scheduler will not use delayed workqueue if
 364                  * MAX_SCHEDULE_TIMEOUT is set.
 365                  * Currently keep it simple and silly.
 366                  */
 367                 timeout = MAX_SCHEDULE_TIMEOUT;
 368         }
 369         r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
 370                            num_hw_submission,
 371                            timeout, ring->name);
 372         if (r) {
 373                 DRM_ERROR("Failed to create scheduler on ring %s.\n",
 374                           ring->name);
 375                 return r;
 376         }
 377
 378         return 0;
 379 }
 380
 381 /**
 382  * amdgpu_fence_driver_init - init the fence driver
 383  * for all possible rings.
 384  *
 385  * @adev: amdgpu device pointer
 386  *
 387  * Init the fence driver for all possible rings (all asics).
 388  * Not all asics have all rings, so each asic will only
 389  * start the fence driver on the rings it has using
 390  * amdgpu_fence_driver_start_ring().
 391  * Returns 0 for success.
 392  */
 393 int amdgpu_fence_driver_init(struct amdgpu_device *adev)
 394 {
 395         if (atomic_inc_return(&amdgpu_fence_slab_ref) == 1) {
 396                 amdgpu_fence_slab = kmem_cache_create(
 397                         "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
 398                         SLAB_HWCACHE_ALIGN, NULL);
 399                 if (!amdgpu_fence_slab)
 400                         return -ENOMEM;
 401         }
 402         if (amdgpu_debugfs_fence_init(adev))
 403                 dev_err(adev->dev, "fence debugfs file creation failed\n");
 404
 405         return 0;
 406 }
 407
 408 /**
 409  * amdgpu_fence_driver_fini - tear down the fence driver
 410  * for all possible rings.
 411  *
 412  * @adev: amdgpu device pointer
 413  *
 414  * Tear down the fence driver for all possible rings (all asics).
 415  */
 416 void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
 417 {
 418         unsigned i, j;
 419         int r;
 420
 421         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 422                 struct amdgpu_ring *ring = adev->rings[i];
 423
 424                 if (!ring || !ring->fence_drv.initialized)
 425                         continue;
 426                 r = amdgpu_fence_wait_empty(ring);
 427                 if (r) {
 428                         /* no need to trigger GPU reset as we are unloading */
 429                         amdgpu_fence_driver_force_completion(adev);
 430                 }
 431                 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 432                                ring->fence_drv.irq_type);
 433                 amd_sched_fini(&ring->sched);
 434                 del_timer_sync(&ring->fence_drv.fallback_timer);
 435                 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
 436                         fence_put(ring->fence_drv.fences[i]);
 437                 kfree(ring->fence_drv.fences);
 438                 ring->fence_drv.initialized = false;
 439         }
 440
 441         if (atomic_dec_and_test(&amdgpu_fence_slab_ref))
 442                 kmem_cache_destroy(amdgpu_fence_slab);
 443 }
 444
 445 /**
 446  * amdgpu_fence_driver_suspend - suspend the fence driver
 447  * for all possible rings.
 448  *
 449  * @adev: amdgpu device pointer
 450  *
 451  * Suspend the fence driver for all possible rings (all asics).
 452  */
 453 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
 454 {
 455         int i, r;
 456
 457         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 458                 struct amdgpu_ring *ring = adev->rings[i];
 459                 if (!ring || !ring->fence_drv.initialized)
 460                         continue;
 461
 462                 /* wait for gpu to finish processing current batch */
 463                 r = amdgpu_fence_wait_empty(ring);
 464                 if (r) {
 465                         /* delay GPU reset to resume */
 466                         amdgpu_fence_driver_force_completion(adev);
 467                 }
 468
 469                 /* disable the interrupt */
 470                 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 471                                ring->fence_drv.irq_type);
 472         }
 473 }
 474
 475 /**
 476  * amdgpu_fence_driver_resume - resume the fence driver
 477  * for all possible rings.
 478  *
 479  * @adev: amdgpu device pointer
 480  *
 481  * Resume the fence driver for all possible rings (all asics).
 482  * Not all asics have all rings, so each asic will only
 483  * start the fence driver on the rings it has using
 484  * amdgpu_fence_driver_start_ring().
 485  * Returns 0 for success.
 486  */
 487 void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
 488 {
 489         int i;
 490
 491         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 492                 struct amdgpu_ring *ring = adev->rings[i];
 493                 if (!ring || !ring->fence_drv.initialized)
 494                         continue;
 495
 496                 /* enable the interrupt */
 497                 amdgpu_irq_get(adev, ring->fence_drv.irq_src,
 498                                ring->fence_drv.irq_type);
 499         }
 500 }
 501
 502 /**
 503  * amdgpu_fence_driver_force_completion - force all fence waiter to complete
 504  *
 505  * @adev: amdgpu device pointer
 506  *
 507  * In case of GPU reset failure make sure no process keep waiting on fence
 508  * that will never complete.
 509  */
 510 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
 511 {
 512         int i;
 513
 514         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 515                 struct amdgpu_ring *ring = adev->rings[i];
 516                 if (!ring || !ring->fence_drv.initialized)
 517                         continue;
 518
 519                 amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
 520         }
 521 }
 522
 523 /*
 524  * Common fence implementation
 525  */
 526
 527 static const char *amdgpu_fence_get_driver_name(struct fence *fence)
 528 {
 529         return "amdgpu";
 530 }
 531
 532 static const char *amdgpu_fence_get_timeline_name(struct fence *f)
 533 {
 534         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 535         return (const char *)fence->ring->name;
 536 }
 537
 538 /**
 539  * amdgpu_fence_enable_signaling - enable signalling on fence
 540  * @fence: fence
 541  *
 542  * This function is called with fence_queue lock held, and adds a callback
 543  * to fence_queue that checks if this fence is signaled, and if so it
 544  * signals the fence and removes itself.
 545  */
 546 static bool amdgpu_fence_enable_signaling(struct fence *f)
 547 {
 548         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 549         struct amdgpu_ring *ring = fence->ring;
 550
 551         if (!timer_pending(&ring->fence_drv.fallback_timer))
 552                 amdgpu_fence_schedule_fallback(ring);
 553
 554         FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
 555
 556         return true;
 557 }
 558
 559 /**
 560  * amdgpu_fence_free - free up the fence memory
 561  *
 562  * @rcu: RCU callback head
 563  *
 564  * Free up the fence memory after the RCU grace period.
 565  */
 566 static void amdgpu_fence_free(struct rcu_head *rcu)
 567 {
 568         struct fence *f = container_of(rcu, struct fence, rcu);
 569         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 570         kmem_cache_free(amdgpu_fence_slab, fence);
 571 }
 572
 573 /**
 574  * amdgpu_fence_release - callback that fence can be freed
 575  *
 576  * @fence: fence
 577  *
 578  * This function is called when the reference count becomes zero.
 579  * It just RCU schedules freeing up the fence.
 580  */
 581 static void amdgpu_fence_release(struct fence *f)
 582 {
 583         call_rcu(&f->rcu, amdgpu_fence_free);
 584 }
 585
 586 static const struct fence_ops amdgpu_fence_ops = {
 587         .get_driver_name = amdgpu_fence_get_driver_name,
 588         .get_timeline_name = amdgpu_fence_get_timeline_name,
 589         .enable_signaling = amdgpu_fence_enable_signaling,
 590         .wait = fence_default_wait,
 591         .release = amdgpu_fence_release,
 592 };
 593
 594 /*
 595  * Fence debugfs
 596  */
 597 #if defined(CONFIG_DEBUG_FS)
 598 static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
 599 {
 600         struct drm_info_node *node = (struct drm_info_node *)m->private;
 601         struct drm_device *dev = node->minor->dev;
 602         struct amdgpu_device *adev = dev->dev_private;
 603         int i;
 604
 605         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 606                 struct amdgpu_ring *ring = adev->rings[i];
 607                 if (!ring || !ring->fence_drv.initialized)
 608                         continue;
 609
 610                 amdgpu_fence_process(ring);
 611
 612                 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
 613                 seq_printf(m, "Last signaled fence 0x%08x\n",
 614                            atomic_read(&ring->fence_drv.last_seq));
 615                 seq_printf(m, "Last emitted        0x%08x\n",
 616                            ring->fence_drv.sync_seq);
 617         }
 618         return 0;
 619 }
 620
 621 /**
 622  * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset
 623  *
 624  * Manually trigger a gpu reset at the next fence wait.
 625  */
 626 static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data)
 627 {
 628         struct drm_info_node *node = (struct drm_info_node *) m->private;
 629         struct drm_device *dev = node->minor->dev;
 630         struct amdgpu_device *adev = dev->dev_private;
 631
 632         seq_printf(m, "gpu reset\n");
 633         amdgpu_gpu_reset(adev);
 634
 635         return 0;
 636 }
 637
 638 static struct drm_info_list amdgpu_debugfs_fence_list[] = {
 639         {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
 640         {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL}
 641 };
 642 #endif
 643
 644 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
 645 {
 646 #if defined(CONFIG_DEBUG_FS)
 647         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2);
 648 #else
 649         return 0;
 650 #endif
 651 }
 652